commit d212040c30bfaaafb0c07f71f30d9b7cf1042a20 Author: github-classroom[bot] <66690702+github-classroom[bot]@users.noreply.github.com> Date: Fri Feb 23 13:01:05 2024 +0000 Initial commit diff --git a/01-WaveformGenerator/Prefs/dp_user/v2_72/dp_user_prefs b/01-WaveformGenerator/Prefs/dp_user/v2_72/dp_user_prefs new file mode 100644 index 0000000..6a67047 --- /dev/null +++ b/01-WaveformGenerator/Prefs/dp_user/v2_72/dp_user_prefs @@ -0,0 +1,64 @@ +[LexParser.LexVHDL2008] +[LexParser] +[Editor] +recentFile0=/usr/opt/HDS/hdl_libs/ieee/hdl/std_logic_1164.vhdl +lastFilter=.vhdl +mark.lineImage=blueball +[Printer] +ENSCRIPT_LIBRARY=/usr/opt/HDS/resources/enscript/share/enscript +[ToolbarFrames] +geom0Group1=top H +geom0Group2=top H +geom0Group3=top H +state0Search=1 +Num=0 +state0VersionManagement=1 +state0Tasks=1 +state0View=1 +state0Standard=1 +state0Edit=1 +Group1=Standard Search +Group2=Edit Bookmarks View Macros DocumentTools Windows +Group3=VersionManagement Tasks +state0Macros=1 +state0Bookmarks=1 +state0Windows=1 +state0DocumentTools=1 +[LexParser.LexPSL] +[DND] +TrackerBg=#c3c3c3 +signalAcceptDropBg=white +signalRefuseDropBg=red +[General] +[Browser] +normalTextBg=white +normalTextFg=black +[Replace] +historyMax=4 +atomicReplaceAll=No +[Console] +[Templates] +Visibility=No +[SearchInFiles] +SearchAsRegExp=0 +MatchCase=0 +LookInSubfolders=0 +historyMax=4 +[VDiff] +[R72] +indentType=spaces +indentString=\#\#\# +[TCOM] +logTCOMActivity=No +afterIdleHandlerTimeSlice=300 +[Menus] +DocAndVis= +[Help] +default=te_guide +[Plugins] +userLanguages= +[Search] +historyMax=4 +[Geometry] +TopWindow0=1286x981+317+1103 +FrameSupp0,0=165 diff --git a/01-WaveformGenerator/Prefs/hds.hdp b/01-WaveformGenerator/Prefs/hds.hdp new file mode 100644 index 0000000..b986ef0 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds.hdp @@ -0,0 +1,19 @@ +[Concat] +[ModelSim] +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hdl +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hds +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/01-WaveformGenerator/Prefs/hds_team/shared.hdp b/01-WaveformGenerator/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs b/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl b/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs b/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl b/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs b/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl b/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg 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"$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair 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"Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pcf" +Description "Xilinx Place and Route Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ucf" +Description "Xilinx User Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncd" +Description "Xilinx Floorplanner File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncd.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bld" +Description "Xilinx NGDBuild Log" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bit" +Description "Xilinx Bit File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "bin" +Description "Xilinx Binary Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbt" +Description "Xilinx ASCII Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "jed" +Description "Xilinx Jedec Bit Map File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ngc" +Description "Xilinx Netlist File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\synthesis.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "npl" +Description "Xilinx ISE Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xilinx_projnav.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psp" +Description "Precision Synthesis Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\precision.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qpf" +Description "Quartus Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\altera_quartus.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qsf" +Description "Quartus Settings and Assigments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "qws" +Description "Quartus Workspace" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "args" +Description "Quartus Arguments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rpt" +Description "Quartus Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "summary" +Description "Quartus Summary File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "eqn" +Description "Quartus Equation File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pin" +Description "Quartus Pin Information File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "vqm" +Description "Quartus Verilog Mapping File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\vqm.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdo" +Description "Standard Delay File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xrf" +Description "Cross Reference File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "pof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbf" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ttf" +Description "Quartus Text Tabular Format Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pdf" +Description "Adobe Acrobat Pdf" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pdf.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "doc" +Description "Microsoft Word Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\word.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "xls" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "tsv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "csv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ppt" +Description "Microsoft PowerPoint Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\powerpoint.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "vsd" +Description "Microsoft Visio Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\visio.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "htm" +Description "HTM File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\web.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "html" +Description "HTML File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\web.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psl" +Description "Property Specification Language File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\psl.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "View" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xlsm" +Description "Excel macro-enabled spreadsheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rcf" +Description "RA control file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\RaCtrlFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "View" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "js" +Description "Javascript" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jsFile.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "xml" +Description "xml file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ipxact" +Description "IP-XACT file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "css" +Description "HTML style sheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cssFile.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "gif" +Description "GIF image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\gifFile.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "png" +Description "PNG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pngFile.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "jpg" +Description "JPG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jpgFile.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "svap" +Description "SVAssistant project file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\svapFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "Open" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +(ActionState +Name "View" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +] +) +] +) +(DMPreferences +version "1.1" +) +(AsmPreferences +version "1.1" +defaultSaveName "asm" +packageListLabelVaSet (VaSet +font "courier,8,1" +) +packageListFontVaSet (VaSet +font "courier,8,0" +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +font "courier,8,0" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" 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b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7348b0e --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/waveformGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/hds_user_prefs b/01-WaveformGenerator/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" 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ISE Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xilinx_projnav.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psp" +Description "Precision Synthesis Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\precision.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qpf" +Description "Quartus Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\altera_quartus.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qsf" +Description "Quartus Settings and Assigments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "qws" +Description "Quartus Workspace" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState 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+"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs b/01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..4cd7572 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6841 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments 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"Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7348b0e --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/waveformGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/01-WaveformGenerator/Scripts/cleanGenerated.bash b/01-WaveformGenerator/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/01-WaveformGenerator/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/01-WaveformGenerator/Scripts/cleanGenerated.bat b/01-WaveformGenerator/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/01-WaveformGenerator/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/01-WaveformGenerator/Scripts/cleanScratch.bat b/01-WaveformGenerator/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/01-WaveformGenerator/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/01-WaveformGenerator/Scripts/generateSSHKey.bash b/01-WaveformGenerator/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/01-WaveformGenerator/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/01-WaveformGenerator/Scripts/hdlDesigner.bash b/01-WaveformGenerator/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/01-WaveformGenerator/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/01-WaveformGenerator/Scripts/hdlDesigner.bat b/01-WaveformGenerator/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..2a612a6 --- /dev/null +++ b/01-WaveformGenerator/Scripts/hdlDesigner.bat @@ -0,0 +1,301 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +if %REQUIRE_ICECUBE2% == 1 ( + set synthesis_subdirectory="Board\icecube2" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + if %REQUIRE_ICECUBE2% == 1 ( + echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=% + echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=% + echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +if %REQUIRE_ICECUBE2% == 1 ( + if exist %ICECUBE2_BASE_DIR% ( + echo %ICECUBE2_BASE_DIR:"=% + echo -> %ICECUBE2_BASE_DIR:"=% + if exist %ICECUBE2_WORK_DIR% ( + rmdir /S /Q "%ICECUBE2_WORK_DIR%" + ) + mkdir "%ICECUBE2_WORK_DIR%" + xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW! + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/01-WaveformGenerator/Scripts/searchPaths.bat b/01-WaveformGenerator/Scripts/searchPaths.bat new file mode 100644 index 0000000..9b37b1b --- /dev/null +++ b/01-WaveformGenerator/Scripts/searchPaths.bat @@ -0,0 +1,209 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +echo Search HEI Library +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings. + pause&goto:eof + ) +) + + +echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2 +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo %INDENT:"=%Found HDL-Designer at !HDS_HOME! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo %INDENT:"=%Found ISE at !ISE_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice Diamond directory +:: +if %REQUIRE_DIAMOND% == 1 ( + if "%DIAMOND_HOME%" == "" ( + set DIAMOND_HOME=C:\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !DIAMOND_HOME! ( + echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice IceCube2 directory +:: +if %REQUIRE_ICECUBE2% == 1 ( + if "%ICECUBE2_HOME%" == "" ( + set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !ICECUBE2_HOME! ( + echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings. + pause + goto:eof + ) +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + goto:eof \ No newline at end of file diff --git a/01-WaveformGenerator/Scripts/trimLibs.pl b/01-WaveformGenerator/Scripts/trimLibs.pl new file mode 100644 index 0000000..76d8d36 --- /dev/null +++ b/01-WaveformGenerator/Scripts/trimLibs.pl @@ -0,0 +1,170 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ama: [Amand Axel](axel.amand@hevs.ch) +# ------------------------------------------------------------------------------ +# Changelog: +# 2023.05.16 : ama +# * Add: ice40 libs support +# 2023.02.01 : ama +# * Add: ECP5U libs support +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40 + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i) and + not($testline =~ m/ice40.*\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u or ice40 + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i) and + not($testline =~ m/ice40/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/01-WaveformGenerator/Scripts/update_ise.pl b/01-WaveformGenerator/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/01-WaveformGenerator/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ '0'); +END ARCHITECTURE studentVersion; diff --git a/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd b/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd new file mode 100644 index 0000000..892bd7d --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothGen_studentVersion.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE studentVersion OF sawtoothGen IS +BEGIN + sawtooth <= (others => '0'); +END ARCHITECTURE studentVersion; + diff --git a/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd b/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd new file mode 100644 index 0000000..f8b09bd --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToSquare_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF sawtoothToSquare IS +BEGIN + square <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd b/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd new file mode 100644 index 0000000..9fa87cc --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hdl/sawtoothToTriangle_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF sawtoothToTriangle IS +BEGIN + triangle <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd b/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd new file mode 100644 index 0000000..0cb1a55 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hdl/triangleToPolygon_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF triangleToPolygon IS +BEGIN + polygon <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_studentVersion.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_lowpass_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_studentVersion.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothGen_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_studentVersion.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToSquare_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_studentVersion.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothToTriangle_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothgen_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtosquare_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_sawtoothtotriangle_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_studentVersion.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangleToPolygon_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_triangletopolygon_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhd._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhg._fpf b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/.hdlsidedata/_waveformgen_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/_lowpass._epf b/01-WaveformGenerator/WaveformGenerator/hds/_lowpass._epf new file mode 100644 index 0000000..cdf774a --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/_lowpass._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom lowpass_studentVersion.vhd diff --git a/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothgen._epf b/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothgen._epf new file mode 100644 index 0000000..31bcc08 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothgen._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom sawtoothGen_studentVersion.vhd +DEFAULT_ARCHITECTURE atom studentVersion diff --git a/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtosquare._epf b/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtosquare._epf new file mode 100644 index 0000000..13aac32 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtosquare._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom sawtoothToSquare_studentVersion.vhd diff --git a/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtotriangle._epf b/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtotriangle._epf new file mode 100644 index 0000000..195e3b8 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/_sawtoothtotriangle._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom sawtoothToTriangle_studentVersion.vhd diff --git a/01-WaveformGenerator/WaveformGenerator/hds/_triangletopolygon._epf b/01-WaveformGenerator/WaveformGenerator/hds/_triangletopolygon._epf new file mode 100644 index 0000000..29d7453 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/_triangletopolygon._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom triangleToPolygon_studentVersion.vhd diff --git a/01-WaveformGenerator/WaveformGenerator/hds/_waveformgen._epf b/01-WaveformGenerator/WaveformGenerator/hds/_waveformgen._epf new file mode 100644 index 0000000..c91c6be --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/_waveformgen._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom waveform@gen/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/01-WaveformGenerator/WaveformGenerator/hds/lowpass/symbol.sb b/01-WaveformGenerator/WaveformGenerator/hds/lowpass/symbol.sb new file mode 100644 index 0000000..8ea05da --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator/hds/lowpass/symbol.sb @@ -0,0 +1,1607 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2004,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 150,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +) +uid 151,0 +) +*3 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 3,0 +) +) +uid 152,0 +) +*4 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "lowpassOut" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 1 +suid 2,0 +) +) +uid 153,0 +) +*5 (LogPort +port (LogicalPort +decl (Decl +n "lowpassIn" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 4 +suid 4,0 +) +) +uid 154,0 +) +*6 (RefLabelRowHdr +) +*7 (TitleRowHdr +) +*8 (FilterRowHdr +) +*9 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*10 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*11 (GroupColHdr +tm "GroupColHdrMgr" +) +*12 (NameColHdr +tm "NameColHdrMgr" +) +*13 (ModeColHdr +tm "ModeColHdrMgr" +) +*14 (TypeColHdr +tm "TypeColHdrMgr" +) +*15 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*16 (InitColHdr +tm "InitColHdrMgr" +) +*17 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 155,0 +optionalChildren [ +*18 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *19 (MRCItem +litem &1 +pos 4 +dimension 20 +) +uid 90,0 +optionalChildren [ +*20 (MRCItem +litem &6 +pos 0 +dimension 20 +uid 93,0 +) +*21 (MRCItem +litem &7 +pos 1 +dimension 23 +uid 95,0 +) +*22 (MRCItem +litem &8 +pos 2 +hidden 1 +dimension 20 +uid 97,0 +) +*23 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 116,0 +) +*24 (MRCItem +litem &3 +pos 2 +dimension 20 +uid 117,0 +) +*25 (MRCItem +litem &4 +pos 1 +dimension 20 +uid 118,0 +) +*26 (MRCItem +litem &5 +pos 3 +dimension 20 +uid 119,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 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128,0 +) +*54 (MRCItem +litem &47 +pos 0 +dimension 20 +uid 147,0 +) +*55 (MRCItem +litem &48 +pos 1 +dimension 20 +uid 148,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 +) +uid 122,0 +optionalChildren [ +*56 (MRCItem +litem &39 +pos 0 +dimension 20 +uid 130,0 +) +*57 (MRCItem +litem &41 +pos 1 +dimension 50 +uid 134,0 +) +*58 (MRCItem +litem &42 +pos 2 +dimension 100 +uid 136,0 +) +*59 (MRCItem +litem &43 +pos 3 +dimension 100 +uid 138,0 +) +*60 (MRCItem +litem &44 +pos 4 +dimension 50 +uid 140,0 +) +*61 (MRCItem +litem &45 +pos 5 +dimension 50 +uid 142,0 +) +*62 (MRCItem +litem &46 +pos 6 +dimension 80 +uid 144,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 120,0 +vaOverrides [ +] +) +] +) +uid 156,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass" +) +(vvPair +variable "date" +value "03/11/19" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "11" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "lowpass" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "03/11/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "08:02:49" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "WaveformGenerator" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/WaveformGenerator" +) +(vvPair +variable "library_downstream_SpyGlass" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "lowpass" +) +(vvPair +variable "month" +value "Mar" +) +(vvPair +variable "month_long" +value "March" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/WaveformGenerator/Prefs/../WaveformGenerator/hds/lowpass/symbol.sb" +) +(vvPair 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"SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,7800,0,7800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 437,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformGen_tester_test.vhd b/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformGen_tester_test.vhd new file mode 100644 index 0000000..52d3ddd --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformGen_tester_test.vhd @@ -0,0 +1,22 @@ +ARCHITECTURE test OF waveformGen_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + +begin + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + reset <= '1', '0' after 2*clockPeriod; + + ------------------------------------------------------------------------------ + -- enable + en <= '0', '1' after 100 us; + + ------------------------------------------------------------------------------ + -- frequency control + step <= to_unsigned(2**(step'length-13), step'length); + +END ARCHITECTURE test; + diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformGen_tester_test.vhd._fpf b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformGen_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformGen_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhd._fpf b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhg._fpf b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhd._fpf b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhg._fpf b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/.hdlsidedata/_waveformgen_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tb._epf b/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tb._epf new file mode 100644 index 0000000..25a3e3e --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom waveform@gen_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tester._epf b/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tester._epf new file mode 100644 index 0000000..f982b8b --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/_waveformgen_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom waveformGen_tester_test.vhd diff --git a/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd new file mode 100644 index 0000000..1363e34 --- /dev/null +++ b/01-WaveformGenerator/WaveformGenerator_test/hds/waveform@gen_tb/struct.bd @@ -0,0 +1,2865 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_tb" +duLibraryName "WaveformGenerator_test" +duName "waveformGen_tester" +elements [ +(GiElement +name "bitNb" +type "positive" +value "bitNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +mwi 0 +uid 421,0 +) +(Instance +name "I_DUT" +duLibraryName "WaveformGenerator" +duName "waveformGen" +elements [ +(GiElement +name "phaseBitNb" +type "positive" +value "bitNb" +) +(GiElement +name "signalBitNb" +type "positive" +value "bitNb" +) +] +mwi 0 +uid 954,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveform@gen_tb" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveformGen_tb" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "waveformGen_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "14:39:46" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "WaveformGenerator_test" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/WaveformGenerator_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "waveformGen_tb" +) +(vvPair +variable "month" +value "avr." +) +(vvPair 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"C:\\dev\\sem-labs\\01-WaveformGenerator\\Prefs\\..\\WaveformGenerator_test\\hds\\waveformGen_tester\\interface" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_AsmPath" +value "$HEI_LIBS_DIR\\NanoBlaze\\hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "" +) +(vvPair +variable "this_file" +value "interface" +) +(vvPair +variable "this_file_logical" +value "interface" +) +(vvPair +variable "time" +value "14:39:31" +) +(vvPair +variable "unit" +value "waveformGen_tester" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "interface" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 47,0 +optionalChildren [ +*63 (SymbolBody +uid 8,0 +optionalChildren [ +*64 (CptPort +uid 636,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 637,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "28625,5250,29375,6000" +) +tg (CPTG +uid 638,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 639,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "28300,7000,29700,10800" +st "clock" +ju 2 +blo "29500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 640,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,59500,2800" +st "clock : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 41,0 +) +) +) +*65 (CptPort +uid 641,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 642,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26625,5250,27375,6000" +) +tg (CPTG +uid 643,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 644,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "26300,7000,27700,9400" +st "en" +ju 2 +blo "27500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 645,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,59500,3600" +st "en : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "en" +t "std_ulogic" +o 2 +suid 42,0 +) +) +) +*66 (CptPort +uid 646,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 647,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30625,5250,31375,6000" +) +tg (CPTG +uid 648,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 649,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "30300,7000,31700,11100" +st "reset" +ju 2 +blo "31500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 650,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,59500,4400" +st "reset : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 43,0 +) +) +) +*67 (CptPort +uid 651,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 652,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "22625,5250,23375,6000" +) +tg (CPTG +uid 653,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 654,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "22300,7000,23700,10600" +st "step" +ju 2 +blo "23500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 655,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,67000,5200" +st "step : OUT unsigned (bitNb-1 DOWNTO 0) +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "step" +t "unsigned" +b "(bitNb-1 DOWNTO 0)" +o 4 +suid 44,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,67000,14000" +) +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "35650,9000,46350,10000" +st "WaveformGenerator_test" +blo "35650,9800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "35650,10000,44050,11000" +st "waveformGen_tester" +blo "35650,10800" +) +) +gi *68 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "17000,6000,34500,9200" +st "Generic Declarations + +bitNb positive 16 +clockFrequency real 60.0E6 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "bitNb" +type "positive" +value "16" +) +(GiElement +name "clockFrequency" +type "real" +value "60.0E6" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *69 (PackageList +uid 16,0 +stg "VerticalLayoutStrategy" +textVec [ +*70 (Text +uid 17,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*71 (MLText +uid 18,0 +va (VaSet +) +xt "0,1000,17500,4600" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL;" +tm "PackageList" +) +] +) +windowSize "0,0,1016,690" +viewArea "-500,-500,70420,47560" +cachedDiagramExtent "0,0,67000,14000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "WaveformGenerator_test" +entityName "waveformGen_tb" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *72 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *73 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,5200,44400,6200" +st "User:" +blo "42000,6000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6200,44000,6200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 663,0 +activeModelName "Symbol:GEN" +) diff --git a/01-WaveformGenerator/waveformGenerator.bash b/01-WaveformGenerator/waveformGenerator.bash new file mode 100755 index 0000000..933ab09 --- /dev/null +++ b/01-WaveformGenerator/waveformGenerator.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#=============================================================================== +# waveformGenerator.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/Scripts/hdlDesigner.bash" + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp diff --git a/01-WaveformGenerator/waveformGenerator.bat b/01-WaveformGenerator/waveformGenerator.bat new file mode 100644 index 0000000..efe9b97 --- /dev/null +++ b/01-WaveformGenerator/waveformGenerator.bat @@ -0,0 +1,79 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/02-SplineInterpolator/Prefs/hds.hdp b/02-SplineInterpolator/Prefs/hds.hdp new file mode 100644 index 0000000..3a75d9b --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds.hdp @@ -0,0 +1,25 @@ +[Concat] +[ModelSim] +SplineInterpolator = $SCRATCH_DIR/SplineInterpolator +SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +SplineInterpolator = $HDS_PROJECT_DIR/../SplineInterpolator/hdl +SplineInterpolator_test = $HDS_PROJECT_DIR/../SplineInterpolator_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +SplineInterpolator = $HDS_PROJECT_DIR/../SplineInterpolator/hds +SplineInterpolator_test = $HDS_PROJECT_DIR/../SplineInterpolator_test/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/02-SplineInterpolator/Prefs/hds_team/shared.hdp b/02-SplineInterpolator/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/02-SplineInterpolator/Prefs/hds_team/v2018.1/hds_team_prefs b/02-SplineInterpolator/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/02-SplineInterpolator/Prefs/hds_team/v2018.1/title_block.tmpl b/02-SplineInterpolator/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs b/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/02-SplineInterpolator/Prefs/hds_team/v2019.2/title_block.tmpl b/02-SplineInterpolator/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/02-SplineInterpolator/Prefs/hds_team/v2019.3/hds_team_prefs b/02-SplineInterpolator/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/02-SplineInterpolator/Prefs/hds_team/v2019.3/title_block.tmpl b/02-SplineInterpolator/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..0a7d5eb --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6092 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] 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+settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..3d39e11 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/sineGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/hds_user_prefs b/02-SplineInterpolator/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) 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"Verdana,12,1" +) +tBlockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +tBlockLineVaSet (VaSet +vasetType 3 +) +tBlockConditionVaSet (VaSet +) +tBlockActionsVaSet (VaSet +) +tPriorityRadius 40 +tPriorityPadding 100 +tPriorityShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +tPriorityNameVaSet (VaSet +) +transitionShapeVaSet (VaSet +vasetType 3 +) +localDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +localDeclValueVaSet (VaSet +font "Courier New,8,0" +) +processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/generate.tsk b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs b/02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..b9d6429 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6842 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) 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+processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/generate.tsk b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..3d39e11 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/sineGen.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/02-SplineInterpolator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/02-SplineInterpolator/Scripts/cleanGenerated.bash b/02-SplineInterpolator/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/02-SplineInterpolator/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/02-SplineInterpolator/Scripts/cleanGenerated.bat b/02-SplineInterpolator/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/02-SplineInterpolator/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/02-SplineInterpolator/Scripts/cleanScratch.bat b/02-SplineInterpolator/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/02-SplineInterpolator/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/02-SplineInterpolator/Scripts/generateSSHKey.bash b/02-SplineInterpolator/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/02-SplineInterpolator/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/02-SplineInterpolator/Scripts/hdlDesigner.bash b/02-SplineInterpolator/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/02-SplineInterpolator/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/02-SplineInterpolator/Scripts/hdlDesigner.bat b/02-SplineInterpolator/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..2a612a6 --- /dev/null +++ b/02-SplineInterpolator/Scripts/hdlDesigner.bat @@ -0,0 +1,301 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +if %REQUIRE_ICECUBE2% == 1 ( + set synthesis_subdirectory="Board\icecube2" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + if %REQUIRE_ICECUBE2% == 1 ( + echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=% + echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=% + echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +if %REQUIRE_ICECUBE2% == 1 ( + if exist %ICECUBE2_BASE_DIR% ( + echo %ICECUBE2_BASE_DIR:"=% + echo -> %ICECUBE2_BASE_DIR:"=% + if exist %ICECUBE2_WORK_DIR% ( + rmdir /S /Q "%ICECUBE2_WORK_DIR%" + ) + mkdir "%ICECUBE2_WORK_DIR%" + xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW! + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/02-SplineInterpolator/Scripts/searchPaths.bat b/02-SplineInterpolator/Scripts/searchPaths.bat new file mode 100644 index 0000000..9b37b1b --- /dev/null +++ b/02-SplineInterpolator/Scripts/searchPaths.bat @@ -0,0 +1,209 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +echo Search HEI Library +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings. + pause&goto:eof + ) +) + + +echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2 +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo %INDENT:"=%Found HDL-Designer at !HDS_HOME! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo %INDENT:"=%Found ISE at !ISE_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice Diamond directory +:: +if %REQUIRE_DIAMOND% == 1 ( + if "%DIAMOND_HOME%" == "" ( + set DIAMOND_HOME=C:\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !DIAMOND_HOME! ( + echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice IceCube2 directory +:: +if %REQUIRE_ICECUBE2% == 1 ( + if "%ICECUBE2_HOME%" == "" ( + set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !ICECUBE2_HOME! ( + echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings. + pause + goto:eof + ) +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + goto:eof \ No newline at end of file diff --git a/02-SplineInterpolator/Scripts/trimLibs.pl b/02-SplineInterpolator/Scripts/trimLibs.pl new file mode 100644 index 0000000..76d8d36 --- /dev/null +++ b/02-SplineInterpolator/Scripts/trimLibs.pl @@ -0,0 +1,170 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ama: [Amand Axel](axel.amand@hevs.ch) +# ------------------------------------------------------------------------------ +# Changelog: +# 2023.05.16 : ama +# * Add: ice40 libs support +# 2023.02.01 : ama +# * Add: ECP5U libs support +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40 + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i) and + not($testline =~ m/ice40.*\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u or ice40 + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i) and + not($testline =~ m/ice40/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/02-SplineInterpolator/Scripts/update_ise.pl b/02-SplineInterpolator/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/02-SplineInterpolator/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ '0'); +END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd new file mode 100644 index 0000000..f213fce --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE studentVersion OF interpolatorCoefficients IS +BEGIN + a <= (others => '0'); + b <= (others => '0'); + c <= (others => '0'); + d <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd new file mode 100644 index 0000000..428b0ab --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE studentVersion OF interpolatorShiftRegister IS +BEGIN + sample1 <= (others => '0'); + sample2 <= (others => '0'); + sample3 <= (others => '0'); + sample4 <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd new file mode 100644 index 0000000..9dd7350 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF interpolatorTrigger IS +BEGIN + triggerOut <= '0'; +END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_studentVersion.vhd new file mode 100644 index 0000000..360c161 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hdl/offsetToUnsigned_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF offsetToUnsigned IS +BEGIN + unsignedOut <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd new file mode 100644 index 0000000..3d675a6 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF resizer IS +BEGIN + resizeOut <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd b/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd new file mode 100644 index 0000000..3d6518d --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd @@ -0,0 +1,27 @@ +ARCHITECTURE studentVersion OF sineTable IS + + signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0); + signal quarterSine : signed(sine'range); + +BEGIN + + phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + quarterTable: process(phaseTableAddress) + begin + case to_integer(phaseTableAddress) is + when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length); + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTable; + + sine <= (others => '0'); + +END ARCHITECTURE studentVersion; diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorCalculatePolynom_studentVersion.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorCalculatePolynom_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorCalculatePolynom_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorCoefficients_studentVersion.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorCoefficients_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorCoefficients_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorShiftRegister_studentVersion.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorShiftRegister_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorShiftRegister_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorTrigger_studentVersion.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorTrigger_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorTrigger_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcalculatepolynom_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcalculatepolynom_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcalculatepolynom_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcalculatepolynom_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcalculatepolynom_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcalculatepolynom_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcoefficients_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcoefficients_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcoefficients_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcoefficients_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcoefficients_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorcoefficients_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorshiftregister_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorshiftregister_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorshiftregister_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorshiftregister_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorshiftregister_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatorshiftregister_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatortrigger_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatortrigger_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatortrigger_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatortrigger_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatortrigger_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_interpolatortrigger_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsetToUnsigned_studentVersion.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsetToUnsigned_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsetToUnsigned_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsettounsigned_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsettounsigned_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsettounsigned_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsettounsigned_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsettounsigned_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_offsettounsigned_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_studentVersion.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_resizer_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sineTable_studentVersion.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sineTable_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sineTable_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_struct.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_struct.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinegen_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinetable_entity.vhd._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinetable_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinetable_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinetable_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinetable_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/.hdlsidedata/_sinetable_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorcalculatepolynom._epf b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorcalculatepolynom._epf new file mode 100644 index 0000000..56741fd --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorcalculatepolynom._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom interpolatorCalculatePolynom_studentVersion.vhd diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorcoefficients._epf b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorcoefficients._epf new file mode 100644 index 0000000..0361627 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorcoefficients._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom interpolatorCoefficients_studentVersion.vhd diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorshiftregister._epf b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorshiftregister._epf new file mode 100644 index 0000000..5ff59f7 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatorshiftregister._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom interpolatorShiftRegister_studentVersion.vhd diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_interpolatortrigger._epf b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatortrigger._epf new file mode 100644 index 0000000..c5b0ad1 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_interpolatortrigger._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom interpolatorTrigger_studentVersion.vhd diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_offsettounsigned._epf b/02-SplineInterpolator/SplineInterpolator/hds/_offsettounsigned._epf new file mode 100644 index 0000000..62b5327 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_offsettounsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom offsetToUnsigned_studentVersion.vhd diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_resizer._epf b/02-SplineInterpolator/SplineInterpolator/hds/_resizer._epf new file mode 100644 index 0000000..1693d2c --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_resizer._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom resizer_studentVersion.vhd diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_sinegen._epf b/02-SplineInterpolator/SplineInterpolator/hds/_sinegen._epf new file mode 100644 index 0000000..6851f1a --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_sinegen._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom sine@gen/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/02-SplineInterpolator/SplineInterpolator/hds/_sinetable._epf b/02-SplineInterpolator/SplineInterpolator/hds/_sinetable._epf new file mode 100644 index 0000000..4501d06 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/_sinetable._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom sineTable_studentVersion.vhd diff --git a/02-SplineInterpolator/SplineInterpolator/hds/interpolator@calculate@polynom/symbol.sb b/02-SplineInterpolator/SplineInterpolator/hds/interpolator@calculate@polynom/symbol.sb new file mode 100644 index 0000000..1b614fd --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator/hds/interpolator@calculate@polynom/symbol.sb @@ -0,0 +1,1938 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2009,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 214,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 2,0 +) +) +uid 215,0 +) +*3 (LogPort +port (LogicalPort +decl (Decl +n "d" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 4 +suid 4,0 +) +) +uid 216,0 +) +*4 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "sampleOut" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 5 +suid 5,0 +) +) +uid 217,0 +) +*5 (LogPort +port (LogicalPort +decl (Decl +n "a" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 8 +suid 8,0 +) +) +uid 218,0 +) +*6 (LogPort +port (LogicalPort +decl (Decl +n "restartPolynom" +t "std_ulogic" +o 3 +suid 3,0 +) +) +uid 219,0 +) +*7 (LogPort +port (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 9 +suid 9,0 +) +) +uid 220,0 +) +*8 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +uid 221,0 +) +*9 (LogPort +port (LogicalPort +decl (Decl +n "c" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 6 +suid 6,0 +) +) +uid 222,0 +) +*10 (LogPort +port (LogicalPort +decl (Decl +n "b" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 7 +suid 7,0 +) +) +uid 223,0 +) +*11 (RefLabelRowHdr +) +*12 (TitleRowHdr +) +*13 (FilterRowHdr +) +*14 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*15 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*16 (GroupColHdr +tm "GroupColHdrMgr" +) +*17 (NameColHdr +tm "NameColHdrMgr" +) +*18 (ModeColHdr +tm "ModeColHdrMgr" +) +*19 (TypeColHdr +tm "TypeColHdrMgr" +) +*20 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*21 (InitColHdr +tm "InitColHdrMgr" +) +*22 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 224,0 +optionalChildren [ +*23 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *24 (MRCItem +litem &1 +pos 9 +dimension 20 +) +uid 147,0 +optionalChildren [ +*25 (MRCItem +litem &11 +pos 0 +dimension 20 +uid 150,0 +) +*26 (MRCItem +litem &12 +pos 1 +dimension 23 +uid 152,0 +) +*27 (MRCItem +litem &13 +pos 2 +hidden 1 +dimension 20 +uid 154,0 +) +*28 (MRCItem +litem &2 +pos 1 +dimension 20 +uid 173,0 +) +*29 (MRCItem +litem &3 +pos 3 +dimension 20 +uid 174,0 +) +*30 (MRCItem +litem &4 +pos 4 +dimension 20 +uid 175,0 +) +*31 (MRCItem +litem &5 +pos 7 +dimension 20 +uid 176,0 +) +*32 (MRCItem +litem &6 +pos 2 +dimension 20 +uid 177,0 +) +*33 (MRCItem +litem &7 +pos 8 +dimension 20 +uid 178,0 +) +*34 (MRCItem +litem &8 +pos 0 +dimension 20 +uid 179,0 +) +*35 (MRCItem +litem &9 +pos 5 +dimension 20 +uid 180,0 +) +*36 (MRCItem +litem &10 +pos 6 +dimension 20 +uid 181,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 +) +uid 148,0 +optionalChildren [ +*37 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 156,0 +) +*38 (MRCItem +litem &16 +pos 1 +dimension 50 +uid 160,0 +) +*39 (MRCItem +litem &17 +pos 2 +dimension 100 +uid 162,0 +) +*40 (MRCItem +litem &18 +pos 3 +dimension 50 +uid 164,0 +) +*41 (MRCItem +litem &19 +pos 4 +dimension 100 +uid 166,0 +) +*42 (MRCItem +litem &20 +pos 5 +dimension 100 +uid 168,0 +) +*43 (MRCItem +litem &21 +pos 6 +dimension 50 +uid 170,0 +) +*44 (MRCItem +litem &22 +pos 7 +dimension 80 +uid 172,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 146,0 +vaOverrides [ +] +) +] +) +uid 213,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *45 (LEmptyRow +) +uid 226,0 +optionalChildren [ +*46 (RefLabelRowHdr +) +*47 (TitleRowHdr +) +*48 (FilterRowHdr +) +*49 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*50 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*51 (GroupColHdr +tm "GroupColHdrMgr" +) +*52 (NameColHdr +tm "GenericNameColHdrMgr" +) +*53 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*54 (InitColHdr +tm "GenericValueColHdrMgr" +) +*55 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*56 (EolColHdr +tm "GenericEolColHdrMgr" +) +*57 (LogGeneric +generic (GiElement +name "signalBitNb" +type "positive" +value "16" +) +uid 207,0 +) +*58 (LogGeneric +generic (GiElement +name "coeffBitNb" +type "positive" +value "16" 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------------------------------------------------------------------------------ + -- controls + step <= to_unsigned(1, step'length); + +END ARCHITECTURE test; diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sineGen_tester_test.vhd._fpf b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sineGen_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sineGen_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_struct.vhg._fpf b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tester_entity.vhg._fpf b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tb._epf b/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tb._epf new file mode 100644 index 0000000..5d5516c --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom sine@gen_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tester._epf b/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tester._epf new file mode 100644 index 0000000..9adfb0b --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom sineGen_tester_test.vhd diff --git a/02-SplineInterpolator/SplineInterpolator_test/hds/sine@gen_tb/struct.bd b/02-SplineInterpolator/SplineInterpolator_test/hds/sine@gen_tb/struct.bd new file mode 100644 index 0000000..0e7d699 --- /dev/null +++ b/02-SplineInterpolator/SplineInterpolator_test/hds/sine@gen_tb/struct.bd @@ -0,0 +1,3042 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" 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real := 66.0E6;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,48000,9000,49000" +st "Diagram Signals:" +blo "0,48800" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "0,41000,6000,42000" +st "Post User:" +blo "0,41800" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,41000,0,41000" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 8,0 +usingSuid 1 +emptyRow *72 (LEmptyRow +) +uid 1087,0 +optionalChildren [ +*73 (RefLabelRowHdr +) +*74 (TitleRowHdr +) +*75 (FilterRowHdr +) +*76 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*77 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*78 (GroupColHdr +tm "GroupColHdrMgr" +) +*79 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*80 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" +) +*81 (TypeColHdr +tm "BlockDiagramTypeColHdrMgr" +) +*82 (BoundsColHdr +tm "BlockDiagramBoundsColHdrMgr" +) +*83 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1116,0 +optionalChildren [ +*113 (RefLabelRowHdr +) +*114 (TitleRowHdr +) +*115 (FilterRowHdr +) +*116 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*117 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*118 (GroupColHdr +tm "GroupColHdrMgr" +) +*119 (NameColHdr +tm "GenericNameColHdrMgr" +) +*120 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*121 (InitColHdr +tm "GenericValueColHdrMgr" +) +*122 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*123 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 1128,0 +optionalChildren [ +*124 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *125 (MRCItem +litem &112 +pos 0 +dimension 20 +) +uid 1130,0 +optionalChildren [ +*126 (MRCItem +litem &113 +pos 0 +dimension 20 +uid 1131,0 +) +*127 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+xt "44000,8600,44000,8600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 447,0 +activeModelName "Symbol:GEN" +) diff --git a/02-SplineInterpolator/splineInterpolator.bash b/02-SplineInterpolator/splineInterpolator.bash new file mode 100755 index 0000000..933ab09 --- /dev/null +++ b/02-SplineInterpolator/splineInterpolator.bash @@ -0,0 +1,32 @@ +#!/bin/bash + +#=============================================================================== +# waveformGenerator.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/Scripts/hdlDesigner.bash" + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp diff --git a/02-SplineInterpolator/splineInterpolator.bat b/02-SplineInterpolator/splineInterpolator.bat new file mode 100644 index 0000000..efe9b97 --- /dev/null +++ b/02-SplineInterpolator/splineInterpolator.bat @@ -0,0 +1,79 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd new file mode 100644 index 0000000..c03bc9a --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order1_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF DAC IS +BEGIN + serialOut <= '0'; +END ARCHITECTURE studentVersion; diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd new file mode 100644 index 0000000..fb41871 --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl/DAC_order2_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE order2_studentVersion OF DAC IS +BEGIN + serialOut <= '0'; +END ARCHITECTURE order2_studentVersion; diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order1_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_DAC_order2_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhg._fpf b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds/.hdlsidedata/_dac_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git 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DAC_order1_studentVersion.vhd diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd b/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd new file mode 100644 index 0000000..843d64b --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl/DAC_tester_test.vhd @@ -0,0 +1,38 @@ +library ieee; + use ieee.math_real.all; + +ARCHITECTURE test OF DAC_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + + signal sineFrequency: real := 20.0E3; + signal tReal: real := 0.0; + signal outAmplitude: real := 1.0; + signal outReal: real := 0.0; + signal outUnsigned: unsigned(parallelIn'range); + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + reset <= '1', '0' after 2*clockPeriod; + + ------------------------------------------------------------------------------ + -- time signals + process(sClock) + begin + if rising_edge(sClock) then + tReal <= tReal + 1.0/clockFrequency; + end if; + end process; + + outReal <= outAmplitude * ( sin(2.0*math_pi*sineFrequency*tReal) + 1.0) / 2.0; + + outUnsigned <= to_unsigned(integer(outReal * real(2**(outUnsigned'length)-1)), outUnsigned'length); + parallelIn <= outUnsigned; +-- parallelIn <= shift_left(to_unsigned(1, parallelIn'length), parallelIn'length-1); +-- parallelIn <= shift_left(to_unsigned(3, parallelIn'length), parallelIn'length-2); + +END ARCHITECTURE test; diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_DAC_tester_test.vhd._fpf b/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/.hdlsidedata/_DAC_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ 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"VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Verdana,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Verdana,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *87 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,0,49000,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,1000,45400,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,6000,45000,7000" +st "User:" +blo "42000,6800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "42000,0,49600,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Verdana,8,0" +) +xt "44000,7000,44000,7000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 389,0 +activeModelName "Symbol:GEN" +) diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tb._epf b/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tb._epf new file mode 100644 index 0000000..066bc61 --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom @d@a@c_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tester._epf b/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tester._epf new file mode 100644 index 0000000..2a4c41f --- /dev/null +++ b/03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds/_dac_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom DAC_tester_test.vhd diff --git a/03-DigitalToAnalogConverter/Prefs/hds.hdp b/03-DigitalToAnalogConverter/Prefs/hds.hdp new file mode 100644 index 0000000..8d4c2df --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds.hdp @@ -0,0 +1,31 @@ +[Concat] +[ModelSim] +DigitalToAnalogConverter = $SCRATCH_DIR/DigitalToAnalogConverter +DigitalToAnalogConverter_test = $SCRATCH_DIR/DigitalToAnalogConverter_test +SplineInterpolator = $SCRATCH_DIR/SplineInterpolator +SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../DigitalToAnalogConverter/hdl +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../DigitalToAnalogConverter_test/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hdl +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl +[hds] +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../DigitalToAnalogConverter/hds +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../DigitalToAnalogConverter_test/hds +ieee = $HDS_HOME/hdl_libs/ieee/hds +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hds +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/03-DigitalToAnalogConverter/Prefs/hds_team/shared.hdp b/03-DigitalToAnalogConverter/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/hds_team_prefs b/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/title_block.tmpl b/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/hds_team_prefs b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/title_block.tmpl b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/hds_team_prefs b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/title_block.tmpl b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..c09cedf --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6092 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Sublime" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ 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+lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "courier,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "courier,8,1" +) +CompDirValueVaSet (VaSet +font "courier,8,0" +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "courier,8,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "courier,8,1" +) +cptPortFontVaSet (VaSet +font "courier,8,0" +) +genericInterfaceFontVaSet (VaSet +font "courier,8,0" +) +portRowVaSet (VaSet +vasetType 4 +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..f0a0260 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/DAC.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pcf" +Description "Xilinx Place and Route Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ucf" +Description "Xilinx User Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncd" +Description "Xilinx Floorplanner File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncd.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bld" +Description "Xilinx NGDBuild Log" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bit" +Description "Xilinx Bit File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "bin" +Description "Xilinx Binary Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbt" +Description "Xilinx ASCII Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "jed" +Description "Xilinx Jedec Bit Map File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ngc" +Description "Xilinx Netlist File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\synthesis.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "npl" +Description "Xilinx ISE Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xilinx_projnav.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psp" +Description "Precision Synthesis Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\precision.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qpf" +Description "Quartus Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\altera_quartus.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "qsf" +Description "Quartus Settings and Assigments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "qws" +Description "Quartus Workspace" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "args" +Description "Quartus Arguments" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_synthesis.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rpt" +Description "Quartus Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "summary" +Description "Quartus Summary File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "eqn" +Description "Quartus Equation File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pin" +Description "Quartus Pin Information File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "vqm" +Description "Quartus Verilog Mapping File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\vqm.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdo" +Description "Standard Delay File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xrf" +Description "Cross Reference File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "pof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbf" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ttf" +Description "Quartus Text Tabular Format Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pdf" +Description "Adobe Acrobat Pdf" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pdf.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "doc" +Description "Microsoft Word Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\word.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "xls" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "tsv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "csv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ppt" +Description "Microsoft PowerPoint Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\powerpoint.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "vsd" +Description "Microsoft Visio Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\visio.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "htm" +Description "HTM File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\web.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "html" +Description "HTML File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\web.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psl" +Description "Property Specification Language File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\psl.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "View" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xlsm" +Description "Excel macro-enabled spreadsheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "rcf" +Description "RA control file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\RaCtrlFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "View" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "js" +Description "Javascript" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jsFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "xml" +Description "xml file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "ipxact" +Description "IP-XACT file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "css" +Description "HTML style sheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cssFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "gif" +Description "GIF image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\gifFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "jpg" +Description "JPG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jpgFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "png" +Description "PNG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pngFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "svap" +Description "SVAssistant project file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\svapFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "Open" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +(ActionState +Name "View" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +] +) +] +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" 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+(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" +width 150 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Name" +displayName "" +width 250 +) +(TreeListVPData_Column +name "Library" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +] +SmartTableVPDatas [ +(SmartTableVPData +theList "Logical Objects" +columns [ +(SmartTableVPData_Column +name "Parse Error" +width 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"Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/generate.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..63ce98f --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6842 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" 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"Cursor_test" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Cursor_test" +primaryName "cursor_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Board" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Board" +primaryName "FPGA_cursor" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "LCD" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 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+vasetType 1 +fg "65535,65535,0" +) +ccondNameVaSet (VaSet +) +ccondShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,32768,49152" +) +recoveryShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +stateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +stateNameVaSet (VaSet +font "Verdana,12,1" +) +stateEncodingVaSet (VaSet +font "Verdana,9,1" +) +stateActionsVaSet (VaSet +) +stateActionShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +stateCaseVaSet (VaSet +font "Verdana,9,1" +) +cStateShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "0,0,32768" +lineWidth 2 +) +cStateNameVaSet (VaSet +font "Verdana,10,1" +) +junctionShapeVaSet (VaSet +vasetType 1 +fg "59904,39936,65280" +) +junctionNameVaSet (VaSet +font "Verdana,9,1" +) +junctionSymbolVaSet (VaSet +font "Verdana,10,1" +) +entryPointShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +) 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+processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..f0a0260 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/DAC.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/03-DigitalToAnalogConverter/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bash b/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bat b/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/03-DigitalToAnalogConverter/Scripts/cleanScratch.bat b/03-DigitalToAnalogConverter/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/03-DigitalToAnalogConverter/Scripts/generateSSHKey.bash b/03-DigitalToAnalogConverter/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bash b/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bat b/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..2a612a6 --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/hdlDesigner.bat @@ -0,0 +1,301 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +if %REQUIRE_ICECUBE2% == 1 ( + set synthesis_subdirectory="Board\icecube2" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + if %REQUIRE_ICECUBE2% == 1 ( + echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=% + echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=% + echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +if %REQUIRE_ICECUBE2% == 1 ( + if exist %ICECUBE2_BASE_DIR% ( + echo %ICECUBE2_BASE_DIR:"=% + echo -> %ICECUBE2_BASE_DIR:"=% + if exist %ICECUBE2_WORK_DIR% ( + rmdir /S /Q "%ICECUBE2_WORK_DIR%" + ) + mkdir "%ICECUBE2_WORK_DIR%" + xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW! + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/03-DigitalToAnalogConverter/Scripts/searchPaths.bat b/03-DigitalToAnalogConverter/Scripts/searchPaths.bat new file mode 100644 index 0000000..9b37b1b --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/searchPaths.bat @@ -0,0 +1,209 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +echo Search HEI Library +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings. + pause&goto:eof + ) +) + + +echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2 +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo %INDENT:"=%Found HDL-Designer at !HDS_HOME! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo %INDENT:"=%Found ISE at !ISE_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice Diamond directory +:: +if %REQUIRE_DIAMOND% == 1 ( + if "%DIAMOND_HOME%" == "" ( + set DIAMOND_HOME=C:\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !DIAMOND_HOME! ( + echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice IceCube2 directory +:: +if %REQUIRE_ICECUBE2% == 1 ( + if "%ICECUBE2_HOME%" == "" ( + set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !ICECUBE2_HOME! ( + echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings. + pause + goto:eof + ) +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + goto:eof \ No newline at end of file diff --git a/03-DigitalToAnalogConverter/Scripts/trimLibs.pl b/03-DigitalToAnalogConverter/Scripts/trimLibs.pl new file mode 100644 index 0000000..76d8d36 --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/trimLibs.pl @@ -0,0 +1,170 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ama: [Amand Axel](axel.amand@hevs.ch) +# ------------------------------------------------------------------------------ +# Changelog: +# 2023.05.16 : ama +# * Add: ice40 libs support +# 2023.02.01 : ama +# * Add: ECP5U libs support +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40 + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i) and + not($testline =~ m/ice40.*\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u or ice40 + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i) and + not($testline =~ m/ice40/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/03-DigitalToAnalogConverter/Scripts/update_ise.pl b/03-DigitalToAnalogConverter/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/03-DigitalToAnalogConverter/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ '0'); + elsif rising_edge(clock) then + if quantized = '0' then + integrator <= integrator + parallelIn1; + else + integrator <= integrator + parallelIn1 - 2**parallelIn'length; + end if; + end if; + end process integrate; + + quantized <= integrator(integrator'high); + + serialOut <= quantized; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:40 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineGen IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineGen ; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:20 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCoefficients IS + GENERIC( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + +-- Declarations + +END interpolatorCoefficients ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCoefficients IS +BEGIN + + calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4) + begin + if interpolateLinear = '1' then + a <= (others => '0'); + b <= (others => '0'); + c <= resize(2*sample3, c'length) + - resize(2*sample2, c'length); + d <= resize( sample2, d'length); + else + a <= resize( sample4, a'length) + - resize(3*sample3, a'length) + + resize(3*sample2, a'length) + - resize( sample1, a'length); + b <= resize(2*sample1, b'length) + - resize(5*sample2, b'length) + + resize(4*sample3, b'length) + - resize( sample4, b'length); + c <= resize( sample3, c'length) + - resize( sample1, c'length); + d <= resize( sample2, d'length); + end if; + end process calcCoeffs; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity WaveformGenerator.sawtoothGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothGen IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END sawtoothGen ; + + + + + +ARCHITECTURE masterVersion OF sawtoothGen IS + + signal counter: unsigned(sawtooth'range); + +begin + + count: process(reset, clock) + begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter + step; + end if; + end if; + end process count; + + sawtooth <= counter; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:24 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorShiftRegister IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + shiftSamples : IN std_ulogic; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END interpolatorShiftRegister ; + + + + + +ARCHITECTURE masterVersion OF interpolatorShiftRegister IS + + -- signal sample4_int: signed(sampleIn'range); + -- signal sample3_int: signed(sampleIn'range); + -- signal sample2_int: signed(sampleIn'range); + -- signal sample1_int: signed(sampleIn'range); + + type samplesArray is array(3 downto 0) of signed(sampleIn'range); + signal samples: samplesArray; + +begin + + shiftThem: process(reset, clock) + begin + if reset = '1' then + samples <= (others=>(others=>'0')); + -- sample1_int <= (others => '0'); + -- sample2_int <= (others => '0'); + -- sample3_int <= (others => '0'); + -- sample4_int <= (others => '0'); + elsif rising_edge(clock) then + if shiftSamples = '1' then + -- sample1_int <= sample2_int; + -- sample2_int <= sample3_int; + -- sample3_int <= sample4_int; + -- sample4_int <= sampleIn; + samples(0) <= samples(1); + samples(1) <= samples(2); + samples(2) <= samples(3); + samples(3) <= sampleIn; + end if; + end if; + end process shiftThem; + + sample4 <= samples(3); + sample3 <= samples(2); + sample2 <= samples(1); + sample1 <= samples(0); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineTable.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:46 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineTable IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineTable ; + + + + + +ARCHITECTURE masterVersion OF sineTable IS + + signal changeSign : std_uLogic; + signal flipPhase : std_uLogic; + signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0); + signal phaseTableAddress2 : unsigned(phaseTableAddress1'range); + signal quarterSine : signed(sine'range); + + signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine + +begin + + changeSign <= phase(phase'high); + flipPhase <= phase(phase'high-1); + + phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1) + begin + if (flipPhase xor shiftPhase) = '0' then + phaseTableAddress2 <= phaseTableAddress1; + else + phaseTableAddress2 <= 0 - phaseTableAddress1; + end if; + end process checkPhase; + + + quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if (flipPhase xor shiftPhase) = '0' then + quarterSine <= to_signed(16#0000#, quarterSine'length); + else + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTable; + + checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine) + begin + if (changeSign xor (flipPhase and shiftPhase)) = '0' then + sine <= quarterSine; + else + sine <= 0 - quarterSine; + end if; + end process checkSign; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.resizer.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:36 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY resizer IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END resizer ; + + + + + +ARCHITECTURE masterVersion OF resizer IS + +BEGIN + + outGtIn: if resizeOut'length > resizeIn'length generate + begin + resizeOut <= shift_left( + resize( + resizeIn, + resizeOut'length + ), + resizeOut'length-resizeIn'length + ); + end generate outGtIn; + + outEqIn: if resizeOut'length = resizeIn'length generate + begin + resizeOut <= resizeIn; + end generate outEqIn; + + outLtIn: if resizeOut'length < resizeIn'length generate + begin + resizeOut <= resize( + shift_right( + resizeIn, + resizeIn'length-resizeOut'length + ), + resizeOut'length + ); + end generate outLtIn; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCalculatePolynom IS + GENERIC( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + restartPolynom : IN std_ulogic; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorCalculatePolynom ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS + + constant additionalBitNb: positive := 1; + constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1 + + additionalBitNb; + signal x: signed(internalsBitNb-1 downto 0); + signal u: signed(internalsBitNb-1 downto 0); + signal v: signed(internalsBitNb-1 downto 0); + signal w: signed(internalsBitNb-1 downto 0); + +BEGIN + + iterativePolynom: process(reset, clock) + begin + if reset = '1' then + x <= (others => '0'); + u <= (others => '0'); + v <= (others => '0'); + w <= (others => '0'); + sampleOut <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if restartPolynom = '1' then + x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb); + u <= resize(a, u'length) + + shift_left(resize(b, u'length), oversamplingBitNb) + + shift_left(resize(c, u'length), 2*oversamplingBitNb); + v <= resize(6*a, v'length) + + shift_left(resize(2*b, v'length), oversamplingBitNb); + w <= resize(6*a, w'length); + sampleOut <= resize(d, sampleOut'length); + else + x <= x + u; + u <= u + v; + v <= v + w; + sampleOut <= resize( + shift_right(x, 3*oversamplingBitNb+1), sampleOut'length + ); + -- limit overflow + if x(x'high downto x'high-additionalBitNb) = "01" then + sampleOut <= not shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + -- limit underflow + if x(x'high downto x'high-additionalBitNb) = "10" then + sampleOut <= shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + end if; + end if; + end if; + end process iterativePolynom; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToSquare IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToSquare ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToSquare IS +BEGIN + + square <= (others => sawtooth(sawtooth'high)); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToTriangle IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToTriangle ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToTriangle IS + + signal MSB: std_uLogic; + signal triangleInt: unsigned(triangle'range); + +begin + + MSB <= sawtooth(sawtooth'high); + + foldDown: process(MSB, sawtooth) + begin + if MSB = '0' then + triangleInt <= sawtooth; + else + triangleInt <= not sawtooth; + end if; + end process foldDown; + + triangle <= triangleInt(triangleInt'high-1 downto 0) & '0'; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:28 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorTrigger IS + GENERIC( + counterBitNb : positive := 4 + ); + PORT( + triggerOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorTrigger ; + + + + + +ARCHITECTURE masterVersion OF interpolatorTrigger IS + + signal triggerCounter: unsigned(counterBitNb-1 downto 0); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + triggerCounter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + triggerCounter <= triggerCounter + 1; + end if; + end if; + end process count; + + trig: process(triggerCounter, en) + begin + if triggerCounter = 0 then + triggerOut <= en; + else + triggerOut <= '0'; + end if; + end process trig; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:32 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY offsetToUnsigned IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END offsetToUnsigned ; + + + + + +ARCHITECTURE masterVersion OF offsetToUnsigned IS + +BEGIN + + unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0)); + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SplineInterpolator.sineGen.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:42:04 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY SplineInterpolator; +LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF sineGen IS + + -- Architecture declarations + constant tableAddressBitNb : positive := 3; + constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb; + constant coeffBitNb : positive := signalBitNb+4; + + -- Internal signal declarations + SIGNAL a : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL b : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL c : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL d : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_ulogic; + SIGNAL newPolynom : std_ulogic; + SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT interpolatorCalculatePolynom + GENERIC ( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + restartPolynom : IN std_ulogic ; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCoefficients + GENERIC ( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT ( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorShiftRegister + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + shiftSamples : IN std_ulogic ; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT interpolatorTrigger + GENERIC ( + counterBitNb : positive := 4 + ); + PORT ( + triggerOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT offsetToUnsigned + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT resizer + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT ( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sineTable + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT ( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT sawtoothToSquare + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothToTriangle + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom; + FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients; + FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister; + FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger; + FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned; + FOR ALL : resizer USE ENTITY SplineInterpolator.resizer; + FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; + FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare; + FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle; + FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + logic1 <= '1'; + + -- HDL Embedded Text Block 3 eb3 + logic0 <= '0'; + + + -- Instance port mappings. + I_spline : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom, + d => d, + sampleOut => sineSigned, + c => c, + b => b, + a => a, + en => logic1 + ); + I_coeffs : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4, + a => a, + b => b, + c => c, + d => d, + interpolateLinear => logic0 + ); + I_shReg : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom, + sampleIn => sineSamples, + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4 + ); + I_trig : interpolatorTrigger + GENERIC MAP ( + counterBitNb => sampleCountBitNb + ) + PORT MAP ( + triggerOut => newPolynom, + clock => clock, + reset => reset, + en => logic1 + ); + I_unsigned : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => sine, + signedIn => sineSigned + ); + I_size : resizer + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb + ) + PORT MAP ( + resizeOut => sawtooth_internal, + resizeIn => phase + ); + I_sin : sineTable + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb, + tableAddressBitNb => tableAddressBitNb + ) + PORT MAP ( + sine => sineSamples, + phase => phase + ); + I_saw : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => phase, + clock => clock, + reset => reset, + step => step, + en => logic1 + ); + I_square : sawtoothToSquare + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + square => square, + sawtooth => sawtooth_internal + ); + I_tri : sawtoothToTriangle + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + triangle => triangle, + sawtooth => sawtooth_internal + ); + + -- Implicit buffered output assignments + sawtooth <= sawtooth_internal; + +END struct; + + + + +-- +-- VHDL Architecture Lissajous.lissajousGenerator.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:47:09 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY DigitalToAnalogConverter; +LIBRARY SplineInterpolator; + +ARCHITECTURE struct OF lissajousGenerator IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT DAC + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + serialOut : OUT std_ulogic ; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT sineGen + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC; + FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + triggerOut <= squareY(squareY'high); + + -- HDL Embedded Text Block 2 eb2 + stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length); + + -- HDL Embedded Text Block 3 eb3 + stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length); + + + -- Instance port mappings. + I_dacX : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => xOut, + parallelIn => sineX, + clock => clock, + reset => reset + ); + I_dacY : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => yOut, + parallelIn => sineY, + clock => clock, + reset => reset + ); + I_sinX : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepXUnsigned, + sawtooth => OPEN, + sine => sineX, + square => OPEN, + triangle => OPEN + ); + I_sinY : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepYUnsigned, + sawtooth => OPEN, + sine => sineY, + square => squareY, + triangle => OPEN + ); + +END struct; + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- +-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:49 01.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY Board; +LIBRARY Lattice; +LIBRARY Lissajous; + +ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant phaseBitNb: positive := 17; + constant stepX: positive := 3; + constant stepY: positive := 4; + + -- Internal signal declarations + SIGNAL clkSys : std_ulogic; + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_N : std_ulogic; + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT lissajousGenerator + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + triggerOut : OUT std_ulogic ; + xOut : OUT std_ulogic ; + yOut : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DFF USE ENTITY Board.DFF; + FOR ALL : inverterIn USE ENTITY Board.inverterIn; + FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator; + FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 5 eb5 + logic1 <= '1'; + + -- HDL Embedded Text Block 6 eb6 + logic0 <= '0'; + + + -- Instance port mappings. + I_dff : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSynch_N + ); + I_inv1 : inverterIn + PORT MAP ( + in1 => reset_N, + out1 => reset + ); + I_inv2 : inverterIn + PORT MAP ( + in1 => resetSynch_N, + out1 => resetSynch + ); + U_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clkSys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_main : lissajousGenerator + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb, + stepX => stepX, + stepY => stepY + ) + PORT MAP ( + clock => clkSys, + reset => resetSynch, + triggerOut => triggerOut, + xOut => xOut, + yOut => yOut + ); + +END masterVersion; + + + + diff --git a/04-Lissajous/Board/concat/lissajous.lpf b/04-Lissajous/Board/concat/lissajous.lpf new file mode 100644 index 0000000..2d14664 --- /dev/null +++ b/04-Lissajous/Board/concat/lissajous.lpf @@ -0,0 +1,334 @@ +### For reference, see TN1262 / FPGA-TN-02032 +# .lpf file format is not really documented by Lattice, normally generated through Diamond + + +################ +#### sysCONFIG +################ + +# The BLOCK commands disable tracing of paths within clock domains (impacting overall timing score) +# It can also be used on paths if the TRACE should not consider the clock domain crossing +# like : BLOCK PATH FROM CLKNET "CLK_A" TO CLKNET "CLK_B" ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK JTAGPATHS ; +BLOCK RD_DURING_WR_PATHS ; + + +# Not comprehensive +# dflt : CONFIG_IOVOLTAGE 1.2, 1.5, 1.8, 2.5(dflt), 3.3 voltage is 3.3V +# dflt : COMPRESS_CONFIG OFF (dflt), ON no bitstream compression +# mod : MCCLK_FREQ 2.4, 4.8, 9.7, 19.4, 38.8, 62 NOR program read @ 62MHz +# mod : MASTER_SPI_PORT DISABLE (dflt), ENABLE master SPI port stays SPI and not GPIOs, other mods disabled by dflt +# dflt : BACKGROUND_RECONFIG - no soft ERC when hot-loading bitstream (due to cosmic rays) +# dflt : DONE_PULL ON (dflt), OFF IPU on DONE pin +# dflt : DONE_EX OFF (dflt), ON not delaying end of the configuration (used for daisy chaining FPGAs) +# mod : DONE_OD OFF (dflt), ON DONE pin as open-drain instead of push-pull +# dflt : CONFIG_SECURE OFF (dflt), ON allows external access to current program +# mod : CONFIG_MODE JTAG (dflt), SSPI, SPI_SERIAL, SPI_DUAL, SPI_QUAD, SLAVE_PARALLEL, SLAVE_SERIAL +# which bus and mode is used to load configuration (for the Lattic IDE) +# dflt : TRANSFR OFF (dflt), ON if using TransFR tool from Lattice +# dflt : WAKE_UP 4 (set DONE=1 before starting user code, dflt for DONE_EX=ON) +# 21 (set DONE=1 once FPGA is already running user code, dflt for DONE_EX=OFF) +# mod : INBUF ON, OFF disable unused input buffers (not sure it impacts the ECP5 family) +SYSCONFIG MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE DONE_OD=ON CONFIG_MODE=SPI_QUAD INBUF=OFF CONFIG_IOVOLTAGE=3.3 ; +IOBUF ALLPORTS IO_TYPE=LVCMOS33 ; + +################ +#### Labs DB +################ + +### Clock and reset ### +#INPUT_SETUP ALLPORTS 50.000000 ns HOLD 10.000000 ns CLKPORT "CLK" ; +#INPUT_SETUP PORT "nRST" 50.000000 ns CLKPORT "CLK" ; + +FREQUENCY PORT "clock" 100.000000 MHz ; +LOCATE COMP "clock" SITE "K16" ; +IOBUF PORT "clock" PULLMODE=NONE ; + +LOCATE COMP "reset_N" SITE "E13" ; +GSR_NET NET "resetSynch_N"; + + +### LEDs ### +LOCATE COMP "LED1" SITE "T14" ;# red +LOCATE COMP "LED2" SITE "R14" ;# green +LOCATE COMP "LED3" SITE "T15" ;# blue + + +################ +#### SODIMM-200 +################ + +### PP2 ### +LOCATE COMP "xOut" SITE "G3" ; +LOCATE COMP "yOut" SITE "E1" ; +#LOCATE COMP "" SITE "F3" ; +LOCATE COMP "triggerOut" SITE "D1" ; +#LOCATE COMP "" SITE "F4" ; +#LOCATE COMP "" SITE "C1" ; +#LOCATE COMP "" SITE "D7" ; +#LOCATE COMP "" SITE "B6" ; +#LOCATE COMP "" SITE "C7" ; +#LOCATE COMP "" SITE "A6" ; # PP2 11 +#LOCATE COMP "" SITE "D8" ; # PP2 13 +#LOCATE COMP "" SITE "B7" ; # PP2 15 +#LOCATE COMP "" SITE "C8" ; # PP2 17 +#LOCATE COMP "" SITE "A7" ; # PP2 19 +#LOCATE COMP "" SITE "E9" ; # PP2 21 +#LOCATE COMP "" SITE "A8" ; # PP2 23 +#LOCATE COMP "" SITE "D9" ; # PP2 25 + + +### PP1 ### +#LOCATE COMP "" SITE "A9" ; +#LOCATE COMP "" SITE "D10" ; +#LOCATE COMP "" SITE "A10" ; +#LOCATE COMP "" SITE "C10" ; +#LOCATE COMP "" SITE "B10" ; +#LOCATE COMP "" SITE "C12" ; +#LOCATE COMP "" SITE "B12" ; +#LOCATE COMP "" SITE "D13" ; +#LOCATE COMP "" SITE "A13" ; +#LOCATE COMP "" SITE "M5" ; # PP1 11 +#LOCATE COMP "" SITE "L5" ; # PP1 13 +#LOCATE COMP "" SITE "K5" ; # PP1 15 +#LOCATE COMP "" SITE "H5" ; # PP1 17 +#LOCATE COMP "" SITE "E8" ; # PP1 19 +#LOCATE COMP "" SITE "E5" ; # PP1 21 +#LOCATE COMP "" SITE "E6" ; # PP1 23 +#LOCATE COMP "" SITE "E7" ; # PP1 25 + + +### USB (FTDI2232HL located on the daughterboard) ### +#LOCATE COMP "TxD" SITE "A14" ; +#IOBUF PORT "TxD" SLEWRATE=FAST ; +#LOCATE COMP "RxD" SITE "B14" ; +#IOBUF PORT "RxD" PULLMODE=UP ; +#LOCATE COMP "USB_DB_RTS" SITE "B13" ; +#IOBUF PORT "USB_DB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_DB_CTS" SITE "C13" ; +#IOBUF PORT "USB_DB_CTS" PULLMODE=UP ; + + + +################ +#### Extras +################ + + +### SD Flash (External SD card) ### +#LOCATE COMP "SD_DETECT" SITE "G12" ; +#IOBUF PORT "SD_DETECT" PULLMODE=UP ; + +#LOCATE COMP "SD_CMD" SITE "C15" ; +#IOBUF PORT "SD_CMD" SLEWRATE=FAST ; +#LOCATE COMP "SD_CLK" SITE "B15" ; +#IOBUF PORT "SD_CLK" SLEWRATE=FAST ; + +#LOCATE COMP "SD_DTA[0]" SITE "B16" ; +##IOBUF PORT "SD_DTA[0]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[1]" SITE "C16" ; +##IOBUF PORT "SD_DTA[1]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[2]" SITE "F12" ; +##IOBUF PORT "SD_DTA[2]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[3]" SITE "C14" ; +##IOBUF PORT "SD_DTA[3]" SLEWRATE=FAST ; + + +### DRAM ### +#LOCATE COMP "DRAM_ADDR[0]" SITE "J15" ; +#IOBUF PORT "DRAM_ADDR[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[1]" SITE "L16" ; +#IOBUF PORT "DRAM_ADDR[1]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[2]" SITE "L15" ; +#IOBUF PORT "DRAM_ADDR[2]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[3]" SITE "K15" ; +#IOBUF PORT "DRAM_ADDR[3]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[4]" SITE "G15" ; +#IOBUF PORT "DRAM_ADDR[4]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[5]" SITE "F15" ; +#IOBUF PORT "DRAM_ADDR[5]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[6]" SITE "F16" ; +#IOBUF PORT "DRAM_ADDR[6]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[7]" SITE "E16" ; +#IOBUF PORT "DRAM_ADDR[7]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[8]" SITE "E15" ; +#IOBUF PORT "DRAM_ADDR[8]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[9]" SITE "G13" ; +#IOBUF PORT "DRAM_ADDR[9]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[10]" SITE "M16" ; +#IOBUF PORT "DRAM_ADDR[10]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[11]" SITE "F13" ; +#IOBUF PORT "DRAM_ADDR[11]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[12]" SITE "D16" ; +#IOBUF PORT "DRAM_ADDR[12]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_BA[0]" SITE "L14" ; +#IOBUF PORT "DRAM_BA[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_BA[1]" SITE "L13" ; +#IOBUF PORT "DRAM_BA[1]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_CLK" SITE "G14" ; +#IOBUF PORT "DRAM_CLK" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_CKE" SITE "G16" ; +#IOBUF PORT "DRAM_CKE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nRAS" SITE "M14" ; +#IOBUF PORT "DRAM_nRAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCAS" SITE "K13" ; +#IOBUF PORT "DRAM_nCAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nWE" SITE "N16" ; +#IOBUF PORT "DRAM_nWE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCS" SITE "M15" ; + +#LOCATE COMP "DRAM_DQ[0]" SITE "P14" ; +#LOCATE COMP "DRAM_DQ[1]" SITE "R15" ; +#LOCATE COMP "DRAM_DQ[2]" SITE "N14" ; +#LOCATE COMP "DRAM_DQ[3]" SITE "R16" ; +#LOCATE COMP "DRAM_DQ[4]" SITE "J14" ; +#LOCATE COMP "DRAM_DQ[5]" SITE "P15" ; +#LOCATE COMP "DRAM_DQ[6]" SITE "K14" ; +#LOCATE COMP "DRAM_DQ[7]" SITE "P16" ; +#LOCATE COMP "DRAM_DQ[8]" SITE "D14" ; +#LOCATE COMP "DRAM_DQ[9]" SITE "H14" ; +#LOCATE COMP "DRAM_DQ[10]" SITE "H12" ; +#LOCATE COMP "DRAM_DQ[11]" SITE "H13" ; +#LOCATE COMP "DRAM_DQ[12]" SITE "E14" ; +#LOCATE COMP "DRAM_DQ[13]" SITE "H15" ; +#LOCATE COMP "DRAM_DQ[14]" SITE "J13" ; +#LOCATE COMP "DRAM_DQ[15]" SITE "J16" ; + +#LOCATE COMP "DRAM_DQM[0]" SITE "M13" ; +#IOBUF PORT "DRAM_DQM[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_DQM[1]" SITE "F14" ; +#IOBUF PORT "DRAM_DQM[1]" SLEWRATE=FAST ; + + + + +### USB (chip located on the motherboard) ### +#LOCATE COMP "USB_MB_TX" SITE "M11" ; +#IOBUF PORT "USB_MB_TX" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_RX" SITE "N12" ; +#IOBUF PORT "USB_MB_RX" PULLMODE=UP ; +#LOCATE COMP "USB_MB_RTS" SITE "N11" ; +#IOBUF PORT "USB_MB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_CTS" SITE "M12" ; +#IOBUF PORT "USB_MB_CTS" PULLMODE=UP ; + + +### PMOD1 ### +#LOCATE COMP "dbg_leds[16]" SITE "P1" ; +#LOCATE COMP "dbg_leds[17]" SITE "N4" ; +#LOCATE COMP "dbg_leds[18]" SITE "P2" ; +#LOCATE COMP "dbg_leds[19]" SITE "P5" ; +#LOCATE COMP "dbg_leds[20]" SITE "R1" ; +#LOCATE COMP "dbg_leds[21]" SITE "N5" ; +#LOCATE COMP "dbg_leds[22]" SITE "R2" ; +#LOCATE COMP "dbg_leds[23]" SITE "N6" ; + + +### PMOD2 ### +#LOCATE COMP "dbg_leds[24]" SITE "R3" ; +#LOCATE COMP "dbg_leds[25]" SITE "P11" ; +#LOCATE COMP "dbg_leds[26]" SITE "P12" ; +#LOCATE COMP "dbg_leds[27]" SITE "T3" ; +#LOCATE COMP "dbg_leds[28]" SITE "R4" ; +#LOCATE COMP "dbg_leds[29]" SITE "R12" ; +#LOCATE COMP "dbg_leds[30]" SITE "T13" ; +#LOCATE COMP "dbg_leds[31]" SITE "R5" ; + + +### PMOD3 ### +#LOCATE COMP "dbg_leds[8]" SITE "B2" ; +#LOCATE COMP "dbg_leds[9]" SITE "B3" ; +#LOCATE COMP "dbg_leds[10]" SITE "A4" ; +#LOCATE COMP "dbg_leds[11]" SITE "D4" ; +#LOCATE COMP "dbg_leds[12]" SITE "A2" ; +#LOCATE COMP "dbg_leds[13]" SITE "B4" ; +#LOCATE COMP "dbg_leds[14]" SITE "C3" ; +#LOCATE COMP "dbg_leds[15]" SITE "C4" ; + + +### PMOD4 ### +#LOCATE COMP "dbg_leds[0]" SITE "J4" ; +#LOCATE COMP "dbg_leds[1]" SITE "J5" ; +#LOCATE COMP "dbg_leds[2]" SITE "H4" ; +#LOCATE COMP "dbg_leds[3]" SITE "E4" ; +#LOCATE COMP "dbg_leds[4]" SITE "J3" ; +#LOCATE COMP "dbg_leds[5]" SITE "H3" ; +#LOCATE COMP "dbg_leds[6]" SITE "E3" ; +#LOCATE COMP "dbg_leds[7]" SITE "D3" ; + + +### Ethernet ### +#LOCATE COMP "ETH_CLK_EN" SITE "B1" ; +#LOCATE COMP "ETH_nRESET" SITE "C2" ; + +#LOCATE COMP "ETH_nLED_Y" SITE "F1" ; +#LOCATE COMP "ETH_nLED_G" SITE "G2" ; + +#LOCATE COMP "ETH_MDC" SITE "J1" ; +#LOCATE COMP "ETH_MDIO" SITE "H2" ; +#IOBUF PORT "ETH_MDIO" OPENDRAIN=ON SLEWRATE=FAST ; +#LOCATE COMP "ETH_MDINT" SITE "G1" ; +#IOBUF PORT "ETH_MDINT" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_REF_CLK" SITE "P3" ; + +#LOCATE COMP "ETH_TX_CLK" SITE "M4" ; +#IOBUF PORT "ETH_TX_CLK" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TX_CTL" SITE "N3" ; +#IOBUF PORT "ETH_TX_CTL" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[0]" SITE "M3" ; +#IOBUF PORT "ETH_TXD[0]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[1]" SITE "L4" ; +#IOBUF PORT "ETH_TXD[1]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[2]" SITE "K4" ; +#IOBUF PORT "ETH_TXD[2]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[3]" SITE "K3" ; +#IOBUF PORT "ETH_TXD[3]" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_RX_CLK" SITE "K1" ; +#LOCATE COMP "ETH_RX_CTL" SITE "K2" ; +#LOCATE COMP "ETH_RXD[0]" SITE "L1" ; +#LOCATE COMP "ETH_RXD[1]" SITE "L2" ; +#LOCATE COMP "ETH_RXD[2]" SITE "M1" ; +#LOCATE COMP "ETH_RXD[3]" SITE "M2" ; + + +### Extras ### +#LOCATE COMP "EXT[1]" SITE "P13" ; +#LOCATE COMP "EXT[2]" SITE "R13" ; +#LOCATE COMP "EXT[3]" SITE "A3" ; +#LOCATE COMP "EXT[4]" SITE "A5" ; +#LOCATE COMP "EXT[5]" SITE "B5" ; +#LOCATE COMP "EXT[6]" SITE "C5" ; +#LOCATE COMP "EXT[7]" SITE "C6" ; +#LOCATE COMP "EXT[8]" SITE "D5" ; +#LOCATE COMP "EXT[9]" SITE "D6" ; +#LOCATE COMP "EXT[10]" SITE "A11" ; +#LOCATE COMP "EXT[11]" SITE "A12" ; +#LOCATE COMP "EXT[12]" SITE "B8" ; +#LOCATE COMP "EXT[13]" SITE "B9" ; +#LOCATE COMP "EXT[14]" SITE "B11" ; +#LOCATE COMP "EXT[15]" SITE "C9" ; +#LOCATE COMP "EXT[16]" SITE "C11" ; +#LOCATE COMP "EXT[17]" SITE "D11" ; +#LOCATE COMP "EXT[18]" SITE "D12" ; +#LOCATE COMP "EXT[19]" SITE "E10" ; +#LOCATE COMP "EXT[20]" SITE "E11" ; +#LOCATE COMP "EXT[21]" SITE "E12" ; +#LOCATE COMP "EXT[22]" SITE "L3" ; +#LOCATE COMP "EXT[23]" SITE "M6" ; +#LOCATE COMP "EXT[24]" SITE "N1" ; +#LOCATE COMP "EXT[25]" SITE "P4" ; +#LOCATE COMP "EXT[26]" SITE "P6" ; +#LOCATE COMP "EXT[27]" SITE "T2" ; +#LOCATE COMP "EXT[28]" SITE "T4" ; +#LOCATE COMP "EXT[29]" SITE "E2" ; +#LOCATE COMP "EXT[30]" SITE "F2" ; +#LOCATE COMP "EXT[31]" SITE "F5" ; +#LOCATE COMP "EXT[32]" SITE "G4" ; +#LOCATE COMP "EXT[33]" SITE "G5" ; +#LOCATE COMP "EXT[34]" SITE "J2" ; diff --git a/04-Lissajous/Board/concat/lissajous.ucf b/04-Lissajous/Board/concat/lissajous.ucf new file mode 100644 index 0000000..b145465 --- /dev/null +++ b/04-Lissajous/Board/concat/lissajous.ucf @@ -0,0 +1,19 @@ +#------------------------------------------------------------------------------- +# Clock and reset +# +NET "clock" LOC = "A10"; +NET "reset_N" LOC = "D3" | PULLUP; + +#------------------------------------------------------------------------------- +# Analog outputs +# +NET "xOut" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +NET "yOut" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +#NET "xOut" LOC = "G4" ; +#NET "yOut" LOC = "G5" ; + +#------------------------------------------------------------------------------- +# Trigger output +# +NET "triggerOut" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +#NET "triggerOut" LOC = "D2" ; diff --git a/04-Lissajous/Board/concat/lissajous.vhd b/04-Lissajous/Board/concat/lissajous.vhd new file mode 100644 index 0000000..02ed33b --- /dev/null +++ b/04-Lissajous/Board/concat/lissajous.vhd @@ -0,0 +1,1585 @@ +-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:49 01.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY lissajousGenerator_circuit_EBS3 IS + PORT( + clock : IN std_ulogic; + reset_N : IN std_ulogic; + triggerOut : OUT std_ulogic; + xOut : OUT std_ulogic; + yOut : OUT std_ulogic + ); + +-- Declarations + +END lissajousGenerator_circuit_EBS3 ; + + + + + +-- VHDL Entity Board.DFF.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:05 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY DFF IS + PORT( + CLK : IN std_uLogic; + CLR : IN std_uLogic; + D : IN std_uLogic; + Q : OUT std_uLogic + ); + +-- Declarations + +END DFF ; + + + + + +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Board.inverterIn.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY inverterIn IS + PORT( + in1 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END inverterIn ; + + + + + +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Lissajous.lissajousGenerator.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:53 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY lissajousGenerator IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + triggerOut : OUT std_ulogic; + xOut : OUT std_ulogic; + yOut : OUT std_ulogic + ); + +-- Declarations + +END lissajousGenerator ; + + + + + +-- VHDL Entity DigitalToAnalogConverter.DAC.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:06:08 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY DAC IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + serialOut : OUT std_ulogic; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END DAC ; + + + + + +ARCHITECTURE masterVersion OF DAC IS + + signal parallelIn1: unsigned(parallelIn'range); + signal integrator: unsigned(parallelIn'high+1 downto 0); + signal quantized: std_ulogic; + +BEGIN + +-- parallelIn1 <= parallelIn; + parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2); + + integrate: process(reset, clock) + begin + if reset = '1' then + integrator <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '0' then + integrator <= integrator + parallelIn1; + else + integrator <= integrator + parallelIn1 - 2**parallelIn'length; + end if; + end if; + end process integrate; + + quantized <= integrator(integrator'high); + + serialOut <= quantized; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:40 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineGen IS + GENERIC( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineGen ; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:20 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCoefficients IS + GENERIC( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + +-- Declarations + +END interpolatorCoefficients ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCoefficients IS +BEGIN + + calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4) + begin + if interpolateLinear = '1' then + a <= (others => '0'); + b <= (others => '0'); + c <= resize(2*sample3, c'length) + - resize(2*sample2, c'length); + d <= resize( sample2, d'length); + else + a <= resize( sample4, a'length) + - resize(3*sample3, a'length) + + resize(3*sample2, a'length) + - resize( sample1, a'length); + b <= resize(2*sample1, b'length) + - resize(5*sample2, b'length) + + resize(4*sample3, b'length) + - resize( sample4, b'length); + c <= resize( sample3, c'length) + - resize( sample1, c'length); + d <= resize( sample2, d'length); + end if; + end process calcCoeffs; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity WaveformGenerator.sawtoothGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothGen IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END sawtoothGen ; + + + + + +ARCHITECTURE masterVersion OF sawtoothGen IS + + signal counter: unsigned(sawtooth'range); + +begin + + count: process(reset, clock) + begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter + step; + end if; + end if; + end process count; + + sawtooth <= counter; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:24 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorShiftRegister IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + shiftSamples : IN std_ulogic; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END interpolatorShiftRegister ; + + + + + +ARCHITECTURE masterVersion OF interpolatorShiftRegister IS + + -- signal sample4_int: signed(sampleIn'range); + -- signal sample3_int: signed(sampleIn'range); + -- signal sample2_int: signed(sampleIn'range); + -- signal sample1_int: signed(sampleIn'range); + + type samplesArray is array(3 downto 0) of signed(sampleIn'range); + signal samples: samplesArray; + +begin + + shiftThem: process(reset, clock) + begin + if reset = '1' then + samples <= (others=>(others=>'0')); + -- sample1_int <= (others => '0'); + -- sample2_int <= (others => '0'); + -- sample3_int <= (others => '0'); + -- sample4_int <= (others => '0'); + elsif rising_edge(clock) then + if shiftSamples = '1' then + -- sample1_int <= sample2_int; + -- sample2_int <= sample3_int; + -- sample3_int <= sample4_int; + -- sample4_int <= sampleIn; + samples(0) <= samples(1); + samples(1) <= samples(2); + samples(2) <= samples(3); + samples(3) <= sampleIn; + end if; + end if; + end process shiftThem; + + sample4 <= samples(3); + sample3 <= samples(2); + sample2 <= samples(1); + sample1 <= samples(0); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.sineTable.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:46 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sineTable IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sineTable ; + + + + + +ARCHITECTURE masterVersion OF sineTable IS + + signal changeSign : std_uLogic; + signal flipPhase : std_uLogic; + signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0); + signal phaseTableAddress2 : unsigned(phaseTableAddress1'range); + signal quarterSine : signed(sine'range); + + signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine + +begin + + changeSign <= phase(phase'high); + flipPhase <= phase(phase'high-1); + + phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1) + begin + if (flipPhase xor shiftPhase) = '0' then + phaseTableAddress2 <= phaseTableAddress1; + else + phaseTableAddress2 <= 0 - phaseTableAddress1; + end if; + end process checkPhase; + + + quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if (flipPhase xor shiftPhase) = '0' then + quarterSine <= to_signed(16#0000#, quarterSine'length); + else + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTable; + + checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine) + begin + if (changeSign xor (flipPhase and shiftPhase)) = '0' then + sine <= quarterSine; + else + sine <= 0 - quarterSine; + end if; + end process checkSign; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.resizer.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:36 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY resizer IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END resizer ; + + + + + +ARCHITECTURE masterVersion OF resizer IS + +BEGIN + + outGtIn: if resizeOut'length > resizeIn'length generate + begin + resizeOut <= shift_left( + resize( + resizeIn, + resizeOut'length + ), + resizeOut'length-resizeIn'length + ); + end generate outGtIn; + + outEqIn: if resizeOut'length = resizeIn'length generate + begin + resizeOut <= resizeIn; + end generate outEqIn; + + outLtIn: if resizeOut'length < resizeIn'length generate + begin + resizeOut <= resize( + shift_right( + resizeIn, + resizeIn'length-resizeOut'length + ), + resizeOut'length + ); + end generate outLtIn; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCalculatePolynom IS + GENERIC( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + restartPolynom : IN std_ulogic; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorCalculatePolynom ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS + + constant additionalBitNb: positive := 1; + constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1 + + additionalBitNb; + signal x: signed(internalsBitNb-1 downto 0); + signal u: signed(internalsBitNb-1 downto 0); + signal v: signed(internalsBitNb-1 downto 0); + signal w: signed(internalsBitNb-1 downto 0); + +BEGIN + + iterativePolynom: process(reset, clock) + begin + if reset = '1' then + x <= (others => '0'); + u <= (others => '0'); + v <= (others => '0'); + w <= (others => '0'); + sampleOut <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if restartPolynom = '1' then + x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb); + u <= resize(a, u'length) + + shift_left(resize(b, u'length), oversamplingBitNb) + + shift_left(resize(c, u'length), 2*oversamplingBitNb); + v <= resize(6*a, v'length) + + shift_left(resize(2*b, v'length), oversamplingBitNb); + w <= resize(6*a, w'length); + sampleOut <= resize(d, sampleOut'length); + else + x <= x + u; + u <= u + v; + v <= v + w; + sampleOut <= resize( + shift_right(x, 3*oversamplingBitNb+1), sampleOut'length + ); + -- limit overflow + if x(x'high downto x'high-additionalBitNb) = "01" then + sampleOut <= not shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + -- limit underflow + if x(x'high downto x'high-additionalBitNb) = "10" then + sampleOut <= shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + end if; + end if; + end if; + end process iterativePolynom; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToSquare IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToSquare ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToSquare IS +BEGIN + + square <= (others => sawtooth(sawtooth'high)); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothToTriangle IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sawtoothToTriangle ; + + + + + +ARCHITECTURE masterVersion OF sawtoothToTriangle IS + + signal MSB: std_uLogic; + signal triangleInt: unsigned(triangle'range); + +begin + + MSB <= sawtooth(sawtooth'high); + + foldDown: process(MSB, sawtooth) + begin + if MSB = '0' then + triangleInt <= sawtooth; + else + triangleInt <= not sawtooth; + end if; + end process foldDown; + + triangle <= triangleInt(triangleInt'high-1 downto 0) & '0'; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:28 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorTrigger IS + GENERIC( + counterBitNb : positive := 4 + ); + PORT( + triggerOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorTrigger ; + + + + + +ARCHITECTURE masterVersion OF interpolatorTrigger IS + + signal triggerCounter: unsigned(counterBitNb-1 downto 0); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + triggerCounter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + triggerCounter <= triggerCounter + 1; + end if; + end if; + end process count; + + trig: process(triggerCounter, en) + begin + if triggerCounter = 0 then + triggerOut <= en; + else + triggerOut <= '0'; + end if; + end process trig; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:32 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY offsetToUnsigned IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END offsetToUnsigned ; + + + + + +ARCHITECTURE masterVersion OF offsetToUnsigned IS + +BEGIN + + unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0)); + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SplineInterpolator.sineGen.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:42:04 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY SplineInterpolator; +-- LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF sineGen IS + + -- Architecture declarations + constant tableAddressBitNb : positive := 3; + constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb; + constant coeffBitNb : positive := signalBitNb+4; + + -- Internal signal declarations + SIGNAL a : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL b : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL c : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL d : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_ulogic; + SIGNAL newPolynom : std_ulogic; + SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT interpolatorCalculatePolynom + GENERIC ( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + restartPolynom : IN std_ulogic ; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCoefficients + GENERIC ( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT ( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorShiftRegister + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + shiftSamples : IN std_ulogic ; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT interpolatorTrigger + GENERIC ( + counterBitNb : positive := 4 + ); + PORT ( + triggerOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT offsetToUnsigned + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT resizer + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16 + ); + PORT ( + resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0); + resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sineTable + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT ( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT sawtoothToSquare + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + square : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothToTriangle + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + triangle : OUT unsigned (bitNb-1 DOWNTO 0); + sawtooth : IN unsigned (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom; +-- FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients; +-- FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister; +-- FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger; +-- FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned; +-- FOR ALL : resizer USE ENTITY SplineInterpolator.resizer; +-- FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; +-- FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare; +-- FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle; +-- FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + logic1 <= '1'; + + -- HDL Embedded Text Block 3 eb3 + logic0 <= '0'; + + + -- Instance port mappings. + I_spline : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom, + d => d, + sampleOut => sineSigned, + c => c, + b => b, + a => a, + en => logic1 + ); + I_coeffs : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4, + a => a, + b => b, + c => c, + d => d, + interpolateLinear => logic0 + ); + I_shReg : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom, + sampleIn => sineSamples, + sample1 => sample1, + sample2 => sample2, + sample3 => sample3, + sample4 => sample4 + ); + I_trig : interpolatorTrigger + GENERIC MAP ( + counterBitNb => sampleCountBitNb + ) + PORT MAP ( + triggerOut => newPolynom, + clock => clock, + reset => reset, + en => logic1 + ); + I_unsigned : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => sine, + signedIn => sineSigned + ); + I_size : resizer + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb + ) + PORT MAP ( + resizeOut => sawtooth_internal, + resizeIn => phase + ); + I_sin : sineTable + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb, + tableAddressBitNb => tableAddressBitNb + ) + PORT MAP ( + sine => sineSamples, + phase => phase + ); + I_saw : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => phase, + clock => clock, + reset => reset, + step => step, + en => logic1 + ); + I_square : sawtoothToSquare + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + square => square, + sawtooth => sawtooth_internal + ); + I_tri : sawtoothToTriangle + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + triangle => triangle, + sawtooth => sawtooth_internal + ); + + -- Implicit buffered output assignments + sawtooth <= sawtooth_internal; + +END struct; + + + + +-- +-- VHDL Architecture Lissajous.lissajousGenerator.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:47:09 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY DigitalToAnalogConverter; +-- LIBRARY SplineInterpolator; + +ARCHITECTURE struct OF lissajousGenerator IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT DAC + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + serialOut : OUT std_ulogic ; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT sineGen + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 10 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (phaseBitNb-1 DOWNTO 0); + sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0); + sine : OUT unsigned (signalBitNb-1 DOWNTO 0); + square : OUT unsigned (signalBitNb-1 DOWNTO 0); + triangle : OUT unsigned (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC; +-- FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + triggerOut <= squareY(squareY'high); + + -- HDL Embedded Text Block 2 eb2 + stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length); + + -- HDL Embedded Text Block 3 eb3 + stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length); + + + -- Instance port mappings. + I_dacX : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => xOut, + parallelIn => sineX, + clock => clock, + reset => reset + ); + I_dacY : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => yOut, + parallelIn => sineY, + clock => clock, + reset => reset + ); + I_sinX : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepXUnsigned, + sawtooth => OPEN, + sine => sineX, + square => OPEN, + triangle => OPEN + ); + I_sinY : sineGen + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + step => stepYUnsigned, + sawtooth => OPEN, + sine => sineY, + square => squareY, + triangle => OPEN + ); + +END struct; + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- +-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:49 01.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Board; +-- LIBRARY Lattice; +-- LIBRARY Lissajous; + +ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant phaseBitNb: positive := 17; + constant stepX: positive := 3; + constant stepY: positive := 4; + + -- Internal signal declarations + SIGNAL clkSys : std_ulogic; + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_N : std_ulogic; + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT lissajousGenerator + GENERIC ( + signalBitNb : positive := 16; + phaseBitNb : positive := 16; + stepX : positive := 1; + stepY : positive := 1 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + triggerOut : OUT std_ulogic ; + xOut : OUT std_ulogic ; + yOut : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DFF USE ENTITY Board.DFF; +-- FOR ALL : inverterIn USE ENTITY Board.inverterIn; +-- FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator; +-- FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 5 eb5 + logic1 <= '1'; + + -- HDL Embedded Text Block 6 eb6 + logic0 <= '0'; + + + -- Instance port mappings. + I_dff : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSynch_N + ); + I_inv1 : inverterIn + PORT MAP ( + in1 => reset_N, + out1 => reset + ); + I_inv2 : inverterIn + PORT MAP ( + in1 => resetSynch_N, + out1 => resetSynch + ); + U_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clkSys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_main : lissajousGenerator + GENERIC MAP ( + signalBitNb => signalBitNb, + phaseBitNb => phaseBitNb, + stepX => stepX, + stepY => stepY + ) + PORT MAP ( + clock => clkSys, + reset => resetSynch, + triggerOut => triggerOut, + xOut => xOut, + yOut => yOut + ); + +END masterVersion; + + + + diff --git a/04-Lissajous/Board/diamond/lissajous.bit b/04-Lissajous/Board/diamond/lissajous.bit new file mode 100644 index 0000000..085c234 Binary files /dev/null and b/04-Lissajous/Board/diamond/lissajous.bit differ diff --git a/04-Lissajous/Board/diamond/lissajous.ldf b/04-Lissajous/Board/diamond/lissajous.ldf new file mode 100644 index 0000000..f1ae61d --- /dev/null +++ b/04-Lissajous/Board/diamond/lissajous.ldf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/04-Lissajous/Board/diamond/programmer.xcf b/04-Lissajous/Board/diamond/programmer.xcf new file mode 100644 index 0000000..468a2da --- /dev/null +++ b/04-Lissajous/Board/diamond/programmer.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Renesas + ECP5U + LFE5U-25F + All + LFE5U-25F + + 8 + 11111111 + 1 + 0 + + + 04/11/23 16:14:28 + 0xA4B0 + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 4 + + + USB2 + FTUSB-0 + LFE5U-25F A Location 0000 Serial 018VFVT3A + + diff --git a/04-Lissajous/Board/diamond/reveal_analyze.rva b/04-Lissajous/Board/diamond/reveal_analyze.rva new file mode 100644 index 0000000..4249e0e --- /dev/null +++ b/04-Lissajous/Board/diamond/reveal_analyze.rva @@ -0,0 +1,638 @@ + + + lun. 6. mars 14:29:10 2023 + + + + + + + + + + + + 1 + + 0 + 1. LFE5U-25F + 0x41111043 + true + false + + 8 + reveal_config.rvl + reveal_config.rvs + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/04-Lissajous/Board/diamond/reveal_config.rvl b/04-Lissajous/Board/diamond/reveal_config.rvl new file mode 100644 index 0000000..28d2f1c --- /dev/null +++ b/04-Lissajous/Board/diamond/reveal_config.rvl @@ -0,0 +1,662 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/04-Lissajous/Board/diamond/strategy.sty b/04-Lissajous/Board/diamond/strategy.sty new file mode 100644 index 0000000..a2b5a4a --- /dev/null +++ b/04-Lissajous/Board/diamond/strategy.sty @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/04-Lissajous/Board/hdl/DFF_sim.vhd b/04-Lissajous/Board/hdl/DFF_sim.vhd new file mode 100644 index 0000000..cf8868a --- /dev/null +++ b/04-Lissajous/Board/hdl/DFF_sim.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/04-Lissajous/Board/hdl/buff_sim.vhd b/04-Lissajous/Board/hdl/buff_sim.vhd new file mode 100644 index 0000000..8ad27be --- /dev/null +++ b/04-Lissajous/Board/hdl/buff_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF buff IS +BEGIN + + out1 <= in1; + +END ARCHITECTURE sim; + diff --git a/04-Lissajous/Board/hdl/inverterIn_sim.vhd b/04-Lissajous/Board/hdl/inverterIn_sim.vhd new file mode 100644 index 0000000..fb039ac --- /dev/null +++ b/04-Lissajous/Board/hdl/inverterIn_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/04-Lissajous/Board/hdl/inverter_sim.vhd b/04-Lissajous/Board/hdl/inverter_sim.vhd new file mode 100644 index 0000000..ca5b6b5 --- /dev/null +++ b/04-Lissajous/Board/hdl/inverter_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverter IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhd._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhd._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_entity.vhg._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhd._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhg._fpf b/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Board/hds/@d@f@f/symbol.sb b/04-Lissajous/Board/hds/@d@f@f/symbol.sb new file mode 100644 index 0000000..555b689 --- /dev/null +++ b/04-Lissajous/Board/hds/@d@f@f/symbol.sb @@ -0,0 +1,1211 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2004,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 157,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +decl (Decl +n "CLR" +t "std_uLogic" +o 2 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a/04-Lissajous/Board/ise/lissajous.xise b/04-Lissajous/Board/ise/lissajous.xise new file mode 100644 index 0000000..076ab77 --- /dev/null +++ b/04-Lissajous/Board/ise/lissajous.xise @@ -0,0 +1,331 @@ + + + +
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b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhg._fpf b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhd._fpf b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhg._fpf b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous/hds/.hdlsidedata/_lissajousgenerator_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous/hds/_lissajousgenerator._epf b/04-Lissajous/Lissajous/hds/_lissajousgenerator._epf new file mode 100644 index 0000000..aa82986 --- /dev/null +++ b/04-Lissajous/Lissajous/hds/_lissajousgenerator._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lissajous@generator/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/04-Lissajous/Lissajous/hds/lissajous@generator/struct.bd b/04-Lissajous/Lissajous/hds/lissajous@generator/struct.bd new file mode 100644 index 0000000..997ee19 --- /dev/null +++ b/04-Lissajous/Lissajous/hds/lissajous@generator/struct.bd @@ -0,0 +1,4708 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_sinY" +duLibraryName "SplineInterpolator" +duName "sineGen" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "phaseBitNb" +type "positive" +value "phaseBitNb" +) +] +mwi 0 +uid 2053,0 +) +(Instance +name "I_sinX" +duLibraryName "SplineInterpolator" +duName "sineGen" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "phaseBitNb" +type "positive" +value "phaseBitNb" +) +] +mwi 0 +uid 2090,0 +) +(Instance +name "I_dacY" +duLibraryName "DigitalToAnalogConverter" +duName "DAC" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +mwi 0 +uid 2162,0 +) +(Instance +name "I_dacX" +duLibraryName "DigitalToAnalogConverter" +duName "DAC" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +mwi 0 +uid 2187,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +(EmbeddedInstance +name "eb2" +number "2" +) +(EmbeddedInstance +name "eb3" +number "3" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajous@generator\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajous@generator\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajous@generator" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous\\hds\\lissajousGenerator" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "lissajousGenerator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value 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"courier,8,1" +) +xt "0,9000,7500,9900" +st "Internal User:" +blo "0,9700" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,16200,2000,16200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,9000,0,9000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 507,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd b/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd new file mode 100644 index 0000000..64427cf --- /dev/null +++ b/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd @@ -0,0 +1,13 @@ +ARCHITECTURE test OF lissajousGenerator_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + reset <= '1', '0' after 2*clockPeriod; + +END ARCHITECTURE test; diff --git a/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousGenerator_tester_test.vhd._fpf b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousGenerator_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousGenerator_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhd._fpf b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhg._fpf b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhd._fpf b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhg._fpf b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_test_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhd._fpf b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhg._fpf b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/.hdlsidedata/_lissajousgenerator_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_test._epf b/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_test._epf new file mode 100644 index 0000000..66cbfb5 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_test._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lissajous@generator_test/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_tester._epf b/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_tester._epf new file mode 100644 index 0000000..335f3fd --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/_lissajousgenerator_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom lissajousGenerator_tester_test.vhd diff --git a/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/_struct.bd._fpf b/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/_struct.bd._fpf new file mode 100755 index 0000000..30e9f19 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/_struct.bd._fpf @@ -0,0 +1,9 @@ +ARCHITECTURES list { + {lissajousgenerator_test struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/lissajousGenerator.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ns TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseCLI 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/struct.bd b/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/struct.bd new file mode 100644 index 0000000..11d0420 --- /dev/null +++ b/04-Lissajous/Lissajous_test/hds/lissajous@generator_test/struct.bd @@ -0,0 +1,3941 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "Lissajous_test" +duName "lissajousGenerator_tester" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +mwi 0 +uid 421,0 +) +(Instance +name "I_DUT" +duLibraryName "Lissajous" +duName "lissajousGenerator" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "phaseBitNb" +type "positive" +value "phaseBitNb" +) +(GiElement +name "stepX" +type "positive" +value "stepX" +) +(GiElement +name "stepY" +type "positive" +value "stepY" +) +] +mwi 0 +uid 1594,0 +) +(Instance +name "I_filtX" +duLibraryName "WaveformGenerator" +duName "lowpass" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "shiftBitNb" +type "positive" +value "lowpassShiftBitNb" +) +] +mwi 0 +uid 1612,0 +) +(Instance +name "I_filty" +duLibraryName "WaveformGenerator" +duName "lowpass" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "shiftBitNb" +type "positive" +value "lowpassShiftBitNb" +) +] +mwi 0 +uid 1699,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_test" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "lissajousGenerator_test" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "14:48:46" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Lissajous_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Lissajous_test/concat" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Lissajous_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "lissajousGenerator_test" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_test\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_AsmPath" +value "$HEI_LIBS_DIR/NanoBlaze/hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "14:48:46" +) +(vvPair +variable "unit" +value "lissajousGenerator_test" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 153,0 +optionalChildren [ +*1 (Grouping +uid 110,0 +optionalChildren [ +*2 (CommentText +uid 112,0 +shape (Rectangle +uid 113,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,65000,79000,66000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 114,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,65500,62200,65500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +uid 115,0 +shape (Rectangle +uid 116,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "79000,61000,83000,62000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 117,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "79200,61500,79200,61500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 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+portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "arial,8,0" +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *93 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,7600,44400,8600" +st "User:" +blo "42000,8400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +) +xt "44000,8600,44000,8600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 697,0 +activeModelName "Symbol:GEN" +) diff --git a/04-Lissajous/Prefs/hds.hdp b/04-Lissajous/Prefs/hds.hdp new file mode 100644 index 0000000..9eb87ee --- /dev/null +++ b/04-Lissajous/Prefs/hds.hdp @@ -0,0 +1,46 @@ +[Concat] +Board = $HDS_PROJECT_DIR/../Board/concat +[ModelSim] +Board = $SCRATCH_DIR/Board +DigitalToAnalogConverter = $SCRATCH_DIR/DigitalToAnalogConverter +DigitalToAnalogConverter_test = $SCRATCH_DIR/DigitalToAnalogConverter_test +Lattice = $SCRATCH_DIR/Lattice +Lissajous = $SCRATCH_DIR/Lissajous +Lissajous_test = $SCRATCH_DIR/Lissajous_test +SplineInterpolator = $SCRATCH_DIR/SplineInterpolator +SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +Board = $HDS_PROJECT_DIR/../Board/hdl +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hdl +Lissajous = $HDS_PROJECT_DIR/../Lissajous/hdl +Lissajous_test = $HDS_PROJECT_DIR/../Lissajous_test/hdl +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hdl +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl +[hds] +Board = $HDS_PROJECT_DIR/../Board/hds +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds +ieee = $HDS_HOME/hdl_libs/ieee/hds +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hds +Lissajous = $HDS_PROJECT_DIR/../Lissajous/hds +Lissajous_test = $HDS_PROJECT_DIR/../Lissajous_test/hds +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hds +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hds +std = $HDS_HOME/hdl_libs/std/hds +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds +[hds_settings] +design_root = Board.lissajousGenerator_circuit_EBS3(masterVersion)lissajous@generator_circuit_@e@b@s3/master@version.bd +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/04-Lissajous/Prefs/hds_team/shared.hdp b/04-Lissajous/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/04-Lissajous/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/04-Lissajous/Prefs/hds_team/v2018.1/hds_team_prefs b/04-Lissajous/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/04-Lissajous/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/04-Lissajous/Prefs/hds_team/v2018.1/title_block.tmpl b/04-Lissajous/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/04-Lissajous/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/04-Lissajous/Prefs/hds_team/v2019.2/hds_team_prefs b/04-Lissajous/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/04-Lissajous/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/04-Lissajous/Prefs/hds_team/v2019.2/title_block.tmpl b/04-Lissajous/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/04-Lissajous/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/04-Lissajous/Prefs/hds_team/v2019.3/hds_team_prefs b/04-Lissajous/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/04-Lissajous/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/04-Lissajous/Prefs/hds_team/v2019.3/title_block.tmpl b/04-Lissajous/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/04-Lissajous/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/04-Lissajous/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..832b396 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6075 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Sublime" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Favorites/ElN_local/Labs/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs_SI/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/04-Lissajous/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/SEm_labs/04-Lissajous/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "$HDS_TEAM_VER/title_block.tmpl" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "courier,8,1" +) +teamPrefsPath "" +remoteSimPath "$HDS_TEAM_VER/remote" +mwMVL4 1 +mwVerilogUseSynthesisPragmas 0 +mwVhdlUseBusSlicesChkBox 0 +mwVerilogUseBusSlicesChkBox 0 +vmCheckInDesc "" +userVariables [ +(pair +first "concat_file" +second "concatenated" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +] +defaultCategoryTemplates [ +1 +"architecture.vhd" +] +defaultCategoryTemplatesPrefs [ +1 +0 +] +tasksOrder [ +"USER:Generate" +"USER:ModelSim Compile" +"USER:ModelSim Simulate" +"USER:ModelSim Flow" +"USER:Prepare for Synthesis" +"USER:Xilinx Project Navigator" +] +tasksToolbarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +"\"USER:Prepare for Synthesis\"" +"\"USER:Xilinx Project Navigator\"" +] +tasksMenubarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +] +tasksShortcutbarOrder [ +"Setup DesignChecker" +"\"USER:ModelSim Compile\"" +"\"USER:ModelSim Flow\"" +"\"USER:ModelSim Simulate\"" +"USER:Generate" +"\"USER:Prepare for Synthesis\"" +] +taskPreferences [ +(TaskPref +taskName "\"USER:Actel Place and Route\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera MegaWizard\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera SOPC Builder\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:C/C++ Wrapper Generator\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:DesignChecker Flow\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "true" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "true" +) +] +) +(TaskPref +taskName "\"USER:DesignChecker Flow\" USER:DesignChecker" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:DesignChecker Flow\" USER:Generate" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:FPGA Library Compile\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:FPGA Technology Setup\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:I/O Design Flow\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:I/O 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+lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "courier,8,1" +) +cptPortFontVaSet (VaSet +font "courier,8,0" +) +genericInterfaceFontVaSet (VaSet +font "courier,8,0" +) +portRowVaSet (VaSet +vasetType 4 +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..ef38408 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/chronometer.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/hds_user_prefs b/04-Lissajous/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pcf" +Description "Xilinx Place and Route Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ucf" +Description "Xilinx User Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncd" +Description "Xilinx Floorplanner File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncd.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bld" +Description "Xilinx NGDBuild Log" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bit" +Description "Xilinx Bit File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "bin" +Description "Xilinx Binary Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbt" +Description "Xilinx ASCII Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "jed" +Description "Xilinx Jedec Bit Map File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ngc" +Description "Xilinx Netlist File" +Bitmap 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"Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xrf" +Description "Cross Reference File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\text.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "pof" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "rbf" +Description "Quartus Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "ttf" +Description "Quartus Text Tabular Format Programming File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\quartus_programmer.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pdf" +Description "Adobe Acrobat Pdf" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pdf.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "doc" +Description "Microsoft Word Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\word.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "xls" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "tsv" +Description "Microsoft Excel Document" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\excel.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "csv" +Description "Microsoft Excel Document" +Bitmap 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+Extension "ipxact" +Description "IP-XACT file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "css" +Description "HTML style sheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cssFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "gif" +Description "GIF image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\gifFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "jpg" +Description "JPG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jpgFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "png" +Description "PNG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pngFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "svap" +Description "SVAssistant project file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\svapFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "Open" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +(ActionState +Name "View" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +] +) +] +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l)" +) +(pair +first "Sublime Text" +second "sublime_text.exe \"%(p)\" -n%(l)" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l) -ro" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Notepad++" +win32DefaultViewer "Notepad++" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +defaultLanguage 11 +defaultVhdlDialect 11 +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 4 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "$TEMP" +projectPaths [ +"hds.hdp" +"D:\\Labs\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\Users\\oliver.gubler\\eda\\VHDL\\labs\\ELN_cursor\\Prefs\\hds.hdp" +"R:\\SYND\\Ele_2131\\ELN\\Labs\\Cursor\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\work\\git\\Education\\Projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\eln_labs.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +" +defaultVerilogPackages "" +defaultFont "Verdana,9,0" +tableFont "Tahoma,10,0" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +printerName "FinePrint" +pageSizes [ +(PageSizeInfo +name "Letter" +width 783 +height 1013 +) +(PageSizeInfo +name "Letter Small" +type 2 +width 783 +height 1013 +) +(PageSizeInfo +name "Tabloid" +type 3 +width 1013 +height 1566 +) +(PageSizeInfo +name "Ledger" +type 4 +width 1013 +height 1566 +) +(PageSizeInfo +name "Legal" +type 5 +width 783 +height 1290 +) +(PageSizeInfo +name "Statement" +type 6 +width 506 +height 783 +) +(PageSizeInfo +name "Executive" +type 7 +width 667 +height 967 +) +(PageSizeInfo +name "A3" +type 8 +width 1077 +height 1523 +) +(PageSizeInfo +name "A4" +type 9 +width 761 +height 1077 +) +(PageSizeInfo +name "A4 Small" +type 10 +width 761 +height 1077 +) +(PageSizeInfo +name "A5" +type 11 +width 536 +height 761 +) +(PageSizeInfo +name "B4 (JIS)" +type 12 +width 932 +height 1320 +) +(PageSizeInfo +name "B5 (JIS)" +type 13 +width 660 +height 932 +) +(PageSizeInfo +name "Folio" +type 14 +width 783 +height 1198 +) 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+(PageSizeInfo +name "Japanese Postcard" +type 43 +width 362 +height 536 +) +(PageSizeInfo +name "9x11" +type 44 +width 829 +height 1013 +) +(PageSizeInfo +name "10x11" +type 45 +width 921 +height 1013 +) +(PageSizeInfo +name "11x15" +type 46 +width 1013 +height 1382 +) +(PageSizeInfo +name "Envelope Invite" +type 47 +width 798 +height 798 +) +(PageSizeInfo +name "Letter Extra" +type 50 +width 875 +height 1105 +) +(PageSizeInfo +name "Legal Extra" +type 51 +width 875 +height 1382 +) +(PageSizeInfo +name "Tabloid Extra" +type 52 +width 1077 +height 1658 +) +(PageSizeInfo +name "A4 Extra" +type 53 +width 854 +height 1169 +) +(PageSizeInfo +name "Letter Transverse" +type 54 +width 783 +height 1013 +) +(PageSizeInfo +name "A4 Transverse" +type 55 +width 761 +height 1077 +) +(PageSizeInfo +name "Letter Extra Transverse" +type 56 +width 875 +height 1105 +) +(PageSizeInfo +name "SuperA/SuperA/A4" +type 57 +width 823 +height 1291 +) +(PageSizeInfo +name "SuperB/SuperB/A3" +type 58 +width 1106 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+processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) 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"0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/tasks/generate.tsk b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt b/04-Lissajous/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs b/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..dc45370 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6853 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState 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Configuration File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "jed" +Description "Xilinx Jedec Bit Map File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\placeroute.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ngc" +Description "Xilinx Netlist File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\synthesis.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "npl" +Description "Xilinx ISE Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xilinx_projnav.bmp" +DefaultAction "" +Actions [ +] +) +(FileTypeState +Extension "psp" +Description "Precision Synthesis Project File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\precision.bmp" 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"65535,65535,0" +) +enableNameVaSet (VaSet +) +enableShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +ccondNameVaSet (VaSet +) +ccondShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,32768,49152" +) +recoveryShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +stateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +stateNameVaSet (VaSet +font "Verdana,12,1" +) +stateEncodingVaSet (VaSet +font "Verdana,9,1" +) +stateActionsVaSet (VaSet +) +stateActionShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +stateCaseVaSet (VaSet +font "Verdana,9,1" +) +cStateShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "0,0,32768" +lineWidth 2 +) +cStateNameVaSet (VaSet +font "Verdana,10,1" +) +junctionShapeVaSet (VaSet +vasetType 1 +fg "59904,39936,65280" +) +junctionNameVaSet (VaSet +font "Verdana,9,1" +) +junctionSymbolVaSet (VaSet +font "Verdana,10,1" +) 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+processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/tasks/generate.tsk b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7a0938e --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/lissajousGenerator.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/04-Lissajous/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/04-Lissajous/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/04-Lissajous/Scripts/cleanGenerated.bash b/04-Lissajous/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/04-Lissajous/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/04-Lissajous/Scripts/cleanGenerated.bat b/04-Lissajous/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/04-Lissajous/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/04-Lissajous/Scripts/cleanScratch.bat b/04-Lissajous/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/04-Lissajous/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/04-Lissajous/Scripts/generateSSHKey.bash b/04-Lissajous/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/04-Lissajous/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/04-Lissajous/Scripts/hdlDesigner.bash b/04-Lissajous/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/04-Lissajous/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/04-Lissajous/Scripts/hdlDesigner.bat b/04-Lissajous/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..2a612a6 --- /dev/null +++ b/04-Lissajous/Scripts/hdlDesigner.bat @@ -0,0 +1,301 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +if %REQUIRE_ICECUBE2% == 1 ( + set synthesis_subdirectory="Board\icecube2" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + if %REQUIRE_ICECUBE2% == 1 ( + echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=% + echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=% + echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +if %REQUIRE_ICECUBE2% == 1 ( + if exist %ICECUBE2_BASE_DIR% ( + echo %ICECUBE2_BASE_DIR:"=% + echo -> %ICECUBE2_BASE_DIR:"=% + if exist %ICECUBE2_WORK_DIR% ( + rmdir /S /Q "%ICECUBE2_WORK_DIR%" + ) + mkdir "%ICECUBE2_WORK_DIR%" + xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW! + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/04-Lissajous/Scripts/searchPaths.bat b/04-Lissajous/Scripts/searchPaths.bat new file mode 100644 index 0000000..9b37b1b --- /dev/null +++ b/04-Lissajous/Scripts/searchPaths.bat @@ -0,0 +1,209 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +echo Search HEI Library +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings. + pause&goto:eof + ) +) + + +echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2 +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo %INDENT:"=%Found HDL-Designer at !HDS_HOME! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo %INDENT:"=%Found ISE at !ISE_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice Diamond directory +:: +if %REQUIRE_DIAMOND% == 1 ( + if "%DIAMOND_HOME%" == "" ( + set DIAMOND_HOME=C:\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !DIAMOND_HOME! ( + echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice IceCube2 directory +:: +if %REQUIRE_ICECUBE2% == 1 ( + if "%ICECUBE2_HOME%" == "" ( + set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !ICECUBE2_HOME! ( + echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings. + pause + goto:eof + ) +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + goto:eof \ No newline at end of file diff --git a/04-Lissajous/Scripts/trimLibs.pl b/04-Lissajous/Scripts/trimLibs.pl new file mode 100644 index 0000000..76d8d36 --- /dev/null +++ b/04-Lissajous/Scripts/trimLibs.pl @@ -0,0 +1,170 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ama: [Amand Axel](axel.amand@hevs.ch) +# ------------------------------------------------------------------------------ +# Changelog: +# 2023.05.16 : ama +# * Add: ice40 libs support +# 2023.02.01 : ama +# * Add: ECP5U libs support +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40 + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i) and + not($testline =~ m/ice40.*\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u or ice40 + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i) and + not($testline =~ m/ice40/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/04-Lissajous/Scripts/update_ise.pl b/04-Lissajous/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/04-Lissajous/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ +-- ----------------------------------------------------------------------------- +-- Common Lib +-- +-- ----------------------------------------------------------------------------- +-- Authors: +-- cof: [François Corthay](francois.corthay@hevs.ch) +-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +-- ----------------------------------------------------------------------------- +-- Changelog: +-- 2016-06 : guo +-- added function sel +-- 2015-06 : guo +-- added counterBitNb +-- added documentation +-- ----------------------------------------------------------------------------- +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + +PACKAGE CommonLib IS + + ------------------------------------------------------------------------------ + -- Returns the number of bits needed to represent the given val + -- Examples: + -- requiredBitNb(1) = 1 (1) + -- requiredBitNb(2) = 2 (10) + -- requiredBitNb(3) = 2 (11) + function requiredBitNb(val : integer) return integer; + + ------------------------------------------------------------------------------ + -- Returns the number of bits needed to count val times (0 to val-1) + -- Examples: + -- counterBitNb(1) = 1 (0) + -- counterBitNb(2) = 1 (0->1) + -- counterBitNb(3) = 2 (0->1->10) + function counterBitNb(val : integer) return integer; + + ------------------------------------------------------------------------------ + -- Functions to return one or the other input based on a boolean. + -- Can be used to build conditional constants. + -- Example: + -- constant bonjour_c : string := sel(ptpRole = master, "fpga20", "fpga02"); + function sel(Cond : BOOLEAN; If_True, If_False : integer) + return integer; + function sel(Cond : BOOLEAN; If_True, If_False : string) + return string; + function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector) + return std_ulogic_vector; + function sel(Cond : BOOLEAN; If_True, If_False : unsigned) + return unsigned; + function sel(Cond : BOOLEAN; If_True, If_False : signed) + return signed; + +END CommonLib; + + + + +-------------------------------------------------------------------------------- +-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch) +-------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-- ----------------------------------------------------------------------------- +-- Often used functions +-- +-- ----------------------------------------------------------------------------- +-- Authors: +-- cof: [François Corthay](francois.corthay@hevs.ch) +-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +-- ----------------------------------------------------------------------------- +-- Changelog: +-- 2016-06 : guo +-- added function sel +-- 2015-06 : guo +-- added counterBitNb +-- ----------------------------------------------------------------------------- +PACKAGE BODY CommonLib IS + + function requiredBitNb (val : integer) return integer is + variable powerOfTwo, bitNb : integer; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo <= val loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end requiredBitNb; + + function counterBitNb (val : integer) return integer is + variable powerOfTwo, bitNb : integer; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo < val loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end counterBitNb; + + function sel(Cond : BOOLEAN; If_True, If_False : integer) + return integer is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : string) + return string is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector) + return std_ulogic_vector is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : unsigned) + return unsigned is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : signed) + return signed is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + +END CommonLib; + + + + +-- library Common; + use work.CommonLib.all; + +architecture RTL of FIFO_bram is + + subtype register_type is std_ulogic_vector(dataIn'high downto 0); + type memory_type is array (0 to depth-1) of register_type; + + signal writeCounter: unsigned(requiredBitNb(depth-1)-1 downto 0); + signal readCounter: unsigned(writeCounter'range); + signal memoryArray: memory_type; + + type fifoStateType is ( + sEmpty, sFull, + sRead, sWrite, sWriteFirst, + sReadWrite, sWait + ); + signal fifoState: fifoStateType; + signal emptyCondition, fullCondition, empty_int: std_ulogic; + +begin + ------------------------------------------------------------------------------ + -- read and write counters + updateWriteCounter: process(reset, clock) + begin + if reset = '1' then + writeCounter <= (others => '0'); + elsif rising_edge(clock) then + if (write = '1') and (fullCondition = '0') then + writeCounter <= writeCounter + 1; + end if; + end if; + end process updateWriteCounter; + + updateReadCounter: process(reset, clock) + begin + if reset = '1' then + readCounter <= (others => '0'); + elsif rising_edge(clock) then + if (read = '1') and (empty_int = '0') then + readCounter <= readCounter + 1; + end if; + end if; + end process updateReadCounter; + + ------------------------------------------------------------------------------ + -- memory access + writeMem: process(clock) + begin + if rising_edge(clock) then + if (write = '1') and (fullCondition = '0') then + memoryArray(to_integer(writeCounter)) <= dataIn; + end if; + end if; + end process writeMem; + + readMem: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0'); + elsif rising_edge(clock) then + if (read = '0') or (empty_int = '1') then + dataOut <= memoryArray(to_integer(readCounter)); + else + dataOut <= memoryArray(to_integer(readCounter+1)); + end if; + end if; + end process readMem; + + ------------------------------------------------------------------------------ + -- controls + emptyCondition <= '1' when + ( (fifoState = sRead) and (writeCounter = readCounter) ) or + (fifoState = sEmpty) + else '0'; + + fullCondition <= '1' when + ( (fifoState = sWrite) and (writeCounter = readCounter) ) or + (fifoState = sFull) + else '0'; + + + fifoControl: process(reset, clock) + begin + if reset = '1' then + fifoState <= sEmpty; + elsif rising_edge(clock) then + case fifoState is + when sEmpty => + if write = '1' then + fifoState <= sWriteFirst; + end if; + when sFull => + if (read = '1') then + fifoState <= sRead; + end if; + when sRead => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif write = '1' then + fifoState <= sWrite; + elsif emptyCondition = '1' then + fifoState <= sEmpty; + elsif read = '1' then + fifoState <= sRead; + else + fifoState <= sWait; + end if; + when sWriteFirst => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif write = '1' then + fifoState <= sWrite; + elsif read = '1' then + fifoState <= sRead; + else + fifoState <= sWait; + end if; + when sWrite => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif read = '1' then + fifoState <= sRead; + elsif fullCondition = '1' then + fifoState <= sFull; + elsif write = '1' then + fifoState <= sWrite; + else + fifoState <= sWait; + end if; + when sReadWrite => + if (read = '0') and (write = '0') then + fifoState <= sWait; + elsif (read = '1') and (write = '0') then + fifoState <= sRead; + elsif (write = '1') and (read = '0') then + fifoState <= sWrite; + end if; + when sWait => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif read = '1' then + fifoState <= sRead; + elsif write = '1' then + fifoState <= sWrite; + end if; + when others => null; + end case; + end if; + end process fifoControl; + + + full <= '1' when + (fifoState = sFull) or + (fullCondition = '1') + else '0'; + + empty_int <= '1' when + (fifoState = sEmpty) or + (fifoState = sWriteFirst) or + ( (emptyCondition = '1') and (fifoState = sRead) ) + else '0'; + empty <= empty_int; + +end RTL; + + + + +-- VHDL Entity Morse.morseToCharDecoder.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:13:01 03/29/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY morseToCharDecoder IS + GENERIC( + unitCountDivide : positive := 100; + unitCountBitNb : positive := 2; + characterBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + charValid : OUT std_ulogic; + symbolDuration : IN unsigned (unitCountBitNb-1 DOWNTO 0); + symbolValid : IN std_ulogic; + symbolValue : IN std_ulogic; + charOut : OUT std_ulogic_vector (characterBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END morseToCharDecoder ; + + + + + +ARCHITECTURE masterVersion OF morseToCharDecoder IS + + constant shortDuration : positive := 1; + constant longDuration : positive := 3; + constant veryLongDuration : positive := 5; + signal isShort, isLong, isVeryLong : std_ulogic; + + type decoderStateType is ( + idle, + atA, atB, atC, atD, atE, atF, atG, atH, atI, atJ, + atK, atL, atM, atN, atO, atP, atQ, atR, atS, atT, + atU, atV, atW, atX, atY, atZ, + atO1, atO2, atU2, + at0, at1, at2, at3, at4, at5, at6, at7, at8, at9, + endOfCharacter, endOfWord + ); + signal decoderState : decoderStateType; + +BEGIN + -- decode symbol lengths + isShort <= '1' when symbolDuration = shortDuration else '0'; + isLong <= '1' when symbolDuration = longDuration else '0'; + isVeryLong <= '1' when symbolDuration = veryLongDuration else '0'; + -- decode Morse Code + updateState: process(reset, clock) + begin + if reset = '1' then + decoderState <= idle; + elsif rising_edge(clock) then + if symbolValid = '1' then + case decoderState is + when idle => + if symbolValue = '1' then + if isShort = '1' then + decoderState <= atE; + else + decoderState <= atT; + end if; + end if; + when atA => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atR; + else + decoderState <= atW; + end if; + end if; + when atB => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= at6; + else + decoderState <= idle; + end if; + end if; + when atC => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when atD => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atB; + else + decoderState <= atX; + end if; + end if; + when atE => + if symbolValue = '0' then + if isLong = '1' then -- end of character + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then -- end of word + decoderState <= endOfWord; + end if; + else -- next character symbol + if isShort = '1' then + decoderState <= atI; + else + decoderState <= atA; + end if; + end if; + when atF => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when atG => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atZ; + else + decoderState <= atQ; + end if; + end if; + when atH => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= at5; + else + decoderState <= at4; + end if; + end if; + when atI => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atS; + else + decoderState <= atU; + end if; + end if; + when atJ => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= idle; + else + decoderState <= at1; + end if; + end if; + when atK => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atC; + else + decoderState <= atY; + end if; + end if; + when atL => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when atM => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atG; + else + decoderState <= atO; + end if; + end if; + when atN => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atD; + else + decoderState <= atK; + end if; + end if; + when atO => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atO1; + else + decoderState <= atO2; + end if; + end if; + when atO1 => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= at8; + else + decoderState <= idle; + end if; + end if; + when atO2 => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= at9; + else + decoderState <= at0; + end if; + end if; + when atP => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when atQ => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when atR => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atL; + else + decoderState <= idle; + end if; + end if; + when atS => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atH; + else + decoderState <= atV; + end if; + end if; + when atT => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atN; + else + decoderState <= atM; + end if; + end if; + when atU => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atF; + else + decoderState <= atU2; + end if; + end if; + when atU2 => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= idle; + else + decoderState <= at2; + end if; + end if; + when atV => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= idle; + else + decoderState <= at3; + end if; + end if; + when atW => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= atP; + else + decoderState <= atJ; + end if; + end if; + when atX => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when atY => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when atZ => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + if isShort = '1' then + decoderState <= at7; + else + decoderState <= idle; + end if; + end if; + when at0 | at1 | at2 | at3 | at4 | at5 | at6 | at7 | at8 | at9 => + if symbolValue = '0' then + if isLong = '1' then + decoderState <= endOfCharacter; + elsif isVeryLong = '1' then + decoderState <= endOfWord; + end if; + else + decoderState <= idle; + end if; + when others => null; + end case; + else + case decoderState is + when endOfCharacter => decoderState <= idle; + when endOfWord => decoderState <= idle; + when others => null; + end case; + end if; + end if; + end process updateState; + -- provide character + provideCharacter: process(reset, clock) + -- could be combinatorial, but made sequential for easier debug + begin + if reset = '1' then + charValid <= '0'; + charOut <= (others => '0'); + elsif rising_edge(clock) then + charValid <= '0'; + if (symbolValid = '1') and (symbolValue = '0') then + if (isLong = '1') or (isVeryLong = '1') then + charValid <= '1'; + case decoderState is + when atA => + charOut <= std_ulogic_vector(to_unsigned(character'pos('a'), charOut'length)); + when atB => + charOut <= std_ulogic_vector(to_unsigned(character'pos('b'), charOut'length)); + when atC => + charOut <= std_ulogic_vector(to_unsigned(character'pos('c'), charOut'length)); + when atD => + charOut <= std_ulogic_vector(to_unsigned(character'pos('d'), charOut'length)); + when atE => + charOut <= std_ulogic_vector(to_unsigned(character'pos('e'), charOut'length)); + when atF => + charOut <= std_ulogic_vector(to_unsigned(character'pos('f'), charOut'length)); + when atG => + charOut <= std_ulogic_vector(to_unsigned(character'pos('g'), charOut'length)); + when atH => + charOut <= std_ulogic_vector(to_unsigned(character'pos('h'), charOut'length)); + when atI => + charOut <= std_ulogic_vector(to_unsigned(character'pos('i'), charOut'length)); + when atJ => + charOut <= std_ulogic_vector(to_unsigned(character'pos('j'), charOut'length)); + when atK => + charOut <= std_ulogic_vector(to_unsigned(character'pos('k'), charOut'length)); + when atL => + charOut <= std_ulogic_vector(to_unsigned(character'pos('l'), charOut'length)); + when atM => + charOut <= std_ulogic_vector(to_unsigned(character'pos('m'), charOut'length)); + when atN => + charOut <= std_ulogic_vector(to_unsigned(character'pos('n'), charOut'length)); + when atO => + charOut <= std_ulogic_vector(to_unsigned(character'pos('o'), charOut'length)); + when atP => + charOut <= std_ulogic_vector(to_unsigned(character'pos('p'), charOut'length)); + when atQ => + charOut <= std_ulogic_vector(to_unsigned(character'pos('q'), charOut'length)); + when atR => + charOut <= std_ulogic_vector(to_unsigned(character'pos('r'), charOut'length)); + when atS => + charOut <= std_ulogic_vector(to_unsigned(character'pos('s'), charOut'length)); + when atT => + charOut <= std_ulogic_vector(to_unsigned(character'pos('t'), charOut'length)); + when atU => + charOut <= std_ulogic_vector(to_unsigned(character'pos('u'), charOut'length)); + when atV => + charOut <= std_ulogic_vector(to_unsigned(character'pos('v'), charOut'length)); + when atW => + charOut <= std_ulogic_vector(to_unsigned(character'pos('w'), charOut'length)); + when atX => + charOut <= std_ulogic_vector(to_unsigned(character'pos('x'), charOut'length)); + when atY => + charOut <= std_ulogic_vector(to_unsigned(character'pos('y'), charOut'length)); + when atZ => + charOut <= std_ulogic_vector(to_unsigned(character'pos('z'), charOut'length)); + when at0 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('0'), charOut'length)); + when at1 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('1'), charOut'length)); + when at2 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('2'), charOut'length)); + when at3 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('3'), charOut'length)); + when at4 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('4'), charOut'length)); + when at5 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('5'), charOut'length)); + when at6 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('6'), charOut'length)); + when at7 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('7'), charOut'length)); + when at8 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('8'), charOut'length)); + when at9 => + charOut <= std_ulogic_vector(to_unsigned(character'pos('9'), charOut'length)); + when others => charOut <= (others => '-'); + end case; + end if; + elsif decoderState = endOfWord then + charValid <= '1'; + charOut <= std_ulogic_vector(to_unsigned(character'pos(' '), charOut'length)); + end if; + end if; + end process provideCharacter; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity Morse.envelopeRetreiver.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:13:01 03/29/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY envelopeRetreiver IS + GENERIC( + toneDivide : positive := 100E3; + deglitchBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + morseWithTone : IN std_ulogic; + morseEnvelope : OUT std_ulogic + ); + +-- Declarations + +END envelopeRetreiver ; + + + + + +-- library Common; + use work.CommonLib.all; + +ARCHITECTURE masterVersion OF envelopeRetreiver IS + + signal morseDelayed, morseRising : std_ulogic; + constant toneCounterBitNb: positive := requiredBitNb(toneDivide-1) + 1; + signal toneCounter, tonePeriod: unsigned(toneCounterBitNb-1 downto 0); + constant triggerShift : positive := 3; + constant triggerMin : positive := toneDivide - toneDivide/2**triggerShift; + constant triggerMax : positive := toneDivide + toneDivide/2**triggerShift; + signal morseTriggered : std_ulogic; + signal deglitchCounter: unsigned(deglitchBitNb-1 downto 0); + +BEGIN + -- find input rising edge + delayMorseIn: process(reset, clock) + begin + if reset = '1' then + morseDelayed <= '1'; + elsif rising_edge(clock) then + morseDelayed <= morseWithTone; + end if; + end process delayMorseIn; + + morseRising <= '1' when (morseWithTone = '1') and (morseDelayed = '0') + else '0'; + -- count period of incoming signal + countInputPeriod: process(reset, clock) + begin + if reset = '1' then + toneCounter <= (others => '0'); + tonePeriod <= (others => '0'); + elsif rising_edge(clock) then + if morseRising = '1' then + toneCounter <= (others => '0'); + tonePeriod <= toneCounter; + elsif toneCounter+1 /= 0 then + toneCounter <= toneCounter + 1; + end if; + end if; + end process countInputPeriod; + -- trigger morse signal + triggerMorse: process(tonePeriod, toneCounter) + begin + morseTriggered <= '1'; + if tonePeriod < triggerMin then + morseTriggered <= '0'; + end if; + if tonePeriod > triggerMax then + morseTriggered <= '0'; + end if; + if toneCounter > triggerMax then + morseTriggered <= '0'; + end if; + end process triggerMorse; + -- deglitch morse signal + countDeglitchDuration: process(reset, clock) + begin + if reset = '1' then + deglitchCounter <= (others => '0'); + elsif rising_edge(clock) then + if morseTriggered = '1' then + if deglitchCounter+1 /= 0 then + deglitchCounter <= deglitchCounter + 1; + end if; + else + if deglitchCounter /= 0 then + deglitchCounter <= deglitchCounter - 1; + end if; + end if; + end if; + end process countDeglitchDuration; + + trigDeglitchCounter: process(reset, clock) + begin + if reset = '1' then + morseEnvelope <= '0'; + elsif rising_edge(clock) then + if deglitchCounter+1 = 0 then + morseEnvelope <= '1'; + end if; + if deglitchCounter = 0 then + morseEnvelope <= '0'; + end if; + end if; + end process trigDeglitchCounter; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity Morse.symbolLengthCounter.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:13:01 03/29/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY symbolLengthCounter IS + GENERIC( + unitCountDivide : positive := 100; + unitCountBitNb : positive := 2 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + morseCode : IN std_ulogic; + symbolDuration : OUT unsigned (unitCountBitNb-1 DOWNTO 0); + symbolValid : OUT std_ulogic; + symbolValue : OUT std_ulogic + ); + +-- Declarations + +END symbolLengthCounter ; + + + + + +-- library Common; + use work.CommonLib.all; + +ARCHITECTURE masterVersion OF symbolLengthCounter IS + + signal morseDelayed, morseChanged : std_ulogic; + signal unitCounter : unsigned(requiredBitNb(unitCountDivide/2-1)-1 downto 0); + signal unitDone : std_ulogic; + signal durationCounter : unsigned(unitCountBitNb+1-1 downto 0); + constant shortDuration : positive := 1; + constant longDuration : positive := 3; + constant veryLongDuration : positive := 5; + +BEGIN + -- find input change + delayMorseCode: process(reset, clock) + begin + if reset = '1' then + morseDelayed <= '1'; + elsif rising_edge(clock) then + morseDelayed <= morseCode; + end if; + end process delayMorseCode; + + morseChanged <= '1' when morseDelayed /= morseCode + else '0'; + -- count half unit duration + countHalfUnitPeriod: process(reset, clock) + begin + if reset = '1' then + unitCounter <= (others => '0'); + elsif rising_edge(clock) then + if morseChanged = '1' then + unitCounter <= (others => '0'); + elsif unitDone = '1' then + unitCounter <= (others => '0'); + else + unitCounter <= unitCounter + 1; + end if; + end if; + end process countHalfUnitPeriod; + + unitDone <= '1' when unitCounter = unitCountDivide/2-1 + else '0'; + -- count unit number + countUnitNumber: process(reset, clock) + begin + if reset = '1' then + durationCounter <= (others => '0'); + elsif rising_edge(clock) then + if morseChanged = '1' then + durationCounter <= (others => '0'); + elsif unitDone = '1' then + if durationCounter+1 /= 0 then + durationCounter <= durationCounter + 1; + end if; + end if; + end if; + end process countUnitNumber; + -- provide symbol information + provideSymbolInformation: process(reset, clock) + -- could be combinatorial, but made sequential for easier debug + begin + if reset = '1' then + symbolValid <= '0'; + symbolValue <= '0'; + symbolDuration <= (others => '0'); + elsif rising_edge(clock) then + symbolValid <= '0'; + if morseChanged = '1' then + symbolValue <= not morseCode; + symbolValid <= '0'; + symbolDuration <= (others => '0'); + if (durationCounter >= 2*shortDuration-1) and + (durationCounter <= 2*shortDuration+1) then + symbolValid <= '1'; + symbolDuration <= to_unsigned(shortDuration, symbolDuration'length); + end if; + if (durationCounter >= 2*longDuration-1) and + (durationCounter <= 2*longDuration+1) then + symbolValid <= '1'; + symbolDuration <= to_unsigned(longDuration, symbolDuration'length); + end if; + end if; + if (durationCounter = 2*veryLongDuration-1) and (unitDone = '1') then + symbolValue <= morseCode; + symbolValid <= '1'; + symbolDuration <= to_unsigned( + veryLongDuration, symbolDuration'length + ); + end if; + end if; + end process provideSymbolInformation; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity RS232.serialPortTransmitter.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:45:48 08/28/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY serialPortTransmitter IS + GENERIC( + dataBitNb : positive := 8; + baudRateDivide : positive := 2083 + ); + PORT( + TxD : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + send : IN std_ulogic; + busy : OUT std_ulogic + ); + +-- Declarations + +END serialPortTransmitter ; + + + + + +-- library Common; + use work.CommonLib.all; + +architecture RTL of serialPortTransmitter is + + signal dividerCounter: unsigned(requiredBitNb(baudRateDivide)-1 downto 0); + signal dividerCounterReset: std_uLogic; + signal txData: std_ulogic_vector(dataBitNb-1 downto 0); + signal send1: std_uLogic; + signal txShiftEnable: std_uLogic; + signal txShiftReg: std_ulogic_vector(dataBitNb+1 downto 0); + signal txSendingByte: std_uLogic; + signal txSendingByteAndStop: std_uLogic; + +begin + + divide: process(reset, clock) + begin + if reset = '1' then + dividerCounter <= (others => '0'); + elsif rising_edge(clock) then + if dividerCounterReset = '1' then + dividerCounter <= to_unsigned(1, dividerCounter'length); + else + dividerCounter <= dividerCounter + 1; + end if; + end if; + end process divide; + + endOfCount: process(dividerCounter, send1) + begin + if dividerCounter = baudRateDivide then + dividerCounterReset <= '1'; + elsif send1 = '1' then + dividerCounterReset <= '1'; + else + dividerCounterReset <= '0'; + end if; + end process endOfCount; + + txShiftEnable <= dividerCounterReset; + + storeData: process(reset, clock) + begin + if reset = '1' then + txData <= (others => '1'); + elsif rising_edge(clock) then + if send = '1' then + txData <= dataIn; + end if; + end if; + end process storeData; + + delaySend: process(reset, clock) + begin + if reset = '1' then + send1 <= '0'; + elsif rising_edge(clock) then + send1 <= send; + end if; + end process delaySend; + + shiftReg: process(reset, clock) + begin + if reset = '1' then + txShiftReg <= (others => '1'); + elsif rising_edge(clock) then + if txShiftEnable = '1' then + if send1 = '1' then + txShiftReg <= '0' & txData & '0'; + else + txShiftReg(txShiftReg'high-1 downto 0) <= txShiftReg(txShiftReg'high downto 1); + txShiftReg(txShiftReg'high) <= '1'; + end if; + end if; + end if; + end process shiftReg; + + txSendingByte <= '1' when (txShiftReg(txShiftReg'high downto 1) /= (txShiftReg'high downto 1 => '1')) + else '0'; + + txSendingByteAndStop <= '1' when txShiftReg /= (txShiftReg'high downto 0 => '1') + else '0'; + + TxD <= txShiftReg(0) when txSendingByte = '1' else '1'; + busy <= txSendingByteAndStop or send1 or send; + +end RTL; + + + + + +-- +-- VHDL Architecture Morse.morseDecoder.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 08:02:13 08.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Memory; +-- LIBRARY Morse; +-- LIBRARY RS232; + +ARCHITECTURE struct OF morseDecoder IS + + -- Architecture declarations + constant unitCountBitNb: positive := 3; + constant fifoDepth : positive := 8; + + -- Internal signal declarations + SIGNAL symbolValue : std_ulogic; + SIGNAL symbolValid : std_ulogic; + SIGNAL symbolDuration : unsigned(unitCountBitNb-1 DOWNTO 0); + SIGNAL charValid : std_ulogic; + SIGNAL charOut : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0); + SIGNAL txWord : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0); + SIGNAL txBusy : std_ulogic; + SIGNAL txSend : std_ulogic; + SIGNAL txFifoEmpty : std_ulogic; + + -- Implicit buffer signal declarations + SIGNAL morseEnvelope_internal : std_ulogic; + + + -- Component Declarations + COMPONENT FIFO_bram + GENERIC ( + dataBitNb : positive := 8; + depth : positive := 8 + ); + PORT ( + write : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + read : IN std_ulogic ; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + empty : OUT std_ulogic ; + full : OUT std_ulogic + ); + END COMPONENT; + COMPONENT envelopeRetreiver + GENERIC ( + toneDivide : positive := 100E3; + deglitchBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + morseWithTone : IN std_ulogic ; + morseEnvelope : OUT std_ulogic + ); + END COMPONENT; + COMPONENT morseToCharDecoder + GENERIC ( + unitCountDivide : positive := 100; + unitCountBitNb : positive := 2; + characterBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + charValid : OUT std_ulogic ; + symbolDuration : IN unsigned (unitCountBitNb-1 DOWNTO 0); + symbolValid : IN std_ulogic ; + symbolValue : IN std_ulogic ; + charOut : OUT std_ulogic_vector (characterBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT symbolLengthCounter + GENERIC ( + unitCountDivide : positive := 100; + unitCountBitNb : positive := 2 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + morseCode : IN std_ulogic ; + symbolDuration : OUT unsigned (unitCountBitNb-1 DOWNTO 0); + symbolValid : OUT std_ulogic ; + symbolValue : OUT std_ulogic + ); + END COMPONENT; + COMPONENT serialPortTransmitter + GENERIC ( + dataBitNb : positive := 8; + baudRateDivide : positive := 2083 + ); + PORT ( + TxD : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + send : IN std_ulogic ; + busy : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : FIFO_bram USE ENTITY Memory.FIFO_bram; +-- FOR ALL : envelopeRetreiver USE ENTITY Morse.envelopeRetreiver; +-- FOR ALL : morseToCharDecoder USE ENTITY Morse.morseToCharDecoder; +-- FOR ALL : serialPortTransmitter USE ENTITY RS232.serialPortTransmitter; +-- FOR ALL : symbolLengthCounter USE ENTITY Morse.symbolLengthCounter; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + process(reset, clock) + begin + if reset = '1' then + txSend <= '0'; + elsif rising_edge(clock) then + if ( (txFifoEmpty = '0') and (txBusy = '0') ) then + txSend <= '1'; + else + txSend <= '0'; + end if; + end if; + end process; + + + + -- Instance port mappings. + I0 : FIFO_bram + GENERIC MAP ( + dataBitNb => uartDataBitNb, + depth => fifoDepth + ) + PORT MAP ( + write => charValid, + clock => clock, + reset => reset, + dataOut => txWord, + read => txSend, + dataIn => charOut, + empty => txFifoEmpty, + full => OPEN + ); + I_env : envelopeRetreiver + GENERIC MAP ( + toneDivide => integer(clockFrequency/toneFrequency + 0.5), + deglitchBitNb => deglitchBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + morseWithTone => morseCode, + morseEnvelope => morseEnvelope_internal + ); + I_dec : morseToCharDecoder + GENERIC MAP ( + unitCountDivide => integer(clockFrequency*unitDuration + 0.5), + unitCountBitNb => unitCountBitNb, + characterBitNb => uartDataBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + charValid => charValid, + symbolDuration => symbolDuration, + symbolValid => symbolValid, + symbolValue => symbolValue, + charOut => charOut + ); + I_len : symbolLengthCounter + GENERIC MAP ( + unitCountDivide => integer(clockFrequency*unitDuration + 0.5), + unitCountBitNb => unitCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + morseCode => morseEnvelope_internal, + symbolDuration => symbolDuration, + symbolValid => symbolValid, + symbolValue => symbolValue + ); + I_tx : serialPortTransmitter + GENERIC MAP ( + dataBitNb => uartDataBitNb, + baudRateDivide => integer(clockFrequency/uartBaudRate + 0.5) + ) + PORT MAP ( + TxD => TxD, + clock => clock, + reset => reset, + dataIn => txWord, + send => txSend, + busy => txBusy + ); + + -- Implicit buffered output assignments + morseEnvelope <= morseEnvelope_internal; + +END struct; + + + + +-- VHDL Entity Morse.morseEncoder.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:13:01 03/29/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY morseEncoder IS + GENERIC( + clockFrequency : real := 100.0E6; + uartBaudRate : real := 115.2E3; + uartDataBitNb : positive := 8; + unitDuration : real := 100.0E-3; + toneFrequency : real := 300.0 + ); + PORT( + morseCode : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + RxD : IN std_ulogic + ); + +-- Declarations + +END morseEncoder ; + + + + + +-- VHDL Entity Morse.charToMorse.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:49:52 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY charToMorse IS + GENERIC( + characterBitNb : positive := 8; + unitCountDivide : positive := 10E3 + ); + PORT( + morseOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + charIn : IN std_ulogic_vector (characterBitNb-1 DOWNTO 0); + readChar : OUT std_ulogic; + charNotReady : IN std_ulogic + ); + +-- Declarations + +END charToMorse ; + + + + + +-- VHDL Entity Morse.unitCounter.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:13:01 03/29/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY unitCounter IS + GENERIC( + unitCountDivide : positive := 10E3; + unitCountBitNb : positive := 3 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + startCounter : IN std_ulogic; + unitNb : IN unsigned (unitCountBitNb-1 DOWNTO 0); + done : OUT std_ulogic + ); + +-- Declarations + +END unitCounter ; + + + + + +-- library Common; + use work.CommonLib.all; + +ARCHITECTURE masterVersion OF unitCounter IS + + signal unitCounter: unsigned(requiredBitNb(unitCountDivide)-1 downto 0); + signal unitCountDone: std_ulogic; + signal unitNbCounter: unsigned(unitnB'range); + signal unitNbCountDone: std_ulogic; + +BEGIN + -- count unit base period + countUnitDuration: process(reset, clock) + begin + if reset = '1' then + unitCounter <= (others => '0'); + elsif rising_edge(clock) then + if unitCounter = 0 then + if (startCounter = '1') or (unitNbCounter > 0) then + unitCounter <= unitCounter + 1; + end if; + else + if unitCountDone = '0' then + unitCounter <= unitCounter + 1; + else + unitCounter <= (others => '0'); + end if; + end if; + end if; + end process countUnitDuration; + + unitCountDone <= '1' when unitCounter = unitCountDivide + else '0'; + -- count unit period number + countPeriods: process(reset, clock) + begin + if reset = '1' then + unitNbCounter <= (others => '0'); + elsif rising_edge(clock) then + if unitNbCounter = 0 then + if startCounter = '1' then + unitNbCounter <= unitNbCounter + 1; + end if; + else + if unitNbCountDone = '0' then + if unitCountDone = '1' then + unitNbCounter <= unitNbCounter + 1; + end if; + else + unitNbCounter <= (others => '0'); + end if; + end if; + end if; + end process countPeriods; + + unitNbCountDone <= '1' when (unitNbCounter = unitNb) and (unitCountDone = '1') + else '0'; + + done <= unitNbCountDone; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity Morse.charToMorseController.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:13:01 03/29/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY charToMorseController IS + GENERIC( + characterBitNb : positive := 8; + unitCountBitNb : positive := 3 + ); + PORT( + morseOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + charNotReady : IN std_ulogic; + char : IN std_ulogic_vector (characterBitNb-1 DOWNTO 0); + startCounter : OUT std_ulogic; + unitNb : OUT unsigned (unitCountBitNb-1 DOWNTO 0); + counterDone : IN std_ulogic; + readChar : OUT std_ulogic + ); + +-- Declarations + +END charToMorseController ; + + + + + +ARCHITECTURE masterVersion OF charToMorseController IS + -- sequence for characters + type characterStateType is ( + idle, waitReg, + sA, sB, sC, sD, sE, sF, sG, sH, sI, sJ, sK, sL, sM, sN, sO, sP, + sQ, sR, sS, sT, sU, sV, sW, sX, sY, sZ, + s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, + s2a, s8a, s9a, + popChar, waitEndOfChar + ); + signal characterState : characterStateType; + signal isA, isB, isC, isD, isE, isF, isG, isH, + isI, isJ, isK, isL, isM, isN, isO, isP, + isQ, isR, isS, isT, isU, isV, isW, isX, + isY, isZ, + is0, is1, is2, is3, is4, is5, is6, is7, + is8, is9 : std_ulogic; + signal gotoE, gotoI, gotoS, gotoH, goto5, + gotoF, + gotoL, gotoR, + gotoP, + gotoN, gotoD, gotoB, goto6, + gotoC, + gotoG, gotoZ, goto7, + goto8, + goto9, + gotoT : std_ulogic; + -- inter-FSM signalling + signal sendDot, sendDash, sendSeparator, sendDotDashDone: std_ulogic; + -- sequence for morse units + type sequencerStateType is ( + idle, + startDot, sendingDot, startDash, sendingDash, + startSeparator, waitingSeparator, startSeparator2, waitingSeparator2, + dotDashDone + ); + signal sequencerState : sequencerStateType; + +BEGIN + ------------------------------------------------------------------------------ + -- conditions for morse units + isA <= '1' when std_match(unsigned(char), "1-0" & x"1") else '0'; + isB <= '1' when std_match(unsigned(char), "1-0" & x"2") else '0'; + isC <= '1' when std_match(unsigned(char), "1-0" & x"3") else '0'; + isD <= '1' when std_match(unsigned(char), "1-0" & x"4") else '0'; + isE <= '1' when std_match(unsigned(char), "1-0" & x"5") else '0'; + isF <= '1' when std_match(unsigned(char), "1-0" & x"6") else '0'; + isG <= '1' when std_match(unsigned(char), "1-0" & x"7") else '0'; + isH <= '1' when std_match(unsigned(char), "1-0" & x"8") else '0'; + isI <= '1' when std_match(unsigned(char), "1-0" & x"9") else '0'; + isJ <= '1' when std_match(unsigned(char), "1-0" & x"A") else '0'; + isK <= '1' when std_match(unsigned(char), "1-0" & x"B") else '0'; + isL <= '1' when std_match(unsigned(char), "1-0" & x"C") else '0'; + isM <= '1' when std_match(unsigned(char), "1-0" & x"D") else '0'; + isN <= '1' when std_match(unsigned(char), "1-0" & x"E") else '0'; + isO <= '1' when std_match(unsigned(char), "1-0" & x"F") else '0'; + isP <= '1' when std_match(unsigned(char), "1-1" & x"0") else '0'; + isQ <= '1' when std_match(unsigned(char), "1-1" & x"1") else '0'; + isR <= '1' when std_match(unsigned(char), "1-1" & x"2") else '0'; + isS <= '1' when std_match(unsigned(char), "1-1" & x"3") else '0'; + isT <= '1' when std_match(unsigned(char), "1-1" & x"4") else '0'; + isU <= '1' when std_match(unsigned(char), "1-1" & x"5") else '0'; + isV <= '1' when std_match(unsigned(char), "1-1" & x"6") else '0'; + isW <= '1' when std_match(unsigned(char), "1-1" & x"7") else '0'; + isX <= '1' when std_match(unsigned(char), "1-1" & x"8") else '0'; + isY <= '1' when std_match(unsigned(char), "1-1" & x"9") else '0'; + isZ <= '1' when std_match(unsigned(char), "1-1" & x"A") else '0'; + is0 <= '1' when std_match(unsigned(char), "011" & x"0") else '0'; + is1 <= '1' when std_match(unsigned(char), "011" & x"1") else '0'; + is2 <= '1' when std_match(unsigned(char), "011" & x"2") else '0'; + is3 <= '1' when std_match(unsigned(char), "011" & x"3") else '0'; + is4 <= '1' when std_match(unsigned(char), "011" & x"4") else '0'; + is5 <= '1' when std_match(unsigned(char), "011" & x"5") else '0'; + is6 <= '1' when std_match(unsigned(char), "011" & x"6") else '0'; + is7 <= '1' when std_match(unsigned(char), "011" & x"7") else '0'; + is8 <= '1' when std_match(unsigned(char), "011" & x"8") else '0'; + is9 <= '1' when std_match(unsigned(char), "011" & x"9") else '0'; + goto5 <= is5; + gotoH <= ish or goto5 or is4; + gotoS <= isS or gotoH or isV or is3; + gotoF <= isF; + gotoI <= isI or gotoS or isU or gotoF or is2; + gotoL <= isL; + gotoR <= isR or gotoL; + gotoP <= isP; + gotoE <= isE or gotoI or isA or gotoR or isW or gotoP or isJ or is1; + goto6 <= is6; + gotoB <= isB or goto6; + gotoD <= isD or gotoB or isX; + gotoC <= isC; + gotoN <= isN or gotoD or isK or gotoC or isY; + goto7 <= is7; + gotoZ <= isZ or goto7; + gotoG <= isG or gotoZ or isQ; + goto8 <= is8; + goto9 <= is9; + gotoT <= isT or gotoN or isM or gotoG or isO or goto8 or goto9 or is0; + -- sequence for morse units + sendCharacterState: process(reset, clock) + begin + if reset = '1' then + characterState <= idle; + elsif rising_edge(clock) then + case characterState is + -- start + when idle => + if charnotReady = '0' then + characterState <= waitReg; + end if; + when waitReg => + if gotoE = '1' then + characterState <= sE; + elsif gotoT = '1' then + characterState <= sT; + else + characterState <= popChar; + end if; + -- level 1 + when sE => + if sendDotDashDone = '1' then + if isE = '1' then + characterState <= popChar; + elsif gotoI = '1' then + characterState <= sI; + else + characterState <= sA; + end if; + end if; + when sT => + if sendDotDashDone = '1' then + if isT = '1' then + characterState <= popChar; + elsif gotoN = '1' then + characterState <= sN; + else + characterState <= sM; + end if; + end if; + -- level 2 + when sI => + if sendDotDashDone = '1' then + if isI = '1' then + characterState <= popChar; + elsif gotoS = '1' then + characterState <= sS; + else + characterState <= sU; + end if; + end if; + when sA => + if sendDotDashDone = '1' then + if isA = '1' then + characterState <= popChar; + elsif gotoR = '1' then + characterState <= sR; + else + characterState <= sW; + end if; + end if; + when sN => + if sendDotDashDone = '1' then + if isN = '1' then + characterState <= popChar; + elsif gotoD = '1' then + characterState <= sD; + else + characterState <= sK; + end if; + end if; + when sM => + if sendDotDashDone = '1' then + if isM = '1' then + characterState <= popChar; + elsif gotoG = '1' then + characterState <= sG; + else + characterState <= sO; + end if; + end if; + -- level 3a + when sS => + if sendDotDashDone = '1' then + if isS = '1' then + characterState <= popChar; + elsif gotoH = '1' then + characterState <= sH; + else + characterState <= sV; + end if; + end if; + when sU => + if sendDotDashDone = '1' then + if isU = '1' then + characterState <= popChar; + elsif gotoF = '1' then + characterState <= sF; + else + characterState <= s2a; + end if; + end if; + when sR => + if sendDotDashDone = '1' then + if isR = '1' then + characterState <= popChar; + elsif gotoL = '1' then + characterState <= sL; + else + characterState <= popChar; + end if; + end if; + when sW => + if sendDotDashDone = '1' then + if isW = '1' then + characterState <= popChar; + elsif gotoP = '1' then + characterState <= sP; + else + characterState <= sJ; + end if; + end if; + -- level 3b + when sD => + if sendDotDashDone = '1' then + if isD = '1' then + characterState <= popChar; + elsif gotoB = '1' then + characterState <= sB; + else + characterState <= sX; + end if; + end if; + when sK => + if sendDotDashDone = '1' then + if isK = '1' then + characterState <= popChar; + elsif gotoC = '1' then + characterState <= sC; + else + characterState <= sY; + end if; + end if; + when sG => + if sendDotDashDone = '1' then + if isG = '1' then + characterState <= popChar; + elsif gotoZ = '1' then + characterState <= sZ; + else + characterState <= sQ; + end if; + end if; + when sO => + if sendDotDashDone = '1' then + if isO = '1' then + characterState <= popChar; + elsif goto8 = '1' then + characterState <= s8a; + else + characterState <= s9a; + end if; + end if; + -- level 4a + when sH => + if sendDotDashDone = '1' then + if isH = '1' then + characterState <= popChar; + elsif goto5 = '1' then + characterState <= s5; + else + characterState <= s4; + end if; + end if; + when sV => + if sendDotDashDone = '1' then + if isV = '1' then + characterState <= popChar; + else + characterState <= s3; + end if; + end if; + when sF => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + when s2a => + if sendDotDashDone = '1' then + characterState <= s2; + end if; + -- level 4b + when sL => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + when sP => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + when sJ => + if sendDotDashDone = '1' then + if isJ = '1' then + characterState <= popChar; + else + characterState <= s1; + end if; + end if; + -- level 4c + when sB => + if sendDotDashDone = '1' then + if isB = '1' then + characterState <= popChar; + elsif goto6 = '1' then + characterState <= s6; + else + characterState <= popChar; + end if; + end if; + when sX => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + when sC => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + when sY => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + -- level 4d + when sZ => + if sendDotDashDone = '1' then + if isZ = '1' then + characterState <= popChar; + elsif goto7 = '1' then + characterState <= s7; + else + characterState <= popChar; + end if; + end if; + when sQ => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + when s8a => + if sendDotDashDone = '1' then + characterState <= s8; + end if; + when s9a => + if sendDotDashDone = '1' then + if goto9 = '1' then + characterState <= s9; + else + characterState <= s0; + end if; + end if; + -- level 5 + when s5 | s4 | s3 | s2 | s1 | s6 | s7 | s8 | s9 | s0 => + if sendDotDashDone = '1' then + characterState <= popChar; + end if; + -- end of character + when popChar => characterState <= waitEndOfChar; + when waitEndOfChar => + if sendDotDashDone = '1' then + characterState <= idle; + end if; + when others => characterState <= idle; + end case; + end if; + end process sendCharacterState; + + sendCharacterOutput: process(characterState) + begin + sendDot <= '0'; + sendDash <= '0'; + sendSeparator <= '0'; + readChar <= '0'; + case characterState is + -- level 1 + when sE => + sendDot <= '1'; + when sT => + sendDash <= '1'; + -- level 2 + when sI => + sendDot <= '1'; + when sA => + sendDash <= '1'; + when sN => + sendDot <= '1'; + when sM => + sendDash <= '1'; + -- level 3a + when sS => + sendDot <= '1'; + when sU => + sendDash <= '1'; + when sR => + sendDot <= '1'; + when sW => + sendDash <= '1'; + -- level 3b + when sD => + sendDot <= '1'; + when sK => + sendDash <= '1'; + when sG => + sendDot <= '1'; + when sO => + sendDash <= '1'; + -- level 4a + when sH => + sendDot <= '1'; + when sV => + sendDash <= '1'; + when sF => + sendDot <= '1'; + when s2a => + sendDash <= '1'; + -- level 4b + when sL => + sendDot <= '1'; + when sP => + sendDot <= '1'; + when sJ => + sendDash <= '1'; + -- level 4c + when sB => + sendDot <= '1'; + when sX => + sendDash <= '1'; + when sC => + sendDot <= '1'; + when sY => + sendDash <= '1'; + -- level 4d + when sZ => + sendDot <= '1'; + when sQ => + sendDash <= '1'; + when s8a => + sendDot <= '1'; + when s9a => + sendDash <= '1'; + -- level 5 + when s5 => + sendDot <= '1'; + when s4 => + sendDash <= '1'; + when s3 => + sendDash <= '1'; + when s2 => + sendDash <= '1'; + when s1 => + sendDash <= '1'; + when s6 => + sendDot <= '1'; + when s7 => + sendDot <= '1'; + when s8 => + sendDot <= '1'; + when s9 => + sendDot <= '1'; + when s0 => + sendDash <= '1'; + -- end of character + when popChar => + readChar <= '1'; + sendSeparator <= '1'; + when others => null; + end case; + end process sendCharacterOutput; + + ------------------------------------------------------------------------------ + -- sequence for morse units + sendDotDashState: process(reset, clock) + begin + if reset = '1' then + sequencerState <= idle; + elsif rising_edge(clock) then + case sequencerState is + -- idle + when idle => + if sendDot = '1' then + sequencerState <= startDot; + elsif sendDash = '1' then + sequencerState <= startDash; + elsif sendSeparator = '1' then + sequencerState <= startSeparator2; + end if; + -- dot + when startDot => + sequencerState <= sendingDot; + when sendingDot => + if counterDone = '1' then + sequencerState <= startSeparator; + end if; + -- dash + when startDash => + sequencerState <= sendingDash; + when sendingDash => + if counterDone = '1' then + sequencerState <= startSeparator; + end if; + -- morse symbol separator + when startSeparator => + sequencerState <= waitingSeparator; + when waitingSeparator => + if counterDone = '1' then + sequencerState <= dotDashDone; + end if; + -- character separator + when startSeparator2 => + sequencerState <= waitingSeparator2; + when waitingSeparator2 => + if counterDone = '1' then + sequencerState <= dotDashDone; + end if; + -- done + when dotDashDone => + sequencerState <= idle; + end case; + end if; + end process sendDotDashState; + + sendDotDashOutput: process(sequencerState) + begin + startCounter <= '0'; + unitNb <= (others => '-'); + sendDotDashDone <= '0'; + morseOut <= '0'; + case sequencerState is + when startDot | startDash => + startCounter <= '1'; + morseOut <= '1'; + when sendingDot => + morseOut <= '1'; + unitNb <= to_unsigned(1, unitNb'length); + when sendingDash => + morseOut <= '1'; + unitNb <= to_unsigned(3, unitNb'length); + when startSeparator => + startCounter <= '1'; + when waitingSeparator => + unitNb <= to_unsigned(1, unitNb'length); + when startSeparator2 => + startCounter <= '1'; + when waitingSeparator2 => + unitNb <= to_unsigned(2, unitNb'length); + when dotDashDone => + sendDotDashDone <= '1'; + when others => null; + end case; + end process sendDotDashOutput; + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture Morse.charToMorse.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:49:52 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Morse; + +ARCHITECTURE struct OF charToMorse IS + + -- Architecture declarations + constant unitCountBitNb: positive := 3; + + -- Internal signal declarations + SIGNAL startCounter : std_ulogic; + SIGNAL done : std_ulogic; + SIGNAL unitNb : unsigned(unitCountBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT charToMorseController + GENERIC ( + characterBitNb : positive := 8; + unitCountBitNb : positive := 3 + ); + PORT ( + morseOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + charNotReady : IN std_ulogic ; + char : IN std_ulogic_vector (characterBitNb-1 DOWNTO 0); + startCounter : OUT std_ulogic ; + unitNb : OUT unsigned (unitCountBitNb-1 DOWNTO 0); + counterDone : IN std_ulogic ; + readChar : OUT std_ulogic + ); + END COMPONENT; + COMPONENT unitCounter + GENERIC ( + unitCountDivide : positive := 10E3; + unitCountBitNb : positive := 3 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + startCounter : IN std_ulogic ; + unitNb : IN unsigned (unitCountBitNb-1 DOWNTO 0); + done : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : charToMorseController USE ENTITY Morse.charToMorseController; +-- FOR ALL : unitCounter USE ENTITY Morse.unitCounter; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + I_ctl : charToMorseController + GENERIC MAP ( + characterBitNb => characterBitNb, + unitCountBitNb => unitCountBitNb + ) + PORT MAP ( + morseOut => morseOut, + clock => clock, + reset => reset, + charNotReady => charNotReady, + char => charIn, + startCounter => startCounter, + unitNb => unitNb, + counterDone => done, + readChar => readChar + ); + I_cnt : unitCounter + GENERIC MAP ( + unitCountDivide => unitCountDivide, + unitCountBitNb => unitCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + startCounter => startCounter, + unitNb => unitNb, + done => done + ); + +END struct; + + + + +-- VHDL Entity Morse.toneGenerator.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:13:01 03/29/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY toneGenerator IS + GENERIC( + toneDivide : positive := 100E3 + ); + PORT( + tone : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END toneGenerator ; + + + + + +-- library Common; + use work.CommonLib.all; + +ARCHITECTURE masterVersion OF toneGenerator IS + + constant toneCounterBitNb: positive := requiredBitNb(toneDivide-1); + signal toneCounter: unsigned(toneCounterBitNb-1 downto 0); + constant toneMin : natural := (2**toneCounterBitNb - toneDivide) / 2; + constant toneMax : natural := toneMin + toneDivide; + +BEGIN + + divide: process(reset, clock) + begin + if reset = '1' then + toneCounter <= to_unsigned(toneMin, toneCounter'length); + elsif rising_edge(clock) then + if toneCounter = toneMax then + toneCounter <= to_unsigned(toneMin, toneCounter'length); + else + toneCounter <= toneCounter + 1; + end if; + end if; + end process divide; + + tone <= toneCounter(toneCounter'high); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity RS232.serialPortReceiver.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:45:48 08/28/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY serialPortReceiver IS + GENERIC( + dataBitNb : positive := 8; + baudRateDivide : positive := 2083 + ); + PORT( + RxD : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataValid : OUT std_ulogic + ); + +-- Declarations + +END serialPortReceiver ; + + + + + +-- library Common; + use work.CommonLib.all; + +architecture RTL of serialPortReceiver is + + signal dividerCounter: unsigned(requiredBitNb(baudRateDivide-1)-1 downto 0); + signal dividerCounterReset: std_uLogic; + signal rxDelayed: std_uLogic; + signal dividerCounterSynchronize: std_uLogic; + signal rxSample: std_uLogic; + signal rxShiftReg: std_ulogic_vector(dataBitNb-1 downto 0); + signal rxReceiving: std_uLogic; + signal rxDataValid: std_uLogic; + signal rxCounter: unsigned(requiredBitNb(dataBitNb)-1 downto 0); + +begin + + divide: process(reset, clock) + begin + if reset = '1' then + dividerCounter <= (others => '0'); + elsif rising_edge(clock) then + if dividerCounterSynchronize = '1' then + dividerCounter <= to_unsigned(baudRateDivide/2, dividerCounter'length); + elsif dividerCounterReset = '1' then + dividerCounter <= (others => '0'); + else + dividerCounter <= dividerCounter + 1; + end if; + end if; + end process divide; + + endOfCount: process(dividerCounter) + begin + if dividerCounter = baudRateDivide-1 then + dividerCounterReset <= '1'; + else + dividerCounterReset <= '0'; + end if; + end process endOfCount; + + delayRx: process(reset, clock) + begin + if reset = '1' then + rxDelayed <= '0'; + elsif rising_edge(clock) then + rxDelayed <= RxD; + end if; + end process delayRx; + + rxSynchronize: process(RxD, rxDelayed) + begin + if RxD /= rxDelayed then + dividerCounterSynchronize <= '1'; + else + dividerCounterSynchronize <= '0'; + end if; + end process rxSynchronize; + + rxSample <= dividerCounterReset and not dividerCounterSynchronize; + + shiftReg: process(reset, clock) + begin + if reset = '1' then + rxShiftReg <= (others => '0'); + elsif rising_edge(clock) then + if rxSample = '1' then + rxShiftReg(rxShiftReg'high-1 downto 0) <= rxShiftReg(rxShiftReg'high downto 1); + rxShiftReg(rxShiftReg'high) <= RxD; + end if; + end if; + end process shiftReg; + + detectReceive: process(reset, clock) + begin + if reset = '1' then + rxReceiving <= '0'; + rxDataValid <= '0'; + elsif rising_edge(clock) then + if rxSample = '1' then + if rxCounter = dataBitNb-1 then + rxDataValid <= '1'; + elsif RxD = '0' then + rxReceiving <= '1'; + end if; + elsif rxDataValid = '1' then + rxReceiving <= '0'; + rxDataValid <= '0'; + end if; + end if; + end process detectReceive; + + countRxBitNb: process(reset, clock) + begin + if reset = '1' then + rxCounter <= (others => '0'); + elsif rising_edge(clock) then + if rxSample = '1' then + if rxReceiving = '1' then + rxCounter <= rxCounter + 1; + else + rxCounter <= (others => '0'); + end if; + end if; + end if; + end process countRxBitNb; + + dataOut <= rxShiftReg; + dataValid <= rxDataValid; + +end RTL; + + + + + +-- +-- VHDL Architecture Morse.morseEncoder.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 14:50:20 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Memory; +-- LIBRARY Morse; +-- LIBRARY RS232; + +ARCHITECTURE struct OF morseEncoder IS + + -- Architecture declarations + constant fifoDepth : positive := 100; + + -- Internal signal declarations + SIGNAL characterReg : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0); + SIGNAL characterIn : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0); + SIGNAL characterValid : std_ulogic; + SIGNAL morseOut : std_ulogic; + SIGNAL tone : std_ulogic; + SIGNAL charNotReady : std_ulogic; + SIGNAL readChar : std_ulogic; + + + -- Component Declarations + COMPONENT FIFO_bram + GENERIC ( + dataBitNb : positive := 8; + depth : positive := 8 + ); + PORT ( + write : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + read : IN std_ulogic ; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + empty : OUT std_ulogic ; + full : OUT std_ulogic + ); + END COMPONENT; + COMPONENT charToMorse + GENERIC ( + characterBitNb : positive := 8; + unitCountDivide : positive := 10E3 + ); + PORT ( + morseOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + charIn : IN std_ulogic_vector (characterBitNb-1 DOWNTO 0); + readChar : OUT std_ulogic ; + charNotReady : IN std_ulogic + ); + END COMPONENT; + COMPONENT toneGenerator + GENERIC ( + toneDivide : positive := 100E3 + ); + PORT ( + tone : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT serialPortReceiver + GENERIC ( + dataBitNb : positive := 8; + baudRateDivide : positive := 2083 + ); + PORT ( + RxD : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataValid : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : FIFO_bram USE ENTITY Memory.FIFO_bram; +-- FOR ALL : charToMorse USE ENTITY Morse.charToMorse; +-- FOR ALL : serialPortReceiver USE ENTITY RS232.serialPortReceiver; +-- FOR ALL : toneGenerator USE ENTITY Morse.toneGenerator; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + morseCode <= morseOut and tone; + + + -- Instance port mappings. + I_FIFO : FIFO_bram + GENERIC MAP ( + dataBitNb => uartDataBitNb, + depth => fifoDepth + ) + PORT MAP ( + write => characterValid, + clock => clock, + reset => reset, + dataOut => characterReg, + read => readChar, + dataIn => characterIn, + empty => charNotReady, + full => OPEN + ); + I_enc : charToMorse + GENERIC MAP ( + characterBitNb => uartDataBitNb, + unitCountDivide => integer(clockFrequency*unitDuration + 0.5) + ) + PORT MAP ( + morseOut => morseOut, + clock => clock, + reset => reset, + charNotReady => charNotReady, + charIn => characterReg, + readChar => readChar + ); + I_tone : toneGenerator + GENERIC MAP ( + toneDivide => integer(clockFrequency/toneFrequency + 0.5) + ) + PORT MAP ( + tone => tone, + clock => clock, + reset => reset + ); + I_UART : serialPortReceiver + GENERIC MAP ( + dataBitNb => uartDataBitNb, + baudRateDivide => integer(clockFrequency/uartBaudRate + 0.5) + ) + PORT MAP ( + RxD => RxD, + clock => clock, + reset => reset, + dataOut => characterIn, + dataValid => characterValid + ); + +END struct; + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- +-- VHDL Architecture Board.morse_ebs3.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 08:06:36 08.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Board; +-- LIBRARY Lattice; +-- LIBRARY Morse; + +ARCHITECTURE struct OF morse_ebs3 IS + + -- Architecture declarations + constant clockFrequency: real := 60.0E6; + constant uartBaudRate: real := 9.6E3; + constant uartDataBitNb: positive := 7; + constant morseUnitDuration: real := 100.0E-3; -- 1/2 * 10 Hz + constant morseToneFrequency: real := 3135.96; -- sol 3eme octave + constant deglitchBitNb: positive := 16; + + -- Internal signal declarations + SIGNAL clk_sys : std_ulogic; + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL morseIn_synch : std_uLogic; + SIGNAL reset1 : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_n : std_ulogic; + + -- Implicit buffer signal declarations + SIGNAL RxD_synch_internal : std_ulogic; + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT morseDecoder + GENERIC ( + clockFrequency : real := 100.0E6; + uartBaudRate : real := 115.2E3; + uartDataBitNb : positive := 8; + unitDuration : real := 100.0E-3; + toneFrequency : real := 300.0; + deglitchBitNb : natural := 8 + ); + PORT ( + morseCode : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + TxD : OUT std_ulogic ; + morseEnvelope : OUT std_ulogic + ); + END COMPONENT; + COMPONENT morseEncoder + GENERIC ( + clockFrequency : real := 100.0E6; + uartBaudRate : real := 115.2E3; + uartDataBitNb : positive := 8; + unitDuration : real := 100.0E-3; + toneFrequency : real := 300.0 + ); + PORT ( + morseCode : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + RxD : IN std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DFF USE ENTITY Board.DFF; +-- FOR ALL : inverterIn USE ENTITY Board.inverterIn; +-- FOR ALL : morseDecoder USE ENTITY Morse.morseDecoder; +-- FOR ALL : morseEncoder USE ENTITY Morse.morseEncoder; +-- FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 6 eb6 + logic1 <= '1'; + + -- HDL Embedded Text Block 7 eb7 + logic0 <= '0'; + + + -- Instance port mappings. + I7 : DFF + PORT MAP ( + CLK => clk_sys, + CLR => resetSynch, + D => RxD, + Q => RxD_synch_internal + ); + I8 : DFF + PORT MAP ( + CLK => clock, + CLR => reset1, + D => logic1, + Q => resetSynch_n + ); + I9 : DFF + PORT MAP ( + CLK => clk_sys, + CLR => resetSynch, + D => morseIn, + Q => morseIn_synch + ); + I3 : inverterIn + PORT MAP ( + in1 => reset_n, + out1 => reset1 + ); + I4 : inverterIn + PORT MAP ( + in1 => resetSynch_n, + out1 => resetSynch + ); + I_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clk_sys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_dec : morseDecoder + GENERIC MAP ( + clockFrequency => clockFrequency, + uartBaudRate => uartBaudRate, + uartDataBitNb => uartDataBitNb, + unitDuration => morseUnitDuration, + toneFrequency => morseToneFrequency, + deglitchBitNb => deglitchBitNb + ) + PORT MAP ( + morseCode => morseIn_synch, + clock => clk_sys, + reset => resetSynch, + TxD => TxD, + morseEnvelope => morseEnvelope + ); + I_enc : morseEncoder + GENERIC MAP ( + clockFrequency => clockFrequency, + uartBaudRate => uartBaudRate, + uartDataBitNb => uartDataBitNb, + unitDuration => morseUnitDuration, + toneFrequency => morseToneFrequency + ) + PORT MAP ( + morseCode => morseOut, + clock => clk_sys, + reset => resetSynch, + RxD => RxD_synch_internal + ); + + -- Implicit buffered output assignments + RxD_synch <= RxD_synch_internal; + +END struct; + + + + diff --git a/05-Morse/Board/diamond/morse.bit b/05-Morse/Board/diamond/morse.bit new file mode 100644 index 0000000..941f5e7 Binary files /dev/null and b/05-Morse/Board/diamond/morse.bit differ diff --git a/05-Morse/Board/diamond/morse.ldf b/05-Morse/Board/diamond/morse.ldf new file mode 100644 index 0000000..f1ae61d --- /dev/null +++ b/05-Morse/Board/diamond/morse.ldf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/05-Morse/Board/diamond/programmer.xcf b/05-Morse/Board/diamond/programmer.xcf new file mode 100644 index 0000000..468a2da --- /dev/null +++ b/05-Morse/Board/diamond/programmer.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Renesas + ECP5U + LFE5U-25F + All + LFE5U-25F + + 8 + 11111111 + 1 + 0 + + + 04/11/23 16:14:28 + 0xA4B0 + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 4 + + + USB2 + FTUSB-0 + LFE5U-25F A Location 0000 Serial 018VFVT3A + + diff --git a/05-Morse/Board/diamond/reveal_analyze.rva b/05-Morse/Board/diamond/reveal_analyze.rva new file mode 100644 index 0000000..4249e0e --- /dev/null +++ b/05-Morse/Board/diamond/reveal_analyze.rva @@ -0,0 +1,638 @@ + + + lun. 6. mars 14:29:10 2023 + + + + + + + + + + + + 1 + + 0 + 1. LFE5U-25F + 0x41111043 + true + false + + 8 + reveal_config.rvl + reveal_config.rvs + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/05-Morse/Board/diamond/reveal_config.rvl b/05-Morse/Board/diamond/reveal_config.rvl new file mode 100644 index 0000000..28d2f1c --- /dev/null +++ b/05-Morse/Board/diamond/reveal_config.rvl @@ -0,0 +1,662 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/05-Morse/Board/diamond/strategy.sty b/05-Morse/Board/diamond/strategy.sty new file mode 100644 index 0000000..a2b5a4a --- /dev/null +++ b/05-Morse/Board/diamond/strategy.sty @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/05-Morse/Board/hdl/DFF_sim.vhd b/05-Morse/Board/hdl/DFF_sim.vhd new file mode 100644 index 0000000..cf8868a --- /dev/null +++ b/05-Morse/Board/hdl/DFF_sim.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/05-Morse/Board/hdl/buff_sim.vhd b/05-Morse/Board/hdl/buff_sim.vhd new file mode 100644 index 0000000..8ad27be --- /dev/null +++ b/05-Morse/Board/hdl/buff_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF buff IS +BEGIN + + out1 <= in1; + +END ARCHITECTURE sim; + diff --git a/05-Morse/Board/hdl/inverterIn_sim.vhd b/05-Morse/Board/hdl/inverterIn_sim.vhd new file mode 100644 index 0000000..fb039ac --- /dev/null +++ b/05-Morse/Board/hdl/inverterIn_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/05-Morse/Board/hdl/inverter_sim.vhd b/05-Morse/Board/hdl/inverter_sim.vhd new file mode 100644 index 0000000..ca5b6b5 --- /dev/null +++ b/05-Morse/Board/hdl/inverter_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverter IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/05-Morse/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf b/05-Morse/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf b/05-Morse/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf b/05-Morse/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf b/05-Morse/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf b/05-Morse/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf b/05-Morse/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_morse_circuit_entity.vhg._fpf b/05-Morse/Board/hds/.hdlsidedata/_morse_circuit_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_morse_circuit_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_morse_circuit_struct.vhg._fpf b/05-Morse/Board/hds/.hdlsidedata/_morse_circuit_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_morse_circuit_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_morse_ebs3_entity.vhg._fpf b/05-Morse/Board/hds/.hdlsidedata/_morse_ebs3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_morse_ebs3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/.hdlsidedata/_morse_ebs3_struct.vhg._fpf b/05-Morse/Board/hds/.hdlsidedata/_morse_ebs3_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Board/hds/.hdlsidedata/_morse_ebs3_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Board/hds/@d@f@f/symbol.sb b/05-Morse/Board/hds/@d@f@f/symbol.sb new file mode 100644 index 0000000..555b689 --- /dev/null +++ b/05-Morse/Board/hds/@d@f@f/symbol.sb @@ -0,0 +1,1211 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +] +libraryRefs [ +"ieee" +] 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"0,10000,2700,11000" +st "Ports:" +blo "0,10800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,19000,2400,20000" +st "User:" +blo "0,19800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,9000,5800,10000" +st "Internal User:" +blo "0,9800" +) +externalText (MLText +uid 5,0 +va (VaSet +) +xt "2000,20000,2000,20000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +) +xt "0,9000,0,9000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 796,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/05-Morse/Board/hds/morse_ebs3/struct.bd b/05-Morse/Board/hds/morse_ebs3/struct.bd new file mode 100644 index 0000000..14dfd10 --- /dev/null +++ b/05-Morse/Board/hds/morse_ebs3/struct.bd @@ -0,0 +1,6210 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I3" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 142,0 +) +(Instance +name "I9" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 162,0 +) +(Instance +name "I7" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 188,0 +) +(Instance +name "I8" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 214,0 +) +(Instance +name "I4" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 240,0 +) +(Instance +name "I_dec" +duLibraryName "Morse" +duName "morseDecoder" +elements [ +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +(GiElement +name "uartBaudRate" +type "real" +value "uartBaudRate" +) +(GiElement +name "uartDataBitNb" +type "positive" +value "uartDataBitNb" +) +(GiElement +name "unitDuration" +type "real" +value "morseUnitDuration" +) +(GiElement +name "toneFrequency" +type "real" +value "morseToneFrequency" +) +(GiElement +name "deglitchBitNb" +type "natural" +value "deglitchBitNb" +) +] +mwi 0 +uid 260,0 +) +(Instance +name "I_enc" +duLibraryName "Morse" +duName "morseEncoder" +elements [ +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +(GiElement +name "uartBaudRate" +type "real" +value "uartBaudRate" +) +(GiElement +name "uartDataBitNb" +type "positive" +value "uartDataBitNb" +) +(GiElement +name "unitDuration" +type "real" +value "morseUnitDuration" +) +(GiElement +name "toneFrequency" +type "real" +value "morseToneFrequency" +) +] +mwi 0 +uid 289,0 +) +(Instance +name "I_pll" +duLibraryName "Lattice" +duName "pll" +elements [ +] +mwi 0 +uid 571,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb6" +number "6" +) +(EmbeddedInstance +name "eb7" +number "7" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds\\morse_ebs3\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds\\morse_ebs3\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds\\morse_ebs3" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds\\morse_ebs3" +) +(vvPair +variable "date" +value "08.05.2023" +) +(vvPair +variable "day" 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+:1053C00004000000040000000400000004000000CD +:1053D00004000000040000000400000004000000BD +:1053E00004000000040000000400000004000000AD +:1053F000040000000400000004000000040000009D +:10540000040000000400000004000000040000008C +:10541000040000000400000004000000040000007C +:10542000040000000400000004000000040000006C +:10543000040000000400000004000000040000005C +:10544000040000000400000004000000040000004C +:105450000C000180000000A00C000580000000008E +:105460000C0000800000FAEA0C000180000000B08F +:10547000040000000400000004000000040000001C +:00000001FF diff --git a/05-Morse/Board/ise/morse.xise b/05-Morse/Board/ise/morse.xise new file mode 100644 index 0000000..5a43e34 --- /dev/null +++ b/05-Morse/Board/ise/morse.xise @@ -0,0 +1,331 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/05-Morse/Morse/hdl/charToMorseController_studentVersion.vhd b/05-Morse/Morse/hdl/charToMorseController_studentVersion.vhd new file mode 100644 index 0000000..16c9397 --- /dev/null +++ b/05-Morse/Morse/hdl/charToMorseController_studentVersion.vhd @@ -0,0 +1,54 @@ +ARCHITECTURE studentVersion OF charToMorseController IS + + signal isA, isB, isC, isD, isE, isF, isG, isH, + isI, isJ, isK, isL, isM, isN, isO, isP, + isQ, isR, isS, isT, isU, isV, isW, isX, + isY, isZ, + is0, is1, is2, is3, is4, is5, is6, is7, + is8, is9 : std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- conditions for morse units + isA <= '1' when std_match(unsigned(char), "1-0" & x"1") else '0'; + isB <= '1' when std_match(unsigned(char), "1-0" & x"2") else '0'; + isC <= '1' when std_match(unsigned(char), "1-0" & x"3") else '0'; + isD <= '1' when std_match(unsigned(char), "1-0" & x"4") else '0'; + isE <= '1' when std_match(unsigned(char), "1-0" & x"5") else '0'; + isF <= '1' when std_match(unsigned(char), "1-0" & x"6") else '0'; + isG <= '1' when std_match(unsigned(char), "1-0" & x"7") else '0'; + isH <= '1' when std_match(unsigned(char), "1-0" & x"8") else '0'; + isI <= '1' when std_match(unsigned(char), "1-0" & x"9") else '0'; + isJ <= '1' when std_match(unsigned(char), "1-0" & x"A") else '0'; + isK <= '1' when std_match(unsigned(char), "1-0" & x"B") else '0'; + isL <= '1' when std_match(unsigned(char), "1-0" & x"C") else '0'; + isM <= '1' when std_match(unsigned(char), "1-0" & x"D") else '0'; + isN <= '1' when std_match(unsigned(char), "1-0" & x"E") else '0'; + isO <= '1' when std_match(unsigned(char), "1-0" & x"F") else '0'; + isP <= '1' when std_match(unsigned(char), "1-1" & x"0") else '0'; + isQ <= '1' when std_match(unsigned(char), "1-1" & x"1") else '0'; + isR <= '1' when std_match(unsigned(char), "1-1" & x"2") else '0'; + isS <= '1' when std_match(unsigned(char), "1-1" & x"3") else '0'; + isT <= '1' when std_match(unsigned(char), "1-1" & x"4") else '0'; + isU <= '1' when std_match(unsigned(char), "1-1" & x"5") else '0'; + isV <= '1' when std_match(unsigned(char), "1-1" & x"6") else '0'; + isW <= '1' when std_match(unsigned(char), "1-1" & x"7") else '0'; + isX <= '1' when std_match(unsigned(char), "1-1" & x"8") else '0'; + isY <= '1' when std_match(unsigned(char), "1-1" & x"9") else '0'; + isZ <= '1' when std_match(unsigned(char), "1-1" & x"A") else '0'; + is0 <= '1' when std_match(unsigned(char), "011" & x"0") else '0'; + is1 <= '1' when std_match(unsigned(char), "011" & x"1") else '0'; + is2 <= '1' when std_match(unsigned(char), "011" & x"2") else '0'; + is3 <= '1' when std_match(unsigned(char), "011" & x"3") else '0'; + is4 <= '1' when std_match(unsigned(char), "011" & x"4") else '0'; + is5 <= '1' when std_match(unsigned(char), "011" & x"5") else '0'; + is6 <= '1' when std_match(unsigned(char), "011" & x"6") else '0'; + is7 <= '1' when std_match(unsigned(char), "011" & x"7") else '0'; + is8 <= '1' when std_match(unsigned(char), "011" & x"8") else '0'; + is9 <= '1' when std_match(unsigned(char), "011" & x"9") else '0'; + + morseOut <= '0'; + startCounter <= '0'; + unitNb <= (others => '-'); + +END ARCHITECTURE studentVersion; diff --git a/05-Morse/Morse/hdl/characterRegister_studentVersion.vhd b/05-Morse/Morse/hdl/characterRegister_studentVersion.vhd new file mode 100644 index 0000000..9df6577 --- /dev/null +++ b/05-Morse/Morse/hdl/characterRegister_studentVersion.vhd @@ -0,0 +1,6 @@ +ARCHITECTURE studentVersion OF characterRegister IS +BEGIN + + charOut <= (others => '0'); + +END ARCHITECTURE studentVersion; diff --git a/05-Morse/Morse/hdl/envelopeRetreiver_studentVersion.vhd b/05-Morse/Morse/hdl/envelopeRetreiver_studentVersion.vhd new file mode 100644 index 0000000..9480c30 --- /dev/null +++ b/05-Morse/Morse/hdl/envelopeRetreiver_studentVersion.vhd @@ -0,0 +1,9 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE studentVersion OF envelopeRetreiver IS +BEGIN + + morseEnvelope <= '0'; + +END ARCHITECTURE studentVersion; diff --git a/05-Morse/Morse/hdl/morseToCharDecoder_studentVersion.vhd b/05-Morse/Morse/hdl/morseToCharDecoder_studentVersion.vhd new file mode 100644 index 0000000..33355ef --- /dev/null +++ b/05-Morse/Morse/hdl/morseToCharDecoder_studentVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE studentVersion OF morseToCharDecoder IS +BEGIN + + charValid <= '0'; + charOut <= (others => '0'); + +END ARCHITECTURE studentVersion; diff --git a/05-Morse/Morse/hdl/symbolLengthCounter_studentVersion.vhd b/05-Morse/Morse/hdl/symbolLengthCounter_studentVersion.vhd new file mode 100644 index 0000000..028073d --- /dev/null +++ b/05-Morse/Morse/hdl/symbolLengthCounter_studentVersion.vhd @@ -0,0 +1,11 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE studentVersion OF symbolLengthCounter IS +BEGIN + + symbolValid <= '0'; + symbolValue <= '0'; + symbolDuration <= (others => '0'); + +END ARCHITECTURE studentVersion; diff --git a/05-Morse/Morse/hdl/toneGenerator_studentVersion.vhd b/05-Morse/Morse/hdl/toneGenerator_studentVersion.vhd new file mode 100644 index 0000000..3309e33 --- /dev/null +++ b/05-Morse/Morse/hdl/toneGenerator_studentVersion.vhd @@ -0,0 +1,28 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE studentVersion OF toneGenerator IS + + constant toneCounterBitNb: positive := requiredBitNb(toneDivide-1); + signal toneCounter: unsigned(toneCounterBitNb-1 downto 0); + constant toneMin : natural := (2**toneCounterBitNb - toneDivide) / 2; + constant toneMax : natural := toneMin + toneDivide; + +BEGIN + + divide: process(reset, clock) + begin + if reset = '1' then + toneCounter <= to_unsigned(toneMin, toneCounter'length); + elsif rising_edge(clock) then + if toneCounter = toneMax then + toneCounter <= to_unsigned(toneMin, toneCounter'length); + else + toneCounter <= toneCounter + 1; + end if; + end if; + end process divide; + + tone <= toneCounter(toneCounter'high); + +END ARCHITECTURE studentVersion; diff --git a/05-Morse/Morse/hdl/unitCounter_studentVersion.vhd b/05-Morse/Morse/hdl/unitCounter_studentVersion.vhd new file mode 100644 index 0000000..94e2db7 --- /dev/null +++ b/05-Morse/Morse/hdl/unitCounter_studentVersion.vhd @@ -0,0 +1,61 @@ +library Common; + use Common.CommonLib.all; + +ARCHITECTURE studentVersion OF unitCounter IS + + signal unitCounter: unsigned(requiredBitNb(unitCountDivide)-1 downto 0); + signal unitCountDone: std_ulogic; + signal unitNbCounter: unsigned(unitnB'range); + signal unitNbCountDone: std_ulogic; + +BEGIN + -- count unit base period + countUnitDuration: process(reset, clock) + begin + if reset = '1' then + unitCounter <= (others => '0'); + elsif rising_edge(clock) then + if unitCounter = 0 then + if (startCounter = '1') or (unitNbCounter > 0) then + unitCounter <= unitCounter + 1; + end if; + else + if unitCountDone = '0' then + unitCounter <= unitCounter + 1; + else + unitCounter <= (others => '0'); + end if; + end if; + end if; + end process countUnitDuration; + + unitCountDone <= '1' when unitCounter = unitCountDivide + else '0'; + -- count unit period number + countPeriods: process(reset, clock) + begin + if reset = '1' then + unitNbCounter <= (others => '0'); + elsif rising_edge(clock) then + if unitNbCounter = 0 then + if startCounter = '1' then + unitNbCounter <= unitNbCounter + 1; + end if; + else + if unitNbCountDone = '0' then + if unitCountDone = '1' then + unitNbCounter <= unitNbCounter + 1; + end if; + else + unitNbCounter <= (others => '0'); + end if; + end if; + end if; + end process countPeriods; + + unitNbCountDone <= '1' when (unitNbCounter = unitNb) and (unitCountDone = '1') + else '0'; + + done <= unitNbCountDone; + +END ARCHITECTURE studentVersion; diff --git a/05-Morse/Morse/hds/.hdlsidedata/_charToMorseController_studentVersion.vhd._fpf b/05-Morse/Morse/hds/.hdlsidedata/_charToMorseController_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_charToMorseController_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_characterRegister_studentVersion.vhd._fpf b/05-Morse/Morse/hds/.hdlsidedata/_characterRegister_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_characterRegister_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_chartomorse_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_chartomorse_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_chartomorse_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_chartomorse_struct.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_chartomorse_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_chartomorse_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_chartomorsecontroller_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_chartomorsecontroller_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_chartomorsecontroller_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_chartomorsecontroller_fsm.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_chartomorsecontroller_fsm.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_chartomorsecontroller_fsm.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_envelopeRetreiver_studentVersion.vhd._fpf b/05-Morse/Morse/hds/.hdlsidedata/_envelopeRetreiver_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_envelopeRetreiver_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_enveloperetreiver_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_enveloperetreiver_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_enveloperetreiver_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_morseToCharDecoder_studentVersion.vhd._fpf b/05-Morse/Morse/hds/.hdlsidedata/_morseToCharDecoder_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_morseToCharDecoder_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_morsedecoder_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_morsedecoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_morsedecoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_morsedecoder_struct.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_morsedecoder_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_morsedecoder_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_morseencoder_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_morseencoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_morseencoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_morseencoder_struct.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_morseencoder_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_morseencoder_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_morsetochardecoder_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_morsetochardecoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_morsetochardecoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_symbolLengthCounter_studentVersion.vhd._fpf b/05-Morse/Morse/hds/.hdlsidedata/_symbolLengthCounter_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_symbolLengthCounter_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_symbollengthcounter_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_symbollengthcounter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_symbollengthcounter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_toneGenerator_studentVersion.vhd._fpf b/05-Morse/Morse/hds/.hdlsidedata/_toneGenerator_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_toneGenerator_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_tonegenerator_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_tonegenerator_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_tonegenerator_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_unitCounter_studentVersion.vhd._fpf b/05-Morse/Morse/hds/.hdlsidedata/_unitCounter_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_unitCounter_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/.hdlsidedata/_unitcounter_entity.vhg._fpf b/05-Morse/Morse/hds/.hdlsidedata/_unitcounter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse/hds/.hdlsidedata/_unitcounter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse/hds/_chartomorse._epf b/05-Morse/Morse/hds/_chartomorse._epf new file mode 100644 index 0000000..cc87d16 --- /dev/null +++ b/05-Morse/Morse/hds/_chartomorse._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom char@to@morse/struct.bd +TOP_MARKER atom 0 diff --git a/05-Morse/Morse/hds/_chartomorsecontroller._epf b/05-Morse/Morse/hds/_chartomorsecontroller._epf new file mode 100644 index 0000000..e137cee --- /dev/null +++ b/05-Morse/Morse/hds/_chartomorsecontroller._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom charToMorseController_studentVersion.vhd diff --git a/05-Morse/Morse/hds/_enveloperetreiver._epf b/05-Morse/Morse/hds/_enveloperetreiver._epf new file mode 100644 index 0000000..58aa12d --- /dev/null +++ b/05-Morse/Morse/hds/_enveloperetreiver._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom envelopeRetreiver_studentVersion.vhd +DEFAULT_ARCHITECTURE atom studentVersion diff --git a/05-Morse/Morse/hds/_morsedecoder._epf b/05-Morse/Morse/hds/_morsedecoder._epf new file mode 100644 index 0000000..b8c04b8 --- /dev/null +++ b/05-Morse/Morse/hds/_morsedecoder._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom morse@decoder/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/05-Morse/Morse/hds/_morseencoder._epf b/05-Morse/Morse/hds/_morseencoder._epf new file mode 100644 index 0000000..6d0fb95 --- /dev/null +++ b/05-Morse/Morse/hds/_morseencoder._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom morse@encoder/struct.bd +TOP_MARKER atom 1 diff --git a/05-Morse/Morse/hds/_morsetochardecoder._epf b/05-Morse/Morse/hds/_morsetochardecoder._epf new file mode 100644 index 0000000..d03b627 --- /dev/null +++ b/05-Morse/Morse/hds/_morsetochardecoder._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom morseToCharDecoder_studentVersion.vhd +DEFAULT_ARCHITECTURE atom studentVersion diff --git a/05-Morse/Morse/hds/_symbollengthcounter._epf b/05-Morse/Morse/hds/_symbollengthcounter._epf new file mode 100644 index 0000000..62bd552 --- /dev/null +++ b/05-Morse/Morse/hds/_symbollengthcounter._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom symbolLengthCounter_studentVersion.vhd +DEFAULT_ARCHITECTURE atom studentVersion diff --git a/05-Morse/Morse/hds/_tonegenerator._epf b/05-Morse/Morse/hds/_tonegenerator._epf new file mode 100644 index 0000000..a283cbf --- /dev/null +++ b/05-Morse/Morse/hds/_tonegenerator._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom toneGenerator_studentVersion.vhd diff --git a/05-Morse/Morse/hds/_unitcounter._epf b/05-Morse/Morse/hds/_unitcounter._epf new file mode 100644 index 0000000..e69de29 diff --git a/05-Morse/Morse/hds/char@to@morse/struct.bd b/05-Morse/Morse/hds/char@to@morse/struct.bd new file mode 100644 index 0000000..33e3f89 --- /dev/null +++ b/05-Morse/Morse/hds/char@to@morse/struct.bd @@ -0,0 +1,3809 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_cnt" +duLibraryName "Morse" +duName "unitCounter" +elements [ +(GiElement +name "unitCountDivide" +type "positive" +value "unitCountDivide" +) +(GiElement +name "unitCountBitNb" +type "positive" +value "unitCountBitNb" +) +] +mwi 0 +uid 427,0 +) +(Instance +name "I_ctl" +duLibraryName "Morse" +duName "charToMorseController" +elements [ +(GiElement +name "characterBitNb" +type "positive" +value "characterBitNb" +) +(GiElement +name "unitCountBitNb" +type "positive" +value "unitCountBitNb" +) +] +mwi 0 +uid 806,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "charToMorse" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "14:49:52" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Morse" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Morse" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "charToMorse" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_AsmPath" +value "$HEI_LIBS_DIR/NanoBlaze/hdl" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_WORK_DIR" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "14:49:52" +) +(vvPair +variable "unit" +value "charToMorse" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 134,0 +optionalChildren [ +*1 (PortIoOut +uid 9,0 +shape (CompositeShape +uid 10,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 11,0 +sl 0 +ro 270 +xt "39500,26625,41000,27375" +) +(Line +uid 12,0 +sl 0 +ro 270 +xt "39000,27000,39500,27000" +pts [ +"39000,27000" +"39500,27000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 13,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14,0 +va (VaSet +isHidden 1 +) +xt "42000,26500,47700,27700" +st "morseOut" +blo "42000,27500" +tm "WireNameMgr" +) +) +) +*2 (Net +uid 21,0 +decl (Decl +n "morseOut" +t "std_ulogic" +o 1 +suid 1,0 +) +declText (MLText +uid 22,0 +va (VaSet +) +xt "-5000,6800,9500,8000" +st "morseOut : std_ulogic" +) +) +*3 (PortIoIn +uid 23,0 +shape (CompositeShape +uid 24,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 25,0 +sl 0 +ro 270 +xt "5000,34625,6500,35375" +) +(Line +uid 26,0 +sl 0 +ro 270 +xt "6500,35000,7000,35000" +pts [ +"6500,35000" +"7000,35000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 27,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 28,0 +va (VaSet +isHidden 1 +) +xt "600,34500,4000,35700" +st "clock" +ju 2 +blo "4000,35500" +tm "WireNameMgr" +) +) +) +*4 (Net +uid 35,0 +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 2,0 +) +declText (MLText +uid 36,0 +va (VaSet +) +xt "-5000,7700,8100,8900" +st "clock : std_ulogic" +) +) +*5 (PortIoIn +uid 37,0 +shape (CompositeShape +uid 38,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 39,0 +sl 0 +ro 270 +xt "5000,36625,6500,37375" +) +(Line +uid 40,0 +sl 0 +ro 270 +xt "6500,37000,7000,37000" +pts [ +"6500,37000" +"7000,37000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 41,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 42,0 +va (VaSet +isHidden 1 +) +xt "700,36500,4000,37700" +st "reset" +ju 2 +blo "4000,37500" +tm "WireNameMgr" +) +) +) +*6 (Net +uid 49,0 +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 3,0 +) +declText (MLText +uid 50,0 +va (VaSet +) +xt "-5000,8600,8000,9800" +st "reset : std_ulogic" +) +) +*7 (PortIoIn +uid 65,0 +shape (CompositeShape +uid 66,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 67,0 +sl 0 +ro 270 +xt "5000,26625,6500,27375" +) +(Line +uid 68,0 +sl 0 +ro 270 +xt "6500,27000,7000,27000" +pts [ +"6500,27000" +"7000,27000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 69,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 70,0 +va (VaSet +isHidden 1 +) +xt "0,26500,4000,27700" +st "charIn" +ju 2 +blo "4000,27500" +tm "WireNameMgr" +) +) +) +*8 (Net +uid 77,0 +decl (Decl +n "charIn" +t "std_ulogic_vector" +b "(characterBitNb-1 DOWNTO 0)" +o 4 +suid 5,0 +) +declText (MLText +uid 78,0 +va (VaSet +) +xt "-5000,9500,28800,10700" +st "charIn : std_ulogic_vector(characterBitNb-1 DOWNTO 0)" +) +) +*9 (Grouping +uid 91,0 +optionalChildren [ +*10 (CommentText +uid 93,0 +shape (Rectangle +uid 94,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,65000,70000,66000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 95,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,65500,53200,65500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*11 (CommentText +uid 96,0 +shape (Rectangle +uid 97,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "70000,61000,74000,62000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 98,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "70200,61500,70200,61500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*12 (CommentText +uid 99,0 +shape (Rectangle +uid 100,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,63000,70000,64000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 101,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,63500,53200,63500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*13 (CommentText +uid 102,0 +shape (Rectangle +uid 103,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "49000,63000,53000,64000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 104,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "49200,63500,49200,63500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*14 (CommentText +uid 105,0 +shape (Rectangle +uid 106,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "70000,62000,90000,66000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 107,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "70200,62200,84300,63400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*15 (CommentText +uid 108,0 +shape (Rectangle +uid 109,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "74000,61000,90000,62000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 110,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "74200,61500,74200,61500" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*16 (CommentText +uid 111,0 +shape (Rectangle +uid 112,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "49000,61000,70000,63000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 113,0 +va (VaSet +fg "32768,0,0" +) +xt "54350,61400,64650,62600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*17 (CommentText +uid 114,0 +shape (Rectangle +uid 115,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "49000,64000,53000,65000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 116,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "49200,64500,49200,64500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*18 (CommentText +uid 117,0 +shape (Rectangle +uid 118,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "49000,65000,53000,66000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 119,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "49200,65500,49200,65500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*19 (CommentText +uid 120,0 +shape (Rectangle +uid 121,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,64000,70000,65000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 122,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,64500,53200,64500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 92,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "49000,61000,90000,66000" +) +oxt "14000,66000,55000,71000" +) +*20 (Net +uid 365,0 +decl (Decl +n "startCounter" +t "std_ulogic" +o 6 +suid 6,0 +) +declText (MLText +uid 366,0 +va (VaSet +) +xt "-5000,14900,14200,16100" +st "SIGNAL startCounter : std_ulogic" +) +) +*21 (Net +uid 371,0 +decl (Decl +n "done" +t "std_ulogic" +o 7 +suid 7,0 +) +declText (MLText +uid 372,0 +va (VaSet +) +xt "-5000,15800,12600,17000" +st "SIGNAL done : std_ulogic" +) +) +*22 (Net +uid 377,0 +decl (Decl +n "unitNb" +t "unsigned" +b "(unitCountBitNb-1 downto 0)" +o 8 +suid 8,0 +) +declText (MLText +uid 378,0 +va (VaSet +) +xt "-5000,16700,27400,17900" +st "SIGNAL unitNb : unsigned(unitCountBitNb-1 downto 0)" +) +) +*23 (SaComponent +uid 427,0 +optionalChildren [ +*24 (CptPort +uid 407,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 408,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46250,36625,47000,37375" +) +tg (CPTG +uid 409,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 410,0 +va (VaSet +) +xt "48000,36400,51400,37600" +st "clock" +blo "48000,37400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 2008,0 +) +) +) +*25 (CptPort +uid 411,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 412,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46250,38625,47000,39375" +) +tg (CPTG +uid 413,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 414,0 +va (VaSet +) +xt "48000,38400,51300,39600" +st "reset" +blo "48000,39400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 2009,0 +) +) +) +*26 (CptPort +uid 415,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 416,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46250,30625,47000,31375" +) +tg (CPTG +uid 417,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 418,0 +va (VaSet +) +xt "48000,30400,55800,31600" +st "startCounter" +blo "48000,31400" +) +) +thePort (LogicalPort +decl (Decl +n "startCounter" +t "std_ulogic" +o 3 +suid 2012,0 +) +) +) +*27 (CptPort +uid 419,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 420,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46250,32625,47000,33375" +) +tg (CPTG +uid 421,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" 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+variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse@controller" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorseController" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "charToMorseController" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "fsm.sm" +) +(vvPair +variable "f_logical" +value "fsm.sm" +) +(vvPair +variable "f_noext" +value "fsm" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value 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"4299,19850,4599,20150" +radius 150 +) +] +) +cond (SmControlCondition +uid 78,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 79,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +lineColor "0,32768,49152" +) +xt "1650,17950,8050,19050" +) +autoResize 1 +cond (MLText +uid 80,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "1750,18050,6950,19050" +st "reset = '1'" +tm "SmControlConditionMgr" +) +) +prio (TransitionPriority +uid 75,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 76,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "5500,19219,7062,20781" +radius 781 +) +pr (Text +uid 77,0 +va (VaSet +isHidden 1 +) +xt "5581,19500,6981,20700" +st "1" +ju 0 +blo "6281,20500" +tm "TransitionPriority" +) +padding "100,100" +) +name (TextAssociate +uid 73,0 +ps "CenterOffsetStrategy" +text (Text +uid 74,0 +va (VaSet +font "Verdana,8,0" +) +xt "750,19500,3250,20500" +st "reset" +ju 2 +blo "3250,20300" +tm "SmControlSignalNameMgr" +) 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"65535,65535,0" +lineWidth 1 +) +xt "3724,14574,4576,15426" +pts [ +"3724,15426" +"4576,14574" +] +) +(Line +uid 93,0 +sl 0 +va (VaSet +vasetType 3 +lineColor "65535,65535,0" +lineWidth 1 +) +xt "3724,14574,4576,15426" +pts [ +"4576,15426" +"3724,14574" +] +) +] +) +) +*7 (Link +uid 94,0 +shape (CompositeShape +uid 95,0 +va (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +optionalChildren [ +(Pentagon +uid 96,0 +sl 0 +ro 270 +xt "17000,14500,19250,15500" +) +(Line +uid 97,0 +sl 0 +ro 270 +xt "16500,15000,17000,15000" +pts [ +"16500,15000" +"17000,15000" +] +) +] +) +name (TextAssociate +uid 98,0 +ps "CenterOffsetStrategy" +text (Text +uid 99,0 +va (VaSet +font "Verdana,8,1" +) +xt "19750,14500,26550,15500" +st "waitForChar" +blo "19750,15300" +tm "LinkName" +) +) +) +*8 (Grouping +uid 120,0 +optionalChildren [ +*9 (CommentText +uid 122,0 +shape (Rectangle +uid 123,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "223000,170000,240000,171000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 124,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "223200,170500,223200,170500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*10 (CommentText +uid 125,0 +shape (Rectangle +uid 126,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "240000,166000,244000,167000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 127,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "240200,166500,240200,166500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*11 (CommentText +uid 128,0 +shape (Rectangle +uid 129,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "223000,168000,240000,169000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 130,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "223200,168500,223200,168500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*12 (CommentText +uid 131,0 +shape (Rectangle +uid 132,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "219000,168000,223000,169000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 133,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "219200,168500,219200,168500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*13 (CommentText +uid 134,0 +shape (Rectangle +uid 135,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "240000,167000,260000,171000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 136,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "240200,167200,254300,168400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*14 (CommentText +uid 137,0 +shape (Rectangle +uid 138,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "244000,166000,260000,167000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 139,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "244200,166500,244200,166500" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*15 (CommentText +uid 140,0 +shape (Rectangle +uid 141,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "219000,166000,240000,168000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 142,0 +va (VaSet +fg "32768,0,0" +) +xt "224350,166400,234650,167600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*16 (CommentText +uid 143,0 +shape (Rectangle +uid 144,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "219000,169000,223000,170000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 145,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "219200,169500,219200,169500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*17 (CommentText +uid 146,0 +shape (Rectangle +uid 147,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "219000,170000,223000,171000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 148,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "219200,170500,219200,170500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*18 (CommentText +uid 149,0 +shape (Rectangle +uid 150,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "223000,169000,240000,170000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 151,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "223200,169500,223200,169500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 121,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "219000,166000,260000,171000" +) +oxt "14000,66000,55000,71000" +) +*19 (State +uid 164,0 +shape (Circle +uid 165,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "61000,14000,77000,30000" +radius 8000 +) +name (Text +uid 166,0 +va (VaSet +font "Verdana,12,1" +) +xt "65300,21300,72700,22700" +st "storeChar" +ju 0 +blo "69000,22500" +tm "ONodeName" +) +wait (TextAssociate +uid 167,0 +ps "CenterOffsetStrategy" +text (Text +uid 168,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "69100,22200,73200,23400" +st "wait 2" +blo "69100,23200" +tm "SmWaitText" +) +) +encoding (Text +uid 169,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "69000,23100,69000,23100" +blo "69000,23100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 172,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 173,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "68900,24900,69100,25100" +) +autoResize 1 +tline (Line +uid 174,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "63900,24300,74100,24300" +pts [ +"63900,24300" +"74100,24300" +] +) +bline (Line +uid 175,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "63900,23650,74100,23650" +pts [ +"63900,23650" +"74100,23650" +] +) +ttri (Triangle +uid 176,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "64550,23925,64900,24275" +) +btri (Triangle +uid 177,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "64550,21625,64900,21975" +) +entryActions (MLText +uid 178,0 +va (VaSet +) +xt "63900,24100,63900,24100" +tm "Actions" +) +inActions (MLText +uid 179,0 +va (VaSet +) +xt "63900,24500,74100,25500" +tm "Actions" +) +exitActions (MLText +uid 180,0 +va (VaSet +) +xt "65000,21800,65000,21800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 170,0 +ps "CenterOffsetStrategy" +text (MLText +uid 171,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "67400,23000,73500,24000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*20 (State +uid 191,0 +shape (Circle +uid 192,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "99000,14000,115000,30000" +radius 8000 +) +name (Text +uid 193,0 +va (VaSet +font "Verdana,12,1" +) +xt "101750,21300,112250,22700" +st "sendDotStart" +ju 0 +blo "107000,22500" +tm "ONodeName" +) +wait (TextAssociate +uid 194,0 +ps "CenterOffsetStrategy" +text (Text +uid 195,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "107100,22200,111200,23400" +st "wait 2" +blo "107100,23200" +tm "SmWaitText" +) +) +encoding (Text +uid 196,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "107000,23100,107000,23100" +blo "107000,23100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 199,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 200,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "100650,25400,108650,26600" +) +autoResize 1 +tline (Line +uid 201,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "100750,25300,108550,25300" +pts [ +"100750,25300" +"108550,25300" +] +) +bline (Line +uid 202,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "100750,24650,108550,24650" +pts [ +"100750,24650" +"108550,24650" +] +) +ttri (Triangle +uid 203,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "100300,24925,100650,25275" +) +btri (Triangle +uid 204,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "100300,22625,100650,22975" +) +entryActions (MLText +uid 205,0 +va (VaSet +) +xt "100750,25100,100750,25100" +tm "Actions" +) +inActions (MLText +uid 206,0 +va (VaSet +) +xt "100750,25500,112950,26700" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 207,0 +va (VaSet +) +xt "100650,22800,100650,22800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 197,0 +ps "CenterOffsetStrategy" +text (MLText +uid 198,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "105400,23000,111500,24000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*21 (State +uid 325,0 +shape (Circle +uid 326,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "121000,14000,137000,30000" +radius 8000 +) +name (Text +uid 327,0 +va (VaSet +font "Verdana,12,1" +) +xt "123850,21300,134150,22700" +st "sendDotWait" +ju 0 +blo "129000,22500" +tm "ONodeName" +) +wait (TextAssociate +uid 328,0 +ps "CenterOffsetStrategy" +text (Text +uid 329,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "129100,22200,133200,23400" +st "wait 2" +blo "129100,23200" +tm "SmWaitText" +) +) +encoding (Text +uid 330,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "129000,23100,129000,23100" +blo "129000,23100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 333,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 334,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "121200,23900,136800,26100" +) +autoResize 1 +tline (Line +uid 335,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "121300,23800,136700,23800" +pts [ +"121300,23800" +"136700,23800" +] +) +bline (Line +uid 336,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "121300,23900,136700,23900" +pts [ +"121300,23900" +"136700,23900" +] +) +ttri (Triangle +uid 337,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "120850,23425,121200,23775" +) +btri (Triangle +uid 338,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "120850,21625,121200,21975" +) +entryActions (MLText +uid 339,0 +va (VaSet +) +xt "121300,23600,121300,23600" +tm "Actions" +) +inActions (MLText +uid 340,0 +va (VaSet +) +xt "121300,24000,144700,26400" +st "unitNb <= to_unsigned(1, unitNb'length); +morseOut <= '1';" +tm "Actions" +) +exitActions (MLText +uid 341,0 +va (VaSet +) +xt "125000,21800,125000,21800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 331,0 +ps "CenterOffsetStrategy" +text (MLText +uid 332,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "127400,23000,133500,24000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*22 (State +uid 364,0 +shape (Circle +uid 365,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "143416,13416,160584,30584" +radius 8584 +) +name (Text +uid 366,0 +va (VaSet +font "Verdana,12,1" +) +xt "144450,21300,159550,22700" +st "sendDotSpacerStart" +ju 0 +blo "152000,22500" +tm "ONodeName" +) +wait (TextAssociate +uid 367,0 +ps "CenterOffsetStrategy" +text (Text +uid 368,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "152100,22200,156200,23400" +st "wait 2" +blo "152100,23200" +tm "SmWaitText" +) +) +encoding (Text +uid 369,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "152000,23100,152000,23100" +blo "152000,23100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 372,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 373,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "149000,24400,157000,25600" +) +autoResize 1 +tline (Line +uid 374,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "149100,24300,156900,24300" +pts [ +"149100,24300" +"156900,24300" +] +) +bline (Line +uid 375,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "149100,23650,156900,23650" +pts [ +"149100,23650" +"156900,23650" +] +) +ttri (Triangle +uid 376,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "148650,23925,149000,24275" +) +btri (Triangle +uid 377,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "148650,21625,149000,21975" +) +entryActions (MLText +uid 378,0 +va (VaSet +) +xt "149100,24100,149100,24100" +tm "Actions" +) +inActions (MLText +uid 379,0 +va (VaSet +) +xt "149100,24500,161300,25700" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 380,0 +va (VaSet +) +xt "149000,21800,149000,21800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 370,0 +ps "CenterOffsetStrategy" +text (MLText +uid 371,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "150400,23000,156500,24000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*23 (State +uid 381,0 +shape (Circle +uid 382,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "165515,13515,182485,30485" +radius 8485 +) +name (Text +uid 383,0 +va (VaSet +font "Verdana,12,1" +) +xt "166550,21300,181450,22700" +st "sendDotSpacerWait" +ju 0 +blo "174000,22500" +tm "ONodeName" +) +wait (TextAssociate +uid 384,0 +ps "CenterOffsetStrategy" +text (Text +uid 385,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "174100,22200,178200,23400" +st "wait 2" +blo "174100,23200" +tm "SmWaitText" +) +) +encoding (Text +uid 386,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "174000,23100,174000,23100" +blo "174000,23100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 389,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 390,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "166200,24400,181800,25600" +) +autoResize 1 +tline (Line +uid 391,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "166300,24300,181700,24300" +pts [ +"166300,24300" +"181700,24300" +] +) +bline (Line +uid 392,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "166300,23650,181700,23650" +pts [ +"166300,23650" +"181700,23650" +] +) +ttri (Triangle +uid 393,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "165850,23925,166200,24275" +) +btri (Triangle +uid 394,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "165850,21625,166200,21975" +) +entryActions (MLText +uid 395,0 +va (VaSet +) +xt "166300,24100,166300,24100" +tm "Actions" +) +inActions (MLText +uid 396,0 +va (VaSet +) +xt "166300,24500,189700,25700" +st "unitNb <= to_unsigned(1, unitNb'length);" +tm "Actions" +) +exitActions (MLText +uid 397,0 +va (VaSet +) +xt "170000,21800,170000,21800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 387,0 +ps "CenterOffsetStrategy" +text (MLText +uid 388,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "172400,23000,178500,24000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*24 (State +uid 428,0 +shape (Circle +uid 429,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "204000,14000,220000,30000" +radius 8000 +) +name (Text +uid 430,0 +va (VaSet +font "Verdana,12,1" +) +xt "205600,21300,218400,22700" +st "sendDotDotStart" +ju 0 +blo "212000,22500" +tm "ONodeName" +) +wait (TextAssociate +uid 431,0 +ps "CenterOffsetStrategy" +text (Text +uid 432,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "212100,22200,216200,23400" +st "wait 2" +blo "212100,23200" +tm "SmWaitText" +) +) +encoding (Text +uid 433,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "212000,23100,212000,23100" +blo "212000,23100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 436,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 437,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "208000,24400,216000,25600" +) +autoResize 1 +tline (Line +uid 438,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "208100,24300,215900,24300" +pts [ +"208100,24300" +"215900,24300" +] +) +bline (Line +uid 439,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "208100,23650,215900,23650" +pts [ +"208100,23650" +"215900,23650" +] +) +ttri (Triangle +uid 440,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "207650,23925,208000,24275" +) +btri (Triangle +uid 441,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "207650,21625,208000,21975" +) +entryActions (MLText +uid 442,0 +va (VaSet +) +xt "208100,24100,208100,24100" +tm "Actions" +) +inActions (MLText +uid 443,0 +va (VaSet +) +xt "208100,24500,220300,25700" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 444,0 +va (VaSet +) +xt "208000,21800,208000,21800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 434,0 +ps "CenterOffsetStrategy" +text (MLText +uid 435,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "210400,23000,216500,24000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*25 (State +uid 445,0 +shape (Circle +uid 446,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "226000,14000,242000,30000" +radius 8000 +) +name (Text +uid 447,0 +va (VaSet +font "Verdana,12,1" +) +xt "227700,21300,240300,22700" +st "sendDotDotWait" +ju 0 +blo "234000,22500" +tm "ONodeName" +) +wait (TextAssociate +uid 448,0 +ps "CenterOffsetStrategy" +text (Text +uid 449,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "234100,22200,238200,23400" +st "wait 2" +blo "234100,23200" +tm "SmWaitText" +) +) +encoding (Text +uid 450,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "234000,23100,234000,23100" +blo "234000,23100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 453,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 454,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "229200,23900,244800,26100" +) +autoResize 1 +tline (Line +uid 455,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "229300,23800,244700,23800" +pts [ +"229300,23800" +"244700,23800" +] +) +bline (Line +uid 456,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "229300,23900,244700,23900" +pts [ +"229300,23900" +"244700,23900" +] +) +ttri (Triangle +uid 457,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "228850,23425,229200,23775" +) +btri (Triangle +uid 458,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "228850,21625,229200,21975" +) +entryActions (MLText +uid 459,0 +va (VaSet +) +xt "229300,23600,229300,23600" +tm "Actions" +) +inActions (MLText +uid 460,0 +va (VaSet +) +xt "229300,24000,252700,26400" +st "unitNb <= to_unsigned(1, unitNb'length); +morseOut <= '1';" +tm "Actions" +) +exitActions (MLText +uid 461,0 +va (VaSet +) +xt "233000,21800,233000,21800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 451,0 +ps "CenterOffsetStrategy" +text (MLText +uid 452,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "232400,23000,238500,24000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*26 (State +uid 502,0 +shape (Circle +uid 503,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "203614,48614,220386,65386" +radius 8386 +) +name (Text +uid 504,0 +va (VaSet +font "Verdana,12,1" +) +xt "205100,56300,218900,57700" +st "sendDotDashStart" +ju 0 +blo "212000,57500" +tm "ONodeName" +) +wait (TextAssociate +uid 505,0 +ps "CenterOffsetStrategy" +text (Text +uid 506,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "212100,57200,216200,58400" +st "wait 2" +blo "212100,58200" +tm "SmWaitText" +) +) +encoding (Text +uid 507,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "212000,58100,212000,58100" +blo "212000,58100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 510,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 511,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "208000,59400,216000,60600" +) +autoResize 1 +tline (Line +uid 512,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "208100,59300,215900,59300" +pts [ +"208100,59300" +"215900,59300" +] +) +bline (Line +uid 513,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "208100,58650,215900,58650" +pts [ +"208100,58650" +"215900,58650" +] +) +ttri (Triangle +uid 514,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "207650,58925,208000,59275" +) +btri (Triangle +uid 515,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "207650,56625,208000,56975" +) +entryActions (MLText +uid 516,0 +va (VaSet +) +xt "208100,59100,208100,59100" +tm "Actions" +) +inActions (MLText +uid 517,0 +va (VaSet +) +xt "208100,59500,220300,60700" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 518,0 +va (VaSet +) +xt "208000,56800,208000,56800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 508,0 +ps "CenterOffsetStrategy" +text (MLText +uid 509,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "210400,58000,216500,59000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*27 (State +uid 519,0 +shape (Circle +uid 520,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "225713,48713,242287,65287" +radius 8287 +) +name (Text +uid 521,0 +va (VaSet +font "Verdana,12,1" +) +xt "227200,56300,240800,57700" +st "sendDotDashWait" +ju 0 +blo "234000,57500" +tm "ONodeName" +) +wait (TextAssociate +uid 522,0 +ps "CenterOffsetStrategy" +text (Text +uid 523,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "234100,57200,238200,58400" +st "wait 2" +blo "234100,58200" +tm "SmWaitText" +) +) +encoding (Text +uid 524,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "234000,58100,234000,58100" +blo "234000,58100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 527,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 528,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "229200,58900,244800,61100" +) +autoResize 1 +tline (Line +uid 529,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "229300,58800,244700,58800" +pts [ +"229300,58800" +"244700,58800" +] +) +bline (Line +uid 530,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "229300,58900,244700,58900" +pts [ +"229300,58900" +"244700,58900" +] +) +ttri (Triangle +uid 531,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "228850,58425,229200,58775" +) +btri (Triangle +uid 532,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "228850,56625,229200,56975" +) +entryActions (MLText +uid 533,0 +va (VaSet +) +xt "229300,58600,229300,58600" +tm "Actions" +) +inActions (MLText +uid 534,0 +va (VaSet +) +xt "229300,59000,252700,61400" +st "unitNb <= to_unsigned(3, unitNb'length); +morseOut <= '1';" +tm "Actions" +) +exitActions (MLText +uid 535,0 +va (VaSet +) +xt "233000,56800,233000,56800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 525,0 +ps "CenterOffsetStrategy" +text (MLText +uid 526,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "232400,58000,238500,59000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*28 (State +uid 586,0 +shape (Circle +uid 587,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "101000,109000,117000,125000" +radius 8000 +) +name (Text +uid 588,0 +va (VaSet +font "Verdana,12,1" +) +xt "103250,116300,114750,117700" +st "sendDashStart" +ju 0 +blo "109000,117500" +tm "ONodeName" +) +wait (TextAssociate +uid 589,0 +ps "CenterOffsetStrategy" +text (Text +uid 590,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "109100,117200,113200,118400" +st "wait 2" +blo "109100,118200" +tm "SmWaitText" +) +) +encoding (Text +uid 591,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "109000,118100,109000,118100" +blo "109000,118100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 594,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 595,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "109000,119600,117000,120800" +) +autoResize 1 +tline (Line +uid 596,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "109100,119500,116900,119500" +pts [ +"109100,119500" +"116900,119500" +] +) +bline (Line +uid 597,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "109100,118850,116900,118850" +pts [ +"109100,118850" +"116900,118850" +] +) +ttri (Triangle +uid 598,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "108650,119125,109000,119475" +) +btri (Triangle +uid 599,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "108650,116825,109000,117175" +) +entryActions (MLText +uid 600,0 +va (VaSet +) +xt "109100,119300,109100,119300" +tm "Actions" +) +inActions (MLText +uid 601,0 +va (VaSet +) +xt "109100,119700,121300,120900" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 602,0 +va (VaSet +) +xt "109000,117000,109000,117000" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 592,0 +ps "CenterOffsetStrategy" +text (MLText +uid 593,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "107400,118000,113500,119000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*29 (State +uid 603,0 +shape (Circle +uid 604,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "123000,109000,139000,125000" +radius 8000 +) +name (Text +uid 605,0 +va (VaSet +font "Verdana,12,1" +) +xt "125350,116300,136650,117700" +st "sendDashWait" +ju 0 +blo "131000,117500" +tm "ONodeName" +) +wait (TextAssociate +uid 606,0 +ps "CenterOffsetStrategy" +text (Text +uid 607,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "131100,117200,135200,118400" +st "wait 2" +blo "131100,118200" +tm "SmWaitText" +) +) +encoding (Text +uid 608,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "131000,118100,131000,118100" +blo "131000,118100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 611,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 612,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "123200,118900,138800,121100" +) +autoResize 1 +tline (Line +uid 613,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "123300,118800,138700,118800" +pts [ +"123300,118800" +"138700,118800" +] +) +bline (Line +uid 614,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "123300,118900,138700,118900" +pts [ +"123300,118900" +"138700,118900" +] +) +ttri (Triangle +uid 615,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "122850,118425,123200,118775" +) +btri (Triangle +uid 616,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "122850,116625,123200,116975" +) +entryActions (MLText +uid 617,0 +va (VaSet +) +xt "123300,118600,123300,118600" +tm "Actions" +) +inActions (MLText +uid 618,0 +va (VaSet +) +xt "123300,119000,146700,121400" +st "unitNb <= to_unsigned(3, unitNb'length); +morseOut <= '1';" +tm "Actions" +) +exitActions (MLText +uid 619,0 +va (VaSet +) +xt "127000,116800,127000,116800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 609,0 +ps "CenterOffsetStrategy" +text (MLText +uid 610,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "129400,118000,135500,119000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*30 (State +uid 620,0 +shape (Circle +uid 621,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "144524,107524,163476,126476" +radius 9476 +) +name (Text +uid 622,0 +va (VaSet +font "Verdana,12,1" +) +xt "145950,116300,162050,117700" +st "sendDahsSpacerStart" +ju 0 +blo "154000,117500" +tm "ONodeName" +) +wait (TextAssociate +uid 623,0 +ps "CenterOffsetStrategy" +text (Text +uid 624,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "154100,117200,158200,118400" +st "wait 2" +blo "154100,118200" +tm "SmWaitText" +) +) +encoding (Text +uid 625,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "154000,118100,154000,118100" +blo "154000,118100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 628,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 629,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "151000,119400,159000,120600" +) +autoResize 1 +tline (Line +uid 630,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "151100,119300,158900,119300" +pts [ +"151100,119300" +"158900,119300" +] +) +bline (Line +uid 631,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "151100,118650,158900,118650" +pts [ +"151100,118650" +"158900,118650" +] +) +ttri (Triangle +uid 632,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "150650,118925,151000,119275" +) +btri (Triangle +uid 633,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "150650,116625,151000,116975" +) +entryActions (MLText +uid 634,0 +va (VaSet +) +xt "151100,119100,151100,119100" +tm "Actions" +) +inActions (MLText +uid 635,0 +va (VaSet +) +xt "151100,119500,163300,120700" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 636,0 +va (VaSet +) +xt "151000,116800,151000,116800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 626,0 +ps "CenterOffsetStrategy" +text (MLText +uid 627,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "152400,118000,158500,119000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*31 (State +uid 637,0 +shape (Circle +uid 638,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "167070,108070,184930,125930" +radius 8930 +) +name (Text +uid 639,0 +va (VaSet +font "Verdana,12,1" +) +xt "168050,116300,183950,117700" +st "sendDashSpacerWait" +ju 0 +blo "176000,117500" +tm "ONodeName" +) +wait (TextAssociate +uid 640,0 +ps "CenterOffsetStrategy" +text (Text +uid 641,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "176100,117200,180200,118400" +st "wait 2" +blo "176100,118200" +tm "SmWaitText" +) +) +encoding (Text +uid 642,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "176000,118100,176000,118100" +blo "176000,118100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 645,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 646,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "168200,119400,183800,120600" +) +autoResize 1 +tline (Line +uid 647,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "168300,119300,183700,119300" +pts [ +"168300,119300" +"183700,119300" +] +) +bline (Line +uid 648,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "168300,118650,183700,118650" +pts [ +"168300,118650" +"183700,118650" +] +) +ttri (Triangle +uid 649,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "167850,118925,168200,119275" +) +btri (Triangle +uid 650,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "167850,116625,168200,116975" +) +entryActions (MLText +uid 651,0 +va (VaSet +) +xt "168300,119100,168300,119100" +tm "Actions" +) +inActions (MLText +uid 652,0 +va (VaSet +) +xt "168300,119500,191700,120700" +st "unitNb <= to_unsigned(1, unitNb'length);" +tm "Actions" +) +exitActions (MLText +uid 653,0 +va (VaSet +) +xt "172000,116800,172000,116800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 643,0 +ps "CenterOffsetStrategy" +text (MLText +uid 644,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "174400,118000,180500,119000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*32 (State +uid 654,0 +shape (Circle +uid 655,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "205664,108664,222336,125336" +radius 8336 +) +name (Text +uid 656,0 +va (VaSet +font "Verdana,12,1" +) +xt "207100,116300,220900,117700" +st "sendDashDotStart" +ju 0 +blo "214000,117500" +tm "ONodeName" +) +wait (TextAssociate +uid 657,0 +ps "CenterOffsetStrategy" +text (Text +uid 658,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "214100,117200,218200,118400" +st "wait 2" +blo "214100,118200" +tm "SmWaitText" +) +) +encoding (Text +uid 659,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "214000,118100,214000,118100" +blo "214000,118100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 662,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 663,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "210000,119400,218000,120600" +) +autoResize 1 +tline (Line +uid 664,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "210100,119300,217900,119300" +pts [ +"210100,119300" +"217900,119300" +] +) +bline (Line +uid 665,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "210100,118650,217900,118650" +pts [ +"210100,118650" +"217900,118650" +] +) +ttri (Triangle +uid 666,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "209650,118925,210000,119275" +) +btri (Triangle +uid 667,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "209650,116625,210000,116975" +) +entryActions (MLText +uid 668,0 +va (VaSet +) +xt "210100,119100,210100,119100" +tm "Actions" +) +inActions (MLText +uid 669,0 +va (VaSet +) +xt "210100,119500,222300,120700" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 670,0 +va (VaSet +) +xt "210000,116800,210000,116800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 660,0 +ps "CenterOffsetStrategy" +text (MLText +uid 661,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "212400,118000,218500,119000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*33 (State +uid 671,0 +shape (Circle +uid 672,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "205169,143169,222831,160831" +radius 8831 +) +name (Text +uid 673,0 +va (VaSet +font "Verdana,12,1" +) +xt "206600,151300,221400,152700" +st "sendDashDashStart" +ju 0 +blo "214000,152500" +tm "ONodeName" +) +wait (TextAssociate +uid 674,0 +ps "CenterOffsetStrategy" +text (Text +uid 675,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "214100,152200,218200,153400" +st "wait 2" +blo "214100,153200" +tm "SmWaitText" +) +) +encoding (Text +uid 676,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "214000,153100,214000,153100" +blo "214000,153100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 679,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 680,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "210000,154400,218000,155600" +) +autoResize 1 +tline (Line +uid 681,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "210100,154300,217900,154300" +pts [ +"210100,154300" +"217900,154300" +] +) +bline (Line +uid 682,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "210100,153650,217900,153650" +pts [ +"210100,153650" +"217900,153650" +] +) +ttri (Triangle +uid 683,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "209650,153925,210000,154275" +) +btri (Triangle +uid 684,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "209650,151625,210000,151975" +) +entryActions (MLText +uid 685,0 +va (VaSet +) +xt "210100,154100,210100,154100" +tm "Actions" +) +inActions (MLText +uid 686,0 +va (VaSet +) +xt "210100,154500,222300,155700" +st "startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 687,0 +va (VaSet +) +xt "210000,151800,210000,151800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 677,0 +ps "CenterOffsetStrategy" +text (MLText +uid 678,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "212400,153000,218500,154000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*34 (State +uid 688,0 +shape (Circle +uid 689,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "227763,108763,244237,125237" +radius 8237 +) +name (Text +uid 690,0 +va (VaSet +font "Verdana,12,1" +) +xt "229200,116300,242800,117700" +st "sendDashDotWait" +ju 0 +blo "236000,117500" +tm "ONodeName" +) +wait (TextAssociate +uid 691,0 +ps "CenterOffsetStrategy" +text (Text +uid 692,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "236100,117200,240200,118400" +st "wait 2" +blo "236100,118200" +tm "SmWaitText" +) +) +encoding (Text +uid 693,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "236000,118100,236000,118100" +blo "236000,118100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 696,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 697,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "231200,118900,246800,121100" +) +autoResize 1 +tline (Line +uid 698,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "231300,118800,246700,118800" +pts [ +"231300,118800" +"246700,118800" +] +) +bline (Line +uid 699,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "231300,118900,246700,118900" +pts [ +"231300,118900" +"246700,118900" +] +) +ttri (Triangle +uid 700,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "230850,118425,231200,118775" +) +btri (Triangle +uid 701,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "230850,116625,231200,116975" +) +entryActions (MLText +uid 702,0 +va (VaSet +) +xt "231300,118600,231300,118600" +tm "Actions" +) +inActions (MLText +uid 703,0 +va (VaSet +) +xt "231300,119000,254700,121400" +st "unitNb <= to_unsigned(1, unitNb'length); +morseOut <= '1';" +tm "Actions" +) +exitActions (MLText +uid 704,0 +va (VaSet +) +xt "235000,116800,235000,116800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 694,0 +ps "CenterOffsetStrategy" +text (MLText +uid 695,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "234400,118000,240500,119000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*35 (State +uid 705,0 +shape (Circle +uid 706,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "227268,143268,244732,160732" +radius 8732 +) +name (Text +uid 707,0 +va (VaSet +font "Verdana,12,1" +) +xt "228700,151300,243300,152700" +st "sendDashDashWait" +ju 0 +blo "236000,152500" +tm "ONodeName" +) +wait (TextAssociate +uid 708,0 +ps "CenterOffsetStrategy" +text (Text +uid 709,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "236100,152200,240200,153400" +st "wait 2" +blo "236100,153200" +tm "SmWaitText" +) +) +encoding (Text +uid 710,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "236000,153100,236000,153100" +blo "236000,153100" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 713,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 714,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "231200,153900,246800,156100" +) +autoResize 1 +tline (Line +uid 715,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "231300,153800,246700,153800" +pts [ +"231300,153800" +"246700,153800" +] +) +bline (Line +uid 716,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "231300,153900,246700,153900" +pts [ +"231300,153900" +"246700,153900" +] +) +ttri (Triangle +uid 717,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "230850,153425,231200,153775" +) +btri (Triangle +uid 718,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "230850,151625,231200,151975" +) +entryActions (MLText +uid 719,0 +va (VaSet +) +xt "231300,153600,231300,153600" +tm "Actions" +) +inActions (MLText +uid 720,0 +va (VaSet +) +xt "231300,154000,254700,156400" +st "unitNb <= to_unsigned(3, unitNb'length); +morseOut <= '1';" +tm "Actions" +) +exitActions (MLText +uid 721,0 +va (VaSet +) +xt "235000,151800,235000,151800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 711,0 +ps "CenterOffsetStrategy" +text (MLText +uid 712,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "234400,153000,240500,154000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*36 (State +uid 1027,0 +shape (Circle +uid 1028,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "31000,46000,47000,62000" +radius 8000 +) +name (Text +uid 1029,0 +va (VaSet +font "Verdana,12,1" +) +xt "35800,53350,42200,54750" +st "popChar" +ju 0 +blo "39000,54550" +tm "ONodeName" +) +wait (TextAssociate +uid 1030,0 +ps "CenterOffsetStrategy" +text (Text +uid 1031,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "39100,54250,43200,55450" +st "wait 2" +blo "39100,55250" +tm "SmWaitText" +) +) +encoding (Text +uid 1032,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "39000,55050,39000,55050" +blo "39000,55050" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1035,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1036,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "26600,56400,51400,57600" +) +autoResize 1 +tline (Line +uid 1037,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "26700,56300,51300,56300" +pts [ +"26700,56300" +"51300,56300" +] +) +bline (Line +uid 1038,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "26700,55650,51300,55650" +pts [ +"26700,55650" +"51300,55650" +] +) +ttri (Triangle +uid 1039,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "26250,55925,26600,56275" +) +btri (Triangle +uid 1040,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "26250,53625,26600,53975" +) +entryActions (MLText +uid 1041,0 +va (VaSet +) +xt "26700,56100,26700,56100" +tm "Actions" +) +inActions (MLText +uid 1042,0 +va (VaSet +) +xt "26700,56500,50100,57700" +st "unitNb <= to_unsigned(3, unitNb'length);" +tm "Actions" +) +exitActions (MLText +uid 1043,0 +va (VaSet +) +xt "35000,53800,35000,53800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1033,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1034,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "37400,55000,43500,56000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*37 (State +uid 1083,0 +shape (Circle +uid 1084,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "31000,78000,47000,94000" +radius 8000 +) +name (Text +uid 1085,0 +va (VaSet +font "Verdana,12,1" +) +xt "35350,85350,42650,86750" +st "popChar1" +ju 0 +blo "39000,86550" +tm "ONodeName" +) +wait (TextAssociate +uid 1086,0 +ps "CenterOffsetStrategy" +text (Text +uid 1087,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,10,1" +) +xt "39100,86250,43200,87450" +st "wait 2" +blo "39100,87250" +tm "SmWaitText" +) +) +encoding (Text +uid 1088,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "39000,87050,39000,87050" +blo "39000,87050" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1091,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1092,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "32600,87900,45400,90100" +) +autoResize 1 +tline (Line +uid 1093,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "32700,87800,45300,87800" +pts [ +"32700,87800" +"45300,87800" +] +) +bline (Line +uid 1094,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "32700,87900,45300,87900" +pts [ +"32700,87900" +"45300,87900" +] +) +ttri (Triangle +uid 1095,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "32250,87425,32600,87775" +) +btri (Triangle +uid 1096,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "32250,85625,32600,85975" +) +entryActions (MLText +uid 1097,0 +va (VaSet +) +xt "32700,87600,32700,87600" +tm "Actions" +) +inActions (MLText +uid 1098,0 +va (VaSet +) +xt "32700,88000,44900,90400" +st "readChar <= '1'; +startCounter <= '1';" +tm "Actions" +) +exitActions (MLText +uid 1099,0 +va (VaSet +) +xt "35000,85800,35000,85800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1089,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1090,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "37400,87000,43500,88000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*38 (Transition +uid 100,0 +shape (Spline +uid 101,0 +va (VaSet +vasetType 3 +) +xt "5500,20000,16500,20000" +pts [ +"5500,20000" +"16500,20000" +] +) +start &4 +end &5 +ss 0 +es 0 +cond "reset = '1'" +tb (TransitionBlock +uid 102,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 103,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "9000,19000,17200,21000" +) +autoResize 1 +lineShape (Line +uid 104,0 +va (VaSet +vasetType 3 +) +xt "9500,20400,16700,20400" +pts [ +"9500,20400" +"16700,20400" +] +) +condition (MLText +uid 105,0 +va (VaSet +) +xt "9500,19000,16100,20200" +st "reset = '1'" +tm "Condition" +) +actions (MLText +uid 106,0 +va (VaSet +isHidden 1 +) +xt "8900,20800,17500,22000" +st "< Automatic >" +tm "Actions" +) +) +tp (TransitionPriority +uid 107,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 108,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "5819,19219,7381,20781" +radius 781 +) +pr (Text +uid 109,0 +va (VaSet +isHidden 1 +) +xt "5900,19500,7300,20700" +st "1" +ju 0 +blo "6600,20500" +tm "TransitionPriority" +) +padding "100,100" +) +) +*39 (Transition +uid 110,0 +shape (Spline +uid 111,0 +va (VaSet +vasetType 3 +) +xt "5050,15000,16500,15000" +pts [ +"5050,15000" +"16500,15000" +] +) +start &6 +end &7 +ss 0 +es 0 +tb (TransitionBlock +uid 112,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 113,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "8575,14495,12975,15505" +) +autoResize 1 +lineShape (Line +uid 114,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "10775,15900,10775,15900" +pts [ +"10775,15900" +"10775,15900" +] +) +condition (MLText +uid 115,0 +va (VaSet +) +xt "9075,14500,12475,15500" +tm "Condition" +) +actions (MLText +uid 116,0 +va (VaSet +) +xt "10775,15900,10775,15900" +tm "Actions" +) +) +tp (TransitionPriority +uid 117,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 118,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "5414,14219,6976,15781" +radius 781 +) +pr (Text +uid 119,0 +va (VaSet +isHidden 1 +) +xt "5495,14500,6895,15700" +st "1" +ju 0 +blo "6195,15500" +tm "TransitionPriority" +) +padding "100,100" +) +) +*40 (Transition +uid 181,0 +shape (Spline +uid 182,0 +va (VaSet +vasetType 3 +) +xt "47000,22046,61000,22047" +pts [ +"47000,22046" +"61000,22047" +] +arrow 1 +) +start &2 +end &19 +cond "charNotReady = '0'" +tb (TransitionBlock +uid 183,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 184,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "47550,20000,61850,22300" +) +autoResize 1 +lineShape (Line +uid 185,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "51850,21900,51850,21900" +pts [ +"51850,21900" +"51850,21900" +] +) +condition (MLText +uid 186,0 +va (VaSet +font "Verdana,12,0" +) +xt "48050,20500,61550,21900" +st "charNotReady = '0'" +tm "Condition" +) +actions (MLText +uid 187,0 +va (VaSet +) +xt "54700,22200,54700,22200" +tm "Actions" +) +) +tp (TransitionPriority +uid 188,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 189,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "47619,21265,49181,22827" +radius 781 +) +pr (Text +uid 190,0 +va (VaSet +isHidden 1 +) +xt "47700,21546,49100,22746" +st "1" +ju 0 +blo "48400,22546" +tm "TransitionPriority" +) +padding "100,100" +) +) +*41 (Transition +uid 208,0 +shape (Spline +uid 209,0 +va (VaSet +vasetType 3 +) +xt "77000,22007,99000,22076" +pts [ +"77000,22007" +"99000,22076" +] +arrow 1 +) +start &19 +end &20 +cond "character'val(to_integer(unsigned(char))) = 'e' or +character'val(to_integer(unsigned(char))) = 'i' or +character'val(to_integer(unsigned(char))) = 'a'" +tb (TransitionBlock +uid 210,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 211,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "78350,17000,97650,21000" +) +autoResize 1 +lineShape (Line +uid 212,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "80550,18900,80550,18900" +pts [ +"80550,18900" +"80550,18900" +] +) +condition (MLText +uid 213,0 +va (VaSet +) +xt "78850,17500,106250,21100" +st "character'val(to_integer(unsigned(char))) = 'e' or +character'val(to_integer(unsigned(char))) = 'i' or +character'val(to_integer(unsigned(char))) = 'a'" +tm "Condition" +) +actions (MLText +uid 214,0 +va (VaSet +) +xt "88000,20900,88000,20900" +tm "Actions" +) +) +tp (TransitionPriority +uid 215,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 216,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "78419,21232,79981,22794" +radius 781 +) +pr (Text +uid 217,0 +va (VaSet +) +xt "78500,21513,79900,22713" +st "1" +ju 0 +blo "79200,22513" +tm "TransitionPriority" +) +padding "100,100" +) +) +*42 (Transition +uid 218,0 +shape (Spline +uid 219,0 +va (VaSet +vasetType 3 +) +xt "44325,30000,68900,80030" +pts [ +"68900,30000" +"64000,49000" +"44325,80030" +] +arrow 1 +) +start &19 +end &37 +tb (TransitionBlock +uid 220,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 221,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "63500,48995,67900,50005" +) +autoResize 1 +lineShape (Line +uid 222,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "65700,50400,65700,50400" +pts [ +"65700,50400" +"65700,50400" +] +) +condition (MLText +uid 223,0 +va (VaSet +) +xt "64000,49000,67400,50000" +tm "Condition" +) +actions (MLText +uid 224,0 +va (VaSet +) +xt "65700,50400,65700,50400" +tm "Actions" +) +) +tp (TransitionPriority +uid 225,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 226,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "67231,34796,68793,36358" +radius 781 +) +pr (Text +uid 227,0 +va (VaSet +) +xt "67312,35077,68712,36277" +st "3" +ju 0 +blo "68012,36077" +tm "TransitionPriority" +) +padding "100,100" +) +) +*43 (Transition +uid 342,0 +shape (Spline +uid 343,0 +va (VaSet +vasetType 3 +) +xt "115000,22007,121000,22073" +pts [ +"115000,22073" +"121000,22007" +] +arrow 1 +) +start &20 +end &21 +tb (TransitionBlock +uid 344,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 345,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "117500,22035,121900,23045" +) +autoResize 1 +lineShape (Line +uid 346,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "119700,23440,119700,23440" +pts [ +"119700,23440" +"119700,23440" +] +) +condition (MLText +uid 347,0 +va (VaSet +) +xt "118000,22040,121400,23040" +tm "Condition" +) +actions (MLText +uid 348,0 +va (VaSet +) +xt "119700,23440,119700,23440" +tm "Actions" +) +) +tp (TransitionPriority +uid 349,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 350,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "114819,21285,116381,22847" +radius 781 +) +pr (Text +uid 351,0 +va (VaSet +isHidden 1 +) +xt "114900,21566,116300,22766" +st "1" +ju 0 +blo "115600,22566" +tm "TransitionPriority" +) +padding "100,100" +) +) +*44 (Transition +uid 352,0 +shape (Spline +uid 353,0 +va (VaSet +vasetType 3 +) +xt "46056,27569,123257,82230" +pts [ +"123257,27569" +"104000,59000" +"46056,82230" +] +arrow 1 +) +start &21 +end &37 +cond "character'val(to_integer(unsigned(char))) = 'e'" +tb (TransitionBlock +uid 354,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 355,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "111766,58000,130166,60000" +) +autoResize 1 +lineShape (Line +uid 356,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "113966,59900,113966,59900" +pts [ +"113966,59900" +"113966,59900" +] +) +condition (MLText +uid 357,0 +va (VaSet +) +xt "112266,58500,138366,59700" +st "character'val(to_integer(unsigned(char))) = 'e'" +tm "Condition" +) +actions (MLText +uid 358,0 +va (VaSet +) +xt "120966,59900,120966,59900" +tm "Actions" +) +) +tp (TransitionPriority +uid 359,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 360,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "118614,36002,120176,37564" +radius 781 +) +pr (Text +uid 361,0 +va (VaSet +) +xt "118695,36283,120095,37483" +st "2" +ju 0 +blo "119395,37283" +tm "TransitionPriority" +) +padding "100,100" +) +) +*45 (Transition +uid 398,0 +shape (Spline +uid 399,0 +va (VaSet +vasetType 3 +) +xt "160584,22007,165515,22078" +pts [ +"160584,22078" +"165515,22007" +] +arrow 1 +) +start &22 +end &23 +tb (TransitionBlock +uid 400,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 401,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "162550,22037,166950,23047" +) +autoResize 1 +lineShape (Line +uid 402,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "164750,23442,164750,23442" +pts [ +"164750,23442" +"164750,23442" +] +) +condition (MLText +uid 403,0 +va (VaSet +) +xt "163050,22042,166450,23042" +tm "Condition" +) +actions (MLText +uid 404,0 +va (VaSet +) +xt "164750,23442,164750,23442" +tm "Actions" +) +) +tp (TransitionPriority +uid 405,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 406,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "160296,21289,161858,22851" +radius 781 +) +pr (Text +uid 407,0 +va (VaSet +isHidden 1 +) +xt "160377,21570,161777,22770" +st "1" +ju 0 +blo "161077,22570" +tm "TransitionPriority" +) +padding "100,100" +) +) +*46 (Transition +uid 408,0 +shape (Spline +uid 409,0 +va (VaSet +vasetType 3 +) +xt "137000,22020,143416,22020" +pts [ +"137000,22020" +"143416,22020" +] +arrow 1 +) +start &21 +end &22 +tb (TransitionBlock +uid 410,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 411,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "138100,20495,145900,21505" +) +autoResize 1 +lineShape (Line +uid 412,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "140300,21900,140300,21900" +pts [ +"140300,21900" +"140300,21900" +] +) +condition (MLText +uid 413,0 +va (VaSet +) +xt "138600,20500,145400,21500" +tm "Condition" +) +actions (MLText +uid 414,0 +va (VaSet +) +xt "142000,21900,142000,21900" +tm "Actions" +) +) +tp (TransitionPriority +uid 415,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 416,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "136860,21239,138422,22801" +radius 781 +) +pr (Text +uid 417,0 +va (VaSet +) +xt "136941,21520,138341,22720" +st "3" +ju 0 +blo "137641,22520" +tm "TransitionPriority" +) +padding "100,100" +) +) +*47 (Transition +uid 418,0 +shape (Spline +uid 419,0 +va (VaSet +vasetType 3 +) +xt "122892,6000,134372,15570" +pts [ +"133759,15570" +"134000,10000" +"128000,6000" +"123000,10000" +"124507,15382" +] +arrow 1 +) +start &21 +end &21 +cond "counterDone = '0'" +tb (TransitionBlock +uid 420,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 421,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "127500,5500,135300,7500" +) +autoResize 1 +lineShape (Line +uid 422,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "129700,7400,129700,7400" +pts [ +"129700,7400" +"129700,7400" +] +) +condition (MLText +uid 423,0 +va (VaSet +) +xt "128000,6000,138400,7200" +st "counterDone = '0'" +tm "Condition" +) +actions (MLText +uid 424,0 +va (VaSet +) +xt "131400,7400,131400,7400" +tm "Actions" +) +) +tp (TransitionPriority +uid 425,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 426,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "133466,12291,135028,13853" +radius 781 +) +pr (Text +uid 427,0 +va (VaSet +) +xt "133547,12572,134947,13772" +st "1" +ju 0 +blo "134247,13572" +tm "TransitionPriority" +) +padding "100,100" +) +) +*48 (Transition +uid 462,0 +shape (Spline +uid 463,0 +va (VaSet +vasetType 3 +) +xt "227892,6000,239372,15570" +pts [ +"238759,15570" +"239000,10000" +"233000,6000" +"228000,10000" +"229507,15382" +] +arrow 1 +) +start &25 +end &25 +cond "counterDone = '0'" +tb (TransitionBlock +uid 464,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 465,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "232500,5500,240300,7500" +) +autoResize 1 +lineShape (Line +uid 466,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "234700,7400,234700,7400" +pts [ +"234700,7400" +"234700,7400" +] +) +condition (MLText +uid 467,0 +va (VaSet +) +xt "233000,6000,243400,7200" +st "counterDone = '0'" +tm "Condition" +) +actions (MLText +uid 468,0 +va (VaSet +) +xt "236400,7400,236400,7400" +tm "Actions" +) +) +tp (TransitionPriority +uid 469,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 470,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "238466,12291,240028,13853" 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"135547,107572,136947,108772" +st "1" +ju 0 +blo "136247,108572" +tm "TransitionPriority" +) +padding "100,100" +) +) +*65 (Transition +uid 802,0 +shape (Spline +uid 803,0 +va (VaSet +vasetType 3 +) +xt "184930,117001,205713,117903" +pts [ +"184930,117001" +"205713,117903" +] +arrow 1 +) +start &31 +end &32 +cond "character'val(to_integer(unsigned(char))) = 'i'" +tb (TransitionBlock +uid 804,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 805,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "185956,115018,204156,117018" +) +autoResize 1 +lineShape (Line +uid 806,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "188156,116918,188156,116918" +pts [ +"188156,116918" +"188156,116918" +] +) +condition (MLText +uid 807,0 +va (VaSet +) +xt "186456,115518,212256,116718" +st "character'val(to_integer(unsigned(char))) = 'i'" +tm "Condition" +) +actions (MLText +uid 808,0 +va (VaSet +) +xt "195056,116918,195056,116918" +tm "Actions" +) +) +tp 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"105228,157400,105228,157400" +pts [ +"105228,157400" +"105228,157400" +] +) +condition (MLText +uid 867,0 +va (VaSet +) +xt "103528,156000,106928,157000" +tm "Condition" +) +actions (MLText +uid 868,0 +va (VaSet +) +xt "105228,157400,105228,157400" +tm "Actions" +) +) +tp (TransitionPriority +uid 869,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 870,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "209558,159715,211120,161277" +radius 781 +) +pr (Text +uid 871,0 +va (VaSet +) +xt "209639,159996,211039,161196" +st "2" +ju 0 +blo "210339,160996" +tm "TransitionPriority" +) +padding "100,100" +) +) +*72 (Transition +uid 1044,0 +shape (Spline +uid 1045,0 +va (VaSet +vasetType 3 +) +xt "39030,30000,39102,46000" +pts [ +"39102,46000" +"39030,30000" +] +arrow 1 +) +start &36 +end &2 +cond "counterDone = '1'" +tb (TransitionBlock +uid 1046,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1047,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" 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(TransitionBlock +uid 1102,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1103,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "38600,69995,45000,71005" +) +autoResize 1 +lineShape (Line +uid 1104,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "40800,71400,40800,71400" +pts [ +"40800,71400" +"40800,71400" +] +) +condition (MLText +uid 1105,0 +va (VaSet +) +xt "39100,70000,44500,71000" +tm "Condition" +) +actions (MLText +uid 1106,0 +va (VaSet +) +xt "41800,71400,41800,71400" +tm "Actions" +) +) +tp (TransitionPriority +uid 1107,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 1108,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "38318,75618,39880,77180" +radius 781 +) +pr (Text +uid 1109,0 +va (VaSet +isHidden 1 +) +xt "38399,75899,39799,77099" +st "1" +ju 0 +blo "39099,76899" +tm "TransitionPriority" +) +padding "100,100" +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 0 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *74 (PackageList +uid 27,0 +stg "VerticalLayoutStrategy" +textVec [ +*75 (Text +uid 28,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,3000,6900,4000" +st "Package List" +blo "0,3800" +) +*76 (MLText +uid 29,0 +va (VaSet +) +xt "0,4000,17500,7600" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "SmPackageListTextMgr" +) +] +) +compDirBlock (MlTextGroup +uid 30,0 +stg "VerticalLayoutStrategy" +textVec [ +*77 (Text +uid 31,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "20000,0,30200,1000" +st "Compiler Directives" +blo "20000,800" +) +*78 (Text +uid 32,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "20000,1000,32200,2000" +st "Pre-module directives:" +blo "20000,1800" +) +*79 (MLText +uid 33,0 +va (VaSet +isHidden 1 +) +xt "20000,2000,32100,4400" +st "`resetall +`timescale 1ns/10ps" +tm "SmCompilerDirectivesTextMgr" +) +*80 (Text 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(PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *99 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,6000,5400,7000" +st "Declarations" +blo "0,6800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,7000,2700,8000" +st "Ports:" +blo "0,7800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,16100,2500,17000" +st "User:" +blo "0,16800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,6000,5800,7000" +st "Internal User:" +blo "0,6800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,17000,2000,17000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,6000,0,6000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 863,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/05-Morse/Morse/hds/character@register/symbol.sb b/05-Morse/Morse/hds/character@register/symbol.sb new file mode 100644 index 0000000..4ee3046 --- /dev/null +++ b/05-Morse/Morse/hds/character@register/symbol.sb @@ -0,0 +1,1654 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2015.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2011,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 158,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm 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"WireNameMgr" +) +) +) +*2 (Net +uid 21,0 +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +declText (MLText +uid 22,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,57000,7200,58000" +st "clock : std_ulogic" +) +) +*3 (Net +uid 35,0 +decl (Decl +n "morseCode" +t "std_ulogic" +o 1 +suid 2,0 +) +declText (MLText +uid 36,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,56000,8600,57000" +st "morseCode : std_ulogic" +) +) +*4 (PortIoIn +uid 37,0 +shape (CompositeShape +uid 38,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 39,0 +sl 0 +ro 270 +xt "10000,17625,11500,18375" +) +(Line +uid 40,0 +sl 0 +ro 270 +xt "11500,18000,12000,18000" +pts [ +"11500,18000" +"12000,18000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 41,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 42,0 +va (VaSet +isHidden 1 +) +xt "5700,17500,9000,18700" +st "reset" +ju 2 +blo "9000,18500" +tm "WireNameMgr" +) +) +) +*5 (Net +uid 49,0 +decl (Decl +n "reset" +t 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+position 1 +ignorePrefs 1 +titleBlock 1 +) +*9 (CommentText +uid 81,0 +shape (Rectangle +uid 82,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "66000,71000,83000,72000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 83,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "66200,71500,66200,71500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*10 (CommentText +uid 84,0 +shape (Rectangle +uid 85,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,71000,66000,72000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 86,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,71500,62200,71500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*11 (CommentText +uid 87,0 +shape (Rectangle +uid 88,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "83000,70000,103000,74000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 89,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "83200,70200,97300,71400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*12 (CommentText +uid 90,0 +shape (Rectangle +uid 91,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "87000,69000,103000,70000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 92,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "87200,69500,87200,69500" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*13 (CommentText +uid 93,0 +shape (Rectangle +uid 94,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,69000,83000,71000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 95,0 +va (VaSet +fg "32768,0,0" +) +xt "67350,69400,77650,70600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*14 (CommentText +uid 96,0 +shape (Rectangle +uid 97,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,72000,66000,73000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 98,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,72500,62200,72500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*15 (CommentText +uid 99,0 +shape (Rectangle +uid 100,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "62000,73000,66000,74000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 101,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "62200,73500,62200,73500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*16 (CommentText +uid 102,0 +shape (Rectangle +uid 103,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "66000,72000,83000,73000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 104,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "66200,72500,66200,72500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 74,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "62000,69000,103000,74000" +) +oxt "14000,66000,55000,71000" +) +*17 (PortIoIn +uid 1148,0 +shape (CompositeShape +uid 1149,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1150,0 +sl 0 +ro 270 +xt "10000,11625,11500,12375" +) +(Line +uid 1151,0 +sl 0 +ro 270 +xt "11500,12000,12000,12000" +pts [ +"11500,12000" +"12000,12000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1152,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1153,0 +va (VaSet +isHidden 1 +) +xt "2600,11500,9000,12700" +st "morseCode" +ju 2 +blo "9000,12500" +tm "WireNameMgr" +) +) +) +*18 (PortIoOut +uid 1154,0 +shape (CompositeShape +uid 1155,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1156,0 +sl 0 +ro 270 +xt "92500,39625,94000,40375" +) +(Line +uid 1157,0 +sl 0 +ro 270 +xt "92000,40000,92500,40000" +pts [ +"92000,40000" +"92500,40000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1158,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1159,0 +va (VaSet +isHidden 1 +) +xt "95000,39500,97800,40700" +st "TxD" +blo "95000,40500" +tm "WireNameMgr" +) +) +) +*19 (Net +uid 1166,0 +decl (Decl +n "TxD" +t "std_ulogic" +o 4 +suid 17,0 +) +declText (MLText +uid 1167,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,59000,7400,60000" +st "TxD : std_ulogic" +) +) +*20 (SaComponent +uid 1565,0 +optionalChildren [ +*21 (CptPort +uid 1541,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1542,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43250,15625,44000,16375" +) +tg (CPTG +uid 1543,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1544,0 +va (VaSet +) +xt "45000,15400,48400,16600" +st "clock" +blo "45000,16400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 2008,0 +) +) +) +*22 (CptPort +uid 1545,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1546,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43250,17625,44000,18375" +) +tg (CPTG +uid 1547,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1548,0 +va (VaSet +) +xt "45000,17400,48300,18600" +st "reset" +blo "45000,18400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 2009,0 +) +) +) +*23 (CptPort +uid 1549,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1550,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43250,11625,44000,12375" +) +tg (CPTG +uid 1551,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1552,0 +va (VaSet +) +xt "45000,11550,51400,12750" +st "morseCode" +blo "45000,12550" +) +) +thePort (LogicalPort +decl (Decl +n "morseCode" +t "std_ulogic" +o 3 +suid 2012,0 +) +) +) +*24 (CptPort +uid 1553,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1554,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60000,13625,60750,14375" +) +tg (CPTG +uid 1555,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1556,0 +va (VaSet +) +xt "49700,13550,59000,14750" +st "symbolDuration" +ju 2 +blo "59000,14550" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "symbolDuration" +t "unsigned" +b "(unitCountBitNb-1 DOWNTO 0)" +o 4 +suid 2014,0 +) +) +) +*25 (CptPort +uid 1557,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1558,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60000,15625,60750,16375" +) +tg (CPTG +uid 1559,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1560,0 +va (VaSet +) +xt "51400,15550,59000,16750" +st "symbolValid" +ju 2 +blo "59000,16550" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "symbolValid" +t "std_ulogic" +o 5 +suid 2015,0 +) +) +) +*26 (CptPort +uid 1561,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1562,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60000,11625,60750,12375" +) +tg (CPTG +uid 1563,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1564,0 +va (VaSet +) +xt "51100,11550,59000,12750" +st "symbolValue" +ju 2 +blo "59000,12550" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "symbolValue" +t "std_ulogic" +o 6 +suid 2016,0 +) +) +) +] +shape (Rectangle +uid 1566,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "44000,8000,60000,20000" +) +oxt "40000,10000,56000,22000" +ttg (MlTextGroup +uid 1567,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*27 (Text +uid 1568,0 +va (VaSet +font "Verdana,9,1" +) +xt "44600,19800,48100,21000" +st "Morse" +blo "44600,20800" +tm "BdLibraryNameMgr" +) +*28 (Text +uid 1569,0 +va (VaSet +font "Verdana,9,1" +) +xt "44600,20700,56700,21900" +st "symbolLengthCounter" +blo "44600,21700" +tm "CptNameMgr" +) +*29 (Text +uid 1570,0 +va (VaSet +font "Verdana,9,1" +) +xt "44600,21600,47800,22800" +st "I_len" +blo "44600,22600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1571,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1572,0 +text (MLText +uid 1573,0 +va (VaSet +font "Verdana,8,0" +) +xt "44000,23600,77800,25600" +st "unitCountDivide = integer(clockFrequency*unitDuration + 0.5) ( positive ) +unitCountBitNb = unitCountBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "unitCountDivide" +type "positive" +value "integer(clockFrequency*unitDuration + 0.5)" +) +(GiElement +name "unitCountBitNb" +type "positive" +value "unitCountBitNb" +) +] +) +viewicon (ZoomableIcon +uid 1574,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "44250,18250,45750,19750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +connectByName 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*30 (Net +uid 1575,0 +decl (Decl +n "symbolValue" +t "std_ulogic" +o 6 +suid 20,0 +) +declText (MLText +uid 1576,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,65000,11700,66000" +st "SIGNAL symbolValue : std_ulogic" +) +) +*31 (Net +uid 1583,0 +decl (Decl +n "symbolValid" +t "std_ulogic" +o 7 +suid 21,0 +) +declText (MLText +uid 1584,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,66000,11400,67000" +st "SIGNAL symbolValid : std_ulogic" +) +) +*32 (Net +uid 1591,0 +decl (Decl +n "symbolDuration" +t "unsigned" +b "(unitCountBitNb-1 DOWNTO 0)" +o 8 +suid 22,0 +) +declText (MLText +uid 1592,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,67000,24600,68000" +st "SIGNAL symbolDuration : unsigned(unitCountBitNb-1 DOWNTO 0)" +) +) +*33 (Net +uid 1727,0 +decl (Decl +n "charValid" +t "std_ulogic" +o 9 +suid 23,0 +) +declText (MLText +uid 1728,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,68000,10800,69000" +st "SIGNAL charValid : std_ulogic" +) +) +*34 (Net +uid 1735,0 +decl (Decl +n "charOut" +t "std_ulogic_vector" +b "(uartDataBitNb-1 DOWNTO 0)" +o 10 +suid 24,0 +) +declText (MLText +uid 1736,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,69000,26500,70000" +st "SIGNAL charOut : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0)" +) +) +*35 (HdlText +uid 1854,0 +optionalChildren [ +*36 (EmbeddedText +uid 1859,0 +commentText (CommentText +uid 1860,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1861,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "44000,47000,60000,61000" +) +oxt "0,0,18000,5000" +text (MLText +uid 1862,0 +va (VaSet +) +xt "44200,47200,59500,60400" +st " +process(reset, clock) + begin + if reset = '1' then + txSend <= '0'; + elsif rising_edge(clock) then + if ( (txFifoEmpty = '0') and (txBusy = '0') ) then + txSend <= '1'; + else + txSend <= '0'; + end if; + end if; + end process; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 14000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 1855,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "44000,46000,60000,62000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1856,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*37 (Text +uid 1857,0 +va (VaSet +) +xt "44400,62000,47000,63200" +st "eb2" +blo "44400,63000" +tm "HdlTextNameMgr" +) +*38 (Text +uid 1858,0 +va (VaSet +) +xt "44400,63000,45800,64200" +st "2" +blo "44400,64000" +tm "HdlTextNumberMgr" +) +] +) +) +*39 (Net +uid 1901,0 +decl (Decl +n "txWord" +t "std_ulogic_vector" +b "(uartDataBitNb-1 DOWNTO 0)" +o 11 +suid 25,0 +) +declText (MLText +uid 1902,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,70000,26600,71000" +st "SIGNAL txWord : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0)" +) +) +*40 (Net +uid 1903,0 +decl (Decl +n "txBusy" +t "std_ulogic" +o 12 +suid 26,0 +) +declText (MLText +uid 1904,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,71000,10800,72000" +st "SIGNAL txBusy : std_ulogic" +) +) +*41 (Net +uid 1905,0 +decl (Decl +n "txSend" +t "std_ulogic" +o 13 +suid 27,0 +) +declText (MLText +uid 1906,0 +va (VaSet +font "Verdana,8,0" +) +xt "-4000,72000,10900,73000" +st "SIGNAL txSend : std_ulogic" +) +) +*42 (SaComponent +uid 1973,0 +optionalChildren [ +*43 (CptPort +uid 1949,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1950,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "84000,39625,84750,40375" +) +tg (CPTG +uid 1951,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1952,0 +va (VaSet +) +xt "80200,39400,83000,40600" +st "TxD" +ju 2 +blo "83000,40400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "TxD" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*44 (CptPort +uid 1953,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1954,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67250,47625,68000,48375" +) +tg (CPTG +uid 1955,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1956,0 +va (VaSet +) +xt "69000,47400,72400,48600" +st "clock" +blo "69000,48400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 2,0 +) +) +) +*45 (CptPort +uid 1957,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1958,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67250,49625,68000,50375" +) +tg (CPTG +uid 1959,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1960,0 +va (VaSet +) +xt "69000,49400,72300,50600" +st "reset" +blo "69000,50400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 3,0 +) +) +) +*46 (CptPort +uid 1961,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1962,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67250,39625,68000,40375" +) +tg (CPTG +uid 1963,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1964,0 +va (VaSet +) +xt "68999,39400,72999,40600" +st "dataIn" +blo "68999,40400" +) +) +thePort (LogicalPort +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 4,0 +) +) +) +*47 (CptPort +uid 1965,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1966,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67250,41625,68000,42375" +) +tg (CPTG +uid 1967,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1968,0 +va (VaSet +) +xt "69000,41400,72100,42600" +st "send" +blo "69000,42400" +) +) +thePort (LogicalPort +decl (Decl +n "send" +t "std_ulogic" +o 5 +suid 5,0 +) +) +) +*48 (CptPort +uid 1969,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1970,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "67250,43625,68000,44375" +) +tg (CPTG +uid 1971,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1972,0 +va (VaSet +) +xt "69000,43400,72100,44600" +st "busy" +blo "69000,44400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "busy" +t "std_ulogic" +o 6 +suid 6,0 +) +) +) +] +shape (Rectangle +uid 1974,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "68000,36000,84000,52000" +) +oxt "34000,12000,50000,28000" +ttg (MlTextGroup +uid 1975,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*49 (Text +uid 1976,0 +va (VaSet +font "Verdana,9,1" +) +xt "68600,51800,72300,53000" +st "RS232" +blo "68600,52800" +tm "BdLibraryNameMgr" +) +*50 (Text +uid 1977,0 +va (VaSet +font "Verdana,9,1" +) +xt "68600,52700,81200,53900" +st "serialPortTransmitter" +blo "68600,53700" +tm "CptNameMgr" +) +*51 (Text +uid 1978,0 +va (VaSet +font "Verdana,9,1" +) +xt "68600,53600,71400,54800" +st "I_tx" +blo "68600,54600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1979,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1980,0 +text (MLText +uid 1981,0 +va (VaSet +font "Verdana,8,0" +) +xt "68000,54800,102300,56800" +st "dataBitNb = uartDataBitNb ( positive ) +baudRateDivide = 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"VerticalLayoutStrategy" +textVec [ +*23 (Text +uid 196,0 +va (VaSet +font "Verdana,9,1" +) +xt "7600,37800,11300,39000" +st "RS232" +blo "7600,38800" +tm "BdLibraryNameMgr" +) +*24 (Text +uid 197,0 +va (VaSet +font "Verdana,9,1" +) +xt "7600,39000,18000,40200" +st "serialPortReceiver" +blo "7600,40000" +tm "CptNameMgr" +) +*25 (Text +uid 198,0 +va (VaSet +font "Verdana,9,1" +) +xt "7600,40200,12100,41400" +st "I_UART" +blo "7600,41200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 199,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 200,0 +text (MLText +uid 201,0 +va (VaSet +) +xt "7000,41400,48600,43800" +st "dataBitNb = uartDataBitNb ( positive ) +baudRateDivide = integer(clockFrequency/uartBaudRate + 0.5) ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "uartDataBitNb" +) +(GiElement +name "baudRateDivide" +type "positive" +value "integer(clockFrequency/uartBaudRate + 0.5)" +) +] +) +viewicon (ZoomableIcon +uid 202,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "7250,36250,8750,37750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*26 (Net +uid 351,0 +decl (Decl +n "characterIn" +t "std_ulogic_vector" +b "(uartDataBitNb-1 DOWNTO 0)" +o 6 +suid 9,0 +) +declText (MLText +uid 352,0 +va (VaSet +) +xt "-4000,17000,35600,18200" +st "SIGNAL characterIn : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0)" +) +) +*27 (Net +uid 353,0 +decl (Decl +n "characterValid" +t "std_ulogic" +o 7 +suid 10,0 +) +declText (MLText +uid 354,0 +va (VaSet +) +xt "-4000,18200,16200,19400" +st "SIGNAL characterValid : std_ulogic" +) +) +*28 (Net +uid 435,0 +decl (Decl +n "characterReg" +t "std_ulogic_vector" +b "(uartDataBitNb-1 DOWNTO 0)" +o 5 +suid 11,0 +) +declText (MLText +uid 436,0 +va (VaSet +) +xt "-4000,15800,36100,17000" +st "SIGNAL characterReg : std_ulogic_vector(uartDataBitNb-1 DOWNTO 0)" +) +) +*29 (HdlText +uid 714,0 +optionalChildren [ +*30 (EmbeddedText +uid 728,0 +commentText (CommentText +uid 729,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 730,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "79000,27000,87000,33000" +) +oxt "0,0,18000,5000" +text (MLText +uid 731,0 +va (VaSet +) +xt "79200,27200,86600,32000" +st " +morseCode <= morseOut and tone; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 8000 +) +) +) +] +shape (Rectangle +uid 715,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "79000,26000,87000,34000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 716,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*31 (Text +uid 717,0 +va (VaSet +font "Verdana,8,1" +) +xt "79150,34000,81450,35000" +st "eb1" +blo "79150,34800" +tm "HdlTextNameMgr" +) +*32 (Text +uid 718,0 +va (VaSet +font "Verdana,8,1" +) +xt "79150,35000,80350,36000" +st "1" +blo "79150,35800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 719,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "79250,32250,80750,33750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*33 (Net +uid 720,0 +decl (Decl +n "morseOut" +t "std_ulogic" +o 8 +suid 12,0 +) +declText (MLText +uid 721,0 +va (VaSet +) +xt "-4000,19400,15600,20600" +st "SIGNAL morseOut : std_ulogic" +) +) +*34 (Net +uid 732,0 +decl (Decl +n "tone" +t "std_ulogic" +o 9 +suid 13,0 +) +declText (MLText +uid 733,0 +va (VaSet +) +xt "-4000,20600,14000,21800" +st "SIGNAL tone : std_ulogic" +) +) +*35 (SaComponent +uid 756,0 +optionalChildren [ +*36 (CptPort +uid 744,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 745,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71000,53625,71750,54375" +) +tg (CPTG +uid 746,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 747,0 +va (VaSet +) +xt "67100,53400,70000,54600" +st "tone" +ju 2 +blo "70000,54400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "tone" +t "std_ulogic" +o 1 +suid 2007,0 +) +) +) +*37 (CptPort +uid 748,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 749,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54250,53625,55000,54375" +) +tg (CPTG +uid 750,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 751,0 +va (VaSet +) +xt "56000,53400,59400,54600" +st "clock" +blo "56000,54400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 2008,0 +) +) +) +*38 (CptPort +uid 752,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 753,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54250,55625,55000,56375" +) +tg (CPTG +uid 754,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 755,0 +va (VaSet +) +xt "56000,55400,59300,56600" +st "reset" +blo "56000,56400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 2009,0 +) +) +) +] +shape (Rectangle +uid 757,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "55000,50000,71000,58000" +) +oxt "42000,20000,58000,28000" +ttg (MlTextGroup +uid 758,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*39 (Text +uid 759,0 +va (VaSet +font "Verdana,9,1" +) +xt "55600,57800,59100,59000" +st "Morse" +blo "55600,58800" +tm "BdLibraryNameMgr" +) +*40 (Text +uid 760,0 +va (VaSet +font "Verdana,9,1" +) +xt "55600,59000,64100,60200" +st "toneGenerator" +blo "55600,60000" +tm "CptNameMgr" +) +*41 (Text +uid 761,0 +va (VaSet +font "Verdana,9,1" +) +xt "55600,60200,59600,61400" +st "I_tone" +blo "55600,61200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 762,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 763,0 +text (MLText +uid 764,0 +va (VaSet +) +xt "55000,61600,94700,62800" +st "toneDivide = integer(clockFrequency/toneFrequency + 0.5) ( positive ) " +) +header "" +) +elements [ +(GiElement +name "toneDivide" +type "positive" +value "integer(clockFrequency/toneFrequency + 0.5)" +) +] +) +viewicon (ZoomableIcon +uid 765,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "55250,56250,56750,57750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*42 (SaComponent +uid 1073,0 +optionalChildren [ +*43 (CptPort +uid 1049,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1050,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "71000,29625,71750,30375" +) +tg (CPTG +uid 1051,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1052,0 +va (VaSet +) +xt "64300,29400,70000,30600" +st "morseOut" +ju 2 +blo "70000,30400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "morseOut" +t "std_ulogic" +o 1 +suid 2007,0 +) +) +) +*44 (CptPort +uid 1053,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1054,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54250,37625,55000,38375" +) +tg (CPTG +uid 1055,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1056,0 +va (VaSet +) +xt "56000,37400,59400,38600" +st "clock" +blo "56000,38400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 2008,0 +) +) +) +*45 (CptPort +uid 1057,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1058,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54250,39625,55000,40375" +) +tg (CPTG +uid 1059,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1060,0 +va (VaSet +) +xt "56000,39400,59300,40600" +st "reset" +blo "56000,40400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 2009,0 +) +) +) +*46 (CptPort +uid 1061,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1062,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54250,31625,55000,32375" +) +tg (CPTG +uid 1063,0 +ps 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+shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *87 (SymDeclBlock +uid 1,0 +stg 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mode 100644 index 0000000..3eca717 --- /dev/null +++ b/05-Morse/Morse_test/hdl/charToMorseController_tester_test.vhd @@ -0,0 +1,70 @@ +LIBRARY std; + USE std.textio.all; +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF charToMorseController_tester IS + -- clock and reset + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + signal sReset: std_uLogic := '1'; + -- character input + constant textToSend : string := "tea time"; + constant charInputDelay : time := 200 us; + signal writePointer, readPointer : integer := 0; + signal fifoDataAvailable: std_uLogic := '0'; + +BEGIN + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + sReset <= '1', '0' after 2*clockPeriod; + reset <= sReset; + + ------------------------------------------------------------------------------ + -- test sequence + testSequence: process + begin + -- send characters + for index in 1 to textToSend'length loop + wait for charInputDelay; + writePointer <= writePointer + 1; + end loop; + -- end of fifo input + print(cr & cr); + assert false + report "End of text" + severity note; + wait; + end process testSequence; + + ------------------------------------------------------------------------------ + -- fifo simulation + fifo: process + begin + -- wait for action + wait until rising_edge(sClock); + -- add char in fifo + if readChar = '1' then + readPointer <= readPointer + 1; + end if; + -- end of simulation + if readPointer = textToSend'length then + wait for charInputDelay; + print(cr & cr); + assert false + report "End of simulation" + severity failure; + end if; + end process fifo; + + char <= std_ulogic_vector(to_unsigned( + character'pos(textToSend(readPointer+1)), char'length + )) when (readPointer < textToSend'length) and (fifoDataAvailable = '1') + else (others => '-'); + + fifoDataAvailable <= '1' when readPointer < writePointer + else '0'; + charNotReady <= not fifoDataAvailable; + +END ARCHITECTURE test; diff --git a/05-Morse/Morse_test/hdl/morseDecoder_tester_test.vhd b/05-Morse/Morse_test/hdl/morseDecoder_tester_test.vhd new file mode 100644 index 0000000..42ded03 --- /dev/null +++ b/05-Morse/Morse_test/hdl/morseDecoder_tester_test.vhd @@ -0,0 +1,108 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF morseDecoder_tester IS + -- clock and reset + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + signal sReset: std_uLogic := '1'; + -- UART + constant uartPeriod: time := (1.0/uartBaudRate) * 1 sec; + constant uartWriteInterval: time := 2 ms; + signal uartInString : string(1 to 32); + signal uartSendInString: std_uLogic; + signal uartSendInDone: std_uLogic; + signal uartInByte: character; + signal uartSendInByte: std_uLogic; + +BEGIN + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + sReset <= '1', '0' after 2*clockPeriod; + reset <= sReset; + + ------------------------------------------------------------------------------ + -- test sequence + process + begin + uartSendInString <= '0'; + wait for 4*uartPeriod; + -- characters with max. 2 Morse symbols + print("Sending characters with max. 2 symbols"); + uartInString <= pad("tea time", uartInString'length); + uartSendInString <= '1', '0' after 1 ns; + wait until uartSendInDone = '1'; + wait for uartWriteInterval; + -- characters starting with a dot + print("Sending characters starting with a dot"); + uartInString <= pad("eish54v3uf2arlwpj1", uartInString'length); + uartSendInString <= '1', '0' after 1 ns; + wait until uartSendInDone = '1'; + wait for uartWriteInterval; + -- characters starting with a dash + print("Sending characters starting with a dash"); + uartInString <= pad("tndb6xkcymgz7qo890", uartInString'length); + uartSendInString <= '1', '0' after 1 ns; + wait until uartSendInDone = '1'; + wait for uartWriteInterval; + -- end of simulation + print(cr & cr); + assert false + report "End of simulation" + severity failure; + wait; + end process; + + --============================================================================ + -- uart send + rsSendSerialString: process + constant uartBytePeriod : time := 15*uartPeriod; + variable commandRight: natural; + begin + + uartSendInByte <= '0'; + uartSendInDone <= '0'; + + wait until rising_edge(uartSendInString); + + commandRight := uartInString'right; + while uartInString(commandRight) = ' ' loop + commandRight := commandRight-1; + end loop; + + for index in uartInString'left to commandRight loop + uartInByte <= uartInString(index); + uartSendInByte <= '1', '0' after 1 ns; + wait for uartBytePeriod; + end loop; + + uartInByte <= cr; + uartSendInByte <= '1', '0' after 1 ns; + wait for uartBytePeriod; + + uartSendInDone <= '1'; + wait for 1 ns; + + end process rsSendSerialString; + + rsSendSerialByte: process + variable rxData: unsigned(uartDataBitNb-1 downto 0); + begin + RxD <= '1'; + + wait until rising_edge(uartSendInByte); + rxData := to_unsigned(character'pos(uartInByte), rxData'length); + + RxD <= '0'; + wait for uartPeriod; + + for index in rxData'reverse_range loop + RxD <= rxData(index); + wait for uartPeriod; + end loop; + + end process rsSendSerialByte; + +END ARCHITECTURE test; + diff --git a/05-Morse/Morse_test/hdl/morseEncoder_tester_test.vhd b/05-Morse/Morse_test/hdl/morseEncoder_tester_test.vhd new file mode 100644 index 0000000..3bd8ccc --- /dev/null +++ b/05-Morse/Morse_test/hdl/morseEncoder_tester_test.vhd @@ -0,0 +1,106 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF morseEncoder_tester IS + -- clock and reset + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + signal sReset: std_uLogic := '1'; + -- UART + constant uartPeriod: time := (1.0/uartBaudRate) * 1 sec; + constant uartWriteInterval: time := 8 ms; + signal uartInString : string(1 to 32); + signal uartSendInString: std_uLogic; + signal uartSendInDone: std_uLogic; + signal uartInByte: character; + signal uartSendInByte: std_uLogic; + +BEGIN + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + sReset <= '1', '0' after 2*clockPeriod; + reset <= sReset; + ------------------------------------------------------------------------------ + -- test sequence + process + begin + uartSendInString <= '0'; + wait for 4*uartPeriod; + -- characters with max. 2 Morse symbols + print("Sending characters with max. 2 symbols"); + uartInString <= pad("tea time", uartInString'length); + uartSendInString <= '1', '0' after 1 ns; + wait until uartSendInDone = '1'; + wait for uartWriteInterval; + -- characters starting with a dot + print("Sending characters starting with a dot"); + uartInString <= pad("eish54v3uf2arlwpj1", uartInString'length); + uartSendInString <= '1', '0' after 1 ns; + wait until uartSendInDone = '1'; + wait for uartWriteInterval; + -- characters starting with a dash + print("Sending characters starting with a dash"); + uartInString <= pad("tndb6xkcymgz7qo890", uartInString'length); + uartSendInString <= '1', '0' after 1 ns; + wait until uartSendInDone = '1'; + wait for uartWriteInterval; + -- end of simulation + print(cr & cr); + assert false + report "End of simulation" + severity failure; + wait; + end process; + + --============================================================================ + -- uart send + rsSendSerialString: process + constant uartBytePeriod : time := 15*uartPeriod; + variable commandRight: natural; + begin + + uartSendInByte <= '0'; + uartSendInDone <= '0'; + + wait until rising_edge(uartSendInString); + + commandRight := uartInString'right; + while uartInString(commandRight) = ' ' loop + commandRight := commandRight-1; + end loop; + + for index in uartInString'left to commandRight loop + uartInByte <= uartInString(index); + uartSendInByte <= '1', '0' after 1 ns; + wait for uartBytePeriod; + end loop; + + uartInByte <= cr; + uartSendInByte <= '1', '0' after 1 ns; + wait for uartBytePeriod; + + uartSendInDone <= '1'; + wait for 1 ns; + + end process rsSendSerialString; + + rsSendSerialByte: process + variable rxData: unsigned(uartDataBitNb-1 downto 0); + begin + RxD <= '1'; + + wait until rising_edge(uartSendInByte); + rxData := to_unsigned(character'pos(uartInByte), rxData'length); + + RxD <= '0'; + wait for uartPeriod; + + for index in rxData'reverse_range loop + RxD <= rxData(index); + wait for uartPeriod; + end loop; + + end process rsSendSerialByte; + +END ARCHITECTURE test; diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_charToMorseController_tester_test.vhd._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_charToMorseController_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_charToMorseController_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tb_entity.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tb_struct.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tester_entity.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_chartomorsecontroller_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morseDecoder_tester_test.vhd._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morseDecoder_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morseDecoder_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morseEncoder_tester_test.vhd._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morseEncoder_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morseEncoder_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tb_entity.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tb_struct.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tester_entity.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morsedecoder_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tb_entity.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tb_struct.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tester_entity.vhg._fpf b/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/05-Morse/Morse_test/hds/.hdlsidedata/_morseencoder_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/05-Morse/Morse_test/hds/@d@a@c_tester_1/interface b/05-Morse/Morse_test/hds/@d@a@c_tester_1/interface new file mode 100644 index 0000000..b372831 --- /dev/null +++ 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+st "In0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +m 3 +o 0 +r 0 +d 0 +s 0 +sf 1 +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,9,0" +) +xt "0,750,3600,1950" +st "Buffer0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +) +DeclarativeBlock *23 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44300,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,6000,44000,7000" +st "User:" +blo "42000,6800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7000,44000,7000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 201,0 +) diff --git a/05-Morse/Morse_test/hds/_chartomorsecontroller_tb._epf b/05-Morse/Morse_test/hds/_chartomorsecontroller_tb._epf new file mode 100644 index 0000000..c21fe47 --- /dev/null +++ b/05-Morse/Morse_test/hds/_chartomorsecontroller_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom char@to@morse@controller_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/05-Morse/Morse_test/hds/_chartomorsecontroller_tester._epf b/05-Morse/Morse_test/hds/_chartomorsecontroller_tester._epf new file mode 100644 index 0000000..d3446c1 --- /dev/null +++ b/05-Morse/Morse_test/hds/_chartomorsecontroller_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom charToMorseController_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/05-Morse/Morse_test/hds/_morsedecoder_tb._epf b/05-Morse/Morse_test/hds/_morsedecoder_tb._epf new file mode 100644 index 0000000..b8b5678 --- /dev/null +++ b/05-Morse/Morse_test/hds/_morsedecoder_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom morse@decoder_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/05-Morse/Morse_test/hds/_morsedecoder_tester._epf b/05-Morse/Morse_test/hds/_morsedecoder_tester._epf new file mode 100644 index 0000000..571e9fc --- /dev/null +++ b/05-Morse/Morse_test/hds/_morsedecoder_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom morseDecoder_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/05-Morse/Morse_test/hds/_morseencoder_tb._epf b/05-Morse/Morse_test/hds/_morseencoder_tb._epf new file mode 100644 index 0000000..b4154a8 --- /dev/null +++ b/05-Morse/Morse_test/hds/_morseencoder_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom morse@encoder_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/05-Morse/Morse_test/hds/_morseencoder_tester._epf b/05-Morse/Morse_test/hds/_morseencoder_tester._epf new file mode 100644 index 0000000..e0552f9 --- /dev/null +++ b/05-Morse/Morse_test/hds/_morseencoder_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom morseEncoder_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/05-Morse/Morse_test/hds/beamer@periph@blanking_tester/interface b/05-Morse/Morse_test/hds/beamer@periph@blanking_tester/interface new file mode 100644 index 0000000..49eb239 --- /dev/null +++ b/05-Morse/Morse_test/hds/beamer@periph@blanking_tester/interface @@ -0,0 +1,1408 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +packageRefs [ +(PackageRef +library "ieee" +unitName "std_logic_1164" +itemName "all" +) +(PackageRef +library "ieee" +unitName "numeric_std" +itemName "all" +) +] +) +version "15.1" +appVersion "2002.1a (Build 22)" +model (Symbol +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "D:\\Users\\ELN_labs\\VHDL_gen" +) +(vvPair +variable "SideDataDesignDir" +value "U:\\SEm_curves\\Test\\beamer@periph@blanking_tester\\interface.info" +) +(vvPair +variable "SideDataUserDir" +value "U:\\SEm_curves\\Test\\beamer@periph@blanking_tester\\interface.user" +) +(vvPair +variable "SourceDir" +value "U:\\SEm_curves\\Test" +) +(vvPair +variable "appl" +value "HDL Designer - Pro" +) +(vvPair +variable "d" +value "U:\\SEm_curves\\Test\\beamer@periph@blanking_tester" +) +(vvPair +variable "d_logical" +value "U:\\SEm_curves\\Test\\beamerPeriphBlanking_tester" +) +(vvPair +variable "date" +value "04/24/08" +) +(vvPair +variable "day" +value "Thu" +) +(vvPair +variable "day_long" +value "Thursday" +) +(vvPair +variable "dd" +value "24" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value 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+) +lastUid 115,0 +) diff --git a/05-Morse/Morse_test/hds/char@to@morse@controller_tb/struct.bd b/05-Morse/Morse_test/hds/char@to@morse@controller_tb/struct.bd new file mode 100644 index 0000000..b4077e5 --- /dev/null +++ b/05-Morse/Morse_test/hds/char@to@morse@controller_tb/struct.bd @@ -0,0 +1,3588 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_DUT" +duLibraryName "Morse" +duName "charToMorseController" +elements [ +(GiElement +name "characterBitNb" +type "positive" +value "characterBitNb" +) +(GiElement +name "unitCountBitNb" +type "positive" +value "unitCountBitNb" +) +] +mwi 0 +uid 3079,0 +) +(Instance +name "I_cnt" +duLibraryName "Morse" +duName "unitCounter" +elements [ +(GiElement +name "unitCountDivide" +type "positive" +value "integer(clockFrequency*unitDuration + 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"C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse_test\\hds\\char@to@morse@controller_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse_test\\hds\\char@to@morse@controller_tb" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Morse_test\\hds\\charToMorseController_tb" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" 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characterBitNb: positive := 7; +constant unitCountBitNb: positive := 3; +constant unitDuration: real := 50.0E-6; +constant clockFrequency: real := 60.0E6; +--constant clockFrequency: real := 66.0E6;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,14600,9000,15600" +st "Diagram Signals:" +blo "0,15400" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "0,5600,6000,6600" +st "Post User:" +blo "0,6400" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +) +xt "0,5600,0,5600" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 35,0 +usingSuid 1 +emptyRow *89 (LEmptyRow +) +uid 1321,0 +optionalChildren [ +*90 (RefLabelRowHdr +) +*91 (TitleRowHdr +) +*92 (FilterRowHdr +) +*93 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*94 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*95 (GroupColHdr +tm "GroupColHdrMgr" +) +*96 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*97 (ModeColHdr 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+type "real" +value "morseUnitDuration" +) +(GiElement +name "toneFrequency" +type "real" +value "morseToneFrequency" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*29 (Net +uid 3293,0 +decl (Decl +n "morseEnvelope" +t "std_ulogic" +o 6 +suid 31,0 +) +declText (MLText +uid 3294,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,20600,17900,21600" +st "SIGNAL morseEnvelope : std_ulogic +" +) +) +*30 (SaComponent +uid 3389,0 +optionalChildren [ +*31 (CptPort +uid 3369,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3370,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58250,23625,59000,24375" +) +tg (CPTG +uid 3371,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3372,0 +va (VaSet +) +xt "60000,23700,66400,24900" +st "morseCode" +blo "60000,24700" +) +) +thePort (LogicalPort +decl (Decl +n "morseCode" +t "std_ulogic" +o 1 +suid 2007,0 +) +) +) +*32 (CptPort +uid 3373,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3374,0 +ro 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"uartBaudRate" +type "real" +value "uartBaudRate" +) +(GiElement +name "uartDataBitNb" +type "positive" +value "uartDataBitNb" +) +(GiElement +name "unitDuration" +type "real" +value "morseUnitDuration" +) +(GiElement +name "toneFrequency" +type "real" +value "morseToneFrequency" +) +(GiElement +name "deglitchBitNb" +type "natural" +value "deglitchBitNb" +) +] +) +ordering 1 +connectByName 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*39 (Wire +uid 2558,0 +shape (OrthoPolyLine +uid 2559,0 +va (VaSet +vasetType 3 +) +xt "33000,30000,34250,40000" +pts [ +"34250,30000" +"33000,30000" +"33000,40000" +] +) +start &24 +end &12 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2562,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2563,0 +va (VaSet +font "Verdana,12,0" +) +xt "29250,28600,33350,30000" +st "reset" +blo "29250,29800" +tm "WireNameMgr" +) +) +on &16 +) +*40 (Wire +uid 2566,0 +shape (OrthoPolyLine +uid 2567,0 +va (VaSet +vasetType 3 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$SCRATCH_DIR/Memory +Memory_test = $SCRATCH_DIR/Memory_test +Morse = $SCRATCH_DIR/Morse +Morse_test = $SCRATCH_DIR/Morse_test +RS232 = $SCRATCH_DIR/RS232 +RS232_test = $SCRATCH_DIR/RS232_test +UVM = $SCRATCH_DIR/UVM +UVM_test = $SCRATCH_DIR/UVM_test +[hdl] +Board = $HDS_PROJECT_DIR/../Board/hdl +Common = $HDS_PROJECT_DIR/../../Libs/Common/hdl +Common_test = $HDS_PROJECT_DIR/../../Libs/Common_test/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hdl +Memory = $HDS_PROJECT_DIR/../../Libs/Memory/hdl +Memory_test = $HDS_PROJECT_DIR/../../Libs/Memory_test/hdl +Morse = $HDS_PROJECT_DIR/../Morse/hdl +Morse_test = $HDS_PROJECT_DIR/../Morse_test/hdl +RS232 = $HDS_PROJECT_DIR/../../Libs/RS232/hdl +RS232_test = $HDS_PROJECT_DIR/../../Libs/RS232_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +UVM = $HDS_PROJECT_DIR/../../Libs/UVM/hdl +UVM_test = $HDS_PROJECT_DIR/../../Libs/UVM_test/hdl +[hds] +Board = $HDS_PROJECT_DIR/../Board/hds +Common = $HDS_PROJECT_DIR/../../Libs/Common/hds +Common_test = $HDS_PROJECT_DIR/../../Libs/Common_test/hds +ieee = $HDS_HOME/hdl_libs/ieee/hds +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hds +Memory = $HDS_PROJECT_DIR/../../Libs/Memory/hds +Memory_test = $HDS_PROJECT_DIR/../../Libs/Memory_test/hds +Morse = $HDS_PROJECT_DIR/../Morse/hds +Morse_test = $HDS_PROJECT_DIR/../Morse_test/hds +RS232 = $HDS_PROJECT_DIR/../../Libs/RS232/hds +RS232_test = $HDS_PROJECT_DIR/../../Libs/RS232_test/hds +std = $HDS_HOME/hdl_libs/std/hds +UVM = $HDS_PROJECT_DIR/../../Libs/UVM/hds +UVM_test = $HDS_PROJECT_DIR/../../Libs/UVM_test/hds +[hds_settings] +design_root = Board.morse_ebs3(struct)morse_ebs3/struct.bd +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/05-Morse/Prefs/hds_team/shared.hdp b/05-Morse/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/05-Morse/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/05-Morse/Prefs/hds_team/v2018.1/hds_team_prefs b/05-Morse/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/05-Morse/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/05-Morse/Prefs/hds_team/v2018.1/title_block.tmpl b/05-Morse/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/05-Morse/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/05-Morse/Prefs/hds_team/v2019.2/hds_team_prefs b/05-Morse/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/05-Morse/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/05-Morse/Prefs/hds_team/v2019.2/title_block.tmpl b/05-Morse/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/05-Morse/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/05-Morse/Prefs/hds_team/v2019.3/hds_team_prefs b/05-Morse/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/05-Morse/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/05-Morse/Prefs/hds_team/v2019.3/title_block.tmpl b/05-Morse/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/05-Morse/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" 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+) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/05-Morse/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..da0e177 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6095 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Sublime" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Favorites/ElN_local/Labs/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs_SI/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/04-Lissajous/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/05-Morse/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/SEm_labs/05-Morse/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "$HDS_TEAM_VER/title_block.tmpl" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "courier,8,1" +) +teamPrefsPath "" +remoteSimPath "$HDS_TEAM_VER/remote" +mwMVL4 1 +mwVerilogUseSynthesisPragmas 0 +mwVhdlUseBusSlicesChkBox 0 +mwVerilogUseBusSlicesChkBox 0 +vmCheckInDesc "" +userVariables [ +(pair +first "concat_file" +second "concatenated" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +] +defaultCategoryTemplates [ +1 +"architecture.vhd" +] +defaultCategoryTemplatesPrefs [ +1 +0 +] +tasksOrder [ +"USER:Generate" +"USER:ModelSim Compile" +"USER:ModelSim Simulate" +"USER:ModelSim Flow" +"USER:Prepare for Synthesis" +"USER:Xilinx Project Navigator" +] +tasksToolbarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +"\"USER:Prepare for Synthesis\"" +"\"USER:Xilinx Project Navigator\"" +] +tasksMenubarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +] +tasksShortcutbarOrder [ +"Setup DesignChecker" +"\"USER:ModelSim Compile\"" +"\"USER:ModelSim Flow\"" +"\"USER:ModelSim Simulate\"" +"USER:Generate" +"\"USER:Prepare for Synthesis\"" +] +taskPreferences [ +(TaskPref +taskName "\"USER:Actel Place and Route\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera MegaWizard\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera SOPC Builder\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) 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[ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Microsemi Libero Flow\" \"USER:Microsemi Libero\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Microsemi Libero Flow\" USER:Generate" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Microsemi Libero Import\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair 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--git a/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..5d1345f --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/uvmRs232.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/05-Morse/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/05-Morse/Prefs/hds_user/v2018.1/hds_user_prefs b/05-Morse/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) 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b/05-Morse/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" 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+onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/05-Morse/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/05-Morse/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" 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+"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/05-Morse/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt b/05-Morse/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/05-Morse/Prefs/hds_user/v2019.2/hds_user_prefs b/05-Morse/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..7e45fd9 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6871 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap 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+cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/05-Morse/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/05-Morse/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/05-Morse/Prefs/hds_user/v2019.2/tasks/generate.tsk b/05-Morse/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..6a2954d --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/charToMorseController.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/05-Morse/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/05-Morse/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/05-Morse/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/05-Morse/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/05-Morse/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/05-Morse/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/05-Morse/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/05-Morse/Scripts/cleanGenerated.bash b/05-Morse/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/05-Morse/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/05-Morse/Scripts/cleanGenerated.bat b/05-Morse/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/05-Morse/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/05-Morse/Scripts/cleanScratch.bat b/05-Morse/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/05-Morse/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/05-Morse/Scripts/generateSSHKey.bash b/05-Morse/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/05-Morse/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/05-Morse/Scripts/hdlDesigner.bash b/05-Morse/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/05-Morse/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/05-Morse/Scripts/hdlDesigner.bat b/05-Morse/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..2a612a6 --- /dev/null +++ b/05-Morse/Scripts/hdlDesigner.bat @@ -0,0 +1,301 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +if %REQUIRE_ICECUBE2% == 1 ( + set synthesis_subdirectory="Board\icecube2" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + if %REQUIRE_ICECUBE2% == 1 ( + echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=% + echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=% + echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +if %REQUIRE_ICECUBE2% == 1 ( + if exist %ICECUBE2_BASE_DIR% ( + echo %ICECUBE2_BASE_DIR:"=% + echo -> %ICECUBE2_BASE_DIR:"=% + if exist %ICECUBE2_WORK_DIR% ( + rmdir /S /Q "%ICECUBE2_WORK_DIR%" + ) + mkdir "%ICECUBE2_WORK_DIR%" + xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW! + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/05-Morse/Scripts/searchPaths.bat b/05-Morse/Scripts/searchPaths.bat new file mode 100644 index 0000000..9b37b1b --- /dev/null +++ b/05-Morse/Scripts/searchPaths.bat @@ -0,0 +1,209 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +echo Search HEI Library +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings. + pause&goto:eof + ) +) + + +echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2 +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo %INDENT:"=%Found HDL-Designer at !HDS_HOME! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo %INDENT:"=%Found ISE at !ISE_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice Diamond directory +:: +if %REQUIRE_DIAMOND% == 1 ( + if "%DIAMOND_HOME%" == "" ( + set DIAMOND_HOME=C:\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !DIAMOND_HOME! ( + echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice IceCube2 directory +:: +if %REQUIRE_ICECUBE2% == 1 ( + if "%ICECUBE2_HOME%" == "" ( + set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !ICECUBE2_HOME! ( + echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings. + pause + goto:eof + ) +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + goto:eof \ No newline at end of file diff --git a/05-Morse/Scripts/trimLibs.pl b/05-Morse/Scripts/trimLibs.pl new file mode 100644 index 0000000..76d8d36 --- /dev/null +++ b/05-Morse/Scripts/trimLibs.pl @@ -0,0 +1,170 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ama: [Amand Axel](axel.amand@hevs.ch) +# ------------------------------------------------------------------------------ +# Changelog: +# 2023.05.16 : ama +# * Add: ice40 libs support +# 2023.02.01 : ama +# * Add: ECP5U libs support +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40 + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i) and + not($testline =~ m/ice40.*\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u or ice40 + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i) and + not($testline =~ m/ice40/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/05-Morse/Scripts/update_ise.pl b/05-Morse/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/05-Morse/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ '0'); + hReady <= '0'; + hResp <= '0'; + + -- Out + ioOut <= (OTHERS => '0'); + ioEn <= (OTHERS => '0'); + +END ARCHITECTURE studentVersion; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbUart_studentVersion.vhd b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbUart_studentVersion.vhd new file mode 100644 index 0000000..249b9d3 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbUart_studentVersion.vhd @@ -0,0 +1,36 @@ +--============================================================================== +-- +-- AHB UART +-- +-- Implements a serial port. +-- +-------------------------------------------------------------------------------- +-- +-- Write registers +-- +-- 00, data register receives the word to be sent to the serial port. +-- 01, control register is used to control the peripheral. +-- 02, scaler register is used to set the baud rate. +-- +-------------------------------------------------------------------------------- +-- +-- Read registers +-- 00, data register provides the last word received by the serial port. +-- 01, status register is used to get the peripheral's state. +-- bit 0: data ready for read +-- bit 1: sending in progress +-- bit 2: receiving in progress +-- +ARCHITECTURE studentVersion OF ahbUart IS +BEGIN + + -- AHB-Lite + hRData <= (OTHERS => '0'); + hReady <= '0'; + hResp <= '0'; + + -- Serial + TxD <= '0'; + +END ARCHITECTURE studentVersion; + diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbGpio_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbGpio_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbGpio_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbUart_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbUart_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbUart_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbgpio_entity.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbgpio_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbgpio_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbuart_entity.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbuart_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.hdlsidedata/_ahbuart_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/_ahbgpio._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/_ahbgpio._epf new file mode 100644 index 0000000..879f967 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/_ahbgpio._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom ahbGpio_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/_ahbuart._epf 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"D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "asm_file" +value "nanoTest.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahb@gpio" +) +(vvPair +variable "d_logical" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahbGpio" +) +(vvPair +variable "date" +value "03.03.2015" +) +(vvPair +variable "day" +value "mar." +) +(vvPair +variable "day_long" +value "mardi" +) +(vvPair +variable "dd" +value "03" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "ahbGpio" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE3673" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "AhbLiteComponents" +) +(vvPair +variable "library_downstream_Concatenation" +value "U:/ELN_Board/Synthesis" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "U:\\ELN_Board\\Synthesis" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../NanoBlaze/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/AhbLiteComponents/work" +) +(vvPair +variable "library_downstream_SpyGlass" +value "U:\\ELN_Board\\Synthesis" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "ahbGpio" +) +(vvPair +variable "month" +value "mars" +) +(vvPair +variable "month_long" +value "mars" +) +(vvPair +variable "p" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahb@gpio\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents\\hds\\ahbGpio\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds-beamer" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "13:18:00" +) +(vvPair +variable "unit" +value "ahbGpio" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2015" +) +(vvPair +variable "yy" +value "15" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*79 (SymbolBody +uid 8,0 +optionalChildren [ +*80 (CptPort +uid 2452,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2683,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46250,19625,47000,20375" +) +tg (CPTG +uid 2454,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2455,0 +va (VaSet +font "Verdana,12,0" +) +xt "48000,19300,52500,20700" +st "hAddr" +blo "48000,20500" +tm "CptPortNameMgr" +) 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(Text +uid 2522,0 +va (VaSet +font "Verdana,12,0" +) +xt "48000,39300,54800,40700" +st "hReset_n" +blo "48000,40500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2523,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,13000,19000,13800" +st "hReset_n : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hReset_n" +t "std_uLogic" +o 8 +suid 2064,0 +) +) +) +*89 (CptPort +uid 2651,0 +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,21625,63750,22375" +) +tg (CPTG +uid 2653,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2654,0 +va (VaSet +font "Verdana,12,0" +) +xt "57800,21300,62000,22700" +st "ioOut" +ju 2 +blo "62000,22500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2655,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21000,30500,21800" +st "ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ioOut" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 10 +suid 2065,0 +) +) +) +*90 (CptPort +uid 2692,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2693,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46250,27625,47000,28375" +) +tg (CPTG +uid 2694,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2695,0 +va (VaSet +font "Verdana,12,0" +) +xt "48000,27300,51500,28700" +st "hSel" +blo "48000,28500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2696,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,13800,19000,14600" +st "hSel : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hSel" +t "std_uLogic" +o 11 +suid 2066,0 +) +) +) +*91 (CptPort +uid 2839,0 +ps "OnEdgeStrategy" +shape (Triangle +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,23625,63750,24375" +) +tg (CPTG +uid 2841,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2842,0 +va (VaSet +font "Verdana,12,0" +) +xt "58800,23300,62000,24700" +st "ioIn" +ju 2 +blo "62000,24500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2843,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,17000,31500,17800" +st "ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "ioIn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 12 +suid 2067,0 +) +) +) +*92 (CptPort +uid 2846,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2847,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,19625,63750,20375" +) +tg (CPTG +uid 2848,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2849,0 +va (VaSet +font "Verdana,12,0" +) +xt "58500,19300,62000,20700" +st "ioEn" +ju 2 +blo "62000,20500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2850,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20200,31500,21000" +st "ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ioEn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 13 +suid 2068,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 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154,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "82000,61000,98000,62000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 155,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "82200,61000,92300,62000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*101 (CommentText +uid 156,0 +shape (Rectangle +uid 157,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,61000,78000,63000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 158,0 +va (VaSet +fg "32768,0,0" +) +xt "64150,61500,70850,62500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*102 (CommentText +uid 159,0 +shape (Rectangle +uid 160,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,64000,61000,65000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 161,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt 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137,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "57000,61000,98000,66000" +) +oxt "14000,66000,55000,71000" +) +*105 (CommentGraphic +uid 2462,0 +shape (PolyLine2D +pts [ +"47000,44000" +"63000,44000" +] +uid 2463,0 +layer 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "47000,44000,63000,44000" +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "65535,0,0" +) +packageList *106 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*107 (Text +uid 103,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*108 (MLText +uid 104,0 +va (VaSet +) +xt "0,1000,11300,6000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all;" +tm "PackageList" +) +] +) +windowSize "117,42,1421,895" +viewArea "-1500,-1500,100490,67966" +cachedDiagramExtent "0,0,98000,66000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 48 +yMargin 48 +paperWidth 761 +paperHeight 1077 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "A4" +windowsPaperName "A4" +windowsPaperType 9 +scale 75 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Courier New,9,0" +) +xt "750,1000,4250,2200" +st "Panel0" +blo "750,1900" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,47000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "29100,14700,32600,15700" +st "" +blo "29100,15500" +) +second (Text +va (VaSet +) +xt "29100,15700,31700,16700" +st "" +blo "29100,16500" +) +) +gi *109 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *110 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,9400,5400,10400" +st "Declarations" +blo "0,10200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,10400,2700,11400" +st "Ports:" +blo "0,11200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,21800,2400,22800" +st "User:" +blo "0,22600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,9400,5800,10400" +st "Internal User:" +blo "0,10200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22800,2000,22800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,9400,0,9400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 2852,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/ahb@uart/symbol.sb b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/ahb@uart/symbol.sb new file mode 100644 index 0000000..4a0a3ec --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents/hds/ahb@uart/symbol.sb @@ -0,0 +1,2089 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2067,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 320,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 1 +suid 2051,0 +) +) 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"CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "47000,46000,60500,49200" +st "Generic Declarations + +txFifoDepth positive 8 +rxFifoDepth positive 1 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "txFifoDepth" +type "positive" +value "8" +) +(GiElement +name "rxFifoDepth" +type "positive" +value "1" +) +] +) +portInstanceVis (PortSigDisplay +sTC 0 +sT 1 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*93 (Grouping +uid 136,0 +optionalChildren [ +*94 (CommentText +uid 138,0 +shape (Rectangle +uid 139,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,65000,78000,66000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 140,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,65000,71700,66000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*95 (CommentText +uid 141,0 +shape (Rectangle +uid 142,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "78000,61000,82000,62000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 143,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "78200,61000,81200,62000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*96 (CommentText +uid 144,0 +shape (Rectangle +uid 145,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,63000,78000,64000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 146,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,63000,71200,64000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*97 (CommentText +uid 147,0 +shape (Rectangle +uid 148,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,63000,61000,64000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 149,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,63000,59300,64000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*98 (CommentText +uid 150,0 +shape (Rectangle +uid 151,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "78000,62000,98000,66000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 152,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "78200,62200,87400,63200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*99 (CommentText +uid 153,0 +shape (Rectangle +uid 154,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "82000,61000,98000,62000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 155,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "82200,61000,92300,62000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*100 (CommentText +uid 156,0 +shape (Rectangle +uid 157,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,61000,78000,63000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 158,0 +va (VaSet +fg "32768,0,0" +) +xt "64150,61500,70850,62500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*101 (CommentText +uid 159,0 +shape (Rectangle +uid 160,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,64000,61000,65000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 161,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,64000,59300,65000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*102 (CommentText +uid 162,0 +shape (Rectangle +uid 163,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,65000,61000,66000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 164,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,65000,59900,66000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*103 (CommentText +uid 165,0 +shape (Rectangle +uid 166,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,64000,78000,65000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 167,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,64000,74500,65000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 137,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "57000,61000,98000,66000" +) +oxt "14000,66000,55000,71000" +) +*104 (CommentGraphic +uid 2462,0 +shape (PolyLine2D +pts [ +"47000,44000" +"63000,44000" +] +uid 2463,0 +layer 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "47000,44000,63000,44000" +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "65535,0,0" +) +packageList *105 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*106 (Text +uid 103,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*107 (MLText +uid 104,0 +va (VaSet +) +xt "0,1000,11300,6000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all;" +tm "PackageList" +) +] +) +windowSize "117,42,1422,895" +viewArea "-1500,-1500,100584,65334" +cachedDiagramExtent "0,0,98000,66000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 48 +yMargin 48 +paperWidth 761 +paperHeight 1077 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "A4" +windowsPaperName "A4" +windowsPaperType 9 +scale 75 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Courier New,9,0" +) +xt "750,1000,4250,2200" +st "Panel0" +blo "750,1900" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,47000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "29100,14700,32600,15700" +st "" +blo "29100,15500" +) +second (Text +va (VaSet +) +xt "29100,15700,31700,16700" +st "" +blo "29100,16500" +) +) +gi *108 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *109 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,9400,5400,10400" +st "Declarations" +blo "0,10200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,10400,2700,11400" +st "Ports:" +blo "0,11200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,21000,2400,22000" +st "User:" +blo "0,21800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,9400,5800,10400" +st "Internal User:" +blo "0,10200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22000,2000,22000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,9400,0,9400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 2869,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/AMBA_AHB-Lite_spec.pdf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/AMBA_AHB-Lite_spec.pdf new file mode 100644 index 0000000..99e720c Binary files /dev/null and b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/AMBA_AHB-Lite_spec.pdf differ diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/MAX11300.pdf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/MAX11300.pdf new file mode 100644 index 0000000..90e7065 Binary files /dev/null and b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/MAX11300.pdf differ diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/ad670.pdf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/ad670.pdf new file mode 100644 index 0000000..9f701ec Binary files /dev/null and b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/doc/ad670.pdf differ diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbGpio_tester_test.vhd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbGpio_tester_test.vhd new file mode 100644 index 0000000..f6f2116 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbGpio_tester_test.vhd @@ -0,0 +1,261 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF ahbGpio_tester IS + -- reset and clock + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + signal reset_int: std_uLogic; + -- test information + signal noteTopSeparator : string(1 to 80) := (others => '-'); + signal errorTopSeparator : string(1 to 80) := (others => '#'); + signal bottomSeparator : string(1 to 80) := (others => '.'); + signal indentation : string(1 to 2) := (others => ' '); + signal noteInformation : string(1 to 9) := (others => ' '); + signal errorInformation : string(1 to 10) := (others => ' '); + signal failureInformation : string(1 to 12) := (others => ' '); + signal testInformation : string(1 to 50) := (others => ' '); + -- register definition + constant peripheralBaseAddress: natural := 2**4; + constant dataRegisterAddress: natural := 0; + constant outputEnableRegisterAddress: natural := 1; + -- AMBA bus access + signal registerAddress: natural; + signal registerData: integer; + signal registerWrite: std_uLogic; + signal registerRead: std_uLogic; + signal writeFlag, readFlag, readFlag1: std_uLogic; + signal writeData, readData: integer; + -- GPIO access + signal ioData: integer; + signal ioMask: integer; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset_int <= '1', '0' after 2*clockPeriod; + hReset_n <= not(reset_int); + + clock_int <= not clock_int after clockPeriod/2; + hClk <= transport clock_int after clockPeriod*9.0/10.0; + + ------------------------------------------------------------------------------ + -- test sequence + testSequence: process + begin + registerAddress <= 0; + registerData <= 0; + registerWrite <= '0'; + registerRead <= '0'; + ioData <= 0; + ioMask <= 0; + wait for 100 ns; + + ---------------------------------------------------------------------------- + -- simple test + -- write en mask + testInformation <= pad("Writing data on the GPIO", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + ioData <= 16#AA#; + ioMask <= 16#0F#; wait for 0 ns; + registerAddress <= outputEnableRegisterAddress; + registerData <= ioMask; + registerWrite <= '1', '0' after clockPeriod/2; + wait for 4*clockPeriod; + -- write output data 55h + registerAddress <= dataRegisterAddress; + registerData <= 16#55#; + registerWrite <= '1', '0' after clockPeriod; + wait for 4*clockPeriod; + assert io = x"A5" + report + errorTopSeparator & cr & + noteInformation & indentation & "IO data not as expected" & cr & + noteInformation & bottomSeparator + severity error; + -- read data + testInformation <= pad("Reading data from the GPIO", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= dataRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#A5# + report + errorTopSeparator & cr & + noteInformation & indentation & "read data not as expected" & cr & + noteInformation & bottomSeparator + severity error; + wait for 100 ns; + + ---------------------------------------------------------------------------- + -- test with a different base address + -- write en mask + testInformation <= pad( + "Writing data to a different base address", testInformation'length + ); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + ioData <= 16#AA#; + ioMask <= 16#F0#; wait for 0 ns; + registerAddress <= peripheralBaseAddress + outputEnableRegisterAddress; + registerData <= ioMask; + registerWrite <= '1', '0' after clockPeriod; + wait for 4*clockPeriod; + -- write output data 55h + registerAddress <= peripheralBaseAddress + dataRegisterAddress; + registerData <= 16#55#; + registerWrite <= '1', '0' after clockPeriod; + wait for 4*clockPeriod; + -- read data + registerAddress <= peripheralBaseAddress + dataRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#5A# + report + errorTopSeparator & cr & + noteInformation & indentation & "read data not as expected" & cr & + noteInformation & bottomSeparator + severity error; + wait for 4*clockPeriod; + + ---------------------------------------------------------------------------- + -- access back to back + -- write en mask + testInformation <= pad("Accessing at full speed", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + wait until rising_edge(clock_int); + ioData <= 16#AA#; + ioMask <= 16#0F#; wait for 0 ns; + registerAddress <= outputEnableRegisterAddress; + registerData <= ioMask; + registerWrite <= '1' after clockPeriod/4, '0' after clockPeriod/2; + -- write output data 55h + wait until rising_edge(clock_int); + registerAddress <= dataRegisterAddress; + registerData <= 16#55#; + registerWrite <= '1' after clockPeriod/4, '0' after clockPeriod/2; + -- read data + wait until rising_edge(clock_int); + registerAddress <= dataRegisterAddress; + registerRead <= '1' after clockPeriod/4, '0' after clockPeriod/2; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#A5# + report + errorTopSeparator & cr & + noteInformation & indentation & "read data not as expected" & cr & + noteInformation & bottomSeparator + severity error; + wait for 4*clockPeriod; + -- end of simulation + wait for 100 ns; + testInformation <= pad("End of tests", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + failureInformation & indentation & testInformation & cr & + failureInformation & bottomSeparator + severity failure; + wait; + end process testSequence; + + ------------------------------------------------------------------------------ + -- AMBA bus access + -- phase 1: address and controls + busAccess1: process + variable writeAccess: boolean := false; + begin + wait on reset_int, registerWrite, registerRead; + if falling_edge(reset_int) then + hAddr <= (others => '-'); + hTrans <= transIdle; + hSel <= '0'; + writeFlag <= '0'; + end if; + if rising_edge(registerWrite) or rising_edge(registerRead) then + writeAccess := false; + if rising_edge(registerWrite) then + writeAccess := true; + end if; + wait until rising_edge(clock_int); + hAddr <= to_unsigned(registerAddress, hAddr'length), + (others => '-') after clockPeriod + 1 ns; + hTrans <= transNonSeq, transIdle after clockPeriod + 1 ns; + hSel <= '1', '0' after clockPeriod + 1 ns; + if writeAccess then + writeFlag <= '1', '0' after clockPeriod + 1 ns; + writeData <= registerData; + else + readFlag <= '1', '0' after clockPeriod + 1 ns; + end if; + end if; + end process busAccess1; + + hWrite <= writeFlag; + -- phase 2: data write + busAccess2: process + begin + wait until rising_edge(clock_int); + hWData <= (others => '-'); + readFlag1 <= '0'; + if writeFlag = '1' then + hWData <= std_uLogic_vector(to_signed(writeData, hWData'length)); + end if; + readFlag1 <= readFlag; + end process busAccess2; + -- phase 3: data read + busAccess3: process + begin + wait until rising_edge(clock_int); + if readFlag1 = '1' then + readData <= to_integer(to_01(unsigned(hRData))); + end if; + end process busAccess3; + + ------------------------------------------------------------------------------ + -- GPIO access + linesAccess: process(ioData, ioMask) + variable ioDataVector: unsigned(io'range); + variable ioMaskVector: unsigned(io'range); + begin + ioDataVector := to_unsigned(ioData, ioDataVector'length); + ioMaskVector := to_unsigned(ioMask, ioMaskVector'length); + for index in io'range loop + if ioMaskVector(index) = '1' then + io(index) <= 'Z'; + else + io(index) <= ioDataVector(index); + end if; + end loop; + end process; + +END ARCHITECTURE test; diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbUart_tester_test.vhd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbUart_tester_test.vhd new file mode 100644 index 0000000..4299ea5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbUart_tester_test.vhd @@ -0,0 +1,330 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + + +ARCHITECTURE test OF ahbUart_tester IS + -- reset and clock + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + signal reset_int: std_uLogic; + -- test information + signal noteTopSeparator : string(1 to 80) := (others => '-'); + signal errorTopSeparator : string(1 to 80) := (others => '#'); + signal bottomSeparator : string(1 to 80) := (others => '.'); + signal indentation : string(1 to 2) := (others => ' '); + signal noteInformation : string(1 to 9) := (others => ' '); + signal errorInformation : string(1 to 10) := (others => ' '); + signal failureInformation : string(1 to 12) := (others => ' '); + signal testInformation : string(1 to 50) := (others => ' '); + -- register definition + constant dataRegisterAddress: natural := 0; + constant controlRegisterAddress: natural := 1; + constant scalerRegisterAddress: natural := 2; + + constant statusRegisterAddress: natural := 1; + constant statusValidAddress: natural := 0; + constant valueRegisterAddress: natural := 1; + -- AMBA bus access + signal registerAddress: natural; + signal registerData: integer; + signal registerWrite: std_uLogic; + signal registerRead: std_uLogic; + signal writeFlag, readFlag, readFlag1: std_uLogic; + signal writeData, readData: integer; + -- UART access + constant baudPeriodNb: positive := 4; + signal uartData: integer; + signal uartSend: std_uLogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset_int <= '1', '0' after 2*clockPeriod; + hReset_n <= not(reset_int); + + clock_int <= not clock_int after clockPeriod/2; + hClk <= transport clock_int after clockPeriod*9.0/10.0; + + ------------------------------------------------------------------------------ + -- test sequence + testSequence: process + begin + registerAddress <= 0; + registerData <= 0; + registerWrite <= '0'; + registerRead <= '0'; + uartSend <= '0'; + wait for 1 us; + -- write baud rate + testInformation <= pad("Writing baud rate", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= scalerRegisterAddress; + registerData <= baudPeriodNb; + registerWrite <= '1', '0' after clockPeriod; + wait for 4*clockPeriod; + -- write Tx data 55h + testInformation <= pad("Writing Tx data", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= dataRegisterAddress; + registerData <= 16#55#; + registerWrite <= '1', '0' after clockPeriod; + wait for 20*baudPeriodNb*clockPeriod; + -- write Tx data 0Fh + testInformation <= (others => ' '); + wait for 1 ns; + testInformation <= pad("Writing Tx data", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= dataRegisterAddress; + registerData <= 16#0F#; + registerWrite <= '1', '0' after clockPeriod; + wait for 4*clockPeriod; + -- read status + testInformation <= pad("Reading status", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= statusRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#02# + report + errorTopSeparator & cr & + errorInformation & indentation & + "expected status sending flag" & cr & + errorInformation & bottomSeparator + severity error; + wait for 12*baudPeriodNb*clockPeriod; + -- read status + testInformation <= (others => ' '); + wait for 1 ns; + testInformation <= pad("Reading status", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#00# + report + errorTopSeparator & cr & + errorInformation & indentation & + "expected no flag" & cr & + errorInformation & bottomSeparator + severity error; + wait for 20*baudPeriodNb*clockPeriod; + -- receive AAh + testInformation <= pad("Receiving Rx data", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + uartData <= 16#AA#; + uartSend <= '1', '0' after clockPeriod; + wait for 4*clockPeriod; + -- read status + testInformation <= pad("Reading status", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= statusRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#04# + report + errorTopSeparator & cr & + errorInformation & indentation & + "expected status receiving flag" & cr & + errorInformation & bottomSeparator + severity error; + wait for 10*baudPeriodNb*clockPeriod; + -- read status again + testInformation <= (others => ' '); + wait for 1 ns; + testInformation <= pad("Reading status", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#01# + report + errorTopSeparator & cr & + errorInformation & indentation & + "expected status data available flag" & cr & + errorInformation & bottomSeparator + severity error; + wait for 4*clockPeriod; + -- read data + testInformation <= pad("Reading data", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= dataRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#AA# + report + errorTopSeparator & cr & + errorInformation & indentation & "read data not as expected" & cr & + errorInformation & bottomSeparator + severity error; + wait for 4*clockPeriod; + -- read status + testInformation <= pad("Reading status", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + noteInformation & indentation & testInformation & cr & + noteInformation & bottomSeparator + severity note; + registerAddress <= statusRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + for index in 1 to 4 loop + wait until rising_edge(clock_int); + end loop; + assert readData = 16#00# + report + errorTopSeparator & cr & + errorInformation & indentation & + "expected no flag" & cr & + errorInformation & bottomSeparator + severity error; + wait for 4*clockPeriod; + -- end of simulation + wait for 100 ns; + testInformation <= pad("End of tests", testInformation'length); + wait for 0 ns; + assert false + report + noteTopSeparator & cr & + failureInformation & indentation & testInformation & cr & + failureInformation & bottomSeparator + severity failure; + wait; + end process testSequence; + + ------------------------------------------------------------------------------ + -- AMBA bus access + -- phase 1: address and controls + busAccess1: process + variable writeAccess: boolean := false; + begin + wait on reset_int, registerWrite, registerRead; + if falling_edge(reset_int) then + hAddr <= (others => '-'); + hTrans <= transIdle; + hSel <= '0'; + writeFlag <= '0'; + end if; + if rising_edge(registerWrite) or rising_edge(registerRead) then + writeAccess := false; + if rising_edge(registerWrite) then + writeAccess := true; + end if; + wait until rising_edge(clock_int); + hAddr <= to_unsigned(registerAddress, hAddr'length), + (others => '-') after clockPeriod + 1 ns; + hTrans <= transNonSeq, transIdle after clockPeriod + 1 ns; + hSel <= '1', '0' after clockPeriod + 1 ns; + if writeAccess then + writeFlag <= '1', '0' after clockPeriod + 1 ns; + writeData <= registerData; + else + readFlag <= '1', '0' after clockPeriod + 1 ns; + end if; + end if; + end process busAccess1; + + hWrite <= writeFlag; + -- phase 2: data write + busAccess2: process + begin + wait until rising_edge(clock_int); + hWData <= (others => '-'); + readFlag1 <= '0'; + if writeFlag = '1' then + hWData <= std_uLogic_vector(to_signed(writeData, hWData'length)); + end if; + readFlag1 <= readFlag; + end process busAccess2; + -- phase 3: data read + busAccess3: process + begin + wait until rising_edge(clock_int); + if readFlag1 = '1' then + readData <= to_integer(to_01(unsigned(hRData))); + end if; + end process busAccess3; + + ------------------------------------------------------------------------------ + -- UART access + sendByte: process + variable serialData: unsigned(7 downto 0); + begin + -- send stop bit + RxD <= '1'; + -- get new word + wait until rising_edge(uartSend); + serialData := to_unsigned(uartData, serialData'length); + -- send start bit + RxD <= '0'; + wait for baudPeriodNb * clockPeriod; + -- send data bits + for index in serialData'reverse_range loop + RxD <= serialData(index); + wait for baudPeriodNb * clockPeriod; + end loop; + end process sendByte; + +END ARCHITECTURE test; diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/uvmAhbDriver_sim.vhd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/uvmAhbDriver_sim.vhd new file mode 100644 index 0000000..e8514e6 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/uvmAhbDriver_sim.vhd @@ -0,0 +1,74 @@ +LIBRARY std; + USE std.TEXTIO.all; +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE RTL OF uvmAhbDriver IS + + constant flipflopDelay: time := 1 ns; + + signal hAddr1, hWData1, hWData2: natural := 0; + signal hWrite1, hWrite2, hRead1, hRead2: std_ulogic := '0'; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + hReset_n <= not(reset); + hClk <= clock; + + ------------------------------------------------------------------------------ + -- interpret transaction + interpretTransaction: process(driverTransaction) + variable my_line : line; + variable command_part : line; + begin + write(my_line, driverTransaction); + read_first(my_line, command_part); + if command_part.all = "write" then + read_first(my_line, command_part); + hAddr1 <= sscanf(command_part.all); + read_first(my_line, command_part); + hWData1 <= sscanf(command_part.all); + hWrite1 <= '1', '0' after 1 ns; + elsif command_part.all = "read" then + read_first(my_line, command_part); + hAddr1 <= sscanf(command_part.all); + hRead1 <= '1', '0' after 1 ns; + end if; + deallocate(my_line); + end process interpretTransaction; + -- expand pulses to the next clock + expandReadWrite: process + begin + hRead2 <= '0'; + hWrite2 <= '0'; + wait on hRead1, hWrite1; + hRead2 <= hRead1; + hWrite2 <= hWrite1; + wait until rising_edge(clock); + end process expandReadWrite; + -- delay signals 1 or 2 clock periods + synchAccess: process(reset, clock) + begin + if reset = '1' then + hAddr <= (others => '0'); + hWData2 <= 0; + hWData <= (others => '0'); + hWrite <= '0'; + hSel <= '0'; + hTrans <= transIdle; + elsif rising_edge(clock) then + hAddr <= to_unsigned(hAddr1, hAddr'length) after flipflopDelay; + hWData2 <= hWData1; + hWData <= std_ulogic_vector(to_unsigned(hWData2, hWData'length)) after flipflopDelay; + hWrite <= hWrite2 after flipflopDelay; + hSel <= hWrite2 or hRead2 after flipflopDelay; + if (hWrite2 = '1') or (hRead2 = '1') then + hTrans <= transNonSeq after flipflopDelay; + else + hTrans <= transIdle after flipflopDelay; + end if; + end if; + end process synchAccess; + +END ARCHITECTURE RTL; diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/uvmAhbMonitor_sim.vhd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/uvmAhbMonitor_sim.vhd new file mode 100644 index 0000000..395ea6f --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/uvmAhbMonitor_sim.vhd @@ -0,0 +1,49 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE RTL OF uvmAhbMonitor IS + + signal addressReg: unsigned(hAddr'range); + signal writeReg: std_ulogic; + signal readReg: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- register address and controls + storeControls: process(hReset_n, hClk) + begin + if not(hReset_n) = '1' then + addressReg <= (others => '0'); + writeReg <= '0'; + readReg <= '0'; + elsif rising_edge(hClk) then + writeReg <= '0'; + readReg <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addressReg <= hAddr(addressReg'range); + writeReg <= hWrite; + readReg <= not hWrite; + end if; + end if; + end process storeControls; + -- monitor acesses + reportBusAccess: process(hReset_n, hClk) + begin + if not(hReset_n) = '1' then + monitorTransaction <= pad( false, ' ', monitorTransaction'length, "idle"); + elsif rising_edge(hClk) then + if readReg = '1' then + monitorTransaction <= pad( + false, ' ', monitorTransaction'length, + "read " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hRData) + ); + elsif writeReg = '1' then + monitorTransaction <= pad( + false, ' ', monitorTransaction'length, + "written " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hWData) + ); + end if; + end if; + end process reportBusAccess; + +END ARCHITECTURE RTL; diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbGpio_tester_test.vhd._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbGpio_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbGpio_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbUart_tester_test.vhd._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbUart_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbUart_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tester_entity.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tester_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbgpio_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_entity.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_struct.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tester_entity.vhg._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tester_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_ahbuart_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbDriver_sim.vhd._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbDriver_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbDriver_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbMonitor_sim.vhd._fpf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbMonitor_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.hdlsidedata/_uvmAhbMonitor_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tb._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tb._epf new file mode 100644 index 0000000..a4f9fe7 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom ahb@gpio_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tester._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tester._epf new file mode 100644 index 0000000..1f5a6c5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbgpio_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom ahbGpio_tester_test.vhd diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tb._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tb._epf new file mode 100644 index 0000000..833e6e1 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom ahb@uart_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tester._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tester._epf new file mode 100644 index 0000000..254f3eb --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_ahbuart_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom ahbUart_tester_test.vhd diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbagenthw._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbagenthw._epf new file mode 100644 index 0000000..7620737 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbagenthw._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom uvm@ahb@agent@hw/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbdriver._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbdriver._epf new file mode 100644 index 0000000..69ad7cc --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbdriver._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom uvmAhbDriver_sim.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbmonitor._epf b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbmonitor._epf new file mode 100644 index 0000000..cba4a77 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/_uvmahbmonitor._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom uvmAhbMonitor_sim.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd new file mode 100644 index 0000000..018b5fa --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd @@ -0,0 +1,4005 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "AhbLiteComponents_test" +duName "ahbGpio_tester" +elements [ +(GiElement +name "ioNb" +type "positive" +value "ioNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +mwi 0 +uid 12657,0 +) +(Instance +name "I_DUT" +duLibraryName "AhbLiteComponents" +duName "ahbGpio" +elements [ +(GiElement +name "ioNb" +type "positive" +value "ioNb" +) +] +mwi 0 +uid 13194,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb" +) +(vvPair +variable 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"VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*43 (HdlText +uid 13204,0 +optionalChildren [ +*44 (EmbeddedText +uid 13246,0 +commentText (CommentText +uid 13247,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 13248,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "104000,34000,120000,44000" +) +oxt "0,0,18000,5000" +text (MLText +uid 13249,0 +va (VaSet +) +xt "104200,34200,119200,43800" +st " +tristate: process(ioEn, ioOut) +begin + for index in io'range loop + if ioEn(index) = '1' then + io(index) <= ioOut(index); + else + io(index) <= 'Z'; + end if; + end loop; +end process tristate; + +ioIn <= std_ulogic_vector(io); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 13205,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "104000,33000,120000,45000" +) +oxt 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(OrthoPolyLine +uid 13221,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "88750,39000,104000,39000" +pts [ +"88750,39000" +"104000,39000" +] +) +start &36 +end &43 +sat 32 +eat 1 +sty 1 +stc 0 +sf 1 +si 0 +tg (WTG +uid 13224,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 13225,0 +va (VaSet +font "Verdana,12,0" +) +xt "90750,37600,94950,39000" +st "ioOut" +blo "90750,38800" +tm "WireNameMgr" +) +) +on &48 +) +*63 (Wire +uid 13228,0 +shape (OrthoPolyLine +uid 13229,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "88750,41000,104000,41000" +pts [ +"88750,41000" +"104000,41000" +] +) +start &38 +end &43 +sat 32 +eat 2 +sty 1 +stc 0 +sf 1 +si 0 +tg (WTG +uid 13232,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 13233,0 +va (VaSet +font "Verdana,12,0" +) +xt "90750,39600,93950,41000" +st "ioIn" +blo "90750,40800" +tm "WireNameMgr" +) +) +on &49 +) +*64 (Wire +uid 13236,0 +shape (OrthoPolyLine +uid 13237,0 +va (VaSet +vasetType 3 +lineWidth 2 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diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tester/interface b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tester/interface new file mode 100644 index 0000000..20ae94a --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tester/interface @@ -0,0 +1,2036 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 66,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 130,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm 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"PackageList" +) +] +) +windowSize "239,85,1256,775" +viewArea "-500,-500,71320,48820" +cachedDiagramExtent "0,0,105000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 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Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va 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734,0 +activeModelName "Symbol:GEN" +) diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@uart_tb/struct.bd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@uart_tb/struct.bd new file mode 100644 index 0000000..3361ac7 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@uart_tb/struct.bd @@ -0,0 +1,3697 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "AhbLiteComponents_test" +duName "ahbUart_tester" +elements [ +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +mwi 0 +uid 12657,0 +) +(Instance +name "I_DUT" +duLibraryName "AhbLiteComponents" +duName "ahbUart" +elements [ +(GiElement +name "txFifoDepth" +type "positive" +value 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+decl (Decl +n "hSel" +t "std_uLogic" +o 9 +suid 53,0 +) +) +) +*85 (CptPort +uid 1249,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1250,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26625,5250,27375,6000" +) +tg (CPTG +uid 1251,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1252,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "26300,7000,27700,12100" +st "hTrans" +ju 2 +blo "27500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1253,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,78000,10000" +st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 10 +suid 54,0 +) +) +) +*86 (CptPort +uid 1254,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1255,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24625,5250,25375,6000" +) +tg (CPTG +uid 1256,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1257,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "24300,7000,25700,12900" +st "hWData" +ju 2 +blo "25500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1258,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,77500,10800" +st "hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 11 +suid 55,0 +) +) +) +*87 (CptPort +uid 1259,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1260,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "28625,5250,29375,6000" +) +tg (CPTG +uid 1261,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1262,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "28300,7000,29700,12000" +st "hWrite" +ju 2 +blo "29500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1263,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,60000,11600" +st "hWrite : OUT std_uLogic +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWrite" +t "std_uLogic" +o 12 +suid 56,0 +) +) +) +*88 (CptPort +uid 1264,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1265,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "64625,5250,65375,6000" +) +tg (CPTG +uid 1266,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1267,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "64300,7000,65700,10200" +st "RxD" +ju 2 +blo "65500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1268,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,61000,6000" +st "RxD : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "RxD" +t "std_ulogic" +o 1 +suid 57,0 +) +) +) +*89 (CptPort +uid 1269,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1270,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "66625,5250,67375,6000" +) +tg (CPTG +uid 1271,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1272,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "66300,7000,67700,10100" +st "TxD" +ju 2 +blo "67500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1273,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,61000,2800" +st "TxD : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "TxD" +t "std_ulogic" +o 2 +suid 58,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,75000,14000" +) +oxt "15000,6000,73000,14000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "39600,9000,50400,10000" +st "AhbLiteComponents_test" +blo "39600,9800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "39600,10000,45900,11000" +st "ahbUart_tester" +blo "39600,10800" +) +) +gi *90 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "21000,6000,33500,8400" +st "Generic Declarations + +clockFrequency real " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "clockFrequency" +type "real" +value "" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*91 (Grouping +uid 16,0 +optionalChildren [ +*92 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48500,36200,48500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*93 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44500,53200,44500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*94 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46500,36200,46500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*95 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46500,32200,46500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*96 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,67300,46400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*97 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44500,57200,44500" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*98 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "37350,44400,47650,45600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*99 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47500,32200,47500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*100 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48500,32200,48500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*101 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47500,36200,47500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *102 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*103 (Text +uid 49,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*104 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,17500,7000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all;" +tm "PackageList" +) +] +) +windowSize "246,67,1263,757" +viewArea "-500,-500,71320,48820" +cachedDiagramExtent "0,0,78000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "AhbLiteComponents_test" +entityName "ahbUart_tb" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *105 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *106 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,11600,44400,12600" +st "User:" +blo "42000,12400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12600,44000,12600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 1297,0 +activeModelName "Symbol:GEN" +) diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@agent@hw/struct.bd b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@agent@hw/struct.bd new file mode 100644 index 0000000..3c0d443 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@agent@hw/struct.bd @@ -0,0 +1,5392 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "NUMERIC_STD" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +instances [ +(Instance +name "I_file2trans" +duLibraryName "UVM" +duName "driverControl" +elements [ +(GiElement +name "driverFileSpec" +type "string" +value "driverFileSpec" +) +(GiElement +name "verbosity" +type "natural" +value "driverVerbosity" +) +] +mwi 0 +uid 136,0 +) +(Instance +name "U_trans2File" +duLibraryName "UVM" +duName "monitorSupervision" +elements [ +(GiElement +name "monitorFileSpec" +type "string" +value "monitorFileSpec" +) +(GiElement +name "verbosity" +type "natural" +value "monitorVerbosity" +) +] +mwi 0 +uid 150,0 +) +(Instance +name "I_driv" +duLibraryName "AhbLiteComponents_test" +duName "uvmAhbDriver" +elements [ +] +mwi 0 +uid 977,0 +) +(Instance +name "I_mon" +duLibraryName "AhbLiteComponents_test" +duName "uvmAhbMonitor" +elements [ +] +mwi 0 +uid 1031,0 +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvmAhbAgentHw" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "uvmAhbAgentHw" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:07:09" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "AhbLiteComponents_test" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/AhbLiteComponents_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "uvmAhbAgentHw" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvm@ahb@agent@hw\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\uvmAhbAgentHw\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_AsmPath" +value "$HDS_LIBS_DIR\\NanoBlaze\\hdl" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:07:09" +) +(vvPair +variable "unit" +value "uvmAhbAgentHw" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "72000,73000,89000,74000" +) +oxt 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+fg "0,65535,0" +) +xt "54000,22625,54750,23375" +) +tg (CPTG +uid 404,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 405,0 +va (VaSet +) +xt "49200,22400,53000,23600" +st "hResp" +ju 2 +blo "53000,23400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 406,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,11800,17000,12600" +st "hResp : IN std_uLogic ;" +) +thePort (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 4 +suid 25,0 +) +) +) +*91 (CptPort +uid 407,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 408,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,16625,54750,17375" +) +tg (CPTG +uid 409,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 410,0 +va (VaSet +) +xt "50100,16400,53000,17600" +st "hSel" +ju 2 +blo "53000,17400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 411,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,15800,17000,16600" +st "hSel : OUT std_uLogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 9 +suid 26,0 +) +) +) +*92 (CptPort +uid 412,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 413,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,12625,54750,13375" +) +tg (CPTG +uid 414,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 415,0 +va (VaSet +) +xt "48800,12400,53000,13600" +st "hTrans" +ju 2 +blo "53000,13400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 416,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,16600,34000,17400" +st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 10 +suid 27,0 +) +) +) +*93 (CptPort +uid 417,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 418,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,10625,54750,11375" +) +tg (CPTG +uid 419,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 420,0 +va (VaSet +) +xt "48400,10400,53000,11600" +st "hWData" +ju 2 +blo "53000,11400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 421,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,17400,33500,18200" +st "hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 11 +suid 28,0 +) +) +) +*94 (CptPort +uid 422,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 423,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,14625,54750,15375" +) +tg (CPTG +uid 424,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 425,0 +va (VaSet +) +xt "49100,14400,53000,15600" +st "hWrite" +ju 2 +blo "53000,15400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 426,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,18200,16000,19000" +st "hWrite : OUT std_uLogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWrite" +t "std_uLogic" +o 12 +suid 29,0 +) +) +) +*95 (CptPort +uid 427,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 428,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,28625,38000,29375" +) +tg (CPTG +uid 429,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 430,0 +va (VaSet +) +xt "39000,28400,42300,29600" +st "reset" +blo "39000,29400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 431,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12600,17000,13400" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 30,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "38000,5000,54000,31000" +) +oxt "15000,6000,27000,16000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Verdana,9,1" +) +xt "37600,31000,52200,32200" +st "AhbLiteComponents_test" +blo "37600,32000" +) +second (Text +uid 12,0 +va (VaSet +font "Verdana,9,1" +) +xt "37600,32200,47600,33400" +st "uvmAhbAgentHw" +blo "37600,33200" +) +) +gi *96 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "38000,35200,53000,40000" +st "Generic Declarations + +driverVerbosity integer +driverFileSpec string +monitorVerbosity integer +monitorFileSpec string " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "driverVerbosity" +type "integer" +value "" +) +(GiElement +name "driverFileSpec" +type "string" +value "" +) +(GiElement +name "monitorVerbosity" +type "integer" +value "" +) +(GiElement +name "monitorFileSpec" +type "string" +value "" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*97 (Grouping +uid 16,0 +optionalChildren [ +*98 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,48000,51000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,48500,34200,48500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*99 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,44000,55000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,44500,51200,44500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*100 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,46000,51000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,46500,34200,46500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*101 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,46000,34000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,46500,30200,46500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*102 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,45000,71000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,45200,65300,46400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*103 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "55000,44000,71000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "55200,44500,55200,44500" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*104 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,44000,51000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "35350,44400,45650,45600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*105 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,47000,34000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,47500,30200,47500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*106 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,48000,34000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,48500,30200,48500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*107 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,47000,51000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,47500,34200,47500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "30000,44000,71000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *108 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*109 (Text +uid 49,0 +va (VaSet +font "arial,8,1" +) +xt "-2000,0,3400,1000" +st "Package List" +blo "-2000,800" +) +*110 (MLText +uid 50,0 +va (VaSet +) +xt "-2000,1000,15500,7000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.NUMERIC_STD.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all;" +tm "PackageList" +) +] +) +windowSize "136,41,1414,882" +viewArea "-3051,-1040,72660,50935" +cachedDiagramExtent "-2000,0,71000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "-2000,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *111 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *112 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "-2000,7400,3400,8400" +st "Declarations" +blo "-2000,8200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "-2000,8400,700,9400" +st "Ports:" +blo "-2000,9200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "-2000,19000,400,20000" +st "User:" +blo "-2000,19800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "-2000,7400,3800,8400" +st "Internal User:" +blo "-2000,8200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,20000,0,20000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "-2000,7400,-2000,7400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 624,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@driver/symbol.sb b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@driver/symbol.sb new file mode 100644 index 0000000..97fe935 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@driver/symbol.sb @@ -0,0 +1,2001 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2074,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 320,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 5 +suid 2051,0 +) +) +uid 2524,0 +) +*15 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 10 +suid 2053,0 +) +) +uid 2526,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hWrite" +t "std_uLogic" +o 11 +suid 2055,0 +) +) +uid 2530,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 9 +suid 2059,0 +) +) +uid 2538,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 2 +suid 2061,0 +) +) +uid 2542,0 +) +*19 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hClk" +t "std_uLogic" +o 6 +suid 2063,0 +) +) +uid 2546,0 +) +*20 (LogPort +port (LogicalPort +m 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"D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds\\ahb@driver\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds\\ahb@driver" +) +(vvPair +variable "d_logical" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds\\ahbDriver" +) +(vvPair +variable "date" +value "15.06.2015" +) +(vvPair +variable "day" +value "lun." +) +(vvPair +variable "day_long" +value "lundi" +) +(vvPair +variable "dd" +value "15" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "ahbDriver" +) +(vvPair +variable "ext" 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+variable "module_name" +value "ahbDriver" +) +(vvPair +variable "month" +value "juin" +) +(vvPair +variable "month_long" +value "juin" +) +(vvPair +variable "p" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds\\ahb@driver\\symbol.sb" +) +(vvPair +variable "p_logical" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds\\ahbDriver\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds-beamer" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_AsmPath" +value "$HDS_LIBS_DIR\\NanoBlaze\\hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value 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+fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,65000,71200,66000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*88 (CommentText +uid 141,0 +shape (Rectangle +uid 142,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "78000,61000,82000,62000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 143,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "78200,61000,81200,62000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*89 (CommentText +uid 144,0 +shape (Rectangle +uid 145,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,63000,78000,64000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 146,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,63000,71200,64000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*90 (CommentText +uid 147,0 +shape (Rectangle +uid 148,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,63000,61000,64000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 149,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,63000,59300,64000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*91 (CommentText +uid 150,0 +shape (Rectangle +uid 151,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "78000,62000,98000,66000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 152,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "78200,62200,87400,63200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*92 (CommentText +uid 153,0 +shape (Rectangle +uid 154,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "82000,61000,98000,62000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 155,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "82200,61000,92300,62000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*93 (CommentText +uid 156,0 +shape (Rectangle +uid 157,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,61000,78000,63000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 158,0 +va (VaSet +fg "32768,0,0" +) +xt "64150,61500,70850,62500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*94 (CommentText +uid 159,0 +shape (Rectangle +uid 160,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,64000,61000,65000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 161,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,64000,59300,65000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*95 (CommentText +uid 162,0 +shape (Rectangle +uid 163,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,65000,61000,66000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 164,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,65000,59900,66000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*96 (CommentText +uid 165,0 +shape (Rectangle +uid 166,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,64000,78000,65000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 167,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,64000,76700,65000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 137,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "57000,61000,98000,66000" +) +oxt "14000,66000,55000,71000" +) +*97 (CommentGraphic +uid 2462,0 +shape (PolyLine2D +pts [ +"47000,44000" +"63000,44000" +] +uid 2463,0 +layer 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "47000,44000,63000,44000" +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "65535,0,0" +) +packageList *98 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*99 (Text +uid 103,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*100 (MLText +uid 104,0 +va (VaSet +) +xt "0,1000,11300,6000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; +" +tm "PackageList" +) +] +) +windowSize "117,42,1429,895" +viewArea "-1400,-1400,101342,68066" +cachedDiagramExtent "0,0,98000,66000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 48 +yMargin 48 +paperWidth 761 +paperHeight 1077 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "A4" +windowsPaperName "A4" +windowsPaperType 9 +scale 75 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Courier New,9,0" +) +xt "750,1000,4250,2200" +st "Panel0" +blo "750,1900" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,47000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "29100,14700,32600,15700" +st "" +blo "29100,15500" +) +second (Text +va (VaSet +) +xt "29100,15700,31700,16700" +st "" +blo "29100,16500" +) +) +gi *101 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *102 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,9400,5400,10400" +st "Declarations" +blo "0,10200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,10400,2700,11400" +st "Ports:" +blo "0,11200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,20200,2400,21200" +st "User:" +blo "0,21000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,9400,5800,10400" +st "Internal User:" +blo "0,10200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,21200,2000,21200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,9400,0,9400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 3091,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@monitor/symbol.sb b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@monitor/symbol.sb new file mode 100644 index 0000000..cde51a8 --- /dev/null +++ b/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@monitor/symbol.sb @@ -0,0 +1,1993 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2074,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 320,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 4 +suid 2051,0 +) +) +uid 2524,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 9 +suid 2053,0 +) +) +uid 2526,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 1 +suid 2054,0 +) +) +uid 2528,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "hWrite" +t "std_uLogic" +o 10 +suid 2055,0 +) +) +uid 2530,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 8 +suid 2059,0 +) +) +uid 2538,0 +) +*19 (LogPort +port (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 2 +suid 2061,0 +) +) +uid 2542,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 3 +suid 2062,0 +) +) +uid 2544,0 +) +*21 (LogPort +port (LogicalPort +decl (Decl +n "hClk" +t "std_uLogic" +o 5 +suid 2063,0 +) +) +uid 2546,0 +) +*22 (LogPort +port (LogicalPort +decl (Decl +n "hReset_n" +t "std_uLogic" +o 6 +suid 2064,0 +) +) +uid 2548,0 +) +*23 (LogPort +port (LogicalPort +decl (Decl +n "hSel" +t "std_uLogic" +o 7 +suid 2066,0 +) +) +uid 2697,0 +) +*24 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "monitorTransaction" +t "string" +o 11 +suid 2071,0 +) +) +uid 2934,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 333,0 +optionalChildren [ +*25 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *26 (MRCItem +litem &1 +pos 11 +dimension 20 +) +uid 254,0 +optionalChildren [ +*27 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 257,0 +) +*28 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 259,0 +) +*29 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 261,0 +) +*30 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 2525,0 +) +*31 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 2527,0 +) +*32 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 2529,0 +) +*33 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 2531,0 +) +*34 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 2539,0 +) +*35 (MRCItem +litem &19 +pos 5 +dimension 20 +uid 2543,0 +) +*36 (MRCItem +litem &20 +pos 6 +dimension 20 +uid 2545,0 +) +*37 (MRCItem +litem &21 +pos 7 +dimension 20 +uid 2547,0 +) +*38 (MRCItem +litem &22 +pos 8 +dimension 20 +uid 2549,0 +) +*39 (MRCItem +litem &23 +pos 9 +dimension 20 +uid 2698,0 +) +*40 (MRCItem +litem &24 +pos 10 +dimension 20 +uid 2935,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 255,0 +optionalChildren [ +*41 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 263,0 +) +*42 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 267,0 +) +*43 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 269,0 +) +*44 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 271,0 +) +*45 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 273,0 +) +*46 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 275,0 +) +*47 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 277,0 +) +*48 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 279,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 253,0 +vaOverrides [ +] +) +] +) +uid 319,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *49 (LEmptyRow +) +uid 335,0 +optionalChildren [ +*50 (RefLabelRowHdr +) +*51 (TitleRowHdr +) +*52 (FilterRowHdr +) +*53 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*54 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*55 (GroupColHdr +tm "GroupColHdrMgr" +) +*56 (NameColHdr +tm "GenericNameColHdrMgr" +) +*57 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*58 (InitColHdr +tm "GenericValueColHdrMgr" +) +*59 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*60 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 336,0 +optionalChildren [ +*61 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *62 (MRCItem +litem &49 +pos 0 +dimension 20 +) +uid 293,0 +optionalChildren [ +*63 (MRCItem +litem &50 +pos 0 +dimension 20 +uid 296,0 +) +*64 (MRCItem +litem &51 +pos 1 +dimension 23 +uid 298,0 +) +*65 (MRCItem +litem &52 +pos 2 +hidden 1 +dimension 20 +uid 300,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 294,0 +optionalChildren [ +*66 (MRCItem +litem &53 +pos 0 +dimension 20 +uid 302,0 +) +*67 (MRCItem +litem &55 +pos 1 +dimension 50 +uid 306,0 +) +*68 (MRCItem +litem &56 +pos 2 +dimension 199 +uid 308,0 +) +*69 (MRCItem +litem &57 +pos 3 +dimension 100 +uid 310,0 +) +*70 (MRCItem +litem &58 +pos 4 +dimension 50 +uid 312,0 +) +*71 (MRCItem +litem &59 +pos 5 +dimension 50 +uid 314,0 +) +*72 (MRCItem +litem &60 +pos 6 +dimension 309 +uid 316,0 +) +] +) +fixedCol 3 +fixedRow 2 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+(vvPair +variable "d" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds\\ahb@monitor" +) +(vvPair +variable "d_logical" +value "D:\\Labs\\SEm_labs\\..\\Libs\\AhbLiteComponents_test\\hds\\ahbMonitor" +) +(vvPair +variable "date" +value "15.06.2015" +) +(vvPair +variable "day" +value "lun." +) +(vvPair +variable "day_long" +value "lundi" +) +(vvPair +variable "dd" +value "15" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "ahbMonitor" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE3673" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "AhbLiteComponents_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "U:/ELN_Board/Synthesis" +) +(vvPair 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+END SoC_ebs3 ; + + + + + +-- VHDL Entity Board.DFF.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:05 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY DFF IS + PORT( + CLK : IN std_uLogic; + CLR : IN std_uLogic; + D : IN std_uLogic; + Q : OUT std_uLogic + ); + +-- Declarations + +END DFF ; + + + + + +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Board.inverterIn.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY inverterIn IS + PORT( + in1 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END inverterIn ; + + + + + +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- VHDL Entity SystemOnChip.beamerSoc.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY beamerSoc IS + GENERIC( + ioNb : positive := 8; + testOutBitNb : positive := 16; + patternAddressBitNb : positive := 9 + ); + PORT( + TxD : OUT std_ulogic; + RxD : IN std_ulogic; + outX : OUT std_ulogic; + outY : OUT std_ulogic; + selSinCos : IN std_ulogic; + reset : IN std_ulogic; + clock : IN std_ulogic; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + testOut : OUT std_ulogic_vector (1 TO testOutBitNb) + ); + +-- Declarations + +END beamerSoc ; + + + + + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + +PACKAGE ahbLite IS + ------------------------------------------------------------------------------ + -- bus components sizes + constant ahbAddressBitNb : positive := 16; + constant ahbDataBitNb : positive := 16; + constant ahbSlaveNb : positive := 16; + + constant ahbTransBitNb : positive := 2; + constant ahbSizeBitNb : positive := 1; + constant ahbBurstBitNb : positive := 3; + constant ahbProtBitNb : positive := 4; + + ------------------------------------------------------------------------------ + -- bus data vector type + subtype ahbDataType is std_logic_vector(ahbDataBitNb-1 downto 0); + type ahbDataVector is array(1 to ahbSlaveNb) of ahbDataType; + + ------------------------------------------------------------------------------ + -- address decoder + type ahbMemoryLocationType is + record + baseAddress: natural; + addressMask: natural; + end record; + type ahbMemoryLocationVector is array(1 to ahbSlaveNb) of ahbMemoryLocationType; + + ------------------------------------------------------------------------------ + -- bus signals + subtype transferType is std_ulogic_vector(ahbTransBitNb-1 downto 0); + constant transIdle : transferType := "00"; + constant transBusy : transferType := "01"; + constant transNonSeq: transferType := "10"; + constant transSeq : transferType := "11"; + + subtype transferSizeType is std_ulogic_vector(ahbSizeBitNb-1 downto 0); + constant size8 : transferSizeType := "0"; + constant size16 : transferSizeType := "1"; + + subtype burstType is std_ulogic_vector(ahbBurstBitNb-1 downto 0); + constant burstSingle : burstType := "000"; + constant burstIncr : burstType := "001"; + constant burstWrap4 : burstType := "010"; + constant burstIncr4 : burstType := "011"; + constant burstWrap8 : burstType := "100"; + constant burstIncr8 : burstType := "101"; + constant burstWrap16 : burstType := "110"; + constant burstIncr16 : burstType := "111"; + + subtype protectionType is std_ulogic_vector(ahbProtBitNb-1 downto 0); + constant protDefault : protectionType := "0011"; + + ------------------------------------------------------------------------------ + -- log2 + function addressBitNb (addressNb : natural) return natural; + +END ahbLite; + + + + +PACKAGE BODY ahbLite IS + + function addressBitNb (addressNb : natural) return natural is + variable powerOfTwo, bitNb : natural; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo <= addressNb loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end addressBitNb; + +END ahbLite; + + + + +-- VHDL Entity SystemOnChip.ahbBeamer.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:22 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbBeamer IS + GENERIC( + patternAddressBitNb : positive := 9; + testOutBitNb : positive := 16 + ); + PORT( + outX : OUT std_ulogic; + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + outY : OUT std_ulogic; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + selSinCos : IN std_ulogic; + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic; + hSel : IN std_ulogic; + hReady : OUT std_ulogic; + hResp : OUT std_ulogic; + hClk : IN std_ulogic; + hReset_n : IN std_ulogic + ); + +-- Declarations + +END ahbBeamer ; + + + + + +-- VHDL Entity SystemOnChip.ahbBeamerOperator.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:21 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ahbBeamerOperator IS + GENERIC( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16 + ); + PORT( + outX : OUT std_ulogic; + run : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + outY : OUT std_ulogic; + selSinCos : IN std_ulogic; + interpolateLin : IN std_ulogic; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + memX : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + newPolynom : OUT std_ulogic + ); + +-- Declarations + +END ahbBeamerOperator ; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:20 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCoefficients IS + GENERIC( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + +-- Declarations + +END interpolatorCoefficients ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCoefficients IS +BEGIN + + calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4) + begin + if interpolateLinear = '1' then + a <= (others => '0'); + b <= (others => '0'); + c <= resize(2*sample3, c'length) + - resize(2*sample2, c'length); + d <= resize( sample2, d'length); + else + a <= resize( sample4, a'length) + - resize(3*sample3, a'length) + + resize(3*sample2, a'length) + - resize( sample1, a'length); + b <= resize(2*sample1, b'length) + - resize(5*sample2, b'length) + + resize(4*sample3, b'length) + - resize( sample4, b'length); + c <= resize( sample3, c'length) + - resize( sample1, c'length); + d <= resize( sample2, d'length); + end if; + end process calcCoeffs; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity DigitalToAnalogConverter.DAC.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:06:08 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY DAC IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + serialOut : OUT std_ulogic; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END DAC ; + + + + + +ARCHITECTURE masterVersion OF DAC IS + + signal parallelIn1: unsigned(parallelIn'range); + signal integrator: unsigned(parallelIn'high+1 downto 0); + signal quantized: std_ulogic; + +BEGIN + +-- parallelIn1 <= parallelIn; + parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2); + + integrate: process(reset, clock) + begin + if reset = '1' then + integrator <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '0' then + integrator <= integrator + parallelIn1; + else + integrator <= integrator + parallelIn1 - 2**parallelIn'length; + end if; + end if; + end process integrate; + + quantized <= integrator(integrator'high); + + serialOut <= quantized; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:32 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY offsetToUnsigned IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END offsetToUnsigned ; + + + + + +ARCHITECTURE masterVersion OF offsetToUnsigned IS + +BEGIN + + unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0)); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothGen IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END sawtoothGen ; + + + + + +ARCHITECTURE masterVersion OF sawtoothGen IS + + signal counter: unsigned(sawtooth'range); + +begin + + count: process(reset, clock) + begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter + step; + end if; + end if; + end process count; + + sawtooth <= counter; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCalculatePolynom IS + GENERIC( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + restartPolynom : IN std_ulogic; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorCalculatePolynom ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS + + constant additionalBitNb: positive := 1; + constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1 + + additionalBitNb; + signal x: signed(internalsBitNb-1 downto 0); + signal u: signed(internalsBitNb-1 downto 0); + signal v: signed(internalsBitNb-1 downto 0); + signal w: signed(internalsBitNb-1 downto 0); + +BEGIN + + iterativePolynom: process(reset, clock) + begin + if reset = '1' then + x <= (others => '0'); + u <= (others => '0'); + v <= (others => '0'); + w <= (others => '0'); + sampleOut <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if restartPolynom = '1' then + x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb); + u <= resize(a, u'length) + + shift_left(resize(b, u'length), oversamplingBitNb) + + shift_left(resize(c, u'length), 2*oversamplingBitNb); + v <= resize(6*a, v'length) + + shift_left(resize(2*b, v'length), oversamplingBitNb); + w <= resize(6*a, w'length); + sampleOut <= resize(d, sampleOut'length); + else + x <= x + u; + u <= u + v; + v <= v + w; + sampleOut <= resize( + shift_right(x, 3*oversamplingBitNb+1), sampleOut'length + ); + -- limit overflow + if x(x'high downto x'high-additionalBitNb) = "01" then + sampleOut <= not shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + -- limit underflow + if x(x'high downto x'high-additionalBitNb) = "10" then + sampleOut <= shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + end if; + end if; + end if; + end process iterativePolynom; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SystemOnChip.sinCosTable.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sinCosTable IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0); + cosine : OUT signed (outputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sinCosTable ; + + + + + +ARCHITECTURE masterVersion OF sinCosTable IS + + signal changeSignSine : std_uLogic; + signal changeSignCosine : std_uLogic; + signal flipPhase : std_uLogic; + signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0); + signal phaseTableAddress2 : unsigned(phaseTableAddress1'range); + signal quarterSine : signed(sine'range); + signal quarterCosine : signed(cosine'range); + +BEGIN + + changeSignSine <= phase(phase'high); + changeSignCosine <= phase(phase'high) xor phase(phase'high-1); + flipPhase <= phase(phase'high-1); + + phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + checkPhase: process(flipPhase, phaseTableAddress1) + begin + if flipPhase = '0' then + phaseTableAddress2 <= phaseTableAddress1; + else + phaseTableAddress2 <= 0 - phaseTableAddress1; + end if; + end process checkPhase; + + + quarterTableSine: process(phaseTableAddress2, flipPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if flipPhase = '0' then + quarterSine <= to_signed(16#0000#, quarterSine'length); + else + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTableSine; + + + quarterTableCosine: process(phaseTableAddress2, flipPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if flipPhase = '1' then + quarterCosine <= to_signed(16#0000#, quarterSine'length); + else + quarterCosine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 7 => quarterCosine <= to_signed(16#18F9#, quarterSine'length); + when 6 => quarterCosine <= to_signed(16#30FB#, quarterSine'length); + when 5 => quarterCosine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterCosine <= to_signed(16#5A82#, quarterSine'length); + when 3 => quarterCosine <= to_signed(16#6A6D#, quarterSine'length); + when 2 => quarterCosine <= to_signed(16#7641#, quarterSine'length); + when 1 => quarterCosine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterCosine <= (others => '-'); + end case; + end process quarterTableCosine; + + + checkSignSine: process(changeSignSine, quarterSine) + begin + if changeSignSine = '0' then + sine <= quarterSine; + else + sine <= 0 - quarterSine; + end if; + end process checkSignSine; + + + checkSignCosine: process(changeSignCosine, quarterCosine) + begin + if changeSignCosine = '0' then + cosine <= quarterCosine; + else + cosine <= 0 - quarterCosine; + end if; + end process checkSignCosine; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SystemOnChip.periphSpeedController.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphSpeedController IS + GENERIC( + updatePeriodBitNb : positive := 16 + ); + PORT( + enableOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + enableIn : IN std_ulogic + ); + +-- Declarations + +END periphSpeedController ; + + + + + +ARCHITECTURE masterVersion OF periphSpeedController IS + + signal enableCounter: unsigned(updatePeriod'range); + signal endOfCount: std_uLogic; + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + enableCounter <= (others => '0'); + elsif rising_edge(clock) then + if (endOfCount = '0') and (enableIn = '1') then + enableCounter <= enableCounter - 1; + else + enableCounter <= updatePeriod; + end if; + end if; + end process count; + + testEndOfCount: process(enableCounter) + begin + if enableCounter = 0 then + endOfCount <= '1'; + else + endOfCount <= '0'; + end if; + end process testEndOfCount; + + enableOut <= endOfCount and enableIn; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:24 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorShiftRegister IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + shiftSamples : IN std_ulogic; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END interpolatorShiftRegister ; + + + + + +ARCHITECTURE masterVersion OF interpolatorShiftRegister IS + + -- signal sample4_int: signed(sampleIn'range); + -- signal sample3_int: signed(sampleIn'range); + -- signal sample2_int: signed(sampleIn'range); + -- signal sample1_int: signed(sampleIn'range); + + type samplesArray is array(3 downto 0) of signed(sampleIn'range); + signal samples: samplesArray; + +begin + + shiftThem: process(reset, clock) + begin + if reset = '1' then + samples <= (others=>(others=>'0')); + -- sample1_int <= (others => '0'); + -- sample2_int <= (others => '0'); + -- sample3_int <= (others => '0'); + -- sample4_int <= (others => '0'); + elsif rising_edge(clock) then + if shiftSamples = '1' then + -- sample1_int <= sample2_int; + -- sample2_int <= sample3_int; + -- sample3_int <= sample4_int; + -- sample4_int <= sampleIn; + samples(0) <= samples(1); + samples(1) <= samples(2); + samples(2) <= samples(3); + samples(3) <= sampleIn; + end if; + end if; + end process shiftThem; + + sample4 <= samples(3); + sample3 <= samples(2); + sample2 <= samples(1); + sample1 <= samples(0); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:28 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorTrigger IS + GENERIC( + counterBitNb : positive := 4 + ); + PORT( + triggerOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorTrigger ; + + + + + +ARCHITECTURE masterVersion OF interpolatorTrigger IS + + signal triggerCounter: unsigned(counterBitNb-1 downto 0); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + triggerCounter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + triggerCounter <= triggerCounter + 1; + end if; + end if; + end process count; + + trig: process(triggerCounter, en) + begin + if triggerCounter = 0 then + triggerOut <= en; + else + triggerOut <= '0'; + end if; + end process trig; + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SystemOnChip.ahbBeamerOperator.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:01:08 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY DigitalToAnalogConverter; +LIBRARY SplineInterpolator; +LIBRARY SystemOnChip; +LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF ahbBeamerOperator IS + + -- Architecture declarations + constant coeffBitNb : positive := signalBitNb+3+1; + constant sampleCountBitNb : positive := 8; + constant patternAddressBitNb : positive := 8; + -- sinewave generator + constant tableAddressBitNb : positive := 3; + constant phaseBitNb : positive := sampleCountBitNb + tableAddressBitNb + 2; + + -- Internal signal declarations + SIGNAL aX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL aY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL bX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL bY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL cX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL cY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL cosine : signed(signalBitNb-1 DOWNTO 0); + SIGNAL dX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL dY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL interpolateLinear : std_ulogic; + SIGNAL interpolationEn : std_ulogic; + SIGNAL interpolationEnable : std_ulogic; + SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sampleX : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL samplesX : signed(signalBitNb-1 DOWNTO 0); + SIGNAL samplesY : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sine : signed(signalBitNb-1 DOWNTO 0); + SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL unsignedX : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL unsignedY : unsigned(signalBitNb-1 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL newPolynom_internal : std_ulogic; + + + -- Component Declarations + COMPONENT DAC + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + serialOut : OUT std_ulogic ; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCalculatePolynom + GENERIC ( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + restartPolynom : IN std_ulogic ; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCoefficients + GENERIC ( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT ( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorShiftRegister + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + shiftSamples : IN std_ulogic ; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT interpolatorTrigger + GENERIC ( + counterBitNb : positive := 4 + ); + PORT ( + triggerOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT offsetToUnsigned + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT periphSpeedController + GENERIC ( + updatePeriodBitNb : positive := 16 + ); + PORT ( + enableOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + enableIn : IN std_ulogic + ); + END COMPONENT; + COMPONENT sinCosTable + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT ( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0); + cosine : OUT signed (outputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC; + FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom; + FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients; + FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister; + FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger; + FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned; + FOR ALL : periphSpeedController USE ENTITY SystemOnChip.periphSpeedController; + FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; + FOR ALL : sinCosTable USE ENTITY SystemOnChip.sinCosTable; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + samplesY <= sine when selSinCos = '1' + else signed(memY); + + -- HDL Embedded Text Block 2 eb2 + samplesX <= cosine when selSinCos = '1' + else signed(memX); + + -- HDL Embedded Text Block 4 eb4 + step <= to_unsigned(1, step'length); + + -- HDL Embedded Text Block 5 eb5 + interpolationEnable <= '1' when selSinCos = '1' + else interpolationEn; + interpolateLinear <= '0' when selSinCos = '1' + else interpolateLin; + --interpolateLinear <= interpolateLin; + + + -- Instance port mappings. + I_dacx : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => outX, + parallelIn => unsignedX, + clock => clock, + reset => reset + ); + I_dacy : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => outY, + parallelIn => unsignedY, + clock => clock, + reset => reset + ); + I_polyx : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom_internal, + d => dX, + sampleOut => sampleX, + c => cX, + b => bX, + a => aX, + en => interpolationEnable + ); + I_polyy : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom_internal, + d => dY, + sampleOut => sampleY, + c => cY, + b => bY, + a => aY, + en => interpolationEnable + ); + I_coeffx : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sampleX1, + sample2 => sampleX2, + sample3 => sampleX3, + sample4 => sampleX4, + a => aX, + b => bX, + c => cX, + d => dX, + interpolateLinear => interpolateLinear + ); + I_coeffy : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sampleY1, + sample2 => sampleY2, + sample3 => sampleY3, + sample4 => sampleY4, + a => aY, + b => bY, + c => cY, + d => dY, + interpolateLinear => interpolateLinear + ); + I_srx : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom_internal, + sampleIn => samplesX, + sample1 => sampleX1, + sample2 => sampleX2, + sample3 => sampleX3, + sample4 => sampleX4 + ); + I_sry : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom_internal, + sampleIn => samplesY, + sample1 => sampleY1, + sample2 => sampleY2, + sample3 => sampleY3, + sample4 => sampleY4 + ); + I_trig : interpolatorTrigger + GENERIC MAP ( + counterBitNb => sampleCountBitNb + ) + PORT MAP ( + triggerOut => newPolynom_internal, + clock => clock, + reset => reset, + en => interpolationEnable + ); + I_offsx : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => unsignedX, + signedIn => sampleX + ); + I_offsy : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => unsignedY, + signedIn => sampleY + ); + I_speed : periphSpeedController + GENERIC MAP ( + updatePeriodBitNb => updatePeriodBitNb + ) + PORT MAP ( + enableOut => interpolationEn, + clock => clock, + reset => reset, + updatePeriod => updatePeriod, + enableIn => run + ); + I_sin : sinCosTable + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb, + tableAddressBitNb => tableAddressBitNb + ) + PORT MAP ( + sine => sine, + phase => phase, + cosine => cosine + ); + I_phase : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => phase, + clock => clock, + reset => reset, + step => step, + en => interpolationEnable + ); + + -- Implicit buffered output assignments + newPolynom <= newPolynom_internal; + +END struct; + + + + +-- VHDL Entity SystemOnChip.ahbBeamerRegisters.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:21 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbBeamerRegisters IS + GENERIC( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16; + patternAddressBitNb : positive := 8; + testOutBitNb : positive := 16 + ); + PORT( + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + memX : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + run : OUT std_ulogic; + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + interpolateLin : OUT std_ulogic; + newPolynom : IN std_ulogic; + hClk : IN std_ulogic; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + hReset_n : IN std_ulogic; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic; + hSel : IN std_ulogic; + hReady : OUT std_ulogic; + hResp : OUT std_ulogic + ); + +-- Declarations + +END ahbBeamerRegisters ; + + + + + +-- VHDL Entity SystemOnChip.blockRAMAddressCounter.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY blockRAMAddressCounter IS + GENERIC( + addressBitNb : positive := 8 + ); + PORT( + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + updateMem : IN std_ulogic; + addr : OUT unsigned (addressBitNb-1 DOWNTO 0); + patternSize : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END blockRAMAddressCounter ; + + + + + +ARCHITECTURE masterVersion OF blockRAMAddressCounter IS + + signal updateMemDelayed : std_ulogic; + signal updateMemChanging : std_ulogic; + signal addressInt : unsigned(addr'range); + +BEGIN + + delay: process(reset, clock) + begin + if reset = '1' then + updateMemDelayed <= '0'; + elsif rising_edge(clock) then + updateMemDelayed <= updateMem; + end if; + end process delay; + + updateMemChanging <= '1' when (updateMem /= updateMemDelayed) + else '0'; + + count: process(reset, clock) + begin + if reset = '1' then + addressInt <= (others => '0'); + elsif rising_edge(clock) then + if updateMemChanging = '1' then + addressInt <= (others => '0'); + elsif en = '1' then + if updateMem = '1' then + addressInt <= addressInt + 1; + else + if addressInt < patternSize - 1 then + addressInt <= addressInt + 1; + else + addressInt <= (others => '0'); + end if; + end if; + end if; + end if; + end process count; + + addr <= addressInt; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SystemOnChip.periphControlReg.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphControlReg IS + GENERIC( + dataBitNb : positive := 16; + patternSizeBitNb : positive := 8 + ); + PORT( + run : OUT std_ulogic; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + updatePattern : OUT std_ulogic; + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + write : IN std_ulogic; + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + interpolateLinear : OUT std_ulogic; + patternSize : OUT unsigned (patternSizeBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END periphControlReg ; + + + + + +ARCHITECTURE masterVersion OF periphControlReg IS + + constant runId : natural := 0; + constant updatePatternId : natural := 1; + constant interpolateLinearId : natural := 2; + constant patternSizeHighId : natural := 15; + + signal runInt : std_ulogic; + signal updatePatternInt : std_ulogic; + signal interpolateLinearInt : std_ulogic; + signal patternSizeInt : std_ulogic_vector(patternSize'range); + + signal dataOutReg : std_ulogic_vector(dataOut'range); + +BEGIN + + store: process(reset, clock) + begin + if reset = '1' then + runInt <= '0'; + updatePatternInt <= '0'; + interpolateLinearInt <= '0'; + patternSizeInt <= (others => '0'); + elsif rising_edge(clock) then + if (en = '1') and (write = '1') then + runInt <= dataIn(runId); + updatePatternInt <= dataIn(updatePatternId); + interpolateLinearInt <= dataIn(interpolateLinearId); + patternSizeInt <= + dataIn(patternSizeHighId downto patternSizeHighId-patternSize'length+1); + end if; + end if; + end process store; + + run <= runInt; + updatePattern <= updatePatternInt; + interpolateLinear <= interpolateLinearInt; + patternSize <= unsigned(patternSizeInt); + + process(runInt, updatePatternInt, interpolateLinearInt, patternSizeInt) + begin + dataOutReg <= (others => '-'); + dataOutReg(runId) <= runInt; + dataOutReg(updatePatternId) <= updatePatternInt; + dataOutReg(interpolateLinearId) <= interpolateLinearInt; + dataOutReg(patternSizeHighId downto patternSizeHighId-patternSize'length+1) + <= patternSizeInt; + end process; + + dataOut <= std_logic_vector(dataOutReg) when en = '1' + else (others => 'Z'); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SystemOnChip.blockRAMControl.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY blockRAMControl IS + PORT( + memWr : OUT std_ulogic; + sel : IN std_ulogic; + memEn : OUT std_ulogic; + update : IN std_ulogic; + wr : IN std_ulogic; + cntIncr : OUT std_ulogic; + newSample : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END blockRAMControl ; + + + + + +ARCHITECTURE masterVersion OF blockRAMControl IS + + signal writeDelayed: std_ulogic; + signal writePulse: std_ulogic; + signal memWr1: std_ulogic; + +BEGIN + + delayWrPulse: process(reset, clock) + begin + if reset = '1' then + writeDelayed <= '0'; + elsif rising_edge(clock) then + writeDelayed <= wr; + end if; + end process delayWrPulse; + + writePulse <= '1' when (wr='1') and (writeDelayed='0') + else '0'; + + cntIncr <= '1' when ( (update = '0') and (newSample = '1') ) + or ( (update = '1') and (writePulse = '1') and (sel = '1') ) + else '0'; + + memWr1 <= '1' when (update = '1') and (writePulse = '1') and (sel = '1') + else '0'; + +-- delayMemWrPulse: process(reset, clock) +-- begin +-- if reset = '1' then +-- memWr <= '0'; +-- elsif rising_edge(clock) then +-- memWr <= memWr1; +-- end if; +-- end process delayMemWrPulse; + memWr <= memWr1; + + memEn <= '1' when (sel = '1') or (update = '0') + else '0'; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SystemOnChip.periphAddressDecoder.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphAddressDecoder IS + GENERIC( + addressBitNb : positive := 24 + ); + PORT( + selControl : OUT std_ulogic; + addr : IN unsigned (addressBitNb-1 DOWNTO 0); + selSpeed : OUT std_ulogic; + selX : OUT std_ulogic; + selY : OUT std_ulogic; + selZ : OUT std_ulogic + ); + +-- Declarations + +END periphAddressDecoder ; + + + + + +ARCHITECTURE masterVersion OF periphAddressDecoder IS +BEGIN + + decode: process(addr) + begin + selControl <= '0'; + selSpeed <= '0'; + selX <= '0'; + selY <= '0'; + selZ <= '0'; + case to_integer(addr(3 downto 0)) is + when 16#00# => selControl <= '1'; + when 16#01# => selSpeed <= '1'; + when 16#02# => selX <= '1'; + when 16#03# => selY <= '1'; + when 16#04# => selZ <= '1'; + when others => null; + end case; + end process decode; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SystemOnChip.blockRAM.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY blockRAM IS + GENERIC( + addressBitNb : positive := 8; + dataBitNb : positive := 16; + initFileSpec : string := "ramInit.txt" + ); + PORT( + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + write : IN std_ulogic; + addr : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END blockRAM ; + + + + + +USE std.textio.all; + +ARCHITECTURE Spartan3E OF blockRAM IS + + subtype registerType is std_ulogic_vector(dataBitNb-1 downto 0); + type memoryType is array (0 to 2**addressBitNb-1) of registerType; + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFileSpec : in string) return memoryType is + FILE ramContentFile : text open read_mode is ramContentFileSpec; + variable ramContentFileLine : line; + variable ramContent : memoryType; + variable ramCurrentWord : bit_vector(registerType'range); + variable index : natural := 0; --241; + begin + for index in ramContent'range loop +-- while not endfile(ramContentFile) loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramCurrentWord); + ramContent(index) := std_ulogic_vector(to_stdlogicvector(ramCurrentWord)); +-- index := index + 1; + end loop; + return ramContent; + end function; + + shared variable memoryArray: memoryType := ReadRamContentFromFile(initFileSpec); + +BEGIN + + portA: process(clock) + begin + if rising_edge(clock) then + if (en = '1') then + if (write = '1') then + memoryArray(to_integer(addr)) := dataIn; + dataOut <= dataIn; + else + dataOut <= memoryArray(to_integer(addr)); + end if; + end if; + end if; + end process portA; + +END ARCHITECTURE Spartan3E; + + + + +-- VHDL Entity SystemOnChip.periphSpeedReg.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphSpeedReg IS + GENERIC( + dataBitNb : positive := 16; + updatePeriodBitNb : positive := 16 + ); + PORT( + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + write : IN std_ulogic + ); + +-- Declarations + +END periphSpeedReg ; + + + + + +ARCHITECTURE masterVersion OF periphSpeedReg IS + + signal updatePeriodInt: unsigned(updatePeriod'range); + +BEGIN + + store: process(reset, clock) + begin + if reset = '1' then + updatePeriodInt <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if write = '1' then + updatePeriodInt <= unsigned(dataIn(updatePeriodInt'range)); + end if; + end if; + end if; + end process store; + + updatePeriod <= updatePeriodInt; + + writeBack: process(en, updatePeriodInt) + begin + if en = '1' then + dataOut <= (others => '-'); + dataOut(updatePeriodInt'range) <= std_logic_vector(updatePeriodInt); + else + dataOut <= (others => 'Z'); + end if; + end process writeBack; + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SystemOnChip.ahbBeamerRegisters.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:01:22 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY SystemOnChip; + +ARCHITECTURE struct OF ahbBeamerRegisters IS + + -- Architecture declarations + constant addressBitNb: positive := hAddr'length; + constant dataBitNb : positive := hWData'length; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL reset : std_ulogic; + SIGNAL addr : unsigned(addressBitNb-1 DOWNTO 0); + SIGNAL addrX : unsigned(patternAddressBitNb-1 DOWNTO 0); + SIGNAL addrY : unsigned(patternAddressBitNb-1 DOWNTO 0); + SIGNAL cntIncrX : std_ulogic; + SIGNAL cntIncrY : std_ulogic; + SIGNAL dataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0); + SIGNAL dataOut : std_logic_vector(dataBitNb-1 DOWNTO 0); + SIGNAL memEnX : std_ulogic; + SIGNAL memEnY : std_ulogic; + SIGNAL memWrX : std_ulogic; + SIGNAL memWrY : std_ulogic; + SIGNAL patternSize : unsigned(patternAddressBitNb-1 DOWNTO 0); + SIGNAL selControl : std_ulogic; + SIGNAL selSpeed : std_ulogic; + SIGNAL selX : std_ulogic; + SIGNAL selY : std_ulogic; + SIGNAL updatePattern : std_ulogic; + SIGNAL write : std_ulogic; + SIGNAL memDataIn : std_ulogic_vector(signalBitNb-1 DOWNTO 0); + SIGNAL run_int : std_ulogic; + SIGNAL interpolateLin_int : std_ulogic; + + + -- Component Declarations + COMPONENT blockRAM + GENERIC ( + addressBitNb : positive := 8; + dataBitNb : positive := 16; + initFileSpec : string := "ramInit.txt" + ); + PORT ( + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + write : IN std_ulogic ; + addr : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT blockRAMAddressCounter + GENERIC ( + addressBitNb : positive := 8 + ); + PORT ( + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + updateMem : IN std_ulogic ; + addr : OUT unsigned (addressBitNb-1 DOWNTO 0); + patternSize : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT blockRAMControl + PORT ( + memWr : OUT std_ulogic ; + sel : IN std_ulogic ; + memEn : OUT std_ulogic ; + update : IN std_ulogic ; + wr : IN std_ulogic ; + cntIncr : OUT std_ulogic ; + newSample : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT periphAddressDecoder + GENERIC ( + addressBitNb : positive := 24 + ); + PORT ( + selControl : OUT std_ulogic ; + addr : IN unsigned (addressBitNb-1 DOWNTO 0); + selSpeed : OUT std_ulogic ; + selX : OUT std_ulogic ; + selY : OUT std_ulogic ; + selZ : OUT std_ulogic + ); + END COMPONENT; + COMPONENT periphControlReg + GENERIC ( + dataBitNb : positive := 16; + patternSizeBitNb : positive := 8 + ); + PORT ( + run : OUT std_ulogic ; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + updatePattern : OUT std_ulogic ; + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + write : IN std_ulogic ; + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + interpolateLinear : OUT std_ulogic ; + patternSize : OUT unsigned (patternSizeBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT periphSpeedReg + GENERIC ( + dataBitNb : positive := 16; + updatePeriodBitNb : positive := 16 + ); + PORT ( + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + write : IN std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : blockRAM USE ENTITY SystemOnChip.blockRAM; + FOR ALL : blockRAMAddressCounter USE ENTITY SystemOnChip.blockRAMAddressCounter; + FOR ALL : blockRAMControl USE ENTITY SystemOnChip.blockRAMControl; + FOR ALL : periphAddressDecoder USE ENTITY SystemOnChip.periphAddressDecoder; + FOR ALL : periphControlReg USE ENTITY SystemOnChip.periphControlReg; + FOR ALL : periphSpeedReg USE ENTITY SystemOnChip.periphSpeedReg; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 3 eb3 + testout( 1) <= run_int; run <= run_int; + testout( 2) <= updatePattern; + testout( 3) <= interpolateLin_int; interpolateLin <= interpolateLin_int; + testout( 4) <= newPolynom; + testout( 5) <= newPolynom; + testout( 6) <= '0'; + testout( 7) <= '0'; + testout( 8) <= selControl; + testout( 9) <= selSpeed; + testout(10) <= selX; + testout(11) <= selY; + testout(12) <= '0'; + testout(13) <= addr(0); + testout(14) <= addr(1); + testout(15) <= dataIn(0); + testout(16) <= dataIn(1); + + -- HDL Embedded Text Block 8 eb8 + storeControls: process(reset, clock) + begin + if reset = '1' then + addr <= (others => '0'); + write <= '0'; + elsif rising_edge(clock) then + write <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addr <= hAddr(addr'range); + write <= hWrite; + end if; + end if; + end process storeControls; + + dataIn <= hWData; + + -- HDL Embedded Text Block 9 eb9 + memDataIn <= dataIn(memDataIn'range); + + -- HDL Embedded Text Block 10 eb10 + hRData <= std_ulogic_vector(dataOut); + + hReady <= '1'; -- no wait state + hResp <= '0'; -- data OK + + -- HDL Embedded Text Block 11 eb11 + clock<= hClk; + + reset <= not hReset_n; + + + -- Instance port mappings. + I_ramx : blockRAM + GENERIC MAP ( + addressBitNb => patternAddressBitNb, + dataBitNb => signalBitNb, + initFileSpec => "$SIMULATION_DIR/ramYInit.txt" + ) + PORT MAP ( + dataIn => memDataIn, + dataOut => memX, + en => memEnX, + clock => clock, + reset => reset, + write => memWrX, + addr => addrX + ); + I_ramy : blockRAM + GENERIC MAP ( + addressBitNb => patternAddressBitNb, + dataBitNb => signalBitNb, + initFileSpec => "$SIMULATION_DIR/ramXInit.txt" + ) + PORT MAP ( + dataIn => memDataIn, + dataOut => memY, + en => memEnY, + clock => clock, + reset => reset, + write => memWrY, + addr => addrY + ); + I_addrx : blockRAMAddressCounter + GENERIC MAP ( + addressBitNb => patternAddressBitNb + ) + PORT MAP ( + en => cntIncrX, + clock => clock, + reset => reset, + updateMem => updatePattern, + addr => addrX, + patternSize => patternSize + ); + I_addry : blockRAMAddressCounter + GENERIC MAP ( + addressBitNb => patternAddressBitNb + ) + PORT MAP ( + en => cntIncrY, + clock => clock, + reset => reset, + updateMem => updatePattern, + addr => addrY, + patternSize => patternSize + ); + I_ctlx : blockRAMControl + PORT MAP ( + memWr => memWrX, + sel => selX, + memEn => memEnX, + update => updatePattern, + wr => write, + cntIncr => cntIncrX, + newSample => newPolynom, + clock => clock, + reset => reset + ); + I_ctly : blockRAMControl + PORT MAP ( + memWr => memWrY, + sel => selY, + memEn => memEnY, + update => updatePattern, + wr => write, + cntIncr => cntIncrY, + newSample => newPolynom, + clock => clock, + reset => reset + ); + I_decoder : periphAddressDecoder + GENERIC MAP ( + addressBitNb => addressBitNb + ) + PORT MAP ( + selControl => selControl, + addr => addr, + selSpeed => selSpeed, + selX => selX, + selY => selY, + selZ => OPEN + ); + I_ctl : periphControlReg + GENERIC MAP ( + dataBitNb => dataBitNb, + patternSizeBitNb => patternAddressBitNb + ) + PORT MAP ( + run => run_int, + dataIn => dataIn, + updatePattern => updatePattern, + dataOut => dataOut, + write => write, + en => selControl, + clock => clock, + reset => reset, + interpolateLinear => interpolateLin_int, + patternSize => patternSize + ); + I_speed : periphSpeedReg + GENERIC MAP ( + dataBitNb => dataBitNb, + updatePeriodBitNb => updatePeriodBitNb + ) + PORT MAP ( + updatePeriod => updatePeriod, + dataIn => dataIn, + dataOut => dataOut, + en => selSpeed, + clock => clock, + reset => reset, + write => write + ); + +END struct; + + + + +-- +-- VHDL Architecture SystemOnChip.ahbBeamer.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:00:20 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +LIBRARY SystemOnChip; + +ARCHITECTURE struct OF ahbBeamer IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant updatePeriodBitNb : positive := 16; + + -- Internal signal declarations + SIGNAL reset : std_ulogic; + SIGNAL run : std_ulogic; + SIGNAL interpolateLin : std_ulogic; + SIGNAL updatePeriod : unsigned(updatePeriodBitNb-1 DOWNTO 0); + SIGNAL memX : std_ulogic_vector(signalBitNb-1 DOWNTO 0); + SIGNAL memY : std_ulogic_vector(signalBitNb-1 DOWNTO 0); + SIGNAL newPolynom : std_ulogic; + + + -- Component Declarations + COMPONENT ahbBeamerOperator + GENERIC ( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16 + ); + PORT ( + outX : OUT std_ulogic ; + run : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + outY : OUT std_ulogic ; + selSinCos : IN std_ulogic ; + interpolateLin : IN std_ulogic ; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + memX : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + newPolynom : OUT std_ulogic + ); + END COMPONENT; + COMPONENT ahbBeamerRegisters + GENERIC ( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16; + patternAddressBitNb : positive := 8; + testOutBitNb : positive := 16 + ); + PORT ( + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + memX : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + run : OUT std_ulogic ; + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + interpolateLin : OUT std_ulogic ; + newPolynom : IN std_ulogic ; + hClk : IN std_ulogic ; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + hReset_n : IN std_ulogic ; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic ; + hSel : IN std_ulogic ; + hReady : OUT std_ulogic ; + hResp : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ahbBeamerOperator USE ENTITY SystemOnChip.ahbBeamerOperator; + FOR ALL : ahbBeamerRegisters USE ENTITY SystemOnChip.ahbBeamerRegisters; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + --process + --begin + -- newPolynom <= '0'; + -- for index in 1 to 2**4-1 loop + -- wait until rising_edge(clock); + -- end loop; + -- newPolynom <= '1'; + -- wait until rising_edge(clock); + --end process; + + -- HDL Embedded Text Block 3 eb3 + reset <= not hReset_n; + + + -- Instance port mappings. + I_op : ahbBeamerOperator + GENERIC MAP ( + updatePeriodBitNb => updatePeriodBitNb, + signalBitNb => signalBitNb + ) + PORT MAP ( + outX => outX, + run => run, + clock => hClk, + reset => reset, + outY => outY, + selSinCos => selSinCos, + interpolateLin => interpolateLin, + updatePeriod => updatePeriod, + memX => memX, + memY => memY, + newPolynom => newPolynom + ); + I_regs : ahbBeamerRegisters + GENERIC MAP ( + updatePeriodBitNb => updatePeriodBitNb, + signalBitNb => signalBitNb, + patternAddressBitNb => patternAddressBitNb, + testOutBitNb => testOutBitNb + ) + PORT MAP ( + testOut => testOut, + memX => memX, + memY => memY, + run => run, + updatePeriod => updatePeriod, + interpolateLin => interpolateLin, + newPolynom => newPolynom, + hClk => hClk, + hRData => hRData, + hAddr => hAddr, + hReset_n => hReset_n, + hWData => hWData, + hTrans => hTrans, + hWrite => hWrite, + hSel => hSel, + hReady => hReady, + hResp => hResp + ); + +END struct; + + + + +-- VHDL Entity AhbLite.ahbMuxConnector.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbMuxConnector IS + GENERIC( + index : positive := 1 + ); + PORT( + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic; + hResp : IN std_uLogic; + hSelV : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRDataV : OUT ahbDataVector; + hReadyV : OUT std_logic_vector (1 TO ahbSlaveNb); + hRespV : OUT std_logic_vector (1 TO ahbSlaveNb); + hSel : OUT std_uLogic + ); + +-- Declarations + +END ahbMuxConnector ; + + + + + +ARCHITECTURE RTL OF ahbMuxConnector IS +BEGIN + + hSel <= hSelV(index); + + hRDataV(index) <= std_logic_vector(hRData); + hReadyV(index) <= hReady; + hRespV(index) <= hResp; + + hRDataV <= (others => (others => 'Z')); + hReadyV <= (others => 'Z'); + hRespV <= (others => 'Z'); + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity AhbLite.ahbDecoder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbDecoder IS + GENERIC( + ahbMemoryLocation : ahbMemoryLocationVector + ); + PORT( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hSel : OUT std_ulogic_vector (1 TO ahbSlaveNb) + ); + +-- Declarations + +END ahbDecoder ; + + + + + +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ARCHITECTURE RTL OF ahbDecoder IS +BEGIN + + decodeAddress: process(hAddr) + variable mask: unsigned(hAddr'range); + begin + hSel <= (others => '0'); + for index in hSel'range loop + mask := to_unsigned(ahbMemoryLocation(index).addressMask, mask'length); + if (hAddr and mask) = ahbMemoryLocation(index).baseAddress then + hSel(index) <= '1'; + end if; + end loop; + end process decodeAddress; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity AhbLiteComponents.ahbGpio.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:43:49 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbGpio IS + GENERIC( + ioNb : positive := 8 + ); + PORT( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic; + hReset_n : IN std_uLogic; + hSel : IN std_uLogic; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic; + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) + ); + +-- Declarations + +END ahbGpio ; + + + + + +--============================================================================== +-- +-- AHB general purpose input/outputs +-- +-- Provides "ioNb" input/output signals . +-- +-------------------------------------------------------------------------------- +-- +-- Write registers +-- +-- 00, data register receives the values to drive the output lines. +-- 01, output enable register defines the signal direction: +-- when '1', the direction is "out". +-- +-------------------------------------------------------------------------------- +-- +-- Read registers +-- 00, data register provides the values detected on the lines. +-- + +ARCHITECTURE masterVersion OF ahbGpio IS + + signal reset, clock: std_ulogic; + -- register definitions + constant dataRegisterId: natural := 0; + constant outputEnableRegisterId: natural := 1; + + signal addressReg: unsigned(addressBitNb(outputEnableRegisterId)-1 downto 0); + signal writeReg: std_ulogic; + -- written registers + subtype registerType is unsigned(ioNb-1 downto 0); + signal dataOutRegister, outputEnableRegister: registerType; + -- read registers + signal dataInRegister : registerType; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= not hReset_n; + clock <= hClk; + + --============================================================================ + -- address and controls + storeControls: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + writeReg <= '0'; + elsif rising_edge(clock) then + writeReg <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addressReg <= hAddr(addressReg'range); + writeReg <= hWrite; + end if; + end if; + end process storeControls; + + --============================================================================ + -- registers + storeWriteRegisters: process(reset, clock) + begin + if reset = '1' then + dataOutRegister <= (others => '0'); + outputEnableRegister <= (others => '0'); + elsif rising_edge(clock) then + if writeReg = '1' then + case to_integer(addressReg) is + when dataRegisterId => dataOutRegister <= unsigned(hWData(dataOutRegister'range)); + when outputEnableRegisterId => outputEnableRegister <= unsigned(hWData(outputEnableRegister'range)); + when others => null; + end case; + end if; + end if; + end process storeWriteRegisters; + + ioOut <= std_ulogic_vector(dataOutRegister); + ioEn <= std_ulogic_vector(outputEnableRegister); + + --============================================================================ + -- data readback + dataInRegister <= unsigned(ioIn); + + hRData <= std_ulogic_vector(resize(dataInRegister, hRData'length)); + hReady <= '1'; -- no wait state + hResp <= '0'; -- data OK + + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity AhbLite.ahbMasterInterface.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbMasterInterface IS + PORT( + clock : IN std_ulogic; + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic; + hResp : IN std_uLogic; + pAddress : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + pDataOut : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + pReadStrobe : IN std_uLogic; + pWriteStrobe : IN std_uLogic; + reset : IN std_ulogic; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hBurst : OUT std_ulogic_vector (ahbBurstBitNb-1 DOWNTO 0); + hClk : OUT std_uLogic; + hMastLock : OUT std_uLogic; + hProt : OUT std_ulogic_vector (ahbProtBitNb-1 DOWNTO 0); + hReset_n : OUT std_uLogic; + hSize : OUT std_ulogic_vector (ahbSizeBitNb-1 DOWNTO 0); + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic; + pDataIn : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END ahbMasterInterface ; + + + + + +ARCHITECTURE RTL OF ahbMasterInterface IS + + signal addressReg: unsigned(pAddress'range); + signal newAddress: std_ulogic; + signal writeReg: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + hReset_n <= not reset; + hClk <= clock; + + ------------------------------------------------------------------------------ + -- address and controls + newAddress <= pReadStrobe or pWriteStrobe; + + storeAddress: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + elsif rising_edge(clock) then + if newAddress = '1' then + addressReg <= pAddress; + end if; + end if; + end process storeAddress; + + hAddr <= pAddress when newAddress = '1' + else addressReg; + + storeWrite: process(reset, clock) + begin + if reset = '1' then + writeReg <= '0'; + elsif rising_edge(clock) then + if newAddress = '1' then + writeReg <= pWriteStrobe; + end if; + end if; + end process storeWrite; + + hWrite <= pWriteStrobe when newAddress = '1' + else writeReg; + + hTrans <= transNonSeq when newAddress = '1' + else transIdle; + + hSize <= size16; + hBurst <= burstSingle; + hProt <= protDefault; + hMastLock <= '0'; + + ------------------------------------------------------------------------------ + -- data out + delayData: process(reset, clock) + begin + if reset = '1' then + hWData <= (others => '0'); + elsif rising_edge(clock) then + if pWriteStrobe = '1' then + hWData <= pDataOut; + end if; + end if; + end process delayData; + + ------------------------------------------------------------------------------ + -- data in + pDataIn <= hRData; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity AhbLite.ahbMultiplexor.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbMultiplexor IS + PORT( + hRDataV : IN ahbDataVector; + hReadyV : IN std_logic_vector (1 TO ahbSlaveNb); + hRespV : IN std_logic_vector (1 TO ahbSlaveNb); + hSel : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic + ); + +-- Declarations + +END ahbMultiplexor ; + + + + + +ARCHITECTURE RTL OF ahbMultiplexor IS +BEGIN + + multiplexData: process(hSel, hRDataV, hReadyV, hRespV) + begin + hRData <= (others => '0'); + hReady <= '1'; + hResp <= '0'; + for index in hSel'range loop + if hSel(index) = '1' then + hRData <= std_ulogic_vector(hRDataV(index)); + hReady <= hReadyV(index); + hResp <= hRespV(index); + end if; + end loop; + end process multiplexData; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity SystemOnChip.programRom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY programRom IS + GENERIC( + addressBitNb : positive := 8; + dataBitNb : positive := 8 + ); + PORT( + address : IN unsigned (addressBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + en : IN std_ulogic; + reset : IN std_ulogic; + dataOut : OUT std_ulogic_vector ( dataBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END programRom ; + + + + + +ARCHITECTURE mapped OF programRom IS + + subtype opCodeType is std_ulogic_vector(5 downto 0); + constant opLoadC : opCodeType := "000000"; + constant opLoadR : opCodeType := "000001"; + constant opInputC : opCodeType := "000100"; + constant opInputR : opCodeType := "000101"; + constant opFetchC : opCodeType := "000110"; + constant opFetchR : opCodeType := "000111"; + constant opAndC : opCodeType := "001010"; + constant opAndR : opCodeType := "001011"; + constant opOrC : opCodeType := "001100"; + constant opOrR : opCodeType := "001101"; + constant opXorC : opCodeType := "001110"; + constant opXorR : opCodeType := "001111"; + constant opTestC : opCodeType := "010010"; + constant opTestR : opCodeType := "010011"; + constant opCompC : opCodeType := "010100"; + constant opCompR : opCodeType := "010101"; + constant opAddC : opCodeType := "011000"; + constant opAddR : opCodeType := "011001"; + constant opAddCyC : opCodeType := "011010"; + constant opAddCyR : opCodeType := "011011"; + constant opSubC : opCodeType := "011100"; + constant opSubR : opCodeType := "011101"; + constant opSubCyC : opCodeType := "011110"; + constant opSubCyR : opCodeType := "011111"; + constant opShRot : opCodeType := "100000"; + constant opOutputC : opCodeType := "101100"; + constant opOutputR : opCodeType := "101101"; + constant opStoreC : opCodeType := "101110"; + constant opStoreR : opCodeType := "101111"; + + subtype shRotCinType is std_ulogic_vector(2 downto 0); + constant shRotLdC : shRotCinType := "00-"; + constant shRotLdM : shRotCinType := "01-"; + constant shRotLdL : shRotCinType := "10-"; + constant shRotLd0 : shRotCinType := "110"; + constant shRotLd1 : shRotCinType := "111"; + + constant registerAddressBitNb : positive := 4; + constant shRotPadLength : positive + := dataOut'length - opCodeType'length - registerAddressBitNb + - 1 - shRotCinType'length; + subtype shRotDirType is std_ulogic_vector(1+shRotPadLength-1 downto 0); + constant shRotL : shRotDirType := (0 => '0', others => '-'); + constant shRotR : shRotDirType := (0 => '1', others => '-'); + + subtype branchCodeType is std_ulogic_vector(4 downto 0); + constant brRet : branchCodeType := "10101"; + constant brCall : branchCodeType := "11000"; + constant brJump : branchCodeType := "11010"; + constant brReti : branchCodeType := "11100"; + constant brEni : branchCodeType := "11110"; + + subtype branchConditionType is std_ulogic_vector(2 downto 0); + constant brDo : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( + --=============================================================== + -- Beamer control + --=============================================================== + -- + ----------------------------------------------------------------- + -- register definitions + -- s0, s1: used for INPUT and OUTPUT operations + -- S2: returns UART data byte + -- S3: uart protocol checksum + -- S4: uart protocol packet id + -- S5: uart protocol command id + -- S6: uart protocol address + -- S7: uart protocol data + -- S8: copy of UART data byte for debug + ----------------------------------------------------------------- + -- + ----------------------------------------------------------------- + -- GPIO definitions + ----------------------------------------------------------------- + ----------------------------------------------------------------- + -- UART definitions + ----------------------------------------------------------------- + -- CONSTANT uartBaudCount, 023D ; 66E6 / 115 200 = 573 + -- CONSTANT uartpollDelay, 0100 + ----------------------------------------------------------------- + -- beamer peripheral definitions + ----------------------------------------------------------------- + -- CONSTANT beamerCtlInit, 1001 + -- + --=============================================================== + -- initializations + --=============================================================== + -- + ----------------------------------------------------------------- + -- initialize GPIO + ----------------------------------------------------------------- + 16#000# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#001# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#002# => opLoadC & "0001" & "0000000010101010", -- LOAD s1, AA + 16#003# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#004# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#005# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#006# => opLoadC & "0001" & "0000000000001111", -- LOAD s1, 0F + 16#007# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize UART + ----------------------------------------------------------------- + 16#008# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 + 16#009# => opAddC & "0000" & "0000000000000010", -- ADD s0, 0002 + 16#00A# => opLoadC & "0001" & "0000000001000010", -- LOAD s1, 0042 + 16#00B# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize beamer peripheral + ----------------------------------------------------------------- + 16#00C# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#00D# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#00E# => opLoadC & "0001" & "0000010000000001", -- LOAD s1, 0401 + 16#00F# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#010# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#011# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#012# => opLoadC & "0001" & "0000000000000100", -- LOAD s1, 0004 + 16#013# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + -- + --=============================================================== + -- Main loop + --=============================================================== + -- + ----------------------------------------------------------------- + -- Process commands from serial port + ----------------------------------------------------------------- + -- _main_: + 16#014# => brCall & brDo & "--------0000100001",-- CALL 021 ; get command from UART + 16#015# => opCompC & "0011" & "0000000000000000", -- COMPARE s3, 0000 ; check function return + 16#016# => brJump & brNZ & "--------0000011111",-- JUMP NZ, 01F + 16#017# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#018# => brJump & brNZ & "--------0000011100",-- JUMP NZ, 01C + 16#019# => opOutputR & "0111" & "0110------------", -- OUTPUT s7, (S6) ; write word to memory location + 16#01A# => brCall & brDo & "--------0001100000",-- CALL 060 ; send write acknowledge + 16#01B# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandRead_: + 16#01C# => opInputR & "0111" & "0110------------", -- INPUT s7, (S6) ; write word in memory location + 16#01D# => brCall & brDo & "--------0001101111",-- CALL 06F ; send back read data + 16#01E# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandAbort_: + 16#01F# => brCall & brDo & "--------0001010001",-- CALL 051 + 16#020# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- + --=============================================================== + -- Subroutines + --=============================================================== + -- + ----------------------------------------------------------------- + -- Get command from serial port + ----------------------------------------------------------------- + -- _uartGetCmd_: + 16#021# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command header + 16#022# => opCompC & "0010" & "0000000010101010", -- COMPARE s2, 00AA + 16#023# => brJump & brNZ & "--------0000100001",-- JUMP NZ, 021 ; loop until byte is AAh + 16#024# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#025# => brCall & brDo & "--------0010000110",-- CALL 086 ; get packet id + 16#026# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#027# => opLoadR & "0100" & "0010------------", -- LOAD s4, s2 ; store id for reply + 16#028# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command + 16#029# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#02A# => opCompC & "0010" & "0000000000000011", -- COMPARE s2, 0003 ; check for WRITE_MEM command + 16#02B# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02C# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; check for READ_MEM command + 16#02D# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02E# => brJump & brDo & "--------0001001111",-- JUMP 04F ; no match + -- _commandOk_: + 16#02F# => opLoadR & "0101" & "0010------------", -- LOAD s5, s2 ; store command for action + 16#030# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data length + 16#031# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#032# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#033# => brJump & brZ & "--------0000110111",-- JUMP Z, 037 ; go to test write command length + 16#034# => opCompC & "0010" & "0000000000000010", -- COMPARE s2, 0002 ; verify READ_MEM length + 16#035# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#036# => brJump & brDo & "--------0000111001",-- JUMP 039 + -- _testWrLength_: + 16#037# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; verify WRITE_MEM length + 16#038# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + -- _getAddress_: + 16#039# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address low + 16#03A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03B# => opLoadR & "0110" & "0010------------", -- LOAD s6, s2 ; store address low + 16#03C# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address high + 16#03D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03E# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#03F# => opAddR & "0110" & "0010------------", -- ADD s6, s2 ; build address from low and high + 16#040# => opCompC & "0101" & "0000000000000100", -- COMPARE s5, 0004 ; check for READ_MEM command + 16#041# => brJump & brZ & "--------0001001001",-- JUMP Z, 049 ; skip reading data word + 16#042# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data low + 16#043# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#044# => opLoadR & "0111" & "0010------------", -- LOAD s7, s2 ; store data low + 16#045# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data high + 16#046# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#047# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#048# => opAddR & "0111" & "0010------------", -- ADD s7, s2 ; build data from low and high + -- _getChecksum_: + 16#049# => brCall & brDo & "--------0010000110",-- CALL 086 ; get checksum + 16#04A# => opAndC & "0011" & "0000000011111111", -- AND s3, 00FF ; limit calculated checksum to 8 bit + 16#04B# => opCompR & "0011" & "0010------------", -- COMPARE s3, s2 ; test checksum + 16#04C# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#04D# => opLoadC & "0011" & "0000000000000000", -- LOAD s3, 0000 ; return OK + 16#04E# => brRet & brDo & "------------------",-- RETURN + -- _commandKo_: + 16#04F# => opLoadC & "0011" & "0000000000000001", -- LOAD s3, 0001 ; return KO + 16#050# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send NACK reply + ----------------------------------------------------------------- + -- _sendNAck_: + 16#051# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#052# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#053# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#054# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#055# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#056# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#057# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; negative Acknowledge + 16#058# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#059# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05A# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#05B# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#05C# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05D# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#05E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send WRITE_MEM reply + ----------------------------------------------------------------- + -- _sendWriteOk_: + 16#060# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#061# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#062# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#063# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#064# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#065# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#066# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#067# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#068# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#069# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#06A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#06B# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06C# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#06D# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06E# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send READ_MEM reply + ----------------------------------------------------------------- + -- _sendReadData_: + 16#06F# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#070# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#071# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#072# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#073# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#074# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#075# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#076# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#077# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#078# => opLoadC & "0010" & "0000000000000010", -- LOAD s2, 0002 ; packet length: 2 bytes + 16#079# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07A# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07B# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data low + 16#07C# => opAndC & "0010" & "0000000011111111", -- AND s2, 00FF ; keep low byte only + 16#07D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07F# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data high + 16#080# => brCall & brDo & "--------0010100101",-- CALL 0A5 ; shift MSBs down to LSBs + 16#081# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#082# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#083# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#084# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#085# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Get byte from serial port + ----------------------------------------------------------------- + -- _uartGetByte_: + 16#086# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#087# => opAddC & "0000" & "0000000000000001", -- ADD s0, 01 + --load s8, 0100 + -- _checkStat_: + 16#088# => opLoadC & "0010" & "0000000001000000", -- LOAD s2, 0040 ; add delay between bus reads + -- _delay0_: + 16#089# => opSubC & "0010" & "0000000000000001", -- SUB s2, 0001 + 16#08A# => brJump & brNZ & "--------0010001001",-- JUMP NZ, 089 + --sub s8, 0001 + --jump nz, continue + --load s2, 0035 + --call uartSendByte + --load s8, 0100 + -- _continue_: + 16#08B# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08C# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08D# => opTestC & "0001" & "0000000000000001", -- TEST s1, 0001 ; check "data ready" bit + 16#08E# => brJump & brZ & "--------0010001000",-- JUMP Z, 088 ; loop until bit is '1' + 16#08F# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART data register + 16#090# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + 16#091# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + --LOAD s8, s2 + 16#092# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Send byte to serial port + ----------------------------------------------------------------- + -- _uartSendByte_: + 16#093# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#094# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + -- _readStatus_: + 16#095# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#096# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#097# => opTestC & "0001" & "0000000000000010", -- TEST s1, 0002 ; check "sending data" bit + 16#098# => brJump & brZ & "--------0010011101",-- JUMP Z, 09D ; loop until bit is '1' + 16#099# => opLoadC & "0001" & "0000000001000000", -- LOAD s1, 0040 ; add delay between bus reads + -- _delay1_: + 16#09A# => opSubC & "0001" & "0000000000000001", -- SUB s1, 0001 + 16#09B# => brJump & brNZ & "--------0010011010",-- JUMP NZ, 09A + 16#09C# => brJump & brDo & "--------0010010101",-- JUMP 095 + -- _sendByte_: + 16#09D# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; write UART data register + 16#09E# => opOutputR & "0010" & "0000------------", -- OUTPUT s2, (S0) + 16#09F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the left + ----------------------------------------------------------------- + -- _shiftS2L8_: + 16#0A0# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftLeftLoop_: + 16#0A1# => opShRot & "0010" & shRotL & shRotLd0, -- SL0 s2 + 16#0A2# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A3# => brJump & brNZ & "--------0010100001",-- JUMP NZ, 0A1 + 16#0A4# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the right + ----------------------------------------------------------------- + -- _shiftS2R8_: + 16#0A5# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftRightLoop_: + 16#0A6# => opShRot & "0010" & shRotR & shRotLd0, -- SR0 s2 + 16#0A7# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A8# => brJump & brNZ & "--------0010100110",-- JUMP NZ, 0A6 + 16#0A9# => brRet & brDo & "------------------",-- RETURN + -- + --=============================================================== + -- End of instruction memory + --=============================================================== + -- _endOfMemory_: + 16#3FF# => brJump & brDo & "--------1111111111",-- JUMP 3FF + others => (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= memoryArray(to_integer(address)); + end if; + end if; + end process; + +END ARCHITECTURE mapped; + + + + +-- VHDL Entity AhbLiteComponents.ahbUart.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:43:49 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +ENTITY ahbUart IS + GENERIC( + txFifoDepth : positive := 8; + rxFifoDepth : positive := 1 + ); + PORT( + RxD : IN std_ulogic; + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic; + hReset_n : IN std_uLogic; + hSel : IN std_uLogic; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic; + TxD : OUT std_ulogic; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic + ); + +-- Declarations + +END ahbUart ; + + + + + +--============================================================================== +-- +-- AHB UART +-- +-- Implements a serial port. +-- +-------------------------------------------------------------------------------- +-- +-- Write registers +-- +-- 00, data register receives the word to be sent to the serial port. +-- 01, control register is used to control the peripheral. +-- 02, scaler register is used to set the baud rate. +-- +-------------------------------------------------------------------------------- +-- +-- Read registers +-- 00, data register provides the last word received by the serial port. +-- 01, status register is used to get the peripheral's state. +-- bit 0: data ready for read +-- bit 1: sending in progress +-- bit 2: receiving in progress +-- + +ARCHITECTURE masterVersion OF ahbUart IS + + signal reset, clock: std_ulogic; + -- register definitions + constant dataOutRegisterId: natural := 0; + constant dataBitNb: positive := 8; + constant controlRegisterId: natural := 1; + constant controlBpoId: natural := 0; + constant controlFormatId: natural := 0; + constant scalerRegisterId: natural := 2; + + constant statusRegisterId: natural := 1; + constant statusReadyId: natural := 0; + constant statusSendingId: natural := 1; + constant statusReceivingId: natural := 2; + -- written registers + signal addressReg: unsigned(addressBitNb(scalerRegisterId)+1-1 downto 0); + signal writeReg: std_ulogic; + signal readReg: std_ulogic; + subtype registerType is unsigned(hWdata'length-1 downto 0); + signal dataOutRegister : unsigned(dataBitNb-1 downto 0); + signal controlRegister, scalerRegister: registerType; + -- serializer + signal txPeriodCounter: unsigned(registerType'range); + signal txEn: std_uLogic; + signal txStart: std_uLogic; + signal txSending: std_uLogic; + signal txShiftCounter : unsigned(addressBitNb(dataOutRegister'length+2)-1 downto 0); + signal txShiftRegister : unsigned(dataOutRegister'high+1 downto 0); + -- read registers + signal dataInRegister : unsigned(dataOutRegister'range); + signal statusRegister: registerType; + -- deserializer + signal rxPeriodCounter: unsigned(registerType'range); + signal rxEn: std_uLogic; + signal rxDelayed, rxChanged: std_uLogic; + signal rxShiftCounter : unsigned(txShiftCounter'range); + signal rxReceiving: std_uLogic; + signal rxShiftRegister : unsigned(dataInRegister'range); + signal rxDataReady: std_uLogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= not hReset_n; + clock <= hClk; + + --============================================================================ + -- address and controls + storeControls: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + writeReg <= '0'; + readReg <= '0'; + elsif rising_edge(clock) then + writeReg <= '0'; + readReg <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addressReg <= hAddr(addressReg'range); + writeReg <= hWrite; + readReg <= not hWrite; + end if; + end if; + end process storeControls; + + --============================================================================ + -- registers + storeWriteRegisters: process(reset, clock) + begin + if reset = '1' then + dataOutRegister <= (others => '0'); + controlRegister <= (others => '0'); + scalerRegister <= (others => '0'); + elsif rising_edge(clock) then + if writeReg = '1' then + case to_integer(addressReg) is + when dataOutRegisterId => dataOutRegister <= unsigned(hWData(dataOutRegister'range)); + when controlRegisterId => controlRegister <= unsigned(hWData); + when scalerRegisterId => scalerRegister <= unsigned(hWData); + when others => null; + end case; + end if; + end if; + end process storeWriteRegisters; + + txStart <= '1' when (writeReg = '1') and (addressReg = dataOutRegisterId) + else '0'; + + --============================================================================ + -- serializer + -- tx baud rate + countTxBaudRate: process(reset, clock) + begin + if reset = '1' then + txPeriodCounter <= (others => '1'); + elsif rising_edge(clock) then + if txPeriodCounter + 1 < scalerRegister then + txPeriodCounter <= txPeriodCounter + 1; + else + txPeriodCounter <= (others => '0'); + end if; + end if; + end process countTxBaudRate; + + txEn <= '1' when txPeriodCounter = 1 + else '0'; + -- count tx shift + countTxShift: process(reset, clock) + begin + if reset = '1' then + txShiftCounter <= (others => '0'); + elsif rising_edge(clock) then + if txShiftCounter = 0 then + if txStart = '1' then + txShiftCounter <= txShiftCounter + 1; + end if; + elsif txEn = '1' then + if txShiftCounter < dataOutRegister'length + 3 then + txShiftCounter <= txShiftCounter + 1; + else + txShiftCounter <= (others => '0'); + end if; + end if; + end if; + end process countTxShift; + + txSending <= '1' when txShiftCounter /= 0 + else '0'; + -- tx serializer + shiftTxData: process(reset, clock) + begin + if reset = '1' then + txShiftRegister <= (others => '1'); + elsif rising_edge(clock) then + if txEn = '1' then + if txShiftCounter = 1 then + txShiftRegister <= dataOutRegister & '0'; + else + txShiftRegister <= shift_right(txShiftRegister, 1); + txShiftRegister(txShiftRegister'high) <= '1'; + end if; + end if; + end if; + end process shiftTxData; + + TxD <= txShiftRegister(0); + + --============================================================================ + -- deserializer + delayRxd: process(reset, clock) + begin + if reset = '1' then + rxDelayed <= '0'; + elsif rising_edge(clock) then + rxDelayed <= RxD; + end if; + end process delayRxd; + + rxChanged <= '1' when rxDelayed /= RxD + else '0'; + -- rx baud rate + countRxBaudRate: process(reset, clock) + begin + if reset = '1' then + rxPeriodCounter <= (others => '1'); + elsif rising_edge(clock) then + if rxChanged = '1' then + rxPeriodCounter <= (others => '0'); + elsif rxPeriodCounter + 1 < scalerRegister then + rxPeriodCounter <= rxPeriodCounter + 1; + else + rxPeriodCounter <= (others => '0'); + end if; + end if; + end process countRxBaudRate; + + rxEn <= '1' when rxPeriodCounter = shift_right(scalerRegister-2, 1) + else '0'; + -- count rx shift + countRxShift: process(reset, clock) + begin + if reset = '1' then + rxShiftCounter <= (others => '0'); + elsif rising_edge(clock) then + if rxShiftCounter = 0 then + if (RxD = '0') and (rxDelayed = '1') then + rxShiftCounter <= rxShiftCounter + 1; + end if; + elsif rxEn = '1' then + if rxShiftCounter < dataInRegister'length + 2 then + rxShiftCounter <= rxShiftCounter + 1; + else + rxShiftCounter <= (others => '0'); + end if; + end if; + end if; + end process countRxShift; + + rxReceiving <= '1' when rxShiftCounter /= 0 + else '0'; + -- rx deserializer + shiftRxData: process(reset, clock) + begin + if reset = '1' then + rxShiftRegister <= (others => '1'); + dataInRegister <= (others => '0'); + elsif rising_edge(clock) then + if rxEn = '1' then + if rxShiftCounter <= dataInRegister'length+1 then + rxShiftRegister <= shift_right(rxShiftRegister, 1); + rxShiftRegister(rxShiftRegister'high) <= RxD; + end if; + if rxShiftCounter = dataInRegister'length+2 then + dataInRegister <= rxShiftRegister; + end if; + end if; + end if; + end process shiftRxData; + -- monitor data ready + checkDataReady: process(reset, clock) + begin + if reset = '1' then + rxDataReady <= '0'; + elsif rising_edge(clock) then + if (rxEn = '1') and (rxShiftCounter = dataInRegister'length+2) then + rxDataReady <= '1'; + elsif (readReg = '1') and (addressReg = dataOutRegisterId) then + rxDataReady <= '0'; + end if; + end if; + end process checkDataReady; + + --============================================================================ + -- data readback + statusRegister <= ( + statusReadyId => rxDataReady, + statusSendingId => txSending, + statusReceivingId => rxReceiving, + others => '0' + ); + + selectData: process(addressReg, dataInRegister, statusRegister) + begin + hRData <= (others => '-'); + case to_integer(addressReg) is + when dataOutRegisterId => hRData <= std_ulogic_vector(resize(dataInRegister, hRData'length)); + when statusRegisterId => hRData <= std_ulogic_vector(statusRegister); + when others => null; + end case; + end process selectData; + + hReady <= '1'; -- no wait state + hResp <= '0'; -- data OK + + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity NanoBlaze.nanoProcessor.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:43 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY nanoProcessor IS + GENERIC( + addressBitNb : positive := 8; + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5; + instructionBitNb : positive := 18; + scratchpadAddressBitNb : natural := 4 + ); + PORT( + clock : IN std_ulogic; + dataIn : IN std_ulogic_vector (registerBitNb-1 DOWNTO 0); + en : IN std_ulogic; + instruction : IN std_ulogic_vector (instructionBitNb-1 DOWNTO 0); + int : IN std_uLogic; + reset : IN std_ulogic; + dataAddress : OUT unsigned (addressBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (registerBitNb-1 DOWNTO 0); + intAck : OUT std_ulogic; + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + readStrobe : OUT std_uLogic; + writeStrobe : OUT std_uLogic + ); + +-- Declarations + +END nanoProcessor ; + + + + + +-- VHDL Entity NanoBlaze.aluAndRegs.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:43 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY aluAndRegs IS + GENERIC( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + portAddressBitNb : positive := 8; + scratchpadAddressBitNb : natural := 4 + ); + PORT( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic; + clock : IN std_ulogic; + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic; + regWrite : IN std_ulogic; + registerFileSel : IN std_ulogic; + reset : IN std_ulogic; + scratchpadSel : IN std_ulogic; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic; + portAddr : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + scratchpadAddr : OUT unsigned (scratchpadAddressBitNb-1 DOWNTO 0); + spadOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + zero : OUT std_ulogic + ); + +-- Declarations + +END aluAndRegs ; + + + + + +-- VHDL Entity NanoBlaze.alu.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY alu IS + GENERIC( + aluCodeBitNb : positive := 5; + dataBitNb : positive := 8 + ); + PORT( + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic; + opA : IN signed ( dataBitNb-1 DOWNTO 0 ); + opB : IN signed ( dataBitNb-1 DOWNTO 0 ); + aluOut : OUT signed ( dataBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic; + zero : OUT std_ulogic + ); + +-- Declarations + +END alu ; + + + + + +ARCHITECTURE RTL OF alu IS + + signal aluCodeInt: unsigned(aluCode'range); + signal aArith: signed(opA'high+1 downto 0); + signal bArith: signed(opA'high+1 downto 0); + signal cInArith: signed(1 downto 0); + signal cInShift: std_ulogic; + signal yArith: signed(aluOut'high+1 downto 0); + signal aluOutInt: signed(aluOut'range); + +BEGIN + ------------------------------------------------------------------------------ + -- clear aluCode don't care LSB for shifts + aluCodeInt(aluCode'high downto 1) <= unsigned(aluCode(aluCode'high downto 1)); + + cleanupLsb: process(aluCode) + begin + if aluCode(aluCode'high) = '1' then + aluCodeInt(0) <= '0'; + else + aluCodeInt(0) <= aluCode(0); + end if; + end process cleanupLsb; + + ------------------------------------------------------------------------------ + -- values for arithmetic operations + aArith <= signed(resize(unsigned(opA), aArith'length)); + bArith <= signed(resize(unsigned(opB), bArith'length)); + cInArith <= (0 => cIn, others => '0'); + + process(aluCode, cIn, opA) + begin + case aluCode(2 downto 1) is + when "00" => cInShift <= cIn; + when "01" => cInShift <= opA(opA'high); + when "10" => cInShift <= opA(opA'low); + when "11" => cInShift <= aluCode(0); + when others => cInShift <= '-'; + end case; + end process; + + ------------------------------------------------------------------------------ + -- alu operations + aluOperation: process( + aluCodeInt, + opA, opB, + aArith, bArith, cInArith, + cInShift, + yArith, aluOutInt + ) + variable xorAcc: std_ulogic; + begin + yArith <= (others => '-'); + cOut <= '-'; + aluOutInt <= (others => '-'); + case to_integer(aluCodeInt) is + when 0 => -- LOAD sX, kk + aluOutInt <= opB; + when 2 => -- INPUT sX, pp + aluOutInt <= opB; + when 3 => -- FETCH sX, ss + aluOutInt <= opB; + when 5 => -- AND sX, kk + aluOutInt <= opA and opB; + cOut <= '0'; + when 6 => -- OR sX, kk + aluOutInt <= opA or opB; + cOut <= '0'; + when 7 => -- XOR sX, kk + aluOutInt <= opA xor opB; + cOut <= '0'; + when 9 => -- TEST sX, kk + aluOutInt <= opA and opB; + xorAcc := '0'; + for index in aluOutInt'range loop + xorAcc := xorAcc xor aluOutInt(index); + end loop; + cOut <= xorAcc; + when 10 => -- COMPARE sX, kk + yArith <= aArith - bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 12 => -- ADD sX, kk + yArith <= aArith + bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 13 => -- ADDCY sX, kk + yArith <= (aArith + bArith) + cInArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 14 => -- SUB sX, kk + yArith <= aArith - bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 15 => -- SUBCY sX, kk + yArith <= (aArith - bArith) - cInArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 16 to 23 => -- SL sX + aluOutInt <= opA(opA'high-1 downto 0) & cInShift; + cOut <= opA(opA'high); + when 24 to 31 => -- SR sX + aluOutInt <= cInShift & opA(opA'high downto 1); + cOut <= opA(0); + when others => + aluOutInt <= (others => '-'); + end case; + end process aluOperation; + + aluOut <= aluOutInt; + zero <= '1' when aluOutInt = 0 else '0'; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.aluBOpSelector.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY aluBOpSelector IS + GENERIC( + registerBitNb : positive := 8 + ); + PORT( + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic; + registerFileIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + registerFileSel : IN std_ulogic; + scratchpadSel : IN std_ulogic; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + opB : OUT signed (registerBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END aluBOpSelector ; + + + + + +ARCHITECTURE RTL OF aluBOpSelector IS +BEGIN + + selectDataSource: process( + registerFileSel, registerFileIn, + scratchpadSel, spadIn, + portInSel, portIn, + instrDataSel, instrData + ) + begin + if registerFileSel = '1' then + opB <= registerFileIn; + elsif scratchpadSel = '1' then + opB <= spadIn; + elsif portInSel = '1' then + opB <= portIn; + elsif instrDataSel = '1' then + opB <= instrData; + else + opB <= (others => '-'); + end if; + end process selectDataSource; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.registerFile.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY registerFile IS + GENERIC( + registerAddressBitNb : positive := 4; + dataBitNb : positive := 8 + ); + PORT( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic; + regWrite : IN std_ulogic; + registersIn : IN signed ( dataBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic; + opA : OUT signed ( dataBitNb-1 DOWNTO 0 ); + opB : OUT signed ( dataBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END registerFile ; + + + + + +ARCHITECTURE RTL OF registerFile IS + + subtype registerType is signed(registersIn'range); + type registerArrayType is array (0 to 2**registerAddressBitNb-1) of registerType; + signal registerArray : registerArrayType; + +BEGIN + ------------------------------------------------------------------------------ + -- write to registers + updateRegister: process(reset, clock) + begin + if reset = '1' then + registerArray <= (others => (others => '0')); + elsif rising_edge(clock) then + if regWrite = '1' then + registerArray(to_integer(addrA)) <= registersIn; + end if; + end if; + end process updateRegister; + + ------------------------------------------------------------------------------ + -- read from registers + opA <= registerArray(to_integer(addrA)); + opB <= registerArray(to_integer(addrB)); + +END ARCHITECTURE RTL; + + + + +-- +-- VHDL Architecture NanoBlaze.aluAndRegs.struct +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:44 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY NanoBlaze; + +ARCHITECTURE struct OF aluAndRegs IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL aluOut : signed(registerBitNb-1 DOWNTO 0); + SIGNAL opA : signed(registerBitNb-1 DOWNTO 0); + SIGNAL opB : signed(registerBitNb-1 DOWNTO 0); + SIGNAL registerFileIn : signed(registerBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT alu + GENERIC ( + aluCodeBitNb : positive := 5; + dataBitNb : positive := 8 + ); + PORT ( + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic ; + opA : IN signed ( dataBitNb-1 DOWNTO 0 ); + opB : IN signed ( dataBitNb-1 DOWNTO 0 ); + aluOut : OUT signed ( dataBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic ; + zero : OUT std_ulogic + ); + END COMPONENT; + COMPONENT aluBOpSelector + GENERIC ( + registerBitNb : positive := 8 + ); + PORT ( + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic ; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic ; + registerFileIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + registerFileSel : IN std_ulogic ; + scratchpadSel : IN std_ulogic ; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + opB : OUT signed (registerBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT registerFile + GENERIC ( + registerAddressBitNb : positive := 4; + dataBitNb : positive := 8 + ); + PORT ( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic ; + regWrite : IN std_ulogic ; + registersIn : IN signed ( dataBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic ; + opA : OUT signed ( dataBitNb-1 DOWNTO 0 ); + opB : OUT signed ( dataBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : alu USE ENTITY NanoBlaze.alu; + FOR ALL : aluBOpSelector USE ENTITY NanoBlaze.aluBOpSelector; + FOR ALL : registerFile USE ENTITY NanoBlaze.registerFile; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + portOut <= opA; + spadOut <= opA; + + -- HDL Embedded Text Block 2 eb2 + portAddr <= resize(unsigned(registerFileIn), portAddressBitNb); + scratchpadAddr <= resize(unsigned(registerFileIn), scratchpadAddressBitNb); + + + -- Instance port mappings. + I_ALU : alu + GENERIC MAP ( + aluCodeBitNb => aluCodeBitNb, + dataBitNb => registerBitNb + ) + PORT MAP ( + aluCode => aluCode, + cIn => cIn, + opA => opA, + opB => opB, + aluOut => aluOut, + cOut => cOut, + zero => zero + ); + I_bSel : aluBOpSelector + GENERIC MAP ( + registerBitNb => registerBitNb + ) + PORT MAP ( + instrData => instrData, + instrDataSel => instrDataSel, + portIn => portIn, + portInSel => portInSel, + registerFileIn => registerFileIn, + registerFileSel => registerFileSel, + scratchpadSel => scratchpadSel, + spadIn => spadIn, + opB => opB + ); + I_regs : registerFile + GENERIC MAP ( + registerAddressBitNb => registerAddressBitNb, + dataBitNb => registerBitNb + ) + PORT MAP ( + addrA => addrA, + addrB => addrB, + clock => clock, + regWrite => regWrite, + registersIn => aluOut, + reset => reset, + opA => opA, + opB => registerFileIn + ); + +END struct; + + + + +-- VHDL Entity NanoBlaze.branchStack.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY branchStack IS + GENERIC( + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5 + ); + PORT( + clock : IN std_ulogic; + prevPC : IN std_ulogic; + progCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic; + storePC : IN std_ulogic; + storedProgCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END branchStack ; + + + + + +ARCHITECTURE RTL OF branchStack IS + + subtype progCounterType is unsigned(progCounter'range); + type progCounterArrayType is array (0 to 2**stackPointerBitNb) of progCounterType; + signal progCounterArray : progCounterArrayType; + + signal writePointer : unsigned(stackPointerBitNb-1 downto 0); + signal readPointer : unsigned(stackPointerBitNb-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- stack pointers + updateStackPointer: process(reset, clock) + begin + if reset = '1' then + writePointer <= (others => '0'); + elsif rising_edge(clock) then + if storePC = '1' then + writePointer <= writePointer + 1; + elsif prevPC = '1' then + writePointer <= writePointer - 1; + end if; + end if; + end process updateStackPointer; + + readPointer <= writePointer - 1; + + ------------------------------------------------------------------------------ + -- program counters stack + updateStack: process(reset, clock) + begin + if rising_edge(clock) then + if storePc = '1' then + progCounterArray(to_integer(writePointer)) <= progCounter; + end if; + storedProgCounter <= progCounterArray(to_integer(readPointer)); + end if; + end process updateStack; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.controller.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY controller IS + GENERIC( + intCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + opCodeBitNb : positive := 5 + ); + PORT( + branchCond : IN std_ulogic_vector ( branchCondBitNb-1 DOWNTO 0 ); + cOut : IN std_ulogic; + clock : IN std_ulogic; + en : IN std_ulogic; + int : IN std_uLogic; + intCode : IN std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : IN std_ulogic_vector (opCodeBitNb-1 DOWNTO 0); + reset : IN std_ulogic; + twoRegInstr : IN std_ulogic; + zero : IN std_ulogic; + cIn : OUT std_ulogic; + incPC : OUT std_ulogic; + instrDataSel : OUT std_ulogic; + intAck : OUT std_ulogic; + loadInstrAddress : OUT std_ulogic; + loadStoredPC : OUT std_ulogic; + portInSel : OUT std_ulogic; + prevPC : OUT std_ulogic; + readStrobe : OUT std_uLogic; + regWrite : OUT std_ulogic; + registerFileSel : OUT std_ulogic; + scratchpadSel : OUT std_ulogic; + scratchpadWrite : OUT std_ulogic; + storePC : OUT std_ulogic; + writeStrobe : OUT std_uLogic + ); + +-- Declarations + +END controller ; + + + + + +ARCHITECTURE RTL OF controller IS + + signal en1, enInt: std_ulogic; + + constant opCodeLength : integer := 5; + subtype opCodeType is std_ulogic_vector(opCodeLength-1 downto 0); + constant opLoad : opCodeType := "00000"; + constant opInput : opCodeType := "00010"; + constant opFetch : opCodeType := "00011"; + constant opAnd : opCodeType := "00101"; + constant opOr : opCodeType := "00110"; + constant opXor : opCodeType := "00111"; + constant opTest : opCodeType := "01001"; + constant opComp : opCodeType := "01010"; + constant opAdd : opCodeType := "01100"; + constant opAddCy : opCodeType := "01101"; + constant opSub : opCodeType := "01110"; + constant opSubCy : opCodeType := "01111"; + constant opShRot : opCodeType := "10000"; + constant opRet : opCodeType := "10101"; + constant opOutput: opCodeType := "10110"; + constant opStore : opCodeType := "10111"; + constant opCall : opCodeType := "11000"; + constant opJump : opCodeType := "11010"; + constant opIntF : opCodeType := "11110"; + + constant branchConditionLength : integer := 3; + subtype branchConditionType is std_ulogic_vector(branchConditionLength-1 downto 0); + constant brAw : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + signal aluOpSel: std_ulogic; + signal regWriteEn: std_ulogic; + + signal flagsEn, flagsEnable: std_ulogic; + signal carrySaved: std_ulogic; + signal zeroSaved: std_ulogic; + + signal branchEnable1, branchEnable: std_ulogic; + signal discardOpCode: std_ulogic; + + signal updateIntFlag: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- Enable signal + buildEnable: process(reset, clock) + begin + if reset = '1' then + en1 <= '0'; + elsif rising_edge(clock) then + en1 <= '1'; + end if; + end process buildEnable; + + enInt <= en1 and en; -- don't enable very first instruction twice + + ------------------------------------------------------------------------------ + -- ALU controls + selectdataSource: process(opCode) + begin + aluOpSel <= '0'; + portInSel <= '0'; + scratchpadSel <= '0'; + case opCode(opCodeLength-1 downto 0) is + when opLoad => aluOpSel <= '1'; + when opInput => portInSel <= '1'; + when opFetch => scratchpadSel <= '1'; + when opAnd => aluOpSel <= '1'; + when opOr => aluOpSel <= '1'; + when opXor => aluOpSel <= '1'; + when opTest => aluOpSel <= '1'; + when opComp => aluOpSel <= '1'; + when opAdd => aluOpSel <= '1'; + when opAddCy => aluOpSel <= '1'; + when opSub => aluOpSel <= '1'; + when opSubCy => aluOpSel <= '1'; + when opShRot => aluOpSel <= '1'; + when others => aluOpSel <= '-'; + portInSel <= '-'; + scratchpadSel <= '-'; + end case; + end process selectdataSource; + + registerFileSel <= aluOpSel and twoRegInstr; + instrDataSel <= aluOpSel and (not twoRegInstr); + + regWriteEn <= enInt and (not discardOpCode); + + regWriteTable: process(opCode, regWriteEn) + begin + case opCode(opCodeLength-1 downto 0) is + when opLoad => regWrite <= regWriteEn; + when opInput => regWrite <= regWriteEn; + when opFetch => regWrite <= regWriteEn; + when opAnd => regWrite <= regWriteEn; + when opOr => regWrite <= regWriteEn; + when opXor => regWrite <= regWriteEn; + when opAdd => regWrite <= regWriteEn; + when opAddCy => regWrite <= regWriteEn; + when opSub => regWrite <= regWriteEn; + when opSubCy => regWrite <= regWriteEn; + when opShRot => regWrite <= regWriteEn; + when others => regWrite <= '0'; + end case; + end process regWriteTable; + + ------------------------------------------------------------------------------ + -- I/O controls + readStrobe <= enInt when (opCode = opInput) and (discardOpCode = '0') + else '0'; + writeStrobe <= enInt when (opCode = opOutput) and (discardOpCode = '0') + else '0'; + + ------------------------------------------------------------------------------ + -- scratchpad controls + scratchpadWrite <= '1' when opCode = opStore else '0'; + + ------------------------------------------------------------------------------ + -- Carry logic + flagsEn <= enInt and (not branchEnable); + + flagsEnableTable: process(opCode, flagsEn) + begin + case opCode(opCodeLength-1 downto 0) is + when opAnd => flagsEnable <= flagsEn; + when opOr => flagsEnable <= flagsEn; + when opXor => flagsEnable <= flagsEn; + when opTest => flagsEnable <= flagsEn; + when opComp => flagsEnable <= flagsEn; + when opAdd => flagsEnable <= flagsEn; + when opAddCy => flagsEnable <= flagsEn; + when opSub => flagsEnable <= flagsEn; + when opSubCy => flagsEnable <= flagsEn; + when opShRot => flagsEnable <= flagsEn; + when others => flagsEnable <= '0'; + end case; + end process flagsEnableTable; + + saveCarries: process(reset, clock) + begin + if reset = '1' then + carrySaved <= '0'; + zeroSaved <= '0'; + elsif rising_edge(clock) then + if flagsEnable = '1' then + carrySaved <= cOut; + zeroSaved <= zero; + end if; + end if; + end process saveCarries; + + cIn <= carrySaved; + + ------------------------------------------------------------------------------ + -- Program counter controls + checkBranchCondition: process(branchCond, zeroSaved, carrySaved) + begin + case branchCond(branchConditionLength-1 downto 0) is + when brAw => branchEnable1 <= '1'; + when brZ => branchEnable1 <= zeroSaved; + when brNZ => branchEnable1 <= not zeroSaved; + when brC => branchEnable1 <= carrySaved; + when brNC => branchEnable1 <= not carrySaved; + when others => branchEnable1 <= '-'; + end case; + end process checkBranchCondition; + + branchEnableTable: process(opCode, branchEnable1, discardOpCode) + begin + if discardOpCode = '0' then + case opCode(opCodeLength-1 downto 0) is + when opRet => branchEnable <= branchEnable1; + when opCall => branchEnable <= branchEnable1; + when opJump => branchEnable <= branchEnable1; + when others => branchEnable <= '0'; + end case; + else + branchEnable <= '0'; + end if; + end process branchEnableTable; + + progCounterControlTable: process(opCode, enInt, branchEnable) + begin + incPC <= enInt; + loadInstrAddress <= '0'; + loadStoredPC <= '0'; + case opCode(opCodeLength-1 downto 0) is + when opRet => incPC <= not branchEnable; + loadStoredPC <= enInt and branchEnable; + when opCall => incPC <= not branchEnable; + loadInstrAddress <= enInt and branchEnable; + when opJump => incPC <= not branchEnable; + loadInstrAddress <= enInt and branchEnable; + when others => null; + end case; + end process progCounterControlTable; + + -- If a branch condition is met, the next operation has to be discarded. + -- This is due to the synchronous operation of the program ROM: the + -- instructions are provided one clock period after the program counter. + -- so while the branch operation is processed, the next instruction is + -- already being fetched. + delayBranchEnable: process(reset, clock) + begin + if reset = '1' then + discardOpCode <= '0'; + elsif rising_edge(clock) then + discardOpCode <= branchEnable; + end if; + end process delayBranchEnable; + + ------------------------------------------------------------------------------ + -- Stack pointer controls + pcStackControlTable: process(discardOpCode, opCode, enInt) + begin + storePC <= '0'; + prevPC <= '0'; + if discardOpCode = '0' then + case opCode(opCodeLength-1 downto 0) is + when opRet => prevPC <= enInt; + when opCall => storePC <= enInt; + when others => null; + end case; + end if; + end process pcStackControlTable; + + + ------------------------------------------------------------------------------ + -- interrupt control + updateIntFlag <= '1' when opCode = opIntF else '0'; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.instructionDecoder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY instructionDecoder IS + GENERIC( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + instructionBitNb : positive := 18; + programCounterBitNb : positive := 10; + opCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + intCodeBitNb : positive := 5; + spadAddressBitNb : natural := 4; + portAddressBitNb : positive := 8 + ); + PORT( + instruction : IN std_ulogic_vector ( instructionBitNb-1 DOWNTO 0 ); + addrA : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : OUT std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + branchCond : OUT std_ulogic_vector (branchCondBitNb-1 DOWNTO 0); + instrAddress : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + instrData : OUT signed ( registerBitNb-1 DOWNTO 0 ); + intCode : OUT std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : OUT std_ulogic_vector ( opCodeBitNb-1 DOWNTO 0 ); + portAddress : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portIndexedSel : OUT std_ulogic; + spadAddress : OUT unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + spadIndexedSel : OUT std_ulogic; + twoRegInstr : OUT std_ulogic + ); + +-- Declarations + +END instructionDecoder ; + + + + + +ARCHITECTURE RTL OF instructionDecoder IS + + constant opCodeIndexH : integer := instruction'high; + constant opCodeIndexL : integer := opCodeIndexH - opCodeBitNb + 1; + + constant twoRegInstrIndex : integer := opCodeIndexL - 1; + constant ioAddrIndexed : integer := twoRegInstrIndex; + + constant addrAIndexH : integer := twoRegInstrIndex - 1; + constant addrAIndexL : integer := addrAIndexH - registerAddressBitNb + 1; + + constant immediateDataIndexH : integer := registerBitNb-1; + constant immediateDataIndexL : integer := 0; + constant addrBIndexH : integer := addrAIndexL - 1; + constant addrBIndexL : integer := addrBIndexH - registerAddressBitNb + 1; + + constant aluCodeIndexH : integer := opCodeIndexH; + constant aluCodeIndexL : integer := aluCodeIndexH - aluCodeBitNb + 1; + + constant portAddressH : integer := registerBitNb-1; + constant portAddressL : integer := portAddressH-portAddressBitNb+1; + constant spadAddressH : integer := registerBitNb-1; + constant spadAddressL : integer := spadAddressH-spadAddressBitNb+1; + + constant branchCondH : integer := opCodeIndexL-1; + constant branchCondL : integer := branchCondH-branchCondBitNb+1; + +BEGIN + ------------------------------------------------------------------------------ + -- ALU control + aluCode <= + instruction(aluCodeIndexH downto aluCodeIndexL) + when instruction(aluCodeIndexH) = '0' else + '1' & instruction(aluCodeBitNb-2 downto 0); + opCode <= instruction(opCodeIndexH downto opCodeIndexL); + twoRegInstr <= instruction(twoRegInstrIndex); + addrA <= unsigned(instruction(addrAIndexH downto addrAIndexL)); + addrB <= unsigned(instruction(addrBIndexH downto addrBIndexL)); + instrData <= signed(instruction(immediateDataIndexH downto immediateDataIndexL)); + + ------------------------------------------------------------------------------ + -- I/O control + portIndexedSel <= instruction(ioAddrIndexed); + portAddress <= unsigned(instruction(portAddressH downto portAddressL)); + + ------------------------------------------------------------------------------ + -- scratchpad control + spadIndexedSel <= instruction(ioAddrIndexed); + spadAddress <= unsigned(instruction(spadAddressH downto spadAddressL)); + + ------------------------------------------------------------------------------ + -- branch control + branchCond <= instruction(branchCondH downto branchCondL); + instrAddress <= unsigned(instruction(instrAddress'range)); + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.programCounter.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY programCounter IS + GENERIC( + programCounterBitNb : positive := 10 + ); + PORT( + clock : IN std_ulogic; + incPC : IN std_ulogic; + instrAddress : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + loadInstrAddress : IN std_ulogic; + loadStoredPC : IN std_ulogic; + reset : IN std_ulogic; + storedProgCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END programCounter ; + + + + + +ARCHITECTURE RTL OF programCounter IS + + signal pCounter: unsigned(progCounter'range); + +BEGIN + + updateProgramCounter: process(reset, clock) + begin + if reset = '1' then + pCounter <= (others => '0'); + elsif rising_edge(clock) then + if incPC = '1' then + pCounter <= pCounter + 1; + elsif loadInstrAddress = '1' then + pCounter <= instrAddress; + elsif loadStoredPC = '1' then + pCounter <= storedProgCounter; + end if; + end if; + end process updateProgramCounter; + + progCounter <= pCounter; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.scratchpad.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY scratchpad IS + GENERIC( + registerBitNb : positive := 8; + spadAddressBitNb : natural := 4 + ); + PORT( + addr : IN unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic; + dataIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic; + write : IN std_ulogic; + dataOut : OUT signed ( registerBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END scratchpad ; + + + + + +ARCHITECTURE RTL OF scratchpad IS + + subtype memoryWordType is signed(dataOut'range); + type memoryArrayType is array (0 to 2**addr'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType; + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if write = '1' then + memoryArray(to_integer(addr)) <= dataIn; + end if; + end if; + end process; + + dataOut <= memoryArray(to_integer(addr)); + +END ARCHITECTURE RTL; + + + + +-- +-- VHDL Architecture NanoBlaze.nanoProcessor.struct +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:43 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY NanoBlaze; + +ARCHITECTURE struct OF nanoProcessor IS + + -- Architecture declarations + constant aluCodeBitNb: positive := 5; + constant opCodeBitNb: positive := 5; + constant branchCondBitNb: positive := 3; + constant intCodeBitNb: positive := 5; + + -- Internal signal declarations + SIGNAL addrA : unsigned( registerAddressBitNb-1 DOWNTO 0 ); + SIGNAL addrB : unsigned( registerAddressBitNb-1 DOWNTO 0 ); + SIGNAL aluCode : std_ulogic_vector( aluCodeBitNb-1 DOWNTO 0 ); + SIGNAL branchCond : std_ulogic_vector(branchCondBitNb-1 DOWNTO 0); + SIGNAL cIn : std_ulogic; + SIGNAL cOut : std_ulogic; + SIGNAL incPC : std_ulogic; + SIGNAL instrAddress : unsigned( programCounterBitNb-1 DOWNTO 0 ); + SIGNAL instrData : signed( registerBitNb-1 DOWNTO 0 ); + SIGNAL instrDataSel : std_ulogic; + SIGNAL instrString : string(1 TO 16); + SIGNAL intCode : std_ulogic_vector( intCodeBitNb-1 DOWNTO 0 ); + SIGNAL loadInstrAddress : std_ulogic; + SIGNAL loadStoredPC : std_ulogic; + SIGNAL opCode : std_ulogic_vector( opCodeBitNb-1 DOWNTO 0 ); + SIGNAL portIn : signed( registerBitNb-1 DOWNTO 0 ); + SIGNAL portInSel : std_ulogic; + SIGNAL portIndexedSel : std_ulogic; + SIGNAL portInstrAddress : unsigned(addressBitNb-1 DOWNTO 0); + SIGNAL portOut : signed( registerBitNb-1 DOWNTO 0 ); + SIGNAL portRegAddress : unsigned(addressBitNb-1 DOWNTO 0); + SIGNAL prevPC : std_ulogic; + SIGNAL regWrite : std_ulogic; + SIGNAL registerFileSel : std_ulogic; + SIGNAL scratchpadSel : std_ulogic; + SIGNAL scratchpadWrite : std_ulogic; + SIGNAL spadAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0); + SIGNAL spadIn : signed(registerBitNb-1 DOWNTO 0); + SIGNAL spadIndexedSel : std_ulogic; + SIGNAL spadInstrAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0); + SIGNAL spadOut : signed(registerBitNb-1 DOWNTO 0); + SIGNAL spadRegAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0); + SIGNAL storePC : std_ulogic; + SIGNAL storedProgCounter : unsigned( programCounterBitNb-1 DOWNTO 0 ); + SIGNAL twoRegInstr : std_ulogic; + SIGNAL zero : std_ulogic; + + -- Implicit buffer signal declarations + SIGNAL progCounter_internal : unsigned ( programCounterBitNb-1 DOWNTO 0 ); + + + -- Component Declarations + COMPONENT aluAndRegs + GENERIC ( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + portAddressBitNb : positive := 8; + scratchpadAddressBitNb : natural := 4 + ); + PORT ( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic ; + clock : IN std_ulogic ; + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic ; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic ; + regWrite : IN std_ulogic ; + registerFileSel : IN std_ulogic ; + reset : IN std_ulogic ; + scratchpadSel : IN std_ulogic ; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic ; + portAddr : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + scratchpadAddr : OUT unsigned (scratchpadAddressBitNb-1 DOWNTO 0); + spadOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + zero : OUT std_ulogic + ); + END COMPONENT; + COMPONENT branchStack + GENERIC ( + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5 + ); + PORT ( + clock : IN std_ulogic ; + prevPC : IN std_ulogic ; + progCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic ; + storePC : IN std_ulogic ; + storedProgCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + COMPONENT controller + GENERIC ( + intCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + opCodeBitNb : positive := 5 + ); + PORT ( + branchCond : IN std_ulogic_vector ( branchCondBitNb-1 DOWNTO 0 ); + cOut : IN std_ulogic ; + clock : IN std_ulogic ; + en : IN std_ulogic ; + int : IN std_uLogic ; + intCode : IN std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : IN std_ulogic_vector (opCodeBitNb-1 DOWNTO 0); + reset : IN std_ulogic ; + twoRegInstr : IN std_ulogic ; + zero : IN std_ulogic ; + cIn : OUT std_ulogic ; + incPC : OUT std_ulogic ; + instrDataSel : OUT std_ulogic ; + intAck : OUT std_ulogic ; + loadInstrAddress : OUT std_ulogic ; + loadStoredPC : OUT std_ulogic ; + portInSel : OUT std_ulogic ; + prevPC : OUT std_ulogic ; + readStrobe : OUT std_uLogic ; + regWrite : OUT std_ulogic ; + registerFileSel : OUT std_ulogic ; + scratchpadSel : OUT std_ulogic ; + scratchpadWrite : OUT std_ulogic ; + storePC : OUT std_ulogic ; + writeStrobe : OUT std_uLogic + ); + END COMPONENT; + COMPONENT instructionDecoder + GENERIC ( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + instructionBitNb : positive := 18; + programCounterBitNb : positive := 10; + opCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + intCodeBitNb : positive := 5; + spadAddressBitNb : natural := 4; + portAddressBitNb : positive := 8 + ); + PORT ( + instruction : IN std_ulogic_vector ( instructionBitNb-1 DOWNTO 0 ); + addrA : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : OUT std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + branchCond : OUT std_ulogic_vector (branchCondBitNb-1 DOWNTO 0); + instrAddress : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + instrData : OUT signed ( registerBitNb-1 DOWNTO 0 ); + intCode : OUT std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : OUT std_ulogic_vector ( opCodeBitNb-1 DOWNTO 0 ); + portAddress : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portIndexedSel : OUT std_ulogic ; + spadAddress : OUT unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + spadIndexedSel : OUT std_ulogic ; + twoRegInstr : OUT std_ulogic + ); + END COMPONENT; + COMPONENT programCounter + GENERIC ( + programCounterBitNb : positive := 10 + ); + PORT ( + clock : IN std_ulogic ; + incPC : IN std_ulogic ; + instrAddress : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + loadInstrAddress : IN std_ulogic ; + loadStoredPC : IN std_ulogic ; + reset : IN std_ulogic ; + storedProgCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + COMPONENT scratchpad + GENERIC ( + registerBitNb : positive := 8; + spadAddressBitNb : natural := 4 + ); + PORT ( + addr : IN unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic ; + dataIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic ; + write : IN std_ulogic ; + dataOut : OUT signed ( registerBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : aluAndRegs USE ENTITY NanoBlaze.aluAndRegs; + FOR ALL : branchStack USE ENTITY NanoBlaze.branchStack; + FOR ALL : controller USE ENTITY NanoBlaze.controller; + FOR ALL : instructionDecoder USE ENTITY NanoBlaze.instructionDecoder; + FOR ALL : programCounter USE ENTITY NanoBlaze.programCounter; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + dataAddress <= portInstrAddress when portIndexedSel = '0' else portRegAddress; + + -- HDL Embedded Text Block 2 eb2 + dataOut <= std_ulogic_vector(portOut); + portIn <= signed(dataIn); + + -- HDL Embedded Text Block 3 eb3 + spadAddress <= spadInstrAddress when spadIndexedSel = '0' else spadRegAddress; + + -- HDL Embedded Text Block 4 eb4 + -- pragma translate_off + + process(instruction) + + constant bitsPerHexDigit : positive := 4; + + function pad(inString : string; outLength : positive) return string is + variable outString : string(1 to outLength); + begin + outString := (others => ' '); + outString(inString'range) := inString; + return outString; + end function pad; + + function hexDigitNb(bitNb : positive) return positive is + begin + return (bitNb-1)/bitsPerHexDigit+1; + end function hexDigitNb; + + function to01(nineValued : unsigned) return unsigned is + variable twoValued : unsigned(nineValued'range); + begin + twoValued := (others => '0'); + for index in nineValued'range loop + if (nineValued(index) = '1') or (nineValued(index) = 'H') then + twoValued(index) := '1'; + end if; + end loop; + return twoValued; + end function to01; + + variable opCode : unsigned(1+opCodeBitNb-1 downto 0); + variable destRegister : unsigned(registerAddressBitNb-1 downto 0); + variable destRegisterString : string(1 to 1+hexDigitNb(registerAddressBitNb)); + variable sourceRegister : unsigned(registerAddressBitNb-1 downto 0); + variable sourceRegisterString : string(1 to 1+hexDigitNb(registerAddressBitNb)); + variable sourceConstant : unsigned(registerBitNb-1 downto 0); + variable sourceConstantString : string(1 to hexDigitNb(registerBitNb)); + variable branchAddress : unsigned(programCounterBitNb-1 downto 0); + variable branchAddressString : string(1 to hexDigitNb(programCounterBitNb)); + variable branchKind : unsigned(1 downto 0); + variable shRotCin : unsigned(2 downto 0); + variable shRotDir: std_ulogic; + + function toHexDigit(binary : unsigned(bitsPerHexDigit-1 downto 0)) return character is + begin + if binary <= 9 then + return character'val(character'pos('0') + to_integer(to01(binary))); + else + return character'val(character'pos('A') + to_integer(to01(binary)) - 10); + end if; + end function toHexDigit; + + function toHexString(binary : unsigned) return string is + variable hexString : string(1 to hexDigitNb(binary'length)); + begin + for index in hexString'high-1 downto 0 loop + hexString(hexString'high-index) := toHexDigit( + resize(shift_right(binary, bitsPerHexDigit*index), bitsPerHexDigit) + ); + end loop; + return hexString; + end function toHexString; + + begin + + opCode := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length), + opCode'length + ); + destRegister := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-destRegister'length), + destRegister'length + ); + destRegisterString := 's' & toHexDigit(destRegister); + sourceRegister := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-destRegister'length-sourceRegister'length), + sourceRegister'length + ); + sourceRegisterString := 's' & toHexDigit(sourceRegister); + sourceConstant := resize(unsigned(instruction), sourceConstant'length); + sourceConstantString := toHexString(sourceConstant); + branchKind := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-branchKind'length), + branchKind'length + ); + branchAddress := resize(unsigned(instruction), branchAddress'length); + branchAddressString := toHexString(branchAddress); + shRotCin := resize(shift_right(unsigned(instruction), 1), shRotCin'length); + shRotDir := instruction(0); + + case opCode is + when "000000" => instrString <= pad("LOAD " & destRegisterString & " " & sourceConstantString, instrString'length); + when "000001" => instrString <= pad("LOAD " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "000100" => instrString <= pad("INPUT " & destRegisterString & " " & sourceConstantString, instrString'length); + when "000101" => instrString <= pad("INPUT " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "000110" => instrString <= pad("FETCH " & destRegisterString & " " & sourceConstantString, instrString'length); + when "000111" => instrString <= pad("FETCH " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "001010" => instrString <= pad("AND " & destRegisterString & " " & sourceConstantString, instrString'length); + when "001011" => instrString <= pad("AND " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "001100" => instrString <= pad("OR " & destRegisterString & " " & sourceConstantString, instrString'length); + when "001101" => instrString <= pad("OR " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "001110" => instrString <= pad("XOR " & destRegisterString & " " & sourceConstantString, instrString'length); + when "001111" => instrString <= pad("XOR " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "010010" => instrString <= pad("TEST " & destRegisterString & " " & sourceConstantString, instrString'length); + when "010011" => instrString <= pad("TEST " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "010100" => instrString <= pad("COMP " & destRegisterString & " " & sourceConstantString, instrString'length); + when "010101" => instrString <= pad("COMP " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011000" => instrString <= pad("ADD " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011001" => instrString <= pad("ADD " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011010" => instrString <= pad("ADDCY " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011011" => instrString <= pad("ADDCY " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011100" => instrString <= pad("SUB " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011101" => instrString <= pad("SUB " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011110" => instrString <= pad("SUBCY " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011111" => instrString <= pad("SUBCY " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "100000" => + case shRotCin is + when "000" => instrString <= pad("SLA " & destRegisterString, instrString'length); + when "001" => instrString <= pad("RL " & destRegisterString, instrString'length); + when "010" => instrString <= pad("SLX " & destRegisterString, instrString'length); + when "011" => + case shRotDir is + when '0' => instrString <= pad("SL0 " & destRegisterString, instrString'length); + when '1' => instrString <= pad("SL1 " & destRegisterString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when "100" => instrString <= pad("SRA " & destRegisterString, instrString'length); + when "101" => instrString <= pad("SRX " & destRegisterString, instrString'length); + when "110" => instrString <= pad("RR " & destRegisterString, instrString'length); + when "111" => + case shRotDir is + when '0' => instrString <= pad("SR0 " & destRegisterString, instrString'length); + when '1' => instrString <= pad("SR1 " & destRegisterString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when others => instrString <= pad("--------", instrString'length); + end case; + when "101100" => instrString <= pad("OUTPUT " & destRegisterString & " " & sourceConstantString, instrString'length); + when "101101" => instrString <= pad("OUTPUT " & destRegisterString & " (" & sourceRegisterString & ")", instrString'length); + when "101110" => instrString <= pad("STORE " & destRegisterString & " " & sourceConstantString, instrString'length); + when "101111" => instrString <= pad("STORE " & destRegisterString & " (" & sourceRegisterString & ")", instrString'length); + when "101010" => instrString <= pad("RET", instrString'length); + when "101011" => + case branchKind is + when "00" => instrString <= pad("RET Z", instrString'length); + when "01" => instrString <= pad("RET NZ", instrString'length); + when "10" => instrString <= pad("RET C", instrString'length); + when "11" => instrString <= pad("RET NC", instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when "110000" => instrString <= pad("CALL " & branchAddressString, instrString'length); + when "110001" => + case branchKind is + when "00" => instrString <= pad("CALL Z " & branchAddressString, instrString'length); + when "01" => instrString <= pad("CALL NZ " & branchAddressString, instrString'length); + when "10" => instrString <= pad("CALL C " & branchAddressString, instrString'length); + when "11" => instrString <= pad("CALL NC " & branchAddressString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when "110100" => instrString <= pad("JUMP " & branchAddressString, instrString'length); + when "110101" => + case branchKind is + when "00" => instrString <= pad("JUMP Z " & branchAddressString, instrString'length); + when "01" => instrString <= pad("JUMP NZ " & branchAddressString, instrString'length); + when "10" => instrString <= pad("JUMP C " & branchAddressString, instrString'length); + when "11" => instrString <= pad("JUMP NC " & branchAddressString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when others => instrString <= pad("--------", instrString'length); + end case; + + end process; + + -- pragma translate_on + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- Instance port mappings. + I_alu : aluAndRegs + GENERIC MAP ( + registerBitNb => registerBitNb, + registerAddressBitNb => registerAddressBitNb, + aluCodeBitNb => aluCodeBitNb, + portAddressBitNb => addressBitNb, + scratchpadAddressBitNb => scratchpadAddressBitNb + ) + PORT MAP ( + addrA => addrA, + addrB => addrB, + aluCode => aluCode, + cIn => cIn, + clock => clock, + instrData => instrData, + instrDataSel => instrDataSel, + portIn => portIn, + portInSel => portInSel, + regWrite => regWrite, + registerFileSel => registerFileSel, + reset => reset, + scratchpadSel => scratchpadSel, + spadIn => spadIn, + cOut => cOut, + portAddr => portRegAddress, + portOut => portOut, + scratchpadAddr => spadRegAddress, + spadOut => spadOut, + zero => zero + ); + I_BR : branchStack + GENERIC MAP ( + programCounterBitNb => programCounterBitNb, + stackPointerBitNb => stackPointerBitNb + ) + PORT MAP ( + clock => clock, + prevPC => prevPC, + progCounter => progCounter_internal, + reset => reset, + storePC => storePC, + storedProgCounter => storedProgCounter + ); + I_ctrl : controller + GENERIC MAP ( + intCodeBitNb => 5, + branchCondBitNb => branchCondBitNb, + opCodeBitNb => opCodeBitNb + ) + PORT MAP ( + branchCond => branchCond, + cOut => cOut, + clock => clock, + en => en, + int => int, + intCode => intCode, + opCode => opCode, + reset => reset, + twoRegInstr => twoRegInstr, + zero => zero, + cIn => cIn, + incPC => incPC, + instrDataSel => instrDataSel, + intAck => intAck, + loadInstrAddress => loadInstrAddress, + loadStoredPC => loadStoredPC, + portInSel => portInSel, + prevPC => prevPC, + readStrobe => readStrobe, + regWrite => regWrite, + registerFileSel => registerFileSel, + scratchpadSel => scratchpadSel, + scratchpadWrite => scratchpadWrite, + storePC => storePC, + writeStrobe => writeStrobe + ); + I_instr : instructionDecoder + GENERIC MAP ( + registerBitNb => registerBitNb, + registerAddressBitNb => registerAddressBitNb, + aluCodeBitNb => aluCodeBitNb, + instructionBitNb => instructionBitNb, + programCounterBitNb => programCounterBitNb, + opCodeBitNb => opCodeBitNb, + branchCondBitNb => branchCondBitNb, + intCodeBitNb => 5, + spadAddressBitNb => scratchpadAddressBitNb, + portAddressBitNb => addressBitNb + ) + PORT MAP ( + instruction => instruction, + addrA => addrA, + addrB => addrB, + aluCode => aluCode, + branchCond => branchCond, + instrAddress => instrAddress, + instrData => instrData, + intCode => intCode, + opCode => opCode, + portAddress => portInstrAddress, + portIndexedSel => portIndexedSel, + spadAddress => spadInstrAddress, + spadIndexedSel => spadIndexedSel, + twoRegInstr => twoRegInstr + ); + I_PC : programCounter + GENERIC MAP ( + programCounterBitNb => programCounterBitNb + ) + PORT MAP ( + clock => clock, + incPC => incPC, + instrAddress => instrAddress, + loadInstrAddress => loadInstrAddress, + loadStoredPC => loadStoredPC, + reset => reset, + storedProgCounter => storedProgCounter, + progCounter => progCounter_internal + ); + + g_scratchpad: IF scratchpadAddressBitNb > 0 GENERATE + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : scratchpad USE ENTITY NanoBlaze.scratchpad; + -- pragma synthesis_on + + BEGIN + I_sPad : scratchpad + GENERIC MAP ( + registerBitNb => registerBitNb, + spadAddressBitNb => scratchpadAddressBitNb + ) + PORT MAP ( + addr => spadAddress, + clock => clock, + dataIn => spadOut, + reset => reset, + write => scratchpadWrite, + dataOut => spadIn + ); + END GENERATE g_scratchpad; + + -- Implicit buffered output assignments + progCounter <= progCounter_internal; + +END struct; + + + + +-- +-- VHDL Architecture SystemOnChip.beamerSoc.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:02:29 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all; + +LIBRARY AhbLiteComponents; +LIBRARY NanoBlaze; +LIBRARY SystemOnChip; + +ARCHITECTURE struct OF beamerSoc IS + + -- Architecture declarations + constant programCounterBitNb: positive := 10; + constant instructionBitNb: positive := 26; + constant stackPointerBitNb: positive := 4; + constant registerAddressBitNb: positive := 4; + constant scratchpadAddressBitNb: natural := 0; + + constant signalBitNb: positive := 16; + constant updatePeriodBitNb : positive := 16; + + constant gpioIndex: positive := 1; + constant uartIndex: positive := gpioIndex+1; + constant beamerIndex: positive := uartIndex+1; + + constant ahbMemoryLocation : ahbMemoryLocationVector := ( + gpioIndex => ( + baseAddress => 16#0000#, + addressMask => 16#10000# - 16#0002# + ), + uartIndex => ( + baseAddress => 16#0010#, + addressMask => 16#10000# - 16#0004# + ), + beamerIndex => ( + baseAddress => 16#0020#, + addressMask => 16#10000# - 16#0004# + ), + others => ( + baseAddress => 16#FFFF#, + addressMask => 16#0000# + ) + ); + + -- Internal signal declarations + SIGNAL upEn : std_ulogic; + SIGNAL int : std_uLogic; + SIGNAL upAddress : unsigned(ahbAddressBitNb-1 DOWNTO 0); + SIGNAL upDataOut : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL upDataIn : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL upReadStrobe : std_uLogic; + SIGNAL upWriteStrobe : std_uLogic; + SIGNAL hAddr : unsigned(ahbAddressBitNb-1 DOWNTO 0); + SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0); + SIGNAL hSize : std_ulogic_vector(ahbSizeBitNb-1 DOWNTO 0); + SIGNAL hBurst : std_ulogic_vector(ahbBurstBitNb-1 DOWNTO 0); + SIGNAL hProt : std_ulogic_vector(ahbProtBitNb-1 DOWNTO 0); + SIGNAL hWrite : std_uLogic; + SIGNAL hReady : std_uLogic; + SIGNAL hMastLock : std_uLogic; + SIGNAL hResp : std_uLogic; + SIGNAL hClk : std_uLogic; + SIGNAL hReset_n : std_uLogic; + SIGNAL hSelV : std_ulogic_vector(1 TO ahbSlaveNb); + SIGNAL hRDataV : ahbDataVector; + SIGNAL hReadyV : std_logic_vector(1 TO ahbSlaveNb); + SIGNAL hRespV : std_logic_vector(1 TO ahbSlaveNb); + SIGNAL hSelGpio : std_uLogic; + SIGNAL hRespGpio : std_uLogic; + SIGNAL hReadyGpio : std_uLogic; + SIGNAL hRDataGpio : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hRDataBeamer : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hRDataUart : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hSelBeamer : std_uLogic; + SIGNAL hSelUart : std_uLogic; + SIGNAL hRespUart : std_uLogic; + SIGNAL hRespBeamer : std_uLogic; + SIGNAL hReadyBeamer : std_uLogic; + SIGNAL hReadyUart : std_uLogic; + SIGNAL intAck : std_ulogic; + SIGNAL instruction : std_ulogic_vector(instructionBitNb-1 DOWNTO 0); + SIGNAL programCounter : unsigned(programCounterBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT ahbDecoder + GENERIC ( + ahbMemoryLocation : ahbMemoryLocationVector + ); + PORT ( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hSel : OUT std_ulogic_vector (1 TO ahbSlaveNb) + ); + END COMPONENT; + COMPONENT ahbMasterInterface + PORT ( + clock : IN std_ulogic ; + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic ; + hResp : IN std_uLogic ; + pAddress : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + pDataOut : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + pReadStrobe : IN std_uLogic ; + pWriteStrobe : IN std_uLogic ; + reset : IN std_ulogic ; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hBurst : OUT std_ulogic_vector (ahbBurstBitNb-1 DOWNTO 0); + hClk : OUT std_uLogic ; + hMastLock : OUT std_uLogic ; + hProt : OUT std_ulogic_vector (ahbProtBitNb-1 DOWNTO 0); + hReset_n : OUT std_uLogic ; + hSize : OUT std_ulogic_vector (ahbSizeBitNb-1 DOWNTO 0); + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic ; + pDataIn : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT ahbMultiplexor + PORT ( + hRDataV : IN ahbDataVector ; + hReadyV : IN std_logic_vector (1 TO ahbSlaveNb); + hRespV : IN std_logic_vector (1 TO ahbSlaveNb); + hSel : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic + ); + END COMPONENT; + COMPONENT ahbMuxConnector + GENERIC ( + index : positive := 1 + ); + PORT ( + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic ; + hResp : IN std_uLogic ; + hSelV : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRDataV : OUT ahbDataVector ; + hReadyV : OUT std_logic_vector (1 TO ahbSlaveNb); + hRespV : OUT std_logic_vector (1 TO ahbSlaveNb); + hSel : OUT std_uLogic + ); + END COMPONENT; + COMPONENT ahbGpio + GENERIC ( + ioNb : positive := 8 + ); + PORT ( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic ; + hReset_n : IN std_uLogic ; + hSel : IN std_uLogic ; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic ; + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic ; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT ahbUart + GENERIC ( + txFifoDepth : positive := 8; + rxFifoDepth : positive := 1 + ); + PORT ( + RxD : IN std_ulogic ; + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic ; + hReset_n : IN std_uLogic ; + hSel : IN std_uLogic ; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic ; + TxD : OUT std_ulogic ; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic + ); + END COMPONENT; + COMPONENT nanoProcessor + GENERIC ( + addressBitNb : positive := 8; + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5; + instructionBitNb : positive := 18; + scratchpadAddressBitNb : natural := 4 + ); + PORT ( + clock : IN std_ulogic ; + dataIn : IN std_ulogic_vector (registerBitNb-1 DOWNTO 0); + en : IN std_ulogic ; + instruction : IN std_ulogic_vector (instructionBitNb-1 DOWNTO 0); + int : IN std_uLogic ; + reset : IN std_ulogic ; + dataAddress : OUT unsigned (addressBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (registerBitNb-1 DOWNTO 0); + intAck : OUT std_ulogic ; + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + readStrobe : OUT std_uLogic ; + writeStrobe : OUT std_uLogic + ); + END COMPONENT; + COMPONENT ahbBeamer + GENERIC ( + patternAddressBitNb : positive := 9; + testOutBitNb : positive := 16 + ); + PORT ( + outX : OUT std_ulogic ; + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + outY : OUT std_ulogic ; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + selSinCos : IN std_ulogic ; + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic ; + hSel : IN std_ulogic ; + hReady : OUT std_ulogic ; + hResp : OUT std_ulogic ; + hClk : IN std_ulogic ; + hReset_n : IN std_ulogic + ); + END COMPONENT; + COMPONENT programRom + GENERIC ( + addressBitNb : positive := 8; + dataBitNb : positive := 8 + ); + PORT ( + address : IN unsigned (addressBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + en : IN std_ulogic ; + reset : IN std_ulogic ; + dataOut : OUT std_ulogic_vector ( dataBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ahbBeamer USE ENTITY SystemOnChip.ahbBeamer; + FOR ALL : ahbDecoder USE ENTITY AhbLite.ahbDecoder; + FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio; + FOR ALL : ahbMasterInterface USE ENTITY AhbLite.ahbMasterInterface; + FOR ALL : ahbMultiplexor USE ENTITY AhbLite.ahbMultiplexor; + FOR ALL : ahbMuxConnector USE ENTITY AhbLite.ahbMuxConnector; + FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart; + FOR ALL : nanoProcessor USE ENTITY NanoBlaze.nanoProcessor; + FOR ALL : programRom USE ENTITY SystemOnChip.programRom; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + upEn <= '1'; + + + -- Instance port mappings. + I_dec : ahbDecoder + GENERIC MAP ( + ahbMemoryLocation => ahbMemoryLocation + ) + PORT MAP ( + hAddr => hAddr, + hSel => hSelV + ); + I_mst : ahbMasterInterface + PORT MAP ( + clock => clock, + hRData => hRData, + hReady => hReady, + hResp => hResp, + pAddress => upAddress, + pDataOut => upDataOut, + pReadStrobe => upReadStrobe, + pWriteStrobe => upWriteStrobe, + reset => reset, + hAddr => hAddr, + hBurst => hBurst, + hClk => hClk, + hMastLock => hMastLock, + hProt => hProt, + hReset_n => hReset_n, + hSize => hSize, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + pDataIn => upDataIn + ); + I_mux : ahbMultiplexor + PORT MAP ( + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelV, + hRData => hRData, + hReady => hReady, + hResp => hResp + ); + I_connBeam : ahbMuxConnector + GENERIC MAP ( + index => beamerIndex + ) + PORT MAP ( + hRData => hRDataBeamer, + hReady => hReadyBeamer, + hResp => hRespBeamer, + hSelV => hSelV, + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelBeamer + ); + I_connT : ahbMuxConnector + GENERIC MAP ( + index => gpioIndex + ) + PORT MAP ( + hRData => hRDataGpio, + hReady => hReadyGpio, + hResp => hRespGpio, + hSelV => hSelV, + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelGpio + ); + I_connUart : ahbMuxConnector + GENERIC MAP ( + index => uartIndex + ) + PORT MAP ( + hRData => hRDataUart, + hReady => hReadyUart, + hResp => hRespUart, + hSelV => hSelV, + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelUart + ); + I_GPIO : ahbGpio + GENERIC MAP ( + ioNb => ioNb + ) + PORT MAP ( + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSelGpio, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + ioIn => ioIn, + hRData => hRDataGpio, + hReady => hReadyGpio, + hResp => hRespGpio, + ioEn => ioEn, + ioOut => ioOut + ); + I_UART : ahbUart + GENERIC MAP ( + txFifoDepth => 8, + rxFifoDepth => 1 + ) + PORT MAP ( + RxD => RxD, + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSelUart, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + TxD => TxD, + hRData => hRDataUart, + hReady => hReadyUart, + hResp => hRespUart + ); + I_up : nanoProcessor + GENERIC MAP ( + addressBitNb => ahbAddressBitNb, + registerBitNb => ahbDataBitNb, + registerAddressBitNb => registerAddressBitNb, + programCounterBitNb => programCounterBitNb, + stackPointerBitNb => stackPointerBitNb, + instructionBitNb => instructionBitNb, + scratchpadAddressBitNb => scratchpadAddressBitNb + ) + PORT MAP ( + clock => clock, + dataIn => upDataIn, + en => upEn, + instruction => instruction, + int => int, + reset => reset, + dataAddress => upAddress, + dataOut => upDataOut, + intAck => intAck, + progCounter => programCounter, + readStrobe => upReadStrobe, + writeStrobe => upWriteStrobe + ); + I_beamer : ahbBeamer + GENERIC MAP ( + patternAddressBitNb => patternAddressBitNb, + testOutBitNb => testOutBitNb + ) + PORT MAP ( + outX => outX, + hAddr => hAddr, + outY => outY, + hWData => hWData, + selSinCos => selSinCos, + testOut => testOut, + hRData => hRDataBeamer, + hTrans => hTrans, + hWrite => hWrite, + hSel => hSelBeamer, + hReady => hReadyBeamer, + hResp => hRespBeamer, + hClk => hClk, + hReset_n => hReset_n + ); + I_rom : programRom + GENERIC MAP ( + addressBitNb => programCounterBitNb, + dataBitNb => instructionBitNb + ) + PORT MAP ( + address => programCounter, + clock => clock, + en => upEn, + reset => reset, + dataOut => instruction + ); + +END struct; + + + + +-- +-- VHDL Architecture Board.SoC_ebs3.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 10:21:25 08.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY Board; +LIBRARY Lattice; +LIBRARY SystemOnChip; + +ARCHITECTURE struct OF SoC_ebs3 IS + + -- Architecture declarations + constant ioNb: positive := 8; + constant testOutBitNb: positive := 16; + constant patternAddressBitNb: positive := 9; + + -- Internal signal declarations + SIGNAL clk_sys : std_ulogic; + SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0); + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_N : std_ulogic; + SIGNAL rxdSynch : std_ulogic; + SIGNAL selSinCos : std_ulogic; + SIGNAL selSinCosSynch : std_ulogic; + SIGNAL testOut : std_ulogic_vector(1 TO testOutBitNb); + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT beamerSoc + GENERIC ( + ioNb : positive := 8; + testOutBitNb : positive := 16; + patternAddressBitNb : positive := 9 + ); + PORT ( + TxD : OUT std_ulogic ; + RxD : IN std_ulogic ; + outX : OUT std_ulogic ; + outY : OUT std_ulogic ; + selSinCos : IN std_ulogic ; + reset : IN std_ulogic ; + clock : IN std_ulogic ; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + testOut : OUT std_ulogic_vector (1 TO testOutBitNb) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : DFF USE ENTITY Board.DFF; + FOR ALL : beamerSoc USE ENTITY SystemOnChip.beamerSoc; + FOR ALL : inverterIn USE ENTITY Board.inverterIn; + FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 3 eb3 + LED1 <= testOut(1); + LED2 <= testOut(2); + spare(testOut'range) <= testOut; + spare(testOut'high+1 to spare'high) <= (others => '0'); + + -- HDL Embedded Text Block 4 eb4 + logic1 <= '1'; + + -- HDL Embedded Text Block 5 eb5 + logic0 <= '0'; + + + -- Instance port mappings. + I8 : DFF + PORT MAP ( + CLK => clk_sys, + CLR => resetSynch, + D => RxD, + Q => rxdSynch + ); + I9 : DFF + PORT MAP ( + CLK => clk_sys, + CLR => resetSynch, + D => selSinCos, + Q => selSinCosSynch + ); + I12 : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSynch_N + ); + I2 : inverterIn + PORT MAP ( + in1 => reset_N, + out1 => reset + ); + I3 : inverterIn + PORT MAP ( + in1 => resetSynch_N, + out1 => resetSynch + ); + I7 : inverterIn + PORT MAP ( + in1 => selSinCos_n, + out1 => selSinCos + ); + I_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clk_sys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_top : beamerSoc + GENERIC MAP ( + ioNb => ioNb, + testOutBitNb => testOutBitNb, + patternAddressBitNb => patternAddressBitNb + ) + PORT MAP ( + TxD => TxD, + RxD => rxdSynch, + outX => xOut, + outY => yOut, + selSinCos => selSinCosSynch, + reset => resetSynch, + clock => clk_sys, + ioEn => OPEN, + ioOut => OPEN, + ioIn => ioIn, + testOut => testOut + ); + +END struct; + + + + diff --git a/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.lpf b/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.lpf new file mode 100644 index 0000000..ae65545 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.lpf @@ -0,0 +1,334 @@ +### For reference, see TN1262 / FPGA-TN-02032 +# .lpf file format is not really documented by Lattice, normally generated through Diamond + + +################ +#### sysCONFIG +################ + +# The BLOCK commands disable tracing of paths within clock domains (impacting overall timing score) +# It can also be used on paths if the TRACE should not consider the clock domain crossing +# like : BLOCK PATH FROM CLKNET "CLK_A" TO CLKNET "CLK_B" ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK JTAGPATHS ; +BLOCK RD_DURING_WR_PATHS ; + + +# Not comprehensive +# dflt : CONFIG_IOVOLTAGE 1.2, 1.5, 1.8, 2.5(dflt), 3.3 voltage is 3.3V +# dflt : COMPRESS_CONFIG OFF (dflt), ON no bitstream compression +# mod : MCCLK_FREQ 2.4, 4.8, 9.7, 19.4, 38.8, 62 NOR program read @ 62MHz +# mod : MASTER_SPI_PORT DISABLE (dflt), ENABLE master SPI port stays SPI and not GPIOs, other mods disabled by dflt +# dflt : BACKGROUND_RECONFIG - no soft ERC when hot-loading bitstream (due to cosmic rays) +# dflt : DONE_PULL ON (dflt), OFF IPU on DONE pin +# dflt : DONE_EX OFF (dflt), ON not delaying end of the configuration (used for daisy chaining FPGAs) +# mod : DONE_OD OFF (dflt), ON DONE pin as open-drain instead of push-pull +# dflt : CONFIG_SECURE OFF (dflt), ON allows external access to current program +# mod : CONFIG_MODE JTAG (dflt), SSPI, SPI_SERIAL, SPI_DUAL, SPI_QUAD, SLAVE_PARALLEL, SLAVE_SERIAL +# which bus and mode is used to load configuration (for the Lattic IDE) +# dflt : TRANSFR OFF (dflt), ON if using TransFR tool from Lattice +# dflt : WAKE_UP 4 (set DONE=1 before starting user code, dflt for DONE_EX=ON) +# 21 (set DONE=1 once FPGA is already running user code, dflt for DONE_EX=OFF) +# mod : INBUF ON, OFF disable unused input buffers (not sure it impacts the ECP5 family) +SYSCONFIG MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE DONE_OD=ON CONFIG_MODE=SPI_QUAD INBUF=OFF CONFIG_IOVOLTAGE=3.3 ; +IOBUF ALLPORTS IO_TYPE=LVCMOS33 ; + +################ +#### Labs DB +################ + +### Clock and reset ### +#INPUT_SETUP ALLPORTS 50.000000 ns HOLD 10.000000 ns CLKPORT "CLK" ; +#INPUT_SETUP PORT "nRST" 50.000000 ns CLKPORT "CLK" ; + +FREQUENCY PORT "clock" 100.000000 MHz ; +LOCATE COMP "clock" SITE "K16" ; +IOBUF PORT "clock" PULLMODE=NONE ; + +LOCATE COMP "reset_n" SITE "E13" ; +GSR_NET NET "resetSynch_n"; + + +### LEDs ### +LOCATE COMP "LED1" SITE "T14" ;# red +LOCATE COMP "LED2" SITE "R14" ;# green +LOCATE COMP "LED3" SITE "T15" ;# blue + + +################ +#### SODIMM-200 +################ + +### PP2 ### +LOCATE COMP "xOut" SITE "G3" ; +LOCATE COMP "yOut" SITE "E1" ; +LOCATE COMP "ampOut" SITE "F3" ; +#LOCATE COMP "" SITE "D1" ; +#LOCATE COMP "" SITE "F4" ; +#LOCATE COMP "" SITE "C1" ; +LOCATE COMP "morseIn" SITE "D7" ; +#LOCATE COMP "" SITE "B6" ; +LOCATE COMP "morseEnvelope" SITE "C7" ; +#LOCATE COMP "" SITE "A6" ; # PP2 11 +#LOCATE COMP "" SITE "D8" ; # PP2 13 +#LOCATE COMP "" SITE "B7" ; # PP2 15 +#LOCATE COMP "" SITE "C8" ; # PP2 17 +#LOCATE COMP "" SITE "A7" ; # PP2 19 +#LOCATE COMP "" SITE "E9" ; # PP2 21 +LOCATE COMP "RxD_synch" SITE "A8" ; # PP2 23 +LOCATE COMP "morseOut" SITE "D9" ; # PP2 25 + + +### PP1 ### +#LOCATE COMP "" SITE "A9" ; +#LOCATE COMP "" SITE "D10" ; +#LOCATE COMP "" SITE "A10" ; +#LOCATE COMP "" SITE "C10" ; +#LOCATE COMP "" SITE "B10" ; +#LOCATE COMP "" SITE "C12" ; +#LOCATE COMP "" SITE "B12" ; +#LOCATE COMP "" SITE "D13" ; +#LOCATE COMP "" SITE "A13" ; +#LOCATE COMP "" SITE "M5" ; # PP1 11 +#LOCATE COMP "" SITE "L5" ; # PP1 13 +#LOCATE COMP "" SITE "K5" ; # PP1 15 +#LOCATE COMP "" SITE "H5" ; # PP1 17 +#LOCATE COMP "" SITE "E8" ; # PP1 19 +#LOCATE COMP "" SITE "E5" ; # PP1 21 +LOCATE COMP "selSinCos_n" SITE "E6" ; # PP1 23 +#LOCATE COMP "" SITE "E7" ; # PP1 25 + + +### USB (FTDI2232HL located on the daughterboard) ### +LOCATE COMP "TxD" SITE "A14" ; +IOBUF PORT "TxD" SLEWRATE=FAST ; +LOCATE COMP "RxD" SITE "B14" ; +IOBUF PORT "RxD" PULLMODE=UP ; +#LOCATE COMP "USB_DB_RTS" SITE "B13" ; +#IOBUF PORT "USB_DB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_DB_CTS" SITE "C13" ; +#IOBUF PORT "USB_DB_CTS" PULLMODE=UP ; + + + +################ +#### Extras +################ + + +### SD Flash (External SD card) ### +#LOCATE COMP "SD_DETECT" SITE "G12" ; +#IOBUF PORT "SD_DETECT" PULLMODE=UP ; + +#LOCATE COMP "SD_CMD" SITE "C15" ; +#IOBUF PORT "SD_CMD" SLEWRATE=FAST ; +#LOCATE COMP "SD_CLK" SITE "B15" ; +#IOBUF PORT "SD_CLK" SLEWRATE=FAST ; + +#LOCATE COMP "SD_DTA[0]" SITE "B16" ; +##IOBUF PORT "SD_DTA[0]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[1]" SITE "C16" ; +##IOBUF PORT "SD_DTA[1]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[2]" SITE "F12" ; +##IOBUF PORT "SD_DTA[2]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[3]" SITE "C14" ; +##IOBUF PORT "SD_DTA[3]" SLEWRATE=FAST ; + + +### DRAM ### +#LOCATE COMP "DRAM_ADDR[0]" SITE "J15" ; +#IOBUF PORT "DRAM_ADDR[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[1]" SITE "L16" ; +#IOBUF PORT "DRAM_ADDR[1]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[2]" SITE "L15" ; +#IOBUF PORT "DRAM_ADDR[2]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[3]" SITE "K15" ; +#IOBUF PORT "DRAM_ADDR[3]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[4]" SITE "G15" ; +#IOBUF PORT "DRAM_ADDR[4]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[5]" SITE "F15" ; +#IOBUF PORT "DRAM_ADDR[5]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[6]" SITE "F16" ; +#IOBUF PORT "DRAM_ADDR[6]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[7]" SITE "E16" ; +#IOBUF PORT "DRAM_ADDR[7]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[8]" SITE "E15" ; +#IOBUF PORT "DRAM_ADDR[8]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[9]" SITE "G13" ; +#IOBUF PORT "DRAM_ADDR[9]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[10]" SITE "M16" ; +#IOBUF PORT "DRAM_ADDR[10]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[11]" SITE "F13" ; +#IOBUF PORT "DRAM_ADDR[11]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[12]" SITE "D16" ; +#IOBUF PORT "DRAM_ADDR[12]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_BA[0]" SITE "L14" ; +#IOBUF PORT "DRAM_BA[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_BA[1]" SITE "L13" ; +#IOBUF PORT "DRAM_BA[1]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_CLK" SITE "G14" ; +#IOBUF PORT "DRAM_CLK" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_CKE" SITE "G16" ; +#IOBUF PORT "DRAM_CKE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nRAS" SITE "M14" ; +#IOBUF PORT "DRAM_nRAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCAS" SITE "K13" ; +#IOBUF PORT "DRAM_nCAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nWE" SITE "N16" ; +#IOBUF PORT "DRAM_nWE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCS" SITE "M15" ; + +#LOCATE COMP "DRAM_DQ[0]" SITE "P14" ; +#LOCATE COMP "DRAM_DQ[1]" SITE "R15" ; +#LOCATE COMP "DRAM_DQ[2]" SITE "N14" ; +#LOCATE COMP "DRAM_DQ[3]" SITE "R16" ; +#LOCATE COMP "DRAM_DQ[4]" SITE "J14" ; +#LOCATE COMP "DRAM_DQ[5]" SITE "P15" ; +#LOCATE COMP "DRAM_DQ[6]" SITE "K14" ; +#LOCATE COMP "DRAM_DQ[7]" SITE "P16" ; +#LOCATE COMP "DRAM_DQ[8]" SITE "D14" ; +#LOCATE COMP "DRAM_DQ[9]" SITE "H14" ; +#LOCATE COMP "DRAM_DQ[10]" SITE "H12" ; +#LOCATE COMP "DRAM_DQ[11]" SITE "H13" ; +#LOCATE COMP "DRAM_DQ[12]" SITE "E14" ; +#LOCATE COMP "DRAM_DQ[13]" SITE "H15" ; +#LOCATE COMP "DRAM_DQ[14]" SITE "J13" ; +#LOCATE COMP "DRAM_DQ[15]" SITE "J16" ; + +#LOCATE COMP "DRAM_DQM[0]" SITE "M13" ; +#IOBUF PORT "DRAM_DQM[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_DQM[1]" SITE "F14" ; +#IOBUF PORT "DRAM_DQM[1]" SLEWRATE=FAST ; + + + + +### USB (chip located on the motherboard) ### +#LOCATE COMP "USB_MB_TX" SITE "M11" ; +#IOBUF PORT "USB_MB_TX" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_RX" SITE "N12" ; +#IOBUF PORT "USB_MB_RX" PULLMODE=UP ; +#LOCATE COMP "USB_MB_RTS" SITE "N11" ; +#IOBUF PORT "USB_MB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_CTS" SITE "M12" ; +#IOBUF PORT "USB_MB_CTS" PULLMODE=UP ; + + +### PMOD1 ### +#LOCATE COMP "dbg_leds[16]" SITE "P1" ; +#LOCATE COMP "dbg_leds[17]" SITE "N4" ; +#LOCATE COMP "dbg_leds[18]" SITE "P2" ; +#LOCATE COMP "dbg_leds[19]" SITE "P5" ; +#LOCATE COMP "dbg_leds[20]" SITE "R1" ; +#LOCATE COMP "dbg_leds[21]" SITE "N5" ; +#LOCATE COMP "dbg_leds[22]" SITE "R2" ; +#LOCATE COMP "dbg_leds[23]" SITE "N6" ; + + +### PMOD2 ### +#LOCATE COMP "dbg_leds[24]" SITE "R3" ; +#LOCATE COMP "dbg_leds[25]" SITE "P11" ; +#LOCATE COMP "dbg_leds[26]" SITE "P12" ; +#LOCATE COMP "dbg_leds[27]" SITE "T3" ; +#LOCATE COMP "dbg_leds[28]" SITE "R4" ; +#LOCATE COMP "dbg_leds[29]" SITE "R12" ; +#LOCATE COMP "dbg_leds[30]" SITE "T13" ; +#LOCATE COMP "dbg_leds[31]" SITE "R5" ; + + +### PMOD3 ### +#LOCATE COMP "dbg_leds[8]" SITE "B2" ; +#LOCATE COMP "dbg_leds[9]" SITE "B3" ; +#LOCATE COMP "dbg_leds[10]" SITE "A4" ; +#LOCATE COMP "dbg_leds[11]" SITE "D4" ; +#LOCATE COMP "dbg_leds[12]" SITE "A2" ; +#LOCATE COMP "dbg_leds[13]" SITE "B4" ; +#LOCATE COMP "dbg_leds[14]" SITE "C3" ; +#LOCATE COMP "dbg_leds[15]" SITE "C4" ; + + +### PMOD4 ### +#LOCATE COMP "dbg_leds[0]" SITE "J4" ; +#LOCATE COMP "dbg_leds[1]" SITE "J5" ; +#LOCATE COMP "dbg_leds[2]" SITE "H4" ; +#LOCATE COMP "dbg_leds[3]" SITE "E4" ; +#LOCATE COMP "dbg_leds[4]" SITE "J3" ; +#LOCATE COMP "dbg_leds[5]" SITE "H3" ; +#LOCATE COMP "dbg_leds[6]" SITE "E3" ; +#LOCATE COMP "dbg_leds[7]" SITE "D3" ; + + +### Ethernet ### +#LOCATE COMP "ETH_CLK_EN" SITE "B1" ; +#LOCATE COMP "ETH_nRESET" SITE "C2" ; + +#LOCATE COMP "ETH_nLED_Y" SITE "F1" ; +#LOCATE COMP "ETH_nLED_G" SITE "G2" ; + +#LOCATE COMP "ETH_MDC" SITE "J1" ; +#LOCATE COMP "ETH_MDIO" SITE "H2" ; +#IOBUF PORT "ETH_MDIO" OPENDRAIN=ON SLEWRATE=FAST ; +#LOCATE COMP "ETH_MDINT" SITE "G1" ; +#IOBUF PORT "ETH_MDINT" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_REF_CLK" SITE "P3" ; + +#LOCATE COMP "ETH_TX_CLK" SITE "M4" ; +#IOBUF PORT "ETH_TX_CLK" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TX_CTL" SITE "N3" ; +#IOBUF PORT "ETH_TX_CTL" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[0]" SITE "M3" ; +#IOBUF PORT "ETH_TXD[0]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[1]" SITE "L4" ; +#IOBUF PORT "ETH_TXD[1]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[2]" SITE "K4" ; +#IOBUF PORT "ETH_TXD[2]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[3]" SITE "K3" ; +#IOBUF PORT "ETH_TXD[3]" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_RX_CLK" SITE "K1" ; +#LOCATE COMP "ETH_RX_CTL" SITE "K2" ; +#LOCATE COMP "ETH_RXD[0]" SITE "L1" ; +#LOCATE COMP "ETH_RXD[1]" SITE "L2" ; +#LOCATE COMP "ETH_RXD[2]" SITE "M1" ; +#LOCATE COMP "ETH_RXD[3]" SITE "M2" ; + + +### Extras ### +#LOCATE COMP "EXT[1]" SITE "P13" ; +#LOCATE COMP "EXT[2]" SITE "R13" ; +#LOCATE COMP "EXT[3]" SITE "A3" ; +#LOCATE COMP "EXT[4]" SITE "A5" ; +#LOCATE COMP "EXT[5]" SITE "B5" ; +#LOCATE COMP "EXT[6]" SITE "C5" ; +#LOCATE COMP "EXT[7]" SITE "C6" ; +#LOCATE COMP "EXT[8]" SITE "D5" ; +#LOCATE COMP "EXT[9]" SITE "D6" ; +#LOCATE COMP "EXT[10]" SITE "A11" ; +#LOCATE COMP "EXT[11]" SITE "A12" ; +#LOCATE COMP "EXT[12]" SITE "B8" ; +#LOCATE COMP "EXT[13]" SITE "B9" ; +#LOCATE COMP "EXT[14]" SITE "B11" ; +#LOCATE COMP "EXT[15]" SITE "C9" ; +#LOCATE COMP "EXT[16]" SITE "C11" ; +#LOCATE COMP "EXT[17]" SITE "D11" ; +#LOCATE COMP "EXT[18]" SITE "D12" ; +#LOCATE COMP "EXT[19]" SITE "E10" ; +#LOCATE COMP "EXT[20]" SITE "E11" ; +#LOCATE COMP "EXT[21]" SITE "E12" ; +#LOCATE COMP "EXT[22]" SITE "L3" ; +#LOCATE COMP "EXT[23]" SITE "M6" ; +#LOCATE COMP "EXT[24]" SITE "N1" ; +#LOCATE COMP "EXT[25]" SITE "P4" ; +#LOCATE COMP "EXT[26]" SITE "P6" ; +#LOCATE COMP "EXT[27]" SITE "T2" ; +#LOCATE COMP "EXT[28]" SITE "T4" ; +#LOCATE COMP "EXT[29]" SITE "E2" ; +#LOCATE COMP "EXT[30]" SITE "F2" ; +#LOCATE COMP "EXT[31]" SITE "F5" ; +#LOCATE COMP "EXT[32]" SITE "G4" ; +#LOCATE COMP "EXT[33]" SITE "G5" ; +#LOCATE COMP "EXT[34]" SITE "J2" ; diff --git a/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.ucf b/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.ucf new file mode 100644 index 0000000..dae497e --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.ucf @@ -0,0 +1,57 @@ +#------------------------------------------------------------------------------- +# Clock and reset +# +NET "reset_n" LOC = "D3" | PULLUP; +NET "clock" LOC = "A10"; + +#------------------------------------------------------------------------------- +# Buttons & LEDs +# +NET "selSinCos_n" LOC = "A15" | PULLUP; +#NET "button2_n" LOC = "D3" | PULLUP; +NET "LED1" LOC = "B16"; +NET "LED2" LOC = "A16"; + +#------------------------------------------------------------------------------- +# Sigma-delta outputs +# +#NET "xOut" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; +#NET "yOut" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; +NET "xOut" LOC = "G4" ; +NET "yOut" LOC = "G5" ; + +#------------------------------------------------------------------------------- +# Serial ports, Rx, Tx defined with FPGA as master +# +NET "rxd0" LOC = "V2" ; # female DB9 on J9 +NET "txd0" LOC = "T1" ; +#NET "rxd1" LOC = "U1" ; # male DB9 on J10 +#NET "txd1" LOC = "P1" ; + +#------------------------------------------------------------------------------- +# Debug +# +NET "spare<1>" LOC = "F8" ; +NET "spare<2>" LOC = "F7" ; +NET "spare<3>" LOC = "F9" ; +NET "spare<4>" LOC = "G9" ; +NET "spare<5>" LOC = "E8" ; +NET "spare<6>" LOC = "E7" ; +NET "spare<7>" LOC = "B14"; +NET "spare<8>" LOC = "B13"; +NET "spare<9>" LOC = "B11"; +NET "spare<10>" LOC = "A8" ; +NET "spare<11>" LOC = "C7" ; +NET "spare<12>" LOC = "A14"; +NET "spare<13>" LOC = "A11"; +NET "spare<14>" LOC = "A13"; +NET "spare<15>" LOC = "D7" ; +NET "spare<16>" LOC = "E9" ; +NET "spare<17>" LOC = "F11"; + + +#------------------------------------------------------------------------------- +# Globals +# +#NET "*" IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +NET "*" IOSTANDARD = LVCMOS33; diff --git a/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.vhd b/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.vhd new file mode 100644 index 0000000..75eb9c5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/concat/systemOnChip.vhd @@ -0,0 +1,6031 @@ +-- VHDL Entity Board.SoC_ebs3.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 10:21:25 08.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY SoC_ebs3 IS + PORT( + RxD : IN std_ulogic; + clock : IN std_ulogic; + reset_N : IN std_ulogic; + selSinCos_n : IN std_ulogic; + LED1 : OUT std_ulogic; + LED2 : OUT std_ulogic; + TxD : OUT std_ulogic; + spare : OUT std_ulogic_vector (1 TO 17); + xOut : OUT std_ulogic; + yOut : OUT std_ulogic + ); + +-- Declarations + +END SoC_ebs3 ; + + + + + +-- VHDL Entity Board.DFF.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:05 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY DFF IS + PORT( + CLK : IN std_uLogic; + CLR : IN std_uLogic; + D : IN std_uLogic; + Q : OUT std_uLogic + ); + +-- Declarations + +END DFF ; + + + + + +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Board.inverterIn.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY inverterIn IS + PORT( + in1 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END inverterIn ; + + + + + +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- VHDL Entity SystemOnChip.beamerSoc.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY beamerSoc IS + GENERIC( + ioNb : positive := 8; + testOutBitNb : positive := 16; + patternAddressBitNb : positive := 9 + ); + PORT( + TxD : OUT std_ulogic; + RxD : IN std_ulogic; + outX : OUT std_ulogic; + outY : OUT std_ulogic; + selSinCos : IN std_ulogic; + reset : IN std_ulogic; + clock : IN std_ulogic; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + testOut : OUT std_ulogic_vector (1 TO testOutBitNb) + ); + +-- Declarations + +END beamerSoc ; + + + + + +LIBRARY ieee; + USE ieee.std_logic_1164.all; + +PACKAGE ahbLite IS + ------------------------------------------------------------------------------ + -- bus components sizes + constant ahbAddressBitNb : positive := 16; + constant ahbDataBitNb : positive := 16; + constant ahbSlaveNb : positive := 16; + + constant ahbTransBitNb : positive := 2; + constant ahbSizeBitNb : positive := 1; + constant ahbBurstBitNb : positive := 3; + constant ahbProtBitNb : positive := 4; + + ------------------------------------------------------------------------------ + -- bus data vector type + subtype ahbDataType is std_logic_vector(ahbDataBitNb-1 downto 0); + type ahbDataVector is array(1 to ahbSlaveNb) of ahbDataType; + + ------------------------------------------------------------------------------ + -- address decoder + type ahbMemoryLocationType is + record + baseAddress: natural; + addressMask: natural; + end record; + type ahbMemoryLocationVector is array(1 to ahbSlaveNb) of ahbMemoryLocationType; + + ------------------------------------------------------------------------------ + -- bus signals + subtype transferType is std_ulogic_vector(ahbTransBitNb-1 downto 0); + constant transIdle : transferType := "00"; + constant transBusy : transferType := "01"; + constant transNonSeq: transferType := "10"; + constant transSeq : transferType := "11"; + + subtype transferSizeType is std_ulogic_vector(ahbSizeBitNb-1 downto 0); + constant size8 : transferSizeType := "0"; + constant size16 : transferSizeType := "1"; + + subtype burstType is std_ulogic_vector(ahbBurstBitNb-1 downto 0); + constant burstSingle : burstType := "000"; + constant burstIncr : burstType := "001"; + constant burstWrap4 : burstType := "010"; + constant burstIncr4 : burstType := "011"; + constant burstWrap8 : burstType := "100"; + constant burstIncr8 : burstType := "101"; + constant burstWrap16 : burstType := "110"; + constant burstIncr16 : burstType := "111"; + + subtype protectionType is std_ulogic_vector(ahbProtBitNb-1 downto 0); + constant protDefault : protectionType := "0011"; + + ------------------------------------------------------------------------------ + -- log2 + function addressBitNb (addressNb : natural) return natural; + +END ahbLite; + + + + +PACKAGE BODY ahbLite IS + + function addressBitNb (addressNb : natural) return natural is + variable powerOfTwo, bitNb : natural; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo <= addressNb loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end addressBitNb; + +END ahbLite; + + + + +-- VHDL Entity SystemOnChip.ahbBeamer.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:22 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbBeamer IS + GENERIC( + patternAddressBitNb : positive := 9; + testOutBitNb : positive := 16 + ); + PORT( + outX : OUT std_ulogic; + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + outY : OUT std_ulogic; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + selSinCos : IN std_ulogic; + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic; + hSel : IN std_ulogic; + hReady : OUT std_ulogic; + hResp : OUT std_ulogic; + hClk : IN std_ulogic; + hReset_n : IN std_ulogic + ); + +-- Declarations + +END ahbBeamer ; + + + + + +-- VHDL Entity SystemOnChip.ahbBeamerOperator.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:21 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ahbBeamerOperator IS + GENERIC( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16 + ); + PORT( + outX : OUT std_ulogic; + run : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + outY : OUT std_ulogic; + selSinCos : IN std_ulogic; + interpolateLin : IN std_ulogic; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + memX : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + newPolynom : OUT std_ulogic + ); + +-- Declarations + +END ahbBeamerOperator ; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:20 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCoefficients IS + GENERIC( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + +-- Declarations + +END interpolatorCoefficients ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCoefficients IS +BEGIN + + calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4) + begin + if interpolateLinear = '1' then + a <= (others => '0'); + b <= (others => '0'); + c <= resize(2*sample3, c'length) + - resize(2*sample2, c'length); + d <= resize( sample2, d'length); + else + a <= resize( sample4, a'length) + - resize(3*sample3, a'length) + + resize(3*sample2, a'length) + - resize( sample1, a'length); + b <= resize(2*sample1, b'length) + - resize(5*sample2, b'length) + + resize(4*sample3, b'length) + - resize( sample4, b'length); + c <= resize( sample3, c'length) + - resize( sample1, c'length); + d <= resize( sample2, d'length); + end if; + end process calcCoeffs; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity DigitalToAnalogConverter.DAC.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:06:08 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY DAC IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + serialOut : OUT std_ulogic; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END DAC ; + + + + + +ARCHITECTURE masterVersion OF DAC IS + + signal parallelIn1: unsigned(parallelIn'range); + signal integrator: unsigned(parallelIn'high+1 downto 0); + signal quantized: std_ulogic; + +BEGIN + +-- parallelIn1 <= parallelIn; + parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2); + + integrate: process(reset, clock) + begin + if reset = '1' then + integrator <= (others => '0'); + elsif rising_edge(clock) then + if quantized = '0' then + integrator <= integrator + parallelIn1; + else + integrator <= integrator + parallelIn1 - 2**parallelIn'length; + end if; + end if; + end process integrate; + + quantized <= integrator(integrator'high); + + serialOut <= quantized; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:32 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY offsetToUnsigned IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END offsetToUnsigned ; + + + + + +ARCHITECTURE masterVersion OF offsetToUnsigned IS + +BEGIN + + unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0)); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity WaveformGenerator.sawtoothGen.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:02:49 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sawtoothGen IS + GENERIC( + bitNb : positive := 16 + ); + PORT( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END sawtoothGen ; + + + + + +ARCHITECTURE masterVersion OF sawtoothGen IS + + signal counter: unsigned(sawtooth'range); + +begin + + count: process(reset, clock) + begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + counter <= counter + step; + end if; + end if; + end process count; + + sawtooth <= counter; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorCalculatePolynom IS + GENERIC( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + restartPolynom : IN std_ulogic; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorCalculatePolynom ; + + + + + +ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS + + constant additionalBitNb: positive := 1; + constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1 + + additionalBitNb; + signal x: signed(internalsBitNb-1 downto 0); + signal u: signed(internalsBitNb-1 downto 0); + signal v: signed(internalsBitNb-1 downto 0); + signal w: signed(internalsBitNb-1 downto 0); + +BEGIN + + iterativePolynom: process(reset, clock) + begin + if reset = '1' then + x <= (others => '0'); + u <= (others => '0'); + v <= (others => '0'); + w <= (others => '0'); + sampleOut <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if restartPolynom = '1' then + x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb); + u <= resize(a, u'length) + + shift_left(resize(b, u'length), oversamplingBitNb) + + shift_left(resize(c, u'length), 2*oversamplingBitNb); + v <= resize(6*a, v'length) + + shift_left(resize(2*b, v'length), oversamplingBitNb); + w <= resize(6*a, w'length); + sampleOut <= resize(d, sampleOut'length); + else + x <= x + u; + u <= u + v; + v <= v + w; + sampleOut <= resize( + shift_right(x, 3*oversamplingBitNb+1), sampleOut'length + ); + -- limit overflow + if x(x'high downto x'high-additionalBitNb) = "01" then + sampleOut <= not shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + -- limit underflow + if x(x'high downto x'high-additionalBitNb) = "10" then + sampleOut <= shift_left( + resize("10", sampleOut'length), sampleOut'length-2 + ); + end if; + end if; + end if; + end if; + end process iterativePolynom; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SystemOnChip.sinCosTable.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY sinCosTable IS + GENERIC( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0); + cosine : OUT signed (outputBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END sinCosTable ; + + + + + +ARCHITECTURE masterVersion OF sinCosTable IS + + signal changeSignSine : std_uLogic; + signal changeSignCosine : std_uLogic; + signal flipPhase : std_uLogic; + signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0); + signal phaseTableAddress2 : unsigned(phaseTableAddress1'range); + signal quarterSine : signed(sine'range); + signal quarterCosine : signed(cosine'range); + +BEGIN + + changeSignSine <= phase(phase'high); + changeSignCosine <= phase(phase'high) xor phase(phase'high-1); + flipPhase <= phase(phase'high-1); + + phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1); + + checkPhase: process(flipPhase, phaseTableAddress1) + begin + if flipPhase = '0' then + phaseTableAddress2 <= phaseTableAddress1; + else + phaseTableAddress2 <= 0 - phaseTableAddress1; + end if; + end process checkPhase; + + + quarterTableSine: process(phaseTableAddress2, flipPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if flipPhase = '0' then + quarterSine <= to_signed(16#0000#, quarterSine'length); + else + quarterSine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length); + when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length); + when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length); + when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length); + when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length); + when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterSine <= (others => '-'); + end case; + end process quarterTableSine; + + + quarterTableCosine: process(phaseTableAddress2, flipPhase) + begin + case to_integer(phaseTableAddress2) is + when 0 => if flipPhase = '1' then + quarterCosine <= to_signed(16#0000#, quarterSine'length); + else + quarterCosine <= to_signed(16#7FFF#, quarterSine'length); + end if; + when 7 => quarterCosine <= to_signed(16#18F9#, quarterSine'length); + when 6 => quarterCosine <= to_signed(16#30FB#, quarterSine'length); + when 5 => quarterCosine <= to_signed(16#471C#, quarterSine'length); + when 4 => quarterCosine <= to_signed(16#5A82#, quarterSine'length); + when 3 => quarterCosine <= to_signed(16#6A6D#, quarterSine'length); + when 2 => quarterCosine <= to_signed(16#7641#, quarterSine'length); + when 1 => quarterCosine <= to_signed(16#7D89#, quarterSine'length); + when others => quarterCosine <= (others => '-'); + end case; + end process quarterTableCosine; + + + checkSignSine: process(changeSignSine, quarterSine) + begin + if changeSignSine = '0' then + sine <= quarterSine; + else + sine <= 0 - quarterSine; + end if; + end process checkSignSine; + + + checkSignCosine: process(changeSignCosine, quarterCosine) + begin + if changeSignCosine = '0' then + cosine <= quarterCosine; + else + cosine <= 0 - quarterCosine; + end if; + end process checkSignCosine; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SystemOnChip.periphSpeedController.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphSpeedController IS + GENERIC( + updatePeriodBitNb : positive := 16 + ); + PORT( + enableOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + enableIn : IN std_ulogic + ); + +-- Declarations + +END periphSpeedController ; + + + + + +ARCHITECTURE masterVersion OF periphSpeedController IS + + signal enableCounter: unsigned(updatePeriod'range); + signal endOfCount: std_uLogic; + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + enableCounter <= (others => '0'); + elsif rising_edge(clock) then + if (endOfCount = '0') and (enableIn = '1') then + enableCounter <= enableCounter - 1; + else + enableCounter <= updatePeriod; + end if; + end if; + end process count; + + testEndOfCount: process(enableCounter) + begin + if enableCounter = 0 then + endOfCount <= '1'; + else + endOfCount <= '0'; + end if; + end process testEndOfCount; + + enableOut <= endOfCount and enableIn; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:24 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorShiftRegister IS + GENERIC( + signalBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset : IN std_ulogic; + shiftSamples : IN std_ulogic; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END interpolatorShiftRegister ; + + + + + +ARCHITECTURE masterVersion OF interpolatorShiftRegister IS + + -- signal sample4_int: signed(sampleIn'range); + -- signal sample3_int: signed(sampleIn'range); + -- signal sample2_int: signed(sampleIn'range); + -- signal sample1_int: signed(sampleIn'range); + + type samplesArray is array(3 downto 0) of signed(sampleIn'range); + signal samples: samplesArray; + +begin + + shiftThem: process(reset, clock) + begin + if reset = '1' then + samples <= (others=>(others=>'0')); + -- sample1_int <= (others => '0'); + -- sample2_int <= (others => '0'); + -- sample3_int <= (others => '0'); + -- sample4_int <= (others => '0'); + elsif rising_edge(clock) then + if shiftSamples = '1' then + -- sample1_int <= sample2_int; + -- sample2_int <= sample3_int; + -- sample3_int <= sample4_int; + -- sample4_int <= sampleIn; + samples(0) <= samples(1); + samples(1) <= samples(2); + samples(2) <= samples(3); + samples(3) <= sampleIn; + end if; + end if; + end process shiftThem; + + sample4 <= samples(3); + sample3 <= samples(2); + sample2 <= samples(1); + sample1 <= samples(0); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:00:28 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY interpolatorTrigger IS + GENERIC( + counterBitNb : positive := 4 + ); + PORT( + triggerOut : OUT std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : IN std_ulogic + ); + +-- Declarations + +END interpolatorTrigger ; + + + + + +ARCHITECTURE masterVersion OF interpolatorTrigger IS + + signal triggerCounter: unsigned(counterBitNb-1 downto 0); + +BEGIN + + count: process(reset, clock) + begin + if reset = '1' then + triggerCounter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + triggerCounter <= triggerCounter + 1; + end if; + end if; + end process count; + + trig: process(triggerCounter, en) + begin + if triggerCounter = 0 then + triggerOut <= en; + else + triggerOut <= '0'; + end if; + end process trig; + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SystemOnChip.ahbBeamerOperator.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:01:08 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +-- LIBRARY DigitalToAnalogConverter; +-- LIBRARY SplineInterpolator; +-- LIBRARY SystemOnChip; +-- LIBRARY WaveformGenerator; + +ARCHITECTURE struct OF ahbBeamerOperator IS + + -- Architecture declarations + constant coeffBitNb : positive := signalBitNb+3+1; + constant sampleCountBitNb : positive := 8; + constant patternAddressBitNb : positive := 8; + -- sinewave generator + constant tableAddressBitNb : positive := 3; + constant phaseBitNb : positive := sampleCountBitNb + tableAddressBitNb + 2; + + -- Internal signal declarations + SIGNAL aX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL aY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL bX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL bY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL cX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL cY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL cosine : signed(signalBitNb-1 DOWNTO 0); + SIGNAL dX : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL dY : signed(coeffBitNb-1 DOWNTO 0); + SIGNAL interpolateLinear : std_ulogic; + SIGNAL interpolationEn : std_ulogic; + SIGNAL interpolationEnable : std_ulogic; + SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL sampleX : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleX4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY1 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY2 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY3 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sampleY4 : signed(signalBitNb-1 DOWNTO 0); + SIGNAL samplesX : signed(signalBitNb-1 DOWNTO 0); + SIGNAL samplesY : signed(signalBitNb-1 DOWNTO 0); + SIGNAL sine : signed(signalBitNb-1 DOWNTO 0); + SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0); + SIGNAL unsignedX : unsigned(signalBitNb-1 DOWNTO 0); + SIGNAL unsignedY : unsigned(signalBitNb-1 DOWNTO 0); + + -- Implicit buffer signal declarations + SIGNAL newPolynom_internal : std_ulogic; + + + -- Component Declarations + COMPONENT DAC + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + serialOut : OUT std_ulogic ; + parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCalculatePolynom + GENERIC ( + signalBitNb : positive := 16; + coeffBitNb : positive := 16; + oversamplingBitNb : positive := 8 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + restartPolynom : IN std_ulogic ; + d : IN signed (coeffBitNb-1 DOWNTO 0); + sampleOut : OUT signed (signalBitNb-1 DOWNTO 0); + c : IN signed (coeffBitNb-1 DOWNTO 0); + b : IN signed (coeffBitNb-1 DOWNTO 0); + a : IN signed (coeffBitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorCoefficients + GENERIC ( + bitNb : positive := 16; + coeffBitNb : positive := 16 + ); + PORT ( + sample1 : IN signed (bitNb-1 DOWNTO 0); + sample2 : IN signed (bitNb-1 DOWNTO 0); + sample3 : IN signed (bitNb-1 DOWNTO 0); + sample4 : IN signed (bitNb-1 DOWNTO 0); + a : OUT signed (coeffBitNb-1 DOWNTO 0); + b : OUT signed (coeffBitNb-1 DOWNTO 0); + c : OUT signed (coeffBitNb-1 DOWNTO 0); + d : OUT signed (coeffBitNb-1 DOWNTO 0); + interpolateLinear : IN std_ulogic + ); + END COMPONENT; + COMPONENT interpolatorShiftRegister + GENERIC ( + signalBitNb : positive := 16 + ); + PORT ( + clock : IN std_ulogic ; + reset : IN std_ulogic ; + shiftSamples : IN std_ulogic ; + sampleIn : IN signed (signalBitNb-1 DOWNTO 0); + sample1 : OUT signed (signalBitNb-1 DOWNTO 0); + sample2 : OUT signed (signalBitNb-1 DOWNTO 0); + sample3 : OUT signed (signalBitNb-1 DOWNTO 0); + sample4 : OUT signed (signalBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT interpolatorTrigger + GENERIC ( + counterBitNb : positive := 4 + ); + PORT ( + triggerOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : IN std_ulogic + ); + END COMPONENT; + COMPONENT offsetToUnsigned + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0); + signedIn : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT periphSpeedController + GENERIC ( + updatePeriodBitNb : positive := 16 + ); + PORT ( + enableOut : OUT std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + enableIn : IN std_ulogic + ); + END COMPONENT; + COMPONENT sinCosTable + GENERIC ( + inputBitNb : positive := 16; + outputBitNb : positive := 16; + tableAddressBitNb : positive := 3 + ); + PORT ( + sine : OUT signed (outputBitNb-1 DOWNTO 0); + phase : IN unsigned (inputBitNb-1 DOWNTO 0); + cosine : OUT signed (outputBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT sawtoothGen + GENERIC ( + bitNb : positive := 16 + ); + PORT ( + sawtooth : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic ; + step : IN unsigned (bitNb-1 DOWNTO 0); + en : IN std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC; +-- FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom; +-- FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients; +-- FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister; +-- FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger; +-- FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned; +-- FOR ALL : periphSpeedController USE ENTITY SystemOnChip.periphSpeedController; +-- FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen; +-- FOR ALL : sinCosTable USE ENTITY SystemOnChip.sinCosTable; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + samplesY <= sine when selSinCos = '1' + else signed(memY); + + -- HDL Embedded Text Block 2 eb2 + samplesX <= cosine when selSinCos = '1' + else signed(memX); + + -- HDL Embedded Text Block 4 eb4 + step <= to_unsigned(1, step'length); + + -- HDL Embedded Text Block 5 eb5 + interpolationEnable <= '1' when selSinCos = '1' + else interpolationEn; + interpolateLinear <= '0' when selSinCos = '1' + else interpolateLin; + --interpolateLinear <= interpolateLin; + + + -- Instance port mappings. + I_dacx : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => outX, + parallelIn => unsignedX, + clock => clock, + reset => reset + ); + I_dacy : DAC + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + serialOut => outY, + parallelIn => unsignedY, + clock => clock, + reset => reset + ); + I_polyx : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom_internal, + d => dX, + sampleOut => sampleX, + c => cX, + b => bX, + a => aX, + en => interpolationEnable + ); + I_polyy : interpolatorCalculatePolynom + GENERIC MAP ( + signalBitNb => signalBitNb, + coeffBitNb => coeffBitNb, + oversamplingBitNb => sampleCountBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + restartPolynom => newPolynom_internal, + d => dY, + sampleOut => sampleY, + c => cY, + b => bY, + a => aY, + en => interpolationEnable + ); + I_coeffx : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sampleX1, + sample2 => sampleX2, + sample3 => sampleX3, + sample4 => sampleX4, + a => aX, + b => bX, + c => cX, + d => dX, + interpolateLinear => interpolateLinear + ); + I_coeffy : interpolatorCoefficients + GENERIC MAP ( + bitNb => signalBitNb, + coeffBitNb => coeffBitNb + ) + PORT MAP ( + sample1 => sampleY1, + sample2 => sampleY2, + sample3 => sampleY3, + sample4 => sampleY4, + a => aY, + b => bY, + c => cY, + d => dY, + interpolateLinear => interpolateLinear + ); + I_srx : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom_internal, + sampleIn => samplesX, + sample1 => sampleX1, + sample2 => sampleX2, + sample3 => sampleX3, + sample4 => sampleX4 + ); + I_sry : interpolatorShiftRegister + GENERIC MAP ( + signalBitNb => signalBitNb + ) + PORT MAP ( + clock => clock, + reset => reset, + shiftSamples => newPolynom_internal, + sampleIn => samplesY, + sample1 => sampleY1, + sample2 => sampleY2, + sample3 => sampleY3, + sample4 => sampleY4 + ); + I_trig : interpolatorTrigger + GENERIC MAP ( + counterBitNb => sampleCountBitNb + ) + PORT MAP ( + triggerOut => newPolynom_internal, + clock => clock, + reset => reset, + en => interpolationEnable + ); + I_offsx : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => unsignedX, + signedIn => sampleX + ); + I_offsy : offsetToUnsigned + GENERIC MAP ( + bitNb => signalBitNb + ) + PORT MAP ( + unsignedOut => unsignedY, + signedIn => sampleY + ); + I_speed : periphSpeedController + GENERIC MAP ( + updatePeriodBitNb => updatePeriodBitNb + ) + PORT MAP ( + enableOut => interpolationEn, + clock => clock, + reset => reset, + updatePeriod => updatePeriod, + enableIn => run + ); + I_sin : sinCosTable + GENERIC MAP ( + inputBitNb => phaseBitNb, + outputBitNb => signalBitNb, + tableAddressBitNb => tableAddressBitNb + ) + PORT MAP ( + sine => sine, + phase => phase, + cosine => cosine + ); + I_phase : sawtoothGen + GENERIC MAP ( + bitNb => phaseBitNb + ) + PORT MAP ( + sawtooth => phase, + clock => clock, + reset => reset, + step => step, + en => interpolationEnable + ); + + -- Implicit buffered output assignments + newPolynom <= newPolynom_internal; + +END struct; + + + + +-- VHDL Entity SystemOnChip.ahbBeamerRegisters.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:21 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbBeamerRegisters IS + GENERIC( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16; + patternAddressBitNb : positive := 8; + testOutBitNb : positive := 16 + ); + PORT( + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + memX : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + run : OUT std_ulogic; + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + interpolateLin : OUT std_ulogic; + newPolynom : IN std_ulogic; + hClk : IN std_ulogic; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + hReset_n : IN std_ulogic; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic; + hSel : IN std_ulogic; + hReady : OUT std_ulogic; + hResp : OUT std_ulogic + ); + +-- Declarations + +END ahbBeamerRegisters ; + + + + + +-- VHDL Entity SystemOnChip.blockRAMAddressCounter.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY blockRAMAddressCounter IS + GENERIC( + addressBitNb : positive := 8 + ); + PORT( + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + updateMem : IN std_ulogic; + addr : OUT unsigned (addressBitNb-1 DOWNTO 0); + patternSize : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END blockRAMAddressCounter ; + + + + + +ARCHITECTURE masterVersion OF blockRAMAddressCounter IS + + signal updateMemDelayed : std_ulogic; + signal updateMemChanging : std_ulogic; + signal addressInt : unsigned(addr'range); + +BEGIN + + delay: process(reset, clock) + begin + if reset = '1' then + updateMemDelayed <= '0'; + elsif rising_edge(clock) then + updateMemDelayed <= updateMem; + end if; + end process delay; + + updateMemChanging <= '1' when (updateMem /= updateMemDelayed) + else '0'; + + count: process(reset, clock) + begin + if reset = '1' then + addressInt <= (others => '0'); + elsif rising_edge(clock) then + if updateMemChanging = '1' then + addressInt <= (others => '0'); + elsif en = '1' then + if updateMem = '1' then + addressInt <= addressInt + 1; + else + if addressInt < patternSize - 1 then + addressInt <= addressInt + 1; + else + addressInt <= (others => '0'); + end if; + end if; + end if; + end if; + end process count; + + addr <= addressInt; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SystemOnChip.periphControlReg.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphControlReg IS + GENERIC( + dataBitNb : positive := 16; + patternSizeBitNb : positive := 8 + ); + PORT( + run : OUT std_ulogic; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + updatePattern : OUT std_ulogic; + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + write : IN std_ulogic; + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + interpolateLinear : OUT std_ulogic; + patternSize : OUT unsigned (patternSizeBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END periphControlReg ; + + + + + +ARCHITECTURE masterVersion OF periphControlReg IS + + constant runId : natural := 0; + constant updatePatternId : natural := 1; + constant interpolateLinearId : natural := 2; + constant patternSizeHighId : natural := 15; + + signal runInt : std_ulogic; + signal updatePatternInt : std_ulogic; + signal interpolateLinearInt : std_ulogic; + signal patternSizeInt : std_ulogic_vector(patternSize'range); + + signal dataOutReg : std_ulogic_vector(dataOut'range); + +BEGIN + + store: process(reset, clock) + begin + if reset = '1' then + runInt <= '0'; + updatePatternInt <= '0'; + interpolateLinearInt <= '0'; + patternSizeInt <= (others => '0'); + elsif rising_edge(clock) then + if (en = '1') and (write = '1') then + runInt <= dataIn(runId); + updatePatternInt <= dataIn(updatePatternId); + interpolateLinearInt <= dataIn(interpolateLinearId); + patternSizeInt <= + dataIn(patternSizeHighId downto patternSizeHighId-patternSize'length+1); + end if; + end if; + end process store; + + run <= runInt; + updatePattern <= updatePatternInt; + interpolateLinear <= interpolateLinearInt; + patternSize <= unsigned(patternSizeInt); + + process(runInt, updatePatternInt, interpolateLinearInt, patternSizeInt) + begin + dataOutReg <= (others => '-'); + dataOutReg(runId) <= runInt; + dataOutReg(updatePatternId) <= updatePatternInt; + dataOutReg(interpolateLinearId) <= interpolateLinearInt; + dataOutReg(patternSizeHighId downto patternSizeHighId-patternSize'length+1) + <= patternSizeInt; + end process; + + dataOut <= std_logic_vector(dataOutReg) when en = '1' + else (others => 'Z'); + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity SystemOnChip.blockRAMControl.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY blockRAMControl IS + PORT( + memWr : OUT std_ulogic; + sel : IN std_ulogic; + memEn : OUT std_ulogic; + update : IN std_ulogic; + wr : IN std_ulogic; + cntIncr : OUT std_ulogic; + newSample : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END blockRAMControl ; + + + + + +ARCHITECTURE masterVersion OF blockRAMControl IS + + signal writeDelayed: std_ulogic; + signal writePulse: std_ulogic; + signal memWr1: std_ulogic; + +BEGIN + + delayWrPulse: process(reset, clock) + begin + if reset = '1' then + writeDelayed <= '0'; + elsif rising_edge(clock) then + writeDelayed <= wr; + end if; + end process delayWrPulse; + + writePulse <= '1' when (wr='1') and (writeDelayed='0') + else '0'; + + cntIncr <= '1' when ( (update = '0') and (newSample = '1') ) + or ( (update = '1') and (writePulse = '1') and (sel = '1') ) + else '0'; + + memWr1 <= '1' when (update = '1') and (writePulse = '1') and (sel = '1') + else '0'; + +-- delayMemWrPulse: process(reset, clock) +-- begin +-- if reset = '1' then +-- memWr <= '0'; +-- elsif rising_edge(clock) then +-- memWr <= memWr1; +-- end if; +-- end process delayMemWrPulse; + memWr <= memWr1; + + memEn <= '1' when (sel = '1') or (update = '0') + else '0'; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SystemOnChip.periphAddressDecoder.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphAddressDecoder IS + GENERIC( + addressBitNb : positive := 24 + ); + PORT( + selControl : OUT std_ulogic; + addr : IN unsigned (addressBitNb-1 DOWNTO 0); + selSpeed : OUT std_ulogic; + selX : OUT std_ulogic; + selY : OUT std_ulogic; + selZ : OUT std_ulogic + ); + +-- Declarations + +END periphAddressDecoder ; + + + + + +ARCHITECTURE masterVersion OF periphAddressDecoder IS +BEGIN + + decode: process(addr) + begin + selControl <= '0'; + selSpeed <= '0'; + selX <= '0'; + selY <= '0'; + selZ <= '0'; + case to_integer(addr(3 downto 0)) is + when 16#00# => selControl <= '1'; + when 16#01# => selSpeed <= '1'; + when 16#02# => selX <= '1'; + when 16#03# => selY <= '1'; + when 16#04# => selZ <= '1'; + when others => null; + end case; + end process decode; + +END ARCHITECTURE masterVersion; + + + + + +-- VHDL Entity SystemOnChip.blockRAM.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY blockRAM IS + GENERIC( + addressBitNb : positive := 8; + dataBitNb : positive := 16; + initFileSpec : string := "ramInit.txt" + ); + PORT( + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + write : IN std_ulogic; + addr : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END blockRAM ; + + + + + +USE std.textio.all; + +ARCHITECTURE Spartan3E OF blockRAM IS + + subtype registerType is std_ulogic_vector(dataBitNb-1 downto 0); + type memoryType is array (0 to 2**addressBitNb-1) of registerType; + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFileSpec : in string) return memoryType is + FILE ramContentFile : text open read_mode is ramContentFileSpec; + variable ramContentFileLine : line; + variable ramContent : memoryType; + variable ramCurrentWord : bit_vector(registerType'range); + variable index : natural := 0; --241; + begin + for index in ramContent'range loop +-- while not endfile(ramContentFile) loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramCurrentWord); + ramContent(index) := std_ulogic_vector(to_stdlogicvector(ramCurrentWord)); +-- index := index + 1; + end loop; + return ramContent; + end function; + + shared variable memoryArray: memoryType := ReadRamContentFromFile(initFileSpec); + +BEGIN + + portA: process(clock) + begin + if rising_edge(clock) then + if (en = '1') then + if (write = '1') then + memoryArray(to_integer(addr)) := dataIn; + dataOut <= dataIn; + else + dataOut <= memoryArray(to_integer(addr)); + end if; + end if; + end if; + end process portA; + +END ARCHITECTURE Spartan3E; + + + + +-- VHDL Entity SystemOnChip.periphSpeedReg.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY periphSpeedReg IS + GENERIC( + dataBitNb : positive := 16; + updatePeriodBitNb : positive := 16 + ); + PORT( + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + write : IN std_ulogic + ); + +-- Declarations + +END periphSpeedReg ; + + + + + +ARCHITECTURE masterVersion OF periphSpeedReg IS + + signal updatePeriodInt: unsigned(updatePeriod'range); + +BEGIN + + store: process(reset, clock) + begin + if reset = '1' then + updatePeriodInt <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if write = '1' then + updatePeriodInt <= unsigned(dataIn(updatePeriodInt'range)); + end if; + end if; + end if; + end process store; + + updatePeriod <= updatePeriodInt; + + writeBack: process(en, updatePeriodInt) + begin + if en = '1' then + dataOut <= (others => '-'); + dataOut(updatePeriodInt'range) <= std_logic_vector(updatePeriodInt); + else + dataOut <= (others => 'Z'); + end if; + end process writeBack; + +END ARCHITECTURE masterVersion; + + + + +-- +-- VHDL Architecture SystemOnChip.ahbBeamerRegisters.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:01:22 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +-- LIBRARY SystemOnChip; + +ARCHITECTURE struct OF ahbBeamerRegisters IS + + -- Architecture declarations + constant addressBitNb: positive := hAddr'length; + constant dataBitNb : positive := hWData'length; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL reset : std_ulogic; + SIGNAL addr : unsigned(addressBitNb-1 DOWNTO 0); + SIGNAL addrX : unsigned(patternAddressBitNb-1 DOWNTO 0); + SIGNAL addrY : unsigned(patternAddressBitNb-1 DOWNTO 0); + SIGNAL cntIncrX : std_ulogic; + SIGNAL cntIncrY : std_ulogic; + SIGNAL dataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0); + SIGNAL dataOut : std_logic_vector(dataBitNb-1 DOWNTO 0); + SIGNAL memEnX : std_ulogic; + SIGNAL memEnY : std_ulogic; + SIGNAL memWrX : std_ulogic; + SIGNAL memWrY : std_ulogic; + SIGNAL patternSize : unsigned(patternAddressBitNb-1 DOWNTO 0); + SIGNAL selControl : std_ulogic; + SIGNAL selSpeed : std_ulogic; + SIGNAL selX : std_ulogic; + SIGNAL selY : std_ulogic; + SIGNAL updatePattern : std_ulogic; + SIGNAL write : std_ulogic; + SIGNAL memDataIn : std_ulogic_vector(signalBitNb-1 DOWNTO 0); + SIGNAL run_int : std_ulogic; + SIGNAL interpolateLin_int : std_ulogic; + + + -- Component Declarations + COMPONENT blockRAM + GENERIC ( + addressBitNb : positive := 8; + dataBitNb : positive := 16; + initFileSpec : string := "ramInit.txt" + ); + PORT ( + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + write : IN std_ulogic ; + addr : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT blockRAMAddressCounter + GENERIC ( + addressBitNb : positive := 8 + ); + PORT ( + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + updateMem : IN std_ulogic ; + addr : OUT unsigned (addressBitNb-1 DOWNTO 0); + patternSize : IN unsigned (addressBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT blockRAMControl + PORT ( + memWr : OUT std_ulogic ; + sel : IN std_ulogic ; + memEn : OUT std_ulogic ; + update : IN std_ulogic ; + wr : IN std_ulogic ; + cntIncr : OUT std_ulogic ; + newSample : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + COMPONENT periphAddressDecoder + GENERIC ( + addressBitNb : positive := 24 + ); + PORT ( + selControl : OUT std_ulogic ; + addr : IN unsigned (addressBitNb-1 DOWNTO 0); + selSpeed : OUT std_ulogic ; + selX : OUT std_ulogic ; + selY : OUT std_ulogic ; + selZ : OUT std_ulogic + ); + END COMPONENT; + COMPONENT periphControlReg + GENERIC ( + dataBitNb : positive := 16; + patternSizeBitNb : positive := 8 + ); + PORT ( + run : OUT std_ulogic ; + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + updatePattern : OUT std_ulogic ; + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + write : IN std_ulogic ; + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + interpolateLinear : OUT std_ulogic ; + patternSize : OUT unsigned (patternSizeBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT periphSpeedReg + GENERIC ( + dataBitNb : positive := 16; + updatePeriodBitNb : positive := 16 + ); + PORT ( + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0); + en : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + write : IN std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : blockRAM USE ENTITY SystemOnChip.blockRAM; +-- FOR ALL : blockRAMAddressCounter USE ENTITY SystemOnChip.blockRAMAddressCounter; +-- FOR ALL : blockRAMControl USE ENTITY SystemOnChip.blockRAMControl; +-- FOR ALL : periphAddressDecoder USE ENTITY SystemOnChip.periphAddressDecoder; +-- FOR ALL : periphControlReg USE ENTITY SystemOnChip.periphControlReg; +-- FOR ALL : periphSpeedReg USE ENTITY SystemOnChip.periphSpeedReg; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 3 eb3 + testout( 1) <= run_int; run <= run_int; + testout( 2) <= updatePattern; + testout( 3) <= interpolateLin_int; interpolateLin <= interpolateLin_int; + testout( 4) <= newPolynom; + testout( 5) <= newPolynom; + testout( 6) <= '0'; + testout( 7) <= '0'; + testout( 8) <= selControl; + testout( 9) <= selSpeed; + testout(10) <= selX; + testout(11) <= selY; + testout(12) <= '0'; + testout(13) <= addr(0); + testout(14) <= addr(1); + testout(15) <= dataIn(0); + testout(16) <= dataIn(1); + + -- HDL Embedded Text Block 8 eb8 + storeControls: process(reset, clock) + begin + if reset = '1' then + addr <= (others => '0'); + write <= '0'; + elsif rising_edge(clock) then + write <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addr <= hAddr(addr'range); + write <= hWrite; + end if; + end if; + end process storeControls; + + dataIn <= hWData; + + -- HDL Embedded Text Block 9 eb9 + memDataIn <= dataIn(memDataIn'range); + + -- HDL Embedded Text Block 10 eb10 + hRData <= std_ulogic_vector(dataOut); + + hReady <= '1'; -- no wait state + hResp <= '0'; -- data OK + + -- HDL Embedded Text Block 11 eb11 + clock<= hClk; + + reset <= not hReset_n; + + + -- Instance port mappings. + I_ramx : blockRAM + GENERIC MAP ( + addressBitNb => patternAddressBitNb, + dataBitNb => signalBitNb, + initFileSpec => "C:/dev/sem-labs/06-07-08-09-SystemOnChip/Simulation/ramYInit.txt" + ) + PORT MAP ( + dataIn => memDataIn, + dataOut => memX, + en => memEnX, + clock => clock, + reset => reset, + write => memWrX, + addr => addrX + ); + I_ramy : blockRAM + GENERIC MAP ( + addressBitNb => patternAddressBitNb, + dataBitNb => signalBitNb, + initFileSpec => "C:/dev/sem-labs/06-07-08-09-SystemOnChip/Simulation/ramXInit.txt" + ) + PORT MAP ( + dataIn => memDataIn, + dataOut => memY, + en => memEnY, + clock => clock, + reset => reset, + write => memWrY, + addr => addrY + ); + I_addrx : blockRAMAddressCounter + GENERIC MAP ( + addressBitNb => patternAddressBitNb + ) + PORT MAP ( + en => cntIncrX, + clock => clock, + reset => reset, + updateMem => updatePattern, + addr => addrX, + patternSize => patternSize + ); + I_addry : blockRAMAddressCounter + GENERIC MAP ( + addressBitNb => patternAddressBitNb + ) + PORT MAP ( + en => cntIncrY, + clock => clock, + reset => reset, + updateMem => updatePattern, + addr => addrY, + patternSize => patternSize + ); + I_ctlx : blockRAMControl + PORT MAP ( + memWr => memWrX, + sel => selX, + memEn => memEnX, + update => updatePattern, + wr => write, + cntIncr => cntIncrX, + newSample => newPolynom, + clock => clock, + reset => reset + ); + I_ctly : blockRAMControl + PORT MAP ( + memWr => memWrY, + sel => selY, + memEn => memEnY, + update => updatePattern, + wr => write, + cntIncr => cntIncrY, + newSample => newPolynom, + clock => clock, + reset => reset + ); + I_decoder : periphAddressDecoder + GENERIC MAP ( + addressBitNb => addressBitNb + ) + PORT MAP ( + selControl => selControl, + addr => addr, + selSpeed => selSpeed, + selX => selX, + selY => selY, + selZ => OPEN + ); + I_ctl : periphControlReg + GENERIC MAP ( + dataBitNb => dataBitNb, + patternSizeBitNb => patternAddressBitNb + ) + PORT MAP ( + run => run_int, + dataIn => dataIn, + updatePattern => updatePattern, + dataOut => dataOut, + write => write, + en => selControl, + clock => clock, + reset => reset, + interpolateLinear => interpolateLin_int, + patternSize => patternSize + ); + I_speed : periphSpeedReg + GENERIC MAP ( + dataBitNb => dataBitNb, + updatePeriodBitNb => updatePeriodBitNb + ) + PORT MAP ( + updatePeriod => updatePeriod, + dataIn => dataIn, + dataOut => dataOut, + en => selSpeed, + clock => clock, + reset => reset, + write => write + ); + +END struct; + + + + +-- +-- VHDL Architecture SystemOnChip.ahbBeamer.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:00:20 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +-- LIBRARY SystemOnChip; + +ARCHITECTURE struct OF ahbBeamer IS + + -- Architecture declarations + constant signalBitNb: positive := 16; + constant updatePeriodBitNb : positive := 16; + + -- Internal signal declarations + SIGNAL reset : std_ulogic; + SIGNAL run : std_ulogic; + SIGNAL interpolateLin : std_ulogic; + SIGNAL updatePeriod : unsigned(updatePeriodBitNb-1 DOWNTO 0); + SIGNAL memX : std_ulogic_vector(signalBitNb-1 DOWNTO 0); + SIGNAL memY : std_ulogic_vector(signalBitNb-1 DOWNTO 0); + SIGNAL newPolynom : std_ulogic; + + + -- Component Declarations + COMPONENT ahbBeamerOperator + GENERIC ( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16 + ); + PORT ( + outX : OUT std_ulogic ; + run : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + outY : OUT std_ulogic ; + selSinCos : IN std_ulogic ; + interpolateLin : IN std_ulogic ; + updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0); + memX : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0); + newPolynom : OUT std_ulogic + ); + END COMPONENT; + COMPONENT ahbBeamerRegisters + GENERIC ( + updatePeriodBitNb : positive := 16; + signalBitNb : positive := 16; + patternAddressBitNb : positive := 8; + testOutBitNb : positive := 16 + ); + PORT ( + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + memX : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + memY : OUT std_ulogic_vector (signalBitNb-1 DOWNTO 0); + run : OUT std_ulogic ; + updatePeriod : OUT unsigned (updatePeriodBitNb-1 DOWNTO 0); + interpolateLin : OUT std_ulogic ; + newPolynom : IN std_ulogic ; + hClk : IN std_ulogic ; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + hReset_n : IN std_ulogic ; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic ; + hSel : IN std_ulogic ; + hReady : OUT std_ulogic ; + hResp : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : ahbBeamerOperator USE ENTITY SystemOnChip.ahbBeamerOperator; +-- FOR ALL : ahbBeamerRegisters USE ENTITY SystemOnChip.ahbBeamerRegisters; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 2 eb2 + --process + --begin + -- newPolynom <= '0'; + -- for index in 1 to 2**4-1 loop + -- wait until rising_edge(clock); + -- end loop; + -- newPolynom <= '1'; + -- wait until rising_edge(clock); + --end process; + + -- HDL Embedded Text Block 3 eb3 + reset <= not hReset_n; + + + -- Instance port mappings. + I_op : ahbBeamerOperator + GENERIC MAP ( + updatePeriodBitNb => updatePeriodBitNb, + signalBitNb => signalBitNb + ) + PORT MAP ( + outX => outX, + run => run, + clock => hClk, + reset => reset, + outY => outY, + selSinCos => selSinCos, + interpolateLin => interpolateLin, + updatePeriod => updatePeriod, + memX => memX, + memY => memY, + newPolynom => newPolynom + ); + I_regs : ahbBeamerRegisters + GENERIC MAP ( + updatePeriodBitNb => updatePeriodBitNb, + signalBitNb => signalBitNb, + patternAddressBitNb => patternAddressBitNb, + testOutBitNb => testOutBitNb + ) + PORT MAP ( + testOut => testOut, + memX => memX, + memY => memY, + run => run, + updatePeriod => updatePeriod, + interpolateLin => interpolateLin, + newPolynom => newPolynom, + hClk => hClk, + hRData => hRData, + hAddr => hAddr, + hReset_n => hReset_n, + hWData => hWData, + hTrans => hTrans, + hWrite => hWrite, + hSel => hSel, + hReady => hReady, + hResp => hResp + ); + +END struct; + + + + +-- VHDL Entity AhbLite.ahbMuxConnector.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbMuxConnector IS + GENERIC( + index : positive := 1 + ); + PORT( + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic; + hResp : IN std_uLogic; + hSelV : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRDataV : OUT ahbDataVector; + hReadyV : OUT std_logic_vector (1 TO ahbSlaveNb); + hRespV : OUT std_logic_vector (1 TO ahbSlaveNb); + hSel : OUT std_uLogic + ); + +-- Declarations + +END ahbMuxConnector ; + + + + + +ARCHITECTURE RTL OF ahbMuxConnector IS +BEGIN + + hSel <= hSelV(index); + + hRDataV(index) <= std_logic_vector(hRData); + hReadyV(index) <= hReady; + hRespV(index) <= hResp; + + hRDataV <= (others => (others => 'Z')); + hReadyV <= (others => 'Z'); + hRespV <= (others => 'Z'); + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity AhbLite.ahbDecoder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbDecoder IS + GENERIC( + ahbMemoryLocation : ahbMemoryLocationVector + ); + PORT( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hSel : OUT std_ulogic_vector (1 TO ahbSlaveNb) + ); + +-- Declarations + +END ahbDecoder ; + + + + + +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ARCHITECTURE RTL OF ahbDecoder IS +BEGIN + + decodeAddress: process(hAddr) + variable mask: unsigned(hAddr'range); + begin + hSel <= (others => '0'); + for index in hSel'range loop + mask := to_unsigned(ahbMemoryLocation(index).addressMask, mask'length); + if (hAddr and mask) = ahbMemoryLocation(index).baseAddress then + hSel(index) <= '1'; + end if; + end loop; + end process decodeAddress; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity AhbLiteComponents.ahbGpio.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:43:49 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbGpio IS + GENERIC( + ioNb : positive := 8 + ); + PORT( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic; + hReset_n : IN std_uLogic; + hSel : IN std_uLogic; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic; + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) + ); + +-- Declarations + +END ahbGpio ; + + + + + +--============================================================================== +-- +-- AHB general purpose input/outputs +-- +-- Provides "ioNb" input/output signals . +-- +-------------------------------------------------------------------------------- +-- +-- Write registers +-- +-- 00, data register receives the values to drive the output lines. +-- 01, output enable register defines the signal direction: +-- when '1', the direction is "out". +-- +-------------------------------------------------------------------------------- +-- +-- Read registers +-- 00, data register provides the values detected on the lines. +-- + +ARCHITECTURE masterVersion OF ahbGpio IS + + signal reset, clock: std_ulogic; + -- register definitions + constant dataRegisterId: natural := 0; + constant outputEnableRegisterId: natural := 1; + + signal addressReg: unsigned(addressBitNb(outputEnableRegisterId)-1 downto 0); + signal writeReg: std_ulogic; + -- written registers + subtype registerType is unsigned(ioNb-1 downto 0); + signal dataOutRegister, outputEnableRegister: registerType; + -- read registers + signal dataInRegister : registerType; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= not hReset_n; + clock <= hClk; + + --============================================================================ + -- address and controls + storeControls: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + writeReg <= '0'; + elsif rising_edge(clock) then + writeReg <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addressReg <= hAddr(addressReg'range); + writeReg <= hWrite; + end if; + end if; + end process storeControls; + + --============================================================================ + -- registers + storeWriteRegisters: process(reset, clock) + begin + if reset = '1' then + dataOutRegister <= (others => '0'); + outputEnableRegister <= (others => '0'); + elsif rising_edge(clock) then + if writeReg = '1' then + case to_integer(addressReg) is + when dataRegisterId => dataOutRegister <= unsigned(hWData(dataOutRegister'range)); + when outputEnableRegisterId => outputEnableRegister <= unsigned(hWData(outputEnableRegister'range)); + when others => null; + end case; + end if; + end if; + end process storeWriteRegisters; + + ioOut <= std_ulogic_vector(dataOutRegister); + ioEn <= std_ulogic_vector(outputEnableRegister); + + --============================================================================ + -- data readback + dataInRegister <= unsigned(ioIn); + + hRData <= std_ulogic_vector(resize(dataInRegister, hRData'length)); + hReady <= '1'; -- no wait state + hResp <= '0'; -- data OK + + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity AhbLite.ahbMasterInterface.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbMasterInterface IS + PORT( + clock : IN std_ulogic; + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic; + hResp : IN std_uLogic; + pAddress : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + pDataOut : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + pReadStrobe : IN std_uLogic; + pWriteStrobe : IN std_uLogic; + reset : IN std_ulogic; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hBurst : OUT std_ulogic_vector (ahbBurstBitNb-1 DOWNTO 0); + hClk : OUT std_uLogic; + hMastLock : OUT std_uLogic; + hProt : OUT std_ulogic_vector (ahbProtBitNb-1 DOWNTO 0); + hReset_n : OUT std_uLogic; + hSize : OUT std_ulogic_vector (ahbSizeBitNb-1 DOWNTO 0); + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic; + pDataIn : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END ahbMasterInterface ; + + + + + +ARCHITECTURE RTL OF ahbMasterInterface IS + + signal addressReg: unsigned(pAddress'range); + signal newAddress: std_ulogic; + signal writeReg: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + hReset_n <= not reset; + hClk <= clock; + + ------------------------------------------------------------------------------ + -- address and controls + newAddress <= pReadStrobe or pWriteStrobe; + + storeAddress: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + elsif rising_edge(clock) then + if newAddress = '1' then + addressReg <= pAddress; + end if; + end if; + end process storeAddress; + + hAddr <= pAddress when newAddress = '1' + else addressReg; + + storeWrite: process(reset, clock) + begin + if reset = '1' then + writeReg <= '0'; + elsif rising_edge(clock) then + if newAddress = '1' then + writeReg <= pWriteStrobe; + end if; + end if; + end process storeWrite; + + hWrite <= pWriteStrobe when newAddress = '1' + else writeReg; + + hTrans <= transNonSeq when newAddress = '1' + else transIdle; + + hSize <= size16; + hBurst <= burstSingle; + hProt <= protDefault; + hMastLock <= '0'; + + ------------------------------------------------------------------------------ + -- data out + delayData: process(reset, clock) + begin + if reset = '1' then + hWData <= (others => '0'); + elsif rising_edge(clock) then + if pWriteStrobe = '1' then + hWData <= pDataOut; + end if; + end if; + end process delayData; + + ------------------------------------------------------------------------------ + -- data in + pDataIn <= hRData; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity AhbLite.ahbMultiplexor.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:16 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbMultiplexor IS + PORT( + hRDataV : IN ahbDataVector; + hReadyV : IN std_logic_vector (1 TO ahbSlaveNb); + hRespV : IN std_logic_vector (1 TO ahbSlaveNb); + hSel : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic + ); + +-- Declarations + +END ahbMultiplexor ; + + + + + +ARCHITECTURE RTL OF ahbMultiplexor IS +BEGIN + + multiplexData: process(hSel, hRDataV, hReadyV, hRespV) + begin + hRData <= (others => '0'); + hReady <= '1'; + hResp <= '0'; + for index in hSel'range loop + if hSel(index) = '1' then + hRData <= std_ulogic_vector(hRDataV(index)); + hReady <= hReadyV(index); + hResp <= hRespV(index); + end if; + end loop; + end process multiplexData; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity SystemOnChip.programRom.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 14:40:20 03/13/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY programRom IS + GENERIC( + addressBitNb : positive := 8; + dataBitNb : positive := 8 + ); + PORT( + address : IN unsigned (addressBitNb-1 DOWNTO 0); + clock : IN std_ulogic; + en : IN std_ulogic; + reset : IN std_ulogic; + dataOut : OUT std_ulogic_vector ( dataBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END programRom ; + + + + + +ARCHITECTURE mapped OF programRom IS + + subtype opCodeType is std_ulogic_vector(5 downto 0); + constant opLoadC : opCodeType := "000000"; + constant opLoadR : opCodeType := "000001"; + constant opInputC : opCodeType := "000100"; + constant opInputR : opCodeType := "000101"; + constant opFetchC : opCodeType := "000110"; + constant opFetchR : opCodeType := "000111"; + constant opAndC : opCodeType := "001010"; + constant opAndR : opCodeType := "001011"; + constant opOrC : opCodeType := "001100"; + constant opOrR : opCodeType := "001101"; + constant opXorC : opCodeType := "001110"; + constant opXorR : opCodeType := "001111"; + constant opTestC : opCodeType := "010010"; + constant opTestR : opCodeType := "010011"; + constant opCompC : opCodeType := "010100"; + constant opCompR : opCodeType := "010101"; + constant opAddC : opCodeType := "011000"; + constant opAddR : opCodeType := "011001"; + constant opAddCyC : opCodeType := "011010"; + constant opAddCyR : opCodeType := "011011"; + constant opSubC : opCodeType := "011100"; + constant opSubR : opCodeType := "011101"; + constant opSubCyC : opCodeType := "011110"; + constant opSubCyR : opCodeType := "011111"; + constant opShRot : opCodeType := "100000"; + constant opOutputC : opCodeType := "101100"; + constant opOutputR : opCodeType := "101101"; + constant opStoreC : opCodeType := "101110"; + constant opStoreR : opCodeType := "101111"; + + subtype shRotCinType is std_ulogic_vector(2 downto 0); + constant shRotLdC : shRotCinType := "00-"; + constant shRotLdM : shRotCinType := "01-"; + constant shRotLdL : shRotCinType := "10-"; + constant shRotLd0 : shRotCinType := "110"; + constant shRotLd1 : shRotCinType := "111"; + + constant registerAddressBitNb : positive := 4; + constant shRotPadLength : positive + := dataOut'length - opCodeType'length - registerAddressBitNb + - 1 - shRotCinType'length; + subtype shRotDirType is std_ulogic_vector(1+shRotPadLength-1 downto 0); + constant shRotL : shRotDirType := (0 => '0', others => '-'); + constant shRotR : shRotDirType := (0 => '1', others => '-'); + + subtype branchCodeType is std_ulogic_vector(4 downto 0); + constant brRet : branchCodeType := "10101"; + constant brCall : branchCodeType := "11000"; + constant brJump : branchCodeType := "11010"; + constant brReti : branchCodeType := "11100"; + constant brEni : branchCodeType := "11110"; + + subtype branchConditionType is std_ulogic_vector(2 downto 0); + constant brDo : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( + --=============================================================== + -- Beamer control + --=============================================================== + -- + ----------------------------------------------------------------- + -- register definitions + -- s0, s1: used for INPUT and OUTPUT operations + -- S2: returns UART data byte + -- S3: uart protocol checksum + -- S4: uart protocol packet id + -- S5: uart protocol command id + -- S6: uart protocol address + -- S7: uart protocol data + -- S8: copy of UART data byte for debug + ----------------------------------------------------------------- + -- + ----------------------------------------------------------------- + -- GPIO definitions + ----------------------------------------------------------------- + ----------------------------------------------------------------- + -- UART definitions + ----------------------------------------------------------------- + -- CONSTANT uartBaudCount, 023D ; 66E6 / 115 200 = 573 + -- CONSTANT uartpollDelay, 0100 + ----------------------------------------------------------------- + -- beamer peripheral definitions + ----------------------------------------------------------------- + -- CONSTANT beamerCtlInit, 1001 + -- + --=============================================================== + -- initializations + --=============================================================== + -- + ----------------------------------------------------------------- + -- initialize GPIO + ----------------------------------------------------------------- + 16#000# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#001# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#002# => opLoadC & "0001" & "0000000010101010", -- LOAD s1, AA + 16#003# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#004# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#005# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#006# => opLoadC & "0001" & "0000000000001111", -- LOAD s1, 0F + 16#007# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize UART + ----------------------------------------------------------------- + 16#008# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 + 16#009# => opAddC & "0000" & "0000000000000010", -- ADD s0, 0002 + 16#00A# => opLoadC & "0001" & "0000000001000010", -- LOAD s1, 0042 + 16#00B# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize beamer peripheral + ----------------------------------------------------------------- + 16#00C# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#00D# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#00E# => opLoadC & "0001" & "0000010000000001", -- LOAD s1, 0401 + 16#00F# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#010# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#011# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#012# => opLoadC & "0001" & "0000000000000100", -- LOAD s1, 0004 + 16#013# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + -- + --=============================================================== + -- Main loop + --=============================================================== + -- + ----------------------------------------------------------------- + -- Process commands from serial port + ----------------------------------------------------------------- + -- _main_: + 16#014# => brCall & brDo & "--------0000100001",-- CALL 021 ; get command from UART + 16#015# => opCompC & "0011" & "0000000000000000", -- COMPARE s3, 0000 ; check function return + 16#016# => brJump & brNZ & "--------0000011111",-- JUMP NZ, 01F + 16#017# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#018# => brJump & brNZ & "--------0000011100",-- JUMP NZ, 01C + 16#019# => opOutputR & "0111" & "0110------------", -- OUTPUT s7, (S6) ; write word to memory location + 16#01A# => brCall & brDo & "--------0001100000",-- CALL 060 ; send write acknowledge + 16#01B# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandRead_: + 16#01C# => opInputR & "0111" & "0110------------", -- INPUT s7, (S6) ; write word in memory location + 16#01D# => brCall & brDo & "--------0001101111",-- CALL 06F ; send back read data + 16#01E# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandAbort_: + 16#01F# => brCall & brDo & "--------0001010001",-- CALL 051 + 16#020# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- + --=============================================================== + -- Subroutines + --=============================================================== + -- + ----------------------------------------------------------------- + -- Get command from serial port + ----------------------------------------------------------------- + -- _uartGetCmd_: + 16#021# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command header + 16#022# => opCompC & "0010" & "0000000010101010", -- COMPARE s2, 00AA + 16#023# => brJump & brNZ & "--------0000100001",-- JUMP NZ, 021 ; loop until byte is AAh + 16#024# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#025# => brCall & brDo & "--------0010000110",-- CALL 086 ; get packet id + 16#026# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#027# => opLoadR & "0100" & "0010------------", -- LOAD s4, s2 ; store id for reply + 16#028# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command + 16#029# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#02A# => opCompC & "0010" & "0000000000000011", -- COMPARE s2, 0003 ; check for WRITE_MEM command + 16#02B# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02C# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; check for READ_MEM command + 16#02D# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02E# => brJump & brDo & "--------0001001111",-- JUMP 04F ; no match + -- _commandOk_: + 16#02F# => opLoadR & "0101" & "0010------------", -- LOAD s5, s2 ; store command for action + 16#030# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data length + 16#031# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#032# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#033# => brJump & brZ & "--------0000110111",-- JUMP Z, 037 ; go to test write command length + 16#034# => opCompC & "0010" & "0000000000000010", -- COMPARE s2, 0002 ; verify READ_MEM length + 16#035# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#036# => brJump & brDo & "--------0000111001",-- JUMP 039 + -- _testWrLength_: + 16#037# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; verify WRITE_MEM length + 16#038# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + -- _getAddress_: + 16#039# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address low + 16#03A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03B# => opLoadR & "0110" & "0010------------", -- LOAD s6, s2 ; store address low + 16#03C# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address high + 16#03D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03E# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#03F# => opAddR & "0110" & "0010------------", -- ADD s6, s2 ; build address from low and high + 16#040# => opCompC & "0101" & "0000000000000100", -- COMPARE s5, 0004 ; check for READ_MEM command + 16#041# => brJump & brZ & "--------0001001001",-- JUMP Z, 049 ; skip reading data word + 16#042# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data low + 16#043# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#044# => opLoadR & "0111" & "0010------------", -- LOAD s7, s2 ; store data low + 16#045# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data high + 16#046# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#047# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#048# => opAddR & "0111" & "0010------------", -- ADD s7, s2 ; build data from low and high + -- _getChecksum_: + 16#049# => brCall & brDo & "--------0010000110",-- CALL 086 ; get checksum + 16#04A# => opAndC & "0011" & "0000000011111111", -- AND s3, 00FF ; limit calculated checksum to 8 bit + 16#04B# => opCompR & "0011" & "0010------------", -- COMPARE s3, s2 ; test checksum + 16#04C# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#04D# => opLoadC & "0011" & "0000000000000000", -- LOAD s3, 0000 ; return OK + 16#04E# => brRet & brDo & "------------------",-- RETURN + -- _commandKo_: + 16#04F# => opLoadC & "0011" & "0000000000000001", -- LOAD s3, 0001 ; return KO + 16#050# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send NACK reply + ----------------------------------------------------------------- + -- _sendNAck_: + 16#051# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#052# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#053# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#054# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#055# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#056# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#057# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; negative Acknowledge + 16#058# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#059# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05A# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#05B# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#05C# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05D# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#05E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send WRITE_MEM reply + ----------------------------------------------------------------- + -- _sendWriteOk_: + 16#060# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#061# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#062# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#063# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#064# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#065# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#066# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#067# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#068# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#069# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#06A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#06B# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06C# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#06D# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06E# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send READ_MEM reply + ----------------------------------------------------------------- + -- _sendReadData_: + 16#06F# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#070# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#071# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#072# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#073# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#074# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#075# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#076# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#077# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#078# => opLoadC & "0010" & "0000000000000010", -- LOAD s2, 0002 ; packet length: 2 bytes + 16#079# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07A# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07B# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data low + 16#07C# => opAndC & "0010" & "0000000011111111", -- AND s2, 00FF ; keep low byte only + 16#07D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07F# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data high + 16#080# => brCall & brDo & "--------0010100101",-- CALL 0A5 ; shift MSBs down to LSBs + 16#081# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#082# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#083# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#084# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#085# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Get byte from serial port + ----------------------------------------------------------------- + -- _uartGetByte_: + 16#086# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#087# => opAddC & "0000" & "0000000000000001", -- ADD s0, 01 + --load s8, 0100 + -- _checkStat_: + 16#088# => opLoadC & "0010" & "0000000001000000", -- LOAD s2, 0040 ; add delay between bus reads + -- _delay0_: + 16#089# => opSubC & "0010" & "0000000000000001", -- SUB s2, 0001 + 16#08A# => brJump & brNZ & "--------0010001001",-- JUMP NZ, 089 + --sub s8, 0001 + --jump nz, continue + --load s2, 0035 + --call uartSendByte + --load s8, 0100 + -- _continue_: + 16#08B# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08C# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08D# => opTestC & "0001" & "0000000000000001", -- TEST s1, 0001 ; check "data ready" bit + 16#08E# => brJump & brZ & "--------0010001000",-- JUMP Z, 088 ; loop until bit is '1' + 16#08F# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART data register + 16#090# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + 16#091# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + --LOAD s8, s2 + 16#092# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Send byte to serial port + ----------------------------------------------------------------- + -- _uartSendByte_: + 16#093# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#094# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + -- _readStatus_: + 16#095# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#096# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#097# => opTestC & "0001" & "0000000000000010", -- TEST s1, 0002 ; check "sending data" bit + 16#098# => brJump & brZ & "--------0010011101",-- JUMP Z, 09D ; loop until bit is '1' + 16#099# => opLoadC & "0001" & "0000000001000000", -- LOAD s1, 0040 ; add delay between bus reads + -- _delay1_: + 16#09A# => opSubC & "0001" & "0000000000000001", -- SUB s1, 0001 + 16#09B# => brJump & brNZ & "--------0010011010",-- JUMP NZ, 09A + 16#09C# => brJump & brDo & "--------0010010101",-- JUMP 095 + -- _sendByte_: + 16#09D# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; write UART data register + 16#09E# => opOutputR & "0010" & "0000------------", -- OUTPUT s2, (S0) + 16#09F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the left + ----------------------------------------------------------------- + -- _shiftS2L8_: + 16#0A0# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftLeftLoop_: + 16#0A1# => opShRot & "0010" & shRotL & shRotLd0, -- SL0 s2 + 16#0A2# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A3# => brJump & brNZ & "--------0010100001",-- JUMP NZ, 0A1 + 16#0A4# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the right + ----------------------------------------------------------------- + -- _shiftS2R8_: + 16#0A5# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftRightLoop_: + 16#0A6# => opShRot & "0010" & shRotR & shRotLd0, -- SR0 s2 + 16#0A7# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A8# => brJump & brNZ & "--------0010100110",-- JUMP NZ, 0A6 + 16#0A9# => brRet & brDo & "------------------",-- RETURN + -- + --=============================================================== + -- End of instruction memory + --=============================================================== + -- _endOfMemory_: + 16#3FF# => brJump & brDo & "--------1111111111",-- JUMP 3FF + others => (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= memoryArray(to_integer(address)); + end if; + end if; + end process; + +END ARCHITECTURE mapped; + + + + +-- VHDL Entity AhbLiteComponents.ahbUart.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:43:49 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +ENTITY ahbUart IS + GENERIC( + txFifoDepth : positive := 8; + rxFifoDepth : positive := 1 + ); + PORT( + RxD : IN std_ulogic; + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic; + hReset_n : IN std_uLogic; + hSel : IN std_uLogic; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic; + TxD : OUT std_ulogic; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic; + hResp : OUT std_uLogic + ); + +-- Declarations + +END ahbUart ; + + + + + +--============================================================================== +-- +-- AHB UART +-- +-- Implements a serial port. +-- +-------------------------------------------------------------------------------- +-- +-- Write registers +-- +-- 00, data register receives the word to be sent to the serial port. +-- 01, control register is used to control the peripheral. +-- 02, scaler register is used to set the baud rate. +-- +-------------------------------------------------------------------------------- +-- +-- Read registers +-- 00, data register provides the last word received by the serial port. +-- 01, status register is used to get the peripheral's state. +-- bit 0: data ready for read +-- bit 1: sending in progress +-- bit 2: receiving in progress +-- + +ARCHITECTURE masterVersion OF ahbUart IS + + signal reset, clock: std_ulogic; + -- register definitions + constant dataOutRegisterId: natural := 0; + constant dataBitNb: positive := 8; + constant controlRegisterId: natural := 1; + constant controlBpoId: natural := 0; + constant controlFormatId: natural := 0; + constant scalerRegisterId: natural := 2; + + constant statusRegisterId: natural := 1; + constant statusReadyId: natural := 0; + constant statusSendingId: natural := 1; + constant statusReceivingId: natural := 2; + -- written registers + signal addressReg: unsigned(addressBitNb(scalerRegisterId)+1-1 downto 0); + signal writeReg: std_ulogic; + signal readReg: std_ulogic; + subtype registerType is unsigned(hWdata'length-1 downto 0); + signal dataOutRegister : unsigned(dataBitNb-1 downto 0); + signal controlRegister, scalerRegister: registerType; + -- serializer + signal txPeriodCounter: unsigned(registerType'range); + signal txEn: std_uLogic; + signal txStart: std_uLogic; + signal txSending: std_uLogic; + signal txShiftCounter : unsigned(addressBitNb(dataOutRegister'length+2)-1 downto 0); + signal txShiftRegister : unsigned(dataOutRegister'high+1 downto 0); + -- read registers + signal dataInRegister : unsigned(dataOutRegister'range); + signal statusRegister: registerType; + -- deserializer + signal rxPeriodCounter: unsigned(registerType'range); + signal rxEn: std_uLogic; + signal rxDelayed, rxChanged: std_uLogic; + signal rxShiftCounter : unsigned(txShiftCounter'range); + signal rxReceiving: std_uLogic; + signal rxShiftRegister : unsigned(dataInRegister'range); + signal rxDataReady: std_uLogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= not hReset_n; + clock <= hClk; + + --============================================================================ + -- address and controls + storeControls: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + writeReg <= '0'; + readReg <= '0'; + elsif rising_edge(clock) then + writeReg <= '0'; + readReg <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addressReg <= hAddr(addressReg'range); + writeReg <= hWrite; + readReg <= not hWrite; + end if; + end if; + end process storeControls; + + --============================================================================ + -- registers + storeWriteRegisters: process(reset, clock) + begin + if reset = '1' then + dataOutRegister <= (others => '0'); + controlRegister <= (others => '0'); + scalerRegister <= (others => '0'); + elsif rising_edge(clock) then + if writeReg = '1' then + case to_integer(addressReg) is + when dataOutRegisterId => dataOutRegister <= unsigned(hWData(dataOutRegister'range)); + when controlRegisterId => controlRegister <= unsigned(hWData); + when scalerRegisterId => scalerRegister <= unsigned(hWData); + when others => null; + end case; + end if; + end if; + end process storeWriteRegisters; + + txStart <= '1' when (writeReg = '1') and (addressReg = dataOutRegisterId) + else '0'; + + --============================================================================ + -- serializer + -- tx baud rate + countTxBaudRate: process(reset, clock) + begin + if reset = '1' then + txPeriodCounter <= (others => '1'); + elsif rising_edge(clock) then + if txPeriodCounter + 1 < scalerRegister then + txPeriodCounter <= txPeriodCounter + 1; + else + txPeriodCounter <= (others => '0'); + end if; + end if; + end process countTxBaudRate; + + txEn <= '1' when txPeriodCounter = 1 + else '0'; + -- count tx shift + countTxShift: process(reset, clock) + begin + if reset = '1' then + txShiftCounter <= (others => '0'); + elsif rising_edge(clock) then + if txShiftCounter = 0 then + if txStart = '1' then + txShiftCounter <= txShiftCounter + 1; + end if; + elsif txEn = '1' then + if txShiftCounter < dataOutRegister'length + 3 then + txShiftCounter <= txShiftCounter + 1; + else + txShiftCounter <= (others => '0'); + end if; + end if; + end if; + end process countTxShift; + + txSending <= '1' when txShiftCounter /= 0 + else '0'; + -- tx serializer + shiftTxData: process(reset, clock) + begin + if reset = '1' then + txShiftRegister <= (others => '1'); + elsif rising_edge(clock) then + if txEn = '1' then + if txShiftCounter = 1 then + txShiftRegister <= dataOutRegister & '0'; + else + txShiftRegister <= shift_right(txShiftRegister, 1); + txShiftRegister(txShiftRegister'high) <= '1'; + end if; + end if; + end if; + end process shiftTxData; + + TxD <= txShiftRegister(0); + + --============================================================================ + -- deserializer + delayRxd: process(reset, clock) + begin + if reset = '1' then + rxDelayed <= '0'; + elsif rising_edge(clock) then + rxDelayed <= RxD; + end if; + end process delayRxd; + + rxChanged <= '1' when rxDelayed /= RxD + else '0'; + -- rx baud rate + countRxBaudRate: process(reset, clock) + begin + if reset = '1' then + rxPeriodCounter <= (others => '1'); + elsif rising_edge(clock) then + if rxChanged = '1' then + rxPeriodCounter <= (others => '0'); + elsif rxPeriodCounter + 1 < scalerRegister then + rxPeriodCounter <= rxPeriodCounter + 1; + else + rxPeriodCounter <= (others => '0'); + end if; + end if; + end process countRxBaudRate; + + rxEn <= '1' when rxPeriodCounter = shift_right(scalerRegister-2, 1) + else '0'; + -- count rx shift + countRxShift: process(reset, clock) + begin + if reset = '1' then + rxShiftCounter <= (others => '0'); + elsif rising_edge(clock) then + if rxShiftCounter = 0 then + if (RxD = '0') and (rxDelayed = '1') then + rxShiftCounter <= rxShiftCounter + 1; + end if; + elsif rxEn = '1' then + if rxShiftCounter < dataInRegister'length + 2 then + rxShiftCounter <= rxShiftCounter + 1; + else + rxShiftCounter <= (others => '0'); + end if; + end if; + end if; + end process countRxShift; + + rxReceiving <= '1' when rxShiftCounter /= 0 + else '0'; + -- rx deserializer + shiftRxData: process(reset, clock) + begin + if reset = '1' then + rxShiftRegister <= (others => '1'); + dataInRegister <= (others => '0'); + elsif rising_edge(clock) then + if rxEn = '1' then + if rxShiftCounter <= dataInRegister'length+1 then + rxShiftRegister <= shift_right(rxShiftRegister, 1); + rxShiftRegister(rxShiftRegister'high) <= RxD; + end if; + if rxShiftCounter = dataInRegister'length+2 then + dataInRegister <= rxShiftRegister; + end if; + end if; + end if; + end process shiftRxData; + -- monitor data ready + checkDataReady: process(reset, clock) + begin + if reset = '1' then + rxDataReady <= '0'; + elsif rising_edge(clock) then + if (rxEn = '1') and (rxShiftCounter = dataInRegister'length+2) then + rxDataReady <= '1'; + elsif (readReg = '1') and (addressReg = dataOutRegisterId) then + rxDataReady <= '0'; + end if; + end if; + end process checkDataReady; + + --============================================================================ + -- data readback + statusRegister <= ( + statusReadyId => rxDataReady, + statusSendingId => txSending, + statusReceivingId => rxReceiving, + others => '0' + ); + + selectData: process(addressReg, dataInRegister, statusRegister) + begin + hRData <= (others => '-'); + case to_integer(addressReg) is + when dataOutRegisterId => hRData <= std_ulogic_vector(resize(dataInRegister, hRData'length)); + when statusRegisterId => hRData <= std_ulogic_vector(statusRegister); + when others => null; + end case; + end process selectData; + + hReady <= '1'; -- no wait state + hResp <= '0'; -- data OK + + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity NanoBlaze.nanoProcessor.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:43 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY nanoProcessor IS + GENERIC( + addressBitNb : positive := 8; + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5; + instructionBitNb : positive := 18; + scratchpadAddressBitNb : natural := 4 + ); + PORT( + clock : IN std_ulogic; + dataIn : IN std_ulogic_vector (registerBitNb-1 DOWNTO 0); + en : IN std_ulogic; + instruction : IN std_ulogic_vector (instructionBitNb-1 DOWNTO 0); + int : IN std_uLogic; + reset : IN std_ulogic; + dataAddress : OUT unsigned (addressBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (registerBitNb-1 DOWNTO 0); + intAck : OUT std_ulogic; + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + readStrobe : OUT std_uLogic; + writeStrobe : OUT std_uLogic + ); + +-- Declarations + +END nanoProcessor ; + + + + + +-- VHDL Entity NanoBlaze.aluAndRegs.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:43 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY aluAndRegs IS + GENERIC( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + portAddressBitNb : positive := 8; + scratchpadAddressBitNb : natural := 4 + ); + PORT( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic; + clock : IN std_ulogic; + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic; + regWrite : IN std_ulogic; + registerFileSel : IN std_ulogic; + reset : IN std_ulogic; + scratchpadSel : IN std_ulogic; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic; + portAddr : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + scratchpadAddr : OUT unsigned (scratchpadAddressBitNb-1 DOWNTO 0); + spadOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + zero : OUT std_ulogic + ); + +-- Declarations + +END aluAndRegs ; + + + + + +-- VHDL Entity NanoBlaze.alu.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY alu IS + GENERIC( + aluCodeBitNb : positive := 5; + dataBitNb : positive := 8 + ); + PORT( + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic; + opA : IN signed ( dataBitNb-1 DOWNTO 0 ); + opB : IN signed ( dataBitNb-1 DOWNTO 0 ); + aluOut : OUT signed ( dataBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic; + zero : OUT std_ulogic + ); + +-- Declarations + +END alu ; + + + + + +ARCHITECTURE RTL OF alu IS + + signal aluCodeInt: unsigned(aluCode'range); + signal aArith: signed(opA'high+1 downto 0); + signal bArith: signed(opA'high+1 downto 0); + signal cInArith: signed(1 downto 0); + signal cInShift: std_ulogic; + signal yArith: signed(aluOut'high+1 downto 0); + signal aluOutInt: signed(aluOut'range); + +BEGIN + ------------------------------------------------------------------------------ + -- clear aluCode don't care LSB for shifts + aluCodeInt(aluCode'high downto 1) <= unsigned(aluCode(aluCode'high downto 1)); + + cleanupLsb: process(aluCode) + begin + if aluCode(aluCode'high) = '1' then + aluCodeInt(0) <= '0'; + else + aluCodeInt(0) <= aluCode(0); + end if; + end process cleanupLsb; + + ------------------------------------------------------------------------------ + -- values for arithmetic operations + aArith <= signed(resize(unsigned(opA), aArith'length)); + bArith <= signed(resize(unsigned(opB), bArith'length)); + cInArith <= (0 => cIn, others => '0'); + + process(aluCode, cIn, opA) + begin + case aluCode(2 downto 1) is + when "00" => cInShift <= cIn; + when "01" => cInShift <= opA(opA'high); + when "10" => cInShift <= opA(opA'low); + when "11" => cInShift <= aluCode(0); + when others => cInShift <= '-'; + end case; + end process; + + ------------------------------------------------------------------------------ + -- alu operations + aluOperation: process( + aluCodeInt, + opA, opB, + aArith, bArith, cInArith, + cInShift, + yArith, aluOutInt + ) + variable xorAcc: std_ulogic; + begin + yArith <= (others => '-'); + cOut <= '-'; + aluOutInt <= (others => '-'); + case to_integer(aluCodeInt) is + when 0 => -- LOAD sX, kk + aluOutInt <= opB; + when 2 => -- INPUT sX, pp + aluOutInt <= opB; + when 3 => -- FETCH sX, ss + aluOutInt <= opB; + when 5 => -- AND sX, kk + aluOutInt <= opA and opB; + cOut <= '0'; + when 6 => -- OR sX, kk + aluOutInt <= opA or opB; + cOut <= '0'; + when 7 => -- XOR sX, kk + aluOutInt <= opA xor opB; + cOut <= '0'; + when 9 => -- TEST sX, kk + aluOutInt <= opA and opB; + xorAcc := '0'; + for index in aluOutInt'range loop + xorAcc := xorAcc xor aluOutInt(index); + end loop; + cOut <= xorAcc; + when 10 => -- COMPARE sX, kk + yArith <= aArith - bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 12 => -- ADD sX, kk + yArith <= aArith + bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 13 => -- ADDCY sX, kk + yArith <= (aArith + bArith) + cInArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 14 => -- SUB sX, kk + yArith <= aArith - bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 15 => -- SUBCY sX, kk + yArith <= (aArith - bArith) - cInArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 16 to 23 => -- SL sX + aluOutInt <= opA(opA'high-1 downto 0) & cInShift; + cOut <= opA(opA'high); + when 24 to 31 => -- SR sX + aluOutInt <= cInShift & opA(opA'high downto 1); + cOut <= opA(0); + when others => + aluOutInt <= (others => '-'); + end case; + end process aluOperation; + + aluOut <= aluOutInt; + zero <= '1' when aluOutInt = 0 else '0'; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.aluBOpSelector.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY aluBOpSelector IS + GENERIC( + registerBitNb : positive := 8 + ); + PORT( + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic; + registerFileIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + registerFileSel : IN std_ulogic; + scratchpadSel : IN std_ulogic; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + opB : OUT signed (registerBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END aluBOpSelector ; + + + + + +ARCHITECTURE RTL OF aluBOpSelector IS +BEGIN + + selectDataSource: process( + registerFileSel, registerFileIn, + scratchpadSel, spadIn, + portInSel, portIn, + instrDataSel, instrData + ) + begin + if registerFileSel = '1' then + opB <= registerFileIn; + elsif scratchpadSel = '1' then + opB <= spadIn; + elsif portInSel = '1' then + opB <= portIn; + elsif instrDataSel = '1' then + opB <= instrData; + else + opB <= (others => '-'); + end if; + end process selectDataSource; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.registerFile.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY registerFile IS + GENERIC( + registerAddressBitNb : positive := 4; + dataBitNb : positive := 8 + ); + PORT( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic; + regWrite : IN std_ulogic; + registersIn : IN signed ( dataBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic; + opA : OUT signed ( dataBitNb-1 DOWNTO 0 ); + opB : OUT signed ( dataBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END registerFile ; + + + + + +ARCHITECTURE RTL OF registerFile IS + + subtype registerType is signed(registersIn'range); + type registerArrayType is array (0 to 2**registerAddressBitNb-1) of registerType; + signal registerArray : registerArrayType; + +BEGIN + ------------------------------------------------------------------------------ + -- write to registers + updateRegister: process(reset, clock) + begin + if reset = '1' then + registerArray <= (others => (others => '0')); + elsif rising_edge(clock) then + if regWrite = '1' then + registerArray(to_integer(addrA)) <= registersIn; + end if; + end if; + end process updateRegister; + + ------------------------------------------------------------------------------ + -- read from registers + opA <= registerArray(to_integer(addrA)); + opB <= registerArray(to_integer(addrB)); + +END ARCHITECTURE RTL; + + + + +-- +-- VHDL Architecture NanoBlaze.aluAndRegs.struct +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:44 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY NanoBlaze; + +ARCHITECTURE struct OF aluAndRegs IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL aluOut : signed(registerBitNb-1 DOWNTO 0); + SIGNAL opA : signed(registerBitNb-1 DOWNTO 0); + SIGNAL opB : signed(registerBitNb-1 DOWNTO 0); + SIGNAL registerFileIn : signed(registerBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT alu + GENERIC ( + aluCodeBitNb : positive := 5; + dataBitNb : positive := 8 + ); + PORT ( + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic ; + opA : IN signed ( dataBitNb-1 DOWNTO 0 ); + opB : IN signed ( dataBitNb-1 DOWNTO 0 ); + aluOut : OUT signed ( dataBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic ; + zero : OUT std_ulogic + ); + END COMPONENT; + COMPONENT aluBOpSelector + GENERIC ( + registerBitNb : positive := 8 + ); + PORT ( + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic ; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic ; + registerFileIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + registerFileSel : IN std_ulogic ; + scratchpadSel : IN std_ulogic ; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + opB : OUT signed (registerBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT registerFile + GENERIC ( + registerAddressBitNb : positive := 4; + dataBitNb : positive := 8 + ); + PORT ( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic ; + regWrite : IN std_ulogic ; + registersIn : IN signed ( dataBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic ; + opA : OUT signed ( dataBitNb-1 DOWNTO 0 ); + opB : OUT signed ( dataBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : alu USE ENTITY NanoBlaze.alu; +-- FOR ALL : aluBOpSelector USE ENTITY NanoBlaze.aluBOpSelector; +-- FOR ALL : registerFile USE ENTITY NanoBlaze.registerFile; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + portOut <= opA; + spadOut <= opA; + + -- HDL Embedded Text Block 2 eb2 + portAddr <= resize(unsigned(registerFileIn), portAddressBitNb); + scratchpadAddr <= resize(unsigned(registerFileIn), scratchpadAddressBitNb); + + + -- Instance port mappings. + I_ALU : alu + GENERIC MAP ( + aluCodeBitNb => aluCodeBitNb, + dataBitNb => registerBitNb + ) + PORT MAP ( + aluCode => aluCode, + cIn => cIn, + opA => opA, + opB => opB, + aluOut => aluOut, + cOut => cOut, + zero => zero + ); + I_bSel : aluBOpSelector + GENERIC MAP ( + registerBitNb => registerBitNb + ) + PORT MAP ( + instrData => instrData, + instrDataSel => instrDataSel, + portIn => portIn, + portInSel => portInSel, + registerFileIn => registerFileIn, + registerFileSel => registerFileSel, + scratchpadSel => scratchpadSel, + spadIn => spadIn, + opB => opB + ); + I_regs : registerFile + GENERIC MAP ( + registerAddressBitNb => registerAddressBitNb, + dataBitNb => registerBitNb + ) + PORT MAP ( + addrA => addrA, + addrB => addrB, + clock => clock, + regWrite => regWrite, + registersIn => aluOut, + reset => reset, + opA => opA, + opB => registerFileIn + ); + +END struct; + + + + +-- VHDL Entity NanoBlaze.branchStack.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY branchStack IS + GENERIC( + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5 + ); + PORT( + clock : IN std_ulogic; + prevPC : IN std_ulogic; + progCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic; + storePC : IN std_ulogic; + storedProgCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END branchStack ; + + + + + +ARCHITECTURE RTL OF branchStack IS + + subtype progCounterType is unsigned(progCounter'range); + type progCounterArrayType is array (0 to 2**stackPointerBitNb) of progCounterType; + signal progCounterArray : progCounterArrayType; + + signal writePointer : unsigned(stackPointerBitNb-1 downto 0); + signal readPointer : unsigned(stackPointerBitNb-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- stack pointers + updateStackPointer: process(reset, clock) + begin + if reset = '1' then + writePointer <= (others => '0'); + elsif rising_edge(clock) then + if storePC = '1' then + writePointer <= writePointer + 1; + elsif prevPC = '1' then + writePointer <= writePointer - 1; + end if; + end if; + end process updateStackPointer; + + readPointer <= writePointer - 1; + + ------------------------------------------------------------------------------ + -- program counters stack + updateStack: process(reset, clock) + begin + if rising_edge(clock) then + if storePc = '1' then + progCounterArray(to_integer(writePointer)) <= progCounter; + end if; + storedProgCounter <= progCounterArray(to_integer(readPointer)); + end if; + end process updateStack; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.controller.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY controller IS + GENERIC( + intCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + opCodeBitNb : positive := 5 + ); + PORT( + branchCond : IN std_ulogic_vector ( branchCondBitNb-1 DOWNTO 0 ); + cOut : IN std_ulogic; + clock : IN std_ulogic; + en : IN std_ulogic; + int : IN std_uLogic; + intCode : IN std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : IN std_ulogic_vector (opCodeBitNb-1 DOWNTO 0); + reset : IN std_ulogic; + twoRegInstr : IN std_ulogic; + zero : IN std_ulogic; + cIn : OUT std_ulogic; + incPC : OUT std_ulogic; + instrDataSel : OUT std_ulogic; + intAck : OUT std_ulogic; + loadInstrAddress : OUT std_ulogic; + loadStoredPC : OUT std_ulogic; + portInSel : OUT std_ulogic; + prevPC : OUT std_ulogic; + readStrobe : OUT std_uLogic; + regWrite : OUT std_ulogic; + registerFileSel : OUT std_ulogic; + scratchpadSel : OUT std_ulogic; + scratchpadWrite : OUT std_ulogic; + storePC : OUT std_ulogic; + writeStrobe : OUT std_uLogic + ); + +-- Declarations + +END controller ; + + + + + +ARCHITECTURE RTL OF controller IS + + signal en1, enInt: std_ulogic; + + constant opCodeLength : integer := 5; + subtype opCodeType is std_ulogic_vector(opCodeLength-1 downto 0); + constant opLoad : opCodeType := "00000"; + constant opInput : opCodeType := "00010"; + constant opFetch : opCodeType := "00011"; + constant opAnd : opCodeType := "00101"; + constant opOr : opCodeType := "00110"; + constant opXor : opCodeType := "00111"; + constant opTest : opCodeType := "01001"; + constant opComp : opCodeType := "01010"; + constant opAdd : opCodeType := "01100"; + constant opAddCy : opCodeType := "01101"; + constant opSub : opCodeType := "01110"; + constant opSubCy : opCodeType := "01111"; + constant opShRot : opCodeType := "10000"; + constant opRet : opCodeType := "10101"; + constant opOutput: opCodeType := "10110"; + constant opStore : opCodeType := "10111"; + constant opCall : opCodeType := "11000"; + constant opJump : opCodeType := "11010"; + constant opIntF : opCodeType := "11110"; + + constant branchConditionLength : integer := 3; + subtype branchConditionType is std_ulogic_vector(branchConditionLength-1 downto 0); + constant brAw : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + signal aluOpSel: std_ulogic; + signal regWriteEn: std_ulogic; + + signal flagsEn, flagsEnable: std_ulogic; + signal carrySaved: std_ulogic; + signal zeroSaved: std_ulogic; + + signal branchEnable1, branchEnable: std_ulogic; + signal discardOpCode: std_ulogic; + + signal updateIntFlag: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- Enable signal + buildEnable: process(reset, clock) + begin + if reset = '1' then + en1 <= '0'; + elsif rising_edge(clock) then + en1 <= '1'; + end if; + end process buildEnable; + + enInt <= en1 and en; -- don't enable very first instruction twice + + ------------------------------------------------------------------------------ + -- ALU controls + selectdataSource: process(opCode) + begin + aluOpSel <= '0'; + portInSel <= '0'; + scratchpadSel <= '0'; + case opCode(opCodeLength-1 downto 0) is + when opLoad => aluOpSel <= '1'; + when opInput => portInSel <= '1'; + when opFetch => scratchpadSel <= '1'; + when opAnd => aluOpSel <= '1'; + when opOr => aluOpSel <= '1'; + when opXor => aluOpSel <= '1'; + when opTest => aluOpSel <= '1'; + when opComp => aluOpSel <= '1'; + when opAdd => aluOpSel <= '1'; + when opAddCy => aluOpSel <= '1'; + when opSub => aluOpSel <= '1'; + when opSubCy => aluOpSel <= '1'; + when opShRot => aluOpSel <= '1'; + when others => aluOpSel <= '-'; + portInSel <= '-'; + scratchpadSel <= '-'; + end case; + end process selectdataSource; + + registerFileSel <= aluOpSel and twoRegInstr; + instrDataSel <= aluOpSel and (not twoRegInstr); + + regWriteEn <= enInt and (not discardOpCode); + + regWriteTable: process(opCode, regWriteEn) + begin + case opCode(opCodeLength-1 downto 0) is + when opLoad => regWrite <= regWriteEn; + when opInput => regWrite <= regWriteEn; + when opFetch => regWrite <= regWriteEn; + when opAnd => regWrite <= regWriteEn; + when opOr => regWrite <= regWriteEn; + when opXor => regWrite <= regWriteEn; + when opAdd => regWrite <= regWriteEn; + when opAddCy => regWrite <= regWriteEn; + when opSub => regWrite <= regWriteEn; + when opSubCy => regWrite <= regWriteEn; + when opShRot => regWrite <= regWriteEn; + when others => regWrite <= '0'; + end case; + end process regWriteTable; + + ------------------------------------------------------------------------------ + -- I/O controls + readStrobe <= enInt when (opCode = opInput) and (discardOpCode = '0') + else '0'; + writeStrobe <= enInt when (opCode = opOutput) and (discardOpCode = '0') + else '0'; + + ------------------------------------------------------------------------------ + -- scratchpad controls + scratchpadWrite <= '1' when opCode = opStore else '0'; + + ------------------------------------------------------------------------------ + -- Carry logic + flagsEn <= enInt and (not branchEnable); + + flagsEnableTable: process(opCode, flagsEn) + begin + case opCode(opCodeLength-1 downto 0) is + when opAnd => flagsEnable <= flagsEn; + when opOr => flagsEnable <= flagsEn; + when opXor => flagsEnable <= flagsEn; + when opTest => flagsEnable <= flagsEn; + when opComp => flagsEnable <= flagsEn; + when opAdd => flagsEnable <= flagsEn; + when opAddCy => flagsEnable <= flagsEn; + when opSub => flagsEnable <= flagsEn; + when opSubCy => flagsEnable <= flagsEn; + when opShRot => flagsEnable <= flagsEn; + when others => flagsEnable <= '0'; + end case; + end process flagsEnableTable; + + saveCarries: process(reset, clock) + begin + if reset = '1' then + carrySaved <= '0'; + zeroSaved <= '0'; + elsif rising_edge(clock) then + if flagsEnable = '1' then + carrySaved <= cOut; + zeroSaved <= zero; + end if; + end if; + end process saveCarries; + + cIn <= carrySaved; + + ------------------------------------------------------------------------------ + -- Program counter controls + checkBranchCondition: process(branchCond, zeroSaved, carrySaved) + begin + case branchCond(branchConditionLength-1 downto 0) is + when brAw => branchEnable1 <= '1'; + when brZ => branchEnable1 <= zeroSaved; + when brNZ => branchEnable1 <= not zeroSaved; + when brC => branchEnable1 <= carrySaved; + when brNC => branchEnable1 <= not carrySaved; + when others => branchEnable1 <= '-'; + end case; + end process checkBranchCondition; + + branchEnableTable: process(opCode, branchEnable1, discardOpCode) + begin + if discardOpCode = '0' then + case opCode(opCodeLength-1 downto 0) is + when opRet => branchEnable <= branchEnable1; + when opCall => branchEnable <= branchEnable1; + when opJump => branchEnable <= branchEnable1; + when others => branchEnable <= '0'; + end case; + else + branchEnable <= '0'; + end if; + end process branchEnableTable; + + progCounterControlTable: process(opCode, enInt, branchEnable) + begin + incPC <= enInt; + loadInstrAddress <= '0'; + loadStoredPC <= '0'; + case opCode(opCodeLength-1 downto 0) is + when opRet => incPC <= not branchEnable; + loadStoredPC <= enInt and branchEnable; + when opCall => incPC <= not branchEnable; + loadInstrAddress <= enInt and branchEnable; + when opJump => incPC <= not branchEnable; + loadInstrAddress <= enInt and branchEnable; + when others => null; + end case; + end process progCounterControlTable; + + -- If a branch condition is met, the next operation has to be discarded. + -- This is due to the synchronous operation of the program ROM: the + -- instructions are provided one clock period after the program counter. + -- so while the branch operation is processed, the next instruction is + -- already being fetched. + delayBranchEnable: process(reset, clock) + begin + if reset = '1' then + discardOpCode <= '0'; + elsif rising_edge(clock) then + discardOpCode <= branchEnable; + end if; + end process delayBranchEnable; + + ------------------------------------------------------------------------------ + -- Stack pointer controls + pcStackControlTable: process(discardOpCode, opCode, enInt) + begin + storePC <= '0'; + prevPC <= '0'; + if discardOpCode = '0' then + case opCode(opCodeLength-1 downto 0) is + when opRet => prevPC <= enInt; + when opCall => storePC <= enInt; + when others => null; + end case; + end if; + end process pcStackControlTable; + + + ------------------------------------------------------------------------------ + -- interrupt control + updateIntFlag <= '1' when opCode = opIntF else '0'; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.instructionDecoder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY instructionDecoder IS + GENERIC( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + instructionBitNb : positive := 18; + programCounterBitNb : positive := 10; + opCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + intCodeBitNb : positive := 5; + spadAddressBitNb : natural := 4; + portAddressBitNb : positive := 8 + ); + PORT( + instruction : IN std_ulogic_vector ( instructionBitNb-1 DOWNTO 0 ); + addrA : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : OUT std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + branchCond : OUT std_ulogic_vector (branchCondBitNb-1 DOWNTO 0); + instrAddress : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + instrData : OUT signed ( registerBitNb-1 DOWNTO 0 ); + intCode : OUT std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : OUT std_ulogic_vector ( opCodeBitNb-1 DOWNTO 0 ); + portAddress : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portIndexedSel : OUT std_ulogic; + spadAddress : OUT unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + spadIndexedSel : OUT std_ulogic; + twoRegInstr : OUT std_ulogic + ); + +-- Declarations + +END instructionDecoder ; + + + + + +ARCHITECTURE RTL OF instructionDecoder IS + + constant opCodeIndexH : integer := instruction'high; + constant opCodeIndexL : integer := opCodeIndexH - opCodeBitNb + 1; + + constant twoRegInstrIndex : integer := opCodeIndexL - 1; + constant ioAddrIndexed : integer := twoRegInstrIndex; + + constant addrAIndexH : integer := twoRegInstrIndex - 1; + constant addrAIndexL : integer := addrAIndexH - registerAddressBitNb + 1; + + constant immediateDataIndexH : integer := registerBitNb-1; + constant immediateDataIndexL : integer := 0; + constant addrBIndexH : integer := addrAIndexL - 1; + constant addrBIndexL : integer := addrBIndexH - registerAddressBitNb + 1; + + constant aluCodeIndexH : integer := opCodeIndexH; + constant aluCodeIndexL : integer := aluCodeIndexH - aluCodeBitNb + 1; + + constant portAddressH : integer := registerBitNb-1; + constant portAddressL : integer := portAddressH-portAddressBitNb+1; + constant spadAddressH : integer := registerBitNb-1; + constant spadAddressL : integer := spadAddressH-spadAddressBitNb+1; + + constant branchCondH : integer := opCodeIndexL-1; + constant branchCondL : integer := branchCondH-branchCondBitNb+1; + +BEGIN + ------------------------------------------------------------------------------ + -- ALU control + aluCode <= + instruction(aluCodeIndexH downto aluCodeIndexL) + when instruction(aluCodeIndexH) = '0' else + '1' & instruction(aluCodeBitNb-2 downto 0); + opCode <= instruction(opCodeIndexH downto opCodeIndexL); + twoRegInstr <= instruction(twoRegInstrIndex); + addrA <= unsigned(instruction(addrAIndexH downto addrAIndexL)); + addrB <= unsigned(instruction(addrBIndexH downto addrBIndexL)); + instrData <= signed(instruction(immediateDataIndexH downto immediateDataIndexL)); + + ------------------------------------------------------------------------------ + -- I/O control + portIndexedSel <= instruction(ioAddrIndexed); + portAddress <= unsigned(instruction(portAddressH downto portAddressL)); + + ------------------------------------------------------------------------------ + -- scratchpad control + spadIndexedSel <= instruction(ioAddrIndexed); + spadAddress <= unsigned(instruction(spadAddressH downto spadAddressL)); + + ------------------------------------------------------------------------------ + -- branch control + branchCond <= instruction(branchCondH downto branchCondL); + instrAddress <= unsigned(instruction(instrAddress'range)); + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.programCounter.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY programCounter IS + GENERIC( + programCounterBitNb : positive := 10 + ); + PORT( + clock : IN std_ulogic; + incPC : IN std_ulogic; + instrAddress : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + loadInstrAddress : IN std_ulogic; + loadStoredPC : IN std_ulogic; + reset : IN std_ulogic; + storedProgCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END programCounter ; + + + + + +ARCHITECTURE RTL OF programCounter IS + + signal pCounter: unsigned(progCounter'range); + +BEGIN + + updateProgramCounter: process(reset, clock) + begin + if reset = '1' then + pCounter <= (others => '0'); + elsif rising_edge(clock) then + if incPC = '1' then + pCounter <= pCounter + 1; + elsif loadInstrAddress = '1' then + pCounter <= instrAddress; + elsif loadStoredPC = '1' then + pCounter <= storedProgCounter; + end if; + end if; + end process updateProgramCounter; + + progCounter <= pCounter; + +END ARCHITECTURE RTL; + + + + +-- VHDL Entity NanoBlaze.scratchpad.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:44:17 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY scratchpad IS + GENERIC( + registerBitNb : positive := 8; + spadAddressBitNb : natural := 4 + ); + PORT( + addr : IN unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic; + dataIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic; + write : IN std_ulogic; + dataOut : OUT signed ( registerBitNb-1 DOWNTO 0 ) + ); + +-- Declarations + +END scratchpad ; + + + + + +ARCHITECTURE RTL OF scratchpad IS + + subtype memoryWordType is signed(dataOut'range); + type memoryArrayType is array (0 to 2**addr'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType; + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if write = '1' then + memoryArray(to_integer(addr)) <= dataIn; + end if; + end if; + end process; + + dataOut <= memoryArray(to_integer(addr)); + +END ARCHITECTURE RTL; + + + + +-- +-- VHDL Architecture NanoBlaze.nanoProcessor.struct +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 07:38:43 11.11.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY NanoBlaze; + +ARCHITECTURE struct OF nanoProcessor IS + + -- Architecture declarations + constant aluCodeBitNb: positive := 5; + constant opCodeBitNb: positive := 5; + constant branchCondBitNb: positive := 3; + constant intCodeBitNb: positive := 5; + + -- Internal signal declarations + SIGNAL addrA : unsigned( registerAddressBitNb-1 DOWNTO 0 ); + SIGNAL addrB : unsigned( registerAddressBitNb-1 DOWNTO 0 ); + SIGNAL aluCode : std_ulogic_vector( aluCodeBitNb-1 DOWNTO 0 ); + SIGNAL branchCond : std_ulogic_vector(branchCondBitNb-1 DOWNTO 0); + SIGNAL cIn : std_ulogic; + SIGNAL cOut : std_ulogic; + SIGNAL incPC : std_ulogic; + SIGNAL instrAddress : unsigned( programCounterBitNb-1 DOWNTO 0 ); + SIGNAL instrData : signed( registerBitNb-1 DOWNTO 0 ); + SIGNAL instrDataSel : std_ulogic; + SIGNAL instrString : string(1 TO 16); + SIGNAL intCode : std_ulogic_vector( intCodeBitNb-1 DOWNTO 0 ); + SIGNAL loadInstrAddress : std_ulogic; + SIGNAL loadStoredPC : std_ulogic; + SIGNAL opCode : std_ulogic_vector( opCodeBitNb-1 DOWNTO 0 ); + SIGNAL portIn : signed( registerBitNb-1 DOWNTO 0 ); + SIGNAL portInSel : std_ulogic; + SIGNAL portIndexedSel : std_ulogic; + SIGNAL portInstrAddress : unsigned(addressBitNb-1 DOWNTO 0); + SIGNAL portOut : signed( registerBitNb-1 DOWNTO 0 ); + SIGNAL portRegAddress : unsigned(addressBitNb-1 DOWNTO 0); + SIGNAL prevPC : std_ulogic; + SIGNAL regWrite : std_ulogic; + SIGNAL registerFileSel : std_ulogic; + SIGNAL scratchpadSel : std_ulogic; + SIGNAL scratchpadWrite : std_ulogic; + SIGNAL spadAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0); + SIGNAL spadIn : signed(registerBitNb-1 DOWNTO 0); + SIGNAL spadIndexedSel : std_ulogic; + SIGNAL spadInstrAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0); + SIGNAL spadOut : signed(registerBitNb-1 DOWNTO 0); + SIGNAL spadRegAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0); + SIGNAL storePC : std_ulogic; + SIGNAL storedProgCounter : unsigned( programCounterBitNb-1 DOWNTO 0 ); + SIGNAL twoRegInstr : std_ulogic; + SIGNAL zero : std_ulogic; + + -- Implicit buffer signal declarations + SIGNAL progCounter_internal : unsigned ( programCounterBitNb-1 DOWNTO 0 ); + + + -- Component Declarations + COMPONENT aluAndRegs + GENERIC ( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + portAddressBitNb : positive := 8; + scratchpadAddressBitNb : natural := 4 + ); + PORT ( + addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : IN std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + cIn : IN std_ulogic ; + clock : IN std_ulogic ; + instrData : IN signed ( registerBitNb-1 DOWNTO 0 ); + instrDataSel : IN std_ulogic ; + portIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + portInSel : IN std_ulogic ; + regWrite : IN std_ulogic ; + registerFileSel : IN std_ulogic ; + reset : IN std_ulogic ; + scratchpadSel : IN std_ulogic ; + spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + cOut : OUT std_ulogic ; + portAddr : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + scratchpadAddr : OUT unsigned (scratchpadAddressBitNb-1 DOWNTO 0); + spadOut : OUT signed ( registerBitNb-1 DOWNTO 0 ); + zero : OUT std_ulogic + ); + END COMPONENT; + COMPONENT branchStack + GENERIC ( + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5 + ); + PORT ( + clock : IN std_ulogic ; + prevPC : IN std_ulogic ; + progCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic ; + storePC : IN std_ulogic ; + storedProgCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + COMPONENT controller + GENERIC ( + intCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + opCodeBitNb : positive := 5 + ); + PORT ( + branchCond : IN std_ulogic_vector ( branchCondBitNb-1 DOWNTO 0 ); + cOut : IN std_ulogic ; + clock : IN std_ulogic ; + en : IN std_ulogic ; + int : IN std_uLogic ; + intCode : IN std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : IN std_ulogic_vector (opCodeBitNb-1 DOWNTO 0); + reset : IN std_ulogic ; + twoRegInstr : IN std_ulogic ; + zero : IN std_ulogic ; + cIn : OUT std_ulogic ; + incPC : OUT std_ulogic ; + instrDataSel : OUT std_ulogic ; + intAck : OUT std_ulogic ; + loadInstrAddress : OUT std_ulogic ; + loadStoredPC : OUT std_ulogic ; + portInSel : OUT std_ulogic ; + prevPC : OUT std_ulogic ; + readStrobe : OUT std_uLogic ; + regWrite : OUT std_ulogic ; + registerFileSel : OUT std_ulogic ; + scratchpadSel : OUT std_ulogic ; + scratchpadWrite : OUT std_ulogic ; + storePC : OUT std_ulogic ; + writeStrobe : OUT std_uLogic + ); + END COMPONENT; + COMPONENT instructionDecoder + GENERIC ( + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + aluCodeBitNb : positive := 5; + instructionBitNb : positive := 18; + programCounterBitNb : positive := 10; + opCodeBitNb : positive := 5; + branchCondBitNb : positive := 3; + intCodeBitNb : positive := 5; + spadAddressBitNb : natural := 4; + portAddressBitNb : positive := 8 + ); + PORT ( + instruction : IN std_ulogic_vector ( instructionBitNb-1 DOWNTO 0 ); + addrA : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + addrB : OUT unsigned ( registerAddressBitNb-1 DOWNTO 0 ); + aluCode : OUT std_ulogic_vector ( aluCodeBitNb-1 DOWNTO 0 ); + branchCond : OUT std_ulogic_vector (branchCondBitNb-1 DOWNTO 0); + instrAddress : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + instrData : OUT signed ( registerBitNb-1 DOWNTO 0 ); + intCode : OUT std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ); + opCode : OUT std_ulogic_vector ( opCodeBitNb-1 DOWNTO 0 ); + portAddress : OUT unsigned (portAddressBitNb-1 DOWNTO 0); + portIndexedSel : OUT std_ulogic ; + spadAddress : OUT unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + spadIndexedSel : OUT std_ulogic ; + twoRegInstr : OUT std_ulogic + ); + END COMPONENT; + COMPONENT programCounter + GENERIC ( + programCounterBitNb : positive := 10 + ); + PORT ( + clock : IN std_ulogic ; + incPC : IN std_ulogic ; + instrAddress : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + loadInstrAddress : IN std_ulogic ; + loadStoredPC : IN std_ulogic ; + reset : IN std_ulogic ; + storedProgCounter : IN unsigned ( programCounterBitNb-1 DOWNTO 0 ); + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + COMPONENT scratchpad + GENERIC ( + registerBitNb : positive := 8; + spadAddressBitNb : natural := 4 + ); + PORT ( + addr : IN unsigned ( spadAddressBitNb-1 DOWNTO 0 ); + clock : IN std_ulogic ; + dataIn : IN signed ( registerBitNb-1 DOWNTO 0 ); + reset : IN std_ulogic ; + write : IN std_ulogic ; + dataOut : OUT signed ( registerBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : aluAndRegs USE ENTITY NanoBlaze.aluAndRegs; +-- FOR ALL : branchStack USE ENTITY NanoBlaze.branchStack; +-- FOR ALL : controller USE ENTITY NanoBlaze.controller; +-- FOR ALL : instructionDecoder USE ENTITY NanoBlaze.instructionDecoder; +-- FOR ALL : programCounter USE ENTITY NanoBlaze.programCounter; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + dataAddress <= portInstrAddress when portIndexedSel = '0' else portRegAddress; + + -- HDL Embedded Text Block 2 eb2 + dataOut <= std_ulogic_vector(portOut); + portIn <= signed(dataIn); + + -- HDL Embedded Text Block 3 eb3 + spadAddress <= spadInstrAddress when spadIndexedSel = '0' else spadRegAddress; + + -- HDL Embedded Text Block 4 eb4 + -- pragma translate_off + + process(instruction) + + constant bitsPerHexDigit : positive := 4; + + function pad(inString : string; outLength : positive) return string is + variable outString : string(1 to outLength); + begin + outString := (others => ' '); + outString(inString'range) := inString; + return outString; + end function pad; + + function hexDigitNb(bitNb : positive) return positive is + begin + return (bitNb-1)/bitsPerHexDigit+1; + end function hexDigitNb; + + function to01(nineValued : unsigned) return unsigned is + variable twoValued : unsigned(nineValued'range); + begin + twoValued := (others => '0'); + for index in nineValued'range loop + if (nineValued(index) = '1') or (nineValued(index) = 'H') then + twoValued(index) := '1'; + end if; + end loop; + return twoValued; + end function to01; + + variable opCode : unsigned(1+opCodeBitNb-1 downto 0); + variable destRegister : unsigned(registerAddressBitNb-1 downto 0); + variable destRegisterString : string(1 to 1+hexDigitNb(registerAddressBitNb)); + variable sourceRegister : unsigned(registerAddressBitNb-1 downto 0); + variable sourceRegisterString : string(1 to 1+hexDigitNb(registerAddressBitNb)); + variable sourceConstant : unsigned(registerBitNb-1 downto 0); + variable sourceConstantString : string(1 to hexDigitNb(registerBitNb)); + variable branchAddress : unsigned(programCounterBitNb-1 downto 0); + variable branchAddressString : string(1 to hexDigitNb(programCounterBitNb)); + variable branchKind : unsigned(1 downto 0); + variable shRotCin : unsigned(2 downto 0); + variable shRotDir: std_ulogic; + + function toHexDigit(binary : unsigned(bitsPerHexDigit-1 downto 0)) return character is + begin + if binary <= 9 then + return character'val(character'pos('0') + to_integer(to01(binary))); + else + return character'val(character'pos('A') + to_integer(to01(binary)) - 10); + end if; + end function toHexDigit; + + function toHexString(binary : unsigned) return string is + variable hexString : string(1 to hexDigitNb(binary'length)); + begin + for index in hexString'high-1 downto 0 loop + hexString(hexString'high-index) := toHexDigit( + resize(shift_right(binary, bitsPerHexDigit*index), bitsPerHexDigit) + ); + end loop; + return hexString; + end function toHexString; + + begin + + opCode := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length), + opCode'length + ); + destRegister := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-destRegister'length), + destRegister'length + ); + destRegisterString := 's' & toHexDigit(destRegister); + sourceRegister := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-destRegister'length-sourceRegister'length), + sourceRegister'length + ); + sourceRegisterString := 's' & toHexDigit(sourceRegister); + sourceConstant := resize(unsigned(instruction), sourceConstant'length); + sourceConstantString := toHexString(sourceConstant); + branchKind := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-branchKind'length), + branchKind'length + ); + branchAddress := resize(unsigned(instruction), branchAddress'length); + branchAddressString := toHexString(branchAddress); + shRotCin := resize(shift_right(unsigned(instruction), 1), shRotCin'length); + shRotDir := instruction(0); + + case opCode is + when "000000" => instrString <= pad("LOAD " & destRegisterString & " " & sourceConstantString, instrString'length); + when "000001" => instrString <= pad("LOAD " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "000100" => instrString <= pad("INPUT " & destRegisterString & " " & sourceConstantString, instrString'length); + when "000101" => instrString <= pad("INPUT " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "000110" => instrString <= pad("FETCH " & destRegisterString & " " & sourceConstantString, instrString'length); + when "000111" => instrString <= pad("FETCH " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "001010" => instrString <= pad("AND " & destRegisterString & " " & sourceConstantString, instrString'length); + when "001011" => instrString <= pad("AND " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "001100" => instrString <= pad("OR " & destRegisterString & " " & sourceConstantString, instrString'length); + when "001101" => instrString <= pad("OR " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "001110" => instrString <= pad("XOR " & destRegisterString & " " & sourceConstantString, instrString'length); + when "001111" => instrString <= pad("XOR " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "010010" => instrString <= pad("TEST " & destRegisterString & " " & sourceConstantString, instrString'length); + when "010011" => instrString <= pad("TEST " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "010100" => instrString <= pad("COMP " & destRegisterString & " " & sourceConstantString, instrString'length); + when "010101" => instrString <= pad("COMP " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011000" => instrString <= pad("ADD " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011001" => instrString <= pad("ADD " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011010" => instrString <= pad("ADDCY " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011011" => instrString <= pad("ADDCY " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011100" => instrString <= pad("SUB " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011101" => instrString <= pad("SUB " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "011110" => instrString <= pad("SUBCY " & destRegisterString & " " & sourceConstantString, instrString'length); + when "011111" => instrString <= pad("SUBCY " & destRegisterString & " " & sourceRegisterString, instrString'length); + when "100000" => + case shRotCin is + when "000" => instrString <= pad("SLA " & destRegisterString, instrString'length); + when "001" => instrString <= pad("RL " & destRegisterString, instrString'length); + when "010" => instrString <= pad("SLX " & destRegisterString, instrString'length); + when "011" => + case shRotDir is + when '0' => instrString <= pad("SL0 " & destRegisterString, instrString'length); + when '1' => instrString <= pad("SL1 " & destRegisterString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when "100" => instrString <= pad("SRA " & destRegisterString, instrString'length); + when "101" => instrString <= pad("SRX " & destRegisterString, instrString'length); + when "110" => instrString <= pad("RR " & destRegisterString, instrString'length); + when "111" => + case shRotDir is + when '0' => instrString <= pad("SR0 " & destRegisterString, instrString'length); + when '1' => instrString <= pad("SR1 " & destRegisterString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when others => instrString <= pad("--------", instrString'length); + end case; + when "101100" => instrString <= pad("OUTPUT " & destRegisterString & " " & sourceConstantString, instrString'length); + when "101101" => instrString <= pad("OUTPUT " & destRegisterString & " (" & sourceRegisterString & ")", instrString'length); + when "101110" => instrString <= pad("STORE " & destRegisterString & " " & sourceConstantString, instrString'length); + when "101111" => instrString <= pad("STORE " & destRegisterString & " (" & sourceRegisterString & ")", instrString'length); + when "101010" => instrString <= pad("RET", instrString'length); + when "101011" => + case branchKind is + when "00" => instrString <= pad("RET Z", instrString'length); + when "01" => instrString <= pad("RET NZ", instrString'length); + when "10" => instrString <= pad("RET C", instrString'length); + when "11" => instrString <= pad("RET NC", instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when "110000" => instrString <= pad("CALL " & branchAddressString, instrString'length); + when "110001" => + case branchKind is + when "00" => instrString <= pad("CALL Z " & branchAddressString, instrString'length); + when "01" => instrString <= pad("CALL NZ " & branchAddressString, instrString'length); + when "10" => instrString <= pad("CALL C " & branchAddressString, instrString'length); + when "11" => instrString <= pad("CALL NC " & branchAddressString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when "110100" => instrString <= pad("JUMP " & branchAddressString, instrString'length); + when "110101" => + case branchKind is + when "00" => instrString <= pad("JUMP Z " & branchAddressString, instrString'length); + when "01" => instrString <= pad("JUMP NZ " & branchAddressString, instrString'length); + when "10" => instrString <= pad("JUMP C " & branchAddressString, instrString'length); + when "11" => instrString <= pad("JUMP NC " & branchAddressString, instrString'length); + when others => instrString <= pad("--------", instrString'length); + end case; + when others => instrString <= pad("--------", instrString'length); + end case; + + end process; + + -- pragma translate_on + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- Instance port mappings. + I_alu : aluAndRegs + GENERIC MAP ( + registerBitNb => registerBitNb, + registerAddressBitNb => registerAddressBitNb, + aluCodeBitNb => aluCodeBitNb, + portAddressBitNb => addressBitNb, + scratchpadAddressBitNb => scratchpadAddressBitNb + ) + PORT MAP ( + addrA => addrA, + addrB => addrB, + aluCode => aluCode, + cIn => cIn, + clock => clock, + instrData => instrData, + instrDataSel => instrDataSel, + portIn => portIn, + portInSel => portInSel, + regWrite => regWrite, + registerFileSel => registerFileSel, + reset => reset, + scratchpadSel => scratchpadSel, + spadIn => spadIn, + cOut => cOut, + portAddr => portRegAddress, + portOut => portOut, + scratchpadAddr => spadRegAddress, + spadOut => spadOut, + zero => zero + ); + I_BR : branchStack + GENERIC MAP ( + programCounterBitNb => programCounterBitNb, + stackPointerBitNb => stackPointerBitNb + ) + PORT MAP ( + clock => clock, + prevPC => prevPC, + progCounter => progCounter_internal, + reset => reset, + storePC => storePC, + storedProgCounter => storedProgCounter + ); + I_ctrl : controller + GENERIC MAP ( + intCodeBitNb => 5, + branchCondBitNb => branchCondBitNb, + opCodeBitNb => opCodeBitNb + ) + PORT MAP ( + branchCond => branchCond, + cOut => cOut, + clock => clock, + en => en, + int => int, + intCode => intCode, + opCode => opCode, + reset => reset, + twoRegInstr => twoRegInstr, + zero => zero, + cIn => cIn, + incPC => incPC, + instrDataSel => instrDataSel, + intAck => intAck, + loadInstrAddress => loadInstrAddress, + loadStoredPC => loadStoredPC, + portInSel => portInSel, + prevPC => prevPC, + readStrobe => readStrobe, + regWrite => regWrite, + registerFileSel => registerFileSel, + scratchpadSel => scratchpadSel, + scratchpadWrite => scratchpadWrite, + storePC => storePC, + writeStrobe => writeStrobe + ); + I_instr : instructionDecoder + GENERIC MAP ( + registerBitNb => registerBitNb, + registerAddressBitNb => registerAddressBitNb, + aluCodeBitNb => aluCodeBitNb, + instructionBitNb => instructionBitNb, + programCounterBitNb => programCounterBitNb, + opCodeBitNb => opCodeBitNb, + branchCondBitNb => branchCondBitNb, + intCodeBitNb => 5, + spadAddressBitNb => scratchpadAddressBitNb, + portAddressBitNb => addressBitNb + ) + PORT MAP ( + instruction => instruction, + addrA => addrA, + addrB => addrB, + aluCode => aluCode, + branchCond => branchCond, + instrAddress => instrAddress, + instrData => instrData, + intCode => intCode, + opCode => opCode, + portAddress => portInstrAddress, + portIndexedSel => portIndexedSel, + spadAddress => spadInstrAddress, + spadIndexedSel => spadIndexedSel, + twoRegInstr => twoRegInstr + ); + I_PC : programCounter + GENERIC MAP ( + programCounterBitNb => programCounterBitNb + ) + PORT MAP ( + clock => clock, + incPC => incPC, + instrAddress => instrAddress, + loadInstrAddress => loadInstrAddress, + loadStoredPC => loadStoredPC, + reset => reset, + storedProgCounter => storedProgCounter, + progCounter => progCounter_internal + ); + + g_scratchpad: IF scratchpadAddressBitNb > 0 GENERATE + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : scratchpad USE ENTITY NanoBlaze.scratchpad; + -- pragma synthesis_on + + BEGIN + I_sPad : scratchpad + GENERIC MAP ( + registerBitNb => registerBitNb, + spadAddressBitNb => scratchpadAddressBitNb + ) + PORT MAP ( + addr => spadAddress, + clock => clock, + dataIn => spadOut, + reset => reset, + write => scratchpadWrite, + dataOut => spadIn + ); + END GENERATE g_scratchpad; + + -- Implicit buffered output assignments + progCounter <= progCounter_internal; + +END struct; + + + + +-- +-- VHDL Architecture SystemOnChip.beamerSoc.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:02:29 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; +-- LIBRARY AhbLite; + use work.ahbLite.all; + +-- LIBRARY AhbLiteComponents; +-- LIBRARY NanoBlaze; +-- LIBRARY SystemOnChip; + +ARCHITECTURE struct OF beamerSoc IS + + -- Architecture declarations + constant programCounterBitNb: positive := 10; + constant instructionBitNb: positive := 26; + constant stackPointerBitNb: positive := 4; + constant registerAddressBitNb: positive := 4; + constant scratchpadAddressBitNb: natural := 0; + + constant signalBitNb: positive := 16; + constant updatePeriodBitNb : positive := 16; + + constant gpioIndex: positive := 1; + constant uartIndex: positive := gpioIndex+1; + constant beamerIndex: positive := uartIndex+1; + + constant ahbMemoryLocation : ahbMemoryLocationVector := ( + gpioIndex => ( + baseAddress => 16#0000#, + addressMask => 16#10000# - 16#0002# + ), + uartIndex => ( + baseAddress => 16#0010#, + addressMask => 16#10000# - 16#0004# + ), + beamerIndex => ( + baseAddress => 16#0020#, + addressMask => 16#10000# - 16#0004# + ), + others => ( + baseAddress => 16#FFFF#, + addressMask => 16#0000# + ) + ); + + -- Internal signal declarations + SIGNAL upEn : std_ulogic; + SIGNAL int : std_uLogic; + SIGNAL upAddress : unsigned(ahbAddressBitNb-1 DOWNTO 0); + SIGNAL upDataOut : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL upDataIn : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL upReadStrobe : std_uLogic; + SIGNAL upWriteStrobe : std_uLogic; + SIGNAL hAddr : unsigned(ahbAddressBitNb-1 DOWNTO 0); + SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0); + SIGNAL hSize : std_ulogic_vector(ahbSizeBitNb-1 DOWNTO 0); + SIGNAL hBurst : std_ulogic_vector(ahbBurstBitNb-1 DOWNTO 0); + SIGNAL hProt : std_ulogic_vector(ahbProtBitNb-1 DOWNTO 0); + SIGNAL hWrite : std_uLogic; + SIGNAL hReady : std_uLogic; + SIGNAL hMastLock : std_uLogic; + SIGNAL hResp : std_uLogic; + SIGNAL hClk : std_uLogic; + SIGNAL hReset_n : std_uLogic; + SIGNAL hSelV : std_ulogic_vector(1 TO ahbSlaveNb); + SIGNAL hRDataV : ahbDataVector; + SIGNAL hReadyV : std_logic_vector(1 TO ahbSlaveNb); + SIGNAL hRespV : std_logic_vector(1 TO ahbSlaveNb); + SIGNAL hSelGpio : std_uLogic; + SIGNAL hRespGpio : std_uLogic; + SIGNAL hReadyGpio : std_uLogic; + SIGNAL hRDataGpio : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hRDataBeamer : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hRDataUart : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0); + SIGNAL hSelBeamer : std_uLogic; + SIGNAL hSelUart : std_uLogic; + SIGNAL hRespUart : std_uLogic; + SIGNAL hRespBeamer : std_uLogic; + SIGNAL hReadyBeamer : std_uLogic; + SIGNAL hReadyUart : std_uLogic; + SIGNAL intAck : std_ulogic; + SIGNAL instruction : std_ulogic_vector(instructionBitNb-1 DOWNTO 0); + SIGNAL programCounter : unsigned(programCounterBitNb-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT ahbDecoder + GENERIC ( + ahbMemoryLocation : ahbMemoryLocationVector + ); + PORT ( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hSel : OUT std_ulogic_vector (1 TO ahbSlaveNb) + ); + END COMPONENT; + COMPONENT ahbMasterInterface + PORT ( + clock : IN std_ulogic ; + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic ; + hResp : IN std_uLogic ; + pAddress : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + pDataOut : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + pReadStrobe : IN std_uLogic ; + pWriteStrobe : IN std_uLogic ; + reset : IN std_ulogic ; + hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hBurst : OUT std_ulogic_vector (ahbBurstBitNb-1 DOWNTO 0); + hClk : OUT std_uLogic ; + hMastLock : OUT std_uLogic ; + hProt : OUT std_ulogic_vector (ahbProtBitNb-1 DOWNTO 0); + hReset_n : OUT std_uLogic ; + hSize : OUT std_ulogic_vector (ahbSizeBitNb-1 DOWNTO 0); + hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : OUT std_uLogic ; + pDataIn : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT ahbMultiplexor + PORT ( + hRDataV : IN ahbDataVector ; + hReadyV : IN std_logic_vector (1 TO ahbSlaveNb); + hRespV : IN std_logic_vector (1 TO ahbSlaveNb); + hSel : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic + ); + END COMPONENT; + COMPONENT ahbMuxConnector + GENERIC ( + index : positive := 1 + ); + PORT ( + hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : IN std_uLogic ; + hResp : IN std_uLogic ; + hSelV : IN std_ulogic_vector ( 1 TO ahbSlaveNb ); + hRDataV : OUT ahbDataVector ; + hReadyV : OUT std_logic_vector (1 TO ahbSlaveNb); + hRespV : OUT std_logic_vector (1 TO ahbSlaveNb); + hSel : OUT std_uLogic + ); + END COMPONENT; + COMPONENT ahbGpio + GENERIC ( + ioNb : positive := 8 + ); + PORT ( + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic ; + hReset_n : IN std_uLogic ; + hSel : IN std_uLogic ; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic ; + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic ; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT ahbUart + GENERIC ( + txFifoDepth : positive := 8; + rxFifoDepth : positive := 1 + ); + PORT ( + RxD : IN std_ulogic ; + hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 ); + hClk : IN std_uLogic ; + hReset_n : IN std_uLogic ; + hSel : IN std_uLogic ; + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hWrite : IN std_uLogic ; + TxD : OUT std_ulogic ; + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hReady : OUT std_uLogic ; + hResp : OUT std_uLogic + ); + END COMPONENT; + COMPONENT nanoProcessor + GENERIC ( + addressBitNb : positive := 8; + registerBitNb : positive := 8; + registerAddressBitNb : positive := 4; + programCounterBitNb : positive := 10; + stackPointerBitNb : positive := 5; + instructionBitNb : positive := 18; + scratchpadAddressBitNb : natural := 4 + ); + PORT ( + clock : IN std_ulogic ; + dataIn : IN std_ulogic_vector (registerBitNb-1 DOWNTO 0); + en : IN std_ulogic ; + instruction : IN std_ulogic_vector (instructionBitNb-1 DOWNTO 0); + int : IN std_uLogic ; + reset : IN std_ulogic ; + dataAddress : OUT unsigned (addressBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (registerBitNb-1 DOWNTO 0); + intAck : OUT std_ulogic ; + progCounter : OUT unsigned ( programCounterBitNb-1 DOWNTO 0 ); + readStrobe : OUT std_uLogic ; + writeStrobe : OUT std_uLogic + ); + END COMPONENT; + COMPONENT ahbBeamer + GENERIC ( + patternAddressBitNb : positive := 9; + testOutBitNb : positive := 16 + ); + PORT ( + outX : OUT std_ulogic ; + hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0); + outY : OUT std_ulogic ; + hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + selSinCos : IN std_ulogic ; + testOut : OUT std_ulogic_vector (1 TO testOutBitNb); + hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0); + hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0); + hWrite : IN std_ulogic ; + hSel : IN std_ulogic ; + hReady : OUT std_ulogic ; + hResp : OUT std_ulogic ; + hClk : IN std_ulogic ; + hReset_n : IN std_ulogic + ); + END COMPONENT; + COMPONENT programRom + GENERIC ( + addressBitNb : positive := 8; + dataBitNb : positive := 8 + ); + PORT ( + address : IN unsigned (addressBitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + en : IN std_ulogic ; + reset : IN std_ulogic ; + dataOut : OUT std_ulogic_vector ( dataBitNb-1 DOWNTO 0 ) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : ahbBeamer USE ENTITY SystemOnChip.ahbBeamer; +-- FOR ALL : ahbDecoder USE ENTITY AhbLite.ahbDecoder; +-- FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio; +-- FOR ALL : ahbMasterInterface USE ENTITY AhbLite.ahbMasterInterface; +-- FOR ALL : ahbMultiplexor USE ENTITY AhbLite.ahbMultiplexor; +-- FOR ALL : ahbMuxConnector USE ENTITY AhbLite.ahbMuxConnector; +-- FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart; +-- FOR ALL : nanoProcessor USE ENTITY NanoBlaze.nanoProcessor; +-- FOR ALL : programRom USE ENTITY SystemOnChip.programRom; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + upEn <= '1'; + + + -- Instance port mappings. + I_dec : ahbDecoder + GENERIC MAP ( + ahbMemoryLocation => ahbMemoryLocation + ) + PORT MAP ( + hAddr => hAddr, + hSel => hSelV + ); + I_mst : ahbMasterInterface + PORT MAP ( + clock => clock, + hRData => hRData, + hReady => hReady, + hResp => hResp, + pAddress => upAddress, + pDataOut => upDataOut, + pReadStrobe => upReadStrobe, + pWriteStrobe => upWriteStrobe, + reset => reset, + hAddr => hAddr, + hBurst => hBurst, + hClk => hClk, + hMastLock => hMastLock, + hProt => hProt, + hReset_n => hReset_n, + hSize => hSize, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + pDataIn => upDataIn + ); + I_mux : ahbMultiplexor + PORT MAP ( + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelV, + hRData => hRData, + hReady => hReady, + hResp => hResp + ); + I_connBeam : ahbMuxConnector + GENERIC MAP ( + index => beamerIndex + ) + PORT MAP ( + hRData => hRDataBeamer, + hReady => hReadyBeamer, + hResp => hRespBeamer, + hSelV => hSelV, + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelBeamer + ); + I_connT : ahbMuxConnector + GENERIC MAP ( + index => gpioIndex + ) + PORT MAP ( + hRData => hRDataGpio, + hReady => hReadyGpio, + hResp => hRespGpio, + hSelV => hSelV, + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelGpio + ); + I_connUart : ahbMuxConnector + GENERIC MAP ( + index => uartIndex + ) + PORT MAP ( + hRData => hRDataUart, + hReady => hReadyUart, + hResp => hRespUart, + hSelV => hSelV, + hRDataV => hRDataV, + hReadyV => hReadyV, + hRespV => hRespV, + hSel => hSelUart + ); + I_GPIO : ahbGpio + GENERIC MAP ( + ioNb => ioNb + ) + PORT MAP ( + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSelGpio, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + ioIn => ioIn, + hRData => hRDataGpio, + hReady => hReadyGpio, + hResp => hRespGpio, + ioEn => ioEn, + ioOut => ioOut + ); + I_UART : ahbUart + GENERIC MAP ( + txFifoDepth => 8, + rxFifoDepth => 1 + ) + PORT MAP ( + RxD => RxD, + hAddr => hAddr, + hClk => hClk, + hReset_n => hReset_n, + hSel => hSelUart, + hTrans => hTrans, + hWData => hWData, + hWrite => hWrite, + TxD => TxD, + hRData => hRDataUart, + hReady => hReadyUart, + hResp => hRespUart + ); + I_up : nanoProcessor + GENERIC MAP ( + addressBitNb => ahbAddressBitNb, + registerBitNb => ahbDataBitNb, + registerAddressBitNb => registerAddressBitNb, + programCounterBitNb => programCounterBitNb, + stackPointerBitNb => stackPointerBitNb, + instructionBitNb => instructionBitNb, + scratchpadAddressBitNb => scratchpadAddressBitNb + ) + PORT MAP ( + clock => clock, + dataIn => upDataIn, + en => upEn, + instruction => instruction, + int => int, + reset => reset, + dataAddress => upAddress, + dataOut => upDataOut, + intAck => intAck, + progCounter => programCounter, + readStrobe => upReadStrobe, + writeStrobe => upWriteStrobe + ); + I_beamer : ahbBeamer + GENERIC MAP ( + patternAddressBitNb => patternAddressBitNb, + testOutBitNb => testOutBitNb + ) + PORT MAP ( + outX => outX, + hAddr => hAddr, + outY => outY, + hWData => hWData, + selSinCos => selSinCos, + testOut => testOut, + hRData => hRDataBeamer, + hTrans => hTrans, + hWrite => hWrite, + hSel => hSelBeamer, + hReady => hReadyBeamer, + hResp => hRespBeamer, + hClk => hClk, + hReset_n => hReset_n + ); + I_rom : programRom + GENERIC MAP ( + addressBitNb => programCounterBitNb, + dataBitNb => instructionBitNb + ) + PORT MAP ( + address => programCounter, + clock => clock, + en => upEn, + reset => reset, + dataOut => instruction + ); + +END struct; + + + + +-- +-- VHDL Architecture Board.SoC_ebs3.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 10:21:25 08.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Board; +-- LIBRARY Lattice; +-- LIBRARY SystemOnChip; + +ARCHITECTURE struct OF SoC_ebs3 IS + + -- Architecture declarations + constant ioNb: positive := 8; + constant testOutBitNb: positive := 16; + constant patternAddressBitNb: positive := 9; + + -- Internal signal declarations + SIGNAL clk_sys : std_ulogic; + SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0); + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_N : std_ulogic; + SIGNAL rxdSynch : std_ulogic; + SIGNAL selSinCos : std_ulogic; + SIGNAL selSinCosSynch : std_ulogic; + SIGNAL testOut : std_ulogic_vector(1 TO testOutBitNb); + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT beamerSoc + GENERIC ( + ioNb : positive := 8; + testOutBitNb : positive := 16; + patternAddressBitNb : positive := 9 + ); + PORT ( + TxD : OUT std_ulogic ; + RxD : IN std_ulogic ; + outX : OUT std_ulogic ; + outY : OUT std_ulogic ; + selSinCos : IN std_ulogic ; + reset : IN std_ulogic ; + clock : IN std_ulogic ; + ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0); + ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0); + testOut : OUT std_ulogic_vector (1 TO testOutBitNb) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DFF USE ENTITY Board.DFF; +-- FOR ALL : beamerSoc USE ENTITY SystemOnChip.beamerSoc; +-- FOR ALL : inverterIn USE ENTITY Board.inverterIn; +-- FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 3 eb3 + LED1 <= testOut(1); + LED2 <= testOut(2); + spare(testOut'range) <= testOut; + spare(testOut'high+1 to spare'high) <= (others => '0'); + + -- HDL Embedded Text Block 4 eb4 + logic1 <= '1'; + + -- HDL Embedded Text Block 5 eb5 + logic0 <= '0'; + + + -- Instance port mappings. + I8 : DFF + PORT MAP ( + CLK => clk_sys, + CLR => resetSynch, + D => RxD, + Q => rxdSynch + ); + I9 : DFF + PORT MAP ( + CLK => clk_sys, + CLR => resetSynch, + D => selSinCos, + Q => selSinCosSynch + ); + I12 : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSynch_N + ); + I2 : inverterIn + PORT MAP ( + in1 => reset_N, + out1 => reset + ); + I3 : inverterIn + PORT MAP ( + in1 => resetSynch_N, + out1 => resetSynch + ); + I7 : inverterIn + PORT MAP ( + in1 => selSinCos_n, + out1 => selSinCos + ); + I_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clk_sys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_top : beamerSoc + GENERIC MAP ( + ioNb => ioNb, + testOutBitNb => testOutBitNb, + patternAddressBitNb => patternAddressBitNb + ) + PORT MAP ( + TxD => TxD, + RxD => rxdSynch, + outX => xOut, + outY => yOut, + selSinCos => selSinCosSynch, + reset => resetSynch, + clock => clk_sys, + ioEn => OPEN, + ioOut => OPEN, + ioIn => ioIn, + testOut => testOut + ); + +END struct; + + + + diff --git a/06-07-08-09-SystemOnChip/Board/diamond/programmer.xcf b/06-07-08-09-SystemOnChip/Board/diamond/programmer.xcf new file mode 100644 index 0000000..468a2da --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/diamond/programmer.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Renesas + ECP5U + LFE5U-25F + All + LFE5U-25F + + 8 + 11111111 + 1 + 0 + + + 04/11/23 16:14:28 + 0xA4B0 + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 4 + + + USB2 + FTUSB-0 + LFE5U-25F A Location 0000 Serial 018VFVT3A + + diff --git a/06-07-08-09-SystemOnChip/Board/diamond/reveal_analyze.rva b/06-07-08-09-SystemOnChip/Board/diamond/reveal_analyze.rva new file mode 100644 index 0000000..4249e0e --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/diamond/reveal_analyze.rva @@ -0,0 +1,638 @@ + + + lun. 6. mars 14:29:10 2023 + + + + + + + + + + + + 1 + + 0 + 1. LFE5U-25F + 0x41111043 + true + false + + 8 + reveal_config.rvl + reveal_config.rvs + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/06-07-08-09-SystemOnChip/Board/diamond/reveal_config.rvl b/06-07-08-09-SystemOnChip/Board/diamond/reveal_config.rvl new file mode 100644 index 0000000..28d2f1c --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/diamond/reveal_config.rvl @@ -0,0 +1,662 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/06-07-08-09-SystemOnChip/Board/diamond/strategy.sty b/06-07-08-09-SystemOnChip/Board/diamond/strategy.sty new file mode 100644 index 0000000..a2b5a4a --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/diamond/strategy.sty @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.bit b/06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.bit new file mode 100644 index 0000000..b654faf Binary files /dev/null and b/06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.bit differ diff --git a/06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.ldf b/06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.ldf new file mode 100644 index 0000000..f1ae61d --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.ldf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/06-07-08-09-SystemOnChip/Board/hdl/DFF_sim.vhd b/06-07-08-09-SystemOnChip/Board/hdl/DFF_sim.vhd new file mode 100644 index 0000000..cf8868a --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hdl/DFF_sim.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/06-07-08-09-SystemOnChip/Board/hdl/buff_sim.vhd b/06-07-08-09-SystemOnChip/Board/hdl/buff_sim.vhd new file mode 100644 index 0000000..8ad27be --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hdl/buff_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF buff IS +BEGIN + + out1 <= in1; + +END ARCHITECTURE sim; + diff --git a/06-07-08-09-SystemOnChip/Board/hdl/inverterIn_sim.vhd b/06-07-08-09-SystemOnChip/Board/hdl/inverterIn_sim.vhd new file mode 100644 index 0000000..fb039ac --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hdl/inverterIn_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/06-07-08-09-SystemOnChip/Board/hdl/inverter_sim.vhd b/06-07-08-09-SystemOnChip/Board/hdl/inverter_sim.vhd new file mode 100644 index 0000000..ca5b6b5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hdl/inverter_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverter IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_fpga_beamer_entity.vhg._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_fpga_beamer_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_fpga_beamer_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_fpga_beamer_struct.vhg._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_fpga_beamer_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_fpga_beamer_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_soc_ebs3_entity.vhg._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_soc_ebs3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_soc_ebs3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_soc_ebs3_struct.vhg._fpf b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_soc_ebs3_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/.hdlsidedata/_soc_ebs3_struct.vhg._fpf @@ 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a/06-07-08-09-SystemOnChip/Board/hds/@f@p@g@a_beamer/struct.bd b/06-07-08-09-SystemOnChip/Board/hds/@f@p@g@a_beamer/struct.bd new file mode 100644 index 0000000..6e60617 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/@f@p@g@a_beamer/struct.bd @@ -0,0 +1,6067 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I2" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 2944,0 +) +(Instance +name "I12" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 3013,0 +) +(Instance +name "I7" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 3775,0 +) +(Instance +name "I9" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 3795,0 +) +(Instance +name "I3" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 3968,0 +) +(Instance +name "I8" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 4904,0 +) +(Instance +name "I_top" +duLibraryName "SystemOnChip" +duName "beamerSoc" +elements [ +(GiElement +name "ioNb" +type "positive" +value "ioNb" +) +(GiElement +name "testOutBitNb" +type "positive" +value "testOutBitNb" +) +(GiElement +name "patternAddressBitNb" +type "positive" +value "patternAddressBitNb" +) +] +mwi 0 +uid 5675,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb2" +number "2" +) +(EmbeddedInstance +name "eb3" +number "3" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@f@p@g@a_beamer\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@f@p@g@a_beamer\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@f@p@g@a_beamer" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\FPGA_beamer" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "FPGA_beamer" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:00:12" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Board" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Board" +) +(vvPair +variable "library_downstream_SpyGlass" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "FPGA_beamer" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@f@p@g@a_beamer\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\FPGA_beamer\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ADMS" +value "" +) +(vvPair +variable "task_AsmPath" +value "$HEI_LIBS_DIR/NanoBlaze/hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "task_NC" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:00:12" +) +(vvPair +variable "unit" +value "FPGA_beamer" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 83,0 +optionalChildren [ +*1 (PortIoIn +uid 9,0 +shape (CompositeShape +uid 10,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 11,0 +sl 0 +ro 270 +xt "26000,70625,27500,71375" +) +(Line +uid 12,0 +sl 0 +ro 270 +xt "27500,71000,28000,71000" +pts [ +"27500,71000" +"28000,71000" +] +) +] +) +tg (WTG +uid 13,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "21200,70300,25000,71700" +st "clock" +ju 2 +blo "25000,71500" +tm "WireNameMgr" +) +) +) +*2 (Net +uid 21,0 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +declText (MLText +uid 22,0 +va (VaSet +font "Verdana,8,0" +) +xt "-1000,7600,10200,8600" +st "clock : std_ulogic" +) +) +*3 (PortIoOut +uid 23,0 +shape (CompositeShape +uid 24,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 25,0 +sl 0 +ro 270 +xt "116500,48625,118000,49375" +) +(Line +uid 26,0 +sl 0 +ro 270 +xt "116000,49000,116500,49000" +pts [ +"116000,49000" +"116500,49000" +] +) +] +) +tg (WTG +uid 27,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 28,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "119000,48300,122800,49700" +st "yOut" +blo "119000,49500" +tm "WireNameMgr" +) +) +) +*4 (PortIoIn +uid 37,0 +shape (CompositeShape +uid 38,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 39,0 +sl 0 +ro 270 +xt "26000,82625,27500,83375" +) +(Line +uid 40,0 +sl 0 +ro 270 +xt "27500,83000,28000,83000" +pts [ +"27500,83000" +"28000,83000" +] +) +] +) +tg (WTG +uid 41,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 42,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "19200,82300,25000,83700" +st "reset_N" +ju 2 +blo "25000,83500" +tm "WireNameMgr" +) +) +) +*5 (Net +uid 49,0 +decl (Decl +n "reset" +t "std_ulogic" +o 13 +suid 2,0 +) +declText (MLText +uid 50,0 +va (VaSet +font "Verdana,8,0" +) +xt "-1000,22900,13400,23900" +st "SIGNAL reset : std_ulogic" +) +) +*6 (Grouping +uid 51,0 +optionalChildren [ +*7 (CommentText +uid 53,0 +shape (Rectangle +uid 54,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "107000,98000,124000,99000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 55,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "107200,98500,107200,98500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +uid 56,0 +shape (Rectangle +uid 57,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "124000,94000,128000,95000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 58,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "124200,94500,124200,94500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +uid 59,0 +shape (Rectangle +uid 60,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "107000,96000,124000,97000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 61,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "107200,96500,107200,96500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +uid 62,0 +shape (Rectangle +uid 63,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "103000,96000,107000,97000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 64,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "103200,96500,103200,96500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*11 (CommentText +uid 65,0 +shape (Rectangle +uid 66,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "124000,95000,144000,99000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 67,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "124200,95200,138300,96400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*12 (CommentText +uid 68,0 +shape (Rectangle +uid 69,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "128000,94000,144000,95000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 70,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "128200,94500,128200,94500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*13 (CommentText +uid 71,0 +shape (Rectangle +uid 72,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "103000,94000,124000,96000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 73,0 +va (VaSet +fg "32768,0,0" +) +xt "108350,94400,118650,95600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*14 (CommentText +uid 74,0 +shape (Rectangle +uid 75,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "103000,97000,107000,98000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 76,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "103200,97500,103200,97500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*15 (CommentText +uid 77,0 +shape (Rectangle +uid 78,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "103000,98000,107000,99000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 79,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "103200,98500,103200,98500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*16 (CommentText +uid 80,0 +shape (Rectangle +uid 81,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "107000,97000,124000,98000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 82,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "107200,97500,107200,97500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 52,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "103000,94000,144000,99000" +) +oxt "14000,66000,55000,71000" +) +*17 (Net +uid 253,0 +decl (Decl +n "reset_N" +t "std_ulogic" +o 2 +suid 3,0 +) +declText (MLText +uid 254,0 +va (VaSet +font "Verdana,8,0" +) +xt "-1000,8500,10700,9500" +st "reset_N : std_ulogic" +) +) +*18 (Net +uid 476,0 +decl (Decl +n "xOut" +t "std_ulogic" +o 9 +suid 4,0 +) +declText (MLText +uid 477,0 +va (VaSet +font "Verdana,8,0" +) +xt "-1000,14800,10400,15800" +st "xOut : std_ulogic" +) +) +*19 (PortIoOut +uid 569,0 +shape (CompositeShape +uid 570,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 571,0 +sl 0 +ro 270 +xt "116500,46625,118000,47375" +) +(Line +uid 572,0 +sl 0 +ro 270 +xt "116000,47000,116500,47000" +pts [ +"116000,47000" +"116500,47000" +] +) +] +) +tg (WTG +uid 573,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 574,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "119000,46300,122800,47700" +st "xOut" +blo "119000,47500" +tm "WireNameMgr" +) +) +) +*20 (Net +uid 611,0 +decl (Decl +n "yOut" +t "std_ulogic" +o 10 +suid 5,0 +) +declText (MLText +uid 612,0 +va (VaSet +font "Verdana,8,0" +) +xt "-1000,15700,10400,16700" +st "yOut : std_ulogic" +) +) +*21 (PortIoIn +uid 954,0 +shape (CompositeShape +uid 955,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 956,0 +sl 0 +ro 270 +xt "26000,40625,27500,41375" +) +(Line +uid 957,0 +sl 0 +ro 270 +xt "27500,41000,28000,41000" +pts [ +"27500,41000" +"28000,41000" +] +) +] +) +tg (WTG +uid 958,0 +ps "PortIoTextPlaceStrategy" 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"21000,23600,39000,25400" +st "nbBits = dataBitNb ( positive ) +delay = 1 ns ( time ) " +) +header "" +) +elements [ +(GiElement +name "nbBits" +type "positive" +value "dataBitNb" +) +(GiElement +name "delay" +type "time" +value "1 ns" +) +] +) +connectByName 1 +portVis (PortSigDisplay +disp 1 +sN 0 +sTC 0 +sT 1 +sIVOD 1 +) +archFileType "UNKNOWN" +) +*71 (Net +uid 1025,0 +decl (Decl +n "dataOut" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 17 +suid 14,0 +) +declText (MLText +uid 1026,0 +va (VaSet +font "courier,8,0" +) +xt "65000,17200,95000,18100" +st "SIGNAL dataOut : std_logic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*72 (Net +uid 1031,0 +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 15 +suid 15,0 +) +declText (MLText +uid 1032,0 +va (VaSet +font "courier,8,0" +) +xt "65000,15600,95500,16500" +st "SIGNAL dataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*73 (Net +uid 1039,0 +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" 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"HdlTextNameMgr" +) +*77 (Text +uid 1057,0 +va (VaSet +) +xt "22400,14000,23200,15000" +st "1" +blo "22400,14800" +tm "HdlTextNumberMgr" +) +] +) +) +*78 (Net +uid 1070,0 +decl (Decl +n "data" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 14 +suid 17,0 +) +declText (MLText +uid 1071,0 +va (VaSet +font "courier,8,0" +) +xt "65000,14800,95000,15700" +st "SIGNAL data : std_logic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*79 (PortIoOut +uid 1157,0 +shape (CompositeShape +uid 1158,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1159,0 +sl 0 +ro 270 +xt "91500,39625,93000,40375" +) +(Line +uid 1160,0 +sl 0 +ro 270 +xt "91000,40000,91500,40000" +pts [ +"91000,40000" +"91500,40000" +] +) +] +) +tg (WTG +uid 1161,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1162,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "94000,39300,98000,40700" +st "LED2" +blo "94000,40500" +tm "WireNameMgr" +) +) +) +*80 (Net +uid 1169,0 +decl (Decl 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1422,0 +va (VaSet +vasetType 3 +) +xt "42000,45000,45000,45000" +pts [ +"42000,45000" +"45000,45000" +] +) +end &87 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1427,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1428,0 +va (VaSet +font "Verdana,12,0" +) +xt "41000,43600,44800,45000" +st "clock" +blo "41000,44800" +tm "WireNameMgr" +) +) +on &2 +) +*124 (Wire +uid 1716,0 +shape (OrthoPolyLine +uid 1717,0 +va (VaSet +vasetType 3 +) +xt "38000,81000,48000,83000" +pts [ +"38000,83000" +"48000,83000" +"48000,81000" +] +) +start &38 +end &46 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1720,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1721,0 +va (VaSet +font "Verdana,12,0" +) +xt "39000,81600,43100,83000" +st "reset" +blo "39000,82800" +tm "WireNameMgr" +) +) +on &5 +) +*125 (Wire +uid 1722,0 +shape (OrthoPolyLine +uid 1723,0 +va (VaSet +vasetType 3 +) +xt "43000,79000,45000,79000" +pts [ +"43000,79000" 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+version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I2" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 133,0 +) +(Instance +name "I8" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 162,0 +) +(Instance +name "I12" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 188,0 +) +(Instance +name "I3" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 214,0 +) +(Instance +name "I_top" +duLibraryName "SystemOnChip" +duName "beamerSoc" +elements [ +(GiElement +name "ioNb" +type "positive" +value "ioNb" +) +(GiElement +name "testOutBitNb" +type "positive" +value "testOutBitNb" +) +(GiElement +name "patternAddressBitNb" +type "positive" +value "patternAddressBitNb" +) +] +mwi 0 +uid 234,0 +) +(Instance +name "I9" +duLibraryName "Board" +duName "DFF" +elements [ +] +mwi 0 +uid 296,0 +) +(Instance +name "I7" +duLibraryName "Board" +duName "inverterIn" +elements [ +] +mwi 0 +uid 340,0 +) +(Instance +name "I_pll" +duLibraryName "Lattice" +duName "pll" +elements [ +] +mwi 0 +uid 653,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb4" +number "4" +) +(EmbeddedInstance +name "eb3" +number "3" +) +(EmbeddedInstance +name "eb5" +number "5" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\SoC_ebs3" +) +(vvPair +variable "date" +value "08.05.2023" +) +(vvPair +variable "day" +value "lun." +) +(vvPair +variable "day_long" +value "lundi" +) +(vvPair +variable "dd" +value "08" +) +(vvPair +variable "entity_name" +value "SoC_ebs3" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "08.05.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "10:21:25" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Board" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Board" +) +(vvPair +variable "mm" +value "05" +) +(vvPair +variable "module_name" +value "SoC_ebs3" +) +(vvPair +variable "month" +value "mai" +) +(vvPair +variable "month_long" +value "mai" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\@so@c_ebs3\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\Board\\hds\\SoC_ebs3\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "10:21:25" +) +(vvPair +variable "unit" +value "SoC_ebs3" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 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(VaSet +font "Verdana,8,0" +) +xt "2000,16800,20900,17800" +st "spare : std_ulogic_vector(1 TO 17) +" +) +) +*102 (Net +uid 516,0 +decl (Decl +n "yOut" +t "std_ulogic" +o 11 +suid 11,0 +) +declText (MLText +uid 517,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,18800,13400,19800" +st "yOut : std_ulogic +" +) +) +*103 (Net +uid 518,0 +decl (Decl +n "reset_N" +t "std_ulogic" +o 12 +suid 12,0 +) +declText (MLText +uid 519,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,12000,13700,13000" +st "reset_N : std_ulogic +" +) +) +*104 (Net +uid 520,0 +decl (Decl +n "rxdSynch" +t "std_ulogic" +o 13 +suid 13,0 +) +declText (MLText +uid 521,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,31200,17200,32200" +st "SIGNAL rxdSynch : std_ulogic +" +) +) +*105 (Net +uid 524,0 +decl (Decl +n "LED1" +t "std_ulogic" +o 15 +suid 15,0 +) +declText (MLText +uid 525,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,14000,13500,15000" +st "LED1 : std_ulogic +" +) +) +*106 (Net +uid 526,0 +decl (Decl +n "LED2" +t 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b/06-07-08-09-SystemOnChip/Board/hds/_buff._epf new file mode 100644 index 0000000..d74258b --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/_buff._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom buff_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/06-07-08-09-SystemOnChip/Board/hds/_fpga_beamer._epf b/06-07-08-09-SystemOnChip/Board/hds/_fpga_beamer._epf new file mode 100644 index 0000000..9f56918 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/_fpga_beamer._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom @f@p@g@a_beamer/struct.bd +TOP_MARKER atom 1 diff --git a/06-07-08-09-SystemOnChip/Board/hds/_lissajousgenerator_circuit._epf b/06-07-08-09-SystemOnChip/Board/hds/_lissajousgenerator_circuit._epf new file mode 100644 index 0000000..50730df --- /dev/null +++ b/06-07-08-09-SystemOnChip/Board/hds/_lissajousgenerator_circuit._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom lissajous@generator_circuit/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 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+SystemOnChip_test = $SCRATCH_DIR/SystemOnChip_test +UVM = $SCRATCH_DIR/UVM +UVM_test = $SCRATCH_DIR/UVM_test +WaveformGenerator = $SCRATCH_DIR/WaveformGenerator +WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test +[hdl] +AhbLite = $HDS_PROJECT_DIR/../../Libs/AhbLite/hdl +AhbLite_test = $HDS_PROJECT_DIR/../../Libs/AhbLite_test/hdl +AhbLiteComponents = $HDS_PROJECT_DIR/../AhbLiteComponents/hdl +AhbLiteComponents_test = $HDS_PROJECT_DIR/../AhbLiteComponents_test/hdl +Board = $HDS_PROJECT_DIR/../Board/hdl +Common = $HDS_PROJECT_DIR/../../Libs/Common/hdl +Common_test = $HDS_PROJECT_DIR/../../Libs/Common_test/hdl +DigitalToAnalogConverter = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl +DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hdl +NanoBlaze = $HDS_PROJECT_DIR/../../Libs/NanoBlaze/hdl +NanoBlaze_test = $HDS_PROJECT_DIR/../../Libs/NanoBlaze_test/hdl +RiscV = $HDS_PROJECT_DIR/../../Libs/RiscV/hdl +RiscV_test = $HDS_PROJECT_DIR/../../Libs/RiscV_test/hdl +SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hdl +SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +SystemOnChip = $HDS_PROJECT_DIR/../SystemOnChip/hdl +SystemOnChip_test = $HDS_PROJECT_DIR/../SystemOnChip_test/hdl +UVM = $HDS_PROJECT_DIR/../../Libs/UVM/hdl +UVM_test = $HDS_PROJECT_DIR/../../Libs/UVM_test/hdl +WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl +WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl +[hds] +AhbLite = $HDS_PROJECT_DIR/../../Libs/AhbLite/hds +AhbLite_test = $HDS_PROJECT_DIR/../../Libs/AhbLite_test/hds +AhbLiteComponents = $HDS_PROJECT_DIR/../AhbLiteComponents/hds +AhbLiteComponents_test = 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+VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/title_block.tmpl b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.3/hds_team_prefs b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.3/title_block.tmpl b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..8b550bd --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6103 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Sublime" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ 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+vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "courier,8,1" +) +packageListFontVaSet (VaSet +font "courier,8,0" +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +font "courier,8,0" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "courier,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "courier,8,1" +) +CompDirValueVaSet (VaSet +font "courier,8,0" +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "courier,8,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "courier,8,1" +) +cptPortFontVaSet (VaSet +font "courier,8,0" +) +genericInterfaceFontVaSet (VaSet +font "courier,8,0" +) +portRowVaSet (VaSet +vasetType 4 +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +) +] diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..5752b73 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/ahbUart.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/logs/HDS_log.txt b/06-07-08-09-SystemOnChip/Prefs/hds_user/logs/HDS_log.txt new file mode 100644 index 0000000..4c4644c --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/logs/HDS_log.txt @@ -0,0 +1,73 @@ +Application HDL Designer version 2019.2 (Build 5) +Created on 02/20/2020 13:36:10 +HDL Designer Series +HDL Designer +Version 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:05 +Verilog parser dynamic library version 5.1.42.f ( 2019/04/20 21:28:10 ) +Running on Professional (Build 9200) + +Loading HDS Project file via Environment variable $HDS_LIBS C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds.hdp +Loading prefs env variable USER_HOME C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_user +Loading teamprefs env variable TEAM_HOME C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_team +Loading user Task files from 'C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_user\v2019.2\tasks'. +Loading team Task files from 'C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_team\v2019.2\tasks'. +The timezone environment variable is set : TZ=GMT-1:0 + +HDS_HOME is set to : C:\tools\eda\HDS + +Environment variables: +HDS_HOME set to C:\tools\eda\HDS +HDS_USER_HOME set to C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_user +HDS_TEAM_HOME set to C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_team +HDS_LIBS set to C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds.hdp +HDS_PORT set to zell:51992 +10 events recorded: +Undo +Undo +Undo +Undo +Undo +Undo +ExecuteAction +Print +Print +ExecuteAction + +Traceback + +hdldesigner.exe caused an EXCEPTION_ACCESS_VIOLATION in module at 0023:6F6C6C61 +EAX=6F6C6C61 EBX=0291A7F0 ECX=142B6EB0 EDX=02FFEF64 ESI=00000000 +EDI=00000111 EBP=03C3F39C ESP=03C3F34C EIP=6F6C6C61 FLG=00210202 +CS=0023 DS=002B SS=002B ES=002B FS=0053 GS=002B +0x6F6C6C61 +0x01C2358B hdldesigner.exe +0x01C1E5B4 hdldesigner.exe +0x01D06A6D hdldesigner.exe +0x01939CB1 hdldesigner.exe +0x018F899B hdldesigner.exe +0x01CD5F69 hdldesigner.exe +0x01AFB193 hdldesigner.exe +0x00702F46 hdldesigner.exe +0x01CE7705 hdldesigner.exe +0x01A07AA9 hdldesigner.exe +0x01A0763F hdldesigner.exe +0x02797EC1 hdldesigner.exe +0x02818CBB hdldesigner.exe +0x027D60D0 hdldesigner.exe +0x0291A820 hdldesigner.exe +0x0004438B USER32.dll, AddClipboardFormatListener()+0075 byte(s) +0x00024F8C USER32.dll, CallWindowProcW()+2860 byte(s) +0x000240DE USER32.dll, DispatchMessageW()+0558 byte(s) +0x0003E7B0 USER32.dll, DispatchMessageA()+0016 byte(s) +0x027D4515 hdldesigner.exe +0x027D42CB hdldesigner.exe +0x0040469A hdldesigner.exe +0x00401BA6 hdldesigner.exe +0x0291B412 hdldesigner.exe +0x028DAD8F hdldesigner.exe +0x00016359 KERNEL32.DLL, BaseThreadInitThunk()+0025 byte(s) +0x00067B74 ntdll.dll, RtlGetAppContainerNamedObjectPath()+0228 byte(s) +0x00067B44 ntdll.dll, RtlGetAppContainerNamedObjectPath()+0180 byte(s) +End of traceback + diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/hds_user_prefs b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap 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+signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/generate.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..28c9b8f --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6866 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ 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+gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/generate.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..ba578c2 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/beamerSoc.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/06-07-08-09-SystemOnChip/Scripts/cleanGenerated.bash b/06-07-08-09-SystemOnChip/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/06-07-08-09-SystemOnChip/Scripts/cleanGenerated.bat b/06-07-08-09-SystemOnChip/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/06-07-08-09-SystemOnChip/Scripts/cleanScratch.bat b/06-07-08-09-SystemOnChip/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/06-07-08-09-SystemOnChip/Scripts/generateSSHKey.bash b/06-07-08-09-SystemOnChip/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/06-07-08-09-SystemOnChip/Scripts/hdlDesigner.bash b/06-07-08-09-SystemOnChip/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/06-07-08-09-SystemOnChip/Scripts/hdlDesigner.bat b/06-07-08-09-SystemOnChip/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..2a612a6 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/hdlDesigner.bat @@ -0,0 +1,301 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +if %REQUIRE_ICECUBE2% == 1 ( + set synthesis_subdirectory="Board\icecube2" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + if %REQUIRE_ICECUBE2% == 1 ( + echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=% + echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=% + echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +if %REQUIRE_ICECUBE2% == 1 ( + if exist %ICECUBE2_BASE_DIR% ( + echo %ICECUBE2_BASE_DIR:"=% + echo -> %ICECUBE2_BASE_DIR:"=% + if exist %ICECUBE2_WORK_DIR% ( + rmdir /S /Q "%ICECUBE2_WORK_DIR%" + ) + mkdir "%ICECUBE2_WORK_DIR%" + xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW! + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/06-07-08-09-SystemOnChip/Scripts/searchPaths.bat b/06-07-08-09-SystemOnChip/Scripts/searchPaths.bat new file mode 100644 index 0000000..9b37b1b --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/searchPaths.bat @@ -0,0 +1,209 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +echo Search HEI Library +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings. + pause&goto:eof + ) +) + + +echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2 +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo %INDENT:"=%Found HDL-Designer at !HDS_HOME! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo %INDENT:"=%Found ISE at !ISE_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice Diamond directory +:: +if %REQUIRE_DIAMOND% == 1 ( + if "%DIAMOND_HOME%" == "" ( + set DIAMOND_HOME=C:\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !DIAMOND_HOME! ( + echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice IceCube2 directory +:: +if %REQUIRE_ICECUBE2% == 1 ( + if "%ICECUBE2_HOME%" == "" ( + set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !ICECUBE2_HOME! ( + echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings. + pause + goto:eof + ) +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + goto:eof \ No newline at end of file diff --git a/06-07-08-09-SystemOnChip/Scripts/trimLibs.pl b/06-07-08-09-SystemOnChip/Scripts/trimLibs.pl new file mode 100644 index 0000000..76d8d36 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/trimLibs.pl @@ -0,0 +1,170 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ama: [Amand Axel](axel.amand@hevs.ch) +# ------------------------------------------------------------------------------ +# Changelog: +# 2023.05.16 : ama +# * Add: ice40 libs support +# 2023.02.01 : ama +# * Add: ECP5U libs support +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40 + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i) and + not($testline =~ m/ice40.*\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u or ice40 + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i) and + not($testline =~ m/ice40/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/06-07-08-09-SystemOnChip/Scripts/update_ise.pl b/06-07-08-09-SystemOnChip/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/06-07-08-09-SystemOnChip/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ commandHeader do + uartData := getSerialPortByte; + checksum := uartData; + { get packet id } + packetId := getSerialPortByte; + checksum := checksum + packetId; + { get command } + commandId := getSerialPortByte; + checksum := checksum + commandId; + { process known commands } + if (commandId = commandWriteMem) or (commandId = commandReadMem) then + begin + { get command length } + commandLength := getSerialPortByte; + checksum := checksum + commandLength; + { check command lengths } + if (commandId = commandWriteMem) and (commandLength <> commandWriteLength) then + getCommand := 1; + else if (commandId = commandReadMem) and (commandLength <> commandReadLength) then + getCommand := 1; + else + begin + { get address } + memoryAddress := getSerialPortByte; + checksum := checksum + memoryAddress; + memoryAddress := (memoryAddress shl 8) + getSerialPortByte; + checksum := checksum + memoryAddress; + { get data } + if commandId = commandReadMem then + begin + memoryData := getSerialPortByte; + checksum := checksum + memoryData; + memoryData := (memoryData shl 8) + getSerialPortByte; + checksum := checksum + memoryData; + end; + { get and verify checksum} + if getSerialPortByte = (checksum and $00FF) then + getCommand := 0; + else + getCommand := 1; + end; + end; + else + getCommand := 1; + end; + + {----------------------------------------------------------------------------} + { Send NACK } + {----------------------------------------------------------------------------} + function sendNegativeAcknowledge(packetId : uint8); + var + uartData: uint8; + checksum: word; + begin + { send packet header } + uartData := $AA; + sendSerialPort(uartData); + checksum := uartData; + { send packet id } + uartData := packetId; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send command id } + uartData := commandNack; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send packet length } + uartData := 0; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send checksum } + uartData := checksum and $00FF; + sendSerialPort(uartData); + end; + + {----------------------------------------------------------------------------} + { Send ACK } + {----------------------------------------------------------------------------} + function sendAcknowledge(packetId, commandId : uint8); + var + uartData: uint8; + checksum: word; + begin + { send packet header } + uartData := $AA; + sendSerialPort(uartData); + checksum := uartData; + { send packet id } + uartData := packetId; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send command id } + uartData := commandId; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send packet length } + uartData := 0; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send checksum } + uartData := checksum and $00FF; + sendSerialPort(uartData); + end; + + {----------------------------------------------------------------------------} + { Send READ_MEM reply } + {----------------------------------------------------------------------------} + function sendReadAnswer(packetId : uint8; memoryData: word); + var + uartData: uint8; + checksum: word; + begin + { send packet header } + uartData := $AA; + sendSerialPort(uartData); + checksum := uartData; + { send packet id } + uartData := packetId; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send command id } + uartData := commandReadMem; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send packet length } + uartData := 2; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send data low } + uartData := memoryData and $00FF; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send data high } + uartData := memoryData shr 8; + sendSerialPort(uartData); + checksum := checksum + uartData; + { send checksum } + uartData := checksum and $00FF; + sendSerialPort(uartData); + end; + +{==============================================================================} +{ Main program } +{==============================================================================} +begin + { initialize SoC registers } + initRegisters; + { main loop } + while true do begin + { get a new command } + errorId := getCommand(packetId, commandId, memoryAddress, memoryData); + { process command } + if errorId = 0 then + begin + { process write command } + if commandId = commandWriteMem then + begin + mem[memoryAddress] := memoryData; + sendAcknowledge(packetId, commandId); + end; + { process read command } + else if commandId = commandReadMem then + begin + memoryData := mem[memoryAddress]; + sendReadAnswer(packetId, memoryData); + end; + { reply to unknown command } + else + sendNegativeAcknowledge(packetId); + end; + { negative acknowledge on reception error } + else + sendNegativeAcknowledge(packetId); + end; +end. + +{ + ;--------------------------------------------------------------- + ; register definitions + ; s0, s1: used for INPUT and OUTPUT operations + ; S2: returns UART data byte + ; S3: uart protocol checksum + ; S4: uart protocol packet id + ; S5: uart protocol command id + ; S6: uart protocol address + ; S7: uart protocol data + ; S8: copy of UART data byte for debug + ;--------------------------------------------------------------- +} diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/beamer.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/beamer.vhd new file mode 100644 index 0000000..24fc8c5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/beamer.vhd @@ -0,0 +1,374 @@ +ARCHITECTURE mapped OF programRom IS + + subtype opCodeType is std_ulogic_vector(5 downto 0); + constant opLoadC : opCodeType := "000000"; + constant opLoadR : opCodeType := "000001"; + constant opInputC : opCodeType := "000100"; + constant opInputR : opCodeType := "000101"; + constant opFetchC : opCodeType := "000110"; + constant opFetchR : opCodeType := "000111"; + constant opAndC : opCodeType := "001010"; + constant opAndR : opCodeType := "001011"; + constant opOrC : opCodeType := "001100"; + constant opOrR : opCodeType := "001101"; + constant opXorC : opCodeType := "001110"; + constant opXorR : opCodeType := "001111"; + constant opTestC : opCodeType := "010010"; + constant opTestR : opCodeType := "010011"; + constant opCompC : opCodeType := "010100"; + constant opCompR : opCodeType := "010101"; + constant opAddC : opCodeType := "011000"; + constant opAddR : opCodeType := "011001"; + constant opAddCyC : opCodeType := "011010"; + constant opAddCyR : opCodeType := "011011"; + constant opSubC : opCodeType := "011100"; + constant opSubR : opCodeType := "011101"; + constant opSubCyC : opCodeType := "011110"; + constant opSubCyR : opCodeType := "011111"; + constant opShRot : opCodeType := "100000"; + constant opOutputC : opCodeType := "101100"; + constant opOutputR : opCodeType := "101101"; + constant opStoreC : opCodeType := "101110"; + constant opStoreR : opCodeType := "101111"; + + subtype shRotCinType is std_ulogic_vector(2 downto 0); + constant shRotLdC : shRotCinType := "00-"; + constant shRotLdM : shRotCinType := "01-"; + constant shRotLdL : shRotCinType := "10-"; + constant shRotLd0 : shRotCinType := "110"; + constant shRotLd1 : shRotCinType := "111"; + + constant registerAddressBitNb : positive := 4; + constant shRotPadLength : positive + := dataOut'length - opCodeType'length - registerAddressBitNb + - 1 - shRotCinType'length; + subtype shRotDirType is std_ulogic_vector(1+shRotPadLength-1 downto 0); + constant shRotL : shRotDirType := (0 => '0', others => '-'); + constant shRotR : shRotDirType := (0 => '1', others => '-'); + + subtype branchCodeType is std_ulogic_vector(4 downto 0); + constant brRet : branchCodeType := "10101"; + constant brCall : branchCodeType := "11000"; + constant brJump : branchCodeType := "11010"; + constant brReti : branchCodeType := "11100"; + constant brEni : branchCodeType := "11110"; + + subtype branchConditionType is std_ulogic_vector(2 downto 0); + constant brDo : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( + --=============================================================== + -- Beamer control + --=============================================================== + -- + ----------------------------------------------------------------- + -- register definitions + -- s0, s1: used for INPUT and OUTPUT operations + -- S2: returns UART data byte + -- S3: uart protocol checksum + -- S4: uart protocol packet id + -- S5: uart protocol command id + -- S6: uart protocol address + -- S7: uart protocol data + -- S8: copy of UART data byte for debug + ----------------------------------------------------------------- + -- + ----------------------------------------------------------------- + -- GPIO definitions + ----------------------------------------------------------------- + ----------------------------------------------------------------- + -- UART definitions + ----------------------------------------------------------------- + -- CONSTANT uartBaudCount, 023D ; 66E6 / 115 200 = 573 + -- CONSTANT uartpollDelay, 0100 + ----------------------------------------------------------------- + -- beamer peripheral definitions + ----------------------------------------------------------------- + -- CONSTANT beamerCtlInit, 1001 + -- + --=============================================================== + -- initializations + --=============================================================== + -- + ----------------------------------------------------------------- + -- initialize GPIO + ----------------------------------------------------------------- + 16#000# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#001# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#002# => opLoadC & "0001" & "0000000010101010", -- LOAD s1, AA + 16#003# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#004# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#005# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#006# => opLoadC & "0001" & "0000000000001111", -- LOAD s1, 0F + 16#007# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize UART + ----------------------------------------------------------------- + 16#008# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 + 16#009# => opAddC & "0000" & "0000000000000010", -- ADD s0, 0002 + 16#00A# => opLoadC & "0001" & "0000000001000010", -- LOAD s1, 0042 + 16#00B# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize beamer peripheral + ----------------------------------------------------------------- + 16#00C# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#00D# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#00E# => opLoadC & "0001" & "0000010000000001", -- LOAD s1, 0401 + 16#00F# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#010# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#011# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#012# => opLoadC & "0001" & "0000000000000100", -- LOAD s1, 0004 + 16#013# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + -- + --=============================================================== + -- Main loop + --=============================================================== + -- + ----------------------------------------------------------------- + -- Process commands from serial port + ----------------------------------------------------------------- + -- _main_: + 16#014# => brCall & brDo & "--------0000100001",-- CALL 021 ; get command from UART + 16#015# => opCompC & "0011" & "0000000000000000", -- COMPARE s3, 0000 ; check function return + 16#016# => brJump & brNZ & "--------0000011111",-- JUMP NZ, 01F + 16#017# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#018# => brJump & brNZ & "--------0000011100",-- JUMP NZ, 01C + 16#019# => opOutputR & "0111" & "0110------------", -- OUTPUT s7, (S6) ; write word to memory location + 16#01A# => brCall & brDo & "--------0001100000",-- CALL 060 ; send write acknowledge + 16#01B# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandRead_: + 16#01C# => opInputR & "0111" & "0110------------", -- INPUT s7, (S6) ; write word in memory location + 16#01D# => brCall & brDo & "--------0001101111",-- CALL 06F ; send back read data + 16#01E# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandAbort_: + 16#01F# => brCall & brDo & "--------0001010001",-- CALL 051 + 16#020# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- + --=============================================================== + -- Subroutines + --=============================================================== + -- + ----------------------------------------------------------------- + -- Get command from serial port + ----------------------------------------------------------------- + -- _uartGetCmd_: + 16#021# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command header + 16#022# => opCompC & "0010" & "0000000010101010", -- COMPARE s2, 00AA + 16#023# => brJump & brNZ & "--------0000100001",-- JUMP NZ, 021 ; loop until byte is AAh + 16#024# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#025# => brCall & brDo & "--------0010000110",-- CALL 086 ; get packet id + 16#026# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#027# => opLoadR & "0100" & "0010------------", -- LOAD s4, s2 ; store id for reply + 16#028# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command + 16#029# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#02A# => opCompC & "0010" & "0000000000000011", -- COMPARE s2, 0003 ; check for WRITE_MEM command + 16#02B# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02C# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; check for READ_MEM command + 16#02D# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02E# => brJump & brDo & "--------0001001111",-- JUMP 04F ; no match + -- _commandOk_: + 16#02F# => opLoadR & "0101" & "0010------------", -- LOAD s5, s2 ; store command for action + 16#030# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data length + 16#031# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#032# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#033# => brJump & brZ & "--------0000110111",-- JUMP Z, 037 ; go to test write command length + 16#034# => opCompC & "0010" & "0000000000000010", -- COMPARE s2, 0002 ; verify READ_MEM length + 16#035# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#036# => brJump & brDo & "--------0000111001",-- JUMP 039 + -- _testWrLength_: + 16#037# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; verify WRITE_MEM length + 16#038# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + -- _getAddress_: + 16#039# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address low + 16#03A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03B# => opLoadR & "0110" & "0010------------", -- LOAD s6, s2 ; store address low + 16#03C# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address high + 16#03D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03E# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#03F# => opAddR & "0110" & "0010------------", -- ADD s6, s2 ; build address from low and high + 16#040# => opCompC & "0101" & "0000000000000100", -- COMPARE s5, 0004 ; check for READ_MEM command + 16#041# => brJump & brZ & "--------0001001001",-- JUMP Z, 049 ; skip reading data word + 16#042# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data low + 16#043# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#044# => opLoadR & "0111" & "0010------------", -- LOAD s7, s2 ; store data low + 16#045# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data high + 16#046# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#047# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#048# => opAddR & "0111" & "0010------------", -- ADD s7, s2 ; build data from low and high + -- _getChecksum_: + 16#049# => brCall & brDo & "--------0010000110",-- CALL 086 ; get checksum + 16#04A# => opAndC & "0011" & "0000000011111111", -- AND s3, 00FF ; limit calculated checksum to 8 bit + 16#04B# => opCompR & "0011" & "0010------------", -- COMPARE s3, s2 ; test checksum + 16#04C# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#04D# => opLoadC & "0011" & "0000000000000000", -- LOAD s3, 0000 ; return OK + 16#04E# => brRet & brDo & "------------------",-- RETURN + -- _commandKo_: + 16#04F# => opLoadC & "0011" & "0000000000000001", -- LOAD s3, 0001 ; return KO + 16#050# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send NACK reply + ----------------------------------------------------------------- + -- _sendNAck_: + 16#051# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#052# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#053# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#054# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#055# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#056# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#057# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; negative Acknowledge + 16#058# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#059# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05A# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#05B# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#05C# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05D# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#05E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send WRITE_MEM reply + ----------------------------------------------------------------- + -- _sendWriteOk_: + 16#060# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#061# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#062# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#063# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#064# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#065# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#066# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#067# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#068# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#069# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#06A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#06B# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06C# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#06D# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06E# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send READ_MEM reply + ----------------------------------------------------------------- + -- _sendReadData_: + 16#06F# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#070# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#071# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#072# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#073# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#074# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#075# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#076# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#077# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#078# => opLoadC & "0010" & "0000000000000010", -- LOAD s2, 0002 ; packet length: 2 bytes + 16#079# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07A# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07B# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data low + 16#07C# => opAndC & "0010" & "0000000011111111", -- AND s2, 00FF ; keep low byte only + 16#07D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07F# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data high + 16#080# => brCall & brDo & "--------0010100101",-- CALL 0A5 ; shift MSBs down to LSBs + 16#081# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#082# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#083# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#084# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#085# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Get byte from serial port + ----------------------------------------------------------------- + -- _uartGetByte_: + 16#086# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#087# => opAddC & "0000" & "0000000000000001", -- ADD s0, 01 + --load s8, 0100 + -- _checkStat_: + 16#088# => opLoadC & "0010" & "0000000001000000", -- LOAD s2, 0040 ; add delay between bus reads + -- _delay0_: + 16#089# => opSubC & "0010" & "0000000000000001", -- SUB s2, 0001 + 16#08A# => brJump & brNZ & "--------0010001001",-- JUMP NZ, 089 + --sub s8, 0001 + --jump nz, continue + --load s2, 0035 + --call uartSendByte + --load s8, 0100 + -- _continue_: + 16#08B# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08C# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08D# => opTestC & "0001" & "0000000000000001", -- TEST s1, 0001 ; check "data ready" bit + 16#08E# => brJump & brZ & "--------0010001000",-- JUMP Z, 088 ; loop until bit is '1' + 16#08F# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART data register + 16#090# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + 16#091# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + --LOAD s8, s2 + 16#092# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Send byte to serial port + ----------------------------------------------------------------- + -- _uartSendByte_: + 16#093# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#094# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + -- _readStatus_: + 16#095# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#096# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#097# => opTestC & "0001" & "0000000000000010", -- TEST s1, 0002 ; check "sending data" bit + 16#098# => brJump & brZ & "--------0010011101",-- JUMP Z, 09D ; loop until bit is '1' + 16#099# => opLoadC & "0001" & "0000000001000000", -- LOAD s1, 0040 ; add delay between bus reads + -- _delay1_: + 16#09A# => opSubC & "0001" & "0000000000000001", -- SUB s1, 0001 + 16#09B# => brJump & brNZ & "--------0010011010",-- JUMP NZ, 09A + 16#09C# => brJump & brDo & "--------0010010101",-- JUMP 095 + -- _sendByte_: + 16#09D# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; write UART data register + 16#09E# => opOutputR & "0010" & "0000------------", -- OUTPUT s2, (S0) + 16#09F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the left + ----------------------------------------------------------------- + -- _shiftS2L8_: + 16#0A0# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftLeftLoop_: + 16#0A1# => opShRot & "0010" & shRotL & shRotLd0, -- SL0 s2 + 16#0A2# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A3# => brJump & brNZ & "--------0010100001",-- JUMP NZ, 0A1 + 16#0A4# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the right + ----------------------------------------------------------------- + -- _shiftS2R8_: + 16#0A5# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftRightLoop_: + 16#0A6# => opShRot & "0010" & shRotR & shRotLd0, -- SR0 s2 + 16#0A7# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A8# => brJump & brNZ & "--------0010100110",-- JUMP NZ, 0A6 + 16#0A9# => brRet & brDo & "------------------",-- RETURN + -- + --=============================================================== + -- End of instruction memory + --=============================================================== + -- _endOfMemory_: + 16#3FF# => brJump & brDo & "--------1111111111",-- JUMP 3FF + others => (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= memoryArray(to_integer(address)); + end if; + end if; + end process; + +END ARCHITECTURE mapped; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAMAddressCounter_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAMAddressCounter_studentVersion.vhd new file mode 100644 index 0000000..f9eaeb8 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAMAddressCounter_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF blockRAMAddressCounter IS +BEGIN + addr <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAMControl_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAMControl_studentVersion.vhd new file mode 100644 index 0000000..95ca788 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAMControl_studentVersion.vhd @@ -0,0 +1,6 @@ +ARCHITECTURE studentVersion OF blockRAMControl IS +BEGIN + cntIncr <= '0'; + memWr <= '0'; + memEn <= '0'; +END ARCHITECTURE studentVersion; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAM_Spartan2.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAM_Spartan2.vhd new file mode 100644 index 0000000..4de467b --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAM_Spartan2.vhd @@ -0,0 +1,29 @@ +ARCHITECTURE Spartan2 OF blockRAM IS + + subtype register_type is std_ulogic_vector(dataBitNb-1 downto 0); + type memory_type is array (0 to 2**addressBitNb-1) of register_type; + + signal memoryArray : memory_type; + +BEGIN + + portA: process(clock) + begin + if rising_edge(clock) then + if (en = '1') then + if (write = '1') then + memoryArray(to_integer(addr)) <= dataIn; + end if; + if reset = '1' then + dataOut <= (others => '0'); + elsif (write = '1') then + dataOut <= dataIn; + else + dataOut <= memoryArray(to_integer(addr)); + end if; + end if; + end if; + end process portA; + +END ARCHITECTURE Spartan2; + diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAM_Spartan3E.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAM_Spartan3E.vhd new file mode 100644 index 0000000..7b9e894 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/blockRAM_Spartan3E.vhd @@ -0,0 +1,44 @@ +USE std.textio.all; + +ARCHITECTURE Spartan3E OF blockRAM IS + + subtype registerType is std_ulogic_vector(dataBitNb-1 downto 0); + type memoryType is array (0 to 2**addressBitNb-1) of registerType; + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFileSpec : in string) return memoryType is + FILE ramContentFile : text open read_mode is ramContentFileSpec; + variable ramContentFileLine : line; + variable ramContent : memoryType; + variable ramCurrentWord : bit_vector(registerType'range); + variable index : natural := 0; --241; + begin + for index in ramContent'range loop +-- while not endfile(ramContentFile) loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramCurrentWord); + ramContent(index) := std_ulogic_vector(to_stdlogicvector(ramCurrentWord)); +-- index := index + 1; + end loop; + return ramContent; + end function; + + shared variable memoryArray: memoryType := ReadRamContentFromFile(initFileSpec); + +BEGIN + + portA: process(clock) + begin + if rising_edge(clock) then + if (en = '1') then + if (write = '1') then + memoryArray(to_integer(addr)) := dataIn; + dataOut <= dataIn; + else + dataOut <= memoryArray(to_integer(addr)); + end if; + end if; + end if; + end process portA; + +END ARCHITECTURE Spartan3E; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphAddressDecoder_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphAddressDecoder_studentVersion.vhd new file mode 100644 index 0000000..58b5a04 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphAddressDecoder_studentVersion.vhd @@ -0,0 +1,10 @@ +ARCHITECTURE studentVersion OF periphAddressDecoder IS +BEGIN + selControl <= '0'; +-- selSize <= '0'; + selSpeed <= '0'; + selX <= '0'; + selY <= '0'; + selZ <= '0'; +END ARCHITECTURE studentVersion; + diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphControlReg_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphControlReg_studentVersion.vhd new file mode 100644 index 0000000..73b4d1d --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphControlReg_studentVersion.vhd @@ -0,0 +1,6 @@ +ARCHITECTURE studentVersion OF periphControlReg IS +BEGIN + run <= '0'; + updatePattern <= '0'; + interpolateLinear <= '0'; +END ARCHITECTURE studentVersion; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSizeReg_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSizeReg_studentVersion.vhd new file mode 100644 index 0000000..0238147 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSizeReg_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF periphSizeReg IS +BEGIN + patternSize <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSpeedController_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSpeedController_studentVersion.vhd new file mode 100644 index 0000000..68a3938 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSpeedController_studentVersion.vhd @@ -0,0 +1,4 @@ +ARCHITECTURE studentVersion OF periphSpeedController IS +BEGIN + enableOut <= '0'; +END ARCHITECTURE studentVersion; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSpeedReg_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSpeedReg_studentVersion.vhd new file mode 100644 index 0000000..9efa810 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/periphSpeedReg_studentVersion.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE studentVersion OF periphSpeedReg IS +BEGIN + updatePeriod <= (others => '0'); +END ARCHITECTURE studentVersion; + diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/rom_mapped.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/rom_mapped.vhd new file mode 100644 index 0000000..24fc8c5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/rom_mapped.vhd @@ -0,0 +1,374 @@ +ARCHITECTURE mapped OF programRom IS + + subtype opCodeType is std_ulogic_vector(5 downto 0); + constant opLoadC : opCodeType := "000000"; + constant opLoadR : opCodeType := "000001"; + constant opInputC : opCodeType := "000100"; + constant opInputR : opCodeType := "000101"; + constant opFetchC : opCodeType := "000110"; + constant opFetchR : opCodeType := "000111"; + constant opAndC : opCodeType := "001010"; + constant opAndR : opCodeType := "001011"; + constant opOrC : opCodeType := "001100"; + constant opOrR : opCodeType := "001101"; + constant opXorC : opCodeType := "001110"; + constant opXorR : opCodeType := "001111"; + constant opTestC : opCodeType := "010010"; + constant opTestR : opCodeType := "010011"; + constant opCompC : opCodeType := "010100"; + constant opCompR : opCodeType := "010101"; + constant opAddC : opCodeType := "011000"; + constant opAddR : opCodeType := "011001"; + constant opAddCyC : opCodeType := "011010"; + constant opAddCyR : opCodeType := "011011"; + constant opSubC : opCodeType := "011100"; + constant opSubR : opCodeType := "011101"; + constant opSubCyC : opCodeType := "011110"; + constant opSubCyR : opCodeType := "011111"; + constant opShRot : opCodeType := "100000"; + constant opOutputC : opCodeType := "101100"; + constant opOutputR : opCodeType := "101101"; + constant opStoreC : opCodeType := "101110"; + constant opStoreR : opCodeType := "101111"; + + subtype shRotCinType is std_ulogic_vector(2 downto 0); + constant shRotLdC : shRotCinType := "00-"; + constant shRotLdM : shRotCinType := "01-"; + constant shRotLdL : shRotCinType := "10-"; + constant shRotLd0 : shRotCinType := "110"; + constant shRotLd1 : shRotCinType := "111"; + + constant registerAddressBitNb : positive := 4; + constant shRotPadLength : positive + := dataOut'length - opCodeType'length - registerAddressBitNb + - 1 - shRotCinType'length; + subtype shRotDirType is std_ulogic_vector(1+shRotPadLength-1 downto 0); + constant shRotL : shRotDirType := (0 => '0', others => '-'); + constant shRotR : shRotDirType := (0 => '1', others => '-'); + + subtype branchCodeType is std_ulogic_vector(4 downto 0); + constant brRet : branchCodeType := "10101"; + constant brCall : branchCodeType := "11000"; + constant brJump : branchCodeType := "11010"; + constant brReti : branchCodeType := "11100"; + constant brEni : branchCodeType := "11110"; + + subtype branchConditionType is std_ulogic_vector(2 downto 0); + constant brDo : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( + --=============================================================== + -- Beamer control + --=============================================================== + -- + ----------------------------------------------------------------- + -- register definitions + -- s0, s1: used for INPUT and OUTPUT operations + -- S2: returns UART data byte + -- S3: uart protocol checksum + -- S4: uart protocol packet id + -- S5: uart protocol command id + -- S6: uart protocol address + -- S7: uart protocol data + -- S8: copy of UART data byte for debug + ----------------------------------------------------------------- + -- + ----------------------------------------------------------------- + -- GPIO definitions + ----------------------------------------------------------------- + ----------------------------------------------------------------- + -- UART definitions + ----------------------------------------------------------------- + -- CONSTANT uartBaudCount, 023D ; 66E6 / 115 200 = 573 + -- CONSTANT uartpollDelay, 0100 + ----------------------------------------------------------------- + -- beamer peripheral definitions + ----------------------------------------------------------------- + -- CONSTANT beamerCtlInit, 1001 + -- + --=============================================================== + -- initializations + --=============================================================== + -- + ----------------------------------------------------------------- + -- initialize GPIO + ----------------------------------------------------------------- + 16#000# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#001# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#002# => opLoadC & "0001" & "0000000010101010", -- LOAD s1, AA + 16#003# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#004# => opLoadC & "0000" & "0000000000000000", -- LOAD s0, 0000 + 16#005# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#006# => opLoadC & "0001" & "0000000000001111", -- LOAD s1, 0F + 16#007# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize UART + ----------------------------------------------------------------- + 16#008# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 + 16#009# => opAddC & "0000" & "0000000000000010", -- ADD s0, 0002 + 16#00A# => opLoadC & "0001" & "0000000001000010", -- LOAD s1, 0042 + 16#00B# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + ----------------------------------------------------------------- + -- initialize beamer peripheral + ----------------------------------------------------------------- + 16#00C# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#00D# => opAddC & "0000" & "0000000000000000", -- ADD s0, 0000 + 16#00E# => opLoadC & "0001" & "0000010000000001", -- LOAD s1, 0401 + 16#00F# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + 16#010# => opLoadC & "0000" & "0000000000100000", -- LOAD s0, 0020 + 16#011# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + 16#012# => opLoadC & "0001" & "0000000000000100", -- LOAD s1, 0004 + 16#013# => opOutputR & "0001" & "0000------------", -- OUTPUT s1, (S0) + -- + --=============================================================== + -- Main loop + --=============================================================== + -- + ----------------------------------------------------------------- + -- Process commands from serial port + ----------------------------------------------------------------- + -- _main_: + 16#014# => brCall & brDo & "--------0000100001",-- CALL 021 ; get command from UART + 16#015# => opCompC & "0011" & "0000000000000000", -- COMPARE s3, 0000 ; check function return + 16#016# => brJump & brNZ & "--------0000011111",-- JUMP NZ, 01F + 16#017# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#018# => brJump & brNZ & "--------0000011100",-- JUMP NZ, 01C + 16#019# => opOutputR & "0111" & "0110------------", -- OUTPUT s7, (S6) ; write word to memory location + 16#01A# => brCall & brDo & "--------0001100000",-- CALL 060 ; send write acknowledge + 16#01B# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandRead_: + 16#01C# => opInputR & "0111" & "0110------------", -- INPUT s7, (S6) ; write word in memory location + 16#01D# => brCall & brDo & "--------0001101111",-- CALL 06F ; send back read data + 16#01E# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- _commandAbort_: + 16#01F# => brCall & brDo & "--------0001010001",-- CALL 051 + 16#020# => brJump & brDo & "--------0000010100",-- JUMP 014 + -- + --=============================================================== + -- Subroutines + --=============================================================== + -- + ----------------------------------------------------------------- + -- Get command from serial port + ----------------------------------------------------------------- + -- _uartGetCmd_: + 16#021# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command header + 16#022# => opCompC & "0010" & "0000000010101010", -- COMPARE s2, 00AA + 16#023# => brJump & brNZ & "--------0000100001",-- JUMP NZ, 021 ; loop until byte is AAh + 16#024# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#025# => brCall & brDo & "--------0010000110",-- CALL 086 ; get packet id + 16#026# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#027# => opLoadR & "0100" & "0010------------", -- LOAD s4, s2 ; store id for reply + 16#028# => brCall & brDo & "--------0010000110",-- CALL 086 ; get command + 16#029# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#02A# => opCompC & "0010" & "0000000000000011", -- COMPARE s2, 0003 ; check for WRITE_MEM command + 16#02B# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02C# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; check for READ_MEM command + 16#02D# => brJump & brZ & "--------0000101111",-- JUMP Z, 02F + 16#02E# => brJump & brDo & "--------0001001111",-- JUMP 04F ; no match + -- _commandOk_: + 16#02F# => opLoadR & "0101" & "0010------------", -- LOAD s5, s2 ; store command for action + 16#030# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data length + 16#031# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#032# => opCompC & "0101" & "0000000000000011", -- COMPARE s5, 0003 ; check for WRITE_MEM command + 16#033# => brJump & brZ & "--------0000110111",-- JUMP Z, 037 ; go to test write command length + 16#034# => opCompC & "0010" & "0000000000000010", -- COMPARE s2, 0002 ; verify READ_MEM length + 16#035# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#036# => brJump & brDo & "--------0000111001",-- JUMP 039 + -- _testWrLength_: + 16#037# => opCompC & "0010" & "0000000000000100", -- COMPARE s2, 0004 ; verify WRITE_MEM length + 16#038# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + -- _getAddress_: + 16#039# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address low + 16#03A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03B# => opLoadR & "0110" & "0010------------", -- LOAD s6, s2 ; store address low + 16#03C# => brCall & brDo & "--------0010000110",-- CALL 086 ; get address high + 16#03D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#03E# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#03F# => opAddR & "0110" & "0010------------", -- ADD s6, s2 ; build address from low and high + 16#040# => opCompC & "0101" & "0000000000000100", -- COMPARE s5, 0004 ; check for READ_MEM command + 16#041# => brJump & brZ & "--------0001001001",-- JUMP Z, 049 ; skip reading data word + 16#042# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data low + 16#043# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#044# => opLoadR & "0111" & "0010------------", -- LOAD s7, s2 ; store data low + 16#045# => brCall & brDo & "--------0010000110",-- CALL 086 ; get data high + 16#046# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#047# => brCall & brDo & "--------0010100000",-- CALL 0A0 + 16#048# => opAddR & "0111" & "0010------------", -- ADD s7, s2 ; build data from low and high + -- _getChecksum_: + 16#049# => brCall & brDo & "--------0010000110",-- CALL 086 ; get checksum + 16#04A# => opAndC & "0011" & "0000000011111111", -- AND s3, 00FF ; limit calculated checksum to 8 bit + 16#04B# => opCompR & "0011" & "0010------------", -- COMPARE s3, s2 ; test checksum + 16#04C# => brJump & brNZ & "--------0001001111",-- JUMP NZ, 04F + 16#04D# => opLoadC & "0011" & "0000000000000000", -- LOAD s3, 0000 ; return OK + 16#04E# => brRet & brDo & "------------------",-- RETURN + -- _commandKo_: + 16#04F# => opLoadC & "0011" & "0000000000000001", -- LOAD s3, 0001 ; return KO + 16#050# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send NACK reply + ----------------------------------------------------------------- + -- _sendNAck_: + 16#051# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#052# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#053# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#054# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#055# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#056# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#057# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; negative Acknowledge + 16#058# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#059# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05A# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#05B# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#05C# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05D# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#05E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#05F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send WRITE_MEM reply + ----------------------------------------------------------------- + -- _sendWriteOk_: + 16#060# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#061# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#062# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#063# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#064# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#065# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#066# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#067# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#068# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#069# => opLoadC & "0010" & "0000000000000000", -- LOAD s2, 0000 ; packet length: no data + 16#06A# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#06B# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06C# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#06D# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#06E# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- send READ_MEM reply + ----------------------------------------------------------------- + -- _sendReadData_: + 16#06F# => opLoadC & "0010" & "0000000010101010", -- LOAD s2, 00AA ; send header + 16#070# => opLoadR & "0011" & "0010------------", -- LOAD s3, s2 ; prepare checksum + 16#071# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#072# => opLoadR & "0010" & "0100------------", -- LOAD s2, s4 ; packet id + 16#073# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#074# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#075# => opLoadR & "0010" & "0101------------", -- LOAD s2, s5 ; received command + 16#076# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#077# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#078# => opLoadC & "0010" & "0000000000000010", -- LOAD s2, 0002 ; packet length: 2 bytes + 16#079# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07A# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07B# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data low + 16#07C# => opAndC & "0010" & "0000000011111111", -- AND s2, 00FF ; keep low byte only + 16#07D# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#07E# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#07F# => opLoadR & "0010" & "0111------------", -- LOAD s2, s7 ; data high + 16#080# => brCall & brDo & "--------0010100101",-- CALL 0A5 ; shift MSBs down to LSBs + 16#081# => opAddR & "0011" & "0010------------", -- ADD s3, s2 ; calculate checksum + 16#082# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#083# => opLoadR & "0010" & "0011------------", -- LOAD s2, s3 ; checksum + 16#084# => brCall & brDo & "--------0010010011",-- CALL 093 + 16#085# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Get byte from serial port + ----------------------------------------------------------------- + -- _uartGetByte_: + 16#086# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#087# => opAddC & "0000" & "0000000000000001", -- ADD s0, 01 + --load s8, 0100 + -- _checkStat_: + 16#088# => opLoadC & "0010" & "0000000001000000", -- LOAD s2, 0040 ; add delay between bus reads + -- _delay0_: + 16#089# => opSubC & "0010" & "0000000000000001", -- SUB s2, 0001 + 16#08A# => brJump & brNZ & "--------0010001001",-- JUMP NZ, 089 + --sub s8, 0001 + --jump nz, continue + --load s2, 0035 + --call uartSendByte + --load s8, 0100 + -- _continue_: + 16#08B# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08C# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#08D# => opTestC & "0001" & "0000000000000001", -- TEST s1, 0001 ; check "data ready" bit + 16#08E# => brJump & brZ & "--------0010001000",-- JUMP Z, 088 ; loop until bit is '1' + 16#08F# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART data register + 16#090# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + 16#091# => opInputR & "0010" & "0000------------", -- INPUT s2, (S0) + --LOAD s8, s2 + 16#092# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- Send byte to serial port + ----------------------------------------------------------------- + -- _uartSendByte_: + 16#093# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; read UART satus register + 16#094# => opAddC & "0000" & "0000000000000001", -- ADD s0, 0001 + -- _readStatus_: + 16#095# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#096# => opInputR & "0001" & "0000------------", -- INPUT s1, (S0) + 16#097# => opTestC & "0001" & "0000000000000010", -- TEST s1, 0002 ; check "sending data" bit + 16#098# => brJump & brZ & "--------0010011101",-- JUMP Z, 09D ; loop until bit is '1' + 16#099# => opLoadC & "0001" & "0000000001000000", -- LOAD s1, 0040 ; add delay between bus reads + -- _delay1_: + 16#09A# => opSubC & "0001" & "0000000000000001", -- SUB s1, 0001 + 16#09B# => brJump & brNZ & "--------0010011010",-- JUMP NZ, 09A + 16#09C# => brJump & brDo & "--------0010010101",-- JUMP 095 + -- _sendByte_: + 16#09D# => opLoadC & "0000" & "0000000000010000", -- LOAD s0, 0010 ; write UART data register + 16#09E# => opOutputR & "0010" & "0000------------", -- OUTPUT s2, (S0) + 16#09F# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the left + ----------------------------------------------------------------- + -- _shiftS2L8_: + 16#0A0# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftLeftLoop_: + 16#0A1# => opShRot & "0010" & shRotL & shRotLd0, -- SL0 s2 + 16#0A2# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A3# => brJump & brNZ & "--------0010100001",-- JUMP NZ, 0A1 + 16#0A4# => brRet & brDo & "------------------",-- RETURN + -- + ----------------------------------------------------------------- + -- shift s2 8 bits to the right + ----------------------------------------------------------------- + -- _shiftS2R8_: + 16#0A5# => opLoadC & "0000" & "0000000000001000", -- LOAD s0, 8 ; loop count + -- _shiftRightLoop_: + 16#0A6# => opShRot & "0010" & shRotR & shRotLd0, -- SR0 s2 + 16#0A7# => opSubC & "0000" & "0000000000000001", -- SUB s0, 0001 + 16#0A8# => brJump & brNZ & "--------0010100110",-- JUMP NZ, 0A6 + 16#0A9# => brRet & brDo & "------------------",-- RETURN + -- + --=============================================================== + -- End of instruction memory + --=============================================================== + -- _endOfMemory_: + 16#3FF# => brJump & brDo & "--------1111111111",-- JUMP 3FF + others => (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= memoryArray(to_integer(address)); + end if; + end if; + end process; + +END ARCHITECTURE mapped; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hdl/sinCosTable_studentVersion.vhd b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/sinCosTable_studentVersion.vhd new file mode 100644 index 0000000..173267c --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hdl/sinCosTable_studentVersion.vhd @@ -0,0 +1,5 @@ +ARCHITECTURE studentVersion OF sinCosTable IS +BEGIN + sine <= (others => '0'); + cosine <= (others => '0'); +END ARCHITECTURE studentVersion; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_struct.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_struct.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamer_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_struct.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_struct.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeameroperator_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_struct.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_struct.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_ahbbeamerregisters_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamer.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamer.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamer.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamersoc_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamersoc_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamersoc_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamersoc_struct.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamersoc_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_beamersoc_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAMAddressCounter_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAMAddressCounter_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAMAddressCounter_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAMControl_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAMControl_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAMControl_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAM_Spartan2.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAM_Spartan2.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAM_Spartan2.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAM_Spartan3E.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAM_Spartan3E.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockRAM_Spartan3E.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockram_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockram_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockram_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockram_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockram_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockram_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramaddresscounter_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramaddresscounter_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramaddresscounter_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramaddresscounter_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramaddresscounter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramaddresscounter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramcontrol_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramcontrol_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramcontrol_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramcontrol_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramcontrol_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_blockramcontrol_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphAddressDecoder_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphAddressDecoder_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphAddressDecoder_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphControlReg_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphControlReg_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphControlReg_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSizeReg_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSizeReg_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSizeReg_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSpeedController_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSpeedController_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSpeedController_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSpeedReg_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSpeedReg_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphSpeedReg_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphaddressdecoder_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphaddressdecoder_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphaddressdecoder_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphaddressdecoder_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphaddressdecoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphaddressdecoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphcontrolreg_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphcontrolreg_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphcontrolreg_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphcontrolreg_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphcontrolreg_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphcontrolreg_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedcontroller_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedcontroller_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedcontroller_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedcontroller_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedcontroller_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedcontroller_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedreg_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedreg_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedreg_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedreg_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedreg_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_periphspeedreg_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_programrom_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_programrom_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_programrom_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_rom_mapped.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_rom_mapped.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_rom_mapped.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sinCosTable_studentVersion.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sinCosTable_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sinCosTable_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sincostable_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sincostable_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sincostable_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sincostable_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sincostable_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/.hdlsidedata/_sincostable_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamer._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamer._epf new file mode 100644 index 0000000..85cc248 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamer._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom ahb@beamer/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamerblanking._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamerblanking._epf new file mode 100644 index 0000000..c6b8ef2 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamerblanking._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom ahb@beamer@blanking/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeameroperator._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeameroperator._epf new file mode 100644 index 0000000..4e4a27c --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeameroperator._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom ahb@beamer@operator/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamerregisters._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamerregisters._epf new file mode 100644 index 0000000..96629ce --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_ahbbeamerregisters._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom ahb@beamer@registers/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiph._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiph._epf new file mode 100644 index 0000000..82aff67 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiph._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom beamer@periph/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphblanking._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphblanking._epf new file mode 100644 index 0000000..4254734 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphblanking._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom beamer@periph@blanking/struct.bd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphoperator._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphoperator._epf new file mode 100644 index 0000000..7886b47 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphoperator._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom beamer@periph@operator/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 0 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphregisters._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphregisters._epf new file mode 100644 index 0000000..82d8c6e --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamerperiphregisters._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom beamer@periph@registers/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 0 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamersoc._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamersoc._epf new file mode 100644 index 0000000..8d18be3 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_beamersoc._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom beamer@soc/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockram._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockram._epf new file mode 100644 index 0000000..e8cefbe --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockram._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Spartan3E +DEFAULT_FILE atom blockRAM_Spartan3E.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockramaddresscounter._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockramaddresscounter._epf new file mode 100644 index 0000000..03318ce --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockramaddresscounter._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom blockRAMAddressCounter_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockramcontrol._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockramcontrol._epf new file mode 100644 index 0000000..79021f5 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_blockramcontrol._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom blockRAMControl_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphaddressdecoder._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphaddressdecoder._epf new file mode 100644 index 0000000..5427f48 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphaddressdecoder._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom periphAddressDecoder_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphcontrolreg._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphcontrolreg._epf new file mode 100644 index 0000000..7cbdd9d --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphcontrolreg._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom periphControlReg_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphsizereg._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphsizereg._epf new file mode 100644 index 0000000..cdb6485 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphsizereg._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom periphSizeReg_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphspeedcontroller._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphspeedcontroller._epf new file mode 100644 index 0000000..97f3a4d --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphspeedcontroller._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom periphSpeedController_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphspeedreg._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphspeedreg._epf new file mode 100644 index 0000000..5ee021b --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_periphspeedreg._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom periphSpeedReg_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_programrom._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_programrom._epf new file mode 100644 index 0000000..04f9d0f --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_programrom._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom rom_mapped.vhd +DEFAULT_ARCHITECTURE atom mapped diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/_sincostable._epf b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_sincostable._epf new file mode 100644 index 0000000..7a46612 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/_sincostable._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom sinCosTable_studentVersion.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer/struct.bd b/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer/struct.bd new file mode 100644 index 0000000..eeb8d8b --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer/struct.bd @@ -0,0 +1,5403 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +instances [ +(Instance +name "I_regs" +duLibraryName "SystemOnChip" +duName "ahbBeamerRegisters" +elements [ +(GiElement +name "updatePeriodBitNb" +type "positive" +value "updatePeriodBitNb" +) +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "patternAddressBitNb" +type "positive" +value "patternAddressBitNb" +) +(GiElement +name "testOutBitNb" +type "positive" +value "testOutBitNb" +) +] +mwi 0 +uid 17506,0 +) +(Instance +name "I_op" +duLibraryName "SystemOnChip" +duName "ahbBeamerOperator" +elements [ +(GiElement +name "updatePeriodBitNb" +type "positive" +value "updatePeriodBitNb" +) +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +mwi 0 +uid 17559,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb2" +number "2" +) +(EmbeddedInstance +name "eb3" +number "3" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\ahb@beamer\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\ahb@beamer\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\ahb@beamer" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip\\hds\\ahbBeamer" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "ahbBeamer" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:00:20" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair 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+) +declText (MLText +uid 15575,0 +va (VaSet +) +xt "2000,4000,31200,5200" +st "testOut : std_ulogic_vector(1 TO testOutBitNb)" +) +) +*14 (PortIoOut +uid 15582,0 +shape (CompositeShape +uid 15583,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15584,0 +sl 0 +ro 270 +xt "62500,-7375,64000,-6625" +) +(Line +uid 15585,0 +sl 0 +ro 270 +xt "62000,-7000,62500,-7000" +pts [ +"62000,-7000" +"62500,-7000" +] +) +] +) +tg (WTG +uid 15586,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15587,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "65000,-7700,82500,-6200" +st "testOut : (1 TO testOutBitNb)" +blo "65000,-6500" +tm "WireNameMgr" +) +) +) +*15 (HdlText +uid 16006,0 +optionalChildren [ +*16 (EmbeddedText +uid 16011,0 +commentText (CommentText +uid 16012,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 16013,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "62000,-22000,78000,-12000" +) +oxt "0,0,18000,5000" +text (MLText +uid 16014,0 +va (VaSet +) +xt "62200,-21800,77500,-12200" +st " +--process +--begin +-- newPolynom <= '0'; +-- for index in 1 to 2**4-1 loop +-- wait until rising_edge(clock); +-- end loop; +-- newPolynom <= '1'; +-- wait until rising_edge(clock); +--end process; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 16007,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "62000,-23000,78000,-11000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 16008,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*17 (Text +uid 16009,0 +va (VaSet +) +xt "62400,-11000,64000,-10000" +st "eb2" +blo "62400,-10200" +tm "HdlTextNameMgr" +) +*18 (Text +uid 16010,0 +va (VaSet +) +xt "62400,-10000,63200,-9000" +st "2" +blo "62400,-9200" +tm "HdlTextNumberMgr" +) +] +) +) +*19 (Net +uid 16103,0 +decl (Decl +n "newPolynom" +t "std_ulogic" +o 21 +suid 83,0 +) +declText (MLText +uid 16104,0 +va (VaSet +) +xt "2000,26400,22200,27600" +st "SIGNAL newPolynom : std_ulogic" +) +) +*20 (PortIoIn +uid 16666,0 +shape (CompositeShape +uid 16667,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16668,0 +sl 0 +ro 270 +xt "36000,625,37500,1375" +) +(Line +uid 16669,0 +sl 0 +ro 270 +xt "37500,1000,38000,1000" +pts [ +"37500,1000" +"38000,1000" +] +) +] +) +tg (WTG +uid 16670,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16671,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "11900,500,35000,2000" +st "hAddr : (ahbAddressBitNb-1 downto 0)" +ju 2 +blo "35000,1700" +tm "WireNameMgr" +) +) +) +*21 (Net +uid 16678,0 +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 downto 0)" +o 2 +suid 84,0 +) +declText (MLText +uid 16679,0 +va (VaSet +) +xt "2000,-800,31600,400" +st "hAddr : unsigned(ahbAddressBitNb-1 downto 0)" +) +) +*22 (PortIoIn +uid 16729,0 +shape (CompositeShape +uid 16730,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16731,0 +sl 0 +ro 270 +xt "36000,2625,37500,3375" +) +(Line +uid 16732,0 +sl 0 +ro 270 +xt "37500,3000,38000,3000" +pts [ +"37500,3000" +"38000,3000" +] +) +] +) +tg (WTG +uid 16733,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16734,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "12700,2500,35000,4000" +st "hWData : (ahbDataBitNb-1 downto 0)" +ju 2 +blo "35000,3700" +tm "WireNameMgr" +) +) +) +*23 (Net +uid 16741,0 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 4 +suid 85,0 +) +declText (MLText +uid 16742,0 +va (VaSet +) +xt "2000,1600,34900,2800" +st "hWData : std_ulogic_vector(ahbDataBitNb-1 downto 0)" +) +) +*24 (PortIoOut +uid 16743,0 +shape (CompositeShape +uid 16744,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16745,0 +sl 0 +ro 90 +xt "36000,10625,37500,11375" +) +(Line +uid 16746,0 +sl 0 +ro 90 +xt "37500,11000,38000,11000" +pts [ +"38000,11000" +"37500,11000" +] +) +] +) +tg (WTG +uid 16747,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16748,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "12900,10300,35000,11800" +st "hRData : (ahbDataBitNb-1 downto 0)" +ju 2 +blo "35000,11500" +tm "WireNameMgr" +) +) +) +*25 (Net +uid 16755,0 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 7 +suid 86,0 +) +declText (MLText +uid 16756,0 +va (VaSet +) +xt "2000,5200,34700,6400" +st "hRData : std_ulogic_vector(ahbDataBitNb-1 downto 0)" +) +) +*26 (PortIoIn +uid 16757,0 +shape (CompositeShape +uid 16758,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16759,0 +sl 0 +ro 270 +xt "36000,4625,37500,5375" +) +(Line +uid 16760,0 +sl 0 +ro 270 +xt "37500,5000,38000,5000" +pts [ +"37500,5000" +"38000,5000" +] +) +] +) +tg (WTG +uid 16761,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16762,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "12600,4500,35000,6000" +st "hTrans : (ahbTransBitNb-1 downto 0)" +ju 2 +blo "35000,5700" +tm "WireNameMgr" +) +) +) +*27 (Net +uid 16769,0 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 downto 0)" +o 8 +suid 87,0 +) +declText (MLText +uid 16770,0 +va (VaSet +) +xt "2000,6400,35000,7600" +st "hTrans : std_ulogic_vector(ahbTransBitNb-1 downto 0)" +) +) +*28 (PortIoIn +uid 16771,0 +shape (CompositeShape +uid 16772,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16773,0 +sl 0 +ro 270 +xt "36000,6625,37500,7375" +) +(Line +uid 16774,0 +sl 0 +ro 270 +xt "37500,7000,38000,7000" +pts [ +"37500,7000" +"38000,7000" +] +) +] +) +tg (WTG +uid 16775,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16776,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "30800,6500,35000,8000" +st "hWrite" +ju 2 +blo "35000,7700" +tm "WireNameMgr" +) +) +) +*29 (Net +uid 16783,0 +decl (Decl +n "hWrite" +t "std_ulogic" +o 9 +suid 88,0 +) +declText (MLText +uid 16784,0 +va (VaSet +) +xt "2000,7600,15900,8800" +st "hWrite : std_ulogic" +) +) +*30 (PortIoIn +uid 16785,0 +shape (CompositeShape +uid 16786,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16787,0 +sl 0 +ro 270 +xt "36000,8625,37500,9375" +) +(Line +uid 16788,0 +sl 0 +ro 270 +xt "37500,9000,38000,9000" +pts [ +"37500,9000" +"38000,9000" +] +) +] +) +tg (WTG +uid 16789,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16790,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "31800,8500,35000,10000" +st "hSel" +ju 2 +blo "35000,9700" +tm "WireNameMgr" +) +) +) +*31 (Net +uid 16797,0 +decl (Decl +n "hSel" +t "std_ulogic" +o 10 +suid 89,0 +) +declText (MLText +uid 16798,0 +va (VaSet +) +xt "2000,8800,15500,10000" +st "hSel : std_ulogic" +) +) +*32 (Net +uid 16811,0 +decl (Decl +n "hReady" +t "std_ulogic" +o 11 +suid 90,0 +) +declText (MLText +uid 16812,0 +va (VaSet +) +xt "2000,10000,16400,11200" +st "hReady : std_ulogic" +) +) +*33 (Net +uid 16825,0 +decl (Decl +n "hResp" +t "std_ulogic" +o 12 +suid 91,0 +) +declText (MLText +uid 16826,0 +va (VaSet +) +xt "2000,11200,16100,12400" +st "hResp : std_ulogic" +) +) +*34 (PortIoIn +uid 16933,0 +shape (CompositeShape +uid 16934,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16935,0 +sl 0 +ro 270 +xt "36000,18625,37500,19375" +) +(Line +uid 16936,0 +sl 0 +ro 270 +xt "37500,19000,38000,19000" +pts [ +"37500,19000" +"38000,19000" +] +) +] +) +tg (WTG +uid 16937,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16938,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "31800,18500,35000,20000" +st "hClk" +ju 2 +blo "35000,19700" +tm "WireNameMgr" +) +) +) +*35 (Net +uid 16945,0 +decl (Decl +n "hClk" +t "std_ulogic" +o 13 +suid 92,0 +) +declText (MLText +uid 16946,0 +va (VaSet +) +xt "2000,12400,15600,13600" +st "hClk : std_ulogic" +) +) +*36 (PortIoIn +uid 16947,0 +shape (CompositeShape +uid 16948,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16949,0 +sl 0 +ro 270 +xt "36000,20625,37500,21375" +) +(Line +uid 16950,0 +sl 0 +ro 270 +xt "37500,21000,38000,21000" +pts [ +"37500,21000" +"38000,21000" +] +) +] +) +tg (WTG +uid 16951,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16952,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "28900,20500,35000,22000" +st "hReset_n" +ju 2 +blo "35000,21700" +tm "WireNameMgr" +) +) +) +*37 (Net +uid 16959,0 +decl (Decl +n "hReset_n" +t "std_ulogic" +o 14 +suid 93,0 +) +declText (MLText +uid 16960,0 +va (VaSet +) +xt "2000,13600,16800,14800" +st "hReset_n : std_ulogic" +) +) +*38 (PortIoOut +uid 17020,0 +shape (CompositeShape +uid 17021,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 17022,0 +sl 0 +ro 90 +xt "36000,14625,37500,15375" +) +(Line +uid 17023,0 +sl 0 +ro 90 +xt "37500,15000,38000,15000" +pts [ +"38000,15000" +"37500,15000" +] +) +] +) +tg (WTG +uid 17024,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17025,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "30600,14300,35000,15800" +st "hResp" +ju 2 +blo "35000,15500" +tm "WireNameMgr" +) +) +) +*39 (PortIoOut +uid 17026,0 +shape (CompositeShape +uid 17027,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 17028,0 +sl 0 +ro 90 +xt "36000,12625,37500,13375" +) +(Line +uid 17029,0 +sl 0 +ro 90 +xt "37500,13000,38000,13000" +pts [ +"38000,13000" +"37500,13000" +] +) +] +) +tg (WTG +uid 17030,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17031,0 +va (VaSet +isHidden 1 +font "Arial,12,0" +) +xt "30100,12300,35000,13800" +st "hReady" +ju 2 +blo "35000,13500" +tm "WireNameMgr" +) +) +) +*40 (HdlText +uid 17109,0 +optionalChildren [ +*41 (EmbeddedText +uid 17114,0 +commentText (CommentText +uid 17115,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 17116,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "66000,24000,74000,26000" +) +oxt "0,0,18000,5000" +text (MLText +uid 17117,0 +va (VaSet +) +xt "66200,24200,74100,25400" +st " +reset <= not hReset_n; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 8000 +) +) +) +] +shape (Rectangle +uid 17110,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "66000,23000,74000,27000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 17111,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*42 (Text +uid 17112,0 +va (VaSet +) +xt "66400,27000,68000,28000" +st "eb3" +blo "66400,27800" +tm "HdlTextNameMgr" +) +*43 (Text +uid 17113,0 +va (VaSet +) +xt "66400,28000,67200,29000" +st "3" +blo "66400,28800" +tm "HdlTextNumberMgr" +) +] +) +) +*44 (SaComponent +uid 17506,0 +optionalChildren [ +*45 (CptPort +uid 17438,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17439,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,18625,46000,19375" +) +tg (CPTG +uid 17440,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17441,0 +va (VaSet +font "Arial,9,0" +) +xt "47000,18400,49400,19600" +st "hClk" +blo "47000,19300" +) +) +thePort (LogicalPort +decl (Decl +n "hClk" +t "std_ulogic" +o 8 +suid 1,0 +) +) +) +*46 (CptPort +uid 17442,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17443,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,625,46000,1375" +) +tg (CPTG +uid 17444,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17445,0 +va (VaSet +font "Arial,9,0" +) +xt "47000,400,49900,1600" +st "hAddr" +blo "47000,1300" +) +) +thePort (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 downto 0)" +o 10 +suid 2,0 +) +) +) +*47 (CptPort +uid 17446,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17447,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,10625,46000,11375" +) +tg (CPTG +uid 17448,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17449,0 +va (VaSet +font "Arial,9,0" +) +xt "47000,10400,50700,11600" +st "hRData" +blo "47000,11300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 9 +suid 11,0 +) +) +) +*48 (CptPort +uid 17450,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17451,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "53625,-3750,54375,-3000" +) +tg (CPTG +uid 17452,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17453,0 +va (VaSet +font "Arial,9,0" +) +xt "52000,-2000,55600,-800" +st "testOut" +blo "52000,-1100" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO testOutBitNb)" +o 1 +suid 12,0 +) +) +) +*49 (CptPort +uid 17454,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17455,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,625,62750,1375" +) +tg (CPTG +uid 17456,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17457,0 +va (VaSet +font "Arial,9,0" +) +xt "59200,400,61000,1600" +st "run" +ju 2 +blo "61000,1300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "run" +t "std_ulogic" +o 4 +suid 2014,0 +) +) +) +*50 (CptPort +uid 17458,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17459,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,4625,62750,5375" +) +tg (CPTG +uid 17460,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17461,0 +va (VaSet +font "Arial,9,0" +) +xt "54600,4400,61000,5600" +st "updatePeriod" +ju 2 +blo "61000,5300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(updatePeriodBitNb-1 DOWNTO 0)" +o 5 +suid 2015,0 +) +) +) +*51 (CptPort +uid 17462,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17463,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,8625,62750,9375" +) +tg (CPTG +uid 17464,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17465,0 +va (VaSet +font "Arial,9,0" +) +xt "57900,8400,61000,9600" +st "memX" +ju 2 +blo "61000,9300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memX" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 2 +suid 2016,0 +) +) +) +*52 (CptPort +uid 17466,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17467,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,10625,62750,11375" +) +tg (CPTG +uid 17468,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17469,0 +va (VaSet +font "Arial,9,0" +) +xt "57700,10400,61000,11600" +st "memY" +ju 2 +blo "61000,11300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memY" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 3 +suid 2017,0 +) +) +) +*53 (CptPort +uid 17470,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17471,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,2625,62750,3375" +) +tg (CPTG +uid 17472,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17473,0 +va (VaSet +font "Arial,9,0" +) +xt "54500,2400,61000,3600" +st "interpolateLin" +ju 2 +blo "61000,3300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "interpolateLin" +t "std_ulogic" +o 6 +suid 2018,0 +) +) +) +*54 (CptPort +uid 17474,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17475,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,20625,46000,21375" +) +tg (CPTG +uid 17476,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17477,0 +va (VaSet +font "Arial,9,0" +) +xt "47000,20400,51500,21600" +st "hReset_n" +blo "47000,21300" +) +) +thePort (LogicalPort +decl (Decl +n "hReset_n" +t "std_ulogic" +o 11 +suid 2021,0 +) +) +) +*55 (CptPort +uid 17478,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17479,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,6625,62750,7375" +) +tg (CPTG +uid 17480,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17481,0 +va (VaSet +font "Arial,9,0" +) +xt "54700,6400,61000,7600" +st "newPolynom" +ju 2 +blo "61000,7300" +) +) +thePort (LogicalPort +decl (Decl +n "newPolynom" +t "std_ulogic" +o 7 +suid 2022,0 +) +) +) +*56 (CptPort +uid 17482,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17483,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,2625,46000,3375" +) +tg (CPTG +uid 17484,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17485,0 +va (VaSet +font "Arial,9,0" +) +xt "47000,2400,50900,3600" +st "hWData" +blo "47000,3300" +) +) +thePort (LogicalPort +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 12 +suid 2023,0 +) +) +) +*57 (CptPort +uid 17486,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17487,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,4625,46000,5375" +) +tg (CPTG +uid 17488,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 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"214000,57100,242000,58100" +st "SIGNAL patternSize : unsigned(dataBitNb/2-1 DOWNTO 0)" +) +) +*89 (PortIoIn +uid 1565,0 +shape (CompositeShape +uid 1566,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1567,0 +sl 0 +ro 270 +xt "17000,9625,18500,10375" +) +(Line +uid 1568,0 +sl 0 +ro 270 +xt "18500,10000,19000,10000" +pts [ +"18500,10000" +"19000,10000" +] +) +] +) +tg (WTG +uid 1569,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1570,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-7800,9300,16000,10700" +st "dataIn : (dataBitNb-1 DOWNTO 0)" +ju 2 +blo "16000,10500" +tm "WireNameMgr" +) +) +) +*90 (PortIoOut +uid 1577,0 +shape (CompositeShape +uid 1578,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1579,0 +sl 0 +ro 90 +xt "17000,3625,18500,4375" +) +(Line +uid 1580,0 +sl 0 +ro 90 +xt "18500,4000,19000,4000" +pts [ +"19000,4000" +"18500,4000" +] +) +] +) +tg (WTG +uid 1581,0 +ps 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"VerticalLayoutStrategy" +f (Text +uid 1795,0 +va (VaSet +) +xt "76000,69400,80800,70600" +st "dataOut" +blo "76000,70400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dataOut" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 3 +) +) +) +*97 (CptPort +uid 1796,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1797,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,73625,75000,74375" +) +tg (CPTG +uid 1798,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1799,0 +va (VaSet +) +xt "76000,73400,84400,74600" +st "writeHighByte" +blo "76000,74400" +) +) +thePort (LogicalPort +decl (Decl +n "writeHighByte" +t "std_ulogic" +o 4 +) +) +) +*98 (CptPort +uid 1800,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1801,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,77625,75000,78375" +) +tg (CPTG +uid 1802,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1803,0 +va (VaSet +) +xt "76000,77400,77900,78600" +st "en" +blo "76000,78400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 5 +) +) +) +*99 (CptPort +uid 1804,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1805,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,81625,75000,82375" +) +tg (CPTG +uid 1806,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1807,0 +va (VaSet +) +xt "76000,81400,79400,82600" +st "clock" +blo "76000,82400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 6 +) +) +) +*100 (CptPort +uid 1808,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1809,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,83625,75000,84375" +) +tg (CPTG +uid 1810,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1811,0 +va (VaSet +) +xt "76000,83400,79300,84600" +st "reset" +blo "76000,84400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 7 +) +) +) +*101 (CptPort +uid 1812,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1813,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,75625,75000,76375" +) +tg (CPTG +uid 1814,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1815,0 +va (VaSet +) +xt "76000,75400,84000,76600" +st "writeLowByte" +blo "76000,76400" +) +) +thePort (LogicalPort +decl (Decl +n "writeLowByte" +t "std_ulogic" +o 8 +) +) +) +] +shape (Rectangle +uid 1817,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "75000,64000,91000,86000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1818,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*102 (Text +uid 1819,0 +va (VaSet +) +xt "75600,85800,79900,87000" +st "Curves" +blo "75600,86800" +tm "BdLibraryNameMgr" +) +*103 (Text +uid 1820,0 +va (VaSet +) +xt "75600,86800,85100,88000" +st "periphSpeedReg" +blo "75600,87800" +tm "CptNameMgr" +) +*104 (Text +uid 1821,0 +va (VaSet +) +xt "75600,87800,77500,89000" +st "I3" +blo "75600,88800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1822,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1823,0 +text (MLText +uid 1824,0 +va (VaSet +font "Verdana,8,0" +) +xt "75000,89600,91600,90600" +st "dataBitNb = dataBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*105 (SaComponent +uid 1853,0 +optionalChildren [ +*106 (CptPort +uid 1825,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1826,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91000,39625,91750,40375" +) +tg (CPTG +uid 1827,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1828,0 +va (VaSet +) +xt "82900,39400,90000,40600" +st "patternSize" +ju 2 +blo "90000,40400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "patternSize" +t "unsigned" +b "(dataBitNb/2-1 DOWNTO 0)" +o 1 +) +) +) +*107 (CptPort +uid 1829,0 +ps "OnEdgeStrategy" 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+xt "74250,45625,75000,46375" +) +tg (CPTG +uid 1839,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1840,0 +va (VaSet +) +xt "76000,45400,79100,46600" +st "write" +blo "76000,46400" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 4 +) +) +) +*110 (CptPort +uid 1841,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1842,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,47625,75000,48375" +) +tg (CPTG +uid 1843,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1844,0 +va (VaSet +) +xt "76000,47400,77900,48600" +st "en" +blo "76000,48400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 5 +) +) +) +*111 (CptPort +uid 1845,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1846,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,51625,75000,52375" +) +tg (CPTG +uid 1847,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1848,0 +va (VaSet +) +xt "76000,51400,79400,52600" +st "clock" +blo "76000,52400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 6 +) +) +) +*112 (CptPort +uid 1849,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1850,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,53625,75000,54375" +) +tg (CPTG +uid 1851,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1852,0 +va (VaSet +) +xt "76000,53400,79300,54600" +st "reset" +blo "76000,54400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 7 +) +) +) +] +shape (Rectangle +uid 1854,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "75000,36000,91000,56000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1855,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*113 (Text +uid 1856,0 +va (VaSet +) +xt "75600,55800,79900,57000" +st "Curves" +blo "75600,56800" +tm "BdLibraryNameMgr" +) +*114 (Text +uid 1857,0 +va (VaSet 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"triggerOut" +ju 2 +blo "176000,176400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "triggerOut" +t "std_ulogic" +o 1 +) +) +) +*118 (CptPort +uid 1907,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1908,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,179625,161000,180375" +) +tg (CPTG +uid 1909,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1910,0 +va (VaSet +) +xt "162000,179400,165400,180600" +st "clock" +blo "162000,180400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*119 (CptPort +uid 1911,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1912,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,181625,161000,182375" +) +tg (CPTG +uid 1913,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1914,0 +va (VaSet +) +xt "162000,181400,165300,182600" +st "reset" +blo "162000,182400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +) +) +) +*120 (CptPort +uid 1915,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1916,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,175625,161000,176375" +) +tg (CPTG +uid 1917,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1918,0 +va (VaSet +) +xt "162000,175400,163900,176600" +st "en" +blo "162000,176400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 4 +) +) +) +] +shape (Rectangle +uid 1920,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "161000,172000,177000,184000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1921,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*121 (Text +uid 1922,0 +va (VaSet +) +xt "161600,184800,165900,186000" +st "Curves" +blo "161600,185800" +tm "BdLibraryNameMgr" +) +*122 (Text +uid 1923,0 +va (VaSet +) +xt "161600,185800,172400,187000" +st "interpolatorTrigger" +blo "161600,186800" +tm "CptNameMgr" +) +*123 (Text +uid 1924,0 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"SIGNAL addrX : unsigned(patternAddressBitNb-1 DOWNTO 0)" +) +) +*126 (Net +uid 2850,0 +decl (Decl +n "cntIncrX" +t "std_ulogic" +o 31 +suid 45,0 +) +declText (MLText +uid 2851,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,37300,230200,38300" +st "SIGNAL cntIncrX : std_ulogic" +) +) +*127 (Net +uid 2852,0 +decl (Decl +n "memWrX" +t "std_ulogic" +o 46 +suid 46,0 +) +declText (MLText +uid 2853,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,50800,231300,51800" +st "SIGNAL memWrX : std_ulogic" +) +) +*128 (Net +uid 2854,0 +decl (Decl +n "memEnX" +t "std_ulogic" +o 43 +suid 47,0 +) +declText (MLText +uid 2855,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,48100,231200,49100" +st "SIGNAL memEnX : std_ulogic" +) +) +*129 (HdlText +uid 3135,0 +optionalChildren [ +*130 (EmbeddedText +uid 3140,0 +commentText (CommentText +uid 3141,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3142,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,152000,146000,156000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3143,0 +va (VaSet +) +xt "132200,152200,144900,155800" +st " +samplesX <= cosine when selSinCos = '1' + else signed(memX); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3136,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,150000,147000,158000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3137,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*131 (Text +uid 3138,0 +va (VaSet +) +xt "131400,158000,134000,159200" +st "eb2" +blo "131400,159000" +tm "HdlTextNameMgr" +) +*132 (Text +uid 3139,0 +va (VaSet +) +xt "131400,159000,132800,160200" +st "2" +blo "131400,160000" +tm "HdlTextNumberMgr" +) +] +) +) +*133 (Net +uid 3152,0 +decl (Decl +n "memX" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 49 +suid 48,0 +) +declText (MLText +uid 3153,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,53500,244700,54500" +st "SIGNAL memX : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*134 (SaComponent +uid 3378,0 +optionalChildren [ +*135 (CptPort +uid 3354,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3355,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,159625,75000,160375" +) +tg (CPTG +uid 3356,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3357,0 +va (VaSet +) +xt "76000,159400,77900,160600" +st "en" +blo "76000,160400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 1 +) +) +) +*136 (CptPort +uid 3358,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3359,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,163625,75000,164375" +) +tg (CPTG +uid 3360,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3361,0 +va (VaSet +) +xt "76000,163400,79400,164600" +st "clock" +blo "76000,164400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*137 (CptPort +uid 3362,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3363,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,165625,75000,166375" +) +tg (CPTG +uid 3364,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3365,0 +va (VaSet +) +xt "76000,165400,79300,166600" +st "reset" +blo "76000,166400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +) +) +) +*138 (CptPort +uid 3366,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3367,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,157625,75000,158375" +) +tg (CPTG +uid 3368,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3369,0 +va (VaSet +) +xt "76000,157400,82500,158600" +st "updateMem" +blo "76000,158400" +) +) +thePort (LogicalPort +decl (Decl +n "updateMem" +t "std_ulogic" +o 4 +) +) +) +*139 (CptPort +uid 3370,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3371,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91000,155625,91750,156375" +) +tg (CPTG +uid 3372,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3373,0 +va (VaSet +) +xt "87100,155400,90000,156600" +st "addr" +ju 2 +blo "90000,156400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 5 +) +) +) +*140 (CptPort +uid 3374,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3375,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,155625,75000,156375" +) +tg (CPTG +uid 3376,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3377,0 +va (VaSet +) +xt "76000,155400,83100,156600" +st "patternSize" +blo "76000,156400" +) +) +thePort (LogicalPort +decl (Decl +n "patternSize" +t "unsigned" +b "(patternSizeBitNb-1 DOWNTO 0)" +o 6 +) +) +) +] +shape (Rectangle +uid 3379,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "75000,152000,91000,168000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3380,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*141 (Text +uid 3381,0 +va (VaSet +) +xt "75600,167800,79900,169000" +st "Curves" +blo "75600,168800" +tm "BdLibraryNameMgr" +) +*142 (Text +uid 3382,0 +va (VaSet +) +xt "75600,168800,91000,170000" +st "blockRAMAddressCounter" +blo "75600,169800" +tm "CptNameMgr" +) +*143 (Text +uid 3383,0 +va (VaSet +) +xt "75600,169800,78200,171000" +st "I18" +blo "75600,170800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3384,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3385,0 +text (MLText +uid 3386,0 +va (VaSet +font "Verdana,8,0" +) +xt "75000,171600,98800,173600" +st "addressBitNb = patternAddressBitNb ( positive ) +patternSizeBitNb = dataBitNb/2 ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +(GiElement +name "patternSizeBitNb" +type "positive" +value "dataBitNb/2" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*144 (SaComponent +uid 3623,0 +optionalChildren [ +*145 (CptPort +uid 3603,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3604,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "123000,65625,123750,66375" +) +tg (CPTG +uid 3605,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3606,0 +va (VaSet +) +xt "116100,65400,122000,66600" +st "enableOut" +ju 2 +blo "122000,66400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "enableOut" +t "std_ulogic" +o 1 +) +) +) +*146 (CptPort +uid 3607,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3608,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "106250,71625,107000,72375" +) +tg (CPTG +uid 3609,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3610,0 +va (VaSet +) +xt "108000,71400,111400,72600" +st "clock" +blo "108000,72400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*147 (CptPort +uid 3611,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3612,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "106250,73625,107000,74375" +) +tg (CPTG +uid 3613,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3614,0 +va (VaSet +) +xt "108000,73400,111300,74600" +st "reset" +blo "108000,74400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +) +) +) +*148 (CptPort +uid 3615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "106250,67625,107000,68375" +) +tg (CPTG +uid 3617,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3618,0 +va (VaSet +) +xt "108000,67400,116000,68600" +st "updatePeriod" +blo "108000,68400" +) +) +thePort (LogicalPort +decl (Decl +n "updatePeriod" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +) +) +) +*149 (CptPort +uid 3619,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3620,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "106250,65625,107000,66375" +) +tg (CPTG +uid 3621,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3622,0 +va (VaSet +) +xt "108000,65400,113100,66600" +st "enableIn" +blo "108000,66400" +) +) +thePort (LogicalPort +decl (Decl +n "enableIn" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 3624,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "107000,62000,123000,76000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3625,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*150 (Text +uid 3626,0 +va (VaSet +) +xt "107600,75800,111900,77000" +st "Curves" +blo "107600,76800" +tm "BdLibraryNameMgr" +) +*151 (Text +uid 3627,0 +va (VaSet +) +xt "107600,76800,120900,78000" +st "periphSpeedController" +blo "107600,77800" +tm "CptNameMgr" +) +*152 (Text +uid 3628,0 +va (VaSet +) +xt "107600,77800,110200,79000" +st "I15" +blo "107600,78800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3629,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3630,0 +text (MLText +uid 3631,0 +va (VaSet +font "Verdana,8,0" +) +xt "107000,79600,123600,80600" +st "dataBitNb = dataBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*153 (SaComponent +uid 3681,0 +optionalChildren [ +*154 (CptPort +uid 3690,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3691,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,109625,75000,110375" +) +tg (CPTG +uid 3692,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3693,0 +va (VaSet +) +xt "76000,109400,77900,110600" +st "en" +blo "76000,110400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 1 +) +) +) +*155 (CptPort +uid 3694,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3695,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,113625,75000,114375" +) +tg (CPTG +uid 3696,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3697,0 +va (VaSet +) +xt "76000,113400,79400,114600" +st "clock" +blo "76000,114400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*156 (CptPort +uid 3698,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3699,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,115625,75000,116375" +) +tg (CPTG +uid 3700,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3701,0 +va (VaSet +) +xt "76000,115400,79300,116600" +st "reset" +blo "76000,116400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +) +) +) +*157 (CptPort +uid 3702,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3703,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,107625,75000,108375" +) +tg (CPTG +uid 3704,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3705,0 +va (VaSet +) +xt "76000,107400,82500,108600" +st "updateMem" +blo "76000,108400" +) +) +thePort (LogicalPort +decl (Decl +n "updateMem" +t "std_ulogic" +o 4 +) +) +) +*158 (CptPort +uid 3706,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3707,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91000,105625,91750,106375" +) +tg (CPTG +uid 3708,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3709,0 +va (VaSet +) +xt "87100,105400,90000,106600" +st "addr" +ju 2 +blo "90000,106400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 5 +) +) +) +*159 (CptPort +uid 3710,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3711,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,105625,75000,106375" +) +tg (CPTG +uid 3712,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3713,0 +va (VaSet +) +xt "76000,105400,83100,106600" +st "patternSize" +blo "76000,106400" +) +) +thePort (LogicalPort +decl (Decl +n "patternSize" +t "unsigned" +b "(patternSizeBitNb-1 DOWNTO 0)" +o 6 +) +) +) +] +shape (Rectangle +uid 3682,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "75000,102000,91000,118000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3683,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*160 (Text +uid 3684,0 +va (VaSet +) +xt "75600,117800,79900,119000" +st "Curves" +blo "75600,118800" +tm "BdLibraryNameMgr" +) +*161 (Text +uid 3685,0 +va (VaSet +) +xt "75600,118800,91000,120000" +st "blockRAMAddressCounter" +blo "75600,119800" +tm "CptNameMgr" +) +*162 (Text +uid 3686,0 +va (VaSet +) +xt "75600,119800,78200,121000" +st "I20" +blo "75600,120800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3687,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3688,0 +text (MLText +uid 3689,0 +va (VaSet +font "Verdana,8,0" +) +xt "75000,121600,98800,123600" +st "addressBitNb = patternAddressBitNb ( positive ) +patternSizeBitNb = dataBitNb/2 ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +(GiElement +name "patternSizeBitNb" +type "positive" +value "dataBitNb/2" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*163 (Net +uid 3827,0 +decl (Decl +n "cntIncrY" +t "std_ulogic" +o 32 +suid 49,0 +) +declText (MLText +uid 3828,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,38200,230200,39200" +st "SIGNAL cntIncrY : std_ulogic" +) +) +*164 (Net +uid 3890,0 +decl (Decl +n "addrY" +t "unsigned" +b "(patternAddressBitNb-1 DOWNTO 0)" +o 25 +suid 50,0 +) +declText (MLText +uid 3891,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,31900,244900,32900" +st "SIGNAL addrY : unsigned(patternAddressBitNb-1 DOWNTO 0)" +) +) +*165 (Net +uid 3892,0 +decl (Decl +n "memWrY" +t "std_ulogic" +o 47 +suid 51,0 +) +declText (MLText +uid 3893,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,51700,231300,52700" +st "SIGNAL memWrY : std_ulogic" +) +) +*166 (Net +uid 3894,0 +decl (Decl +n "memEnY" +t "std_ulogic" +o 44 +suid 52,0 +) +declText (MLText +uid 3895,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,49000,231200,50000" +st "SIGNAL memEnY : std_ulogic" +) +) +*167 (HdlText +uid 3896,0 +optionalChildren [ +*168 (EmbeddedText +uid 3901,0 +commentText (CommentText +uid 3902,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3903,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,115000,146000,119000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3904,0 +va (VaSet +) +xt "132200,115200,144900,118800" +st " +samplesY <= sine when selSinCos = '1' + else signed(memY); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3897,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,113000,147000,121000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3898,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*169 (Text +uid 3899,0 +va (VaSet +) +xt "131400,121000,134000,122200" +st "eb1" +blo "131400,122000" +tm "HdlTextNameMgr" +) +*170 (Text +uid 3900,0 +va (VaSet +) +xt "131400,122000,132800,123200" +st "1" +blo "131400,123000" +tm "HdlTextNumberMgr" +) +] +) +) +*171 (Net +uid 3913,0 +decl (Decl +n "memY" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 50 +suid 53,0 +) +declText (MLText +uid 3914,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,54400,244700,55400" +st "SIGNAL memY : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*172 (PortIoOut +uid 4041,0 +shape (CompositeShape +uid 4042,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4043,0 +sl 0 +ro 270 +xt "289500,5625,291000,6375" +) +(Line +uid 4044,0 +sl 0 +ro 270 +xt "289000,6000,289500,6000" +pts [ +"289000,6000" +"289500,6000" +] +) +] +) +tg (WTG +uid 4045,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4046,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "292000,5300,305600,6700" +st "testOut : (1 TO 16)" +blo "292000,6500" +tm "WireNameMgr" +) +) +) +*173 (Net +uid 4053,0 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO 16)" +o 12 +suid 54,0 +) +declText (MLText +uid 4054,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,12100,234500,13100" +st "testOut : std_ulogic_vector(1 TO 16)" +) +) +*174 (HdlText +uid 4055,0 +optionalChildren [ +*175 (EmbeddedText +uid 4060,0 +commentText (CommentText +uid 4061,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4062,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "266000,5000,280000,27000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4063,0 +va (VaSet +) +xt "266200,5200,278400,26800" +st " +testout(1) <= run; +testout(2) <= updatePattern; +testout(3) <= interpolationEnable; +testout(4) <= newPolynom; +testout(5) <= selSinCos; +testout(6) <= cs; +testout(7) <= rd; +testout(8) <= wrH; +testout(9) <= wrL; +testout(10) <= addrReg(1); +testout(11) <= dataInReg(0); +--testout(10) <= selControl; +--testout(11) <= selSize; +testout(12) <= selSpeed; +testout(13) <= selX; +testout(14) <= selY; +testout(15) <= cntIncrX; +testout(16) <= cntIncrY; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 22000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4056,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "265000,4000,281000,28000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4057,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*176 (Text +uid 4058,0 +va (VaSet +) +xt "265400,28000,268000,29200" +st "eb3" +blo "265400,29000" +tm "HdlTextNameMgr" +) +*177 (Text +uid 4059,0 +va (VaSet +) +xt "265400,29000,266800,30200" +st "3" +blo "265400,30000" +tm "HdlTextNumberMgr" +) +] +) +) +*178 (SaComponent +uid 4245,0 +optionalChildren [ +*179 (CptPort +uid 4225,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4226,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,57625,43750,58375" +) +tg (CPTG +uid 4227,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4228,0 +va (VaSet +) +xt "35400,57400,42000,58600" +st "writePulse" +ju 2 +blo "42000,58400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writePulse" +t "std_ulogic" +o 1 +) +) +) +*180 (CptPort +uid 4229,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4230,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,57625,27000,58375" +) +tg (CPTG +uid 4231,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4232,0 +va (VaSet +) +xt "28000,57400,31100,58600" +st "write" +blo "28000,58400" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 2 +) +) +) +*181 (CptPort +uid 4233,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4234,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,59625,27000,60375" +) +tg (CPTG +uid 4235,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4236,0 +va (VaSet +) +xt "28000,59400,34700,60600" +st "chipSelect" +blo "28000,60400" +) +) +thePort (LogicalPort +decl (Decl +n "chipSelect" +t "std_ulogic" +o 3 +) +) +) +*182 (CptPort +uid 4237,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4238,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,63625,27000,64375" +) +tg (CPTG +uid 4239,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4240,0 +va (VaSet +) +xt "28000,63400,31400,64600" +st "clock" +blo "28000,64400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 4 +) +) +) +*183 (CptPort +uid 4241,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4242,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,65625,27000,66375" +) +tg (CPTG +uid 4243,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4244,0 +va (VaSet +) +xt "28000,65400,31300,66600" +st "reset" +blo "28000,66400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 4246,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "27000,54000,43000,68000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4247,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*184 (Text +uid 4248,0 +va (VaSet +) +xt "27600,67800,31900,69000" +st "Curves" +blo "27600,68800" +tm "BdLibraryNameMgr" +) +*185 (Text +uid 4249,0 +va (VaSet +) +xt "27600,68800,37500,70000" +st "periphWritePulse" +blo "27600,69800" +tm "CptNameMgr" +) +*186 (Text +uid 4250,0 +va (VaSet +) +xt "27600,69800,30200,71000" +st "I22" +blo "27600,70800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4251,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4252,0 +text (MLText +uid 4253,0 +va (VaSet +font "Verdana,8,0" +) +xt "-7000,45000,-7000,45000" +) +header "" +) +elements [ +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*187 (Net +uid 4290,0 +decl (Decl +n "wrHPulse" +t "std_ulogic" +o 85 +suid 55,0 +) +declText (MLText +uid 4291,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,85900,230700,86900" +st "SIGNAL wrHPulse : std_ulogic" +) +) +*188 (SaComponent +uid 4300,0 +optionalChildren [ +*189 (CptPort +uid 4309,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4310,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,79625,43750,80375" +) +tg (CPTG +uid 4311,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4312,0 +va (VaSet +) +xt "35400,79400,42000,80600" +st "writePulse" +ju 2 +blo "42000,80400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writePulse" +t "std_ulogic" +o 1 +) +) +) +*190 (CptPort +uid 4313,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4314,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,79625,27000,80375" +) +tg (CPTG +uid 4315,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4316,0 +va (VaSet +) +xt "28000,79400,31100,80600" +st "write" +blo "28000,80400" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 2 +) +) +) +*191 (CptPort +uid 4317,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4318,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,81625,27000,82375" +) +tg (CPTG +uid 4319,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4320,0 +va (VaSet +) +xt "28000,81400,34700,82600" +st "chipSelect" +blo "28000,82400" +) +) +thePort (LogicalPort +decl (Decl +n "chipSelect" +t "std_ulogic" +o 3 +) +) +) +*192 (CptPort +uid 4321,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4322,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,85625,27000,86375" +) +tg (CPTG +uid 4323,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4324,0 +va (VaSet +) +xt "28000,85400,31400,86600" +st "clock" +blo "28000,86400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 4 +) +) +) +*193 (CptPort +uid 4325,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4326,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,87625,27000,88375" +) +tg (CPTG +uid 4327,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4328,0 +va (VaSet +) +xt "28000,87400,31300,88600" +st "reset" +blo "28000,88400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 4301,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "27000,76000,43000,90000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4302,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*194 (Text +uid 4303,0 +va (VaSet +) +xt "27600,89800,31900,91000" +st "Curves" +blo "27600,90800" +tm "BdLibraryNameMgr" +) +*195 (Text +uid 4304,0 +va (VaSet +) +xt "27600,90800,37500,92000" +st "periphWritePulse" +blo "27600,91800" +tm "CptNameMgr" +) +*196 (Text +uid 4305,0 +va (VaSet +) +xt "27600,91800,30200,93000" +st "I23" +blo "27600,92800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4306,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4307,0 +text (MLText +uid 4308,0 +va (VaSet +font "Verdana,8,0" +) +xt "-7000,67000,-7000,67000" +) +header "" +) +elements [ +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*197 (Net +uid 4347,0 +decl (Decl +n "wrLPulse" +t "std_ulogic" +o 86 +suid 56,0 +) +declText (MLText +uid 4348,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,86800,230500,87800" +st "SIGNAL wrLPulse : std_ulogic" +) +) +*198 (HdlText +uid 4719,0 +optionalChildren [ +*199 (EmbeddedText +uid 4724,0 +commentText (CommentText +uid 4725,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4726,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "150000,75000,164000,77000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4727,0 +va (VaSet +) +xt "150200,75200,164000,76400" +st " +step <= to_unsigned(1, step'length); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4720,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "149000,74000,165000,78000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4721,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*200 (Text +uid 4722,0 +va (VaSet +) +xt "149400,78000,152000,79200" +st "eb4" +blo "149400,79000" +tm "HdlTextNameMgr" +) +*201 (Text +uid 4723,0 +va (VaSet +) +xt "149400,79000,150800,80200" +st "4" +blo "149400,80000" +tm "HdlTextNumberMgr" +) +] +) +) +*202 (Net +uid 4800,0 +decl (Decl +n "phase" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 54 +suid 57,0 +) +declText (MLText +uid 4801,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,58000,241400,59000" +st "SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*203 (Net +uid 4802,0 +decl (Decl +n "step" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 78 +suid 58,0 +) +declText (MLText +uid 4803,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,79600,241000,80600" +st "SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*204 (Net +uid 4858,0 +decl (Decl +n "sine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 77 +suid 59,0 +) +declText (MLText +uid 4859,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,78700,239800,79700" +st "SIGNAL sine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*205 (SaComponent +uid 4923,0 +optionalChildren [ +*206 (CptPort +uid 4903,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4904,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,89625,161000,90375" +) +tg (CPTG +uid 4905,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4906,0 +va (VaSet +) +xt "162000,89400,165400,90600" +st "clock" +blo "162000,90400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*207 (CptPort +uid 4907,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4908,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "177000,83625,177750,84375" +) +tg (CPTG +uid 4909,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4910,0 +va (VaSet +) +xt "170800,83400,176000,84600" +st "sawtooth" +ju 2 +blo "176000,84400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sawtooth" +t "unsigned" +b "(bitNb-1 DOWNTO 0)" +o 1 +) +) +) +*208 (CptPort +uid 4911,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4912,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,91625,161000,92375" +) +tg (CPTG +uid 4913,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4914,0 +va (VaSet +) +xt "162000,91400,165300,92600" +st "reset" +blo "162000,92400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +) +) +) +*209 (CptPort +uid 4915,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4916,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,83625,161000,84375" +) +tg (CPTG +uid 4917,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4918,0 +va (VaSet +) +xt "162000,83400,164900,84600" +st "step" +blo "162000,84400" +) +) +thePort (LogicalPort +decl (Decl +n "step" +t "unsigned" +b "(bitNb-1 DOWNTO 0)" +o 4 +) +) +) +*210 (CptPort +uid 4919,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4920,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,85625,161000,86375" +) +tg (CPTG +uid 4921,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4922,0 +va (VaSet +) +xt "162000,85400,163900,86600" +st "en" +blo "162000,86400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 4924,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "161000,80000,177000,94000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4925,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*211 (Text +uid 4926,0 +va (VaSet +) +xt "161600,93800,165900,95000" +st "Curves" +blo "161600,94800" +tm "BdLibraryNameMgr" +) +*212 (Text +uid 4927,0 +va (VaSet +) +xt "161600,94800,169500,96000" +st "sawtoothGen" +blo "161600,95800" +tm "CptNameMgr" +) +*213 (Text +uid 4928,0 +va (VaSet +) +xt "161600,95800,164200,97000" +st "I24" +blo "161600,96800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4929,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4930,0 +text (MLText +uid 4931,0 +va (VaSet +font "Verdana,8,0" +) +xt "161000,96600,176400,97600" +st "bitNb = phaseBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "bitNb" +type "positive" +value "phaseBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*214 (PortIoIn +uid 5080,0 +shape (CompositeShape +uid 5081,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5082,0 +sl 0 +ro 270 +xt "151000,69625,152500,70375" +) +(Line +uid 5083,0 +sl 0 +ro 270 +xt "152500,70000,153000,70000" +pts [ +"152500,70000" +"153000,70000" +] +) +] +) +tg (WTG +uid 5084,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5085,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "143100,69300,150000,70700" +st "selSinCos" +ju 2 +blo "150000,70500" +tm "WireNameMgr" +) +) +) +*215 (HdlText +uid 5244,0 +optionalChildren [ +*216 (EmbeddedText +uid 5249,0 +commentText (CommentText +uid 5250,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 5251,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "162000,65000,176000,71000" +) +oxt "0,0,18000,5000" +text (MLText +uid 5252,0 +va (VaSet +) +xt "162200,65200,176100,71200" +st " +interpolationEnable <= '1' when selSinCos = '1' + else interpolationEn; +--interpolateLinear <= '1' when selSinCos = '1' +-- else interpolateLin; +interpolateLinear <= interpolateLin; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 5245,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "161000,64000,177000,72000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 5246,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*217 (Text +uid 5247,0 +va (VaSet +) +xt "161400,72000,164000,73200" +st "eb5" +blo "161400,73000" +tm "HdlTextNameMgr" +) +*218 (Text +uid 5248,0 +va (VaSet +) +xt "161400,73000,162800,74200" +st "5" +blo "161400,74000" +tm "HdlTextNumberMgr" +) +] +) +) +*219 (Net +uid 5261,0 +decl (Decl +n "interpolationEn" +t "std_ulogic" +o 40 +suid 60,0 +) +declText (MLText +uid 5262,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,45400,230900,46400" +st "SIGNAL interpolationEn : std_ulogic" +) +) +*220 (Net +uid 5936,0 +decl (Decl +n "cosine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 34 +suid 61,0 +) +declText (MLText +uid 5937,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,40000,240100,41000" +st "SIGNAL cosine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*221 (SaComponent +uid 5956,0 +optionalChildren [ +*222 (CptPort +uid 5944,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5945,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "201000,83625,201750,84375" +) +tg (CPTG +uid 5946,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5947,0 +va (VaSet +) +xt "197200,83400,200000,84600" +st "sine" +ju 2 +blo "200000,84400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sine" +t "signed" +b "(outputBitNb-1 DOWNTO 0)" +o 1 +) +) +) +*223 (CptPort +uid 5948,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5949,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "184250,83625,185000,84375" +) +tg (CPTG +uid 5950,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5951,0 +va (VaSet +) +xt "186000,83400,189700,84600" +st "phase" +blo "186000,84400" +) +) +thePort (LogicalPort +decl (Decl +n "phase" +t "unsigned" +b "(inputBitNb-1 DOWNTO 0)" +o 2 +) +) +) +*224 (CptPort +uid 5952,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5953,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "201000,85625,201750,86375" +) +tg (CPTG +uid 5954,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5955,0 +va (VaSet +) +xt "196000,85400,200000,86600" +st "cosine" +ju 2 +blo "200000,86400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "cosine" +t "signed" +b "(outputBitNb-1 DOWNTO 0)" +o 3 +) +) +) +] +shape (Rectangle +uid 5957,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "185000,80000,201000,90000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 5958,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*225 (Text +uid 5959,0 +va (VaSet +) +xt "185600,89800,189900,91000" +st "Curves" +blo "185600,90800" +tm "BdLibraryNameMgr" +) +*226 (Text +uid 5960,0 +va (VaSet +) +xt "185600,90800,193300,92000" +st "sinCosTable" +blo "185600,91800" +tm "CptNameMgr" +) +*227 (Text +uid 5961,0 +va (VaSet +) +xt "185600,91800,188200,93000" +st "I25" +blo "185600,92800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5962,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5963,0 +text (MLText +uid 5964,0 +va (VaSet +font "Verdana,8,0" +) +xt "185000,93000,208700,96000" +st "inputBitNb = phaseBitNb ( positive ) +outputBitNb = signalBitNb ( positive ) +tableAddressBitNb = tableAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "inputBitNb" +type "positive" +value "phaseBitNb" +) +(GiElement +name "outputBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "tableAddressBitNb" +type "positive" +value "tableAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*228 (HdlText +uid 6125,0 +optionalChildren [ +*229 (EmbeddedText +uid 6130,0 +commentText (CommentText +uid 6131,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6132,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "28000,151000,42000,165000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6133,0 +va (VaSet +) +xt "28200,151200,42200,164400" +st " +writeX: process(selX, memX) +begin + if selX = '1' then + dataOut <= std_logic_vector(memX); + else + dataOut <= (others => 'Z'); + end if; +end process writeX; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 14000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 6126,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "27000,150000,43000,166000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6127,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*230 (Text +uid 6128,0 +va (VaSet +) +xt "27400,166000,30000,167200" +st "eb6" +blo "27400,167000" +tm "HdlTextNameMgr" +) +*231 (Text +uid 6129,0 +va (VaSet +) +xt "27400,167000,28800,168200" +st "6" +blo "27400,168000" +tm "HdlTextNumberMgr" +) +] +) +) +*232 (Net +uid 6503,0 +decl (Decl +n "selSinCos" +t "std_ulogic" +o 13 +suid 62,0 +) +declText (MLText +uid 6504,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,13000,227300,14000" +st "selSinCos : std_ulogic" +) +) +*233 (HdlText +uid 6825,0 +optionalChildren [ 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(VaSet +) +xt "27400,187000,28800,188200" +st "7" +blo "27400,188000" +tm "HdlTextNumberMgr" +) +] +) +) +*237 (SaComponent +uid 7019,0 +optionalChildren [ +*238 (CptPort +uid 6994,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6995,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,15625,27000,16375" +) +tg (CPTG +uid 6996,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6997,0 +va (VaSet +font "Verdana,12,0" +) +xt "28000,15300,31800,16700" +st "clock" +blo "28000,16500" +) +s (Text +uid 6998,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "28000,16700,28000,16700" +blo "9000,34900" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*239 (CptPort +uid 6999,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7000,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,9625,27000,10375" +) +tg (CPTG +uid 7001,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7002,0 +va (VaSet +font "Verdana,12,0" +) +xt "28000,9300,33000,10700" +st "dataIn" +blo "28000,10500" +) +s (Text +uid 7003,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "28000,10700,28000,10700" +blo "-37800,34100" +) +) +thePort (LogicalPort +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(registerNbBits-1 DOWNTO 0)" +o 1 +) +) +) +*240 (CptPort +uid 7004,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7005,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,9625,43750,10375" +) +tg (CPTG +uid 7006,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 7007,0 +va (VaSet +font "Verdana,12,0" +) +xt "36000,9300,42000,10700" +st "dataOut" +ju 2 +blo "42000,10500" +) +s (Text +uid 7008,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "42000,10700,42000,10700" +ju 2 +blo "-23600,-18900" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dataOut" +t "std_ulogic_vector" +b "(registerNbBits-1 DOWNTO 0)" +o 3 +) +) +) +*241 (CptPort +uid 7009,0 +ps "OnEdgeStrategy" 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"1 ns" +) +(GiElement +name "registerNbBits" +type "positive" +value "dataBitNb" +) +] +) +portVis (PortSigDisplay +disp 1 +sTC 0 +sT 1 +sIVOD 1 +) +archFileType "UNKNOWN" +) +*246 (Net +uid 7053,0 +decl (Decl +n "dataInReg" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 37 +suid 63,0 +) +declText (MLText +uid 7054,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,42700,244800,43700" +st "SIGNAL dataInReg : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*247 (Net +uid 7073,0 +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 6 +suid 64,0 +) +declText (MLText +uid 7074,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,6700,240900,7700" +st "dataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*248 (SaComponent +uid 7075,0 +optionalChildren [ +*249 (CptPort +uid 7084,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7085,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "6250,37625,7000,38375" +) +tg (CPTG +uid 7086,0 +ps "CptPortTextPlaceStrategy" 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"8000,36700,8000,36700" +blo "-11000,56900" +) +) +thePort (LogicalPort +decl (Decl +n "enable" +t "std_ulogic" +o 4 +) +) +) +*253 (CptPort +uid 7104,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7105,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "6250,39625,7000,40375" +) +tg (CPTG +uid 7106,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7107,0 +va (VaSet +font "Verdana,12,0" +) +xt "8000,39300,12100,40700" +st "reset" +blo "8000,40500" +) +s (Text +uid 7108,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "8000,40700,8000,40700" +blo "-11000,56900" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 7076,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "7000,28000,23000,42000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 7077,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*254 (Text +uid 7078,0 +va (VaSet +) +xt "6910,42700,13510,43900" +st "sequential" +blo "6910,43700" +tm "BdLibraryNameMgr" +) +*255 (Text +uid 7079,0 +va (VaSet +) +xt "6910,43700,16910,44900" +st "registerUnsigned" +blo "6910,44700" +tm "CptNameMgr" +) +*256 (Text +uid 7080,0 +va (VaSet +) +xt "6910,44700,9510,45900" +st "I27" +blo "6910,45700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 7081,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 7082,0 +text (MLText +uid 7083,0 +va (VaSet +) +xt "7000,45600,32100,48000" +st "delay = 1 ns ( time ) +registerNbBits = addressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "delay" +type "time" +value "1 ns" +) +(GiElement +name "registerNbBits" +type "positive" +value "addressBitNb" +) +] +) +portVis (PortSigDisplay +disp 1 +sTC 0 +sT 1 +sIVOD 1 +) +archFileType "UNKNOWN" +) +*257 (Net +uid 7115,0 +decl (Decl +n "addrReg" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 23 +suid 65,0 +) +declText (MLText +uid 7116,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,30100,242500,31100" +st "SIGNAL addrReg : unsigned(addressBitNb-1 DOWNTO 0)" +) +) +*258 (HdlText +uid 7149,0 +optionalChildren [ +*259 (EmbeddedText +uid 7154,0 +commentText (CommentText +uid 7155,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 7156,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "12000,13000,18000,15000" +) +oxt "0,0,18000,5000" +text (MLText +uid 7157,0 +va (VaSet +) +xt "12200,13200,17700,14400" +st " +logic1 <= '1'; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 6000 +) +) +) +] +shape (Rectangle +uid 7150,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "11000,12000,19000,16000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 7151,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*260 (Text +uid 7152,0 +va (VaSet +) +xt "11400,16000,14000,17200" +st "eb8" +blo "11400,17000" +tm "HdlTextNameMgr" +) +*261 (Text +uid 7153,0 +va (VaSet +) +xt "11400,17000,12800,18200" +st "8" +blo "11400,18000" +tm "HdlTextNumberMgr" +) +] +) +) +*262 (Net +uid 7166,0 +decl (Decl +n "logic1" +t "std_ulogic" +o 42 +suid 66,0 +) +declText (MLText +uid 7167,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,47200,229900,48200" +st "SIGNAL logic1 : std_ulogic" +) +) +*263 (SaComponent +uid 7695,0 +optionalChildren [ +*264 (CptPort +uid 7704,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7705,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,107625,43750,108375" +) +tg (CPTG +uid 7706,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 7707,0 +va (VaSet +) +xt "35400,107400,42000,108600" +st "writePulse" +ju 2 +blo "42000,108400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writePulse" +t "std_ulogic" +o 1 +) +) +) +*265 (CptPort +uid 7708,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7709,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,107625,27000,108375" +) +tg (CPTG +uid 7710,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7711,0 +va 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std_ulogic" +) +) +*528 (PortIoOut +uid 12120,0 +shape (CompositeShape +uid 12121,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 12122,0 +sl 0 +ro 270 +xt "289500,60625,291000,61375" +) +(Line +uid 12123,0 +sl 0 +ro 270 +xt "289000,61000,289500,61000" +pts [ +"289000,61000" +"289500,61000" +] +) +] +) +tg (WTG +uid 12124,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12125,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "292000,60300,296500,61700" +st "SDI_Y" +blo "292000,61500" +tm "WireNameMgr" +) +) +) +*529 (Net +uid 12132,0 +decl (Decl +n "SDI_Y" +t "std_ulogic" +o 20 +suid 86,0 +) +declText (MLText +uid 12133,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,19300,227100,20300" +st "SDI_Y : std_ulogic" +) +) +*530 (Wire +uid 59,0 +shape (OrthoPolyLine +uid 60,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "3000,32000,6250,32000" +pts [ +"3000,32000" +"6250,32000" +] +) +start &12 +end &250 +es 0 +sat 32 +eat 32 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"outY" +blo "286000,116800" +tm "WireNameMgr" +) +) +on &21 +) +*535 (Wire +uid 143,0 +shape (OrthoPolyLine +uid 144,0 +va (VaSet +vasetType 3 +) +xt "19000,96000,27000,96000" +pts [ +"19000,96000" +"27000,96000" +] +) +start &22 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 147,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 148,0 +va (VaSet +font "Verdana,12,0" +) +xt "19000,94600,21100,96000" +st "rd" +blo "19000,95800" +tm "WireNameMgr" +) +) +on &23 +) +*536 (Wire +uid 157,0 +shape (OrthoPolyLine +uid 158,0 +va (VaSet +vasetType 3 +) +xt "71000,26000,74250,26000" +pts [ +"71000,26000" +"74250,26000" +] +) +start &24 +end &289 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 161,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 162,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,24600,75100,26000" +st "reset" +blo "71000,25800" +tm "WireNameMgr" +) +) +on &25 +) +*537 (Wire +uid 171,0 +shape (OrthoPolyLine +uid 172,0 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"152600,155600,153400,156400" +radius 400 +) +) +*541 (BdJunction +uid 11549,0 +ps "OnConnectorStrategy" +shape (Circle +uid 11550,0 +va (VaSet +vasetType 1 +) +xt "152600,168600,153400,169400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 355,0 +va (VaSet +vasetType 3 +) +xt "153000,156000,181000,176000" +pts [ +"181000,176000" +"181000,169000" +"153000,169000" +"153000,156000" +"160250,156000" +] +) +start *542 (BdJunction +uid 564,0 +ps "OnConnectorStrategy" +shape (Circle +uid 565,0 +va (VaSet +vasetType 1 +) +xt "180600,175600,181400,176400" +radius 400 +) +) +end &358 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 356,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 357,0 +va (VaSet +font "Verdana,12,0" +) +xt "152000,154600,161600,156000" +st "newPolynom" +blo "152000,155800" +tm "WireNameMgr" +) +) +on &30 +) +*543 (Wire +uid 360,0 +optionalChildren [ +&542 +*544 (BdJunction +uid 9244,0 +ps "OnConnectorStrategy" +shape (Circle +uid 9245,0 +va (VaSet +vasetType 1 +) +xt "204600,161600,205400,162400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 361,0 +va (VaSet +vasetType 3 +) +xt "177750,162000,216250,176000" +pts [ +"177750,176000" +"205000,176000" +"205000,162000" +"216250,162000" +] +) +start &117 +end &383 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 362,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 363,0 +va (VaSet +font "Verdana,12,0" +) +xt "201000,174600,210600,176000" +st "newPolynom" +blo "201000,175800" +tm "WireNameMgr" +) +) +on &30 +) +*545 (Wire +uid 364,0 +shape (OrthoPolyLine +uid 365,0 +va (VaSet +vasetType 3 +) +xt "157000,182000,160250,182000" +pts [ +"157000,182000" +"160250,182000" +] +) +end &119 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 368,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 369,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,180600,160100,182000" +st "reset" +blo "156000,181800" +tm "WireNameMgr" +) +) +on &25 +) +*546 (Wire +uid 370,0 +shape (OrthoPolyLine +uid 371,0 +va (VaSet +vasetType 3 +) +xt "157000,180000,160250,180000" +pts [ +"157000,180000" +"160250,180000" +] +) +end &118 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 374,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 375,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,178600,159800,180000" +st "clock" +blo "156000,179800" +tm "WireNameMgr" +) +) +on &15 +) +*547 (Wire +uid 376,0 +shape (OrthoPolyLine +uid 377,0 +va (VaSet +vasetType 3 +) +xt "157000,162000,160250,162000" +pts [ +"157000,162000" +"160250,162000" +] +) +end &357 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 380,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 381,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,160600,160100,162000" +st "reset" +blo "156000,161800" +tm "WireNameMgr" +) +) +on &25 +) +*548 (Wire +uid 382,0 +shape (OrthoPolyLine +uid 383,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "147000,154000,160250,154000" +pts [ +"147000,154000" +"160250,154000" +] +) +start &129 +end &359 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 384,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 385,0 +va (VaSet +font "Verdana,12,0" +) +xt "149000,152600,155800,154000" +st "samplesX" +blo "149000,153800" +tm "WireNameMgr" +) +) +on &47 +) +*549 (Wire +uid 386,0 +shape (OrthoPolyLine +uid 387,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,156000,184250,156000" +pts [ +"177750,156000" +"184250,156000" +] +) +start &361 +end &297 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 388,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 389,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,154600,184900,156000" +st "sampleX2" +blo "178000,155800" +tm "WireNameMgr" +) +) +on &49 +) +*550 (Wire +uid 390,0 +shape (OrthoPolyLine +uid 391,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,154000,184250,154000" +pts [ +"177750,154000" +"184250,154000" +] +) +start &360 +end &296 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 392,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 393,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,152600,184900,154000" +st "sampleX1" +blo "178000,153800" +tm "WireNameMgr" +) +) +on &48 +) +*551 (Wire +uid 394,0 +shape (OrthoPolyLine +uid 395,0 +va (VaSet +vasetType 3 +) +xt "157000,160000,160250,160000" +pts [ +"157000,160000" +"160250,160000" +] +) +end &356 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 398,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 399,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,158600,159800,160000" +st "clock" +blo "156000,159800" +tm "WireNameMgr" +) +) +on &15 +) +*552 (Wire +uid 400,0 +shape (OrthoPolyLine +uid 401,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,154000,216250,154000" +pts [ +"201750,154000" +"216250,154000" +] +) +start &300 +end &388 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 402,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 403,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,152600,206150,154000" +st "aX" +blo "203750,153800" +tm "WireNameMgr" +) +) +on &52 +) +*553 (Wire +uid 404,0 +shape (OrthoPolyLine +uid 405,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,160000,184250,160000" +pts [ +"177750,160000" +"184250,160000" +] +) +start &363 +end &299 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 406,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 407,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,158600,184900,160000" +st "sampleX4" +blo "178000,159800" +tm "WireNameMgr" +) +) +on &51 +) +*554 (Wire +uid 408,0 +shape (OrthoPolyLine +uid 409,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,158000,184250,158000" +pts [ +"177750,158000" +"184250,158000" +] +) +start &362 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(VaSet +vasetType 1 +) +xt "62600,13600,63400,14400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 1584,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "19000,4000,63000,74000" +pts [ +"63000,74000" +"63000,4000" +"19000,4000" +] +) +end &90 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1587,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1588,0 +va (VaSet +font "Verdana,12,0" +) +xt "18000,1600,24000,3000" +st "dataOut" +blo "18000,2800" +tm "WireNameMgr" +) +) +on &91 +) +*608 (Wire +uid 1653,0 +shape (OrthoPolyLine +uid 1654,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "63000,42000,74250,42000" +pts [ +"74250,42000" +"63000,42000" +] +) +start &108 +end &606 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1655,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1656,0 +va (VaSet +font "Verdana,12,0" +) +xt "68250,40600,74250,42000" +st "dataOut" +blo "68250,41800" +tm "WireNameMgr" +) +) +on &91 +) +*609 (Wire +uid 1732,0 +shape (OrthoPolyLine +uid 1733,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "59000,68000,74250,68000" +pts [ +"59000,68000" +"74250,68000" +] +) +start &598 +end &95 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1734,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1735,0 +va (VaSet +font "Verdana,12,0" +) +xt "69250,66600,76650,68000" +st "dataInReg" +blo "69250,67800" +tm "WireNameMgr" +) +) +on &246 +) +*610 (Wire +uid 1738,0 +shape (OrthoPolyLine +uid 1739,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "63000,70000,74250,70000" +pts [ +"63000,70000" +"74250,70000" +] +) +start &605 +end &96 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1740,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1741,0 +va (VaSet +font "Verdana,12,0" +) +xt "68250,68600,74250,70000" +st "dataOut" +blo "68250,69800" +tm "WireNameMgr" +) +) +on &91 +) +*611 (Wire +uid 1744,0 +shape (OrthoPolyLine +uid 1745,0 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32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1766,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1767,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,72600,73700,74000" +st "wrHPulse" +blo "67000,73800" +tm "WireNameMgr" +) +) +on &187 +) +*614 (Wire +uid 1768,0 +shape (OrthoPolyLine +uid 1769,0 +va (VaSet +vasetType 3 +) +xt "67000,76000,74250,76000" +pts [ +"67000,76000" +"74250,76000" +] +) +end &101 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1774,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1775,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,74600,73500,76000" +st "wrLPulse" +blo "67000,75800" +tm "WireNameMgr" +) +) +on &197 +) +*615 (Wire +uid 1778,0 +shape (OrthoPolyLine +uid 1779,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "91750,68000,106250,68000" +pts [ +"91750,68000" +"106250,68000" +] +) +start &94 +end &148 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1782,0 +ps "ConnStartEndStrategy" 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"WireNameMgr" +) +) +on &124 +) +*620 (Wire +uid 2472,0 +shape (OrthoPolyLine +uid 2473,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "59000,150000,106250,154000" +pts [ +"106250,154000" +"99000,154000" +"99000,150000" +"59000,150000" +] +) +start &333 +end &599 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2474,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2475,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,152600,107400,154000" +st "dataInReg" +blo "100000,153800" +tm "WireNameMgr" +) +) +on &246 +) +*621 (Wire +uid 2478,0 +shape (OrthoPolyLine +uid 2479,0 +va (VaSet +vasetType 3 +) +xt "103000,166000,106250,166000" +pts [ +"103000,166000" +"106250,166000" +] +) +end &336 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2484,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2485,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,164600,106800,166000" +st "clock" +blo "103000,165800" +tm "WireNameMgr" +) +) +on &15 +) +*622 (Wire +uid 2486,0 +shape (OrthoPolyLine +uid 2487,0 +va (VaSet +vasetType 3 +) +xt "103000,168000,106250,168000" +pts [ +"103000,168000" +"106250,168000" +] +) +end &337 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2492,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2493,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,166600,107100,168000" +st "reset" +blo "103000,167800" +tm "WireNameMgr" +) +) +on &25 +) +*623 (Wire +uid 2638,0 +shape (OrthoPolyLine +uid 2639,0 +va (VaSet +vasetType 3 +) +xt "91750,160000,106250,184000" +pts [ +"91750,184000" +"99000,184000" +"99000,160000" +"106250,160000" +] +) +start &452 +end &338 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2640,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2641,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,158600,106400,160000" +st "memWrX" +blo "100000,159800" +tm "WireNameMgr" +) +) +on &127 +) +*624 (Wire +uid 2644,0 +shape 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+"74250,14000" +] +) +start &607 +end &285 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2862,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2863,0 +va (VaSet +font "Verdana,12,0" +) +xt "68250,12600,74250,14000" +st "dataOut" +blo "68250,13800" +tm "WireNameMgr" +) +) +on &91 +) +*631 (Wire +uid 2866,0 +shape (OrthoPolyLine +uid 2867,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "67000,156000,74250,156000" +pts [ +"67000,156000" +"74250,156000" +] +) +end &140 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2872,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2873,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,154600,74900,156000" +st "patternSize" +blo "66000,155800" +tm "WireNameMgr" +) +) +on &88 +) +*632 (Wire +uid 2919,0 +shape (OrthoPolyLine +uid 2920,0 +va (VaSet +vasetType 3 +) +xt "67000,186000,74250,186000" +pts [ +"74250,186000" +"67000,186000" +] +) +start &458 +sat 32 +eat 16 +stc 0 +st 0 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"125000,152600,129600,154000" +st "memX" +blo "125000,153800" +tm "WireNameMgr" +) +) +on &133 +) +*637 (Wire +uid 3432,0 +shape (OrthoPolyLine +uid 3433,0 +va (VaSet +vasetType 3 +) +xt "209000,166000,216250,166000" +pts [ +"209000,166000" +"216250,166000" +] +) +end &389 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3438,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3439,0 +va (VaSet +font "Verdana,12,0" +) +xt "204000,164600,217900,166000" +st "interpolationEnable" +blo "204000,165800" +tm "WireNameMgr" +) +) +on &124 +) +*638 (Wire +uid 3485,0 +shape (OrthoPolyLine +uid 3486,0 +va (VaSet +vasetType 3 +) +xt "209000,129000,216250,129000" +pts [ +"209000,129000" +"216250,129000" +] +) +end &376 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3491,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3492,0 +va (VaSet +font "Verdana,12,0" +) +xt "204000,127600,217900,129000" +st "interpolationEnable" +blo "204000,128800" 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3764,0 +va (VaSet +vasetType 3 +) +xt "67000,134000,74250,134000" +pts [ +"67000,134000" +"74250,134000" +] +) +end &442 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3767,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3768,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,132600,76800,134000" +st "updatePattern" +blo "66000,133800" +tm "WireNameMgr" +) +) +on &87 +) +*642 (Wire +uid 3769,0 +shape (OrthoPolyLine +uid 3770,0 +va (VaSet +vasetType 3 +) +xt "91750,125000,106250,136000" +pts [ +"91750,136000" +"101000,136000" +"101000,125000" +"106250,125000" +] +) +start &441 +end &324 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3771,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3772,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,123600,106100,125000" +st "memEnY" +blo "100000,124800" +tm "WireNameMgr" +) +) +on &166 +) +*643 (Wire +uid 3773,0 +shape (OrthoPolyLine +uid 3774,0 +va (VaSet +vasetType 3 +) +xt "91750,123000,106250,134000" +pts [ +"91750,134000" +"99000,134000" +"99000,123000" +"106250,123000" +] +) +start &439 +end &327 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3775,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3776,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,121600,106300,123000" +st "memWrY" +blo "100000,122800" +tm "WireNameMgr" +) +) +on &165 +) +*644 (Wire +uid 3777,0 +shape (OrthoPolyLine +uid 3778,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "91750,106000,106250,119000" +pts [ +"91750,106000" +"99000,106000" +"99000,119000" +"106250,119000" +] +) +start &158 +end &328 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3779,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3780,0 +va (VaSet +font "Verdana,12,0" +) +xt "102000,117600,106400,119000" +st "addrY" +blo "102000,118800" +tm "WireNameMgr" +) +) +on &164 +) +*645 (Wire +uid 3793,0 +shape (OrthoPolyLine +uid 3794,0 +va (VaSet +vasetType 3 +) +xt "69000,110000,95000,130000" +pts [ +"91750,130000" +"95000,130000" +"95000,124000" +"69000,124000" +"69000,110000" +"74250,110000" +] +) +start &444 +end &154 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3795,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3796,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,108600,74800,110000" +st "cntIncrY" +blo "69000,109800" +tm "WireNameMgr" +) +) +on &163 +) +*646 (Wire +uid 3797,0 +shape (OrthoPolyLine +uid 3798,0 +va (VaSet +vasetType 3 +) +xt "67000,136000,74250,136000" +pts [ +"74250,136000" +"67000,136000" +] +) +start &445 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3801,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3802,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,134600,75600,136000" +st "newPolynom" +blo "66000,135800" +tm "WireNameMgr" +) +) +on &30 +) +*647 (Wire +uid 3803,0 +shape (OrthoPolyLine +uid 3804,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "67000,106000,74250,106000" +pts [ +"67000,106000" +"74250,106000" +] +) +end &159 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3807,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3808,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,104600,74900,106000" +st "patternSize" +blo "66000,105800" +tm "WireNameMgr" +) +) +on &88 +) +*648 (Wire +uid 3809,0 +shape (OrthoPolyLine +uid 3810,0 +va (VaSet +vasetType 3 +) +xt "67000,108000,74250,108000" +pts [ +"67000,108000" +"74250,108000" +] +) +end &157 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3813,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3814,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,106600,76800,108000" +st "updatePattern" +blo "66000,107800" +tm "WireNameMgr" +) +) +on &87 +) +*649 (Wire +uid 3815,0 +shape (OrthoPolyLine +uid 3816,0 +va (VaSet +vasetType 3 +) +xt "71000,140000,74250,140000" +pts [ +"71000,140000" +"74250,140000" +] +) +end &446 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3819,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3820,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,138600,74800,140000" +st "clock" +blo "71000,139800" +tm "WireNameMgr" +) +) +on &15 +) +*650 (Wire +uid 3821,0 +shape (OrthoPolyLine +uid 3822,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "59000,100000,106250,117000" +pts [ +"59000,100000" +"103000,100000" +"103000,117000" +"106250,117000" +] +) +start &600 +end &322 +es 0 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3823,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3824,0 +va (VaSet +font "Verdana,12,0" +) +xt "101250,115600,108650,117000" +st "dataInReg" +blo "101250,116800" +tm "WireNameMgr" +) +) +on &246 +) +*651 (Wire +uid 3866,0 +shape (OrthoPolyLine +uid 3867,0 +va (VaSet +vasetType 3 +) +xt "71000,114000,74250,114000" +pts [ +"71000,114000" +"74250,114000" +] +) +end &155 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3872,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3873,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,112600,74800,114000" +st "clock" +blo "71000,113800" +tm "WireNameMgr" +) +) +on &15 +) +*652 (Wire +uid 3874,0 +shape (OrthoPolyLine +uid 3875,0 +va (VaSet +vasetType 3 +) +xt "71000,116000,74250,116000" +pts [ +"71000,116000" +"74250,116000" +] +) +end &156 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3880,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3881,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,114600,75100,116000" +st "reset" +blo "71000,115800" +tm "WireNameMgr" +) +) +on &25 +) +*653 (Wire +uid 3882,0 +shape (OrthoPolyLine +uid 3883,0 +va (VaSet +vasetType 3 +) +xt "71000,142000,74250,142000" +pts [ +"71000,142000" +"74250,142000" +] +) +end &447 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3888,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3889,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,140600,75100,142000" +st "reset" +blo "71000,141800" +tm "WireNameMgr" +) +) +on &25 +) +*654 (Wire +uid 3907,0 +shape (OrthoPolyLine +uid 3908,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "123750,117000,131000,117000" +pts [ +"123750,117000" +"131000,117000" +] +) +start &323 +end &167 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3911,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3912,0 +va (VaSet +font "Verdana,12,0" +) +xt "125750,115600,130250,117000" +st "memY" +blo "125750,116800" +tm "WireNameMgr" +) +) +on &171 +) +*655 (Wire +uid 4047,0 +shape (OrthoPolyLine +uid 4048,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "281000,6000,289000,6000" +pts [ +"281000,6000" +"289000,6000" +] +) +start &174 +end &172 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4051,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4052,0 +va (VaSet +font "Verdana,12,0" +) +xt "284000,4600,289600,6000" +st "testOut" +blo "284000,5800" +tm "WireNameMgr" +) +) +on &173 +) +*656 (Wire +uid 4274,0 +shape (OrthoPolyLine +uid 4275,0 +va (VaSet +vasetType 3 +) +xt "23000,66000,26250,66000" +pts [ +"23000,66000" +"26250,66000" +] +) +end &183 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4280,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4281,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,64600,27100,66000" +st "reset" +blo "23000,65800" +tm "WireNameMgr" +) +) +on &25 +) +*657 (Wire +uid 4282,0 +shape (OrthoPolyLine +uid 4283,0 +va (VaSet +vasetType 3 +) +xt "23000,64000,26250,64000" +pts [ +"23000,64000" +"26250,64000" +] +) +end &182 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4288,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4289,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,62600,26800,64000" +st "clock" +blo "23000,63800" +tm "WireNameMgr" +) +) +on &15 +) +*658 (Wire +uid 4292,0 +shape (OrthoPolyLine +uid 4293,0 +va (VaSet +vasetType 3 +) +xt "43750,58000,47000,58000" +pts [ +"43750,58000" +"47000,58000" +] +) +start &179 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4298,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4299,0 +va (VaSet +font "Verdana,12,0" +) +xt "44000,56600,50700,58000" +st "wrHPulse" +blo "44000,57800" +tm "WireNameMgr" +) +) +on &187 +) +*659 (Wire +uid 4329,0 +shape (OrthoPolyLine +uid 4330,0 +va (VaSet +vasetType 3 +) +xt "23000,86000,26250,86000" +pts [ +"23000,86000" +"26250,86000" +] +) +end &192 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4333,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4334,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,84600,26800,86000" +st "clock" +blo "23000,85800" +tm "WireNameMgr" +) +) +on &15 +) +*660 (Wire +uid 4335,0 +shape (OrthoPolyLine +uid 4336,0 +va (VaSet +vasetType 3 +) +xt "23000,88000,26250,88000" +pts [ +"23000,88000" +"26250,88000" +] +) +end &193 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4339,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4340,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,86600,27100,88000" +st "reset" +blo "23000,87800" +tm "WireNameMgr" +) +) +on &25 +) +*661 (Wire +uid 4341,0 +shape (OrthoPolyLine +uid 4342,0 +va (VaSet +vasetType 3 +) +xt "43750,80000,47000,80000" +pts [ +"43750,80000" +"47000,80000" +] +) +start &189 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4345,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4346,0 +va (VaSet +font "Verdana,12,0" +) +xt "44000,78600,50500,80000" +st "wrLPulse" +blo "44000,79800" +tm "WireNameMgr" +) +) +on &197 +) +*662 (Wire +uid 4349,0 +shape (OrthoPolyLine +uid 4350,0 +va (VaSet +vasetType 3 +) +xt "19000,82000,26250,82000" +pts [ +"19000,82000" +"26250,82000" +] +) +end &191 +sat 16 +eat 32 +stc 0 +st 0 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"STSignalDisplayStrategy" +f (Text +uid 4787,0 +va (VaSet +font "Verdana,12,0" +) +xt "157000,90600,161100,92000" +st "reset" +blo "157000,91800" +tm "WireNameMgr" +) +) +on &25 +) +*665 (Wire +uid 4788,0 +shape (OrthoPolyLine +uid 4789,0 +va (VaSet +vasetType 3 +) +xt "157000,90000,160250,90000" +pts [ +"157000,90000" +"160250,90000" +] +) +end &206 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4792,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4793,0 +va (VaSet +font "Verdana,12,0" +) +xt "157000,88600,160800,90000" +st "clock" +blo "157000,89800" +tm "WireNameMgr" +) +) +on &15 +) +*666 (Wire +uid 4794,0 +shape (OrthoPolyLine +uid 4795,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "157000,78000,160250,84000" +pts [ +"160250,84000" +"157000,84000" +"157000,78000" +] +) +start &209 +end &198 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4798,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4799,0 +va (VaSet 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"23000,31800" +tm "WireNameMgr" +) +s (Text +uid 7337,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,32000,23000,32000" +blo "23000,32000" +tm "SignalTypeMgr" +) +) +on &257 +) +*675 (Wire +uid 7117,0 +shape (OrthoPolyLine +uid 7118,0 +va (VaSet +vasetType 3 +) +xt "23000,18000,26250,18000" +pts [ +"23000,18000" +"26250,18000" +] +) +end &242 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7123,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7124,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,16600,27100,18000" +st "reset" +blo "23000,17800" +tm "WireNameMgr" +) +) +on &25 +) +*676 (Wire +uid 7125,0 +shape (OrthoPolyLine +uid 7126,0 +va (VaSet +vasetType 3 +) +xt "23000,16000,26250,16000" +pts [ +"23000,16000" +"26250,16000" +] +) +end &238 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7131,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7132,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,14600,26800,16000" +st "clock" +blo "23000,15800" +tm "WireNameMgr" +) +) +on &15 +) +*677 (Wire +uid 7133,0 +shape (OrthoPolyLine +uid 7134,0 +va (VaSet +vasetType 3 +) +xt "3000,40000,6250,40000" +pts [ +"3000,40000" +"6250,40000" +] +) +end &253 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7139,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7140,0 +va (VaSet +font "Verdana,12,0" +) +xt "3000,38600,7100,40000" +st "reset" +blo "3000,39800" +tm "WireNameMgr" +) +) +on &25 +) +*678 (Wire +uid 7141,0 +shape (OrthoPolyLine +uid 7142,0 +va (VaSet +vasetType 3 +) +xt "3000,38000,6250,38000" +pts [ +"3000,38000" +"6250,38000" +] +) +end &249 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7147,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7148,0 +va (VaSet +font "Verdana,12,0" +) +xt "3000,36600,6800,38000" +st "clock" +blo "3000,37800" +tm "WireNameMgr" +) +) +on &15 +) +*679 (Wire +uid 7160,0 +shape (OrthoPolyLine +uid 7161,0 +va (VaSet +vasetType 3 +) +xt "19000,14000,26250,14000" +pts [ +"26250,14000" +"19000,14000" +] +) +start &241 +end &258 +sat 32 +eat 2 +stc 0 +sf 1 +si 0 +tg (WTG +uid 7164,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7165,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,12600,27400,14000" +st "logic1" +blo "23000,13800" +tm "WireNameMgr" +) +s (Text +uid 7348,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,14000,23000,14000" +blo "23000,14000" +tm "SignalTypeMgr" +) +) +on &262 +) +*680 (Wire +uid 7168,0 +shape (OrthoPolyLine +uid 7169,0 +va (VaSet +vasetType 3 +) +xt "3000,36000,6250,36000" +pts [ +"6250,36000" +"3000,36000" +] +) +start &252 +sat 32 +eat 16 +stc 0 +sf 1 +si 0 +tg (WTG +uid 7174,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7175,0 +va (VaSet +font "Verdana,12,0" +) +xt "3000,34600,7400,36000" +st "logic1" +blo "3000,35800" +tm "WireNameMgr" +) +s (Text +uid 7176,0 +va (VaSet +font "Verdana,12,0" +) +xt "3000,36000,3000,36000" +blo "3000,36000" +tm "SignalTypeMgr" +) +) +on &262 +) +*681 (Wire +uid 7724,0 +shape (OrthoPolyLine +uid 7725,0 +va (VaSet +vasetType 3 +) +xt "23000,116000,26250,116000" +pts [ +"23000,116000" +"26250,116000" +] +) +end &268 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7730,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7731,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,114600,27100,116000" +st "reset" +blo "23000,115800" +tm "WireNameMgr" +) +) +on &25 +) +*682 (Wire +uid 7732,0 +shape (OrthoPolyLine +uid 7733,0 +va (VaSet +vasetType 3 +) +xt "23000,114000,26250,114000" +pts [ +"23000,114000" +"26250,114000" +] +) +end &267 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7738,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7739,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,112600,26800,114000" +st "clock" +blo "23000,113800" +tm "WireNameMgr" +) +) +on &15 +) +*683 (Wire +uid 7740,0 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+"26250,108000" +"17950,108000" +] +) +start &265 +end &276 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7795,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7796,0 +va (VaSet +font "Verdana,12,0" +) +xt "20000,106600,24000,108000" +st "wr16" +blo "20000,107800" +tm "WireNameMgr" +) +) +on &280 +) +*686 (Wire +uid 7801,0 +shape (OrthoPolyLine +uid 7802,0 +va (VaSet +vasetType 3 +) +xt "7000,106000,11000,106000" +pts [ +"7000,106000" +"11000,106000" +] +) +end &274 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7807,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7808,0 +va (VaSet +font "Verdana,12,0" +) +xt "7000,104600,10300,106000" +st "wrH" +blo "7000,105800" +tm "WireNameMgr" +) +) +on &27 +) +*687 (Wire +uid 7809,0 +shape (OrthoPolyLine +uid 7810,0 +va (VaSet +vasetType 3 +) +xt "7000,110000,11000,110000" +pts [ +"7000,110000" +"11000,110000" +] +) +end &275 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7815,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7816,0 +va (VaSet +font "Verdana,12,0" +) +xt "7000,108600,10100,110000" +st "wrL" +blo "7000,109800" +tm "WireNameMgr" +) +) +on &29 +) +*688 (Wire +uid 7907,0 +shape (OrthoPolyLine +uid 7908,0 +va (VaSet +vasetType 3 +) +xt "67000,132000,74250,132000" +pts [ +"67000,132000" +"74250,132000" +] +) +end &443 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7913,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7914,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,130600,74400,132000" +st "wr16Pulse" +blo "67000,131800" +tm "WireNameMgr" +) +) +on &272 +) +*689 (Wire +uid 7915,0 +shape (OrthoPolyLine +uid 7916,0 +va (VaSet +vasetType 3 +) +xt "67000,182000,74250,182000" +pts [ +"67000,182000" +"74250,182000" +] +) +end &456 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7921,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7922,0 +va (VaSet +font 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9253,0 +va (VaSet +font "Verdana,12,0" +) +xt "139000,123600,145900,125000" +st "selSinCos" +blo "139000,124800" +tm "WireNameMgr" +) +) +on &232 +) +*695 (Wire +uid 9254,0 +shape (OrthoPolyLine +uid 9255,0 +va (VaSet +vasetType 3 +) +xt "139000,158000,139000,162000" +pts [ +"139000,162000" +"139000,158000" +] +) +end &129 +sat 16 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 9260,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9261,0 +va (VaSet +font "Verdana,12,0" +) +xt "139000,160600,145900,162000" +st "selSinCos" +blo "139000,161800" +tm "WireNameMgr" +) +) +on &232 +) +*696 (Wire +uid 10531,0 +shape (OrthoPolyLine +uid 10532,0 +va (VaSet +vasetType 3 +) +xt "91750,212000,106250,236000" +pts [ +"91750,236000" +"101000,236000" +"101000,212000" +"106250,212000" +] +) +start &467 +end &407 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10533,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10534,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,210600,106200,212000" +st "memEnZ" +blo "100000,211800" +tm "WireNameMgr" +) +) +on &419 +) +*697 (Wire +uid 10535,0 +shape (OrthoPolyLine +uid 10536,0 +va (VaSet +vasetType 3 +) +xt "91750,210000,106250,234000" +pts [ +"91750,234000" +"99000,234000" +"99000,210000" +"106250,210000" +] +) +start &465 +end &410 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10537,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10538,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,208600,106400,210000" +st "memWrZ" +blo "100000,209800" +tm "WireNameMgr" +) +) +on &418 +) +*698 (Wire +uid 10539,0 +shape (OrthoPolyLine +uid 10540,0 +va (VaSet +vasetType 3 +) +xt "71000,216000,74250,216000" +pts [ +"71000,216000" +"74250,216000" +] +) +end &397 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10543,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10544,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,214600,75100,216000" +st "reset" +blo "71000,215800" +tm "WireNameMgr" +) +) +on &25 +) +*699 (Wire +uid 10545,0 +shape (OrthoPolyLine +uid 10546,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "91750,206000,106250,206000" +pts [ +"91750,206000" +"106250,206000" +] +) +start &399 +end &411 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10547,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10548,0 +va (VaSet +font "Verdana,12,0" +) +xt "102000,204600,106500,206000" +st "addrZ" +blo "102000,205800" +tm "WireNameMgr" +) +) +on &416 +) +*700 (Wire +uid 10549,0 +shape (OrthoPolyLine +uid 10550,0 +va (VaSet +vasetType 3 +) +xt "67000,234000,74250,234000" +pts [ +"67000,234000" +"74250,234000" +] +) +end &468 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10553,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10554,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,232600,76800,234000" +st "updatePattern" +blo "66000,233800" +tm "WireNameMgr" +) +) +on &87 +) +*701 (Wire +uid 10555,0 +shape (OrthoPolyLine +uid 10556,0 +va (VaSet +vasetType 3 +) +xt "69000,210000,95000,230000" +pts [ +"91750,230000" +"95000,230000" +"95000,224000" +"69000,224000" +"69000,210000" +"74250,210000" +] +) +start &470 +end &395 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10557,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10558,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,208600,74900,210000" +st "cntIncrZ" +blo "69000,209800" +tm "WireNameMgr" +) +) +on &415 +) +*702 (Wire +uid 10559,0 +shape (OrthoPolyLine +uid 10560,0 +va (VaSet +vasetType 3 +) +xt "71000,214000,74250,214000" +pts [ +"71000,214000" +"74250,214000" +] +) +end &396 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10563,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10564,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,212600,74800,214000" +st "clock" +blo "71000,213800" +tm "WireNameMgr" +) +) +on &15 +) +*703 (Wire +uid 10565,0 +shape (OrthoPolyLine +uid 10566,0 +va (VaSet +vasetType 3 +) +xt "67000,236000,74250,236000" +pts [ +"74250,236000" +"67000,236000" +] +) +start &471 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10569,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10570,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,234600,75600,236000" +st "newPolynom" +blo "66000,235800" +tm "WireNameMgr" +) +) +on &30 +) +*704 (Wire +uid 10571,0 +shape (OrthoPolyLine +uid 10572,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "67000,206000,74250,206000" +pts [ +"67000,206000" +"74250,206000" +] +) +end &400 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10575,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10576,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,204600,74900,206000" +st "patternSize" +blo "66000,205800" +tm "WireNameMgr" +) +) +on &88 +) +*705 (Wire +uid 10577,0 +shape (OrthoPolyLine +uid 10578,0 +va (VaSet +vasetType 3 +) +xt "67000,208000,74250,208000" +pts [ +"67000,208000" +"74250,208000" +] +) +end &398 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10581,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10582,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,206600,76800,208000" +st "updatePattern" +blo "66000,207800" +tm "WireNameMgr" +) +) +on &87 +) +*706 (Wire +uid 10583,0 +shape (OrthoPolyLine +uid 10584,0 +va (VaSet +vasetType 3 +) +xt "71000,240000,74250,240000" +pts [ +"71000,240000" +"74250,240000" +] +) +end &472 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10587,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10588,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,238600,74800,240000" +st "clock" +blo "71000,239800" +tm "WireNameMgr" +) +) +on &15 +) +*707 (Wire +uid 10589,0 +shape (OrthoPolyLine +uid 10590,0 +va (VaSet +vasetType 3 +) +xt "71000,242000,74250,242000" +pts [ +"71000,242000" +"74250,242000" +] +) +end &473 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10593,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10594,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,240600,75100,242000" +st "reset" +blo "71000,241800" +tm "WireNameMgr" +) +) +on &25 +) +*708 (Wire +uid 10595,0 +shape (OrthoPolyLine +uid 10596,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "123750,204000,131000,204000" +pts [ +"123750,204000" +"131000,204000" +] +) +start &406 +end &491 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10599,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10600,0 +va (VaSet +font "Verdana,12,0" +) +xt "127000,202600,131600,204000" +st "memZ" +blo "127000,203800" +tm "WireNameMgr" +) +) +on &417 +) +*709 (Wire +uid 10601,0 +shape (OrthoPolyLine +uid 10602,0 +va (VaSet +vasetType 3 +) +xt "67000,232000,74250,232000" +pts [ +"67000,232000" +"74250,232000" +] +) +end &469 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10605,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10606,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,230600,73500,232000" +st "wrLPulse" +blo "67000,231800" +tm "WireNameMgr" +) +) +on &197 +) +*710 (Wire +uid 10617,0 +shape (OrthoPolyLine +uid 10618,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "59000,200000,106250,204000" +pts [ +"59000,200000" +"99000,200000" +"99000,204000" +"106250,204000" +] +) +start &601 +end &405 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10619,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10620,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,202600,107400,204000" +st "dataInReg" +blo "100000,203800" +tm "WireNameMgr" +) +) +on &246 +) +*711 (Wire +uid 10662,0 +shape (OrthoPolyLine +uid 10663,0 +va (VaSet +vasetType 3 +) +xt "43750,42000,74250,230000" +pts [ +"43750,42000" +"49000,42000" +"49000,230000" +"74250,230000" +] +) +start &427 +end &466 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10664,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10665,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,228600,70400,230000" +st "selZ" +blo "67000,229800" +tm "WireNameMgr" +) +) +on &431 +) +*712 (Wire +uid 10884,0 +shape (OrthoPolyLine +uid 10885,0 +va (VaSet +vasetType 3 +) +xt "201000,206000,209000,206000" +pts [ +"201000,206000" +"209000,206000" +] +) +start &434 +end &432 +sat 2 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10888,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10889,0 +va (VaSet +font "Verdana,12,0" +) +xt "205000,204600,208700,206000" +st "outZ" +blo "205000,205800" +tm "WireNameMgr" +) +) +on &433 +) +*713 (Wire +uid 10901,0 +shape (OrthoPolyLine +uid 10902,0 +va (VaSet +vasetType 3 +) +xt "103000,218000,106250,218000" +pts [ +"103000,218000" +"106250,218000" +] +) +end &409 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10907,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10908,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,216600,107100,218000" +st "reset" +blo "103000,217800" +tm "WireNameMgr" +) +) +on &25 +) +*714 (Wire +uid 10909,0 +shape (OrthoPolyLine +uid 10910,0 +va (VaSet +vasetType 3 +) +xt "103000,216000,106250,216000" +pts [ +"103000,216000" +"106250,216000" +] +) +end &408 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10915,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10916,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,214600,106800,216000" +st "clock" +blo "103000,215800" +tm "WireNameMgr" +) +) +on &15 +) +*715 (Wire +uid 11529,0 +shape (OrthoPolyLine +uid 11530,0 +va (VaSet +vasetType 3 +) +xt "157000,210000,160250,210000" +pts [ +"157000,210000" +"160250,210000" +] +) +end &478 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11535,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11536,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,208600,159800,210000" +st "clock" +blo "156000,209800" +tm "WireNameMgr" +) +) +on &15 +) +*716 (Wire +uid 11537,0 +shape (OrthoPolyLine +uid 11538,0 +va (VaSet +vasetType 3 +) +xt "157000,212000,160250,212000" +pts [ +"157000,212000" +"160250,212000" +] +) +end &479 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11543,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11544,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,210600,160100,212000" +st "reset" +blo "156000,211800" +tm "WireNameMgr" +) +) +on &25 +) +*717 (Wire +uid 11545,0 +shape (OrthoPolyLine +uid 11546,0 +va (VaSet +vasetType 3 +) +xt "153000,169000,160250,206000" +pts [ +"153000,169000" +"153000,206000" +"160250,206000" +] +) +start &541 +end &480 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11547,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11548,0 +va (VaSet +font "Verdana,12,0" +) +xt "153000,204600,162600,206000" +st "newPolynom" +blo "153000,205800" +tm "WireNameMgr" +) +) +on &30 +) +*718 (Wire +uid 11553,0 +shape (OrthoPolyLine +uid 11554,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,204000,185000,204000" +pts [ +"177750,204000" +"185000,204000" +] +) +start &482 +end &434 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11557,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11558,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,202600,184900,204000" +st "sampleZ1" +blo "178000,203800" +tm "WireNameMgr" +) +) +on &489 +) +*719 (Wire +uid 11561,0 +shape (OrthoPolyLine +uid 11562,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,206000,185000,206000" +pts [ +"177750,206000" +"185000,206000" +] +) +start &483 +end &434 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11565,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11566,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,204600,184900,206000" +st "sampleZ2" +blo "178000,205800" +tm "WireNameMgr" +) +) +on &490 +) +*720 (Wire +uid 11582,0 +shape (OrthoPolyLine +uid 11583,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "147000,204000,160250,204000" +pts [ +"160250,204000" +"147000,204000" +] +) +start &481 +end &491 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11586,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11587,0 +va (VaSet +font "Verdana,12,0" +) +xt "149000,202600,155800,204000" +st "samplesZ" +blo "149000,203800" +tm "WireNameMgr" +) +) +on &495 +) +*721 (Wire +uid 11590,0 +shape (OrthoPolyLine +uid 11591,0 +va (VaSet +vasetType 3 +) +xt "139000,208000,139000,212000" +pts [ +"139000,212000" +"139000,208000" +] +) +end &491 +sat 16 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11596,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11597,0 +va (VaSet +font "Verdana,12,0" +) +xt "139000,210600,145900,212000" +st "selSinCos" +blo "139000,211800" +tm "WireNameMgr" +) +) +on &232 +) +*722 (Wire +uid 11911,0 +shape (OrthoPolyLine +uid 11912,0 +va (VaSet +vasetType 3 +) +xt "261000,89000,264250,89000" +pts [ +"261000,89000" +"264250,89000" +] +) +end &501 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11917,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11918,0 +va (VaSet +font "Verdana,12,0" +) +xt "260000,87600,264100,89000" +st "reset" +blo "260000,88800" +tm "WireNameMgr" +) +) +on &25 +) +*723 (Wire +uid 11919,0 +shape (OrthoPolyLine +uid 11920,0 +va (VaSet +vasetType 3 +) +xt "261000,87000,264250,87000" +pts [ +"261000,87000" +"264250,87000" +] +) +end &498 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11925,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11926,0 +va (VaSet +font "Verdana,12,0" +) +xt "260000,85600,263800,87000" +st "clock" +blo "260000,86800" +tm "WireNameMgr" +) +) +on &15 +) +*724 (Wire +uid 11927,0 +shape (OrthoPolyLine +uid 11928,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "257000,81000,264250,81000" +pts [ +"257000,81000" +"264250,81000" +] +) +end &502 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11933,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11934,0 +va (VaSet +font "Verdana,12,0" +) +xt "258000,79600,265400,81000" +st "unsignedX" +blo "258000,80800" +tm "WireNameMgr" +) +) +on &46 +) +*725 (Wire +uid 11935,0 +shape (OrthoPolyLine +uid 11936,0 +va (VaSet +vasetType 3 +) +xt "257000,83000,264250,83000" +pts [ +"257000,83000" +"264250,83000" +] +) +end &500 +es 0 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11941,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11942,0 +va (VaSet +font "Verdana,12,0" +) +xt "252000,81600,265900,83000" +st "interpolationEnable" +blo "252000,82800" +tm "WireNameMgr" +) +) +on &124 +) +*726 (Wire +uid 11980,0 +shape (OrthoPolyLine +uid 11981,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "257000,59000,264250,59000" +pts [ +"257000,59000" +"264250,59000" +] +) +end &513 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11984,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11985,0 +va (VaSet +font "Verdana,12,0" +) +xt "258000,57600,265300,59000" +st "unsignedY" +blo "258000,58800" +tm "WireNameMgr" +) +) +on &80 +) +*727 (Wire +uid 11986,0 +shape (OrthoPolyLine +uid 11987,0 +va (VaSet +vasetType 3 +) +xt "257000,61000,264250,61000" +pts [ +"257000,61000" +"264250,61000" +] +) +end &511 +es 0 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11990,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11991,0 +va (VaSet +font "Verdana,12,0" +) +xt "252000,59600,265900,61000" +st "interpolationEnable" +blo "252000,60800" +tm "WireNameMgr" +) +) +on &124 +) +*728 (Wire +uid 11992,0 +shape (OrthoPolyLine +uid 11993,0 +va (VaSet +vasetType 3 +) +xt "261000,65000,264250,65000" +pts [ +"261000,65000" +"264250,65000" +] +) +end &509 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 11998,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 11999,0 +va (VaSet +font "Verdana,12,0" +) +xt "260000,63600,263800,65000" +st "clock" +blo "260000,64800" +tm "WireNameMgr" +) +) +on &15 +) +*729 (Wire +uid 12000,0 +shape (OrthoPolyLine +uid 12001,0 +va (VaSet +vasetType 3 +) +xt "261000,67000,264250,67000" +pts [ +"261000,67000" +"264250,67000" +] +) +end &512 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 12006,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12007,0 +va (VaSet +font "Verdana,12,0" +) +xt "260000,65600,264100,67000" +st "reset" +blo "260000,66800" +tm "WireNameMgr" +) +) +on &25 +) +*730 (Wire +uid 12056,0 +shape (OrthoPolyLine +uid 12057,0 +va (VaSet +vasetType 3 +) +xt "281750,85000,289000,85000" +pts [ +"281750,85000" +"289000,85000" +] +) +start &497 +end &518 +ss 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877,0 +decl (Decl +n "bY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 15 +suid 28,0 +) +declText (MLText +uid 878,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,142500,44500,143500" +st "SIGNAL bY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*37 (Net +uid 879,0 +decl (Decl +n "cY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 17 +suid 29,0 +) +declText (MLText +uid 880,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,144300,44400,145300" +st "SIGNAL cY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*38 (Net +uid 881,0 +decl (Decl +n "dY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 20 +suid 30,0 +) +declText (MLText +uid 882,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,147000,44500,148000" +st "SIGNAL dY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*39 (Net +uid 883,0 +decl (Decl +n "sampleY" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 30 +suid 31,0 +) +declText (MLText +uid 884,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,156000,45700,157000" +st "SIGNAL sampleY : signed(signalBitNb-1 DOWNTO 0)" +) +) +*40 (Net +uid 885,0 +decl (Decl +n "unsignedY" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 40 +suid 32,0 +) +declText (MLText +uid 886,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,165000,46800,166000" +st "SIGNAL unsignedY : unsigned(signalBitNb-1 DOWNTO 0)" +) +) +*41 (Net +uid 1348,0 +decl (Decl +n "run" +t "std_ulogic" +o 2 +suid 38,0 +) +declText (MLText +uid 1349,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,123600,31600,124600" +st "run : std_ulogic" +) +) +*42 (Net +uid 1776,0 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(updatePeriodBitNb-1 DOWNTO 0)" +o 8 +suid 42,0 +) +declText (MLText +uid 1777,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,129000,46900,130000" +st "updatePeriod : unsigned(updatePeriodBitNb-1 DOWNTO 0)" +) +) +*43 (Net +uid 1993,0 +decl (Decl +n "interpolationEnable" +t "std_ulogic" +o 23 +suid 43,0 +) +declText (MLText +uid 1994,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,149700,36400,150700" +st "SIGNAL interpolationEnable : std_ulogic" +) +) +*44 (HdlText +uid 3135,0 +optionalChildren [ +*45 (EmbeddedText +uid 3140,0 +commentText (CommentText +uid 3141,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3142,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,152000,146000,156000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3143,0 +va (VaSet +) +xt "132200,152200,144900,155800" +st " +samplesX <= cosine when selSinCos = '1' + else signed(memX); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3136,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,150000,147000,158000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3137,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*46 (Text +uid 3138,0 +va (VaSet +) +xt "131400,158000,134000,159200" +st "eb2" +blo "131400,159000" +tm "HdlTextNameMgr" +) +*47 (Text +uid 3139,0 +va (VaSet +) +xt "131400,159000,132800,160200" +st "2" +blo "131400,160000" +tm "HdlTextNumberMgr" +) +] +) +) +*48 (Net +uid 3152,0 +decl (Decl +n "memX" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 9 +suid 48,0 +) +declText (MLText +uid 3153,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,129900,47000,130900" +st "memX : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*49 (HdlText +uid 3896,0 +optionalChildren [ +*50 (EmbeddedText +uid 3901,0 +commentText (CommentText +uid 3902,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3903,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,115000,146000,119000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3904,0 +va (VaSet +) +xt "132200,115200,144900,118800" +st " +samplesY <= sine when selSinCos = '1' + else signed(memY); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3897,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,113000,147000,121000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3898,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*51 (Text +uid 3899,0 +va (VaSet +) +xt "131400,121000,134000,122200" +st "eb1" +blo "131400,122000" +tm "HdlTextNameMgr" +) +*52 (Text +uid 3900,0 +va (VaSet +) +xt "131400,122000,132800,123200" +st "1" +blo "131400,123000" +tm "HdlTextNumberMgr" +) +] +) +) +*53 (Net +uid 3913,0 +decl (Decl +n "memY" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 10 +suid 53,0 +) +declText (MLText +uid 3914,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,130800,47000,131800" +st "memY : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*54 (HdlText +uid 4719,0 +optionalChildren [ +*55 (EmbeddedText +uid 4724,0 +commentText (CommentText +uid 4725,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4726,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "64000,141000,78000,143000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4727,0 +va (VaSet +) +xt "64200,141200,78000,142400" +st " +step <= to_unsigned(1, step'length); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4720,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "63000,140000,79000,144000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4721,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*56 (Text +uid 4722,0 +va (VaSet +) +xt "63400,144000,66000,145200" +st "eb4" +blo "63400,145000" +tm "HdlTextNameMgr" +) +*57 (Text +uid 4723,0 +va (VaSet +) +xt "63400,145000,64800,146200" +st "4" +blo "63400,146000" +tm "HdlTextNumberMgr" +) +] +) +) +*58 (Net +uid 4800,0 +decl (Decl +n "phase" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 24 +suid 57,0 +) +declText (MLText +uid 4801,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,150600,46400,151600" +st "SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*59 (Net +uid 4802,0 +decl (Decl +n "step" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 38 +suid 58,0 +) +declText (MLText +uid 4803,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,163200,46000,164200" +st "SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*60 (Net +uid 4858,0 +decl (Decl +n "sine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 37 +suid 59,0 +) +declText (MLText +uid 4859,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,162300,44800,163300" +st "SIGNAL sine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*61 (PortIoIn +uid 5080,0 +shape (CompositeShape +uid 5081,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5082,0 +sl 0 +ro 270 +xt "89000,108625,90500,109375" +) +(Line +uid 5083,0 +sl 0 +ro 270 +xt "90500,109000,91000,109000" +pts [ +"90500,109000" +"91000,109000" +] +) +] +) +tg (WTG +uid 5084,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5085,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "81100,108300,88000,109700" +st "selSinCos" +ju 2 +blo "88000,109500" +tm "WireNameMgr" +) +) +) +*62 (HdlText +uid 5244,0 +optionalChildren [ +*63 (EmbeddedText +uid 5249,0 +commentText (CommentText +uid 5250,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 5251,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "99000,104000,115000,114000" +) +oxt "0,0,18000,5000" +text (MLText +uid 5252,0 +va (VaSet +) +xt "99200,104200,114600,113800" +st " +interpolationEnable <= '1' when selSinCos = '1' + else interpolationEn; +interpolateLinear <= '0' when selSinCos = '1' + else interpolateLin; +--interpolateLinear <= interpolateLin; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 5245,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "99000,103000,115000,115000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 5246,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*64 (Text +uid 5247,0 +va (VaSet +) +xt "99400,115000,102000,116200" +st "eb5" +blo "99400,116000" +tm "HdlTextNameMgr" +) +*65 (Text +uid 5248,0 +va (VaSet +) +xt "99400,116000,100800,117200" +st "5" +blo "99400,117000" +tm "HdlTextNumberMgr" +) +] +) +) +*66 (Net +uid 5261,0 +decl (Decl +n "interpolationEn" +t "std_ulogic" +o 22 +suid 60,0 +) +declText (MLText +uid 5262,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,148800,35900,149800" +st "SIGNAL interpolationEn : std_ulogic" +) +) +*67 (Net +uid 5936,0 +decl (Decl +n "cosine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 18 +suid 61,0 +) +declText (MLText +uid 5937,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,145200,45100,146200" +st "SIGNAL cosine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*68 (Net +uid 6503,0 +decl (Decl +n "selSinCos" +t "std_ulogic" +o 6 +suid 62,0 +) +declText (MLText +uid 6504,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,127200,32300,128200" +st "selSinCos : std_ulogic" +) +) +*69 (Net +uid 8148,0 +decl (Decl +n "interpolateLinear" +t "std_ulogic" +o 21 +suid 69,0 +) +declText (MLText +uid 8149,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,147900,36000,148900" +st "SIGNAL interpolateLinear : std_ulogic" +) +) +*70 (Net +uid 9646,0 +decl (Decl +n "interpolateLin" +t "std_ulogic" +o 7 +suid 70,0 +) +declText (MLText +uid 9647,0 +va (VaSet +font "Verdana,8,0" +) +xt "19000,128100,32400,129100" +st "interpolateLin : std_ulogic" +) +) +*71 (PortIoIn +uid 15558,0 +shape (CompositeShape +uid 15559,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15560,0 +sl 0 +ro 270 +xt "49000,112625,50500,113375" +) +(Line +uid 15561,0 +sl 0 +ro 270 +xt "50500,113000,51000,113000" +pts [ +"50500,113000" +"51000,113000" +] +) +] +) +tg (WTG +uid 15562,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15563,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "44200,112500,48000,113900" +st "clock" +ju 2 +blo "48000,113700" +tm "WireNameMgr" +) +) +) +*72 (PortIoIn +uid 15570,0 +shape (CompositeShape +uid 15571,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15572,0 +sl 0 +ro 270 +xt "89000,110625,90500,111375" +) +(Line +uid 15573,0 +sl 0 +ro 270 +xt "90500,111000,91000,111000" +pts [ +"90500,111000" +"91000,111000" +] +) +] +) +tg (WTG +uid 15574,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15575,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "77700,110500,88000,111900" +st "interpolateLin" +ju 2 +blo "88000,111700" +tm "WireNameMgr" +) +) +) +*73 (PortIoIn +uid 15582,0 +shape (CompositeShape +uid 15583,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15584,0 +sl 0 +ro 270 +xt "121000,153625,122500,154375" +) +(Line +uid 15585,0 +sl 0 +ro 270 +xt "122500,154000,123000,154000" +pts [ +"122500,154000" +"123000,154000" +] +) +] +) +tg (WTG +uid 15586,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15587,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "95800,153500,120000,154900" +st "memX : (signalBitNb-1 DOWNTO 0)" +ju 2 +blo "120000,154700" +tm "WireNameMgr" +) +) +) +*74 (PortIoIn +uid 15594,0 +shape (CompositeShape +uid 15595,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15596,0 +sl 0 +ro 270 +xt "49000,114625,50500,115375" +) +(Line +uid 15597,0 +sl 0 +ro 270 +xt "50500,115000,51000,115000" +pts [ +"50500,115000" +"51000,115000" +] +) +] +) +tg (WTG +uid 15598,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15599,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "43900,114500,48000,115900" +st "reset" +ju 2 +blo "48000,115700" +tm "WireNameMgr" +) +) +) +*75 (PortIoIn +uid 15606,0 +shape (CompositeShape +uid 15607,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15608,0 +sl 0 +ro 270 +xt "49000,106625,50500,107375" +) +(Line +uid 15609,0 +sl 0 +ro 270 +xt "50500,107000,51000,107000" +pts [ +"50500,107000" +"51000,107000" +] +) +] +) +tg (WTG +uid 15610,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15611,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "45100,106500,48000,107900" +st "run" +ju 2 +blo "48000,107700" +tm "WireNameMgr" +) +) +) +*76 (PortIoIn +uid 15632,0 +shape (CompositeShape +uid 15633,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15634,0 +sl 0 +ro 270 +xt "49000,108625,50500,109375" +) +(Line +uid 15635,0 +sl 0 +ro 270 +xt "50500,109000,51000,109000" +pts [ +"50500,109000" +"51000,109000" +] +) +] +) +tg (WTG +uid 15636,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15637,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "13500,108500,48000,109900" +st "updatePeriod : (updatePeriodBitNb-1 DOWNTO 0)" +ju 2 +blo "48000,109700" +tm "WireNameMgr" +) +) +) +*77 (PortIoIn +uid 16404,0 +shape (CompositeShape +uid 16405,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16406,0 +sl 0 +ro 270 +xt "121000,116625,122500,117375" +) +(Line +uid 16407,0 +sl 0 +ro 270 +xt "122500,117000,123000,117000" +pts [ +"122500,117000" +"123000,117000" +] +) +] +) +tg (WTG +uid 16408,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16409,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "95900,116500,120000,117900" +st "memY : (signalBitNb-1 DOWNTO 0)" +ju 2 +blo "120000,117700" +tm "WireNameMgr" +) +) +) +*78 (PortIoOut +uid 16674,0 +shape (CompositeShape +uid 16675,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16676,0 +sl 0 +ro 270 +xt "209500,175625,211000,176375" +) +(Line +uid 16677,0 +sl 0 +ro 270 +xt "209000,176000,209500,176000" +pts [ +"209000,176000" +"209500,176000" +] +) +] +) +tg (WTG +uid 16678,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16679,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "212000,175500,221600,176900" +st "newPolynom" +blo "212000,176700" +tm "WireNameMgr" +) +) +) +*79 (SaComponent +uid 17519,0 +optionalChildren [ +*80 (CptPort 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tableAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "inputBitNb" +type "positive" +value "phaseBitNb" +) +(GiElement +name "outputBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "tableAddressBitNb" +type "positive" +value "tableAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*95 (SaComponent +uid 17565,0 +optionalChildren [ +*96 (CptPort +uid 17549,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17550,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "264250,120625,265000,121375" +) +tg (CPTG +uid 17551,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17552,0 +va (VaSet +) +xt "266000,120400,269400,121600" +st "clock" +blo "266000,121400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 3 +suid 1,0 +) +) +) +*97 (CptPort +uid 17553,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17554,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt 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"Verdana,9,1" +) +xt "265600,163600,269600,164800" +st "I_dacx" +blo "265600,164600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 17596,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 17597,0 +text (MLText +uid 17598,0 +va (VaSet +font "Verdana,8,0" +) +xt "265000,165600,283400,166600" +st "signalBitNb = signalBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*111 (SaComponent +uid 17619,0 +optionalChildren [ +*112 (CptPort +uid 17599,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17600,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,155625,75000,156375" +) +tg (CPTG +uid 17601,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17602,0 +va (VaSet +) +xt "76000,155400,79400,156600" +st "clock" +blo "76000,156400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 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"interpolatorCoefficients" +blo "185600,167700" +tm "CptNameMgr" +) +*152 (Text +uid 17735,0 +va (VaSet +font "Verdana,9,1" +) +xt "185600,167600,190600,168800" +st "I_coeffx" +blo "185600,168600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 17736,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 17737,0 +text (MLText +uid 17738,0 +va (VaSet +font "Verdana,8,0" +) +xt "185000,169800,203100,171800" +st "bitNb = signalBitNb ( positive ) +coeffBitNb = coeffBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "bitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "coeffBitNb" +type "positive" +value "coeffBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*153 (SaComponent +uid 17775,0 +optionalChildren [ +*154 (CptPort +uid 17739,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17740,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "216250,167625,217000,168375" +) +tg (CPTG +uid 17741,0 +ps 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"217000,140000,241500,143000" +st "signalBitNb = signalBitNb ( positive ) +coeffBitNb = coeffBitNb ( positive ) +oversamplingBitNb = sampleCountBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "coeffBitNb" +type "positive" +value "coeffBitNb" +) +(GiElement +name "oversamplingBitNb" +type "positive" +value "sampleCountBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*191 (SaComponent +uid 17899,0 +optionalChildren [ +*192 (CptPort +uid 17863,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17864,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "184250,116625,185000,117375" +) +tg (CPTG +uid 17865,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17866,0 +va (VaSet +) +xt "186000,116400,191000,117600" +st "sample1" +blo "186000,117400" +) +) +thePort (LogicalPort +decl (Decl +n "sample1" +t "signed" +b "(bitNb-1 DOWNTO 0)" +o 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"178000,119600,184800,121000" +st "sampleY3" +blo "178000,120800" +tm "WireNameMgr" +) +) +on &33 +) +*252 (Wire +uid 813,0 +shape (OrthoPolyLine +uid 814,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,123000,184250,123000" +pts [ +"177750,123000" +"184250,123000" +] +) +start &212 +end &195 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 815,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 816,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,121600,184800,123000" +st "sampleY4" +blo "178000,122800" +tm "WireNameMgr" +) +) +on &34 +) +*253 (Wire +uid 817,0 +shape (OrthoPolyLine +uid 818,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,117000,216250,117000" +pts [ +"201750,117000" +"216250,117000" +] +) +start &196 +end &186 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 819,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 820,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,115600,206050,117000" +st "aY" +blo "203750,116800" +tm "WireNameMgr" +) +) +on &35 +) +*254 (Wire +uid 821,0 +shape (OrthoPolyLine +uid 822,0 +va (VaSet +vasetType 3 +) +xt "213000,133000,216250,133000" +pts [ +"213000,133000" +"216250,133000" +] +) +end &180 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 825,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 826,0 +va (VaSet +font "Verdana,12,0" +) +xt "212000,131600,216100,133000" +st "reset" +blo "212000,132800" +tm "WireNameMgr" +) +) +on &17 +) +*255 (Wire +uid 827,0 +shape (OrthoPolyLine +uid 828,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,119000,216250,119000" +pts [ +"201750,119000" +"216250,119000" +] +) +start &197 +end &185 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 829,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 830,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,117600,206050,119000" +st "bY" +blo "203750,118800" +tm "WireNameMgr" +) +) +on &36 +) +*256 (Wire +uid 831,0 +shape (OrthoPolyLine +uid 832,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,121000,216250,121000" +pts [ +"201750,121000" +"216250,121000" +] +) +start &199 +end &184 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 833,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 834,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,119600,205850,121000" +st "cY" +blo "203750,120800" +tm "WireNameMgr" +) +) +on &37 +) +*257 (Wire +uid 835,0 +shape (OrthoPolyLine +uid 836,0 +va (VaSet +vasetType 3 +) +xt "261000,123000,264250,123000" +pts [ +"261000,123000" +"264250,123000" +] +) +end &99 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 839,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 840,0 +va (VaSet +font "Verdana,12,0" +) +xt "260000,121600,264100,123000" +st "reset" +blo "260000,122800" +tm "WireNameMgr" +) +) +on &17 +) +*258 (Wire +uid 841,0 +shape (OrthoPolyLine +uid 842,0 +va (VaSet +vasetType 3 +) +xt "213000,131000,216250,131000" +pts [ +"213000,131000" +"216250,131000" +] +) +end &179 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 845,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 846,0 +va (VaSet +font "Verdana,12,0" +) +xt "212000,129600,215800,131000" +st "clock" +blo "212000,130800" +tm "WireNameMgr" +) +) +on &12 +) +*259 (Wire +uid 847,0 +shape (OrthoPolyLine +uid 848,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "233750,117000,240250,117000" +pts [ +"233750,117000" +"240250,117000" +] +) +start &183 +end &174 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 849,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 850,0 +va (VaSet +font "Verdana,12,0" +) +xt "234000,115600,240000,117000" +st "sampleY" +blo "234000,116800" +tm "WireNameMgr" +) +) +on &39 +) +*260 (Wire +uid 851,0 +shape (OrthoPolyLine +uid 852,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "257750,117000,264250,117000" +pts [ +"257750,117000" +"264250,117000" +] +) +start &173 +end &97 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 853,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 854,0 +va (VaSet +font "Verdana,12,0" +) +xt "258000,115600,265300,117000" +st "unsignedY" +blo "258000,116800" +tm "WireNameMgr" +) +) +on &40 +) +*261 (Wire +uid 855,0 +shape (OrthoPolyLine +uid 856,0 +va (VaSet +vasetType 3 +) +xt "261000,121000,264250,121000" +pts [ +"261000,121000" +"264250,121000" +] +) +end &96 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 859,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 860,0 +va (VaSet +font "Verdana,12,0" +) +xt "260000,119600,263800,121000" +st "clock" +blo "260000,120800" +tm "WireNameMgr" +) +) +on &12 +) +*262 (Wire +uid 1995,0 +shape (OrthoPolyLine +uid 1996,0 +va (VaSet +vasetType 3 +) +xt "153000,176000,160250,176000" +pts [ +"153000,176000" +"160250,176000" +] +) +end &124 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2001,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2002,0 +va (VaSet +font "Verdana,12,0" +) +xt "148000,174600,161900,176000" +st "interpolationEnable" +blo "148000,175800" +tm "WireNameMgr" +) +) +on &43 +) +*263 (Wire +uid 3146,0 +shape (OrthoPolyLine +uid 3147,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "123000,154000,131000,154000" +pts [ +"123000,154000" +"131000,154000" +] +) +start &73 +end &44 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3150,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3151,0 +va (VaSet +font "Verdana,12,0" +) +xt "124000,152600,128600,154000" +st "memX" +blo "124000,153800" +tm "WireNameMgr" +) +) +on &48 +) +*264 (Wire +uid 3432,0 +shape (OrthoPolyLine +uid 3433,0 +va (VaSet +vasetType 3 +) +xt "209000,166000,216250,166000" +pts [ +"209000,166000" +"216250,166000" +] +) +end &162 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3438,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3439,0 +va (VaSet +font "Verdana,12,0" +) +xt "204000,164600,217900,166000" +st "interpolationEnable" +blo "204000,165800" +tm "WireNameMgr" +) +) +on &43 +) +*265 (Wire +uid 3485,0 +shape (OrthoPolyLine +uid 3486,0 +va (VaSet +vasetType 3 +) +xt "209000,129000,216250,129000" +pts [ +"209000,129000" +"216250,129000" +] +) +end &187 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3491,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3492,0 +va (VaSet +font "Verdana,12,0" +) +xt "204000,127600,217900,129000" +st "interpolationEnable" +blo "204000,128800" +tm "WireNameMgr" +) +) +on &43 +) +*266 (Wire +uid 3907,0 +shape (OrthoPolyLine +uid 3908,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "123000,117000,131000,117000" +pts [ +"123000,117000" +"131000,117000" +] +) +start &77 +end &49 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3911,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3912,0 +va (VaSet +font "Verdana,12,0" +) +xt "125750,115600,130250,117000" +st "memY" +blo "125750,116800" +tm "WireNameMgr" +) +) +on &53 +) +*267 (Wire +uid 4770,0 +shape (OrthoPolyLine +uid 4771,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "91750,150000,98250,150000" +pts [ +"91750,150000" +"98250,150000" +] +) +start &113 +end &90 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4774,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4775,0 +va (VaSet +font "Verdana,12,0" +) +xt "92000,148600,96700,150000" +st "phase" +blo "92000,149800" +tm "WireNameMgr" +) +) +on &58 +) +*268 (Wire +uid 4782,0 +shape (OrthoPolyLine +uid 4783,0 +va (VaSet +vasetType 3 +) +xt "71000,158000,74250,158000" +pts [ +"71000,158000" +"74250,158000" +] +) +end &114 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4786,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4787,0 +va (VaSet +font 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0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,9,0" +) +xt "200,200,2200,1100" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title 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+ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *106 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,5800,6500,6700" +st "Declarations" +blo "0,6500" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,6700,3000,7600" +st "Ports:" +blo "0,7400" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,17500,2500,18400" +st "User:" +blo "0,18200" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,5800,7500,6700" +st "Internal User:" +blo "0,6500" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,18400,2000,18400" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,5800,0,5800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 776,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer@registers/struct.bd b/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer@registers/struct.bd new file mode 100644 index 0000000..b8a0102 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer@registers/struct.bd @@ -0,0 +1,10779 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_ctl" +duLibraryName "SystemOnChip" +duName "periphControlReg" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "patternSizeBitNb" +type "positive" +value "patternAddressBitNb" +) +] +mwi 0 +uid 21149,0 +) +(Instance +name "I_speed" +duLibraryName "SystemOnChip" +duName "periphSpeedReg" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "updatePeriodBitNb" +type "positive" +value "updatePeriodBitNb" +) +] +mwi 0 +uid 21186,0 +) +(Instance +name "I_decoder" +duLibraryName "SystemOnChip" +duName "periphAddressDecoder" +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "addressBitNb" +) +] +mwi 0 +uid 21219,0 +) +(Instance +name "I_addry" +duLibraryName "SystemOnChip" +duName "blockRAMAddressCounter" +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +] +mwi 0 +uid 21252,0 +) +(Instance +name "I_ctly" +duLibraryName "SystemOnChip" +duName "blockRAMControl" +elements [ +] +mwi 0 +uid 21297,0 +) +(Instance +name "I_addrx" +duLibraryName "SystemOnChip" +duName "blockRAMAddressCounter" +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +] +mwi 0 +uid 21330,0 +) +(Instance +name "I_ctlx" +duLibraryName "SystemOnChip" +duName "blockRAMControl" +elements [ +] +mwi 0 +uid 21375,0 +) +(Instance +name "I_ramx" +duLibraryName "SystemOnChip" +duName "blockRAM" +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +(GiElement +name "dataBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "initFileSpec" +type "string" +value "\"$SIMULATION_DIR/ramYInit.txt\"" +) +] +mwi 0 +uid 21412,0 +) +(Instance +name "I_ramy" +duLibraryName "SystemOnChip" +duName "blockRAM" +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +(GiElement +name "dataBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "initFileSpec" +type "string" +value "\"$SIMULATION_DIR/ramXInit.txt\"" +) +] +mwi 0 +uid 21449,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb3" +number "3" +) +(EmbeddedInstance +name "eb8" +number "8" +) +(EmbeddedInstance +name "eb9" +number "9" +) +(EmbeddedInstance +name "eb10" +number "10" +) +(EmbeddedInstance +name "eb11" +number "11" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander 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"graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:01:22" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "SystemOnChip" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/SystemOnChip" +) +(vvPair +variable "library_downstream_SpyGlass" +value "U:\\SEm_curves\\Synthesis" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "ahbBeamerRegisters" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value 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+o 3 +suid 53,0 +) +declText (MLText +uid 3914,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,103000,29700,104000" +st "memY : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*34 (PortIoOut +uid 4041,0 +shape (CompositeShape +uid 4042,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4043,0 +sl 0 +ro 270 +xt "143500,3625,145000,4375" +) +(Line +uid 4044,0 +sl 0 +ro 270 +xt "143000,4000,143500,4000" +pts [ +"143000,4000" +"143500,4000" +] +) +] +) +tg (WTG +uid 4045,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4046,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "146000,3300,166900,4700" +st "testOut : (1 TO testOutBitNb)" +blo "146000,4500" +tm "WireNameMgr" +) +) +) +*35 (Net +uid 4053,0 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO testOutBitNb)" +o 1 +suid 54,0 +) +declText (MLText +uid 4054,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,101200,26200,102200" +st "testOut : std_ulogic_vector(1 TO testOutBitNb)" +) +) +*36 (HdlText +uid 4055,0 +optionalChildren [ +*37 (EmbeddedText +uid 4060,0 +commentText (CommentText +uid 4061,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4062,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "120000,3000,134000,25000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4063,0 +va (VaSet +) +xt "120200,3200,133900,24800" +st " +testout( 1) <= run_int; run <= run_int; +testout( 2) <= updatePattern; +testout( 3) <= interpolateLin_int; interpolateLin <= interpolateLin_int; +testout( 4) <= newPolynom; +testout( 5) <= newPolynom; +testout( 6) <= '0'; +testout( 7) <= '0'; +testout( 8) <= selControl; +testout( 9) <= selSpeed; +testout(10) <= selX; +testout(11) <= selY; +testout(12) <= '0'; +testout(13) <= addr(0); +testout(14) <= addr(1); +testout(15) <= dataIn(0); +testout(16) <= dataIn(1); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 22000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4056,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "119000,2000,135000,26000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4057,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*38 (Text +uid 4058,0 +va (VaSet +) +xt "119400,26000,122000,27200" +st "eb3" +blo "119400,27000" +tm "HdlTextNameMgr" +) +*39 (Text +uid 4059,0 +va (VaSet +) +xt "119400,27000,120800,28200" +st "3" +blo "119400,28000" +tm "HdlTextNumberMgr" +) +] +) +) +*40 (Net +uid 9646,0 +decl (Decl +n "interpolateLin" +t "std_ulogic" +o 6 +suid 70,0 +) +declText (MLText +uid 9647,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,105700,15100,106700" +st "interpolateLin : std_ulogic" +) +) +*41 (PortIoOut +uid 14845,0 +shape (CompositeShape +uid 14846,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14847,0 +sl 0 +ro 270 +xt "134500,115625,136000,116375" +) +(Line +uid 14848,0 +sl 0 +ro 270 +xt "134000,116000,134500,116000" +pts [ +"134000,116000" +"134500,116000" +] +) +] +) +tg (WTG +uid 14849,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14850,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "137000,115300,161100,116700" +st "memY : (signalBitNb-1 DOWNTO 0)" +blo "137000,116500" +tm "WireNameMgr" +) +) +) +*42 (PortIoOut +uid 14851,0 +shape (CompositeShape +uid 14852,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14853,0 +sl 0 +ro 270 +xt "134500,153625,136000,154375" +) +(Line +uid 14854,0 +sl 0 +ro 270 +xt "134000,154000,134500,154000" +pts [ +"134000,154000" +"134500,154000" +] +) +] +) +tg (WTG +uid 14855,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14856,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "137000,153300,161200,154700" +st "memX : (signalBitNb-1 DOWNTO 0)" +blo "137000,154500" +tm "WireNameMgr" +) +) +) +*43 (PortIoOut +uid 14857,0 +shape (CompositeShape +uid 14858,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14859,0 +sl 0 +ro 270 +xt "109750,41625,111250,42375" +) +(Line +uid 14860,0 +sl 0 +ro 270 +xt "109250,42000,109750,42000" +pts [ +"109250,42000" +"109750,42000" +] +) +] +) +tg (WTG +uid 14861,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14862,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "112000,41300,114900,42700" +st "run" +blo "112000,42500" +tm "WireNameMgr" +) +) +) +*44 (PortIoOut +uid 14863,0 +shape (CompositeShape +uid 14864,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14865,0 +sl 0 +ro 270 +xt "109750,69625,111250,70375" +) +(Line +uid 14866,0 +sl 0 +ro 270 +xt "109250,70000,109750,70000" +pts [ +"109250,70000" +"109750,70000" +] +) +] +) +tg (WTG +uid 14867,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14868,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "112000,69300,146500,70700" +st "updatePeriod : (updatePeriodBitNb-1 DOWNTO 0)" +blo "112000,70500" +tm "WireNameMgr" +) +) +) +*45 (PortIoOut +uid 14869,0 +shape (CompositeShape +uid 14870,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14871,0 +sl 0 +ro 270 +xt "109500,43625,111000,44375" +) +(Line +uid 14872,0 +sl 0 +ro 270 +xt "109000,44000,109500,44000" +pts [ +"109000,44000" +"109500,44000" +] +) +] +) +tg (WTG +uid 14873,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14874,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "112000,43300,122300,44700" +st "interpolateLin" +blo "112000,44500" +tm "WireNameMgr" +) +) +) +*46 (Net +uid 16705,0 +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 25 +suid 74,0 +) +declText (MLText +uid 16706,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,126400,31800,127400" +st "SIGNAL dataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*47 (HdlText +uid 16707,0 +optionalChildren [ +*48 (EmbeddedText +uid 16712,0 +commentText (CommentText +uid 16713,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 16714,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "30000,39000,46000,53000" +) +oxt "0,0,18000,5000" +text (MLText +uid 16715,0 +va (VaSet +) +xt "30200,39200,45400,52400" +st " +storeControls: process(reset, clock) +begin + if reset = '1' then + addr <= (others => '0'); + write <= '0'; + elsif rising_edge(clock) then + write <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addr <= hAddr(addr'range); + write <= hWrite; + end if; + end if; +end process storeControls; + +dataIn <= hWData; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 14000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 16708,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "30000,38000,46000,54000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 16709,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*49 (Text +uid 16710,0 +va (VaSet +) +xt "30400,54000,33000,55200" +st "eb8" +blo "30400,55000" +tm "HdlTextNameMgr" +) +*50 (Text +uid 16711,0 +va (VaSet +) +xt "30400,55000,31800,56200" +st "8" +blo "30400,56000" +tm "HdlTextNumberMgr" +) +] +) +) +*51 (Net +uid 16716,0 +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 20 +suid 75,0 +) +declText (MLText +uid 16717,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,121900,29500,122900" +st "SIGNAL addr : unsigned(addressBitNb-1 DOWNTO 0)" +) +) +*52 (HdlText +uid 17145,0 +optionalChildren [ +*53 (EmbeddedText +uid 17150,0 +commentText (CommentText +uid 17151,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 17152,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "58000,87000,66000,93000" +) +oxt "0,0,18000,5000" +text (MLText +uid 17153,0 +va (VaSet +) +xt "58200,87200,65800,92000" +st " +memDataIn <= dataIn(memDataIn'range); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 8000 +) +) +) +] +shape (Rectangle +uid 17146,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "58000,86000,66000,94000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 17147,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*54 (Text +uid 17148,0 +va (VaSet +) +xt "58400,94000,61000,95200" +st "eb9" +blo "58400,95000" +tm "HdlTextNameMgr" +) +*55 (Text +uid 17149,0 +va (VaSet +) +xt "58400,95000,59800,96200" +st "9" +blo "58400,96000" +tm "HdlTextNumberMgr" +) +] +) +) +*56 (Net +uid 17162,0 +decl (Decl +n "memDataIn" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 38 +suid 77,0 +) +declText (MLText +uid 17163,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,138100,33600,139100" +st "SIGNAL memDataIn : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*57 (Net +uid 17505,0 +decl (Decl +n "write" +t "std_ulogic" +o 37 +suid 78,0 +) +declText (MLText +uid 17506,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,137200,17600,138200" +st "SIGNAL write : std_ulogic" +) +) +*58 (HdlText +uid 17860,0 +optionalChildren [ +*59 (EmbeddedText +uid 17865,0 +commentText (CommentText +uid 17866,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 17867,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "30000,19000,46000,29000" +) +oxt "0,0,18000,5000" +text (MLText +uid 17868,0 +va (VaSet +) +xt "30200,19200,46200,27600" +st " +hRData <= std_ulogic_vector(dataOut); + +hReady <= '1'; -- no wait state +hResp <= '0'; -- data OK +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 17861,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "30000,18000,46000,30000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 17862,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*60 (Text +uid 17863,0 +va (VaSet +) +xt "30400,30000,33700,31200" +st "eb10" +blo "30400,31000" +tm "HdlTextNameMgr" +) +*61 (Text +uid 17864,0 +va (VaSet +) +xt "30400,31000,32500,32200" +st "10" +blo "30400,32000" +tm "HdlTextNumberMgr" +) +] +) +) +*62 (PortIoIn +uid 18266,0 +shape (CompositeShape +uid 18267,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 18268,0 +sl 0 +ro 270 +xt "68000,135625,69500,136375" +) +(Line +uid 18269,0 +sl 0 +ro 270 +xt "69500,136000,70000,136000" +pts [ +"69500,136000" +"70000,136000" +] +) +] +) +tg (WTG +uid 18270,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18271,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "57400,135300,67000,136700" +st "newPolynom" +ju 2 +blo "67000,136500" +tm "WireNameMgr" +) +) +) +*63 (PortIoIn +uid 19642,0 +shape (CompositeShape +uid 19643,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19644,0 +sl 0 +ro 270 +xt "20000,3625,21500,4375" +) +(Line +uid 19645,0 +sl 0 +ro 270 +xt "21500,4000,22000,4000" +pts [ +"21500,4000" +"22000,4000" +] +) +] +) +tg (WTG +uid 19646,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19647,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "15500,3500,19000,4900" +st "hClk" +ju 2 +blo "19000,4700" +tm "WireNameMgr" +) +) +) +*64 (Net +uid 19654,0 +decl (Decl +n "hClk" +t "std_ulogic" +o 8 +suid 79,0 +) +declText (MLText +uid 19655,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,107500,14500,108500" +st "hClk : std_ulogic" +) +) +*65 (PortIoOut +uid 19656,0 +shape (CompositeShape +uid 19657,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19658,0 +sl 0 +ro 90 +xt "20000,21625,21500,22375" +) +(Line +uid 19659,0 +sl 0 +ro 90 +xt "21500,22000,22000,22000" +pts [ +"22000,22000" +"21500,22000" +] +) +] +) +tg (WTG +uid 19660,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19661,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-6700,21300,19000,22700" +st "hRData : (ahbDataBitNb-1 downto 0)" +ju 2 +blo "19000,22500" +tm "WireNameMgr" +) +) +) +*66 (Net +uid 19668,0 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 9 +suid 80,0 +) +declText (MLText +uid 19669,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,108400,29900,109400" +st "hRData : std_ulogic_vector(ahbDataBitNb-1 downto 0)" +) +) +*67 (PortIoIn +uid 19670,0 +shape (CompositeShape +uid 19671,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19672,0 +sl 0 +ro 270 +xt "20000,41625,21500,42375" +) +(Line +uid 19673,0 +sl 0 +ro 270 +xt "21500,42000,22000,42000" +pts [ +"21500,42000" +"22000,42000" +] +) +] +) +tg (WTG +uid 19674,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19675,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-7900,41500,19000,42900" +st "hAddr : (ahbAddressBitNb-1 downto 0)" +ju 2 +blo "19000,42700" +tm "WireNameMgr" +) +) +) +*68 (Net +uid 19682,0 +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 downto 0)" +o 10 +suid 81,0 +) +declText (MLText +uid 19683,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,109300,27300,110300" +st "hAddr : unsigned(ahbAddressBitNb-1 downto 0)" +) +) +*69 (PortIoIn +uid 19684,0 +shape (CompositeShape +uid 19685,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19686,0 +sl 0 +ro 270 +xt "20000,5625,21500,6375" +) +(Line +uid 19687,0 +sl 0 +ro 270 +xt "21500,6000,22000,6000" +pts [ +"21500,6000" +"22000,6000" +] +) +] +) +tg (WTG +uid 19688,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19689,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "12200,5500,19000,6900" +st "hReset_n" +ju 2 +blo "19000,6700" +tm "WireNameMgr" +) +) +) +*70 (Net +uid 19696,0 +decl (Decl +n "hReset_n" +t "std_ulogic" +o 11 +suid 82,0 +) +declText (MLText +uid 19697,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,110200,15300,111200" +st "hReset_n : std_ulogic" +) +) +*71 (PortIoIn +uid 19698,0 +shape (CompositeShape +uid 19699,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19700,0 +sl 0 +ro 270 +xt "20000,43625,21500,44375" +) +(Line +uid 19701,0 +sl 0 +ro 270 +xt "21500,44000,22000,44000" +pts [ +"21500,44000" +"22000,44000" +] +) +] +) +tg (WTG +uid 19702,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19703,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-7200,43500,19000,44900" +st "hWData : (ahbDataBitNb-1 downto 0)" +ju 2 +blo "19000,44700" +tm "WireNameMgr" +) +) +) +*72 (Net +uid 19710,0 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 12 +suid 83,0 +) +declText (MLText +uid 19711,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,111100,30100,112100" +st "hWData : std_ulogic_vector(ahbDataBitNb-1 downto 0)" +) +) +*73 (PortIoIn +uid 19712,0 +shape (CompositeShape +uid 19713,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19714,0 +sl 0 +ro 270 +xt "20000,45625,21500,46375" +) +(Line +uid 19715,0 +sl 0 +ro 270 +xt "21500,46000,22000,46000" +pts [ +"21500,46000" +"22000,46000" +] +) +] +) +tg (WTG +uid 19716,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19717,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-6900,45500,19000,46900" +st "hTrans : (ahbTransBitNb-1 downto 0)" +ju 2 +blo "19000,46700" +tm "WireNameMgr" +) +) +) +*74 (Net +uid 19724,0 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 downto 0)" +o 13 +suid 84,0 +) +declText (MLText +uid 19725,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,112000,29900,113000" +st "hTrans : std_ulogic_vector(ahbTransBitNb-1 downto 0)" +) +) +*75 (PortIoIn +uid 19726,0 +shape (CompositeShape +uid 19727,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19728,0 +sl 0 +ro 270 +xt "20000,47625,21500,48375" +) +(Line +uid 19729,0 +sl 0 +ro 270 +xt "21500,48000,22000,48000" +pts [ +"21500,48000" +"22000,48000" +] +) +] +) +tg (WTG +uid 19730,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19731,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "14000,47500,19000,48900" +st "hWrite" +ju 2 +blo "19000,48700" +tm "WireNameMgr" +) +) +) +*76 (Net +uid 19738,0 +decl (Decl +n "hWrite" +t "std_ulogic" +o 14 +suid 85,0 +) +declText (MLText +uid 19739,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,112900,14700,113900" +st "hWrite : std_ulogic" +) +) +*77 (PortIoIn +uid 19740,0 +shape (CompositeShape +uid 19741,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 19742,0 +sl 0 +ro 270 +xt "20000,49625,21500,50375" +) +(Line +uid 19743,0 +sl 0 +ro 270 +xt "21500,50000,22000,50000" +pts [ +"21500,50000" +"22000,50000" +] +) +] +) +tg (WTG +uid 19744,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 19745,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "15500,49500,19000,50900" +st "hSel" +ju 2 +blo "19000,50700" +tm "WireNameMgr" +) +) +) +*78 (Net +uid 19752,0 +decl (Decl +n "hSel" +t "std_ulogic" +o 15 +suid 86,0 +) +declText (MLText +uid 19753,0 +va (VaSet +font "Verdana,8,0" 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"83100,43400,93000,44600" +st "interpolateLinear" +ju 2 +blo "93000,44400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "interpolateLinear" +t "std_ulogic" +o 9 +suid 9,0 +) +) +) +*99 (CptPort +uid 21145,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21146,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,49625,94750,50375" +) +tg (CPTG +uid 21147,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21148,0 +va (VaSet +) +xt "85900,49400,93000,50600" +st "patternSize" +ju 2 +blo "93000,50400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "patternSize" +t "unsigned" +b "(patternSizeBitNb-1 downto 0)" +o 10 +suid 2011,0 +) +) +) +] +shape (Rectangle +uid 21150,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "78000,38000,94000,58000" +) +oxt "38000,9000,54000,29000" +ttg (MlTextGroup +uid 21151,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*100 (Text +uid 21152,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,57800,87000,59000" +st "SystemOnChip" +blo "78600,58800" +tm "BdLibraryNameMgr" +) +*101 (Text +uid 21153,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,58700,88400,59900" +st "periphControlReg" +blo "78600,59700" +tm "CptNameMgr" +) +*102 (Text +uid 21154,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,59600,81600,60800" +st "I_ctl" +blo "78600,60600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 21155,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 21156,0 +text (MLText +uid 21157,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,61600,102300,63600" +st "dataBitNb = dataBitNb ( positive ) +patternSizeBitNb = patternAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "patternSizeBitNb" +type "positive" +value "patternAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*103 (SaComponent +uid 21186,0 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(CptPort +uid 21166,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21167,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,71625,78000,72375" +) +tg (CPTG +uid 21168,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21169,0 +va (VaSet +) +xt "79000,71400,83800,72600" +st "dataOut" +blo "79000,72400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dataOut" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 3 +suid 3,0 +) +) +) +*107 (CptPort +uid 21170,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21171,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,77625,78000,78375" +) +tg (CPTG +uid 21172,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21173,0 +va (VaSet +) +xt "79000,77400,80900,78600" +st "en" +blo "79000,78400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 4 +suid 5,0 +) +) +) +*108 (CptPort +uid 21174,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21175,0 +ro 90 +va (VaSet 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"VerticalLayoutStrategy" +f (Text +uid 21185,0 +va (VaSet +) +xt "79000,75400,82100,76600" +st "write" +blo "79000,76400" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 7 +suid 8,0 +) +) +) +] +shape (Rectangle +uid 21187,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "78000,66000,94000,86000" +) +oxt "38000,9000,54000,29000" +ttg (MlTextGroup +uid 21188,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*111 (Text +uid 21189,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,85800,87000,87000" +st "SystemOnChip" +blo "78600,86800" +tm "BdLibraryNameMgr" +) +*112 (Text +uid 21190,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,86700,87800,87900" +st "periphSpeedReg" +blo "78600,87700" +tm "CptNameMgr" +) +*113 (Text +uid 21191,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,87600,83200,88800" +st "I_speed" +blo "78600,88600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 21192,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 21193,0 +text (MLText +uid 21194,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,89600,102400,91600" +st "dataBitNb = dataBitNb ( positive ) +updatePeriodBitNb = updatePeriodBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "updatePeriodBitNb" +type "positive" +value "updatePeriodBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*114 (SaComponent +uid 21219,0 +optionalChildren [ +*115 (CptPort +uid 21195,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21196,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,71625,46750,72375" +) +tg (CPTG +uid 21197,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21198,0 +va (VaSet +) +xt "38400,71400,45000,72600" +st "selControl" +ju 2 +blo "45000,72400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selControl" +t "std_ulogic" +o 1 +suid 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21208,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,77625,46750,78375" +) +tg (CPTG +uid 21209,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21210,0 +va (VaSet +) +xt "42100,77400,45000,78600" +st "selX" +ju 2 +blo "45000,78400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selX" +t "std_ulogic" +o 4 +suid 5,0 +) +) +) +*119 (CptPort +uid 21211,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21212,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,79625,46750,80375" +) +tg (CPTG +uid 21213,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21214,0 +va (VaSet +) +xt "42100,79400,45000,80600" +st "selY" +ju 2 +blo "45000,80400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selY" +t "std_ulogic" +o 5 +suid 6,0 +) +) +) +*120 (CptPort +uid 21215,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21216,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,81625,46750,82375" +) +tg (CPTG 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"CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21243,0 +va (VaSet +) +xt "79000,107400,85500,108600" +st "updateMem" +blo "79000,108400" +) +) +thePort (LogicalPort +decl (Decl +n "updateMem" +t "std_ulogic" +o 4 +suid 4,0 +) +) +) +*129 (CptPort +uid 21244,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21245,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,105625,94750,106375" +) +tg (CPTG +uid 21246,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21247,0 +va (VaSet +) +xt "90100,105400,93000,106600" +st "addr" +ju 2 +blo "93000,106400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 5 +suid 5,0 +) +) +) +*130 (CptPort +uid 21248,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21249,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,105625,78000,106375" +) +tg (CPTG +uid 21250,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21251,0 +va (VaSet +) +xt "79000,105400,86100,106600" +st "patternSize" +blo "79000,106400" +) +) +thePort (LogicalPort +decl (Decl +n "patternSize" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 6 +suid 6,0 +) +) +) +] +shape (Rectangle +uid 21253,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "78000,102000,94000,118000" +) +oxt "38000,13000,54000,29000" +ttg (MlTextGroup +uid 21254,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*131 (Text +uid 21255,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,117800,87000,119000" +st "SystemOnChip" +blo "78600,118800" +tm "BdLibraryNameMgr" +) +*132 (Text +uid 21256,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,118700,93200,119900" +st "blockRAMAddressCounter" +blo "78600,119700" +tm "CptNameMgr" +) +*133 (Text +uid 21257,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,119600,83100,120800" +st "I_addry" +blo "78600,120600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 21258,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 21259,0 +text (MLText +uid 21260,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,121600,100900,122600" +st "addressBitNb = patternAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*134 (SaComponent +uid 21297,0 +optionalChildren [ +*135 (CptPort +uid 21261,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21262,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,133625,94750,134375" +) +tg (CPTG +uid 21263,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21264,0 +va (VaSet +) +xt "88600,133400,93000,134600" +st "memWr" +ju 2 +blo "93000,134400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memWr" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*136 (CptPort +uid 21265,0 +ps "OnEdgeStrategy" +shape (Triangle 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"88600,129400,93000,130600" +st "cntIncr" +ju 2 +blo "93000,130400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "cntIncr" +t "std_ulogic" +o 6 +suid 6,0 +) +) +) +*141 (CptPort +uid 21285,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21286,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,135625,78000,136375" +) +tg (CPTG +uid 21287,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21288,0 +va (VaSet +) +xt "79000,135400,85300,136600" +st "newSample" +blo "79000,136400" +) +) +thePort (LogicalPort +decl (Decl +n "newSample" +t "std_ulogic" +o 7 +suid 7,0 +) +) +) +*142 (CptPort +uid 21289,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21290,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,139625,78000,140375" +) +tg (CPTG +uid 21291,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21292,0 +va (VaSet +) +xt "79000,139400,82400,140600" +st "clock" +blo "79000,140400" +) +) +thePort (LogicalPort +decl (Decl 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+xt "78600,144700,88300,145900" +st "blockRAMControl" +blo "78600,145700" +tm "CptNameMgr" +) +*146 (Text +uid 21302,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,145600,82200,146800" +st "I_ctly" +blo "78600,146600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 21303,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 21304,0 +text (MLText +uid 21305,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,139800,78000,139800" +) +header "" +) +elements [ +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*147 (SaComponent +uid 21330,0 +optionalChildren [ +*148 (CptPort +uid 21306,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21307,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,159625,78000,160375" +) +tg (CPTG +uid 21308,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21309,0 +va (VaSet +) +xt "79000,159400,80900,160600" +st "en" +blo "79000,160400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t 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"77250,155625,78000,156375" +) +tg (CPTG +uid 21328,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21329,0 +va (VaSet +) +xt "79000,155400,86100,156600" +st "patternSize" +blo "79000,156400" +) +) +thePort (LogicalPort +decl (Decl +n "patternSize" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 6 +suid 6,0 +) +) +) +] +shape (Rectangle +uid 21331,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "78000,152000,94000,168000" +) +oxt "38000,13000,54000,29000" +ttg (MlTextGroup +uid 21332,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*154 (Text +uid 21333,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,167800,87000,169000" +st "SystemOnChip" +blo "78600,168800" +tm "BdLibraryNameMgr" +) +*155 (Text +uid 21334,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,168700,93200,169900" +st "blockRAMAddressCounter" +blo "78600,169700" +tm "CptNameMgr" +) +*156 (Text +uid 21335,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,169600,83100,170800" +st "I_addrx" +blo "78600,170600" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 21336,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 21337,0 +text (MLText +uid 21338,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,171600,100900,172600" +st "addressBitNb = patternAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*157 (SaComponent +uid 21375,0 +optionalChildren [ +*158 (CptPort +uid 21339,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21340,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,183625,94750,184375" +) +tg (CPTG +uid 21341,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21342,0 +va (VaSet +) +xt "88600,183400,93000,184600" +st "memWr" +ju 2 +blo "93000,184400" +) +) +thePort (LogicalPort +m 1 +decl (Decl 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(Wire +uid 1732,0 +shape (OrthoPolyLine +uid 1733,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "62000,70000,77250,70000" +pts [ +"62000,70000" +"77250,70000" +] +) +start &204 +end &105 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1734,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1735,0 +va (VaSet +font "Verdana,12,0" +) +xt "72250,68600,77250,70000" +st "dataIn" +blo "72250,69800" +tm "WireNameMgr" +) +) +on &46 +) +*210 (Wire +uid 1738,0 +shape (OrthoPolyLine +uid 1739,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "66000,72000,77250,72000" +pts [ +"66000,72000" +"77250,72000" +] +) +start &207 +end &106 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1740,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1741,0 +va (VaSet +font "Verdana,12,0" +) +xt "71250,70600,77250,72000" +st "dataOut" +blo "71250,71800" +tm "WireNameMgr" +) +) +on &22 +) +*211 (Wire +uid 1744,0 +shape (OrthoPolyLine +uid 1745,0 +va (VaSet +vasetType 3 +) +xt "74000,84000,77250,84000" +pts [ +"74000,84000" +"77250,84000" +] +) +end &109 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1750,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1751,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,82600,78100,84000" +st "reset" +blo "74000,83800" +tm "WireNameMgr" +) +) +on &13 +) +*212 (Wire +uid 1752,0 +shape (OrthoPolyLine +uid 1753,0 +va (VaSet +vasetType 3 +) +xt "74000,82000,77250,82000" +pts [ +"74000,82000" +"77250,82000" +] +) +end &108 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1758,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1759,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,80600,77800,82000" +st "clock" +blo "74000,81800" +tm "WireNameMgr" +) +) +on &12 +) +*213 (Wire +uid 1778,0 +shape (OrthoPolyLine +uid 1779,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "94750,70000,109250,70000" +pts [ +"94750,70000" +"109250,70000" +] +) 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2647,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,160600,109200,162000" +st "memEnX" +blo "103000,161800" +tm "WireNameMgr" +) +) +on &27 +) +*218 (Wire +uid 2648,0 +shape (OrthoPolyLine +uid 2649,0 +va (VaSet +vasetType 3 +) +xt "70000,184000,77250,184000" +pts [ +"70000,184000" +"77250,184000" +] +) +end &161 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2654,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2655,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,182600,79800,184000" +st "updatePattern" +blo "69000,183800" +tm "WireNameMgr" +) +) +on &20 +) +*219 (Wire +uid 2772,0 +shape (OrthoPolyLine +uid 2773,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "94750,156000,109250,156000" +pts [ +"94750,156000" +"109250,156000" +] +) +start &152 +end &177 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2774,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2775,0 +va (VaSet +font "Verdana,12,0" +) +xt "105000,154600,109500,156000" +st "addrX" +blo "105000,155800" +tm "WireNameMgr" +) +) +on &24 +) +*220 (Wire +uid 2778,0 +shape (OrthoPolyLine +uid 2779,0 +va (VaSet +vasetType 3 +) +xt "74000,166000,77250,166000" +pts [ +"74000,166000" +"77250,166000" +] +) +end &150 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2784,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2785,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,164600,78100,166000" +st "reset" +blo "74000,165800" +tm "WireNameMgr" +) +) +on &13 +) +*221 (Wire +uid 2786,0 +shape (OrthoPolyLine +uid 2787,0 +va (VaSet +vasetType 3 +) +xt "74000,164000,77250,164000" +pts [ +"74000,164000" +"77250,164000" +] +) +end &149 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2792,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2793,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,162600,77800,164000" +st "clock" +blo "74000,163800" +tm "WireNameMgr" +) +) +on &12 +) +*222 (Wire +uid 2844,0 +shape (OrthoPolyLine +uid 2845,0 +va (VaSet +vasetType 3 +) +xt "72000,160000,98000,180000" +pts [ +"94750,180000" +"98000,180000" +"98000,174000" +"72000,174000" +"72000,160000" +"77250,160000" +] +) +start &163 +end &148 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2846,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2847,0 +va (VaSet +font "Verdana,12,0" +) +xt "72000,158600,77900,160000" +st "cntIncrX" +blo "72000,159800" +tm "WireNameMgr" +) +) +on &25 +) +*223 (Wire +uid 2860,0 +shape (OrthoPolyLine +uid 2861,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "66000,44000,77250,44000" +pts [ +"66000,44000" +"77250,44000" +] +) +start &208 +end &93 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2862,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2863,0 +va (VaSet +font "Verdana,12,0" +) +xt "71250,42600,77250,44000" +st "dataOut" +blo "71250,43800" +tm "WireNameMgr" +) +) +on &22 +) +*224 (Wire +uid 2866,0 +shape (OrthoPolyLine +uid 2867,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "70000,156000,77250,156000" +pts [ +"70000,156000" +"77250,156000" +] +) +end &153 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2872,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2873,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,154600,77900,156000" +st "patternSize" +blo "69000,155800" +tm "WireNameMgr" +) +) +on &21 +) +*225 (Wire +uid 2919,0 +shape (OrthoPolyLine +uid 2920,0 +va (VaSet +vasetType 3 +) +xt "70000,186000,77250,186000" +pts [ +"77250,186000" +"70000,186000" +] +) +start &164 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2925,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2926,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,184600,78600,186000" +st "newPolynom" +blo "69000,185800" +tm "WireNameMgr" +) +) +on &14 +) +*226 (Wire +uid 2996,0 +shape (OrthoPolyLine +uid 2997,0 +va (VaSet +vasetType 3 +) +xt "74000,192000,77250,192000" +pts [ +"74000,192000" +"77250,192000" +] +) +end &166 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3002,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3003,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,190600,78100,192000" +st "reset" +blo "74000,191800" +tm "WireNameMgr" +) +) +on &13 +) +*227 (Wire +uid 3004,0 +shape (OrthoPolyLine +uid 3005,0 +va (VaSet +vasetType 3 +) +xt "74000,190000,77250,190000" +pts [ +"74000,190000" +"77250,190000" +] +) +end &165 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3010,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3011,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,188600,77800,190000" +st "clock" +blo "74000,189800" +tm "WireNameMgr" +) +) +on &12 +) +*228 (Wire +uid 3094,0 +shape (OrthoPolyLine +uid 3095,0 +va (VaSet +vasetType 3 +) +xt "70000,158000,77250,158000" +pts [ +"70000,158000" +"77250,158000" +] +) +end &151 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3100,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3101,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,156600,79800,158000" +st "updatePattern" +blo "69000,157800" +tm "WireNameMgr" +) +) +on &20 +) +*229 (Wire +uid 3146,0 +shape (OrthoPolyLine +uid 3147,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "126750,154000,134000,154000" +pts [ +"126750,154000" +"134000,154000" +] +) +start &172 +end &42 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3150,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3151,0 +va (VaSet +font "Verdana,12,0" +) +xt "128000,152600,132600,154000" +st "memX" +blo "128000,153800" +tm "WireNameMgr" +) +) +on &28 +) +*230 (Wire +uid 3751,0 +shape (OrthoPolyLine +uid 3752,0 +va (VaSet +vasetType 3 +) +xt "106000,130000,109250,130000" +pts [ +"106000,130000" +"109250,130000" +] +) +end &186 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3755,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3756,0 +va (VaSet +font "Verdana,12,0" +) +xt "106000,128600,110100,130000" +st "reset" +blo "106000,129800" +tm "WireNameMgr" +) +) +on &13 +) +*231 (Wire +uid 3757,0 +shape (OrthoPolyLine +uid 3758,0 +va (VaSet +vasetType 3 +) +xt "106000,128000,109250,128000" +pts [ +"106000,128000" +"109250,128000" +] +) +end &185 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3761,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3762,0 +va (VaSet +font "Verdana,12,0" +) +xt "106000,126600,109800,128000" +st "clock" +blo "106000,127800" +tm "WireNameMgr" +) +) +on &12 +) +*232 (Wire +uid 3763,0 +shape (OrthoPolyLine +uid 3764,0 +va (VaSet +vasetType 3 +) +xt "70000,134000,77250,134000" +pts [ +"70000,134000" +"77250,134000" +] +) +end &138 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3767,0 +ps "ConnStartEndStrategy" +stg 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b/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer@registers/symbol.sb new file mode 100644 index 0000000..6efdcca --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip/hds/ahb@beamer@registers/symbol.sb @@ -0,0 +1,2501 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2028,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 201,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +decl (Decl +n "hClk" +t "std_ulogic" +o 8 +suid 1,0 +) +) +uid 206,0 +) +*3 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 9 +suid 11,0 +) +) +uid 207,0 +) +*4 (LogPort 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+bg "0,0,32768" +) +xt "72200,48500,72200,48500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +uid 14,0 +shape (Rectangle +uid 15,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "89000,44000,93000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 16,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "89200,44500,89200,44500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +uid 17,0 +shape (Rectangle +uid 18,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "72000,46000,89000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 19,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "72200,46500,72200,46500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText 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"PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 128,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "93000,2300,96600,3700" +st "outY" +blo "93000,3500" +tm "WireNameMgr" +) +) +) +*15 (Net +uid 135,0 +decl (Decl +n "outY" +t "std_ulogic" +o 4 +suid 5,0 +) +declText (MLText +uid 136,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,31400,13300,32400" +st "outY : std_ulogic" +) +) +*16 (PortIoIn +uid 5080,0 +shape (CompositeShape +uid 5081,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5082,0 +sl 0 +ro 90 +xt "90500,6625,92000,7375" +) +(Line +uid 5083,0 +sl 0 +ro 90 +xt "90000,7000,90500,7000" +pts [ +"90500,7000" +"90000,7000" +] +) +] +) +tg (WTG +uid 5084,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5085,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "93000,6300,99900,7700" +st "selSinCos" +blo "93000,7500" +tm "WireNameMgr" +) +) +) +*17 (Net +uid 6503,0 +decl (Decl +n "selSinCos" +t "std_ulogic" +o 6 +suid 62,0 +) +declText (MLText +uid 6504,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,33000,13800,34000" +st "selSinCos : std_ulogic" +) +) +*18 (PortIoIn +uid 13128,0 +shape (CompositeShape +uid 13129,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 13130,0 +sl 0 +ro 270 +xt "16000,625,17500,1375" +) +(Line +uid 13131,0 +sl 0 +ro 270 +xt "17500,1000,18000,1000" +pts [ +"17500,1000" +"18000,1000" +] +) +] +) +tg (WTG +uid 13132,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 13133,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "11500,500,15000,1900" +st "apbi" +ju 2 +blo "15000,1700" +tm "WireNameMgr" +) +) +) +*19 (Net +uid 13140,0 +decl (Decl +n "apbi" +t "apb_slv_in_type" +o 2 +suid 71,0 +) +declText (MLText +uid 13141,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,29800,15800,30800" +st "apbi : apb_slv_in_type" +) +) +*20 (PortIoOut +uid 13373,0 +shape (CompositeShape +uid 13374,0 +va (VaSet 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(WTG +uid 13626,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 13627,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "1300,14500,7000,15900" +st "reset_n" +ju 2 +blo "7000,15700" +tm "WireNameMgr" +) +) +) +*23 (Net +uid 13634,0 +decl (Decl +n "reset_n" +t "std_ulogic" +o 3 +suid 73,0 +) +declText (MLText +uid 13635,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,30600,13600,31600" +st "reset_n : std_ulogic" +) +) +*24 (Net +uid 14876,0 +decl (Decl +n "clock" +t "std_ulogic" +o 7 +suid 74,0 +) +declText (MLText +uid 14877,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,33800,13200,34800" +st "clock : std_ulogic" +) +) +*25 (PortIoIn +uid 14884,0 +shape (CompositeShape +uid 14885,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14886,0 +sl 0 +ro 270 +xt "16000,10625,17500,11375" +) +(Line +uid 14887,0 +sl 0 +ro 270 +xt "17500,11000,18000,11000" +pts [ +"17500,11000" +"18000,11000" +] +) +] +) +tg (WTG +uid 14888,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14889,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "11200,10300,15000,11700" +st "clock" +ju 2 +blo "15000,11500" +tm "WireNameMgr" +) +) +) +*26 (HdlText +uid 14916,0 +optionalChildren [ +*27 (EmbeddedText +uid 14921,0 +commentText (CommentText +uid 14922,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 14923,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "18000,14000,26000,16000" +) +oxt "0,0,18000,5000" +text (MLText +uid 14924,0 +va (VaSet +) +xt "18200,14200,26100,15400" +st " +reset <= not reset_n; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 8000 +) +) +) +] +shape (Rectangle +uid 14917,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "18000,13000,26000,17000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 14918,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*28 (Text +uid 14919,0 +va (VaSet +) +xt "18400,17000,21000,18200" +st "eb1" +blo "18400,18000" +tm "HdlTextNameMgr" +) +*29 (Text +uid 14920,0 +va (VaSet +) +xt "18400,18000,19800,19200" +st "1" +blo "18400,19000" +tm "HdlTextNumberMgr" +) +] +) +) +*30 (Net +uid 14974,0 +decl (Decl +n "reset" +t "std_ulogic" +o 9 +suid 75,0 +) +declText (MLText +uid 14975,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,39800,16400,40800" +st "SIGNAL reset : std_ulogic" +) +) +*31 (Net +uid 15201,0 +decl (Decl +n "run" +t "std_ulogic" +o 10 +suid 76,0 +) +declText (MLText +uid 15202,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,40600,16300,41600" +st "SIGNAL run : std_ulogic" +) +) +*32 (Net +uid 15207,0 +decl (Decl +n "interpolateLin" +t "std_ulogic" +o 11 +suid 77,0 +) +declText (MLText +uid 15208,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,41400,17100,42400" +st "SIGNAL interpolateLin : std_ulogic" +) +) +*33 (Net +uid 15213,0 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(updatePeriodBitNb-1 DOWNTO 0)" +o 12 +suid 78,0 +) +declText (MLText +uid 15214,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,42200,31600,43200" +st "SIGNAL updatePeriod : unsigned(updatePeriodBitNb-1 DOWNTO 0)" +) +) +*34 (Net +uid 15462,0 +decl (Decl +n "memX" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 13 +suid 79,0 +) +declText (MLText +uid 15463,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,43000,31700,44000" +st "SIGNAL memX : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*35 (Net +uid 15468,0 +decl (Decl +n "memY" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 14 +suid 80,0 +) +declText (MLText +uid 15469,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,43800,31700,44800" +st "SIGNAL memY : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*36 (Net +uid 15574,0 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO testOutBitNb)" +o 8 +suid 81,0 +) +declText (MLText +uid 15575,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,34600,25000,35600" +st "testOut : std_ulogic_vector(1 TO testOutBitNb)" +) +) +*37 (PortIoOut +uid 15582,0 +shape (CompositeShape +uid 15583,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 15584,0 +sl 0 +ro 270 +xt "50500,-7375,52000,-6625" +) +(Line +uid 15585,0 +sl 0 +ro 270 +xt "50000,-7000,50500,-7000" +pts [ +"50000,-7000" +"50500,-7000" +] +) +] +) +tg (WTG +uid 15586,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15587,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "53000,-7700,73900,-6300" +st "testOut : (1 TO testOutBitNb)" +blo "53000,-6500" +tm "WireNameMgr" +) +) +) +*38 (HdlText +uid 16006,0 +optionalChildren [ +*39 (EmbeddedText +uid 16011,0 +commentText (CommentText +uid 16012,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 16013,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "50000,-20000,66000,-10000" +) +oxt "0,0,18000,5000" +text (MLText +uid 16014,0 +va (VaSet +) +xt "50200,-19800,65500,-10200" +st " +--process +--begin +-- newPolynom <= '0'; +-- for index in 1 to 2**4-1 loop +-- wait until rising_edge(clock); +-- end loop; +-- newPolynom <= '1'; +-- wait until rising_edge(clock); +--end process; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 16007,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "50000,-21000,66000,-9000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 16008,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*40 (Text +uid 16009,0 +va (VaSet +) +xt "50400,-9000,53000,-7800" +st "eb2" +blo "50400,-8000" +tm "HdlTextNameMgr" +) +*41 (Text +uid 16010,0 +va (VaSet +) +xt "50400,-8000,51800,-6800" +st "2" +blo "50400,-7000" +tm "HdlTextNumberMgr" +) +] +) +) +*42 (SaComponent +uid 16094,0 +optionalChildren [ +*43 (CptPort +uid 16050,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16051,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "65250,14625,66000,15375" +) +tg (CPTG +uid 16052,0 +ps "CptPortTextPlaceStrategy" +stg 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(Text +uid 737,0 +va (VaSet +) +xt "248200,116400,256000,117600" +st "unsignedOut" +ju 2 +blo "256000,117400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "unsignedOut" +t "unsigned" +b "(bitNb-1 DOWNTO 0)" +o 1 +) +) +) +*58 (CptPort +uid 738,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 739,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "240250,116625,241000,117375" +) +tg (CPTG +uid 740,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 741,0 +va (VaSet +) +xt "242000,116400,247100,117600" +st "signedIn" +blo "242000,117400" +) +) +thePort (LogicalPort +decl (Decl +n "signedIn" +t "signed" +b "(bitNb-1 DOWNTO 0)" +o 2 +) +) +) +] +shape (Rectangle +uid 726,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "241000,113000,257000,121000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 727,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*59 (Text +uid 728,0 +va (VaSet +) +xt "241600,121800,245900,123000" +st "Curves" +blo "241600,122800" +tm "BdLibraryNameMgr" +) +*60 (Text +uid 729,0 +va (VaSet +) +xt "241600,122800,251800,124000" +st "offsetToUnsigned" +blo "241600,123800" +tm "CptNameMgr" +) +*61 (Text +uid 730,0 +va (VaSet +) +xt "241600,123800,244200,125000" +st "I14" +blo "241600,124800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 731,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 732,0 +text (MLText +uid 733,0 +va (VaSet +font "Verdana,8,0" +) +xt "241000,124800,256300,125800" +st "bitNb = signalBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "bitNb" +type "positive" +value "signalBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*62 (SaComponent +uid 742,0 +optionalChildren [ +*63 (CptPort +uid 751,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 752,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "264250,120625,265000,121375" +) +tg (CPTG +uid 753,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 754,0 +va (VaSet +) +xt "266000,120400,269400,121600" +st "clock" +blo "266000,121400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 3 +) +) +) +*64 (CptPort +uid 755,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 756,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "264250,116625,265000,117375" +) +tg (CPTG +uid 757,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 758,0 +va (VaSet +) +xt "266000,116400,272200,117600" +st "parallelIn" +blo "266000,117400" +) +) +thePort (LogicalPort +decl (Decl +n "parallelIn" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 2 +) +) +) +*65 (CptPort +uid 759,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 760,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "281000,116625,281750,117375" +) +tg (CPTG +uid 761,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 762,0 +va (VaSet +) +xt "274601,116400,280001,117600" +st "serialOut" +ju 2 +blo "280001,117400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "serialOut" +t "std_ulogic" +o 1 +) +) +) +*66 (CptPort +uid 763,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 764,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "264250,122625,265000,123375" +) +tg (CPTG +uid 765,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 766,0 +va (VaSet +) +xt "266000,122400,269300,123600" +st "reset" +blo "266000,123400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 4 +) +) +) +] +shape (Rectangle +uid 743,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "265000,113000,281000,125000" +) +oxt "114000,86000,130000,98000" +ttg (MlTextGroup +uid 744,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*67 (Text +uid 745,0 +va (VaSet +) +xt "265600,124800,269900,126000" +st "Curves" +blo "265600,125800" +tm "BdLibraryNameMgr" +) +*68 (Text +uid 746,0 +va (VaSet +) +xt "265600,125800,268700,127000" +st "DAC" +blo "265600,126800" +tm "CptNameMgr" +) +*69 (Text +uid 747,0 +va (VaSet +) +xt "265600,126800,267500,128000" +st "I1" +blo "265600,127800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 748,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 749,0 +text (MLText +uid 750,0 +va (VaSet +font "Verdana,8,0" +) +xt "265000,128600,283100,129600" +st "signalBitNb = signalBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*70 (Net +uid 865,0 +decl (Decl +n "samplesY" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 69 +suid 22,0 +) +declText (MLText +uid 866,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,71500,240800,72500" +st "SIGNAL samplesY : signed(signalBitNb-1 DOWNTO 0)" +) +) +*71 (Net +uid 867,0 +decl (Decl +n "sampleY1" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 62 +suid 23,0 +) +declText (MLText +uid 868,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,65200,240900,66200" +st "SIGNAL sampleY1 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*72 (Net +uid 869,0 +decl (Decl +n "sampleY2" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 63 +suid 24,0 +) +declText (MLText +uid 870,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,66100,240900,67100" +st "SIGNAL sampleY2 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*73 (Net +uid 871,0 +decl (Decl +n "sampleY3" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 64 +suid 25,0 +) +declText (MLText +uid 872,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,67000,240900,68000" +st "SIGNAL sampleY3 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*74 (Net +uid 873,0 +decl (Decl +n "sampleY4" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 65 +suid 26,0 +) +declText (MLText +uid 874,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,67900,240900,68900" +st "SIGNAL sampleY4 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*75 (Net +uid 875,0 +decl (Decl +n "aY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 22 +suid 27,0 +) +declText (MLText +uid 876,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,29200,239500,30200" +st "SIGNAL aY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*76 (Net +uid 877,0 +decl (Decl +n "bY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 28 +suid 28,0 +) +declText (MLText +uid 878,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,34600,239500,35600" +st "SIGNAL bY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*77 (Net +uid 879,0 +decl (Decl +n "cY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 30 +suid 29,0 +) +declText (MLText +uid 880,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,36400,239400,37400" +st "SIGNAL cY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*78 (Net +uid 881,0 +decl (Decl +n "dY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 36 +suid 30,0 +) +declText (MLText +uid 882,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,41800,239500,42800" +st "SIGNAL dY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*79 (Net +uid 883,0 +decl (Decl +n "sampleY" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 61 +suid 31,0 +) +declText (MLText +uid 884,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,64300,240700,65300" +st "SIGNAL sampleY : signed(signalBitNb-1 DOWNTO 0)" +) +) +*80 (Net +uid 885,0 +decl (Decl +n "unsignedY" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 80 +suid 32,0 +) +declText (MLText +uid 886,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,81400,241800,82400" +st "SIGNAL unsignedY : unsigned(signalBitNb-1 DOWNTO 0)" +) +) +*81 (Net +uid 990,0 +decl (Decl +n "selControl" +t "std_ulogic" +o 71 +suid 33,0 +) +declText (MLText +uid 991,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,73300,230400,74300" +st "SIGNAL selControl : std_ulogic" +) +) +*82 (Net +uid 1047,0 +decl (Decl +n "selSize" +t "std_ulogic" +o 72 +suid 34,0 +) +declText (MLText +uid 1048,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,74200,230000,75200" +st "SIGNAL selSize : std_ulogic" +) +) +*83 (Net +uid 1055,0 +decl (Decl +n "selSpeed" +t "std_ulogic" +o 73 +suid 35,0 +) +declText (MLText +uid 1056,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,75100,230600,76100" +st "SIGNAL selSpeed : std_ulogic" +) +) +*84 (Net +uid 1063,0 +decl (Decl +n "selX" +t "std_ulogic" +o 74 +suid 36,0 +) +declText (MLText +uid 1064,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,76000,229800,77000" +st "SIGNAL selX : std_ulogic" +) +) +*85 (Net +uid 1071,0 +decl (Decl +n "selY" +t "std_ulogic" +o 75 +suid 37,0 +) +declText (MLText +uid 1072,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,76900,229800,77900" +st "SIGNAL selY : std_ulogic" +) +) +*86 (Net +uid 1348,0 +decl (Decl +n "run" +t "std_ulogic" +o 55 +suid 38,0 +) +declText (MLText +uid 1349,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,58900,229800,59900" +st "SIGNAL run : std_ulogic" +) +) +*87 (Net +uid 1356,0 +decl (Decl +n "updatePattern" +t "std_ulogic" +o 81 +suid 39,0 +) +declText (MLText +uid 1357,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,82300,231200,83300" +st "SIGNAL updatePattern : std_ulogic" +) +) +*88 (Net +uid 1470,0 +decl (Decl +n "patternSize" +t "unsigned" +b "(dataBitNb/2-1 DOWNTO 0)" +o 53 +suid 40,0 +) +declText (MLText +uid 1471,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,57100,242000,58100" +st "SIGNAL patternSize : unsigned(dataBitNb/2-1 DOWNTO 0)" +) +) +*89 (PortIoIn +uid 1565,0 +shape (CompositeShape +uid 1566,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1567,0 +sl 0 +ro 270 +xt "17000,9625,18500,10375" +) +(Line +uid 1568,0 +sl 0 +ro 270 +xt "18500,10000,19000,10000" +pts [ +"18500,10000" +"19000,10000" +] +) +] +) +tg (WTG +uid 1569,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1570,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-7800,9300,16000,10700" +st "dataIn : (dataBitNb-1 DOWNTO 0)" +ju 2 +blo "16000,10500" +tm "WireNameMgr" +) +) +) +*90 (PortIoOut +uid 1577,0 +shape (CompositeShape +uid 1578,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1579,0 +sl 0 +ro 90 +xt "17000,3625,18500,4375" +) +(Line +uid 1580,0 +sl 0 +ro 90 +xt "18500,4000,19000,4000" +pts [ +"19000,4000" +"18500,4000" +] +) +] +) +tg (WTG +uid 1581,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1582,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "-8800,3300,16000,4700" +st "dataOut : (dataBitNb-1 DOWNTO 0)" +ju 2 +blo "16000,4500" +tm "WireNameMgr" +) +) +) +*91 (Net +uid 1589,0 +decl (Decl +n "dataOut" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 41,0 +) +declText (MLText +uid 1590,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,11200,240700,12200" +st "dataOut : std_logic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*92 (Net +uid 1776,0 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 82 +suid 42,0 +) +declText (MLText +uid 1777,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,83200,241600,84200" +st "SIGNAL updatePeriod : unsigned(dataBitNb-1 DOWNTO 0)" +) +) +*93 (SaComponent +uid 1816,0 +optionalChildren [ +*94 (CptPort +uid 1784,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1785,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91000,67625,91750,68375" +) +tg (CPTG +uid 1786,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1787,0 +va (VaSet +) +xt "82000,67400,90000,68600" +st "updatePeriod" +ju 2 +blo "90000,68400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 1 +) +) +) +*95 (CptPort +uid 1788,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1789,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,67625,75000,68375" +) +tg (CPTG +uid 1790,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1791,0 +va (VaSet +) +xt "76000,67400,80000,68600" +st "dataIn" +blo "76000,68400" +) +) +thePort (LogicalPort +decl (Decl +n "dataIn" +t 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"OnEdgeStrategy" +shape (Triangle +uid 1801,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,77625,75000,78375" +) +tg (CPTG +uid 1802,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1803,0 +va (VaSet +) +xt "76000,77400,77900,78600" +st "en" +blo "76000,78400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 5 +) +) +) +*99 (CptPort +uid 1804,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1805,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,81625,75000,82375" +) +tg (CPTG +uid 1806,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1807,0 +va (VaSet +) +xt "76000,81400,79400,82600" +st "clock" +blo "76000,82400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 6 +) +) +) +*100 (CptPort +uid 1808,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1809,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,83625,75000,84375" +) +tg (CPTG +uid 1810,0 +ps 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"214000,48100,231200,49100" +st "SIGNAL memEnX : std_ulogic" +) +) +*129 (HdlText +uid 3135,0 +optionalChildren [ +*130 (EmbeddedText +uid 3140,0 +commentText (CommentText +uid 3141,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3142,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,152000,146000,156000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3143,0 +va (VaSet +) +xt "132200,152200,144900,155800" +st " +samplesX <= cosine when selSinCos = '1' + else signed(memX); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3136,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,150000,147000,158000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3137,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*131 (Text +uid 3138,0 +va (VaSet +) +xt "131400,158000,134000,159200" +st "eb2" +blo "131400,159000" +tm "HdlTextNameMgr" +) +*132 (Text +uid 3139,0 +va (VaSet +) +xt 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(Text +uid 3627,0 +va (VaSet +) +xt "107600,76800,120900,78000" +st "periphSpeedController" +blo "107600,77800" +tm "CptNameMgr" +) +*152 (Text +uid 3628,0 +va (VaSet +) +xt "107600,77800,110200,79000" +st "I15" +blo "107600,78800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3629,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3630,0 +text (MLText +uid 3631,0 +va (VaSet +font "Verdana,8,0" +) +xt "107000,79600,123600,80600" +st "dataBitNb = dataBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*153 (SaComponent +uid 3681,0 +optionalChildren [ +*154 (CptPort +uid 3690,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3691,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,109625,75000,110375" +) +tg (CPTG +uid 3692,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3693,0 +va (VaSet +) +xt "76000,109400,77900,110600" +st "en" +blo "76000,110400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 1 +) +) +) +*155 (CptPort +uid 3694,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3695,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,113625,75000,114375" +) +tg (CPTG +uid 3696,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3697,0 +va (VaSet +) +xt "76000,113400,79400,114600" +st "clock" +blo "76000,114400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*156 (CptPort +uid 3698,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3699,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,115625,75000,116375" +) +tg (CPTG +uid 3700,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3701,0 +va (VaSet +) +xt "76000,115400,79300,116600" +st "reset" +blo "76000,116400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +) +) +) +*157 (CptPort +uid 3702,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3703,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,107625,75000,108375" +) +tg (CPTG +uid 3704,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3705,0 +va (VaSet +) +xt "76000,107400,82500,108600" +st "updateMem" +blo "76000,108400" +) +) +thePort (LogicalPort +decl (Decl +n "updateMem" +t "std_ulogic" +o 4 +) +) +) +*158 (CptPort +uid 3706,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3707,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91000,105625,91750,106375" +) +tg (CPTG +uid 3708,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3709,0 +va (VaSet +) +xt "87100,105400,90000,106600" +st "addr" +ju 2 +blo "90000,106400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 5 +) +) +) +*159 (CptPort +uid 3710,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3711,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,105625,75000,106375" +) +tg (CPTG +uid 3712,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3713,0 +va (VaSet +) +xt "76000,105400,83100,106600" +st "patternSize" +blo "76000,106400" +) +) +thePort (LogicalPort +decl (Decl +n "patternSize" +t "unsigned" +b "(patternSizeBitNb-1 DOWNTO 0)" +o 6 +) +) +) +] +shape (Rectangle +uid 3682,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "75000,102000,91000,118000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3683,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*160 (Text +uid 3684,0 +va (VaSet +) +xt "75600,117800,79900,119000" +st "Curves" +blo "75600,118800" +tm "BdLibraryNameMgr" +) +*161 (Text +uid 3685,0 +va (VaSet +) +xt "75600,118800,91000,120000" +st "blockRAMAddressCounter" +blo "75600,119800" +tm "CptNameMgr" +) +*162 (Text +uid 3686,0 +va (VaSet +) +xt "75600,119800,78200,121000" +st "I20" +blo "75600,120800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3687,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3688,0 +text (MLText +uid 3689,0 +va (VaSet +font "Verdana,8,0" +) +xt "75000,121600,98800,123600" +st "addressBitNb = patternAddressBitNb ( positive ) +patternSizeBitNb = dataBitNb/2 ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +(GiElement +name "patternSizeBitNb" +type "positive" +value "dataBitNb/2" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*163 (Net +uid 3827,0 +decl (Decl +n "cntIncrY" +t "std_ulogic" +o 32 +suid 49,0 +) +declText (MLText +uid 3828,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,38200,230200,39200" +st "SIGNAL cntIncrY : std_ulogic" +) +) +*164 (Net +uid 3890,0 +decl (Decl +n "addrY" +t "unsigned" +b "(patternAddressBitNb-1 DOWNTO 0)" +o 25 +suid 50,0 +) +declText (MLText +uid 3891,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,31900,244900,32900" +st "SIGNAL addrY : unsigned(patternAddressBitNb-1 DOWNTO 0)" +) +) +*165 (Net +uid 3892,0 +decl (Decl +n "memWrY" +t "std_ulogic" +o 47 +suid 51,0 +) +declText (MLText +uid 3893,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,51700,231300,52700" +st "SIGNAL memWrY : std_ulogic" +) +) +*166 (Net +uid 3894,0 +decl (Decl +n "memEnY" +t "std_ulogic" +o 44 +suid 52,0 +) +declText (MLText +uid 3895,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,49000,231200,50000" +st "SIGNAL memEnY : std_ulogic" +) +) +*167 (HdlText +uid 3896,0 +optionalChildren [ +*168 (EmbeddedText +uid 3901,0 +commentText (CommentText +uid 3902,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3903,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,115000,146000,119000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3904,0 +va (VaSet +) +xt "132200,115200,144900,118800" +st " +samplesY <= sine when selSinCos = '1' + else signed(memY); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3897,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,113000,147000,121000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3898,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*169 (Text +uid 3899,0 +va (VaSet +) +xt "131400,121000,134000,122200" +st "eb1" +blo "131400,122000" +tm "HdlTextNameMgr" +) +*170 (Text +uid 3900,0 +va (VaSet +) +xt "131400,122000,132800,123200" +st "1" +blo "131400,123000" +tm "HdlTextNumberMgr" +) +] +) +) +*171 (Net +uid 3913,0 +decl (Decl +n "memY" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 50 +suid 53,0 +) +declText (MLText +uid 3914,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,54400,244700,55400" +st "SIGNAL memY : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*172 (PortIoOut +uid 4041,0 +shape (CompositeShape +uid 4042,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4043,0 +sl 0 +ro 270 +xt "289500,5625,291000,6375" +) +(Line +uid 4044,0 +sl 0 +ro 270 +xt "289000,6000,289500,6000" +pts [ +"289000,6000" +"289500,6000" +] +) +] +) +tg (WTG +uid 4045,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4046,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "292000,5300,305600,6700" +st "testOut : (1 TO 16)" +blo "292000,6500" +tm "WireNameMgr" +) +) +) +*173 (Net +uid 4053,0 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO 16)" +o 12 +suid 54,0 +) +declText (MLText +uid 4054,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,12100,234500,13100" +st "testOut : std_ulogic_vector(1 TO 16)" +) +) +*174 (HdlText +uid 4055,0 +optionalChildren [ +*175 (EmbeddedText +uid 4060,0 +commentText (CommentText +uid 4061,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4062,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "266000,5000,280000,27000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4063,0 +va (VaSet +) +xt "266200,5200,278400,26800" +st " +testout(1) <= run; +testout(2) <= updatePattern; +testout(3) <= interpolationEnable; +testout(4) <= newPolynom; +testout(5) <= selSinCos; +testout(6) <= cs; +testout(7) <= rd; +testout(8) <= wrH; +testout(9) <= wrL; +testout(10) <= addrReg(1); +testout(11) <= dataInReg(0); +--testout(10) <= selControl; +--testout(11) <= selSize; +testout(12) <= selSpeed; +testout(13) <= selX; +testout(14) <= selY; +testout(15) <= cntIncrX; +testout(16) <= cntIncrY; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 22000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4056,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "265000,4000,281000,28000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4057,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*176 (Text +uid 4058,0 +va (VaSet +) +xt "265400,28000,268000,29200" +st "eb3" +blo "265400,29000" +tm "HdlTextNameMgr" +) +*177 (Text +uid 4059,0 +va (VaSet +) +xt "265400,29000,266800,30200" +st "3" +blo "265400,30000" +tm "HdlTextNumberMgr" +) +] +) +) +*178 (SaComponent +uid 4245,0 +optionalChildren [ +*179 (CptPort +uid 4225,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4226,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,57625,43750,58375" +) +tg (CPTG +uid 4227,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4228,0 +va (VaSet +) +xt "35400,57400,42000,58600" +st "writePulse" +ju 2 +blo "42000,58400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writePulse" +t "std_ulogic" +o 1 +) +) +) +*180 (CptPort +uid 4229,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4230,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,57625,27000,58375" +) +tg (CPTG +uid 4231,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4232,0 +va (VaSet +) +xt "28000,57400,31100,58600" +st "write" +blo "28000,58400" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 2 +) +) +) +*181 (CptPort +uid 4233,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4234,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,59625,27000,60375" +) +tg (CPTG +uid 4235,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4236,0 +va (VaSet +) +xt "28000,59400,34700,60600" +st "chipSelect" +blo "28000,60400" +) +) +thePort (LogicalPort +decl (Decl +n "chipSelect" +t "std_ulogic" +o 3 +) +) +) +*182 (CptPort +uid 4237,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4238,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,63625,27000,64375" +) +tg (CPTG +uid 4239,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4240,0 +va (VaSet +) +xt "28000,63400,31400,64600" +st "clock" +blo "28000,64400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 4 +) +) +) +*183 (CptPort +uid 4241,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4242,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,65625,27000,66375" +) +tg (CPTG +uid 4243,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4244,0 +va (VaSet +) +xt "28000,65400,31300,66600" +st "reset" +blo "28000,66400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 4246,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "27000,54000,43000,68000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4247,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*184 (Text +uid 4248,0 +va (VaSet +) +xt "27600,67800,31900,69000" +st "Curves" +blo "27600,68800" +tm "BdLibraryNameMgr" +) +*185 (Text +uid 4249,0 +va (VaSet +) +xt "27600,68800,37500,70000" +st "periphWritePulse" +blo "27600,69800" +tm "CptNameMgr" +) +*186 (Text +uid 4250,0 +va (VaSet +) +xt "27600,69800,30200,71000" +st "I22" +blo "27600,70800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4251,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4252,0 +text (MLText +uid 4253,0 +va (VaSet +font "Verdana,8,0" +) +xt "-7000,45000,-7000,45000" +) +header "" +) +elements [ +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*187 (Net +uid 4290,0 +decl (Decl +n "wrHPulse" +t "std_ulogic" +o 85 +suid 55,0 +) +declText (MLText +uid 4291,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,85900,230700,86900" +st "SIGNAL wrHPulse : std_ulogic" +) +) +*188 (SaComponent +uid 4300,0 +optionalChildren [ +*189 (CptPort +uid 4309,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4310,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,79625,43750,80375" +) +tg (CPTG +uid 4311,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4312,0 +va (VaSet +) +xt "35400,79400,42000,80600" +st "writePulse" +ju 2 +blo "42000,80400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writePulse" +t "std_ulogic" +o 1 +) +) +) +*190 (CptPort +uid 4313,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4314,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,79625,27000,80375" +) +tg (CPTG +uid 4315,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4316,0 +va (VaSet +) +xt "28000,79400,31100,80600" +st "write" +blo "28000,80400" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 2 +) +) +) +*191 (CptPort +uid 4317,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4318,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,81625,27000,82375" +) +tg (CPTG +uid 4319,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4320,0 +va (VaSet +) +xt "28000,81400,34700,82600" +st "chipSelect" +blo "28000,82400" +) +) +thePort (LogicalPort +decl (Decl +n "chipSelect" +t "std_ulogic" +o 3 +) +) +) +*192 (CptPort +uid 4321,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4322,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,85625,27000,86375" +) +tg (CPTG +uid 4323,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4324,0 +va (VaSet +) +xt "28000,85400,31400,86600" +st "clock" +blo "28000,86400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 4 +) +) +) +*193 (CptPort +uid 4325,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4326,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,87625,27000,88375" +) +tg (CPTG +uid 4327,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4328,0 +va (VaSet +) +xt "28000,87400,31300,88600" +st "reset" +blo "28000,88400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 4301,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "27000,76000,43000,90000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4302,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*194 (Text +uid 4303,0 +va (VaSet +) +xt "27600,89800,31900,91000" +st "Curves" +blo "27600,90800" +tm "BdLibraryNameMgr" +) +*195 (Text +uid 4304,0 +va (VaSet +) +xt "27600,90800,37500,92000" +st "periphWritePulse" +blo "27600,91800" +tm "CptNameMgr" +) +*196 (Text +uid 4305,0 +va (VaSet +) +xt "27600,91800,30200,93000" +st "I23" +blo "27600,92800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4306,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4307,0 +text (MLText +uid 4308,0 +va (VaSet +font "Verdana,8,0" +) +xt "-7000,67000,-7000,67000" +) +header "" +) +elements [ +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*197 (Net +uid 4347,0 +decl (Decl +n "wrLPulse" +t "std_ulogic" +o 86 +suid 56,0 +) +declText (MLText +uid 4348,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,86800,230500,87800" +st "SIGNAL wrLPulse : std_ulogic" +) +) +*198 (HdlText +uid 4719,0 +optionalChildren [ +*199 (EmbeddedText +uid 4724,0 +commentText (CommentText +uid 4725,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4726,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "150000,75000,164000,77000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4727,0 +va (VaSet +) +xt "150200,75200,164000,76400" +st " +step <= to_unsigned(1, step'length); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4720,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "149000,74000,165000,78000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4721,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*200 (Text +uid 4722,0 +va (VaSet +) +xt "149400,78000,152000,79200" +st "eb4" +blo "149400,79000" +tm "HdlTextNameMgr" +) +*201 (Text +uid 4723,0 +va (VaSet +) +xt "149400,79000,150800,80200" +st "4" +blo "149400,80000" +tm "HdlTextNumberMgr" +) +] +) +) +*202 (Net +uid 4800,0 +decl (Decl +n "phase" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 54 +suid 57,0 +) +declText (MLText +uid 4801,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,58000,241400,59000" +st "SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*203 (Net +uid 4802,0 +decl (Decl +n "step" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 78 +suid 58,0 +) +declText (MLText +uid 4803,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,79600,241000,80600" +st "SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*204 (Net +uid 4858,0 +decl (Decl +n "sine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 77 +suid 59,0 +) +declText (MLText +uid 4859,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,78700,239800,79700" +st "SIGNAL sine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*205 (SaComponent +uid 4923,0 +optionalChildren [ +*206 (CptPort +uid 4903,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4904,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,89625,161000,90375" +) +tg (CPTG +uid 4905,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4906,0 +va (VaSet +) +xt "162000,89400,165400,90600" +st "clock" +blo "162000,90400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*207 (CptPort +uid 4907,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4908,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "177000,83625,177750,84375" +) +tg (CPTG +uid 4909,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4910,0 +va (VaSet +) +xt "170800,83400,176000,84600" +st "sawtooth" +ju 2 +blo "176000,84400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sawtooth" +t "unsigned" +b "(bitNb-1 DOWNTO 0)" +o 1 +) +) +) +*208 (CptPort +uid 4911,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4912,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,91625,161000,92375" +) +tg (CPTG +uid 4913,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4914,0 +va (VaSet +) +xt "162000,91400,165300,92600" +st "reset" +blo "162000,92400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +) +) +) +*209 (CptPort +uid 4915,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4916,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,83625,161000,84375" +) +tg (CPTG +uid 4917,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4918,0 +va (VaSet +) +xt "162000,83400,164900,84600" +st "step" +blo "162000,84400" +) +) +thePort (LogicalPort +decl (Decl +n "step" +t "unsigned" +b "(bitNb-1 DOWNTO 0)" +o 4 +) +) +) +*210 (CptPort +uid 4919,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4920,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,85625,161000,86375" +) +tg (CPTG +uid 4921,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4922,0 +va (VaSet +) +xt "162000,85400,163900,86600" +st "en" +blo "162000,86400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 5 +) +) +) +] +shape (Rectangle +uid 4924,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "161000,80000,177000,94000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4925,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*211 (Text +uid 4926,0 +va (VaSet +) +xt "161600,93800,165900,95000" +st "Curves" +blo "161600,94800" +tm "BdLibraryNameMgr" +) +*212 (Text +uid 4927,0 +va (VaSet +) +xt "161600,94800,169500,96000" +st "sawtoothGen" +blo "161600,95800" +tm "CptNameMgr" +) +*213 (Text +uid 4928,0 +va (VaSet +) +xt "161600,95800,164200,97000" +st "I24" +blo "161600,96800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4929,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4930,0 +text (MLText +uid 4931,0 +va (VaSet +font "Verdana,8,0" +) +xt "161000,96600,176400,97600" +st "bitNb = phaseBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "bitNb" +type "positive" +value "phaseBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*214 (PortIoIn +uid 5080,0 +shape (CompositeShape +uid 5081,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5082,0 +sl 0 +ro 270 +xt "151000,69625,152500,70375" +) +(Line +uid 5083,0 +sl 0 +ro 270 +xt "152500,70000,153000,70000" +pts [ +"152500,70000" +"153000,70000" +] +) +] +) +tg (WTG +uid 5084,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5085,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "143100,69300,150000,70700" +st "selSinCos" +ju 2 +blo "150000,70500" +tm "WireNameMgr" +) +) +) +*215 (HdlText +uid 5244,0 +optionalChildren [ +*216 (EmbeddedText +uid 5249,0 +commentText (CommentText +uid 5250,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 5251,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "162000,65000,176000,71000" +) +oxt "0,0,18000,5000" +text (MLText +uid 5252,0 +va (VaSet +) +xt "162200,65200,176100,71200" +st " +interpolationEnable <= '1' when selSinCos = '1' + else interpolationEn; +--interpolateLinear <= '1' when selSinCos = '1' +-- else interpolateLin; +interpolateLinear <= interpolateLin; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 5245,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "161000,64000,177000,72000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 5246,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*217 (Text +uid 5247,0 +va (VaSet +) +xt "161400,72000,164000,73200" +st "eb5" +blo "161400,73000" +tm "HdlTextNameMgr" +) +*218 (Text +uid 5248,0 +va (VaSet +) +xt "161400,73000,162800,74200" +st "5" +blo "161400,74000" +tm "HdlTextNumberMgr" +) +] +) +) +*219 (Net +uid 5261,0 +decl (Decl +n "interpolationEn" +t "std_ulogic" +o 40 +suid 60,0 +) +declText (MLText +uid 5262,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,45400,230900,46400" +st "SIGNAL interpolationEn : std_ulogic" +) +) +*220 (Net +uid 5936,0 +decl (Decl +n "cosine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 34 +suid 61,0 +) +declText (MLText +uid 5937,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,40000,240100,41000" +st "SIGNAL cosine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*221 (SaComponent +uid 5956,0 +optionalChildren [ +*222 (CptPort +uid 5944,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5945,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "201000,83625,201750,84375" +) +tg (CPTG +uid 5946,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5947,0 +va (VaSet +) +xt "197200,83400,200000,84600" +st "sine" +ju 2 +blo "200000,84400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sine" +t "signed" +b "(outputBitNb-1 DOWNTO 0)" +o 1 +) +) +) +*223 (CptPort +uid 5948,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5949,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "184250,83625,185000,84375" +) +tg (CPTG +uid 5950,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 5951,0 +va (VaSet +) +xt "186000,83400,189700,84600" +st "phase" +blo "186000,84400" +) +) +thePort (LogicalPort +decl (Decl +n "phase" +t "unsigned" +b "(inputBitNb-1 DOWNTO 0)" +o 2 +) +) +) +*224 (CptPort +uid 5952,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 5953,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "201000,85625,201750,86375" +) +tg (CPTG +uid 5954,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 5955,0 +va (VaSet +) +xt "196000,85400,200000,86600" +st "cosine" +ju 2 +blo "200000,86400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "cosine" +t "signed" +b "(outputBitNb-1 DOWNTO 0)" +o 3 +) +) +) +] +shape (Rectangle +uid 5957,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "185000,80000,201000,90000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 5958,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*225 (Text +uid 5959,0 +va (VaSet +) +xt "185600,89800,189900,91000" +st "Curves" +blo "185600,90800" +tm "BdLibraryNameMgr" +) +*226 (Text +uid 5960,0 +va (VaSet +) +xt "185600,90800,193300,92000" +st "sinCosTable" +blo "185600,91800" +tm "CptNameMgr" +) +*227 (Text +uid 5961,0 +va (VaSet +) +xt "185600,91800,188200,93000" +st "I25" +blo "185600,92800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 5962,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 5963,0 +text (MLText +uid 5964,0 +va (VaSet +font "Verdana,8,0" +) +xt "185000,93000,208700,96000" +st "inputBitNb = phaseBitNb ( positive ) +outputBitNb = signalBitNb ( positive ) +tableAddressBitNb = tableAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "inputBitNb" +type "positive" +value "phaseBitNb" +) +(GiElement +name "outputBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "tableAddressBitNb" +type "positive" +value "tableAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*228 (HdlText +uid 6125,0 +optionalChildren [ +*229 (EmbeddedText +uid 6130,0 +commentText (CommentText +uid 6131,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6132,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "28000,151000,42000,165000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6133,0 +va (VaSet +) +xt "28200,151200,42200,164400" +st " +writeX: process(selX, memX) +begin + if selX = '1' then + dataOut <= std_logic_vector(memX); + else + dataOut <= (others => 'Z'); + end if; +end process writeX; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 14000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 6126,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "27000,150000,43000,166000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6127,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*230 (Text +uid 6128,0 +va (VaSet +) +xt "27400,166000,30000,167200" +st "eb6" +blo "27400,167000" +tm "HdlTextNameMgr" +) +*231 (Text +uid 6129,0 +va (VaSet +) +xt "27400,167000,28800,168200" +st "6" +blo "27400,168000" +tm "HdlTextNumberMgr" +) +] +) +) +*232 (Net +uid 6503,0 +decl (Decl +n "selSinCos" +t "std_ulogic" +o 13 +suid 62,0 +) +declText (MLText +uid 6504,0 +va (VaSet +font "Verdana,8,0" +) +xt "214000,13000,227300,14000" +st "selSinCos : std_ulogic" +) +) +*233 (HdlText +uid 6825,0 +optionalChildren [ +*234 (EmbeddedText +uid 6830,0 +commentText (CommentText +uid 6831,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6832,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "28000,171000,42000,185000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6833,0 +va (VaSet +) +xt "28200,171200,42200,184400" +st " +writeCounters: process(addr, addrX, addrY) +begin + if addr = 16#84# then + dataOut <= std_logic_vector(addrX & addrY); + else + dataOut <= (others => 'Z'); + end if; +end process writeCounters; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 14000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 6826,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "27000,170000,43000,186000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6827,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*235 (Text +uid 6828,0 +va (VaSet +) +xt "27400,186000,30000,187200" +st "eb7" +blo "27400,187000" +tm "HdlTextNameMgr" +) +*236 (Text +uid 6829,0 +va (VaSet +) +xt "27400,187000,28800,188200" +st "7" +blo "27400,188000" +tm "HdlTextNumberMgr" +) +] +) +) +*237 (SaComponent +uid 7019,0 +optionalChildren [ +*238 (CptPort +uid 6994,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6995,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,15625,27000,16375" +) +tg (CPTG +uid 6996,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6997,0 +va (VaSet +font "Verdana,12,0" +) +xt "28000,15300,31800,16700" +st "clock" +blo "28000,16500" +) +s (Text +uid 6998,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "28000,16700,28000,16700" +blo "9000,34900" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*239 (CptPort +uid 6999,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7000,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26250,9625,27000,10375" +) +tg (CPTG +uid 7001,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7002,0 +va (VaSet +font "Verdana,12,0" +) +xt "28000,9300,33000,10700" +st "dataIn" +blo "28000,10500" +) +s (Text +uid 7003,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "28000,10700,28000,10700" +blo "-37800,34100" +) +) +thePort (LogicalPort +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(registerNbBits-1 DOWNTO 0)" +o 1 +) +) +) +*240 (CptPort +uid 7004,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7005,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43000,9625,43750,10375" +) +tg (CPTG +uid 7006,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 7007,0 +va (VaSet +font "Verdana,12,0" +) +xt "36000,9300,42000,10700" +st "dataOut" +ju 2 +blo "42000,10500" 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400 +) +) +*598 (BdJunction +uid 1736,0 +ps "OnConnectorStrategy" +shape (Circle +uid 1737,0 +va (VaSet +vasetType 1 +) +xt "58600,67600,59400,68400" +radius 400 +) +) +*599 (BdJunction +uid 2476,0 +ps "OnConnectorStrategy" +shape (Circle +uid 2477,0 +va (VaSet +vasetType 1 +) +xt "58600,149600,59400,150400" +radius 400 +) +) +*600 (BdJunction +uid 3825,0 +ps "OnConnectorStrategy" +shape (Circle +uid 3826,0 +va (VaSet +vasetType 1 +) +xt "58600,99600,59400,100400" +radius 400 +) +) +*601 (BdJunction +uid 10621,0 +ps "OnConnectorStrategy" +shape (Circle +uid 10622,0 +va (VaSet +vasetType 1 +) +xt "58600,199600,59400,200400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 1527,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "43750,10000,59000,204000" +pts [ +"59000,204000" +"59000,10000" +"43750,10000" +] +) +end &240 +es 0 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1532,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1533,0 +va (VaSet +font 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"100000,152600,107400,154000" +st "dataInReg" +blo "100000,153800" +tm "WireNameMgr" +) +) +on &246 +) +*621 (Wire +uid 2478,0 +shape (OrthoPolyLine +uid 2479,0 +va (VaSet +vasetType 3 +) +xt "103000,166000,106250,166000" +pts [ +"103000,166000" +"106250,166000" +] +) +end &336 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2484,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2485,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,164600,106800,166000" +st "clock" +blo "103000,165800" +tm "WireNameMgr" +) +) +on &15 +) +*622 (Wire +uid 2486,0 +shape (OrthoPolyLine +uid 2487,0 +va (VaSet +vasetType 3 +) +xt "103000,168000,106250,168000" +pts [ +"103000,168000" +"106250,168000" +] +) +end &337 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2492,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2493,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,166600,107100,168000" +st "reset" +blo "103000,167800" +tm "WireNameMgr" +) +) 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2779,0 +va (VaSet +vasetType 3 +) +xt "71000,166000,74250,166000" +pts [ +"71000,166000" +"74250,166000" +] +) +end &137 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2784,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2785,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,164600,75100,166000" +st "reset" +blo "71000,165800" +tm "WireNameMgr" +) +) +on &25 +) +*628 (Wire +uid 2786,0 +shape (OrthoPolyLine +uid 2787,0 +va (VaSet +vasetType 3 +) +xt "71000,164000,74250,164000" +pts [ +"71000,164000" +"74250,164000" +] +) +end &136 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2792,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2793,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,162600,74800,164000" +st "clock" +blo "71000,163800" +tm "WireNameMgr" +) +) +on &15 +) +*629 (Wire +uid 2844,0 +shape (OrthoPolyLine +uid 2845,0 +va (VaSet +vasetType 3 +) +xt "69000,160000,95000,180000" +pts [ +"91750,180000" +"95000,180000" +"95000,174000" +"69000,174000" +"69000,160000" +"74250,160000" +] +) +start &457 +end &135 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2846,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2847,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,158600,74900,160000" +st "cntIncrX" +blo "69000,159800" +tm "WireNameMgr" +) +) +on &126 +) +*630 (Wire +uid 2860,0 +shape (OrthoPolyLine +uid 2861,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "63000,14000,74250,14000" +pts [ +"63000,14000" +"74250,14000" +] +) +start &607 +end &285 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2862,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2863,0 +va (VaSet +font "Verdana,12,0" +) +xt "68250,12600,74250,14000" +st "dataOut" +blo "68250,13800" +tm "WireNameMgr" +) +) +on &91 +) +*631 (Wire +uid 2866,0 +shape (OrthoPolyLine +uid 2867,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "67000,156000,74250,156000" +pts [ +"67000,156000" +"74250,156000" +] +) +end &140 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2872,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2873,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,154600,74900,156000" +st "patternSize" +blo "66000,155800" +tm "WireNameMgr" +) +) +on &88 +) +*632 (Wire +uid 2919,0 +shape (OrthoPolyLine +uid 2920,0 +va (VaSet +vasetType 3 +) +xt "67000,186000,74250,186000" +pts [ +"74250,186000" +"67000,186000" +] +) +start &458 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2925,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2926,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,184600,75600,186000" +st "newPolynom" +blo "66000,185800" +tm "WireNameMgr" +) +) +on &30 +) +*633 (Wire +uid 2996,0 +shape (OrthoPolyLine +uid 2997,0 +va (VaSet +vasetType 3 +) +xt "71000,192000,74250,192000" +pts [ +"71000,192000" +"74250,192000" +] +) +end &460 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3002,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3003,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,190600,75100,192000" +st "reset" +blo "71000,191800" +tm "WireNameMgr" +) +) +on &25 +) +*634 (Wire +uid 3004,0 +shape (OrthoPolyLine +uid 3005,0 +va (VaSet +vasetType 3 +) +xt "71000,190000,74250,190000" +pts [ +"71000,190000" +"74250,190000" +] +) +end &459 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3010,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3011,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,188600,74800,190000" +st "clock" +blo "71000,189800" +tm "WireNameMgr" +) +) +on &15 +) +*635 (Wire +uid 3094,0 +shape (OrthoPolyLine +uid 3095,0 +va (VaSet +vasetType 3 +) +xt "67000,158000,74250,158000" +pts [ +"67000,158000" +"74250,158000" +] +) +end &138 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3100,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3101,0 +va (VaSet +font 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"interpolationEnable" +blo "204000,165800" +tm "WireNameMgr" +) +) +on &124 +) +*638 (Wire +uid 3485,0 +shape (OrthoPolyLine +uid 3486,0 +va (VaSet +vasetType 3 +) +xt "209000,129000,216250,129000" +pts [ +"209000,129000" +"216250,129000" +] +) +end &376 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3491,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3492,0 +va (VaSet +font "Verdana,12,0" +) +xt "204000,127600,217900,129000" +st "interpolationEnable" +blo "204000,128800" +tm "WireNameMgr" +) +) +on &124 +) +*639 (Wire +uid 3751,0 +shape (OrthoPolyLine +uid 3752,0 +va (VaSet +vasetType 3 +) +xt "103000,131000,106250,131000" +pts [ +"103000,131000" +"106250,131000" +] +) +end &326 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3755,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3756,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,129600,107100,131000" +st "reset" +blo "103000,130800" +tm "WireNameMgr" +) +) +on &25 +) +*640 (Wire +uid 3757,0 +shape (OrthoPolyLine +uid 3758,0 +va (VaSet +vasetType 3 +) +xt "103000,129000,106250,129000" +pts [ +"103000,129000" +"106250,129000" +] +) +end &325 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3761,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3762,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,127600,106800,129000" +st "clock" +blo "103000,128800" +tm "WireNameMgr" +) +) +on &15 +) +*641 (Wire +uid 3763,0 +shape (OrthoPolyLine +uid 3764,0 +va (VaSet +vasetType 3 +) +xt "67000,134000,74250,134000" +pts [ +"67000,134000" +"74250,134000" +] +) +end &442 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3767,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3768,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,132600,76800,134000" +st "updatePattern" +blo "66000,133800" +tm "WireNameMgr" +) +) +on &87 +) +*642 (Wire +uid 3769,0 +shape (OrthoPolyLine +uid 3770,0 +va (VaSet +vasetType 3 +) +xt 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+"106250,117000" +] +) +start &600 +end &322 +es 0 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3823,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3824,0 +va (VaSet +font "Verdana,12,0" +) +xt "101250,115600,108650,117000" +st "dataInReg" +blo "101250,116800" +tm "WireNameMgr" +) +) +on &246 +) +*651 (Wire +uid 3866,0 +shape (OrthoPolyLine +uid 3867,0 +va (VaSet +vasetType 3 +) +xt "71000,114000,74250,114000" +pts [ +"71000,114000" +"74250,114000" +] +) +end &155 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3872,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3873,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,112600,74800,114000" +st "clock" +blo "71000,113800" +tm "WireNameMgr" +) +) +on &15 +) +*652 (Wire +uid 3874,0 +shape (OrthoPolyLine +uid 3875,0 +va (VaSet +vasetType 3 +) +xt "71000,116000,74250,116000" +pts [ +"71000,116000" +"74250,116000" +] +) +end &156 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 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"STSignalDisplayStrategy" +f (Text +uid 3912,0 +va (VaSet +font "Verdana,12,0" +) +xt "125750,115600,130250,117000" +st "memY" +blo "125750,116800" +tm "WireNameMgr" +) +) +on &171 +) +*655 (Wire +uid 4047,0 +shape (OrthoPolyLine +uid 4048,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "281000,6000,289000,6000" +pts [ +"281000,6000" +"289000,6000" +] +) +start &174 +end &172 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4051,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4052,0 +va (VaSet +font "Verdana,12,0" +) +xt "284000,4600,289600,6000" +st "testOut" +blo "284000,5800" +tm "WireNameMgr" +) +) +on &173 +) +*656 (Wire +uid 4274,0 +shape (OrthoPolyLine +uid 4275,0 +va (VaSet +vasetType 3 +) +xt "23000,66000,26250,66000" +pts [ +"23000,66000" +"26250,66000" +] +) +end &183 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4280,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4281,0 +va (VaSet +font "Verdana,12,0" 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"STSignalDisplayStrategy" +f (Text +uid 4865,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,82600,207150,84000" +st "sine" +blo "203750,83800" +tm "WireNameMgr" +) +) +on &204 +) +*668 (Wire +uid 4866,0 +shape (OrthoPolyLine +uid 4867,0 +va (VaSet +vasetType 3 +) +xt "153000,86000,160250,86000" +pts [ +"153000,86000" +"160250,86000" +] +) +end &210 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 4872,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4873,0 +va (VaSet +font "Verdana,12,0" +) +xt "149000,84600,162900,86000" +st "interpolationEnable" +blo "149000,85800" +tm "WireNameMgr" +) +) +on &124 +) +*669 (Wire +uid 5086,0 +shape (OrthoPolyLine +uid 5087,0 +va (VaSet +vasetType 3 +) +xt "153000,70000,161000,70000" +pts [ +"153000,70000" +"161000,70000" +] +) +start &214 +end &215 +sat 32 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5090,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5091,0 +va (VaSet +font "Verdana,12,0" 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"WireNameMgr" +) +) +on &219 +) +*672 (Wire +uid 5938,0 +shape (OrthoPolyLine +uid 5939,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "127000,86000,207000,152000" +pts [ +"201750,86000" +"207000,86000" +"207000,97000" +"127000,97000" +"127000,152000" +"131000,152000" +] +) +start &224 +end &129 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 5942,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5943,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,84600,208550,86000" +st "cosine" +blo "203750,85800" +tm "WireNameMgr" +) +) +on &220 +) +*673 (Wire +uid 7055,0 +shape (OrthoPolyLine +uid 7056,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "19000,10000,26250,10000" +pts [ +"26250,10000" +"19000,10000" +] +) +start &239 +end &89 +es 0 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7061,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7062,0 +va (VaSet +font "Verdana,12,0" +) +xt "19000,8600,24000,10000" +st "dataIn" +blo "19000,9800" +tm "WireNameMgr" +) +) +on &247 +) +*674 (Wire +uid 7111,0 +shape (OrthoPolyLine +uid 7112,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "23750,32000,26250,32000" +pts [ +"23750,32000" +"26250,32000" +] +) +start &251 +end &422 +sat 32 +eat 32 +sty 1 +stc 0 +sf 1 +si 0 +tg (WTG +uid 7113,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7114,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,30600,29100,32000" +st "addrReg" +blo "23000,31800" +tm "WireNameMgr" +) +s (Text +uid 7337,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,32000,23000,32000" +blo "23000,32000" +tm "SignalTypeMgr" +) +) +on &257 +) +*675 (Wire +uid 7117,0 +shape (OrthoPolyLine +uid 7118,0 +va (VaSet +vasetType 3 +) +xt "23000,18000,26250,18000" +pts [ +"23000,18000" +"26250,18000" +] +) +end &242 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7123,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7124,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,16600,27100,18000" +st "reset" +blo "23000,17800" +tm "WireNameMgr" +) +) +on &25 +) +*676 (Wire +uid 7125,0 +shape (OrthoPolyLine +uid 7126,0 +va (VaSet +vasetType 3 +) +xt "23000,16000,26250,16000" +pts [ +"23000,16000" +"26250,16000" +] +) +end &238 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7131,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7132,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,14600,26800,16000" +st "clock" +blo "23000,15800" +tm "WireNameMgr" +) +) +on &15 +) +*677 (Wire +uid 7133,0 +shape (OrthoPolyLine +uid 7134,0 +va (VaSet +vasetType 3 +) +xt "3000,40000,6250,40000" +pts [ +"3000,40000" +"6250,40000" +] +) +end &253 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7139,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7140,0 +va (VaSet +font "Verdana,12,0" +) +xt "3000,38600,7100,40000" +st "reset" +blo "3000,39800" +tm "WireNameMgr" +) +) +on &25 +) +*678 (Wire +uid 7141,0 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7168,0 +shape (OrthoPolyLine +uid 7169,0 +va (VaSet +vasetType 3 +) +xt "3000,36000,6250,36000" +pts [ +"6250,36000" +"3000,36000" +] +) +start &252 +sat 32 +eat 16 +stc 0 +sf 1 +si 0 +tg (WTG +uid 7174,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7175,0 +va (VaSet +font "Verdana,12,0" +) +xt "3000,34600,7400,36000" +st "logic1" +blo "3000,35800" +tm "WireNameMgr" +) +s (Text +uid 7176,0 +va (VaSet +font "Verdana,12,0" +) +xt "3000,36000,3000,36000" +blo "3000,36000" +tm "SignalTypeMgr" +) +) +on &262 +) +*681 (Wire +uid 7724,0 +shape (OrthoPolyLine +uid 7725,0 +va (VaSet +vasetType 3 +) +xt "23000,116000,26250,116000" +pts [ +"23000,116000" +"26250,116000" +] +) +end &268 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7730,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7731,0 +va (VaSet +font "Verdana,12,0" +) +xt "23000,114600,27100,116000" +st "reset" +blo "23000,115800" +tm "WireNameMgr" +) +) +on &25 +) +*682 (Wire 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[ +"43750,108000" +"47000,108000" +] +) +start &264 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7754,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7755,0 +va (VaSet +font "Verdana,12,0" +) +xt "44000,106600,51400,108000" +st "wr16Pulse" +blo "44000,107800" +tm "WireNameMgr" +) +) +on &272 +) +*685 (Wire +uid 7793,0 +shape (OrthoPolyLine +uid 7794,0 +va (VaSet +vasetType 3 +) +xt "17950,108000,26250,108000" +pts [ +"26250,108000" +"17950,108000" +] +) +start &265 +end &276 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7795,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7796,0 +va (VaSet +font "Verdana,12,0" +) +xt "20000,106600,24000,108000" +st "wr16" +blo "20000,107800" +tm "WireNameMgr" +) +) +on &280 +) +*686 (Wire +uid 7801,0 +shape (OrthoPolyLine +uid 7802,0 +va (VaSet +vasetType 3 +) +xt "7000,106000,11000,106000" +pts [ +"7000,106000" +"11000,106000" +] +) +end &274 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7807,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7808,0 +va (VaSet +font "Verdana,12,0" +) +xt "7000,104600,10300,106000" +st "wrH" +blo "7000,105800" +tm "WireNameMgr" +) +) +on &27 +) +*687 (Wire +uid 7809,0 +shape (OrthoPolyLine +uid 7810,0 +va (VaSet +vasetType 3 +) +xt "7000,110000,11000,110000" +pts [ +"7000,110000" +"11000,110000" +] +) +end &275 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7815,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7816,0 +va (VaSet +font "Verdana,12,0" +) +xt "7000,108600,10100,110000" +st "wrL" +blo "7000,109800" +tm "WireNameMgr" +) +) +on &29 +) +*688 (Wire +uid 7907,0 +shape (OrthoPolyLine +uid 7908,0 +va (VaSet +vasetType 3 +) +xt "67000,132000,74250,132000" +pts [ +"67000,132000" +"74250,132000" +] +) +end &443 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7913,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7914,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,130600,74400,132000" +st "wr16Pulse" +blo "67000,131800" +tm "WireNameMgr" +) +) +on &272 +) +*689 (Wire +uid 7915,0 +shape (OrthoPolyLine +uid 7916,0 +va (VaSet +vasetType 3 +) +xt "67000,182000,74250,182000" +pts [ +"67000,182000" +"74250,182000" +] +) +end &456 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 7921,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7922,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,180600,74400,182000" +st "wr16Pulse" +blo "67000,181800" +tm "WireNameMgr" +) +) +on &272 +) +*690 (Wire +uid 8150,0 +shape (OrthoPolyLine +uid 8151,0 +va (VaSet +vasetType 3 +) +xt "91750,16000,99000,16000" +pts [ +"91750,16000" +"99000,16000" +] +) +start &290 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8154,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8155,0 +va (VaSet +font "Verdana,12,0" +) +xt "93750,14600,104050,16000" +st "interpolateLin" +blo "93750,15800" +tm "WireNameMgr" +) +) +on &393 +) +*691 (Wire +uid 8248,0 +optionalChildren [ +*692 (BdJunction +uid 8258,0 +ps "OnConnectorStrategy" +shape (Circle +uid 8259,0 +va (VaSet +vasetType 1 +) +xt "180600,124600,181400,125400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 8249,0 +va (VaSet +vasetType 3 +) +xt "177000,69000,184250,162000" +pts [ +"184250,162000" +"181000,162000" +"181000,69000" +"177000,69000" +] +) +start &304 +end &215 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8252,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8253,0 +va (VaSet +font "Verdana,12,0" +) +xt "179000,67600,191400,69000" +st "interpolateLinear" +blo "179000,68800" +tm "WireNameMgr" +) +) +on &294 +) +*693 (Wire +uid 8254,0 +shape (OrthoPolyLine +uid 8255,0 +va (VaSet +vasetType 3 +) +xt "181000,125000,184250,125000" +pts [ +"184250,125000" +"181000,125000" +] +) +start &317 +end &692 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 8256,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 8257,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "171250,123600,183650,125000" +st "interpolateLinear" +blo "171250,124800" +tm "WireNameMgr" +) +) +on &294 +) +*694 (Wire +uid 9246,0 +shape (OrthoPolyLine +uid 9247,0 +va (VaSet +vasetType 3 +) +xt "139000,121000,139000,125000" +pts [ +"139000,125000" +"139000,121000" +] +) +end &167 +sat 16 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 9252,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9253,0 +va (VaSet +font "Verdana,12,0" +) +xt "139000,123600,145900,125000" +st "selSinCos" +blo "139000,124800" +tm "WireNameMgr" +) +) +on &232 +) +*695 (Wire +uid 9254,0 +shape (OrthoPolyLine +uid 9255,0 +va (VaSet +vasetType 3 +) +xt "139000,158000,139000,162000" +pts [ +"139000,162000" +"139000,158000" +] +) +end &129 +sat 16 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 9260,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 9261,0 +va (VaSet +font "Verdana,12,0" +) +xt "139000,160600,145900,162000" +st "selSinCos" +blo "139000,161800" +tm "WireNameMgr" +) +) +on &232 +) +*696 (Wire +uid 10531,0 +shape (OrthoPolyLine +uid 10532,0 +va (VaSet +vasetType 3 +) +xt "91750,212000,106250,236000" +pts [ +"91750,236000" +"101000,236000" +"101000,212000" +"106250,212000" +] +) +start &467 +end &407 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10533,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10534,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,210600,106200,212000" +st "memEnZ" +blo "100000,211800" +tm "WireNameMgr" +) +) +on &419 +) +*697 (Wire +uid 10535,0 +shape (OrthoPolyLine +uid 10536,0 +va (VaSet +vasetType 3 +) +xt "91750,210000,106250,234000" +pts [ +"91750,234000" +"99000,234000" +"99000,210000" +"106250,210000" +] +) +start &465 +end &410 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10537,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10538,0 +va (VaSet +font "Verdana,12,0" +) +xt "100000,208600,106400,210000" +st "memWrZ" +blo "100000,209800" +tm "WireNameMgr" +) +) +on &418 +) +*698 (Wire +uid 10539,0 +shape (OrthoPolyLine +uid 10540,0 +va (VaSet +vasetType 3 +) +xt "71000,216000,74250,216000" +pts [ +"71000,216000" +"74250,216000" +] +) +end &397 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10543,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10544,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,214600,75100,216000" +st "reset" +blo "71000,215800" +tm "WireNameMgr" +) +) +on &25 +) +*699 (Wire +uid 10545,0 +shape (OrthoPolyLine +uid 10546,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "91750,206000,106250,206000" +pts [ +"91750,206000" +"106250,206000" +] +) +start &399 +end &411 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10547,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10548,0 +va (VaSet +font "Verdana,12,0" +) +xt "102000,204600,106500,206000" +st "addrZ" +blo "102000,205800" +tm "WireNameMgr" +) +) +on &416 +) +*700 (Wire +uid 10549,0 +shape (OrthoPolyLine +uid 10550,0 +va (VaSet +vasetType 3 +) +xt "67000,234000,74250,234000" +pts [ +"67000,234000" +"74250,234000" +] +) +end &468 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10553,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10554,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,232600,76800,234000" +st "updatePattern" +blo "66000,233800" +tm "WireNameMgr" +) +) +on &87 +) +*701 (Wire +uid 10555,0 +shape (OrthoPolyLine +uid 10556,0 +va (VaSet +vasetType 3 +) +xt "69000,210000,95000,230000" +pts [ +"91750,230000" +"95000,230000" +"95000,224000" +"69000,224000" +"69000,210000" +"74250,210000" +] +) +start &470 +end &395 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10557,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10558,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,208600,74900,210000" +st "cntIncrZ" +blo "69000,209800" +tm "WireNameMgr" +) +) +on &415 +) +*702 (Wire +uid 10559,0 +shape (OrthoPolyLine +uid 10560,0 +va (VaSet +vasetType 3 +) +xt "71000,214000,74250,214000" +pts [ +"71000,214000" +"74250,214000" +] +) +end &396 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10563,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10564,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,212600,74800,214000" +st "clock" +blo "71000,213800" +tm "WireNameMgr" +) +) +on &15 +) +*703 (Wire +uid 10565,0 +shape (OrthoPolyLine +uid 10566,0 +va (VaSet +vasetType 3 +) +xt "67000,236000,74250,236000" +pts [ +"74250,236000" +"67000,236000" +] +) +start &471 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10569,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10570,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,234600,75600,236000" +st "newPolynom" +blo "66000,235800" +tm "WireNameMgr" +) +) +on &30 +) +*704 (Wire +uid 10571,0 +shape (OrthoPolyLine +uid 10572,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "67000,206000,74250,206000" +pts [ +"67000,206000" +"74250,206000" +] +) +end &400 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10575,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10576,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,204600,74900,206000" +st "patternSize" +blo "66000,205800" +tm "WireNameMgr" +) +) +on &88 +) +*705 (Wire +uid 10577,0 +shape (OrthoPolyLine +uid 10578,0 +va (VaSet +vasetType 3 +) +xt "67000,208000,74250,208000" +pts [ +"67000,208000" +"74250,208000" +] +) +end &398 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10581,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10582,0 +va (VaSet +font "Verdana,12,0" +) +xt "66000,206600,76800,208000" +st "updatePattern" +blo "66000,207800" +tm "WireNameMgr" +) +) +on &87 +) +*706 (Wire +uid 10583,0 +shape (OrthoPolyLine +uid 10584,0 +va (VaSet +vasetType 3 +) +xt "71000,240000,74250,240000" +pts [ +"71000,240000" +"74250,240000" +] +) +end &472 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10587,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10588,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,238600,74800,240000" +st "clock" +blo "71000,239800" +tm "WireNameMgr" +) +) +on &15 +) +*707 (Wire +uid 10589,0 +shape (OrthoPolyLine +uid 10590,0 +va (VaSet +vasetType 3 +) +xt "71000,242000,74250,242000" +pts [ +"71000,242000" +"74250,242000" +] +) +end &473 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10593,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10594,0 +va (VaSet +font "Verdana,12,0" +) +xt "71000,240600,75100,242000" +st "reset" +blo "71000,241800" +tm "WireNameMgr" +) +) +on &25 +) +*708 (Wire +uid 10595,0 +shape (OrthoPolyLine +uid 10596,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "123750,204000,131000,204000" +pts [ +"123750,204000" +"131000,204000" +] +) +start &406 +end &491 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10599,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10600,0 +va (VaSet +font "Verdana,12,0" +) +xt "127000,202600,131600,204000" +st "memZ" +blo "127000,203800" +tm "WireNameMgr" +) +) +on &417 +) +*709 (Wire +uid 10601,0 +shape (OrthoPolyLine +uid 10602,0 +va (VaSet +vasetType 3 +) +xt "67000,232000,74250,232000" +pts [ +"67000,232000" +"74250,232000" +] +) +end &469 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 10605,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 10606,0 +va (VaSet +font "Verdana,12,0" +) +xt "67000,230600,73500,232000" +st "wrLPulse" +blo "67000,231800" +tm "WireNameMgr" +) +) +on &197 +) +*710 (Wire +uid 10617,0 +shape (OrthoPolyLine +uid 10618,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "59000,200000,106250,204000" +pts [ +"59000,200000" +"99000,200000" +"99000,204000" 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"CptPortNameMgr" +) +) +dt (MLText +uid 101,0 +va (VaSet +font "courier,8,0" +) +xt "2000,13900,18500,14800" +st "wrH : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "wrH" +t "std_ulogic" +o 8 +suid 8,0 +) +) +) +*104 (CptPort +uid 102,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 103,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "35250,19625,36000,20375" +) +tg (CPTG +uid 104,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 105,0 +va (VaSet +font "courier,9,0" +) +xt "37000,19400,38000,20300" +st "cs" +blo "37000,20100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 106,0 +va (VaSet +font "courier,8,0" +) +xt "2000,14800,18500,15700" +st "cs : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "cs" +t "std_ulogic" +o 9 +suid 9,0 +) +) +) +*105 (CptPort +uid 107,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 108,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "35250,17625,36000,18375" +) +tg (CPTG +uid 109,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 110,0 +va (VaSet +font "courier,9,0" +) +xt "37000,17400,38500,18300" +st "wrL" +blo "37000,18100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 111,0 +va (VaSet +font "courier,8,0" +) +xt "2000,15700,18500,16600" +st "wrL : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "wrL" +t "std_ulogic" +o 10 +suid 10,0 +) +) +) +*106 (CptPort +uid 113,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 119,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "35250,9625,36000,10375" +) +tg (CPTG +uid 115,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 116,0 +va (VaSet +font "courier,9,0" +) +xt "37000,9400,40500,10300" +st "dataOut" +blo "37000,10100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 117,0 +va (VaSet +font "courier,8,0" +) +xt "2000,16600,32500,17500" +st "dataOut : OUT std_logic_vector (dataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dataOut" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 11,0 +) +) +) +*107 (CptPort +uid 120,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 121,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52000,31625,52750,32375" +) +tg (CPTG +uid 122,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 123,0 +va (VaSet +font "courier,9,0" +) +xt "47501,31400,51001,32300" +st "testOut" +ju 2 +blo "51001,32100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 124,0 +va (VaSet +font "courier,8,0" +) +xt "2000,17500,26500,18400" +st "testOut : OUT std_ulogic_vector (1 TO 16) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO 16)" +o 12 +suid 12,0 +) +) +) +*108 (CptPort +uid 125,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 130,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52000,29625,52750,30375" +) +tg (CPTG +uid 127,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 128,0 +va (VaSet +font "courier,9,0" +) +xt "46501,29400,51001,30300" +st "selSinCos" +ju 2 +blo "51001,30100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 129,0 +va (VaSet +font "courier,8,0" +) +xt "2000,18400,18500,19300" +st "selSinCos : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "selSinCos" +t "std_ulogic" +o 13 +suid 13,0 +) +) +) +*109 (CptPort +uid 131,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 132,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52000,9625,52750,10375" +) +tg (CPTG +uid 133,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 134,0 +va (VaSet +font "courier,9,0" +) +xt "49001,9400,51001,10300" +st "outZ" +ju 2 +blo "51001,10100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 135,0 +va (VaSet +font "courier,8,0" +) +xt "2000,19300,18500,20200" +st "outZ : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "outZ" +t "std_ulogic" +o 14 +suid 14,0 +) +) +) +*110 (CptPort +uid 136,0 +ps "OnEdgeStrategy" +shape (Triangle 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"2000,20200,18500,21100" +st "CS_X_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CS_X_n" +t "std_ulogic" +o 15 +suid 16,0 +) +) +) +*112 (CptPort +uid 146,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 147,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52000,17625,52750,18375" +) +tg (CPTG +uid 148,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 149,0 +va (VaSet +font "courier,9,0" +) +xt "48500,17400,51000,18300" +st "SDI_X" +ju 2 +blo "51000,18100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 150,0 +va (VaSet +font "courier,8,0" +) +xt "2000,21100,18500,22000" +st "SDI_X : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "SDI_X" +t "std_ulogic" +o 16 +suid 17,0 +) +) +) +*113 (CptPort +uid 151,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 152,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52000,21625,52750,22375" +) +tg (CPTG +uid 153,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 154,0 +va (VaSet +font "courier,9,0" +) +xt "48000,21400,51000,22300" +st "CS_Y_n" +ju 2 +blo "51000,22100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 155,0 +va (VaSet +font "courier,8,0" +) +xt "2000,23800,18500,24700" +st "CS_Y_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "CS_Y_n" +t "std_ulogic" +o 19 +suid 18,0 +) +) +) +*114 (CptPort +uid 156,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 157,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52000,25625,52750,26375" +) +tg (CPTG +uid 158,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 159,0 +va (VaSet +font "courier,9,0" +) +xt "48500,25400,51000,26300" +st "SDI_Y" +ju 2 +blo "51000,26100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 160,0 +va (VaSet +font "courier,8,0" +) +xt "2000,24700,17500,25600" +st "SDI_Y : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "SDI_Y" +t "std_ulogic" +o 20 +suid 19,0 +) +) +) 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"36600,36500" +) +second (Text +uid 12,0 +va (VaSet +font "courier,9,1" +) +xt "36600,36700,47100,37600" +st "beamerPeriphBlanking" +blo "36600,37400" +) +) +gi *116 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "36000,39600,49500,43200" +st "Generic Declarations + +dataBitNb positive 16 +addressBitNb positive 24 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "16" +) +(GiElement +name "addressBitNb" +type "positive" +value "24" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*117 (Grouping +uid 16,0 +optionalChildren [ +*118 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg 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std_ulogic" +) +) +*19 (Net +uid 542,0 +decl (Decl +n "sampleX" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 25 +suid 11,0 +) +declText (MLText +uid 543,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,184200,28700,185200" +st "SIGNAL sampleX : signed(signalBitNb-1 DOWNTO 0)" +) +) +*20 (Net +uid 544,0 +decl (Decl +n "unsignedX" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 39 +suid 12,0 +) +declText (MLText +uid 545,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,195400,29800,196400" +st "SIGNAL unsignedX : unsigned(signalBitNb-1 DOWNTO 0)" +) +) +*21 (Net +uid 546,0 +decl (Decl +n "samplesX" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 35 +suid 13,0 +) +declText (MLText +uid 547,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,192200,28800,193200" +st "SIGNAL samplesX : signed(signalBitNb-1 DOWNTO 0)" +) +) +*22 (Net +uid 548,0 +decl (Decl +n "sampleX1" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 26 +suid 14,0 +) +declText (MLText +uid 549,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,185000,28900,186000" +st "SIGNAL sampleX1 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*23 (Net +uid 550,0 +decl (Decl +n "sampleX2" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 27 +suid 15,0 +) +declText (MLText +uid 551,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,185800,28900,186800" +st "SIGNAL sampleX2 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*24 (Net +uid 552,0 +decl (Decl +n "sampleX3" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 28 +suid 16,0 +) +declText (MLText +uid 553,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,186600,28900,187600" +st "SIGNAL sampleX3 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*25 (Net +uid 554,0 +decl (Decl +n "sampleX4" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 29 +suid 17,0 +) +declText (MLText +uid 555,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,187400,28900,188400" +st "SIGNAL sampleX4 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*26 (Net +uid 556,0 +decl (Decl +n "aX" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 12 +suid 18,0 +) +declText (MLText +uid 557,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,173800,27500,174800" +st "SIGNAL aX : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*27 (Net +uid 558,0 +decl (Decl +n "bX" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 14 +suid 19,0 +) +declText (MLText +uid 559,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,175400,27500,176400" +st "SIGNAL bX : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*28 (Net +uid 560,0 +decl (Decl +n "cX" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 16 +suid 20,0 +) +declText (MLText +uid 561,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,177000,27400,178000" +st "SIGNAL cX : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*29 (Net +uid 562,0 +decl (Decl +n "dX" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 19 +suid 21,0 +) +declText (MLText +uid 563,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,179400,27500,180400" +st "SIGNAL dX : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*30 (Net +uid 865,0 +decl (Decl +n "samplesY" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 36 +suid 22,0 +) +declText (MLText +uid 866,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,193000,28800,194000" +st "SIGNAL samplesY : signed(signalBitNb-1 DOWNTO 0)" +) +) +*31 (Net +uid 867,0 +decl (Decl +n "sampleY1" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 31 +suid 23,0 +) +declText (MLText +uid 868,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,189000,28900,190000" +st "SIGNAL sampleY1 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*32 (Net +uid 869,0 +decl (Decl +n "sampleY2" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 32 +suid 24,0 +) +declText (MLText +uid 870,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,189800,28900,190800" +st "SIGNAL sampleY2 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*33 (Net +uid 871,0 +decl (Decl +n "sampleY3" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 33 +suid 25,0 +) +declText (MLText +uid 872,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,190600,28900,191600" +st "SIGNAL sampleY3 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*34 (Net +uid 873,0 +decl (Decl +n "sampleY4" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 34 +suid 26,0 +) +declText (MLText +uid 874,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,191400,28900,192400" +st "SIGNAL sampleY4 : signed(signalBitNb-1 DOWNTO 0)" +) +) +*35 (Net +uid 875,0 +decl (Decl +n "aY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 13 +suid 27,0 +) +declText (MLText +uid 876,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,174600,27500,175600" +st "SIGNAL aY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*36 (Net +uid 877,0 +decl (Decl +n "bY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 15 +suid 28,0 +) +declText (MLText +uid 878,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,176200,27500,177200" +st "SIGNAL bY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*37 (Net +uid 879,0 +decl (Decl +n "cY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 17 +suid 29,0 +) +declText (MLText +uid 880,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,177800,27400,178800" +st "SIGNAL cY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*38 (Net +uid 881,0 +decl (Decl +n "dY" +t "signed" +b "(coeffBitNb-1 DOWNTO 0)" +o 20 +suid 30,0 +) +declText (MLText +uid 882,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,180200,27500,181200" +st "SIGNAL dY : signed(coeffBitNb-1 DOWNTO 0)" +) +) +*39 (Net +uid 883,0 +decl (Decl +n "sampleY" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 30 +suid 31,0 +) +declText (MLText +uid 884,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,188200,28700,189200" +st "SIGNAL sampleY : signed(signalBitNb-1 DOWNTO 0)" +) +) +*40 (Net +uid 885,0 +decl (Decl +n "unsignedY" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 40 +suid 32,0 +) +declText (MLText +uid 886,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,196200,29800,197200" +st "SIGNAL unsignedY : unsigned(signalBitNb-1 DOWNTO 0)" +) +) +*41 (Net +uid 1348,0 +decl (Decl +n "run" +t "std_ulogic" +o 2 +suid 38,0 +) +declText (MLText +uid 1349,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,159000,14600,160000" +st "run : std_ulogic" +) +) +*42 (Net +uid 1776,0 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(updatePeriodBitNb-1 DOWNTO 0)" +o 8 +suid 42,0 +) +declText (MLText +uid 1777,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,163800,29900,164800" +st "updatePeriod : unsigned(updatePeriodBitNb-1 DOWNTO 0)" +) +) +*43 (Net +uid 1993,0 +decl (Decl +n "interpolationEnable" +t "std_ulogic" +o 23 +suid 43,0 +) +declText (MLText +uid 1994,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,182600,19400,183600" +st "SIGNAL interpolationEnable : std_ulogic" +) +) +*44 (HdlText +uid 3135,0 +optionalChildren [ +*45 (EmbeddedText +uid 3140,0 +commentText (CommentText +uid 3141,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3142,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,152000,146000,156000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3143,0 +va (VaSet +) +xt "132200,152200,144900,155800" +st " +samplesX <= cosine when selSinCos = '1' + else signed(memX); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3136,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,150000,147000,158000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3137,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*46 (Text +uid 3138,0 +va (VaSet +) +xt "131400,158000,134000,159200" +st "eb2" +blo "131400,159000" +tm "HdlTextNameMgr" +) +*47 (Text +uid 3139,0 +va (VaSet +) +xt "131400,159000,132800,160200" +st "2" +blo "131400,160000" +tm "HdlTextNumberMgr" +) +] +) +) +*48 (Net +uid 3152,0 +decl (Decl +n "memX" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 9 +suid 48,0 +) +declText (MLText +uid 3153,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,164600,30000,165600" +st "memX : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*49 (HdlText +uid 3896,0 +optionalChildren [ +*50 (EmbeddedText +uid 3901,0 +commentText (CommentText +uid 3902,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 3903,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,115000,146000,119000" +) +oxt "0,0,18000,5000" +text (MLText +uid 3904,0 +va (VaSet +) +xt "132200,115200,144900,118800" +st " +samplesY <= sine when selSinCos = '1' + else signed(memY); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 4000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 3897,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "131000,113000,147000,121000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 3898,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*51 (Text +uid 3899,0 +va (VaSet +) +xt "131400,121000,134000,122200" +st "eb1" +blo "131400,122000" +tm "HdlTextNameMgr" +) +*52 (Text +uid 3900,0 +va (VaSet +) +xt "131400,122000,132800,123200" +st "1" +blo "131400,123000" +tm "HdlTextNumberMgr" +) +] +) +) +*53 (Net +uid 3913,0 +decl (Decl +n "memY" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 10 +suid 53,0 +) +declText (MLText +uid 3914,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,165400,30000,166400" +st "memY : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*54 (HdlText +uid 4719,0 +optionalChildren [ +*55 (EmbeddedText +uid 4724,0 +commentText (CommentText +uid 4725,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4726,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "64000,141000,78000,143000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4727,0 +va (VaSet +) +xt "64200,141200,78000,142400" +st " +step <= to_unsigned(1, step'length); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4720,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "63000,140000,79000,144000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4721,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*56 (Text +uid 4722,0 +va (VaSet +) +xt "63400,144000,66000,145200" +st "eb4" +blo "63400,145000" +tm "HdlTextNameMgr" +) +*57 (Text +uid 4723,0 +va (VaSet +) +xt "63400,145000,64800,146200" +st "4" +blo "63400,146000" +tm "HdlTextNumberMgr" +) +] +) +) +*58 (Net +uid 4800,0 +decl (Decl +n "phase" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 24 +suid 57,0 +) +declText (MLText +uid 4801,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,183400,29400,184400" +st "SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*59 (Net +uid 4802,0 +decl (Decl +n "step" +t "unsigned" +b "(phaseBitNb-1 DOWNTO 0)" +o 38 +suid 58,0 +) +declText (MLText +uid 4803,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,194600,29000,195600" +st "SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0)" +) +) +*60 (Net +uid 4858,0 +decl (Decl +n "sine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 37 +suid 59,0 +) +declText (MLText +uid 4859,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,193800,27800,194800" +st "SIGNAL sine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*61 (PortIoIn +uid 5080,0 +shape (CompositeShape +uid 5081,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5082,0 +sl 0 +ro 270 +xt "89000,108625,90500,109375" +) +(Line +uid 5083,0 +sl 0 +ro 270 +xt "90500,109000,91000,109000" +pts [ +"90500,109000" +"91000,109000" +] +) +] +) +tg (WTG +uid 5084,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5085,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "81100,108300,88000,109700" +st "selSinCos" +ju 2 +blo "88000,109500" +tm "WireNameMgr" +) +) +) +*62 (HdlText +uid 5244,0 +optionalChildren [ +*63 (EmbeddedText +uid 5249,0 +commentText (CommentText +uid 5250,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 5251,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "99000,104000,115000,114000" +) +oxt "0,0,18000,5000" +text (MLText +uid 5252,0 +va (VaSet +) +xt "99200,104200,114600,113800" +st " +interpolationEnable <= '1' when selSinCos = '1' + else interpolationEn; +interpolateLinear <= '0' when selSinCos = '1' + else interpolateLin; +--interpolateLinear <= interpolateLin; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 5245,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "99000,103000,115000,115000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 5246,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*64 (Text +uid 5247,0 +va (VaSet +) +xt "99400,115000,102000,116200" +st "eb5" +blo "99400,116000" +tm "HdlTextNameMgr" +) +*65 (Text +uid 5248,0 +va (VaSet +) +xt "99400,116000,100800,117200" +st "5" +blo "99400,117000" +tm "HdlTextNumberMgr" +) +] +) +) +*66 (Net +uid 5261,0 +decl (Decl +n "interpolationEn" +t "std_ulogic" +o 22 +suid 60,0 +) +declText (MLText +uid 5262,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,181800,18900,182800" +st "SIGNAL interpolationEn : std_ulogic" +) +) +*67 (Net +uid 5936,0 +decl (Decl +n "cosine" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 18 +suid 61,0 +) +declText (MLText +uid 5937,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,178600,28100,179600" +st "SIGNAL cosine : signed(signalBitNb-1 DOWNTO 0)" +) +) +*68 (Net +uid 6503,0 +decl (Decl +n "selSinCos" +t "std_ulogic" +o 6 +suid 62,0 +) +declText (MLText +uid 6504,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,162200,15300,163200" +st "selSinCos : std_ulogic" +) +) +*69 (Net +uid 8148,0 +decl (Decl +n "interpolateLinear" +t "std_ulogic" +o 21 +suid 69,0 +) +declText (MLText +uid 8149,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,181000,19000,182000" +st "SIGNAL interpolateLinear : std_ulogic" +) +) +*70 (Net +uid 9646,0 +decl (Decl +n "interpolateLin" +t "std_ulogic" +o 7 +suid 70,0 +) +declText (MLText +uid 9647,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,163000,15400,164000" +st "interpolateLin : std_ulogic" +) +) +*71 (SaComponent +uid 11853,0 +optionalChildren [ +*72 (CptPort +uid 11833,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11834,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,155625,75000,156375" +) +tg (CPTG +uid 11835,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11836,0 +va (VaSet +) +xt "76000,155400,79400,156600" +st "clock" +blo "76000,156400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +) +) +*73 (CptPort +uid 11837,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11838,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91000,149625,91750,150375" +) +tg (CPTG +uid 11839,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11840,0 +va (VaSet +) +xt "84800,149400,90000,150600" +st "sawtooth" +ju 2 +blo "90000,150400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sawtooth" +t "unsigned" +b "(bitNb-1 DOWNTO 0)" +o 1 +suid 2,0 +) +) +) +*74 (CptPort +uid 11841,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11842,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74250,157625,75000,158375" +) +tg (CPTG +uid 11843,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11844,0 +va (VaSet +) +xt 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positive ) " +) +header "" +) +elements [ +(GiElement +name "bitNb" +type "positive" +value "phaseBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*80 (SaComponent +uid 11874,0 +optionalChildren [ +*81 (CptPort +uid 11862,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11863,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "115000,149625,115750,150375" +) +tg (CPTG +uid 11864,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11865,0 +va (VaSet +) +xt "111200,149400,114000,150600" +st "sine" +ju 2 +blo "114000,150400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sine" +t "signed" +b "(outputBitNb-1 DOWNTO 0)" +o 1 +suid 1,0 +) +) +) +*82 (CptPort +uid 11866,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11867,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98250,149625,99000,150375" +) +tg (CPTG +uid 11868,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11869,0 +va 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"0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "161000,113000,177000,127000" +) +oxt "35000,9000,51000,23000" +ttg (MlTextGroup +uid 11917,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*96 (Text +uid 11918,0 +va (VaSet +font "Verdana,9,1" +) +xt "161600,126800,166000,128000" +st "Beamer" +blo "161600,127800" +tm "BdLibraryNameMgr" +) +*97 (Text +uid 11919,0 +va (VaSet +font "Verdana,9,1" +) +xt "161600,128000,176100,129200" +st "interpolatorShiftRegister" +blo "161600,129000" +tm "CptNameMgr" +) +*98 (Text +uid 11920,0 +va (VaSet +font "Verdana,9,1" +) +xt "161600,129200,164800,130400" +st "I_sry" +blo "161600,130200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 11921,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 11922,0 +text (MLText +uid 11923,0 +va (VaSet +font "Verdana,8,0" +) +xt "161000,130600,179400,131600" +st "signalBitNb = signalBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*99 (SaComponent +uid 11924,0 +optionalChildren [ +*100 (CptPort +uid 11933,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11934,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,159625,161000,160375" +) +tg (CPTG +uid 11935,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11936,0 +va (VaSet +) +xt "162000,159400,165400,160600" +st "clock" +blo "162000,160400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +) +) +) +*101 (CptPort +uid 11937,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11938,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "160250,161625,161000,162375" +) +tg (CPTG +uid 11939,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11940,0 +va (VaSet +) +xt "162000,161400,165300,162600" +st "reset" +blo "162000,162400" +) +) +thePort (LogicalPort +decl (Decl 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11958,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "177000,157625,177750,158375" +) +tg (CPTG +uid 11959,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11960,0 +va (VaSet +) +xt "171000,157400,176000,158600" +st "sample3" +ju 2 +blo "176000,158400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sample3" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 7 +) +) +) +*107 (CptPort +uid 11961,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11962,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "177000,159625,177750,160375" +) +tg (CPTG +uid 11963,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11964,0 +va (VaSet +) +xt "171000,159400,176000,160600" +st "sample4" +ju 2 +blo "176000,160400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sample4" +t "signed" +b "(signalBitNb-1 DOWNTO 0)" +o 8 +) +) +) +] +shape (Rectangle +uid 11925,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor 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"WireNameMgr" +) +) +on &29 +) +*235 (Wire +uid 416,0 +shape (OrthoPolyLine +uid 417,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,158000,216250,158000" +pts [ +"201750,158000" +"216250,158000" +] +) +start &132 +end &164 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 418,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 419,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,156600,205950,158000" +st "cX" +blo "203750,157800" +tm "WireNameMgr" +) +) +on &28 +) +*236 (Wire +uid 420,0 +shape (OrthoPolyLine +uid 421,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,156000,216250,156000" +pts [ +"201750,156000" +"216250,156000" +] +) +start &130 +end &165 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 422,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 423,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,154600,206150,156000" +st "bX" +blo "203750,155800" +tm "WireNameMgr" +) +) +on &27 +) +*237 (Wire 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&163 +end &179 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 534,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 535,0 +va (VaSet +font "Verdana,12,0" +) +xt "234000,152600,240100,154000" +st "sampleX" +blo "234000,153800" +tm "WireNameMgr" +) +) +on &19 +) +*242 (Wire +uid 538,0 +shape (OrthoPolyLine +uid 539,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "257750,154000,264250,154000" +pts [ +"257750,154000" +"264250,154000" +] +) +start &178 +end &193 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 540,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 541,0 +va (VaSet +font "Verdana,12,0" +) +xt "258000,152600,265400,154000" +st "unsignedX" +blo "258000,153800" +tm "WireNameMgr" +) +) +on &20 +) +*243 (Wire +uid 767,0 +shape (OrthoPolyLine +uid 768,0 +va (VaSet +vasetType 3 +) +xt "205000,125000,216250,162000" +pts [ +"205000,162000" +"205000,125000" +"216250,125000" +] +) +start &222 +end &148 +sat 32 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"ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 784,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,123600,160100,125000" +st "reset" +blo "156000,124800" +tm "WireNameMgr" +) +) +on &17 +) +*246 (Wire +uid 785,0 +shape (OrthoPolyLine +uid 786,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,117000,184250,117000" +pts [ +"177750,117000" +"184250,117000" +] +) +start &92 +end &112 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 787,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 788,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,115600,184800,117000" +st "sampleY1" +blo "178000,116800" +tm "WireNameMgr" +) +) +on &31 +) +*247 (Wire +uid 789,0 +shape (OrthoPolyLine +uid 790,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,119000,184250,119000" +pts [ +"177750,119000" +"184250,119000" +] +) +start &93 +end &113 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 791,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 792,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,117600,184800,119000" +st "sampleY2" +blo "178000,118800" +tm "WireNameMgr" +) +) +on &32 +) +*248 (Wire +uid 793,0 +shape (OrthoPolyLine +uid 794,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "147000,117000,160250,117000" +pts [ +"147000,117000" +"160250,117000" +] +) +start &49 +end &91 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 797,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 798,0 +va (VaSet +font "Verdana,12,0" +) +xt "148000,115600,154700,117000" +st "samplesY" +blo "148000,116800" +tm "WireNameMgr" +) +) +on &30 +) +*249 (Wire +uid 799,0 +shape (OrthoPolyLine +uid 800,0 +va (VaSet +vasetType 3 +) +xt "157000,123000,160250,123000" +pts [ +"157000,123000" +"160250,123000" +] +) +end &88 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 803,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 804,0 +va (VaSet +font "Verdana,12,0" +) +xt "156000,121600,159800,123000" +st "clock" +blo "156000,122800" +tm "WireNameMgr" +) +) +on &12 +) +*250 (Wire +uid 805,0 +shape (OrthoPolyLine +uid 806,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,123000,216250,123000" +pts [ +"201750,123000" +"216250,123000" +] +) +start &118 +end &149 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 807,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 808,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,121600,206050,123000" +st "dY" +blo "203750,122800" +tm "WireNameMgr" +) +) +on &38 +) +*251 (Wire +uid 809,0 +shape (OrthoPolyLine +uid 810,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,121000,184250,121000" +pts [ +"177750,121000" +"184250,121000" +] +) +start &94 +end &114 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 811,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 812,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,119600,184800,121000" +st "sampleY3" +blo "178000,120800" +tm "WireNameMgr" +) +) +on &33 +) +*252 (Wire +uid 813,0 +shape (OrthoPolyLine +uid 814,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "177750,123000,184250,123000" +pts [ +"177750,123000" +"184250,123000" +] +) +start &95 +end &115 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 815,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 816,0 +va (VaSet +font "Verdana,12,0" +) +xt "178000,121600,184800,123000" +st "sampleY4" +blo "178000,122800" +tm "WireNameMgr" +) +) +on &34 +) +*253 (Wire +uid 817,0 +shape (OrthoPolyLine +uid 818,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,117000,216250,117000" +pts [ +"201750,117000" +"216250,117000" +] +) +start &116 +end &153 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 819,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 820,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,115600,206050,117000" +st "aY" +blo "203750,116800" +tm "WireNameMgr" +) +) +on &35 +) +*254 (Wire +uid 821,0 +shape (OrthoPolyLine +uid 822,0 +va (VaSet +vasetType 3 +) +xt "213000,133000,216250,133000" +pts [ +"213000,133000" +"216250,133000" +] +) +end &147 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 825,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 826,0 +va (VaSet +font "Verdana,12,0" +) +xt "212000,131600,216100,133000" +st "reset" +blo "212000,132800" +tm "WireNameMgr" +) +) +on &17 +) +*255 (Wire +uid 827,0 +shape (OrthoPolyLine +uid 828,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,119000,216250,119000" +pts [ +"201750,119000" +"216250,119000" +] +) +start &117 +end &152 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 829,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 830,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,117600,206050,119000" +st "bY" +blo "203750,118800" +tm "WireNameMgr" +) +) +on &36 +) +*256 (Wire +uid 831,0 +shape (OrthoPolyLine +uid 832,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "201750,121000,216250,121000" +pts [ +"201750,121000" +"216250,121000" +] +) +start &119 +end &151 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 833,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 834,0 +va (VaSet +font "Verdana,12,0" +) +xt "203750,119600,205850,121000" +st "cY" +blo "203750,120800" +tm "WireNameMgr" +) +) +on &37 +) +*257 (Wire +uid 835,0 +shape (OrthoPolyLine +uid 836,0 +va (VaSet +vasetType 3 +) +xt "261000,123000,264250,123000" +pts [ +"261000,123000" +"264250,123000" +] +) +end &187 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 839,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 840,0 +va (VaSet +font "Verdana,12,0" +) +xt "260000,121600,264100,123000" +st "reset" +blo "260000,122800" +tm "WireNameMgr" +) +) +on &17 +) +*258 (Wire +uid 841,0 +shape (OrthoPolyLine +uid 842,0 +va (VaSet +vasetType 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+xt "2000,123400,16900,124400" +st "SIGNAL selControl : std_ulogic" +) +) +*17 (Net +uid 1055,0 +decl (Decl +n "selSpeed" +t "std_ulogic" +o 25 +suid 35,0 +) +declText (MLText +uid 1056,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,124200,17100,125200" +st "SIGNAL selSpeed : std_ulogic" +) +) +*18 (Net +uid 1063,0 +decl (Decl +n "selX" +t "std_ulogic" +o 26 +suid 36,0 +) +declText (MLText +uid 1064,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,125000,16300,126000" +st "SIGNAL selX : std_ulogic" +) +) +*19 (Net +uid 1071,0 +decl (Decl +n "selY" +t "std_ulogic" +o 27 +suid 37,0 +) +declText (MLText +uid 1072,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,125800,16300,126800" +st "SIGNAL selY : std_ulogic" +) +) +*20 (Net +uid 1348,0 +decl (Decl +n "run" +t "std_ulogic" +o 7 +suid 38,0 +) +declText (MLText +uid 1349,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,106200,13100,107200" +st "run : std_ulogic" +) +) +*21 (Net +uid 1356,0 +decl (Decl +n "updatePattern" +t "std_ulogic" +o 28 +suid 39,0 +) +declText (MLText +uid 1357,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,126600,17700,127600" +st "SIGNAL updatePattern : std_ulogic" +) +) +*22 (Net +uid 1470,0 +decl (Decl +n "patternSize" +t "unsigned" +b "(patternAddressBitNb-1 DOWNTO 0)" +o 23 +suid 40,0 +) +declText (MLText +uid 1471,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,122600,31800,123600" +st "SIGNAL patternSize : unsigned(patternAddressBitNb-1 DOWNTO 0)" +) +) +*23 (Net +uid 1589,0 +decl (Decl +n "dataOut" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 18 +suid 41,0 +) +declText (MLText +uid 1590,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,118600,30400,119600" +st "SIGNAL dataOut : std_logic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*24 (Net +uid 1776,0 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(updatePeriodBitNb-1 DOWNTO 0)" +o 8 +suid 42,0 +) +declText (MLText +uid 1777,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,107000,28400,108000" +st "updatePeriod : unsigned(updatePeriodBitNb-1 DOWNTO 0)" +) +) +*25 (Net +uid 2776,0 +decl (Decl +n "addrX" +t "unsigned" +b "(patternAddressBitNb-1 DOWNTO 0)" +o 13 +suid 44,0 +) +declText (MLText +uid 2777,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,114600,31400,115600" +st "SIGNAL addrX : unsigned(patternAddressBitNb-1 DOWNTO 0)" +) +) +*26 (Net +uid 2850,0 +decl (Decl +n "cntIncrX" +t "std_ulogic" +o 15 +suid 45,0 +) +declText (MLText +uid 2851,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,116200,16700,117200" +st "SIGNAL cntIncrX : std_ulogic" +) +) +*27 (Net +uid 2852,0 +decl (Decl +n "memWrX" +t "std_ulogic" +o 21 +suid 46,0 +) +declText (MLText +uid 2853,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,121000,17800,122000" +st "SIGNAL memWrX : std_ulogic" +) +) +*28 (Net +uid 2854,0 +decl (Decl +n "memEnX" +t "std_ulogic" +o 19 +suid 47,0 +) +declText (MLText +uid 2855,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,119400,17700,120400" +st "SIGNAL memEnX : std_ulogic" +) +) +*29 (Net +uid 3152,0 +decl (Decl +n "memX" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 5 +suid 48,0 +) +declText (MLText +uid 3153,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,104600,28500,105600" +st "memX : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*30 (Net +uid 3827,0 +decl (Decl +n "cntIncrY" +t "std_ulogic" +o 16 +suid 49,0 +) +declText (MLText +uid 3828,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,117000,16700,118000" +st "SIGNAL cntIncrY : std_ulogic" +) +) +*31 (Net +uid 3890,0 +decl (Decl +n "addrY" +t "unsigned" +b "(patternAddressBitNb-1 DOWNTO 0)" +o 14 +suid 50,0 +) +declText (MLText +uid 3891,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,115400,31400,116400" +st "SIGNAL addrY : unsigned(patternAddressBitNb-1 DOWNTO 0)" +) +) +*32 (Net +uid 3892,0 +decl (Decl +n "memWrY" +t "std_ulogic" +o 22 +suid 51,0 +) +declText (MLText +uid 3893,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,121800,17800,122800" +st "SIGNAL memWrY : std_ulogic" +) +) +*33 (Net +uid 3894,0 +decl (Decl +n "memEnY" +t "std_ulogic" +o 20 +suid 52,0 +) +declText (MLText +uid 3895,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,120200,17700,121200" +st "SIGNAL memEnY : std_ulogic" +) +) +*34 (Net +uid 3913,0 +decl (Decl +n "memY" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 6 +suid 53,0 +) +declText (MLText +uid 3914,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,105400,28500,106400" +st "memY : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*35 (PortIoOut +uid 4041,0 +shape (CompositeShape +uid 4042,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4043,0 +sl 0 +ro 270 +xt "143500,3625,145000,4375" +) +(Line +uid 4044,0 +sl 0 +ro 270 +xt "143000,4000,143500,4000" +pts [ +"143000,4000" +"143500,4000" +] +) +] +) +tg (WTG +uid 4045,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4046,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "146000,3300,166900,4700" +st "testOut : (1 TO testOutBitNb)" +blo "146000,4500" +tm "WireNameMgr" +) +) +) +*36 (Net +uid 4053,0 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO testOutBitNb)" +o 4 +suid 54,0 +) +declText (MLText +uid 4054,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,103800,25000,104800" +st "testOut : std_ulogic_vector(1 TO testOutBitNb)" +) +) +*37 (HdlText +uid 4055,0 +optionalChildren [ +*38 (EmbeddedText +uid 4060,0 +commentText (CommentText +uid 4061,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4062,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "120000,3000,134000,25000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4063,0 +va (VaSet +) +xt "120200,3200,134200,24800" +st " +testout(1) <= '0'; +testout(2) <= updatePattern; +testout(3) <= '0'; +testout(4) <= newPolynom; +testout(5) <= '0'; +testout(6) <= '0'; +testout(7) <= '0'; +testout(8) <= '0'; +testout(9) <= '0'; +testout(10) <= addr(1); +testout(11) <= dataIn(0); +--testout(10) <= selControl; +--testout(11) <= selSize; +testout(12) <= selSpeed; +testout(13) <= selX; +testout(14) <= selY; +testout(15) <= cntIncrX; +testout(16) <= cntIncrY; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 22000 +visibleWidth 14000 +) +) +) +] +shape (Rectangle +uid 4056,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "119000,2000,135000,26000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4057,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*39 (Text +uid 4058,0 +va (VaSet +) +xt "119400,26000,122000,27200" +st "eb3" +blo "119400,27000" +tm "HdlTextNameMgr" +) +*40 (Text +uid 4059,0 +va (VaSet +) +xt "119400,27000,120800,28200" +st "3" +blo "119400,28000" +tm "HdlTextNumberMgr" +) +] +) +) +*41 (Net +uid 9646,0 +decl (Decl +n "interpolateLin" +t "std_ulogic" +o 9 +suid 70,0 +) +declText (MLText +uid 9647,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,107800,13900,108800" +st "interpolateLin : std_ulogic" +) +) +*42 (SaComponent +uid 11639,0 +optionalChildren [ +*43 (CptPort +uid 11603,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11604,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,133625,94750,134375" +) +tg (CPTG +uid 11605,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11606,0 +va (VaSet +) +xt "88600,133400,93000,134600" +st "memWr" +ju 2 +blo "93000,134400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memWr" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*44 (CptPort +uid 11607,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11608,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,129625,78000,130375" +) +tg (CPTG +uid 11609,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11610,0 +va (VaSet +) +xt "79000,129400,81200,130600" +st "sel" +blo "79000,130400" +) +) +thePort (LogicalPort +decl (Decl +n "sel" +t "std_ulogic" +o 2 +suid 2,0 +) +) +) +*45 (CptPort +uid 11611,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11612,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,135625,94750,136375" +) +tg (CPTG +uid 11613,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11614,0 +va (VaSet +) +xt "88600,135400,93000,136600" +st "memEn" +ju 2 +blo "93000,136400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memEn" +t "std_ulogic" +o 3 +suid 3,0 +) +) +) +*46 (CptPort +uid 11615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,133625,78000,134375" +) +tg (CPTG +uid 11617,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11618,0 +va (VaSet +) +xt "79000,133400,83100,134600" +st "update" +blo "79000,134400" +) +) +thePort (LogicalPort +decl (Decl +n "update" +t "std_ulogic" +o 4 +suid 4,0 +) +) +) +*47 (CptPort +uid 11619,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11620,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,131625,78000,132375" +) +tg (CPTG +uid 11621,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11622,0 +va (VaSet +) +xt "79000,131400,80800,132600" +st "wr" +blo "79000,132400" +) +) +thePort (LogicalPort +decl (Decl +n "wr" +t "std_ulogic" +o 5 +suid 5,0 +) +) +) +*48 (CptPort +uid 11623,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11624,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,129625,94750,130375" +) +tg (CPTG +uid 11625,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11626,0 +va (VaSet +) +xt "88600,129400,93000,130600" +st "cntIncr" +ju 2 +blo "93000,130400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "cntIncr" +t "std_ulogic" +o 6 +suid 6,0 +) +) +) +*49 (CptPort +uid 11627,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11628,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,135625,78000,136375" +) +tg (CPTG +uid 11629,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11630,0 +va (VaSet +) +xt "79000,135400,85300,136600" +st "newSample" +blo "79000,136400" +) +) +thePort (LogicalPort +decl (Decl +n "newSample" +t "std_ulogic" +o 7 +suid 7,0 +) +) +) +*50 (CptPort +uid 11631,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11632,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,139625,78000,140375" +) +tg (CPTG +uid 11633,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11634,0 +va (VaSet +) +xt "79000,139400,82400,140600" +st "clock" +blo "79000,140400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 8 +suid 8,0 +) +) +) +*51 (CptPort +uid 11635,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11636,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,141625,78000,142375" +) +tg (CPTG +uid 11637,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11638,0 +va (VaSet +) +xt "79000,141400,82300,142600" +st "reset" +blo "79000,142400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 9 +suid 9,0 +) +) +) +] +shape (Rectangle +uid 11640,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "78000,126000,94000,144000" +) +oxt "32000,8000,48000,26000" +ttg (MlTextGroup +uid 11641,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*52 (Text +uid 11642,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,143800,83000,145000" +st "Beamer" +blo "78600,144800" +tm "BdLibraryNameMgr" +) +*53 (Text +uid 11643,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,145000,88300,146200" +st "blockRAMControl" +blo "78600,146000" +tm "CptNameMgr" +) +*54 (Text +uid 11644,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,146200,80900,147400" +st "I19" +blo "78600,147200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 11645,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 11646,0 +text (MLText +uid 11647,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,139800,78000,139800" +) +header "" +) +elements [ +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*55 (SaComponent +uid 11714,0 +optionalChildren [ +*56 (CptPort +uid 11723,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11724,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,183625,94750,184375" +) +tg (CPTG +uid 11725,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11726,0 +va (VaSet +) +xt "88600,183400,93000,184600" +st "memWr" +ju 2 +blo "93000,184400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memWr" +t "std_ulogic" +o 1 +) +) +) +*57 (CptPort +uid 11727,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11728,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,179625,78000,180375" +) +tg (CPTG +uid 11729,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11730,0 +va (VaSet +) +xt "79000,179400,81200,180600" +st "sel" +blo "79000,180400" +) +) +thePort (LogicalPort +decl (Decl +n "sel" +t "std_ulogic" +o 2 +) +) +) +*58 (CptPort +uid 11731,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11732,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,185625,94750,186375" +) +tg (CPTG +uid 11733,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11734,0 +va (VaSet +) +xt "88600,185400,93000,186600" +st "memEn" +ju 2 +blo "93000,186400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memEn" +t "std_ulogic" +o 3 +) +) +) +*59 (CptPort +uid 11735,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11736,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,183625,78000,184375" +) +tg (CPTG +uid 11737,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11738,0 +va (VaSet +) +xt "79000,183400,83100,184600" +st "update" +blo "79000,184400" +) +) +thePort (LogicalPort +decl (Decl +n "update" +t "std_ulogic" +o 4 +) +) +) +*60 (CptPort +uid 11739,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11740,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,181625,78000,182375" +) +tg (CPTG +uid 11741,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11742,0 +va (VaSet +) +xt "79000,181400,80800,182600" +st "wr" +blo "79000,182400" +) +) +thePort (LogicalPort +decl (Decl +n "wr" +t "std_ulogic" +o 5 +) +) +) +*61 (CptPort +uid 11743,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11744,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,179625,94750,180375" +) +tg (CPTG +uid 11745,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 11746,0 +va (VaSet +) +xt "88600,179400,93000,180600" +st "cntIncr" +ju 2 +blo "93000,180400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "cntIncr" +t "std_ulogic" +o 6 +) +) +) +*62 (CptPort +uid 11747,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11748,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,185625,78000,186375" +) +tg (CPTG +uid 11749,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11750,0 +va (VaSet +) +xt "79000,185400,85300,186600" +st "newSample" +blo "79000,186400" +) +) +thePort (LogicalPort +decl (Decl +n "newSample" +t "std_ulogic" +o 7 +) +) +) +*63 (CptPort +uid 11751,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11752,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,189625,78000,190375" +) +tg (CPTG +uid 11753,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11754,0 +va (VaSet +) +xt "79000,189400,82400,190600" +st "clock" +blo "79000,190400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 8 +) +) +) +*64 (CptPort +uid 11755,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 11756,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,191625,78000,192375" +) +tg (CPTG +uid 11757,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 11758,0 +va (VaSet +) +xt "79000,191400,82300,192600" +st "reset" +blo "79000,192400" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 9 +) +) +) +] +shape (Rectangle +uid 11715,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "78000,176000,94000,194000" +) +oxt "32000,8000,48000,26000" +ttg (MlTextGroup +uid 11716,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*65 (Text +uid 11717,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,193800,83000,195000" +st "Beamer" +blo "78600,194800" +tm "BdLibraryNameMgr" +) +*66 (Text +uid 11718,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,195000,88300,196200" +st "blockRAMControl" +blo "78600,196000" +tm "CptNameMgr" +) +*67 (Text +uid 11719,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,196200,80900,197400" +st "I31" +blo "78600,197200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 11720,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 11721,0 +text (MLText +uid 11722,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,189800,78000,189800" +) +header "" +) +elements [ +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*68 (PortIoIn +uid 13128,0 +shape (CompositeShape +uid 13129,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 13130,0 +sl 0 +ro 270 +xt "20000,41625,21500,42375" +) +(Line +uid 13131,0 +sl 0 +ro 270 +xt "21500,42000,22000,42000" +pts [ +"21500,42000" +"22000,42000" +] +) +] +) +tg (WTG +uid 13132,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 13133,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "15500,41500,19000,42900" +st "apbi" +ju 2 +blo "19000,42700" +tm "WireNameMgr" +) +) +) +*69 (Net +uid 13140,0 +decl (Decl +n "apbi" +t "apb_slv_in_type" +o 1 +suid 71,0 +) +declText (MLText +uid 13141,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,101400,15800,102400" +st "apbi : apb_slv_in_type" +) +) +*70 (PortIoOut +uid 13373,0 +shape (CompositeShape +uid 13374,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 13375,0 +sl 0 +ro 90 +xt "20000,25625,21500,26375" +) +(Line +uid 13376,0 +sl 0 +ro 90 +xt "21500,26000,22000,26000" +pts [ +"22000,26000" +"21500,26000" +] +) +] +) +tg (WTG +uid 13377,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 13378,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "15000,25300,19000,26700" +st "apbo" +ju 2 +blo "19000,26500" +tm "WireNameMgr" +) +) +) +*71 (Net +uid 13385,0 +decl (Decl +n "apbo" +t "apb_slv_out_type" +o 3 +suid 72,0 +) +declText (MLText +uid 13386,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,103000,16700,104000" +st "apbo : apb_slv_out_type" +) +) +*72 (PortIoOut +uid 14845,0 +shape (CompositeShape +uid 14846,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14847,0 +sl 0 +ro 270 +xt "134500,115625,136000,116375" +) +(Line +uid 14848,0 +sl 0 +ro 270 +xt "134000,116000,134500,116000" +pts [ +"134000,116000" +"134500,116000" +] +) +] +) +tg (WTG +uid 14849,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14850,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "137000,115300,161100,116700" +st "memY : (signalBitNb-1 DOWNTO 0)" +blo "137000,116500" +tm "WireNameMgr" +) +) +) +*73 (PortIoOut +uid 14851,0 +shape (CompositeShape +uid 14852,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14853,0 +sl 0 +ro 270 +xt "134500,153625,136000,154375" +) +(Line +uid 14854,0 +sl 0 +ro 270 +xt "134000,154000,134500,154000" +pts [ +"134000,154000" +"134500,154000" +] +) +] +) +tg (WTG +uid 14855,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14856,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "137000,153300,161200,154700" +st "memX : (signalBitNb-1 DOWNTO 0)" +blo "137000,154500" +tm "WireNameMgr" +) +) +) +*74 (PortIoOut +uid 14857,0 +shape (CompositeShape +uid 14858,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14859,0 +sl 0 +ro 270 +xt "109750,41625,111250,42375" +) +(Line +uid 14860,0 +sl 0 +ro 270 +xt "109250,42000,109750,42000" +pts [ +"109250,42000" +"109750,42000" +] +) +] +) +tg (WTG +uid 14861,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14862,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "112000,41300,114900,42700" +st "run" +blo "112000,42500" +tm "WireNameMgr" +) +) +) +*75 (PortIoOut +uid 14863,0 +shape (CompositeShape +uid 14864,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14865,0 +sl 0 +ro 270 +xt "109750,69625,111250,70375" +) +(Line +uid 14866,0 +sl 0 +ro 270 +xt "109250,70000,109750,70000" +pts [ +"109250,70000" +"109750,70000" +] +) +] +) +tg (WTG +uid 14867,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14868,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "112000,69300,146500,70700" +st "updatePeriod : (updatePeriodBitNb-1 DOWNTO 0)" +blo "112000,70500" +tm "WireNameMgr" +) +) +) +*76 (PortIoOut +uid 14869,0 +shape (CompositeShape +uid 14870,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 14871,0 +sl 0 +ro 270 +xt "109500,43625,111000,44375" +) +(Line +uid 14872,0 +sl 0 +ro 270 +xt "109000,44000,109500,44000" +pts [ +"109000,44000" +"109500,44000" +] +) +] +) +tg (WTG +uid 14873,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14874,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "112000,43300,122300,44700" +st "interpolateLin" +blo "112000,44500" +tm "WireNameMgr" +) +) +) +*77 (PortIoIn +uid 16542,0 +shape (CompositeShape +uid 16543,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16544,0 +sl 0 +ro 270 +xt "72000,55625,73500,56375" +) +(Line +uid 16545,0 +sl 0 +ro 270 +xt "73500,56000,74000,56000" +pts [ +"73500,56000" +"74000,56000" +] +) +] +) +tg (WTG +uid 16546,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16547,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "66900,55500,71000,56900" +st "reset" +ju 2 +blo "71000,56700" +tm "WireNameMgr" +) +) +) +*78 (Net +uid 16705,0 +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 17 +suid 74,0 +) +declText (MLText +uid 16706,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,117800,30600,118800" +st "SIGNAL dataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*79 (HdlText +uid 16707,0 +optionalChildren [ +*80 (EmbeddedText +uid 16712,0 +commentText (CommentText +uid 16713,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 16714,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "30000,39000,46000,49000" +) +oxt "0,0,18000,5000" +text (MLText +uid 16715,0 +va (VaSet +) +xt "30200,39200,45700,48800" +st " +dataIn <= std_ulogic_vector(apbi.pwdata); +addr <= unsigned(apbi.paddr); +write <= apbi.pwrite and apbi.psel(pindex) and apbi.penable; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 10000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 16708,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "30000,38000,46000,50000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 16709,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*81 (Text +uid 16710,0 +va (VaSet +) +xt "30400,50000,33000,51200" +st "eb8" +blo "30400,51000" +tm "HdlTextNameMgr" +) +*82 (Text +uid 16711,0 +va (VaSet +) +xt "30400,51000,31800,52200" +st "8" +blo "30400,52000" +tm "HdlTextNumberMgr" +) +] +) +) +*83 (Net +uid 16716,0 +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 12 +suid 75,0 +) +declText (MLText +uid 16717,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,113800,28300,114800" +st "SIGNAL addr : unsigned(addressBitNb-1 DOWNTO 0)" +) +) +*84 (HdlText +uid 17145,0 +optionalChildren [ +*85 (EmbeddedText +uid 17150,0 +commentText (CommentText +uid 17151,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 17152,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "58000,87000,66000,93000" +) +oxt "0,0,18000,5000" +text (MLText +uid 17153,0 +va (VaSet +) +xt "58200,87200,65800,92000" +st " +memDataIn <= dataIn(memDataIn'range); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 8000 +) +) +) +] +shape (Rectangle +uid 17146,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "58000,86000,66000,94000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 17147,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*86 (Text +uid 17148,0 +va (VaSet +) +xt "58400,94000,61000,95200" +st "eb9" +blo "58400,95000" +tm "HdlTextNameMgr" +) +*87 (Text +uid 17149,0 +va (VaSet +) +xt "58400,95000,59800,96200" +st "9" +blo "58400,96000" +tm "HdlTextNumberMgr" +) +] +) +) +*88 (Net +uid 17162,0 +decl (Decl +n "memDataIn" +t "std_ulogic_vector" +b "(signalBitNb-1 DOWNTO 0)" +o 30 +suid 77,0 +) +declText (MLText +uid 17163,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,128200,32400,129200" +st "SIGNAL memDataIn : std_ulogic_vector(signalBitNb-1 DOWNTO 0)" +) +) +*89 (Net +uid 17505,0 +decl (Decl +n "write" +t "std_ulogic" +o 29 +suid 78,0 +) +declText (MLText +uid 17506,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,127400,16400,128400" +st "SIGNAL write : std_ulogic" +) +) +*90 (SaComponent +uid 17547,0 +optionalChildren [ +*91 (CptPort +uid 17523,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17524,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,71625,46750,72375" +) +tg (CPTG +uid 17525,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17526,0 +va (VaSet +) +xt "38400,71400,45000,72600" +st "selControl" +ju 2 +blo "45000,72400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selControl" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*92 (CptPort +uid 17527,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17528,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "29250,71625,30000,72375" +) +tg (CPTG +uid 17529,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17530,0 +va (VaSet +) +xt "31000,71400,33900,72600" +st "addr" +blo "31000,72400" +) +) +thePort (LogicalPort +decl (Decl +n "addr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 2 +suid 2,0 +) +) +) +*93 (CptPort +uid 17531,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17532,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,73625,46750,74375" +) +tg (CPTG +uid 17533,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17534,0 +va (VaSet +) +xt "39700,73400,45000,74600" +st "selSpeed" +ju 2 +blo "45000,74400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selSpeed" +t "std_ulogic" +o 3 +suid 4,0 +) +) +) +*94 (CptPort +uid 17535,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17536,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,77625,46750,78375" +) +tg (CPTG +uid 17537,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17538,0 +va (VaSet +) +xt "42100,77400,45000,78600" +st "selX" +ju 2 +blo "45000,78400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selX" +t "std_ulogic" +o 4 +suid 5,0 +) +) +) +*95 (CptPort +uid 17539,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17540,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,79625,46750,80375" +) +tg (CPTG +uid 17541,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17542,0 +va (VaSet +) +xt "42100,79400,45000,80600" +st "selY" +ju 2 +blo "45000,80400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selY" +t "std_ulogic" +o 5 +suid 6,0 +) +) +) +*96 (CptPort +uid 17543,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17544,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "46000,81625,46750,82375" +) +tg (CPTG +uid 17545,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17546,0 +va (VaSet +) +xt "42100,81400,45000,82600" +st "selZ" +ju 2 +blo "45000,82400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selZ" +t "std_ulogic" +o 6 +suid 7,0 +) +) +) +] +shape (Rectangle +uid 17548,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "30000,68000,46000,86000" +) +oxt "34000,9000,50000,27000" +ttg (MlTextGroup +uid 17549,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*97 (Text +uid 17550,0 +va (VaSet +font "Verdana,9,1" +) +xt "30600,85800,35000,87000" +st "Beamer" +blo "30600,86800" +tm "BdLibraryNameMgr" +) +*98 (Text +uid 17551,0 +va (VaSet +font "Verdana,9,1" +) +xt "30600,87000,43500,88200" +st "periphAddressDecoder" +blo "30600,88000" +tm "CptNameMgr" +) +*99 (Text +uid 17552,0 +va (VaSet +font "Verdana,9,1" +) +xt "30600,88200,32300,89400" +st "I2" +blo "30600,89200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 17553,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 17554,0 +text (MLText +uid 17555,0 +va (VaSet +font "Verdana,8,0" +) +xt "30000,89600,50000,90600" +st "addressBitNb = addressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "addressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*100 (HdlText +uid 17860,0 +optionalChildren [ +*101 (EmbeddedText +uid 17865,0 +commentText (CommentText +uid 17866,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 17867,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "30000,23000,46000,29000" +) +oxt "0,0,18000,5000" +text (MLText +uid 17868,0 +va (VaSet +) +xt "30200,23200,44700,29200" +st " +apbo.prdata <= dataOut; + +apbo.pindex <= pindex; + +apbo.pconfig <= ( + 0 => ahb_device_reg ( 16#ff#, 16#3ff#, 0, 1, 7), + 1 => apb_iobar(paddr, pmask) +); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 17861,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "30000,22000,46000,30000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 17862,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*102 (Text +uid 17863,0 +va (VaSet +) +xt "30400,30000,33700,31200" +st "eb10" +blo "30400,31000" +tm "HdlTextNameMgr" +) +*103 (Text +uid 17864,0 +va (VaSet +) +xt "30400,31000,32500,32200" +st "10" +blo "30400,32000" +tm "HdlTextNumberMgr" +) +] +) +) +*104 (SaComponent +uid 18007,0 +optionalChildren [ +*105 (CptPort +uid 17967,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17968,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,41625,94750,42375" +) +tg (CPTG +uid 17969,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17970,0 +va (VaSet +) +xt "90700,41400,93000,42600" +st "run" +ju 2 +blo "93000,42400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "run" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*106 (CptPort +uid 17971,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17972,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,41625,78000,42375" +) +tg (CPTG +uid 17973,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17974,0 +va (VaSet +) +xt "79000,41400,83000,42600" +st "dataIn" +blo "79000,42400" +) +) +thePort (LogicalPort +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 2 +suid 2,0 +) +) +) +*107 (CptPort +uid 17975,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17976,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,47625,94750,48375" +) +tg (CPTG +uid 17977,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 17978,0 +va (VaSet +) +xt "84500,47400,93000,48600" +st "updatePattern" +ju 2 +blo "93000,48400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "updatePattern" +t "std_ulogic" +o 3 +suid 3,0 +) +) +) +*108 (CptPort +uid 17979,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 17980,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,43625,78000,44375" +) +tg (CPTG +uid 17981,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 17982,0 +va (VaSet +) +xt "79000,43400,83800,44600" +st "dataOut" +blo "79000,44400" +) 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"positive" +value "patternAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*118 (SaComponent +uid 18179,0 +optionalChildren [ +*119 (CptPort +uid 18155,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18156,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,109625,78000,110375" +) +tg (CPTG +uid 18157,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18158,0 +va (VaSet +) +xt "79000,109400,80900,110600" +st "en" +blo "79000,110400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*120 (CptPort +uid 18159,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18160,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,113625,78000,114375" +) +tg (CPTG +uid 18161,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18162,0 +va (VaSet +) +xt "79000,113400,82400,114600" +st "clock" +blo "79000,114400" +) +) +thePort (LogicalPort +decl (Decl +n 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"patternAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*128 (SaComponent +uid 18212,0 +optionalChildren [ +*129 (CptPort +uid 18188,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18189,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,159625,78000,160375" +) +tg (CPTG +uid 18190,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18191,0 +va (VaSet +) +xt "79000,159400,80900,160600" +st "en" +blo "79000,160400" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*130 (CptPort +uid 18192,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18193,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,163625,78000,164375" +) +tg (CPTG +uid 18194,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18195,0 +va (VaSet +) +xt "79000,163400,82400,164600" +st "clock" +blo "79000,164400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t 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"0,32896,0" +lineWidth 2 +) +xt "78000,152000,94000,168000" +) +oxt "38000,13000,54000,29000" +ttg (MlTextGroup +uid 18214,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*135 (Text +uid 18215,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,167800,83000,169000" +st "Beamer" +blo "78600,168800" +tm "BdLibraryNameMgr" +) +*136 (Text +uid 18216,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,169000,93200,170200" +st "blockRAMAddressCounter" +blo "78600,170000" +tm "CptNameMgr" +) +*137 (Text +uid 18217,0 +va (VaSet +font "Verdana,9,1" +) +xt "78600,170200,80900,171400" +st "I30" +blo "78600,171200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 18218,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 18219,0 +text (MLText +uid 18220,0 +va (VaSet +font "Verdana,8,0" +) +xt "78000,171600,100900,172600" +st "addressBitNb = patternAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "patternAddressBitNb" +) +] +) +ordering 1 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*138 (SaComponent +uid 18249,0 +optionalChildren [ +*139 (CptPort +uid 18221,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18222,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94000,69625,94750,70375" +) +tg (CPTG +uid 18223,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18224,0 +va (VaSet +) +xt "85000,69400,93000,70600" +st "updatePeriod" +ju 2 +blo "93000,70400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "updatePeriod" +t "unsigned" +b "(updatePeriodBitNb-1 DOWNTO 0)" +o 1 +suid 1,0 +) +) +) +*140 (CptPort +uid 18225,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18226,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77250,69625,78000,70375" +) +tg (CPTG +uid 18227,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18228,0 +va (VaSet +) +xt "79000,69400,83000,70600" +st "dataIn" +blo "79000,70400" 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"65600,43600,66400,44400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 1584,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "46000,26000,66000,76000" +pts [ +"66000,76000" +"66000,26000" +"46000,26000" +] +) +end &100 +sat 16 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1587,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1588,0 +va (VaSet +font "Verdana,12,0" +) +xt "49000,24600,55000,26000" +st "dataOut" +blo "49000,25800" +tm "WireNameMgr" +) +) +on &23 +) +*189 (Wire +uid 1732,0 +shape (OrthoPolyLine +uid 1733,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "62000,70000,77250,70000" +pts [ +"62000,70000" +"77250,70000" +] +) +start &184 +end &140 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1734,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1735,0 +va (VaSet +font "Verdana,12,0" +) +xt "72250,68600,77250,70000" +st "dataIn" +blo "72250,69800" +tm "WireNameMgr" +) +) +on &78 +) +*190 (Wire +uid 1738,0 +shape (OrthoPolyLine +uid 1739,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "66000,72000,77250,72000" +pts [ +"66000,72000" +"77250,72000" +] +) +start &187 +end &141 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1740,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1741,0 +va (VaSet +font "Verdana,12,0" +) +xt "71250,70600,77250,72000" +st "dataOut" +blo "71250,71800" +tm "WireNameMgr" +) +) +on &23 +) +*191 (Wire +uid 1744,0 +shape (OrthoPolyLine +uid 1745,0 +va (VaSet +vasetType 3 +) +xt "74000,84000,77250,84000" +pts [ +"74000,84000" +"77250,84000" +] +) +end &144 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1750,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1751,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,82600,78100,84000" +st "reset" +blo "74000,83800" +tm "WireNameMgr" +) +) +on &14 +) +*192 (Wire +uid 1752,0 +shape (OrthoPolyLine +uid 1753,0 +va (VaSet +vasetType 3 +) +xt "74000,82000,77250,82000" +pts [ +"74000,82000" +"77250,82000" +] +) +end &143 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1758,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1759,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,80600,77800,82000" +st "clock" +blo "74000,81800" +tm "WireNameMgr" +) +) +on &13 +) +*193 (Wire +uid 1778,0 +shape (OrthoPolyLine +uid 1779,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "94750,70000,109250,70000" +pts [ +"94750,70000" +"109250,70000" +] +) +start &139 +end &75 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1782,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1783,0 +va (VaSet +font "Verdana,12,0" +) +xt "96000,68600,106100,70000" +st "updatePeriod" +blo "96000,69800" +tm "WireNameMgr" +) +) +on &24 +) +*194 (Wire +uid 2478,0 +shape (OrthoPolyLine +uid 2479,0 +va (VaSet +vasetType 3 +) +xt "106000,166000,109250,166000" +pts [ +"106000,166000" +"109250,166000" +] +) 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0 +tg (WTG +uid 2640,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2641,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,158600,109400,160000" +st "memWrX" +blo "103000,159800" +tm "WireNameMgr" +) +) +on &27 +) +*197 (Wire +uid 2644,0 +shape (OrthoPolyLine +uid 2645,0 +va (VaSet +vasetType 3 +) +xt "94750,162000,109250,186000" +pts [ +"94750,186000" +"104000,186000" +"104000,162000" +"109250,162000" +] +) +start &58 +end &153 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2646,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2647,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,160600,109200,162000" +st "memEnX" +blo "103000,161800" +tm "WireNameMgr" +) +) +on &28 +) +*198 (Wire +uid 2648,0 +shape (OrthoPolyLine +uid 2649,0 +va (VaSet +vasetType 3 +) +xt "70000,184000,77250,184000" +pts [ +"70000,184000" +"77250,184000" +] +) +end &59 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2654,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2655,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,182600,79800,184000" +st "updatePattern" +blo "69000,183800" +tm "WireNameMgr" +) +) +on &21 +) +*199 (Wire +uid 2772,0 +shape (OrthoPolyLine +uid 2773,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "94750,156000,109250,156000" +pts [ +"94750,156000" +"109250,156000" +] +) +start &133 +end &157 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2774,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2775,0 +va (VaSet +font "Verdana,12,0" +) +xt "105000,154600,109500,156000" +st "addrX" +blo "105000,155800" +tm "WireNameMgr" +) +) +on &25 +) +*200 (Wire +uid 2778,0 +shape (OrthoPolyLine +uid 2779,0 +va (VaSet +vasetType 3 +) +xt "74000,166000,77250,166000" +pts [ +"74000,166000" +"77250,166000" +] +) +end &131 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2784,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2785,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,164600,78100,166000" +st "reset" +blo "74000,165800" +tm "WireNameMgr" +) +) +on &14 +) +*201 (Wire +uid 2786,0 +shape (OrthoPolyLine +uid 2787,0 +va (VaSet +vasetType 3 +) +xt "74000,164000,77250,164000" +pts [ +"74000,164000" +"77250,164000" +] +) +end &130 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2792,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2793,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,162600,77800,164000" +st "clock" +blo "74000,163800" +tm "WireNameMgr" +) +) +on &13 +) +*202 (Wire +uid 2844,0 +shape (OrthoPolyLine +uid 2845,0 +va (VaSet +vasetType 3 +) +xt "72000,160000,98000,180000" +pts [ +"94750,180000" +"98000,180000" +"98000,174000" +"72000,174000" +"72000,160000" +"77250,160000" +] +) +start &61 +end &129 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2846,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2847,0 +va (VaSet +font "Verdana,12,0" +) +xt "72000,158600,77900,160000" +st "cntIncrX" +blo "72000,159800" +tm "WireNameMgr" +) +) +on &26 +) +*203 (Wire +uid 2860,0 +shape (OrthoPolyLine +uid 2861,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "66000,44000,77250,44000" +pts [ +"66000,44000" +"77250,44000" +] +) +start &188 +end &108 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2862,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2863,0 +va (VaSet +font "Verdana,12,0" +) +xt "71250,42600,77250,44000" +st "dataOut" +blo "71250,43800" +tm "WireNameMgr" +) +) +on &23 +) +*204 (Wire +uid 2866,0 +shape (OrthoPolyLine +uid 2867,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "70000,156000,77250,156000" +pts [ +"70000,156000" +"77250,156000" +] +) +end &134 +sat 16 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2872,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2873,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,154600,77900,156000" +st "patternSize" +blo "69000,155800" +tm "WireNameMgr" +) +) +on &22 +) +*205 (Wire +uid 2919,0 +shape (OrthoPolyLine +uid 2920,0 +va (VaSet +vasetType 3 +) +xt "70000,186000,77250,186000" +pts [ +"77250,186000" +"70000,186000" +] +) +start &62 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2925,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2926,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,184600,78600,186000" +st "newPolynom" +blo "69000,185800" +tm "WireNameMgr" +) +) +on &15 +) +*206 (Wire +uid 2996,0 +shape (OrthoPolyLine +uid 2997,0 +va (VaSet +vasetType 3 +) +xt "74000,192000,77250,192000" +pts [ +"74000,192000" +"77250,192000" +] +) +end &64 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3002,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3003,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,190600,78100,192000" +st "reset" +blo "74000,191800" +tm "WireNameMgr" +) +) +on &14 +) +*207 (Wire +uid 3004,0 +shape (OrthoPolyLine +uid 3005,0 +va (VaSet +vasetType 3 +) +xt "74000,190000,77250,190000" +pts [ +"74000,190000" +"77250,190000" +] +) +end &63 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3010,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3011,0 +va (VaSet +font "Verdana,12,0" +) +xt "74000,188600,77800,190000" +st "clock" +blo "74000,189800" +tm "WireNameMgr" +) +) +on &13 +) +*208 (Wire +uid 3094,0 +shape (OrthoPolyLine +uid 3095,0 +va (VaSet +vasetType 3 +) +xt "70000,158000,77250,158000" +pts [ +"70000,158000" +"77250,158000" +] +) +end &132 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3100,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3101,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,156600,79800,158000" +st "updatePattern" +blo "69000,157800" +tm "WireNameMgr" +) +) +on &21 +) +*209 (Wire +uid 3146,0 +shape (OrthoPolyLine +uid 3147,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "126750,154000,134000,154000" +pts [ +"126750,154000" +"134000,154000" +] +) +start &152 +end &73 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3150,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3151,0 +va (VaSet +font "Verdana,12,0" +) +xt "128000,152600,132600,154000" +st "memX" +blo "128000,153800" +tm "WireNameMgr" +) +) +on &29 +) +*210 (Wire +uid 3751,0 +shape (OrthoPolyLine +uid 3752,0 +va (VaSet +vasetType 3 +) +xt "106000,130000,109250,130000" +pts [ +"106000,130000" +"109250,130000" +] +) +end &166 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3755,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3756,0 +va (VaSet +font "Verdana,12,0" +) +xt "106000,128600,110100,130000" +st "reset" +blo "106000,129800" +tm "WireNameMgr" +) +) +on &14 +) +*211 (Wire +uid 3757,0 +shape (OrthoPolyLine +uid 3758,0 +va (VaSet +vasetType 3 +) +xt "106000,128000,109250,128000" +pts [ +"106000,128000" +"109250,128000" +] +) +end &165 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3761,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3762,0 +va (VaSet +font "Verdana,12,0" +) +xt "106000,126600,109800,128000" +st "clock" +blo "106000,127800" +tm "WireNameMgr" +) +) +on &13 +) +*212 (Wire +uid 3763,0 +shape (OrthoPolyLine +uid 3764,0 +va (VaSet +vasetType 3 +) +xt "70000,134000,77250,134000" +pts [ +"70000,134000" +"77250,134000" +] +) +end &46 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3767,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3768,0 +va (VaSet +font "Verdana,12,0" +) +xt "69000,132600,79800,134000" +st "updatePattern" +blo "69000,133800" +tm "WireNameMgr" +) +) +on &21 +) +*213 (Wire +uid 3769,0 +shape (OrthoPolyLine +uid 3770,0 +va (VaSet +vasetType 3 +) +xt "94750,124000,109250,136000" +pts [ +"94750,136000" +"102000,136000" +"102000,124000" +"109250,124000" +] +) +start &45 +end &164 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3771,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3772,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,122600,109100,124000" +st "memEnY" +blo "103000,123800" +tm "WireNameMgr" +) +) +on &33 +) +*214 (Wire +uid 3773,0 +shape (OrthoPolyLine +uid 3774,0 +va (VaSet +vasetType 3 +) +xt "94750,122000,109250,134000" +pts [ +"94750,134000" +"100000,134000" +"100000,122000" +"109250,122000" +] +) +start &43 +end &167 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3775,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3776,0 +va (VaSet +font "Verdana,12,0" +) +xt "103000,120600,109300,122000" +st "memWrY" +blo "103000,121800" +tm "WireNameMgr" +) +) +on &32 +) +*215 (Wire +uid 3777,0 +shape (OrthoPolyLine +uid 3778,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "94750,106000,109250,118000" +pts [ +"94750,106000" +"98000,106000" +"98000,118000" +"109250,118000" +] +) +start &123 +end &168 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG 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16725,0 +va (VaSet +) +xt "85000,15400,85000,15400" +) +header "" +) +elements [ +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*44 (SaComponent +uid 16806,0 +optionalChildren [ +*45 (CptPort +uid 16815,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16816,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "141000,22625,141750,23375" +) +tg (CPTG +uid 16817,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16818,0 +va (VaSet +font "Verdana,12,0" +) +xt "136500,22300,140000,23700" +st "hSel" +ju 2 +blo "140000,23500" +) +) +thePort (LogicalPort +decl (Decl +n "hSel" +t "std_ulogic_vector" +b "( 1 TO ahbSlaveNb )" +o 5 +) +) +) +*46 (CptPort +uid 16819,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16820,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "141000,26625,141750,27375" +) +tg (CPTG +uid 16821,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16822,0 +va (VaSet +font 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(Text +uid 16810,0 +va (VaSet +) +xt "125100,35700,133900,36900" +st "ahbMultiplexor" +blo "125100,36700" +tm "CptNameMgr" +) +*54 (Text +uid 16811,0 +va (VaSet +) +xt "125100,36700,129000,37900" +st "I_mux" +blo "125100,37700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 16812,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 16813,0 +text (MLText +uid 16814,0 +va (VaSet +) +xt "125000,37400,125000,37400" +) +header "" +) +elements [ +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*55 (SaComponent +uid 16843,0 +optionalChildren [ +*56 (CptPort +uid 16852,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16853,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "124250,-1375,125000,-625" +) +tg (CPTG +uid 16854,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16855,0 +va (VaSet +font "Verdana,12,0" +) +xt "126000,-1700,130500,-300" +st "hAddr" +blo "126000,-500" +) +) +thePort (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 1 +) +) +) +*57 (CptPort +uid 16856,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16857,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "141000,-1375,141750,-625" +) +tg (CPTG +uid 16858,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16859,0 +va (VaSet +font "Verdana,12,0" +) +xt "136500,-1700,140000,-300" +st "hSel" +ju 2 +blo "140000,-500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_ulogic_vector" +b "(1 to ahbSlaveNb)" +o 2 +) +) +) +] +shape (Rectangle +uid 16844,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "125000,-5000,141000,3000" +) +oxt "39000,14000,55000,22000" +ttg (MlTextGroup +uid 16845,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*58 (Text +uid 16846,0 +va (VaSet +) +xt "125100,2700,129700,3900" +st "AhbLite" +blo "125100,3700" +tm "BdLibraryNameMgr" +) +*59 (Text +uid 16847,0 +va (VaSet +) +xt "125100,3700,132500,4900" +st "ahbDecoder" +blo "125100,4700" +tm "CptNameMgr" +) +*60 (Text +uid 16848,0 +va (VaSet +) +xt "125100,4700,128700,5900" +st "I_dec" +blo "125100,5700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 16849,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 16850,0 +text (MLText +uid 16851,0 +va (VaSet +) +xt "125000,5400,166000,6600" +st "ahbMemoryLocation = ahbMemoryLocation ( ahbMemoryLocationVector ) " +) +header "" +) +elements [ +(GiElement +name "ahbMemoryLocation" +type "ahbMemoryLocationVector" +value "ahbMemoryLocation" +) +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*61 (SaComponent +uid 16860,0 +optionalChildren [ +*62 (CptPort +uid 16869,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16870,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,-1375,157000,-625" +) +tg (CPTG +uid 16871,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16872,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,-1700,162300,-300" +st "hSelV" +blo "158000,-500" +) +) +thePort (LogicalPort +decl (Decl +n "hSelV" +t "std_ulogic_vector" +b "( 1 TO ahbSlaveNb )" +o 5 +) +) +) +*63 (CptPort +uid 16873,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16874,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,625,157000,1375" +) +tg (CPTG +uid 16875,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16876,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,300,164200,1700" +st "hRDataV" +blo "158000,1500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRDataV" +t "ahbDataVector" +o 1 +) +) +) +*64 (CptPort +uid 16877,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16878,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,2625,173750,3375" +) +tg (CPTG +uid 16879,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16880,0 +va (VaSet +font "Verdana,12,0" +) +xt "166500,2300,172000,3700" +st "hReady" +ju 2 +blo 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+b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +) +) +) +*67 (CptPort +uid 16889,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16890,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,2625,157000,3375" +) +tg (CPTG +uid 16891,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16892,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,2300,164300,3700" +st "hReadyV" +blo "158000,3500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 2 +) +) +) +*68 (CptPort +uid 16893,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16894,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,4625,157000,5375" +) +tg (CPTG +uid 16895,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16896,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,4300,163500,5700" +st "hRespV" +blo "158000,5500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 4 +) +) +) +*69 (CptPort +uid 16897,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16898,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,-1375,173750,-625" +) +tg (CPTG +uid 16899,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16900,0 +va (VaSet +font "Verdana,12,0" +) +xt "168500,-1700,172000,-300" +st "hSel" +ju 2 +blo "172000,-500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 8 +) +) +) +] +shape (Rectangle +uid 16861,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "157000,-5000,173000,9000" +) +oxt "40000,11000,56000,25000" +ttg (MlTextGroup +uid 16862,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*70 (Text +uid 16863,0 +va (VaSet +) +xt "157100,8700,161700,9900" +st "AhbLite" +blo "157100,9700" +tm "BdLibraryNameMgr" +) +*71 (Text +uid 16864,0 +va (VaSet +) +xt "157100,9700,167600,10900" +st "ahbMuxConnector" +blo "157100,10700" +tm "CptNameMgr" +) +*72 (Text +uid 16865,0 +va (VaSet +) +xt "157100,10700,162000,11900" +st "I_connT" +blo "157100,11700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 16866,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 16867,0 +text (MLText +uid 16868,0 +va (VaSet +) +xt "157000,11400,175300,12600" +st "index = gpioIndex ( positive ) " +) +header "" +) +elements [ +(GiElement +name "index" +type "positive" +value "gpioIndex" +) +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*73 (SaComponent +uid 16901,0 +optionalChildren [ +*74 (CptPort +uid 16910,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16911,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,32625,157000,33375" +) +tg (CPTG +uid 16912,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16913,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,32300,162300,33700" +st "hSelV" +blo "158000,33500" +) +) +thePort (LogicalPort +decl (Decl +n "hSelV" +t "std_ulogic_vector" +b "( 1 TO ahbSlaveNb )" +o 5 +) +) +) +*75 (CptPort +uid 16914,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16915,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,34625,157000,35375" +) +tg (CPTG +uid 16916,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16917,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,34300,164200,35700" +st "hRDataV" +blo "158000,35500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRDataV" +t "ahbDataVector" +o 1 +) +) +) +*76 (CptPort +uid 16918,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16919,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,36625,173750,37375" +) +tg (CPTG +uid 16920,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16921,0 +va (VaSet +font "Verdana,12,0" +) +xt "166500,36300,172000,37700" +st "hReady" +ju 2 +blo "172000,37500" +) +) +thePort (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +) +) +) +*77 (CptPort +uid 16922,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16923,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,38625,173750,39375" +) +tg (CPTG +uid 16924,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16925,0 +va (VaSet +font "Verdana,12,0" +) +xt "167300,38300,172000,39700" +st "hResp" +ju 2 +blo "172000,39500" +) +) +thePort (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 3 +) +) +) +*78 (CptPort +uid 16926,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16927,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,34625,173750,35375" +) +tg (CPTG +uid 16928,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16929,0 +va (VaSet +font "Verdana,12,0" +) +xt "166600,34300,172000,35700" +st "hRData" +ju 2 +blo "172000,35500" +) +) +thePort (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +) +) +) +*79 (CptPort +uid 16930,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16931,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,36625,157000,37375" +) +tg (CPTG +uid 16932,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16933,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,36300,164300,37700" +st "hReadyV" +blo "158000,37500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 2 +) +) +) +*80 (CptPort +uid 16934,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16935,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,38625,157000,39375" +) +tg (CPTG +uid 16936,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 16937,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,38300,163500,39700" +st "hRespV" +blo "158000,39500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 4 +) +) +) +*81 (CptPort +uid 16938,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 16939,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,32625,173750,33375" +) +tg (CPTG +uid 16940,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 16941,0 +va (VaSet +font "Verdana,12,0" +) +xt "168500,32300,172000,33700" +st "hSel" +ju 2 +blo "172000,33500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 8 +) +) +) +] +shape (Rectangle +uid 16902,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "157000,29000,173000,43000" +) +oxt "40000,11000,56000,25000" +ttg (MlTextGroup +uid 16903,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*82 (Text +uid 16904,0 +va (VaSet +) +xt "157100,42700,161700,43900" +st "AhbLite" +blo "157100,43700" +tm "BdLibraryNameMgr" +) +*83 (Text +uid 16905,0 +va (VaSet +) +xt "157100,43700,167600,44900" +st "ahbMuxConnector" +blo "157100,44700" +tm "CptNameMgr" +) +*84 (Text +uid 16906,0 +va (VaSet +) +xt "157100,44700,164200,45900" +st "I_connUart" +blo "157100,45700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 16907,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 16908,0 +text (MLText +uid 16909,0 +va (VaSet +) +xt "157000,45400,175200,46600" +st "index = uartIndex ( positive ) " +) +header "" +) +elements [ +(GiElement +name "index" +type "positive" +value "uartIndex" +) +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*85 (Net +uid 17490,0 +decl (Decl +n "int" +t "std_uLogic" +o 13 +suid 87,0 +) +declText (MLText +uid 17491,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,91300,16200,92300" +st "SIGNAL int : std_uLogic" +) +) +*86 (Net +uid 17492,0 +decl (Decl +n "upAddress" +t "unsigned" +b "(ahbAddressBitNb-1 DOWNTO 0)" +o 14 +suid 88,0 +) +declText (MLText +uid 17493,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,92200,30600,93200" +st "SIGNAL upAddress : unsigned(ahbAddressBitNb-1 DOWNTO 0)" +) +) +*87 (Net +uid 17494,0 +decl (Decl +n "upDataOut" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 15 +suid 89,0 +) +declText (MLText +uid 17495,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,93100,33000,94100" +st "SIGNAL upDataOut : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*88 (Net +uid 17496,0 +decl (Decl +n "upDataIn" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 16 +suid 90,0 +) +declText (MLText +uid 17497,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,94000,32700,95000" +st "SIGNAL upDataIn : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*89 (Net +uid 17498,0 +decl (Decl +n "upReadStrobe" +t "std_uLogic" +o 17 +suid 91,0 +) +declText (MLText +uid 17499,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,94900,18200,95900" +st "SIGNAL upReadStrobe : std_uLogic" +) +) +*90 (Net +uid 17500,0 +decl (Decl +n "upWriteStrobe" +t "std_uLogic" +o 18 +suid 92,0 +) +declText (MLText +uid 17501,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,95800,17900,96800" +st "SIGNAL upWriteStrobe : std_uLogic" +) +) +*91 (Net +uid 17502,0 +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 DOWNTO 0)" +o 19 +suid 93,0 +) +declText (MLText +uid 17503,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,96700,30000,97700" +st "SIGNAL hAddr : unsigned(ahbAddressBitNb-1 DOWNTO 0)" +) +) +*92 (Net +uid 17504,0 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 20 +suid 94,0 +) +declText (MLText +uid 17505,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,97600,32800,98600" +st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*93 (Net +uid 17506,0 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 21 +suid 95,0 +) +declText (MLText +uid 17507,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,98500,32600,99500" +st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*94 (Net +uid 17508,0 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 22 +suid 96,0 +) +declText (MLText +uid 17509,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,99400,32600,100400" +st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)" +) +) +*95 (Net +uid 17510,0 +decl (Decl +n "hSize" +t "std_ulogic_vector" +b "(ahbSizeBitNb-1 DOWNTO 0)" +o 23 +suid 97,0 +) +declText (MLText +uid 17511,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,100300,31700,101300" +st "SIGNAL hSize : std_ulogic_vector(ahbSizeBitNb-1 DOWNTO 0)" +) +) +*96 (Net +uid 17512,0 +decl (Decl +n "hBurst" +t "std_ulogic_vector" +b "(ahbBurstBitNb-1 DOWNTO 0)" +o 24 +suid 98,0 +) +declText (MLText +uid 17513,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,101200,32200,102200" +st "SIGNAL hBurst : std_ulogic_vector(ahbBurstBitNb-1 DOWNTO 0)" +) +) +*97 (Net +uid 17514,0 +decl (Decl +n "hProt" +t "std_ulogic_vector" +b "(ahbProtBitNb-1 DOWNTO 0)" +o 25 +suid 99,0 +) +declText (MLText +uid 17515,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,102100,31700,103100" +st "SIGNAL hProt : std_ulogic_vector(ahbProtBitNb-1 DOWNTO 0)" +) +) +*98 (Net +uid 17516,0 +decl (Decl +n "hWrite" +t "std_uLogic" +o 26 +suid 100,0 +) +declText (MLText +uid 17517,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,103000,16900,104000" +st "SIGNAL hWrite : std_uLogic" +) +) +*99 (Net +uid 17518,0 +decl (Decl +n "hReady" +t "std_uLogic" +o 27 +suid 101,0 +) +declText (MLText +uid 17519,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,103900,17400,104900" +st "SIGNAL hReady : std_uLogic" +) +) +*100 (Net +uid 17520,0 +decl (Decl +n "hMastLock" +t "std_uLogic" +o 28 +suid 102,0 +) +declText (MLText +uid 17521,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,104800,17600,105800" +st "SIGNAL hMastLock : std_uLogic" +) +) +*101 (Net +uid 17522,0 +decl (Decl +n "hResp" +t "std_uLogic" +o 29 +suid 103,0 +) +declText (MLText +uid 17523,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,105700,17100,106700" +st "SIGNAL hResp : std_uLogic" +) +) +*102 (Net +uid 17524,0 +decl (Decl +n "hClk" +t "std_uLogic" +o 30 +suid 104,0 +) +declText (MLText +uid 17525,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,106600,16700,107600" +st "SIGNAL hClk : std_uLogic" +) +) +*103 (Net +uid 17526,0 +decl (Decl +n "hReset_n" +t "std_uLogic" +o 31 +suid 105,0 +) +declText (MLText +uid 17527,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,107500,17500,108500" +st "SIGNAL hReset_n : std_uLogic" +) +) +*104 (Net +uid 17528,0 +decl (Decl +n "hSelV" +t "std_ulogic_vector" +b "(1 TO ahbSlaveNb)" +o 32 +suid 106,0 +) +declText (MLText +uid 17529,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,108400,27900,109400" +st "SIGNAL hSelV : std_ulogic_vector(1 TO ahbSlaveNb)" +) +) +*105 (Net +uid 17530,0 +decl (Decl +n "hRDataV" +t "ahbDataVector" +o 33 +suid 107,0 +) +declText (MLText +uid 17531,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,109300,19200,110300" +st "SIGNAL hRDataV : ahbDataVector" +) +) +*106 (Net +uid 17532,0 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 TO ahbSlaveNb)" +o 34 +suid 108,0 +) +declText (MLText +uid 17533,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,110200,28200,111200" +st "SIGNAL hReadyV : std_logic_vector(1 TO ahbSlaveNb)" +) +) +*107 (Net +uid 17534,0 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 TO ahbSlaveNb)" +o 35 +suid 109,0 +) +declText (MLText +uid 17535,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,111100,27900,112100" +st "SIGNAL hRespV : std_logic_vector(1 TO ahbSlaveNb)" +) +) +*108 (Net +uid 17751,0 +decl (Decl +n "clock" +t "std_ulogic" +o 7 +suid 126,0 +) +declText (MLText +uid 17752,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,56200,13200,57200" +st "clock : std_ulogic" +) +) +*109 (Net +uid 17753,0 +decl (Decl +n "reset" +t "std_ulogic" +o 6 +suid 127,0 +) +declText (MLText +uid 17754,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,55300,13200,56300" +st "reset : std_ulogic" +) +) +*110 (SaComponent +uid 18307,0 +optionalChildren [ +*111 (CptPort +uid 18259,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18260,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,24625,189000,25375" +) +tg (CPTG +uid 18261,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18262,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,24300,194500,25700" +st "hAddr" +blo "190000,25500" +) +) +thePort (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 1 +suid 2051,0 +) +) +) +*112 (CptPort +uid 18263,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18264,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,26625,189000,27375" +) +tg (CPTG +uid 18265,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18266,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,26300,195900,27700" +st "hWData" +blo "190000,27500" +) +) +thePort (LogicalPort +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 3 +suid 2053,0 +) +) +) +*113 (CptPort +uid 18267,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18268,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,34625,189000,35375" +) +tg (CPTG +uid 18269,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18270,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,34300,195400,35700" +st "hRData" +blo "190000,35500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +suid 2054,0 +) +) +) +*114 (CptPort +uid 18271,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18272,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,30625,189000,31375" +) +tg (CPTG +uid 18273,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18274,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,30300,195000,31700" +st "hWrite" +blo "190000,31500" +) +) +thePort (LogicalPort +decl (Decl +n "hWrite" +t "std_uLogic" +o 4 +suid 2055,0 +) +) +) +*115 (CptPort +uid 18275,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18276,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,28625,189000,29375" +) +tg (CPTG +uid 18277,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18278,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,28300,195100,29700" +st "hTrans" +blo "190000,29500" +) +) +thePort (LogicalPort +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 2 +suid 2059,0 +) +) +) +*116 (CptPort +uid 18279,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18280,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,36625,189000,37375" +) +tg (CPTG +uid 18281,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18282,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,36300,195500,37700" +st "hReady" +blo "190000,37500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +suid 2061,0 +) +) +) +*117 (CptPort +uid 18283,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18284,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,38625,189000,39375" +) +tg (CPTG +uid 18285,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18286,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,38300,194700,39700" +st "hResp" +blo "190000,39500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hResp" +t "std_uLogic" +o 9 +suid 2062,0 +) +) +) +*118 (CptPort +uid 18287,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18288,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,42625,189000,43375" +) +tg (CPTG +uid 18289,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18290,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,42300,193500,43700" +st "hClk" +blo "190000,43500" +) +) +thePort (LogicalPort +decl (Decl +n "hClk" +t "std_uLogic" +o 5 +suid 2063,0 +) +) +) +*119 (CptPort +uid 18291,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18292,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,44625,189000,45375" +) +tg (CPTG +uid 18293,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18294,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,44300,196800,45700" +st "hReset_n" +blo "190000,45500" +) +) +thePort (LogicalPort +decl (Decl +n "hReset_n" +t "std_uLogic" +o 8 +suid 2064,0 +) +) +) +*120 (CptPort +uid 18295,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18296,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "205000,24625,205750,25375" +) +tg (CPTG +uid 18297,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18298,0 +va (VaSet +font "Verdana,12,0" +) +xt "200900,24300,204000,25700" +st "TxD" +ju 2 +blo "204000,25500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "TxD" +t "std_ulogic" +o 10 +suid 2065,0 +) +) +) +*121 (CptPort +uid 18299,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18300,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,32625,189000,33375" +) +tg (CPTG +uid 18301,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18302,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,32300,193500,33700" +st "hSel" +blo "190000,33500" +) +) +thePort (LogicalPort +decl (Decl +n "hSel" +t "std_uLogic" +o 11 +suid 2066,0 +) +) +) +*122 (CptPort +uid 18303,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18304,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "205000,26625,205750,27375" +) +tg (CPTG +uid 18305,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18306,0 +va (VaSet +font "Verdana,12,0" +) +xt "200800,26300,204000,27700" +st "RxD" +ju 2 +blo "204000,27500" +) +) +thePort (LogicalPort +decl (Decl +n "RxD" +t "std_ulogic" +o 12 +suid 2067,0 +) +) +) +] +shape (Rectangle +uid 18308,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "189000,21000,205000,47000" +) +oxt "47000,16000,63000,42000" +ttg (MlTextGroup +uid 18309,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*123 (Text +uid 18310,0 +va (VaSet +) +xt "189100,46700,200700,47900" +st "AhbLiteComponents" +blo "189100,47700" +tm "BdLibraryNameMgr" +) +*124 (Text +uid 18311,0 +va (VaSet +) +xt "189100,47700,193800,48900" +st "ahbUart" +blo "189100,48700" +tm "CptNameMgr" +) +*125 (Text +uid 18312,0 +va (VaSet +) +xt "189100,48700,193900,49900" +st "I_UART" +blo "189100,49700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 18313,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 18314,0 +text (MLText +uid 18315,0 +va (VaSet +font "Verdana,8,0" +) +xt "189000,51000,203300,53000" +st "txFifoDepth = 8 ( positive ) +rxFifoDepth = 1 ( positive ) " +) +header "" +) +elements [ +(GiElement +name "txFifoDepth" +type "positive" +value "8" +) +(GiElement +name "rxFifoDepth" +type "positive" +value "1" +) +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*126 (PortIoOut +uid 18316,0 +shape (CompositeShape +uid 18317,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 18318,0 +sl 0 +ro 270 +xt "213500,24625,215000,25375" +) +(Line +uid 18319,0 +sl 0 +ro 270 +xt "213000,25000,213500,25000" +pts [ +"213000,25000" +"213500,25000" +] +) +] +) +tg (WTG +uid 18320,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18321,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "216000,24300,219100,25700" +st "TxD" +blo "216000,25500" +tm "WireNameMgr" +) +) +) +*127 (PortIoIn +uid 18340,0 +shape (CompositeShape +uid 18341,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 18342,0 +sl 0 +ro 90 +xt "213500,26625,215000,27375" +) +(Line +uid 18343,0 +sl 0 +ro 90 +xt "213000,27000,213500,27000" +pts [ +"213500,27000" +"213000,27000" +] +) +] +) +tg (WTG +uid 18344,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18345,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "216000,26300,219200,27700" +st "RxD" +blo "216000,27500" +tm "WireNameMgr" +) +) +) +*128 (Net +uid 18346,0 +decl (Decl +n "TxD" +t "std_ulogic" +o 1 +suid 128,0 +) +declText (MLText +uid 18347,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,50800,13400,51800" +st "TxD : std_ulogic" +) +) +*129 (Net +uid 18348,0 +decl (Decl +n "RxD" +t "std_ulogic" +o 2 +suid 129,0 +) +declText (MLText +uid 18349,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,51700,13500,52700" +st "RxD : std_ulogic" +) +) +*130 (Net +uid 18350,0 +decl (Decl +n "hSelUart" +t "std_uLogic" +o 43 +suid 130,0 +) +declText (MLText +uid 18351,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,118300,17100,119300" +st "SIGNAL hSelUart : std_uLogic" +) +) +*131 (Net +uid 18352,0 +decl (Decl +n "hRDataUart" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 41 +suid 131,0 +) +declText (MLText +uid 18353,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,116500,33100,117500" +st "SIGNAL hRDataUart : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*132 (Net +uid 18354,0 +decl (Decl +n "hReadyUart" +t "std_uLogic" +o 47 +suid 132,0 +) +declText (MLText +uid 18355,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,121900,17900,122900" +st "SIGNAL hReadyUart : std_uLogic" +) +) +*133 (Net +uid 18356,0 +decl (Decl +n "hRespUart" +t "std_uLogic" +o 44 +suid 133,0 +) +declText (MLText +uid 18357,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,119200,17600,120200" +st "SIGNAL hRespUart : std_uLogic" +) +) +*134 (SaComponent +uid 18370,0 +optionalChildren [ +*135 (CptPort +uid 18379,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18380,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,66625,157000,67375" +) +tg (CPTG +uid 18381,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18382,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,66300,162300,67700" +st "hSelV" +blo "158000,67500" +) +) +thePort (LogicalPort +decl (Decl +n "hSelV" +t "std_ulogic_vector" +b "( 1 TO ahbSlaveNb )" +o 5 +) +) +) +*136 (CptPort +uid 18383,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18384,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,68625,157000,69375" +) +tg (CPTG +uid 18385,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18386,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,68300,164200,69700" +st "hRDataV" +blo "158000,69500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRDataV" +t "ahbDataVector" +o 1 +) +) +) +*137 (CptPort +uid 18387,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18388,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,70625,173750,71375" +) +tg (CPTG +uid 18389,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18390,0 +va (VaSet +font "Verdana,12,0" +) +xt "166500,70300,172000,71700" +st "hReady" +ju 2 +blo "172000,71500" +) +) +thePort (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +) +) +) +*138 (CptPort +uid 18391,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18392,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,72625,173750,73375" +) +tg (CPTG +uid 18393,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18394,0 +va (VaSet +font "Verdana,12,0" +) +xt "167300,72300,172000,73700" +st "hResp" +ju 2 +blo "172000,73500" +) +) +thePort (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 3 +) +) +) +*139 (CptPort +uid 18395,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18396,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,68625,173750,69375" +) +tg (CPTG +uid 18397,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18398,0 +va (VaSet +font "Verdana,12,0" +) +xt "166600,68300,172000,69700" +st "hRData" +ju 2 +blo "172000,69500" +) +) +thePort (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +) +) +) +*140 (CptPort +uid 18399,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18400,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,70625,157000,71375" +) +tg (CPTG +uid 18401,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18402,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,70300,164300,71700" +st "hReadyV" +blo "158000,71500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 2 +) +) +) +*141 (CptPort +uid 18403,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18404,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "156250,72625,157000,73375" +) +tg (CPTG +uid 18405,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18406,0 +va (VaSet +font "Verdana,12,0" +) +xt "158000,72300,163500,73700" +st "hRespV" +blo "158000,73500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 4 +) +) +) +*142 (CptPort +uid 18407,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18408,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "173000,66625,173750,67375" +) +tg (CPTG +uid 18409,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18410,0 +va (VaSet +font "Verdana,12,0" +) +xt "168500,66300,172000,67700" +st "hSel" +ju 2 +blo "172000,67500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 8 +) +) +) +] +shape (Rectangle +uid 18371,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "157000,63000,173000,77000" +) +oxt "40000,11000,56000,25000" +ttg (MlTextGroup +uid 18372,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*143 (Text +uid 18373,0 +va (VaSet +) +xt "157100,76700,161700,77900" +st "AhbLite" +blo "157100,77700" +tm "BdLibraryNameMgr" +) +*144 (Text +uid 18374,0 +va (VaSet +) +xt "157100,77700,167600,78900" +st "ahbMuxConnector" +blo "157100,78700" +tm "CptNameMgr" +) +*145 (Text +uid 18375,0 +va (VaSet +) +xt "157100,78700,164800,79900" +st "I_connBeam" +blo "157100,79700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 18376,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 18377,0 +text (MLText +uid 18378,0 +va (VaSet +) +xt "157000,79400,176900,80600" +st "index = beamerIndex ( positive ) " +) +header "" +) +elements [ +(GiElement +name "index" +type "positive" +value "beamerIndex" +) +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*146 (Net +uid 18467,0 +decl (Decl +n "hSelBeamer" +t "std_uLogic" +o 42 +suid 134,0 +) +declText (MLText +uid 18468,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,117400,17900,118400" +st "SIGNAL hSelBeamer : std_uLogic" +) +) +*147 (Net +uid 18469,0 +decl (Decl +n "hRDataBeamer" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 40 +suid 135,0 +) +declText (MLText +uid 18470,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,115600,33900,116600" +st "SIGNAL hRDataBeamer : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*148 (Net +uid 18471,0 +decl (Decl +n "hReadyBeamer" +t "std_uLogic" +o 46 +suid 136,0 +) +declText (MLText +uid 18472,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,121000,18700,122000" +st "SIGNAL hReadyBeamer : std_uLogic" +) +) +*149 (Net +uid 18473,0 +decl (Decl +n "hRespBeamer" +t "std_uLogic" +o 45 +suid 137,0 +) +declText (MLText +uid 18474,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,120100,18400,121100" +st "SIGNAL hRespBeamer : std_uLogic" +) +) +*150 (SaComponent +uid 18666,0 +optionalChildren [ +*151 (CptPort +uid 18614,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18615,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,-9375,189000,-8625" +) +tg (CPTG +uid 18616,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18617,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,-9700,194500,-8300" +st "hAddr" +blo "190000,-8500" +) +) +thePort (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 1 +suid 2051,0 +) +) +) +*152 (CptPort +uid 18618,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18619,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,-7375,189000,-6625" +) +tg (CPTG +uid 18620,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18621,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,-7700,195900,-6300" +st "hWData" +blo "190000,-6500" +) +) +thePort (LogicalPort +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 3 +suid 2053,0 +) +) +) +*153 (CptPort +uid 18622,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18623,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,625,189000,1375" +) +tg (CPTG +uid 18624,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18625,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,300,195400,1700" +st "hRData" +blo "190000,1500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +suid 2054,0 +) +) +) +*154 (CptPort +uid 18626,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18627,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,-3375,189000,-2625" +) +tg (CPTG +uid 18628,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18629,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,-3700,195000,-2300" +st "hWrite" +blo "190000,-2500" +) +) +thePort (LogicalPort +decl (Decl +n "hWrite" +t "std_uLogic" +o 4 +suid 2055,0 +) +) +) +*155 (CptPort +uid 18630,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18631,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,-5375,189000,-4625" +) +tg (CPTG +uid 18632,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18633,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,-5700,195100,-4300" +st "hTrans" +blo "190000,-4500" +) +) +thePort (LogicalPort +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 2 +suid 2059,0 +) +) +) +*156 (CptPort +uid 18634,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18635,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,2625,189000,3375" +) +tg (CPTG +uid 18636,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18637,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,2300,195500,3700" +st "hReady" +blo "190000,3500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +suid 2061,0 +) +) +) +*157 (CptPort +uid 18638,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18639,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,4625,189000,5375" +) +tg (CPTG +uid 18640,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18641,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,4300,194700,5700" +st "hResp" +blo "190000,5500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hResp" +t "std_uLogic" +o 9 +suid 2062,0 +) +) +) +*158 (CptPort +uid 18642,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18643,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,8625,189000,9375" +) +tg (CPTG +uid 18644,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18645,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,8300,193500,9700" +st "hClk" +blo "190000,9500" +) +) +thePort (LogicalPort +decl (Decl +n "hClk" +t "std_uLogic" +o 5 +suid 2063,0 +) +) +) +*159 (CptPort +uid 18646,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18647,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,10625,189000,11375" +) +tg (CPTG +uid 18648,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18649,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,10300,196800,11700" +st "hReset_n" +blo "190000,11500" +) +) +thePort (LogicalPort +decl (Decl +n "hReset_n" +t "std_uLogic" +o 8 +suid 2064,0 +) +) +) +*160 (CptPort +uid 18650,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18651,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "205000,-7375,205750,-6625" +) +tg (CPTG +uid 18652,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18653,0 +va (VaSet +font "Verdana,12,0" +) +xt "199800,-7700,204000,-6300" +st "ioOut" +ju 2 +blo "204000,-6500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ioOut" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 10 +suid 2065,0 +) +) +) +*161 (CptPort +uid 18654,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18655,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "188250,-1375,189000,-625" +) +tg (CPTG +uid 18656,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18657,0 +va (VaSet +font "Verdana,12,0" +) +xt "190000,-1700,193500,-300" +st "hSel" +blo "190000,-500" +) +) +thePort (LogicalPort +decl (Decl +n "hSel" +t "std_uLogic" +o 11 +suid 2066,0 +) +) +) +*162 (CptPort +uid 18658,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18659,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "205000,-5375,205750,-4625" +) +tg (CPTG +uid 18660,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18661,0 +va (VaSet +font "Verdana,12,0" +) +xt "200800,-5700,204000,-4300" +st "ioIn" +ju 2 +blo "204000,-4500" +) +) +thePort (LogicalPort +decl (Decl +n "ioIn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 12 +suid 2067,0 +) +) +) +*163 (CptPort +uid 18662,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18663,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "205000,-9375,205750,-8625" +) +tg (CPTG +uid 18664,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18665,0 +va (VaSet +font "Verdana,12,0" +) +xt "200500,-9700,204000,-8300" +st "ioEn" +ju 2 +blo "204000,-8500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ioEn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 13 +suid 2068,0 +) +) +) +] +shape (Rectangle +uid 18667,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "189000,-13000,205000,13000" +) +oxt "47000,16000,63000,42000" +ttg (MlTextGroup +uid 18668,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*164 (Text +uid 18669,0 +va (VaSet +) +xt "189100,12700,200700,13900" +st "AhbLiteComponents" +blo "189100,13700" +tm "BdLibraryNameMgr" +) +*165 (Text +uid 18670,0 +va (VaSet +) +xt "189100,13700,193900,14900" +st "ahbGpio" +blo "189100,14700" +tm "CptNameMgr" +) +*166 (Text +uid 18671,0 +va (VaSet +) +xt "189100,14700,193800,15900" +st "I_GPIO" +blo "189100,15700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 18672,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 18673,0 +text (MLText +uid 18674,0 +va (VaSet +font "Verdana,8,0" +) +xt "189000,17000,201700,18000" +st "ioNb = ioNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "ioNb" +type "positive" +value "ioNb" +) +] +) +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*167 (Net +uid 18675,0 +decl (Decl +n "hSelGpio" +t "std_uLogic" +o 36 +suid 138,0 +) +declText (MLText +uid 18676,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,112000,17200,113000" +st "SIGNAL hSelGpio : std_uLogic" +) +) +*168 (Net +uid 18677,0 +decl (Decl +n "hRDataGpio" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 39 +suid 139,0 +) +declText (MLText +uid 18678,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,114700,33200,115700" +st "SIGNAL hRDataGpio : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*169 (Net +uid 18679,0 +decl (Decl +n "hReadyGpio" +t "std_uLogic" +o 38 +suid 140,0 +) +declText (MLText +uid 18680,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,113800,18000,114800" +st "SIGNAL hReadyGpio : std_uLogic" +) +) +*170 (Net +uid 18681,0 +decl (Decl +n "hRespGpio" +t "std_uLogic" +o 37 +suid 141,0 +) +declText (MLText +uid 18682,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,112900,17700,113900" +st "SIGNAL hRespGpio : std_uLogic" +) +) +*171 (PortIoOut +uid 18683,0 +shape (CompositeShape +uid 18684,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 18685,0 +sl 0 +ro 270 +xt "213500,-7375,215000,-6625" +) +(Line +uid 18686,0 +sl 0 +ro 270 +xt "213000,-7000,213500,-7000" +pts [ +"213000,-7000" +"213500,-7000" +] +) +] +) +tg (WTG +uid 18687,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18688,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "216000,-7700,235600,-6300" +st "ioOut : (ioNb-1 DOWNTO 0)" +blo "216000,-6500" +tm "WireNameMgr" +) +) +) +*172 (PortIoIn +uid 18689,0 +shape (CompositeShape +uid 18690,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 18691,0 +sl 0 +ro 90 +xt "213500,-5375,215000,-4625" +) +(Line +uid 18692,0 +sl 0 +ro 90 +xt "213000,-5000,213500,-5000" +pts [ +"213500,-5000" +"213000,-5000" +] +) +] +) +tg (WTG +uid 18693,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18694,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "216000,-5700,234600,-4300" +st "ioIn : (ioNb-1 DOWNTO 0)" +blo "216000,-4500" +tm "WireNameMgr" +) +) +) +*173 (PortIoOut +uid 18707,0 +shape (CompositeShape +uid 18708,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 18709,0 +sl 0 +ro 270 +xt "213500,-9375,215000,-8625" +) +(Line +uid 18710,0 +sl 0 +ro 270 +xt "213000,-9000,213500,-9000" +pts [ +"213000,-9000" +"213500,-9000" +] +) +] +) +tg (WTG +uid 18711,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18712,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "216000,-9700,234900,-8300" +st "ioEn : (ioNb-1 DOWNTO 0)" +blo "216000,-8500" +tm "WireNameMgr" +) +) +) +*174 (Net +uid 18713,0 +decl (Decl +n "ioEn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 8 +suid 142,0 +) +declText (MLText +uid 18714,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,57100,25000,58100" +st "ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0)" +) +) +*175 (Net +uid 18719,0 +decl (Decl +n "ioOut" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 9 +suid 143,0 +) +declText (MLText +uid 18720,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,58000,25100,59000" +st "ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0)" +) +) +*176 (Net +uid 18725,0 +decl (Decl +n "ioIn" +t "std_ulogic_vector" +b "(ioNb-1 DOWNTO 0)" +o 10 +suid 144,0 +) +declText (MLText +uid 18726,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,58900,24800,59900" +st "ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0)" +) +) +*177 (Net +uid 19108,0 +decl (Decl +n "intAck" +t "std_ulogic" +o 48 +suid 145,0 +) +declText (MLText +uid 19109,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,122800,16500,123800" +st "SIGNAL intAck : std_ulogic" +) +) +*178 (Net +uid 19120,0 +decl (Decl +n "instruction" +t "std_ulogic_vector" +b "(instructionBitNb-1 DOWNTO 0)" +o 49 +suid 151,0 +) +declText (MLText +uid 19121,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,123700,32900,124700" +st "SIGNAL instruction : std_ulogic_vector(instructionBitNb-1 DOWNTO 0)" +) +) +*179 (Net +uid 19122,0 +decl (Decl +n "programCounter" +t "unsigned" +b "(programCounterBitNb-1 DOWNTO 0)" +o 50 +suid 152,0 +) +declText (MLText +uid 19123,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,124600,33600,125600" +st "SIGNAL programCounter : unsigned(programCounterBitNb-1 DOWNTO 0)" +) +) +*180 (Net +uid 19320,0 +decl (Decl +n "upEn" +t "std_ulogic" +o 12 +suid 160,0 +) +declText (MLText +uid 19321,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,90400,16700,91400" +st "SIGNAL upEn : std_ulogic" +) +) +*181 (HdlText +uid 19389,0 +optionalChildren [ +*182 (EmbeddedText +uid 19395,0 +commentText (CommentText +uid 19396,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 19397,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "12000,-8000,28000,-6000" +) +oxt "0,0,18000,5000" +text (MLText +uid 19398,0 +va (VaSet +) +xt "12200,-7800,19800,-6600" +st " +upEn <= '1'; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 19390,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "12000,-9000,28000,-5000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 19391,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*183 (Text +uid 19392,0 +va (VaSet +font "Verdana,8,1" +) +xt "11850,-5000,14150,-4000" +st "eb1" +blo "11850,-4200" +tm "HdlTextNameMgr" +) +*184 (Text +uid 19393,0 +va (VaSet +font "Verdana,8,1" +) +xt "11850,-4000,13050,-3000" +st "1" +blo "11850,-3200" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 19394,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "12250,-6750,13750,-5250" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*185 (SaComponent +uid 19476,0 +optionalChildren [ +*186 (CptPort +uid 19428,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 19429,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43250,-5375,44000,-4625" +) +tg (CPTG +uid 19430,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 19431,0 +va (VaSet +font "Verdana,12,0" +) +xt "45000,-5700,48800,-4300" +st "clock" +blo "45000,-4500" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*187 (CptPort +uid 19432,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 19433,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43250,-3375,44000,-2625" +) +tg (CPTG +uid 19434,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 19435,0 +va (VaSet +font "Verdana,12,0" +) +xt "45000,-3700,49100,-2300" +st "reset" +blo "45000,-2500" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 6 +suid 12,0 +) +) +) +*188 (CptPort +uid 19436,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 19437,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60000,-7375,60750,-6625" +) +tg (CPTG +uid 19438,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 19439,0 +va (VaSet +font "Verdana,12,0" +) +xt "50300,-7700,59000,-6300" +st "readStrobe" +ju 2 +blo "59000,-6500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "readStrobe" +t "std_uLogic" +o 11 +suid 2024,0 +) +) +) +*189 (CptPort +uid 19440,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 19441,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60000,-5375,60750,-4625" +) +tg (CPTG +uid 19442,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 19443,0 +va (VaSet +font "Verdana,12,0" +) +xt "50000,-5700,59000,-4300" +st "writeStrobe" +ju 2 +blo "59000,-4500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writeStrobe" +t "std_uLogic" +o 12 +suid 2026,0 +) +) +) +*190 (CptPort +uid 19444,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 19445,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43250,-7375,44000,-6625" +) +tg (CPTG +uid 19446,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 19447,0 +va (VaSet +font "Verdana,12,0" +) +xt "45000,-7700,47400,-6300" +st "en" +blo "45000,-6500" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 2027,0 +) +) +) +*191 (CptPort +uid 19448,0 +ps "OnEdgeStrategy" +shape (Triangle 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+constant beamerIndex: positive := uartIndex+1; + +constant ahbMemoryLocation : ahbMemoryLocationVector := ( + gpioIndex => ( + baseAddress => 16#0000#, + addressMask => 16#10000# - 16#0002# + ), + uartIndex => ( + baseAddress => 16#0010#, + addressMask => 16#10000# - 16#0004# + ), + beamerIndex => ( + baseAddress => 16#0020#, + addressMask => 16#10000# - 16#0004# + ), + others => ( + baseAddress => 16#FFFF#, + addressMask => 16#0000# + ) +);" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,89500,9000,90500" +st "Diagram Signals:" +blo "0,90300" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "0,49000,6000,50000" +st "Post User:" +blo "0,49800" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,49000,0,49000" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 162,0 +usingSuid 1 +emptyRow *375 (LEmptyRow +) +uid 10774,0 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"courier,8,1" +) +xt "0,9000,7500,9900" +st "Internal User:" +blo "0,9700" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,14400,2000,14400" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,9000,0,9000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 186,0 +activeModelName "Symbol" +) diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/ahbBeamer_tester_test.vhd b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/ahbBeamer_tester_test.vhd new file mode 100644 index 0000000..516688e --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/ahbBeamer_tester_test.vhd @@ -0,0 +1,479 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF ahbBeamer_tester IS + -- reset and clock + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + signal reset_int: std_uLogic; + -- test information + signal testSeparator : string(1 to 80) := (others => '-'); + signal errorTopSeparator : string(1 to 80) := (others => '#'); + signal bottomSeparator : string(1 to 80) := (others => '.'); + signal indentation : string(1 to 2) := (others => ' '); + signal noteInformation : string(1 to 9) := (others => ' '); + signal errorInformation : string(1 to 10) := (others => ' '); + signal failureInformation : string(1 to 12) := (others => ' '); + signal testInformation : string(1 to 50) := (others => ' '); + -- register definition + constant controlRegisterAddress: natural := 0; + constant controlRun: natural := 2#001#; + constant controlUpdatePattern: natural := 2#010#; + constant controlInterpolateLinear: natural := 2#100#; + constant speedRegisterAddress: natural := 1; + constant xFifoRegisterAddress: natural := 2; + constant yFifoRegisterAddress: natural := 3; + signal updatePeriod: natural := 1; + signal patternLength: natural := 32; + -- AMBA bus access + constant registerWriteDelay: time := 4*clockPeriod; + signal registerAddress: natural; + signal registerDataOut, registerDataIn: integer; + signal registerWrite: std_uLogic; + signal registerRead: std_uLogic; + -- UART access + constant baudPeriodNb: positive := 4; + signal uartData: integer; + signal uartSend: std_uLogic; + -- functions + function clearBits (word, bits : natural) return natural is + variable andMask: unsigned(hRData'range); + begin + andMask := not(to_unsigned(bits, hRData'length)); + return to_integer(to_unsigned(word, hRData'length) and andMask); + end clearBits; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset_int <= '1', '0' after 2*clockPeriod; + hReset_n <= not(reset_int); + reset <= reset_int; + + clock_int <= not clock_int after clockPeriod/2; + hClk <= transport clock_int after clockPeriod*9.0/10.0; + clock <= transport clock_int after clockPeriod*9.0/10.0; + + ------------------------------------------------------------------------------ + -- test sequence + testSequence: process + begin + selSinCos <= '0'; + registerAddress <= 0; + registerDataOut <= 0; + registerWrite <= '0'; + registerRead <= '0'; + uartSend <= '0'; + wait for 100 ns; + print(cr & cr & cr & cr); + + ---------------------------------------------------------------------------- + -- test control register + wait for 1 us - now; + testInformation <= pad("Testing control register", testInformation'length); + wait for 0 ns; + print(testSeparator & cr & testInformation); + -- set control register bits + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerDataOut <= controlRun + controlUpdatePattern + controlInterpolateLinear; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + -- readback control register + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + wait for 3*clockPeriod; + assert(registerDataIn = controlRun + controlUpdatePattern + controlInterpolateLinear) + report "Control register write / readback error" + severity error; + wait for registerWriteDelay; + -- stop running and pattern update + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + wait for 3*clockPeriod; + registerDataOut <= clearBits(registerDataIn, controlRun + controlUpdatePattern); + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + + ---------------------------------------------------------------------------- + -- test speed register + wait for 2 us - now; + testInformation <= pad("Testing speed register", testInformation'length); + wait for 0 ns; + print(testSeparator & cr & testInformation); + -- set speed count value + wait until rising_edge(clock_int); + registerAddress <= speedRegisterAddress; + registerDataOut <= updatePeriod; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + -- readback speed count + wait until rising_edge(clock_int); + registerAddress <= speedRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + wait for 3*clockPeriod; + assert(registerDataIn = updatePeriod) + report "Speed register write / readback error" + severity error; + wait for registerWriteDelay; + + ---------------------------------------------------------------------------- + -- write sinewave data points to RAM + wait for 3 us - now; + testInformation <= pad("Writing sinewaves to RAM", testInformation'length); + wait for 0 ns; + print(testSeparator & cr & testInformation); + -- start pattern update + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerDataOut <= controlUpdatePattern; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + -- write X FIFO values + wait until rising_edge(clock_int); + registerAddress <= xFifoRegisterAddress; + registerDataOut <= 16#0000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7FFF#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#0000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7FFF#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for 10*registerWriteDelay; + -- write Y FIFO values + wait until rising_edge(clock_int); + registerAddress <= yFifoRegisterAddress; + registerDataOut <= 16#7FFF#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#0000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7FFF#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#0000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#18F9#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#30FB#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#471C#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#5A82#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#6A6D#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7641#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7D89#; + registerWrite <= '1', '0' after clockPeriod; + wait for 10*registerWriteDelay; + -- end pattern update + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerDataOut <= 0; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + + ---------------------------------------------------------------------------- + -- playing waveforms + wait for 7 us - now; + testInformation <= pad("Playing waveforms", testInformation'length); + wait for 0 ns; + print(testSeparator & cr & testInformation); + -- start run + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerDataOut <= controlRun + patternLength * 2**(hWData'length-patternAddressBitNb); + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + -- run for some time + wait for 250 us - now; + -- stop run + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerDataOut <= 0; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + + ---------------------------------------------------------------------------- + -- play data points to RAM for overflow + wait for 300 us - now; + testInformation <= pad( + "Writing waveform to RAM for overflow", testInformation'length + ); + wait for 0 ns; + print(testSeparator & cr & testInformation); + -- start pattern update + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerDataOut <= controlUpdatePattern; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + -- write X FIFO values + wait until rising_edge(clock_int); + registerAddress <= xFifoRegisterAddress; + registerDataOut <= 16#4000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for 10*registerWriteDelay; + -- write Y FIFO values + wait until rising_edge(clock_int); + registerAddress <= yFifoRegisterAddress; + registerDataOut <= -16#4000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= 16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + registerDataOut <= -16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for 10*registerWriteDelay; + -- end pattern update and start run + patternLength <= 4; + wait until rising_edge(clock_int); + registerAddress <= controlRegisterAddress; + registerDataOut <= controlRun + patternLength * 2**(hWData'length-patternAddressBitNb); + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + -- set lower speed execution + updatePeriod <= 9; + wait until rising_edge(clock_int); + registerAddress <= speedRegisterAddress; + registerDataOut <= updatePeriod; + registerWrite <= '1', '0' after clockPeriod; + wait for registerWriteDelay; + ---------------------------------------------------------------------------- + -- sin/cos debug mode + wait for 700 us - now; + testInformation <= pad("Drawing debug mode circle", testInformation'length); + wait for 0 ns; + print(testSeparator & cr & testInformation); + selSinCos <= '1'; + ---------------------------------------------------------------------------- + -- stop simulation + wait for 1 ms - now; + assert false + report "End" & cr & " --> " & + "End of simulation" + severity failure; + end process testSequence; + + ------------------------------------------------------------------------------ + -- AMBA bus access + busAccess: process + variable writeAccess: boolean; + variable hRData01: std_ulogic_vector(hRData'range); + begin + hAddr <= (others => '-'); + hWData <= (others => '-'); + hTrans <= transIdle; + hSel <= '0'; + hWrite <= '0'; + wait on registerWrite, registerRead; + writeAccess := false; + if rising_edge(registerWrite) then + writeAccess := true; + end if; + -- phase 1: address and controls + wait until rising_edge(clock_int); + hAddr <= to_unsigned(registerAddress, hAddr'length); + hTrans <= transNonSeq; + hSel <= '1'; + if writeAccess then + hWrite <= '1'; + end if; + -- phase 2: data + wait until rising_edge(clock_int); + hAddr <= (others => '-'); + hTrans <= transIdle; + hSel <= '0'; + hWrite <= '0'; + if writeAccess then + hWData <= std_uLogic_vector(to_signed(registerDataOut, hWData'length)); + else + wait until falling_edge(clock_int); + hRData01 := hRData; + for index in hRData01'range loop + if (hRData01(index) /= '0') and (hRData01(index) /= '1') then + hRData01(index) := '0'; + end if; + end loop; + registerDataIn <= to_integer(unsigned(hRData01)); + end if; + wait until rising_edge(clock_int); + end process; + +END ARCHITECTURE test; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerSoc_tester_test.vhd b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerSoc_tester_test.vhd new file mode 100644 index 0000000..050ff65 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerSoc_tester_test.vhd @@ -0,0 +1,294 @@ +ARCHITECTURE test OF beamerSoc_tester IS + -- clock and reset + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + signal sReset: std_uLogic := '1'; + -- register definition + constant beamerBaseAddress: natural := 16#20#; + constant beamerControlRegisterAddress: natural := beamerBaseAddress + 0; + constant beamerControlRun: natural := 2#001#; + constant beamerControlUpdatePattern: natural := 2#010#; + constant beamerControlInterpolateLinear: natural := 2#100#; + constant beamerControlsizeBase: natural := 16#80#; + constant beamerSpeedRegisterAddress: natural := beamerBaseAddress + 1; + constant beamerXFifoRegisterAddress: natural := beamerBaseAddress + 2; + constant beamerYFifoRegisterAddress: natural := beamerBaseAddress + 3; + -- microprocessor bus access + constant registerWriteDelay: time := 4*clockPeriod; + signal registerAddress: natural; + signal registerDataOut, registerDataIn: integer; + signal registerWrite, registerRead, registerDone: std_uLogic; + -- UART access +-- constant uartFrequency: real := 115200.0; + constant uartDataBitNb: positive := 8; + constant uartFrequency: real := 1.0E6; + constant uartPeriod: time := (1.0/uartFrequency) * 1 sec; + constant uartDataSpan: time := 10*uartPeriod; + constant uartWriteReplySpan: time := 5*uartDataSpan; + constant uartReadReplySpan: time := 10*uartDataSpan; + signal uartRxData, uartTxData: integer; + signal uartSend, uartDone: std_uLogic; + signal uartTxShiftRegister: unsigned(2*uartDataBitNb-1 downto 0); + signal uartTxDataWord: integer; + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + reset <= '1', '0' after 2*clockPeriod; + + ------------------------------------------------------------------------------ + -- test sequence + process + begin + io <= (others => 'Z'); + selSinCos <= '0'; + wait for 1 ns; + assert false + report cr & cr & cr & cr & + "----------------------------------------" & + "----------------------------------------" & + "----------------------------------------" + severity note; + ---------------------------------------------------------------------------- + -- initialization by microprocessor + wait for 100 ns - now; + assert false + report "Init" & cr & " --> " & + "Letting the microprocessor initialize the peripherals" + severity note; + ---------------------------------------------------------------------------- + -- test GPIOs + wait for 400 ns - now; + assert false + report "GPIOs" & cr & " --> " & + "Testing the GPIOs" + severity note; + io(7 downto 4) <= x"5"; + wait for 1 ns; + assert io = x"5A" + report "GPIO error" + severity error; + ---------------------------------------------------------------------------- + -- set speed count value + wait for 3*uartPeriod - now; + assert false + report "Beamer init" & cr & " --> " & + "Setting drawing speed" + severity note; + registerAddress <= beamerSpeedRegisterAddress; + registerDataOut <= 2; +--registerAddress <= 16#1234#; +--registerDataOut <= 16#5678#; + registerWrite <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartWriteReplySpan; + ---------------------------------------------------------------------------- + -- start updating pattern + assert false + report "Beamer init" & cr & " --> " & + "Writing y-pattern to beamer RAM" + severity note; + registerAddress <= beamerControlRegisterAddress; + registerDataOut <= beamerControlUpdatePattern; + registerWrite <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartWriteReplySpan; + ---------------------------------------------------------------------------- + -- write y-FIFO + registerAddress <= beamerYFifoRegisterAddress; + registerDataOut <= -16#4000# + 16#10000#; + registerWrite <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartWriteReplySpan; + registerDataOut <= 16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartWriteReplySpan; + registerDataOut <= 16#7000#; + registerWrite <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartWriteReplySpan; + registerDataOut <= -16#7000# + 16#10000#; + registerWrite <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartWriteReplySpan; + ---------------------------------------------------------------------------- + -- start run + assert false + report "Beamer play" & cr & " --> " & + "Launching pattern drawing (setting pattern size and run flag)" + severity note; + registerAddress <= beamerControlRegisterAddress; + registerDataOut <= beamerControlRun + beamerControlsizeBase * 4; + registerWrite <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartWriteReplySpan; + ---------------------------------------------------------------------------- + -- readback control register + assert false + report "Beamer test" & cr & " --> " & + "Reading back control register" + severity note; + registerAddress <= beamerControlRegisterAddress; + registerRead <= '1', '0' after clockPeriod; + wait for uartPeriod; + wait until registerDone = '1'; + wait for uartReadReplySpan; + assert uartTxDataWord = beamerControlRun + beamerControlsizeBase * 4 + report "Beamer register readback error" + severity error; + ---------------------------------------------------------------------------- + -- stop simulation + wait for 1.5 ms - now; + assert false + report "End" & cr & " --> " & + "End of simulation" + severity failure; + end process; + + --============================================================================ + -- microprocessor bus access + busAccess: process + variable writeAccess: boolean; +-- variable packetId: natural := 0; +variable packetId: natural := 16#1D#; + variable checksum: natural; + begin + registerDone <= '1'; + uartSend <= '0'; + uartRxData <= 16#AA#; + wait on registerWrite, registerRead; + registerDone <= '0'; + writeAccess := false; + if registerWrite = '1' then + writeAccess := true; + end if; + -- send header + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := uartRxData; + -- send packet id + uartRxData <= packetId; + packetId := (packetId + 1) mod 2**8; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := (checksum + uartRxData) mod 2**8; + -- send command + if writeAccess then + uartRxData <= 16#03#; + else + uartRxData <= 16#04#; + end if; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := (checksum + uartRxData) mod 2**8; + -- send data length + if writeAccess then + uartRxData <= 4; + else + uartRxData <= 2; + end if; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := (checksum + uartRxData) mod 2**8; + -- send addresss low + uartRxData <= registerAddress mod 2**8; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := (checksum + uartRxData) mod 2**8; + -- send addresss high + uartRxData <= registerAddress / 2**8; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := (checksum + uartRxData) mod 2**8; + -- send data low + if writeAccess then + uartRxData <= registerDataOut mod 2**8; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := (checksum + uartRxData) mod 2**8; + -- send data high + uartRxData <= registerDataOut / 2**8; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + checksum := (checksum + uartRxData) mod 2**8; + end if; + -- send checksum + uartRxData <= checksum; + uartSend <= '1', '0' after uartPeriod; + wait for uartPeriod; + wait until uartDone = '1'; + end process; + + ------------------------------------------------------------------------------ + -- UART access + sendByte: process + variable serialData: unsigned(7 downto 0); + begin + -- send stop bit + uartDone <= '1'; + RxD <= '1'; + -- get new word + wait until rising_edge(uartSend); + uartDone <= '0'; + serialData := to_unsigned(uartRxData, serialData'length); + -- send start bit + RxD <= '0'; + wait for uartPeriod; + -- send data bits + for index in serialData'reverse_range loop + RxD <= serialData(index); + wait for uartPeriod; + end loop; + -- send stop bits + RxD <= '1'; + wait for 4*uartPeriod; + end process sendByte; + + ------------------------------------------------------------------------------ + -- UART access + receiveByte: process + variable serialData: unsigned(uartDataBitNb-1 downto 0); + begin + -- wait for stat bit + wait until falling_edge(TxD); + -- jump to middle of first data bit + wait for 1.5 * uartPeriod; + -- read data bits + for index in serialData'reverse_range loop + if Is_X(TxD) then + serialData(index) := '0'; + else + serialData(index) := TxD; + end if; + wait for uartPeriod; + end loop; + -- write data to signal + uartTxData <= to_integer(serialData); + uartTxDataWord <= to_integer(uartTxShiftRegister); + uartTxShiftRegister <= shift_right(uartTxShiftRegister, serialData'length); + uartTxShiftRegister( + uartTxShiftRegister'high downto + uartTxShiftRegister'high-serialData'length+1 + ) <= serialData; + end process receiveByte; + +END ARCHITECTURE test; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerTest_pck_pkg.vhd b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerTest_pck_pkg.vhd new file mode 100644 index 0000000..490ad4e --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerTest_pck_pkg.vhd @@ -0,0 +1,9 @@ +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +PACKAGE beamerTest_pck IS + + function trim_X (arg : signed) return signed; + +END beamerTest_pck; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerTest_pck_pkg_body.vhd b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerTest_pck_pkg_body.vhd new file mode 100644 index 0000000..2c83ab7 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerTest_pck_pkg_body.vhd @@ -0,0 +1,16 @@ +PACKAGE BODY beamerTest_pck IS + + function trim_X (arg : signed) return signed is + variable returnVal : signed(arg'range); + begin + for i in arg'range loop + case arg(i) is + when '0' | 'L' => returnVal(i) := '0'; + when '1' | 'H' => returnVal(i) := '1'; + when others => returnVal(i) := '0'; + end case; + end loop; + return returnVal; + end trim_X; + +END beamerTest_pck; diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbBeamer_tester_test.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbBeamer_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbBeamer_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_struct.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_struct.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tester_entity.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tester_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tester_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tester_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_ahbbeamer_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerSoc_tester_test.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerSoc_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerSoc_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerTest_pck_pkg.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerTest_pck_pkg.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerTest_pck_pkg.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerTest_pck_pkg_body.vhd._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerTest_pck_pkg_body.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamerTest_pck_pkg_body.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tb_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tb_struct.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tester_entity.vhg._fpf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/.hdlsidedata/_beamersoc_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_ahbbeamer_tb._epf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_ahbbeamer_tb._epf new file mode 100644 index 0000000..50e0e8c --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_ahbbeamer_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom ahb@beamer_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_ahbbeamer_tester._epf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_ahbbeamer_tester._epf new file mode 100644 index 0000000..036f8ec --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_ahbbeamer_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom ahbBeamer_tester_test.vhd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_beamerperiphblanking_tb._epf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_beamerperiphblanking_tb._epf new file mode 100644 index 0000000..9cb6082 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_beamerperiphblanking_tb._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom beamer@periph@blanking_tb/struct.bd diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_beamersoc_tb._epf b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/_beamersoc_tb._epf new file mode 100644 index 0000000..1de05b2 --- /dev/null +++ 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"87000,85000,138000,93000" +) +oxt "13000,22000,64000,30000" +) +*12 (Net +uid 12555,0 +decl (Decl +n "hReset_n" +t "std_uLogic" +o 6 +suid 108,0 +) +declText (MLText +uid 12556,0 +va (VaSet +isHidden 1 +) +xt "0,0,18700,1200" +st "SIGNAL hReset_n : std_uLogic" +) +) +*13 (Net +uid 12563,0 +decl (Decl +n "hClk" +t "std_uLogic" +o 3 +suid 109,0 +) +declText (MLText +uid 12564,0 +va (VaSet +isHidden 1 +) +xt "0,0,17500,1200" +st "SIGNAL hClk : std_uLogic" +) +) +*14 (Net +uid 12571,0 +decl (Decl +n "hResp" +t "std_uLogic" +o 7 +suid 110,0 +) +declText (MLText +uid 12572,0 +va (VaSet +isHidden 1 +) +xt "0,0,18000,1200" +st "SIGNAL hResp : std_uLogic" +) +) +*15 (Net +uid 12579,0 +decl (Decl +n "hReady" +t "std_uLogic" +o 5 +suid 111,0 +) +declText (MLText +uid 12580,0 +va (VaSet +isHidden 1 +) +xt "0,0,18300,1200" +st "SIGNAL hReady : std_uLogic" +) +) +*16 (Net +uid 12587,0 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 4 +suid 112,0 +) +declText (MLText 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"39400,79700,45300,81100" +st "I_tester" +blo "39400,80900" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 12663,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 12664,0 +text (MLText +uid 12665,0 +va (VaSet +font "Verdana,8,0" +) +xt "39400,82300,65200,85300" +st "patternAddressBitNb = patternAddressBitNb ( positive ) +signalBitNb = signalBitNb ( positive ) +clockFrequency = clockFrequency ( real ) " +) +header "" +) +elements [ +(GiElement +name "patternAddressBitNb" +type "positive" +value "patternAddressBitNb" +) +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +) +viewicon (ZoomableIcon +uid 12742,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "39250,75250,40750,76750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +) +*26 (Net +uid 13629,0 +decl (Decl +n "selSinCos" +t "std_ulogic" +o 17 +suid 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16000 +) +) +) +] +shape (Rectangle +uid 13841,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "85000,27000,101000,31000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 13842,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*31 (Text +uid 13843,0 +va (VaSet +) +xt "85400,31000,88000,32200" +st "eb2" +blo "85400,32000" +tm "HdlTextNameMgr" +) +*32 (Text +uid 13844,0 +va (VaSet +) +xt "85400,32000,86800,33200" +st "2" +blo "85400,33000" +tm "HdlTextNumberMgr" +) +] +) +) +*33 (SaComponent +uid 13849,0 +optionalChildren [ +*34 (CptPort +uid 13858,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 13859,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "100250,44625,101000,45375" +) +tg (CPTG +uid 13860,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 13861,0 +va (VaSet +) +xt "102000,44400,105400,45600" +st "clock" +blo "102000,45400" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +) +) +) +*35 (CptPort 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(VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "2000,14600,15500,15600" +st "SIGNAL reset : std_ulogic" +) +) +*43 (Net +uid 13922,0 +decl (Decl +n "lowpassInY" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 12 +suid 127,0 +) +declText (MLText +uid 13923,0 +va (VaSet +isHidden 1 +) +xt "0,0,33000,1200" +st "SIGNAL lowpassInY : unsigned(signalBitNb-1 DOWNTO 0)" +) +) +*44 (Net +uid 13924,0 +decl (Decl +n "lowpassOutY" +t "unsigned" +b "(signalBitNb-1 DOWNTO 0)" +o 13 +suid 128,0 +) +declText (MLText +uid 13925,0 +va (VaSet +isHidden 1 +) +xt "0,0,33500,1200" +st "SIGNAL lowpassOutY : unsigned(signalBitNb-1 DOWNTO 0)" +) +) +*45 (SaComponent +uid 14527,0 +optionalChildren [ +*46 (CptPort +uid 14471,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 14472,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "68250,56625,69000,57375" +) +tg (CPTG +uid 14473,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 14474,0 +va (VaSet +) +xt "70000,56400,73000,57600" +st "hClk" +blo "70000,57400" +) +) +thePort (LogicalPort +decl (Decl +n "hClk" +t "std_ulogic" +o 13 +suid 1,0 +) +) +) +*47 (CptPort +uid 14475,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 14476,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "68250,38625,69000,39375" +) +tg (CPTG +uid 14477,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 14478,0 +va (VaSet +) +xt "70000,38400,73700,39600" +st "hAddr" +blo "70000,39400" +) +) +thePort (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 downto 0)" +o 2 +suid 2,0 +) +) +) +*48 (CptPort +uid 14479,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 14480,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "85000,38625,85750,39375" +) +tg (CPTG +uid 14481,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 14482,0 +va (VaSet +) +xt "81001,38400,84001,39600" +st "outX" +ju 2 +blo "84001,39400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "outX" +t 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14492,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "68250,40625,69000,41375" +) +tg (CPTG +uid 14493,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 14494,0 +va (VaSet +) +xt "70000,40400,74600,41600" +st "hWData" +blo "70000,41400" +) +) +thePort (LogicalPort +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 4 +suid 11,0 +) +) +) +*52 (CptPort +uid 14495,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 14496,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "85000,44625,85750,45375" +) +tg (CPTG +uid 14497,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 14498,0 +va (VaSet +) +xt "78201,44400,84001,45600" +st "selSinCos" +ju 2 +blo "84001,45400" +) +) +thePort (LogicalPort +decl (Decl +n "selSinCos" +t "std_ulogic" +o 5 +suid 13,0 +) +) +) +*53 (CptPort +uid 14499,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 14500,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "85000,56625,85750,57375" +) +tg (CPTG +uid 14501,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 14502,0 +va (VaSet +) +xt "79400,56400,84000,57600" +st "testOut" +ju 2 +blo "84000,57400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "testOut" +t "std_ulogic_vector" +b "(1 TO testOutBitNb)" +o 6 +suid 2014,0 +) +) +) +*54 (CptPort +uid 14503,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 14504,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "68250,48625,69000,49375" +) +tg (CPTG +uid 14505,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 14506,0 +va (VaSet +) +xt "70000,48400,74400,49600" +st "hRData" +blo "70000,49400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 downto 0)" +o 7 +suid 2015,0 +) +) +) +*55 (CptPort +uid 14507,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 14508,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "68250,42625,69000,43375" +) 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+va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,79000,2800" +st "hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 4 +suid 52,0 +) +) +) +*94 (CptPort +uid 654,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 655,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34625,5250,35375,6000" +) +tg (CPTG +uid 656,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 657,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "34300,7000,35700,12500" +st "hReady" +ju 2 +blo "35500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 658,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,62500,3600" +st "hReady : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 5 +suid 53,0 +) +) +) +*95 (CptPort +uid 659,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 660,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt 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"Verdana,12,0" +) +xt "26300,7000,27700,12100" +st "hTrans" +ju 2 +blo "27500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 678,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,79500,11600" +st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 9 +suid 57,0 +) +) +) +*99 (CptPort +uid 679,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 680,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24625,5250,25375,6000" +) +tg (CPTG +uid 681,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 682,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "24300,7000,25700,12900" +st "hWData" +ju 2 +blo "25500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 683,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,79000,12400" +st "hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n 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(CptPort +uid 268,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 269,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "42625,5250,43375,6000" +) +tg (CPTG +uid 270,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 271,0 +ro 270 +va (VaSet +font "courier,8,0" +) +xt "42550,7000,43450,11000" +st "hReset_n" +ju 2 +blo "43250,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 272,0 +va (VaSet +font "courier,8,0" +) +xt "44000,9900,61500,10800" +st "hReset_n : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReset_n" +t "std_uLogic" +o 6 +suid 22,0 +) +) +) +*90 (CptPort +uid 273,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 274,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36625,5250,37375,6000" +) +tg (CPTG +uid 275,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 276,0 +ro 270 +va (VaSet +font "courier,8,0" +) +xt "36550,7000,37450,9500" +st "hResp" +ju 2 +blo "37250,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 277,0 +va (VaSet +font "courier,8,0" +) +xt "44000,3600,61500,4500" +st "hResp : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 7 +suid 23,0 +) +) +) +*91 (CptPort +uid 278,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 279,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30625,5250,31375,6000" +) +tg (CPTG +uid 280,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 281,0 +ro 270 +va (VaSet +font "courier,8,0" +) +xt "30550,7000,31450,9000" +st "hSel" +ju 2 +blo "31250,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 282,0 +va (VaSet +font "courier,8,0" +) +xt "44000,10800,61500,11700" +st "hSel : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 8 +suid 24,0 +) +) +) +*92 (CptPort +uid 283,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 284,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26625,5250,27375,6000" +) +tg (CPTG +uid 285,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 286,0 +ro 270 +va (VaSet +font "courier,8,0" +) +xt "26550,7000,27450,10000" +st "hTrans" +ju 2 +blo "27250,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 287,0 +va (VaSet +font "courier,8,0" +) +xt "44000,11700,78000,12600" +st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 9 +suid 25,0 +) +) +) +*93 (CptPort +uid 288,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 289,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24625,5250,25375,6000" +) +tg (CPTG +uid 290,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 291,0 +ro 270 +va (VaSet +font "courier,8,0" +) +xt "24550,7000,25450,10000" +st "hWData" +ju 2 +blo "25250,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 292,0 +va (VaSet +font "courier,8,0" +) +xt "44000,12600,77500,13500" +st "hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 10 +suid 26,0 +) +) +) +*94 (CptPort +uid 293,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 294,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "28625,5250,29375,6000" +) +tg (CPTG +uid 295,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 296,0 +ro 270 +va (VaSet +font "courier,8,0" +) +xt "28550,7000,29450,10000" +st "hWrite" +ju 2 +blo "29250,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 297,0 +va (VaSet +font "courier,8,0" +) +xt "44000,13500,61500,14400" +st "hWrite : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWrite" +t "std_uLogic" +o 11 +suid 27,0 +) +) +) +*95 (CptPort +uid 298,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 299,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "96625,5250,97375,6000" +) +tg (CPTG +uid 300,0 +ps "CptPortTextPlaceStrategy" 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+) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *116 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "42000,0,48500,900" +st "Declarations" +blo "42000,700" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "42000,900,45000,1800" +st "Ports:" +blo "42000,1600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "42000,16200,44500,17100" +st "User:" +blo "42000,16900" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,0,49500,900" +st "Internal User:" +blo "42000,700" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "44000,17100,44000,17100" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 354,0 +activeModelName "Symbol:CDM" +) diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/beamer@periph@blanking_tb/struct.bd b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/beamer@periph@blanking_tb/struct.bd new file mode 100644 index 0000000..603cb46 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/beamer@periph@blanking_tb/struct.bd @@ -0,0 +1,5636 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I1" +duLibraryName "Curves_test" +duName "beamerPeriphBlanking_tester" +elements [ +] +mwi 0 +uid 421,0 +) +(Instance +name "I3" +duLibraryName "Curves" +duName "lowpass" +elements [ +(GiElement +name "signalBitNb" +type "positive" +value "signalBitNb" +) +(GiElement +name "shiftBitNb" +type "positive" +value "8" +) +] +mwi 0 +uid 984,0 +) +(Instance +name "I0" +duLibraryName "Curves" +duName "beamerPeriphBlanking" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "16" +) +(GiElement +name "addressBitNb" +type "positive" +value "24" +) +] +mwi 0 +uid 1599,0 +) +(Instance +name "I2" +duLibraryName "Curves_test" +duName "DAC_5543" +elements [ +] +mwi 0 +uid 1624,0 +) +(Instance +name "I4" +duLibraryName "Curves_test" +duName "DAC_5543" +elements [ +] +mwi 0 +uid 1649,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb2" +number "2" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerPeriphBlanking_tb" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "beamerPeriphBlanking_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:05:23" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "SystemOnChip_test" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/SystemOnChip_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "beamerPeriphBlanking_tb" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamer@periph@blanking_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\beamerPeriphBlanking_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_AsmPath" +value "$HEI_LIBS_DIR/NanoBlaze/hdl" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_WORK_DIR" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME/modeltech/bin" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:05:23" +) +(vvPair +variable "unit" +value "beamerPeriphBlanking_tb" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 153,0 +optionalChildren [ +*1 (Net +uid 45,0 +decl (Decl +n "reset" +t "std_ulogic" +o 20 +suid 1,0 +) +declText (MLText +uid 46,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,35600,15200,36600" +st "SIGNAL reset : std_ulogic +" +) +) +*2 (Net +uid 53,0 +decl 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"VerticalLayoutStrategy" +f (Text +uid 1669,0 +va (VaSet +) +xt "108000,46400,110700,47600" +st "SDI" +blo "108000,47400" +) +) +thePort (LogicalPort +decl (Decl +n "SDI" +t "std_ulogic" +o 16 +) +) +) +*79 (CptPort +uid 1670,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1671,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "115000,44625,115750,45375" +) +tg (CPTG +uid 1672,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1673,0 +va (VaSet +) +xt "111200,44400,114000,45600" +st "Iout" +ju 2 +blo "114000,45400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "Iout" +t "natural" +o 4 +) +) +) +] +shape (Rectangle +uid 1650,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "107000,43000,115000,51000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1651,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*80 (Text +uid 1652,0 +va (VaSet +) +xt "107600,50800,115200,52000" +st "Curves_test" +blo "107600,51800" +tm "BdLibraryNameMgr" +) +*81 (Text +uid 1653,0 +va (VaSet +) +xt "107600,51800,114100,53000" +st "DAC_5543" +blo "107600,52800" +tm "CptNameMgr" +) +*82 (Text +uid 1654,0 +va (VaSet +) +xt "107600,52800,109500,54000" +st "I4" +blo "107600,53800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1655,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1656,0 +text (MLText +uid 1657,0 +va (VaSet +font "Verdana,8,0" +) +xt "72000,28000,72000,28000" +) +header "" +) +elements [ +] +) +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +*83 (Net +uid 1674,0 +decl (Decl +n "CS_X_n" +t "std_ulogic" +o 3 +suid 16,0 +) +declText (MLText +uid 1675,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,18600,16000,19600" +st "SIGNAL CS_X_n : std_ulogic +" +) +) +*84 (Net +uid 1682,0 +decl (Decl +n "CLK_X" +t "std_ulogic" +o 1 +suid 17,0 +) +declText (MLText +uid 1683,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,16600,15800,17600" +st "SIGNAL CLK_X : std_ulogic +" +) +) +*85 (Net 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"2000,20600,14100,21600" +st "SIGNAL IoutX : natural +" +) +) +*90 (Net +uid 1788,0 +decl (Decl +n "IoutY" +t "natural" +o 6 +suid 23,0 +) +declText (MLText +uid 1789,0 +va (VaSet +font "Verdana,8,0" +) +xt "2000,21600,14100,22600" +st "SIGNAL IoutY : natural +" +) +) +*91 (Wire +uid 47,0 +shape (OrthoPolyLine +uid 48,0 +va (VaSet +vasetType 3 +) +xt "45000,34000,48250,44000" +pts [ +"45000,44000" +"45000,34000" +"48250,34000" +] +) +start &14 +end &47 +sat 2 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 51,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 52,0 +va (VaSet +font "Verdana,12,0" +) +xt "45000,32600,49100,34000" +st "reset" +blo "45000,33800" +tm "WireNameMgr" +) +) +on &1 +) +*92 (Wire +uid 55,0 +shape (OrthoPolyLine +uid 56,0 +va (VaSet +vasetType 3 +) +xt "43000,32000,48250,44000" +pts [ +"43000,44000" +"43000,32000" +"48250,32000" +] +) +start &14 +end &44 +sat 2 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 59,0 +ps "ConnStartEndStrategy" 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+xt "45250,16600,48350,18000" +st "wrL" +blo "45250,17800" +tm "WireNameMgr" +) +) +on &19 +) +*95 (Wire +uid 776,0 +shape (OrthoPolyLine +uid 777,0 +va (VaSet +vasetType 3 +) +xt "35000,16000,48250,44000" +pts [ +"48250,16000" +"35000,16000" +"35000,44000" +] +) +start &51 +end &14 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 780,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 781,0 +va (VaSet +font "Verdana,12,0" +) +xt "44250,14600,47550,16000" +st "wrH" +blo "44250,15800" +tm "WireNameMgr" +) +) +on &20 +) +*96 (Wire +uid 784,0 +shape (OrthoPolyLine +uid 785,0 +va (VaSet +vasetType 3 +) +xt "33000,14000,48250,44000" +pts [ +"48250,14000" +"33000,14000" +"33000,44000" +] +) +start &50 +end &14 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 788,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 789,0 +va (VaSet +font "Verdana,12,0" +) +xt "46250,12600,48350,14000" +st "rd" +blo "46250,13800" +tm "WireNameMgr" +) +) +on &21 +) +*97 (Wire +uid 792,0 +shape (OrthoPolyLine +uid 793,0 +va (VaSet +vasetType 3 +) +xt "65750,8000,79000,44000" +pts [ +"65750,8000" +"79000,8000" +"79000,44000" +] +) +start &48 +end &14 +sat 32 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 796,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 797,0 +va (VaSet +font "Verdana,12,0" +) +xt "67750,6600,71350,8000" +st "outY" +blo "67750,7800" +tm "WireNameMgr" +) +) +on &22 +) +*98 (Wire +uid 800,0 +shape (OrthoPolyLine +uid 801,0 +va (VaSet +vasetType 3 +) +xt "65750,6000,81000,44000" +pts [ +"65750,6000" +"81000,6000" +"81000,44000" +] +) +start &46 +end &14 +sat 32 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 804,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 805,0 +va (VaSet +font "Verdana,12,0" +) +xt "67750,4600,71450,6000" +st "outX" +blo "67750,5800" +tm "WireNameMgr" +) +) +on &23 +) +*99 (Wire +uid 808,0 +shape (OrthoPolyLine +uid 809,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "29000,10000,48250,44000" +pts [ +"48250,10000" +"29000,10000" +"29000,44000" +] +) +start &54 +end &14 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 812,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 813,0 +va (VaSet +font "Verdana,12,0" +) +xt "42250,8600,48250,10000" +st "dataOut" +blo "42250,9800" +tm "WireNameMgr" +) +) +on &24 +) +*100 (Wire +uid 816,0 +shape (OrthoPolyLine +uid 817,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "27000,8000,48250,44000" +pts [ +"48250,8000" +"27000,8000" +"27000,44000" +] +) +start &49 +end &14 +sat 32 +eat 2 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 820,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 821,0 +va (VaSet +font "Verdana,12,0" +) +xt "43250,6600,48250,8000" +st "dataIn" +blo "43250,7800" +tm "WireNameMgr" +) +) +on &25 +) +*101 (Wire +uid 824,0 +shape (OrthoPolyLine +uid 825,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "25000,6000,48250,44000" +pts [ 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"STSignalDisplayStrategy" +f (Text +uid 1032,0 +va (VaSet +font "Verdana,12,0" +) +xt "126750,9600,135850,11000" +st "lowpassOut" +blo "126750,10800" +tm "WireNameMgr" +) +) +on &40 +) +*106 (Wire +uid 1191,0 +shape (OrthoPolyLine +uid 1192,0 +va (VaSet +vasetType 3 +) +xt "65750,30000,73000,44000" +pts [ +"65750,30000" +"73000,30000" +"73000,44000" +] +) +start &56 +end &14 +sat 32 +eat 2 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1195,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1196,0 +va (VaSet +font "Verdana,12,0" +) +xt "67750,28600,74650,30000" +st "selSinCos" +blo "67750,29800" +tm "WireNameMgr" +) +) +on &41 +) +*107 (Wire +uid 1479,0 +shape (OrthoPolyLine +uid 1480,0 +va (VaSet +vasetType 3 +) +xt "65750,10000,77000,44000" +pts [ +"65750,10000" +"77000,10000" +"77000,44000" +] +) +start &57 +end &14 +sat 32 +eat 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1483,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1484,0 +va (VaSet +font "Verdana,12,0" +) +xt "67750,8600,71450,10000" +st "outZ" +blo "67750,9800" +tm "WireNameMgr" +) +) +on &42 +) +*108 (Wire +uid 1676,0 +shape (OrthoPolyLine +uid 1677,0 +va (VaSet +vasetType 3 +) +xt "65750,14000,73000,14000" +pts [ +"65750,14000" +"73000,14000" +] +) +start &59 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1680,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1681,0 +va (VaSet +font "Verdana,12,0" +) +xt "67750,12600,73450,14000" +st "CS_X_n" +blo "67750,13800" +tm "WireNameMgr" +) +) +on &83 +) +*109 (Wire +uid 1684,0 +shape (OrthoPolyLine +uid 1685,0 +va (VaSet +vasetType 3 +) +xt "65750,16000,73000,16000" +pts [ +"65750,16000" +"73000,16000" +] +) +start &58 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1688,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1689,0 +va (VaSet +font "Verdana,12,0" +) +xt "67750,14600,72550,16000" +st "CLK_X" +blo "67750,15800" +tm "WireNameMgr" +) +) +on &84 +) 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"outX" +t "std_ulogic" +o 8 +r 2 +d 0 +s 0 +sf 1 +tg (CPTG +uid 78,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 79,0 +ro 270 +va (VaSet +font "Verdana,9,0" +) +xt "78400,7000,79600,9300" +st "outX" +ju 2 +blo "79400,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 80,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,61500,3600" +st "outX : IN std_ulogic ; +" +) +) +*8 (CptPort +uid 81,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 82,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "76625,5250,77375,6000" +) +n "outY" +t "std_ulogic" +o 7 +r 3 +d 0 +s 0 +sf 1 +tg (CPTG +uid 83,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 84,0 +ro 270 +va (VaSet +font "Verdana,9,0" +) +xt "76400,7000,77600,9300" +st "outY" +ju 2 +blo "77400,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 85,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,61500,4400" +st "outY : IN std_ulogic ; +" +) +) +*9 (CptPort +uid 86,0 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(MLText +uid 50,0 +va (VaSet +) +xt "0,1000,11300,4000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL;" +tm "PackageList" +) +] +) +windowSize "0,0,895,750" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +font "Courier New,9,0" +) +xt "200,200,2200,1400" +st " +Text" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Verdana,9,1" +) +xt "1000,1000,4400,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentViewRef (DesignUnitViewRef +libraryName "Curves_test" +duName "beamerPeriphBlanking_tb" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,35000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "22600,14800,27400,16000" +st "" +blo "22600,15800" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "22600,16000,25900,17200" +st "" +blo "22600,17000" +) +) +gi *30 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +r 0 +d 0 +s 0 +sf 1 +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,9,0" +) +xt "0,750,1800,1950" +st "In0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +m 3 +o 0 +r 0 +d 0 +s 0 +sf 1 +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,9,0" +) +xt "0,750,3600,1950" +st "Buffer0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +) +DeclarativeBlock *31 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44300,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,12400,44000,13400" +st "User:" +blo "42000,13200" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13400,44000,13400" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 115,0 +) diff --git a/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/beamer@soc_tb/struct.bd b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/beamer@soc_tb/struct.bd new file mode 100644 index 0000000..f22f293 --- /dev/null +++ b/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/beamer@soc_tb/struct.bd @@ -0,0 +1,4189 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 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"22600,16000,25900,17200" +st "" +blo "22600,17000" +) +) +gi *21 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +r 0 +d 0 +s 0 +sf 1 +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,9,0" +) +xt "0,750,1800,1950" +st "In0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +m 3 +o 0 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7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 126,0 +) diff --git a/06-07-08-09-SystemOnChip/systemOnChip.bash b/06-07-08-09-SystemOnChip/systemOnChip.bash new file mode 100755 index 0000000..553408f --- /dev/null +++ b/06-07-08-09-SystemOnChip/systemOnChip.bash @@ -0,0 +1,33 @@ +#!/bin/bash + +#=============================================================================== +# systemOnChip.bash +# Starts HDL designer based on the generic hdlDesigner.bash +# + +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +hdl_script_name="$design_directory/Scripts/hdlDesigner.bash" +export HEI_LIBS_DIR=$design_directory/../Libs + +verbose=1 +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#------------------------------------------------------------------------------- +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Design name is $design_name" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}HDL designer script is $hdl_script_name" +fi + +#------------------------------------------------------------------------------- +# Launch application +# +$hdl_script_name -v -d $design_directory -n $design_name -m hds.hdp diff --git a/06-07-08-09-SystemOnChip/systemOnChip.bat b/06-07-08-09-SystemOnChip/systemOnChip.bat new file mode 100644 index 0000000..983c9d9 --- /dev/null +++ b/06-07-08-09-SystemOnChip/systemOnChip.bat @@ -0,0 +1,81 @@ +::============================================================================== +:: eln_labs.bat +:: Starts HDL designer based on the generic hdlDesigner.bat +:: +@echo off + +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: TO BE MODIFIED +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +:: Define environment variables to be modified +:: You can change one or more values as needed +:: +set VERBOSE=1 + +:: Define required Tools to be present +set REQUIRE_LIBS=0 +set REQUIRE_HDS=1 +set REQUIRE_MODELSIM=1 +set REQUIRE_ISE=0 +set REQUIRE_DIAMOND=1 + +:: Set project name +set design_name=%~n0 + +:: Manually override Library & Tools Folder location +::set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + +::set HDS_HOME=C:\eda\MentorGraphics\HDS +::set MODELSIM_HOME=C:\eda\MentorGraphics\Modelsim\win64 +::set ISE_VERSION=14.7 +::set ISE_HOME=C:\eda\Xilinx\%ISE_VERSION%\ISE_DS\ISE +::set LIBERO_HOME=C:\eda\Microsemi\Libero + +::set SCRATCH_DIR=C:\temp\eda\%username% +:: +::%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +::------------------------------------------------------------------------------ +:: Static environment variables +:: +set SEPARATOR="--------------------------------------------------------------------------------" +set INDENT=" " +set design_directory=%~dp0 +::remove trailing backslash +if %design_directory:~-1%==\ set design_directory=%design_directory:~0,-1% +pushd %design_directory% +set hdl_script_name="%design_directory:"=%\Scripts\hdlDesigner.bat" + +::------------------------------------------------------------------------------ +:: Main script +:: +if %VERBOSE% == 1 ( + echo "%SEPARATOR:"=%" + echo "-- HDL Designer Poject" + echo "%INDENT:"=%Design name is %design_name:"=%" + echo "%INDENT:"=%Start directory is %design_directory:"=%" + echo "%INDENT:"=%HDL designer script is %hdl_script_name:"=%" + echo. +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +if %VERBOSE% == 1 ( + set command=%hdl_script_name% -v -n %design_name% -d %design_directory% +) else ( + set command=%hdl_script_name% -n %design_name% -d %design_directory% +) +echo "Launch HDL Designer Script" +echo "%INDENT:"=%%command:"=%" +echo. +call %command% + +:end +popd +echo. +echo -- %~nx0 Finished! +echo %SEPARATOR% +echo. +if not %errorlevel% lss 1 pause +goto:eof diff --git a/10-PipelinedOperators/Board/concat/pipelinedOperators.lpf b/10-PipelinedOperators/Board/concat/pipelinedOperators.lpf new file mode 100644 index 0000000..f155067 --- /dev/null +++ b/10-PipelinedOperators/Board/concat/pipelinedOperators.lpf @@ -0,0 +1,334 @@ +### For reference, see TN1262 / FPGA-TN-02032 +# .lpf file format is not really documented by Lattice, normally generated through Diamond + + +################ +#### sysCONFIG +################ + +# The BLOCK commands disable tracing of paths within clock domains (impacting overall timing score) +# It can also be used on paths if the TRACE should not consider the clock domain crossing +# like : BLOCK PATH FROM CLKNET "CLK_A" TO CLKNET "CLK_B" ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK JTAGPATHS ; +BLOCK RD_DURING_WR_PATHS ; + + +# Not comprehensive +# dflt : CONFIG_IOVOLTAGE 1.2, 1.5, 1.8, 2.5(dflt), 3.3 voltage is 3.3V +# dflt : COMPRESS_CONFIG OFF (dflt), ON no bitstream compression +# mod : MCCLK_FREQ 2.4, 4.8, 9.7, 19.4, 38.8, 62 NOR program read @ 62MHz +# mod : MASTER_SPI_PORT DISABLE (dflt), ENABLE master SPI port stays SPI and not GPIOs, other mods disabled by dflt +# dflt : BACKGROUND_RECONFIG - no soft ERC when hot-loading bitstream (due to cosmic rays) +# dflt : DONE_PULL ON (dflt), OFF IPU on DONE pin +# dflt : DONE_EX OFF (dflt), ON not delaying end of the configuration (used for daisy chaining FPGAs) +# mod : DONE_OD OFF (dflt), ON DONE pin as open-drain instead of push-pull +# dflt : CONFIG_SECURE OFF (dflt), ON allows external access to current program +# mod : CONFIG_MODE JTAG (dflt), SSPI, SPI_SERIAL, SPI_DUAL, SPI_QUAD, SLAVE_PARALLEL, SLAVE_SERIAL +# which bus and mode is used to load configuration (for the Lattic IDE) +# dflt : TRANSFR OFF (dflt), ON if using TransFR tool from Lattice +# dflt : WAKE_UP 4 (set DONE=1 before starting user code, dflt for DONE_EX=ON) +# 21 (set DONE=1 once FPGA is already running user code, dflt for DONE_EX=OFF) +# mod : INBUF ON, OFF disable unused input buffers (not sure it impacts the ECP5 family) +SYSCONFIG MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE DONE_OD=ON CONFIG_MODE=SPI_QUAD INBUF=OFF CONFIG_IOVOLTAGE=3.3 ; +IOBUF ALLPORTS IO_TYPE=LVCMOS33 ; + +################ +#### Labs DB +################ + +### Clock and reset ### +#INPUT_SETUP ALLPORTS 50.000000 ns HOLD 10.000000 ns CLKPORT "CLK" ; +#INPUT_SETUP PORT "nRST" 50.000000 ns CLKPORT "CLK" ; + +FREQUENCY PORT "clock" 100.000000 MHz ; +LOCATE COMP "clock" SITE "K16" ; +IOBUF PORT "clock" PULLMODE=NONE ; + +LOCATE COMP "reset_n" SITE "E13" ; +GSR_NET NET "resetSynch_n"; + + +### LEDs ### +LOCATE COMP "LED1" SITE "T14" ;# red +LOCATE COMP "LED2" SITE "R14" ;# green +LOCATE COMP "LED3" SITE "T15" ;# blue + + +################ +#### SODIMM-200 +################ + +### PP2 ### +LOCATE COMP "xOut" SITE "G3" ; +LOCATE COMP "yOut" SITE "E1" ; +#LOCATE COMP "" SITE "F3" ; +#LOCATE COMP "" SITE "D1" ; +LOCATE COMP "triggerOut" SITE "F4" ; +#LOCATE COMP "" SITE "C1" ; +#LOCATE COMP "" SITE "D7" ; +#LOCATE COMP "" SITE "B6" ; +#LOCATE COMP "" SITE "C7" ; +#LOCATE COMP "" SITE "A6" ; # PP2 11 +#LOCATE COMP "" SITE "D8" ; # PP2 13 +#LOCATE COMP "" SITE "B7" ; # PP2 15 +#LOCATE COMP "" SITE "C8" ; # PP2 17 +#LOCATE COMP "" SITE "A7" ; # PP2 19 +#LOCATE COMP "" SITE "E9" ; # PP2 21 +#LOCATE COMP "" SITE "A8" ; # PP2 23 +#LOCATE COMP "" SITE "D9" ; # PP2 25 + + +### PP1 ### +#LOCATE COMP "" SITE "A9" ; +#LOCATE COMP "" SITE "D10" ; +#LOCATE COMP "" SITE "A10" ; +#LOCATE COMP "" SITE "C10" ; +#LOCATE COMP "" SITE "B10" ; +#LOCATE COMP "" SITE "C12" ; +#LOCATE COMP "" SITE "B12" ; +#LOCATE COMP "" SITE "D13" ; +#LOCATE COMP "" SITE "A13" ; +#LOCATE COMP "" SITE "M5" ; # PP1 11 +#LOCATE COMP "" SITE "L5" ; # PP1 13 +#LOCATE COMP "" SITE "K5" ; # PP1 15 +#LOCATE COMP "" SITE "H5" ; # PP1 17 +#LOCATE COMP "" SITE "E8" ; # PP1 19 +#LOCATE COMP "" SITE "E5" ; # PP1 21 +LOCATE COMP "selSinCos_n" SITE "E6" ; # PP1 23 +#LOCATE COMP "" SITE "E7" ; # PP1 25 + + +### USB (FTDI2232HL located on the daughterboard) ### +LOCATE COMP "TxD" SITE "A14" ; +IOBUF PORT "TxD" SLEWRATE=FAST ; +LOCATE COMP "RxD" SITE "B14" ; +IOBUF PORT "RxD" PULLMODE=UP ; +#LOCATE COMP "USB_DB_RTS" SITE "B13" ; +#IOBUF PORT "USB_DB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_DB_CTS" SITE "C13" ; +#IOBUF PORT "USB_DB_CTS" PULLMODE=UP ; + + + +################ +#### Extras +################ + + +### SD Flash (External SD card) ### +#LOCATE COMP "SD_DETECT" SITE "G12" ; +#IOBUF PORT "SD_DETECT" PULLMODE=UP ; + +#LOCATE COMP "SD_CMD" SITE "C15" ; +#IOBUF PORT "SD_CMD" SLEWRATE=FAST ; +#LOCATE COMP "SD_CLK" SITE "B15" ; +#IOBUF PORT "SD_CLK" SLEWRATE=FAST ; + +#LOCATE COMP "SD_DTA[0]" SITE "B16" ; +##IOBUF PORT "SD_DTA[0]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[1]" SITE "C16" ; +##IOBUF PORT "SD_DTA[1]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[2]" SITE "F12" ; +##IOBUF PORT "SD_DTA[2]" SLEWRATE=FAST ; +#LOCATE COMP "SD_DTA[3]" SITE "C14" ; +##IOBUF PORT "SD_DTA[3]" SLEWRATE=FAST ; + + +### DRAM ### +#LOCATE COMP "DRAM_ADDR[0]" SITE "J15" ; +#IOBUF PORT "DRAM_ADDR[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[1]" SITE "L16" ; +#IOBUF PORT "DRAM_ADDR[1]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[2]" SITE "L15" ; +#IOBUF PORT "DRAM_ADDR[2]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[3]" SITE "K15" ; +#IOBUF PORT "DRAM_ADDR[3]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[4]" SITE "G15" ; +#IOBUF PORT "DRAM_ADDR[4]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[5]" SITE "F15" ; +#IOBUF PORT "DRAM_ADDR[5]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[6]" SITE "F16" ; +#IOBUF PORT "DRAM_ADDR[6]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[7]" SITE "E16" ; +#IOBUF PORT "DRAM_ADDR[7]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[8]" SITE "E15" ; +#IOBUF PORT "DRAM_ADDR[8]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[9]" SITE "G13" ; +#IOBUF PORT "DRAM_ADDR[9]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[10]" SITE "M16" ; +#IOBUF PORT "DRAM_ADDR[10]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[11]" SITE "F13" ; +#IOBUF PORT "DRAM_ADDR[11]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_ADDR[12]" SITE "D16" ; +#IOBUF PORT "DRAM_ADDR[12]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_BA[0]" SITE "L14" ; +#IOBUF PORT "DRAM_BA[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_BA[1]" SITE "L13" ; +#IOBUF PORT "DRAM_BA[1]" SLEWRATE=FAST ; + +#LOCATE COMP "DRAM_CLK" SITE "G14" ; +#IOBUF PORT "DRAM_CLK" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_CKE" SITE "G16" ; +#IOBUF PORT "DRAM_CKE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nRAS" SITE "M14" ; +#IOBUF PORT "DRAM_nRAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCAS" SITE "K13" ; +#IOBUF PORT "DRAM_nCAS" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nWE" SITE "N16" ; +#IOBUF PORT "DRAM_nWE" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_nCS" SITE "M15" ; + +#LOCATE COMP "DRAM_DQ[0]" SITE "P14" ; +#LOCATE COMP "DRAM_DQ[1]" SITE "R15" ; +#LOCATE COMP "DRAM_DQ[2]" SITE "N14" ; +#LOCATE COMP "DRAM_DQ[3]" SITE "R16" ; +#LOCATE COMP "DRAM_DQ[4]" SITE "J14" ; +#LOCATE COMP "DRAM_DQ[5]" SITE "P15" ; +#LOCATE COMP "DRAM_DQ[6]" SITE "K14" ; +#LOCATE COMP "DRAM_DQ[7]" SITE "P16" ; +#LOCATE COMP "DRAM_DQ[8]" SITE "D14" ; +#LOCATE COMP "DRAM_DQ[9]" SITE "H14" ; +#LOCATE COMP "DRAM_DQ[10]" SITE "H12" ; +#LOCATE COMP "DRAM_DQ[11]" SITE "H13" ; +#LOCATE COMP "DRAM_DQ[12]" SITE "E14" ; +#LOCATE COMP "DRAM_DQ[13]" SITE "H15" ; +#LOCATE COMP "DRAM_DQ[14]" SITE "J13" ; +#LOCATE COMP "DRAM_DQ[15]" SITE "J16" ; + +#LOCATE COMP "DRAM_DQM[0]" SITE "M13" ; +#IOBUF PORT "DRAM_DQM[0]" SLEWRATE=FAST ; +#LOCATE COMP "DRAM_DQM[1]" SITE "F14" ; +#IOBUF PORT "DRAM_DQM[1]" SLEWRATE=FAST ; + + + + +### USB (chip located on the motherboard) ### +#LOCATE COMP "USB_MB_TX" SITE "M11" ; +#IOBUF PORT "USB_MB_TX" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_RX" SITE "N12" ; +#IOBUF PORT "USB_MB_RX" PULLMODE=UP ; +#LOCATE COMP "USB_MB_RTS" SITE "N11" ; +#IOBUF PORT "USB_MB_RTS" SLEWRATE=FAST ; +#LOCATE COMP "USB_MB_CTS" SITE "M12" ; +#IOBUF PORT "USB_MB_CTS" PULLMODE=UP ; + + +### PMOD1 ### +#LOCATE COMP "dbg_leds[16]" SITE "P1" ; +#LOCATE COMP "dbg_leds[17]" SITE "N4" ; +#LOCATE COMP "dbg_leds[18]" SITE "P2" ; +#LOCATE COMP "dbg_leds[19]" SITE "P5" ; +#LOCATE COMP "dbg_leds[20]" SITE "R1" ; +#LOCATE COMP "dbg_leds[21]" SITE "N5" ; +#LOCATE COMP "dbg_leds[22]" SITE "R2" ; +#LOCATE COMP "dbg_leds[23]" SITE "N6" ; + + +### PMOD2 ### +#LOCATE COMP "dbg_leds[24]" SITE "R3" ; +#LOCATE COMP "dbg_leds[25]" SITE "P11" ; +#LOCATE COMP "dbg_leds[26]" SITE "P12" ; +#LOCATE COMP "dbg_leds[27]" SITE "T3" ; +#LOCATE COMP "dbg_leds[28]" SITE "R4" ; +#LOCATE COMP "dbg_leds[29]" SITE "R12" ; +#LOCATE COMP "dbg_leds[30]" SITE "T13" ; +#LOCATE COMP "dbg_leds[31]" SITE "R5" ; + + +### PMOD3 ### +#LOCATE COMP "dbg_leds[8]" SITE "B2" ; +#LOCATE COMP "dbg_leds[9]" SITE "B3" ; +#LOCATE COMP "dbg_leds[10]" SITE "A4" ; +#LOCATE COMP "dbg_leds[11]" SITE "D4" ; +#LOCATE COMP "dbg_leds[12]" SITE "A2" ; +#LOCATE COMP "dbg_leds[13]" SITE "B4" ; +#LOCATE COMP "dbg_leds[14]" SITE "C3" ; +#LOCATE COMP "dbg_leds[15]" SITE "C4" ; + + +### PMOD4 ### +#LOCATE COMP "dbg_leds[0]" SITE "J4" ; +#LOCATE COMP "dbg_leds[1]" SITE "J5" ; +#LOCATE COMP "dbg_leds[2]" SITE "H4" ; +#LOCATE COMP "dbg_leds[3]" SITE "E4" ; +#LOCATE COMP "dbg_leds[4]" SITE "J3" ; +#LOCATE COMP "dbg_leds[5]" SITE "H3" ; +#LOCATE COMP "dbg_leds[6]" SITE "E3" ; +#LOCATE COMP "dbg_leds[7]" SITE "D3" ; + + +### Ethernet ### +#LOCATE COMP "ETH_CLK_EN" SITE "B1" ; +#LOCATE COMP "ETH_nRESET" SITE "C2" ; + +#LOCATE COMP "ETH_nLED_Y" SITE "F1" ; +#LOCATE COMP "ETH_nLED_G" SITE "G2" ; + +#LOCATE COMP "ETH_MDC" SITE "J1" ; +#LOCATE COMP "ETH_MDIO" SITE "H2" ; +#IOBUF PORT "ETH_MDIO" OPENDRAIN=ON SLEWRATE=FAST ; +#LOCATE COMP "ETH_MDINT" SITE "G1" ; +#IOBUF PORT "ETH_MDINT" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_REF_CLK" SITE "P3" ; + +#LOCATE COMP "ETH_TX_CLK" SITE "M4" ; +#IOBUF PORT "ETH_TX_CLK" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TX_CTL" SITE "N3" ; +#IOBUF PORT "ETH_TX_CTL" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[0]" SITE "M3" ; +#IOBUF PORT "ETH_TXD[0]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[1]" SITE "L4" ; +#IOBUF PORT "ETH_TXD[1]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[2]" SITE "K4" ; +#IOBUF PORT "ETH_TXD[2]" SLEWRATE=FAST ; +#LOCATE COMP "ETH_TXD[3]" SITE "K3" ; +#IOBUF PORT "ETH_TXD[3]" SLEWRATE=FAST ; + +#LOCATE COMP "ETH_RX_CLK" SITE "K1" ; +#LOCATE COMP "ETH_RX_CTL" SITE "K2" ; +#LOCATE COMP "ETH_RXD[0]" SITE "L1" ; +#LOCATE COMP "ETH_RXD[1]" SITE "L2" ; +#LOCATE COMP "ETH_RXD[2]" SITE "M1" ; +#LOCATE COMP "ETH_RXD[3]" SITE "M2" ; + + +### Extras ### +#LOCATE COMP "EXT[1]" SITE "P13" ; +#LOCATE COMP "EXT[2]" SITE "R13" ; +#LOCATE COMP "EXT[3]" SITE "A3" ; +#LOCATE COMP "EXT[4]" SITE "A5" ; +#LOCATE COMP "EXT[5]" SITE "B5" ; +#LOCATE COMP "EXT[6]" SITE "C5" ; +#LOCATE COMP "EXT[7]" SITE "C6" ; +#LOCATE COMP "EXT[8]" SITE "D5" ; +#LOCATE COMP "EXT[9]" SITE "D6" ; +#LOCATE COMP "EXT[10]" SITE "A11" ; +#LOCATE COMP "EXT[11]" SITE "A12" ; +#LOCATE COMP "EXT[12]" SITE "B8" ; +#LOCATE COMP "EXT[13]" SITE "B9" ; +#LOCATE COMP "EXT[14]" SITE "B11" ; +#LOCATE COMP "EXT[15]" SITE "C9" ; +#LOCATE COMP "EXT[16]" SITE "C11" ; +#LOCATE COMP "EXT[17]" SITE "D11" ; +#LOCATE COMP "EXT[18]" SITE "D12" ; +#LOCATE COMP "EXT[19]" SITE "E10" ; +#LOCATE COMP "EXT[20]" SITE "E11" ; +#LOCATE COMP "EXT[21]" SITE "E12" ; +#LOCATE COMP "EXT[22]" SITE "L3" ; +#LOCATE COMP "EXT[23]" SITE "M6" ; +#LOCATE COMP "EXT[24]" SITE "N1" ; +#LOCATE COMP "EXT[25]" SITE "P4" ; +#LOCATE COMP "EXT[26]" SITE "P6" ; +#LOCATE COMP "EXT[27]" SITE "T2" ; +#LOCATE COMP "EXT[28]" SITE "T4" ; +#LOCATE COMP "EXT[29]" SITE "E2" ; +#LOCATE COMP "EXT[30]" SITE "F2" ; +#LOCATE COMP "EXT[31]" SITE "F5" ; +#LOCATE COMP "EXT[32]" SITE "G4" ; +#LOCATE COMP "EXT[33]" SITE "G5" ; +#LOCATE COMP "EXT[34]" SITE "J2" ; diff --git a/10-PipelinedOperators/Board/concat/pipelinedOperators.ucf b/10-PipelinedOperators/Board/concat/pipelinedOperators.ucf new file mode 100644 index 0000000..b145465 --- /dev/null +++ b/10-PipelinedOperators/Board/concat/pipelinedOperators.ucf @@ -0,0 +1,19 @@ +#------------------------------------------------------------------------------- +# Clock and reset +# +NET "clock" LOC = "A10"; +NET "reset_N" LOC = "D3" | PULLUP; + +#------------------------------------------------------------------------------- +# Analog outputs +# +NET "xOut" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +NET "yOut" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +#NET "xOut" LOC = "G4" ; +#NET "yOut" LOC = "G5" ; + +#------------------------------------------------------------------------------- +# Trigger output +# +NET "triggerOut" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW; +#NET "triggerOut" LOC = "D2" ; diff --git a/10-PipelinedOperators/Board/concat/pipelinedOperators.vhd b/10-PipelinedOperators/Board/concat/pipelinedOperators.vhd new file mode 100644 index 0000000..a017aaf --- /dev/null +++ b/10-PipelinedOperators/Board/concat/pipelinedOperators.vhd @@ -0,0 +1,623 @@ +-- VHDL Entity Board.pipelineCounter_ebs3.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:16:01 08.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY pipelineCounter_ebs3 IS + GENERIC( + counterBitNb : positive := 16 + ); + PORT( + clock : IN std_ulogic; + reset_n : IN std_ulogic; + countOut : OUT unsigned (counterBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END pipelineCounter_ebs3 ; + + + + + +-- VHDL Entity PipelinedOperators.pipelineCounter.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:50:00 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY pipelineCounter IS + GENERIC( + bitNb : positive; + stageNb : positive + ); + PORT( + countOut : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END pipelineCounter ; + + + + + +-- VHDL Entity PipelinedOperators.pipelineAdder.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 08:50:15 03/11/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY pipelineAdder IS + GENERIC( + bitNb : positive; + stageNb : positive + ); + PORT( + sum : OUT signed (bitNb-1 DOWNTO 0); + clock : IN std_ulogic; + reset : IN std_ulogic; + cIn : IN std_ulogic; + cOut : OUT std_ulogic; + a : IN signed (bitNb-1 DOWNTO 0); + b : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END pipelineAdder ; + + + + + +-- VHDL Entity PipelinedOperators.parallelAdder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:43:49 28.04.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY parallelAdder IS + GENERIC( + bitNb : positive := 32 + ); + PORT( + sum : OUT signed (bitNb-1 DOWNTO 0); + cIn : IN std_ulogic; + cOut : OUT std_ulogic; + a : IN signed (bitNb-1 DOWNTO 0); + b : IN signed (bitNb-1 DOWNTO 0) + ); + +-- Declarations + +END parallelAdder ; + + + + + +ARCHITECTURE masterVersion OF parallelAdder IS + + signal sum_int: unsigned(sum'high+1 downto 0); + +BEGIN + + sum_int <= resize(unsigned(a), sum_int'length) + + resize(unsigned(b), sum_int'length) + + resize('0' & cIn, sum_int'length); + + sum <= signed(sum_int(sum'range)); + cOut <= sum_int(sum_int'high); + +END ARCHITECTURE masterVersion; + + + + + +ARCHITECTURE masterVersion OF pipelineAdder IS + + constant stageBitNb : positive := sum'length/stageNb; + subtype stageOperandType is signed(stageBitNb-1 downto 0); + type stageOperandVectorType is array(stageNb-1 downto 0) of stageOperandType; + type stageOperandMatrixType is array(stageNb-1 downto 0) of stageOperandVectorType; + subtype carryType is std_ulogic_vector(stageNb downto 0); + + signal a_int, b_int, sum_int : stageOperandMatrixType; + signal carryIn, carryOut : carryType; + + COMPONENT parallelAdder + GENERIC ( + bitNb : positive := 32 + ); + PORT ( + sum : OUT signed (bitNb-1 DOWNTO 0); + cIn : IN std_ulogic ; + cOut : OUT std_ulogic ; + a : IN signed (bitNb-1 DOWNTO 0); + b : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + carryIn(0) <= cIn; + + distributeInput: for wordIndex in stageOperandVectorType'range generate + a_int(wordIndex)(0) <= a(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb); + b_int(wordIndex)(0) <= b(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb); + end generate distributeInput; + + inputRegistersX: for wordIndex in stageOperandVectorType'high downto 1 generate + inputRegistersY: for pipeIndex in stageOperandMatrixType'high downto 1 generate + upperTriangle: if wordIndex >= pipeIndex generate + inputRegisters: process(reset, clock) + begin + if reset = '1' then + a_int(wordIndex)(pipeIndex) <= (others => '0'); + b_int(wordIndex)(pipeIndex) <= (others => '0'); + elsif rising_edge(clock) then + a_int(wordIndex)(pipeIndex) <= a_int(wordIndex)(pipeIndex-1); + b_int(wordIndex)(pipeIndex) <= b_int(wordIndex)(pipeIndex-1); + end if; + end process inputRegisters; + end generate upperTriangle; + end generate inputRegistersY; + end generate inputRegistersX; + + operation: for index in stageOperandVectorType'range generate + partialAdder: parallelAdder + GENERIC MAP (bitNb => stageBitNb) + PORT MAP ( + a => a_int(index)(index), + b => b_int(index)(index), + sum => sum_int(index)(index), + cIn => carryIn(index), + cOut => carryOut(index) + ); + carryRegisters: process(reset, clock) + begin + if reset = '1' then + carryIn(index+1) <= '0'; + elsif rising_edge(clock) then + carryIn(index+1) <= carryOut(index); + end if; + end process carryRegisters; + end generate operation; + + outputRegistersX: for wordIndex in stageOperandVectorType'range generate + outputRegistersY: for pipeIndex in stageOperandMatrixType'range generate + lowerTriangle: if wordIndex < pipeIndex generate + outputRegisters: process(reset, clock) + begin + if reset = '1' then + sum_int(wordIndex)(pipeIndex) <= (others => '0'); + elsif rising_edge(clock) then + sum_int(wordIndex)(pipeIndex) <= sum_int(wordIndex)(pipeIndex-1); + end if; + end process outputRegisters; + end generate lowerTriangle; + end generate outputRegistersY; + end generate outputRegistersX; + + packOutput: for index in stageOperandVectorType'range generate + sum(index*stageBitNb+stageBitNb-1 downto index*stageBitNb) <= + sum_int(index)(stageOperandMatrixType'high); + end generate packOutput; + + cOut <= carryOut(carryOut'high-1); + +END ARCHITECTURE masterVersion; + + + + +ARCHITECTURE masterVersion OF pipelineCounter IS + + signal initCounter : unsigned(countOut'length/stageNb-1 downto 0); + signal b : signed(countOut'range); + signal sum : signed(countOut'range); + + COMPONENT pipelineAdder + GENERIC ( + bitNb : positive := 32; + stageNb : positive := 4 + ); + PORT ( + reset : IN std_ulogic; + clock : IN std_ulogic; + cIn : IN std_ulogic; + a : IN signed (bitNb-1 DOWNTO 0); + b : IN signed (bitNb-1 DOWNTO 0); + sum : OUT signed (bitNb-1 DOWNTO 0); + cOut : OUT std_ulogic + ); + END COMPONENT; + +BEGIN + + adder: pipelineAdder + GENERIC MAP ( + bitNb => countOut'length, + stageNb => stageNb + ) + PORT MAP ( + reset => reset, + clock => clock, + cIn => '0', + a => sum, + b => b, + sum => sum, + cOut => open + ); + + prepareBInput: process(reset, clock) + begin + if reset = '1' then + initCounter <= (others => '0'); + elsif rising_edge(clock) then + if initCounter < stageNb then + initCounter <= initCounter + 1; + end if; + end if; + end process prepareBInput; + + selectInitOrRun: process(initCounter, sum) + begin + if initCounter < stageNb-1 then + b <= signed(resize(initCounter+stageNb-1, b'length)); + countOut <= resize(initCounter, countOut'length); + else + b <= to_signed(stageNb-1, b'length); + countOut <= unsigned(sum); + end if; + end process selectInitOrRun; + +END ARCHITECTURE masterVersion; + + + + +-- VHDL Entity Board.DFF.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:05 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY DFF IS + PORT( + CLK : IN std_uLogic; + CLR : IN std_uLogic; + D : IN std_uLogic; + Q : OUT std_uLogic + ); + +-- Declarations + +END DFF ; + + + + + +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + + + + + +-- VHDL Entity Board.inverterIn.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:14 02/19/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY inverterIn IS + PORT( + in1 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END inverterIn ; + + + + + +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + + + + + +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; + + + + +-- +-- VHDL Architecture Board.pipelineCounter_ebs3.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 11:16:01 08.05.2023 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +-- LIBRARY Board; +-- LIBRARY Lattice; +-- LIBRARY PipelinedOperators; + +ARCHITECTURE struct OF pipelineCounter_ebs3 IS + + -- Architecture declarations + constant pipelineStageNb: positive := 5; + + -- Internal signal declarations + SIGNAL clk_sys : std_ulogic; + SIGNAL logic0 : std_ulogic; + SIGNAL logic1 : std_uLogic; + SIGNAL reset : std_ulogic; + SIGNAL resetSynch : std_ulogic; + SIGNAL resetSynch_n : std_ulogic; + + + -- Component Declarations + COMPONENT DFF + PORT ( + CLK : IN std_uLogic ; + CLR : IN std_uLogic ; + D : IN std_uLogic ; + Q : OUT std_uLogic + ); + END COMPONENT; + COMPONENT inverterIn + PORT ( + in1 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT pll + PORT ( + clkIn100M : IN std_ulogic ; + en75M : IN std_ulogic ; + en50M : IN std_ulogic ; + en10M : IN std_ulogic ; + clk60MHz : OUT std_ulogic ; + clk75MHz : OUT std_ulogic ; + clk50MHz : OUT std_ulogic ; + clk10MHz : OUT std_ulogic ; + pllLocked : OUT std_ulogic + ); + END COMPONENT; + COMPONENT pipelineCounter + GENERIC ( + bitNb : positive; + stageNb : positive + ); + PORT ( + countOut : OUT unsigned (bitNb-1 DOWNTO 0); + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off +-- FOR ALL : DFF USE ENTITY Board.DFF; +-- FOR ALL : inverterIn USE ENTITY Board.inverterIn; +-- FOR ALL : pipelineCounter USE ENTITY PipelinedOperators.pipelineCounter; +-- FOR ALL : pll USE ENTITY Lattice.pll; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 5 eb5 + logic1 <= '1'; + + -- HDL Embedded Text Block 6 eb6 + logic0 <= '0'; + + + -- Instance port mappings. + I_dff : DFF + PORT MAP ( + CLK => clock, + CLR => reset, + D => logic1, + Q => resetSynch_n + ); + I_inv1 : inverterIn + PORT MAP ( + in1 => reset_n, + out1 => reset + ); + I_inv2 : inverterIn + PORT MAP ( + in1 => resetSynch_n, + out1 => resetSynch + ); + I_pll : pll + PORT MAP ( + clkIn100M => clock, + en75M => logic0, + en50M => logic0, + en10M => logic0, + clk60MHz => clk_sys, + clk75MHz => OPEN, + clk50MHz => OPEN, + clk10MHz => OPEN, + pllLocked => OPEN + ); + I_cnt : pipelineCounter + GENERIC MAP ( + bitNb => counterBitNb, + stageNb => pipelineStageNb + ) + PORT MAP ( + countOut => countOut, + clock => clk_sys, + reset => resetSynch + ); + +END struct; + + + + diff --git a/10-PipelinedOperators/Board/diamond/pipelinedOperators.bit b/10-PipelinedOperators/Board/diamond/pipelinedOperators.bit new file mode 100644 index 0000000..e4efb02 Binary files /dev/null and b/10-PipelinedOperators/Board/diamond/pipelinedOperators.bit differ diff --git a/10-PipelinedOperators/Board/diamond/pipelinedOperators.ldf b/10-PipelinedOperators/Board/diamond/pipelinedOperators.ldf new file mode 100644 index 0000000..f1ae61d --- /dev/null +++ b/10-PipelinedOperators/Board/diamond/pipelinedOperators.ldf @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/10-PipelinedOperators/Board/diamond/programmer.xcf b/10-PipelinedOperators/Board/diamond/programmer.xcf new file mode 100644 index 0000000..468a2da --- /dev/null +++ b/10-PipelinedOperators/Board/diamond/programmer.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Renesas + ECP5U + LFE5U-25F + All + LFE5U-25F + + 8 + 11111111 + 1 + 0 + + + 04/11/23 16:14:28 + 0xA4B0 + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 4 + + + USB2 + FTUSB-0 + LFE5U-25F A Location 0000 Serial 018VFVT3A + + diff --git a/10-PipelinedOperators/Board/diamond/reveal_analyze.rva b/10-PipelinedOperators/Board/diamond/reveal_analyze.rva new file mode 100644 index 0000000..4249e0e --- /dev/null +++ b/10-PipelinedOperators/Board/diamond/reveal_analyze.rva @@ -0,0 +1,638 @@ + + + lun. 6. mars 14:29:10 2023 + + + + + + + + + + + + 1 + + 0 + 1. LFE5U-25F + 0x41111043 + true + false + + 8 + reveal_config.rvl + reveal_config.rvs + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/10-PipelinedOperators/Board/diamond/reveal_config.rvl b/10-PipelinedOperators/Board/diamond/reveal_config.rvl new file mode 100644 index 0000000..28d2f1c --- /dev/null +++ b/10-PipelinedOperators/Board/diamond/reveal_config.rvl @@ -0,0 +1,662 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/10-PipelinedOperators/Board/diamond/strategy.sty b/10-PipelinedOperators/Board/diamond/strategy.sty new file mode 100644 index 0000000..a2b5a4a --- /dev/null +++ b/10-PipelinedOperators/Board/diamond/strategy.sty @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/10-PipelinedOperators/Board/hdl/DFF_sim.vhd b/10-PipelinedOperators/Board/hdl/DFF_sim.vhd new file mode 100644 index 0000000..cf8868a --- /dev/null +++ b/10-PipelinedOperators/Board/hdl/DFF_sim.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE sim OF DFF IS +BEGIN + + process(clk, clr) + begin + if clr = '1' then + q <= '0'; + elsif rising_edge(clk) then + q <= d; + end if; + end process; + +END ARCHITECTURE sim; + diff --git a/10-PipelinedOperators/Board/hdl/buff_sim.vhd b/10-PipelinedOperators/Board/hdl/buff_sim.vhd new file mode 100644 index 0000000..8ad27be --- /dev/null +++ b/10-PipelinedOperators/Board/hdl/buff_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF buff IS +BEGIN + + out1 <= in1; + +END ARCHITECTURE sim; + diff --git a/10-PipelinedOperators/Board/hdl/inverterIn_sim.vhd b/10-PipelinedOperators/Board/hdl/inverterIn_sim.vhd new file mode 100644 index 0000000..fb039ac --- /dev/null +++ b/10-PipelinedOperators/Board/hdl/inverterIn_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverterIn IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/10-PipelinedOperators/Board/hdl/inverter_sim.vhd b/10-PipelinedOperators/Board/hdl/inverter_sim.vhd new file mode 100644 index 0000000..ca5b6b5 --- /dev/null +++ b/10-PipelinedOperators/Board/hdl/inverter_sim.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE sim OF inverter IS +BEGIN + + out1 <= NOT in1; + +END ARCHITECTURE sim; + diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_entity.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_entity.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_struct.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_struct.vhg._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_entity.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_struct.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_entity.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_struct.vhg._fpf b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/Board/hds/@d@f@f/symbol.sb b/10-PipelinedOperators/Board/hds/@d@f@f/symbol.sb new file mode 100644 index 0000000..555b689 --- /dev/null +++ b/10-PipelinedOperators/Board/hds/@d@f@f/symbol.sb @@ -0,0 +1,1211 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2004,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 157,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +decl (Decl +n "CLR" +t "std_uLogic" +o 2 +suid 3,0 +) +) +uid 158,0 +) +*3 (LogPort +port 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+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/10-PipelinedOperators/PipelinedOperators/hdl/parallelAdder_studentVersion.vhd b/10-PipelinedOperators/PipelinedOperators/hdl/parallelAdder_studentVersion.vhd new file mode 100644 index 0000000..63da026 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hdl/parallelAdder_studentVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE studentVersion OF parallelAdder IS +BEGIN + + sum <= (others => '0'); + cOut <= '0'; + +END ARCHITECTURE studentVersion; diff --git a/10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_noPipe.vhd b/10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_noPipe.vhd new file mode 100644 index 0000000..8da0b7a --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_noPipe.vhd @@ -0,0 +1,45 @@ +ARCHITECTURE noPipe OF pipelineAdder IS + + constant stageBitNb : positive := sum'length/stageNb; + subtype stageOperandType is signed(stageBitNb-1 downto 0); + type stageOperandArrayType is array(stageNb-1 downto 0) of stageOperandType; + subtype carryType is std_ulogic_vector(stageNb downto 0); + + signal a_int, b_int, sum_int : stageOperandArrayType; + signal carryIn : carryType; + + COMPONENT parallelAdder + GENERIC ( + bitNb : positive := 32 + ); + PORT ( + sum : OUT signed (bitNb-1 DOWNTO 0); + cIn : IN std_ulogic ; + cOut : OUT std_ulogic ; + a : IN signed (bitNb-1 DOWNTO 0); + b : IN signed (bitNb-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + carryIn(0) <= cIn; + + pipeline: for index in stageOperandArrayType'range generate + a_int(index) <= a(index*stageBitNb+stageBitNb-1 downto index*stageBitNb); + b_int(index) <= b(index*stageBitNb+stageBitNb-1 downto index*stageBitNb); + partialAdder: parallelAdder + GENERIC MAP (bitNb => stageBitNb) + PORT MAP ( + a => a_int(index), + b => b_int(index), + sum => sum_int(index), + cIn => carryIn(index), + cOut => carryIn(index+1) + ); + sum(index*stageBitNb+stageBitNb-1 downto index*stageBitNb) <= sum_int(index); + end generate pipeline; + + cOut <= carryIn(carryIn'high); + +END ARCHITECTURE noPipe; diff --git a/10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_studentVersion.vhd b/10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_studentVersion.vhd new file mode 100644 index 0000000..c5475b6 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_studentVersion.vhd @@ -0,0 +1,7 @@ +ARCHITECTURE studentVersion OF pipelineAdder IS +BEGIN + + sum <= (others => '0'); + cOut <= '0'; + +END ARCHITECTURE studentVersion; diff --git a/10-PipelinedOperators/PipelinedOperators/hdl/pipelineCounter_studentVersion.vhd b/10-PipelinedOperators/PipelinedOperators/hdl/pipelineCounter_studentVersion.vhd new file mode 100644 index 0000000..fff62b4 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hdl/pipelineCounter_studentVersion.vhd @@ -0,0 +1,43 @@ +ARCHITECTURE studentVersion OF pipelineCounter IS + + signal b : signed(countOut'range); + signal sum : signed(countOut'range); + + COMPONENT pipelineAdder + GENERIC ( + bitNb : positive := 32; + stageNb : positive := 4 + ); + PORT ( + reset : IN std_ulogic; + clock : IN std_ulogic; + cIn : IN std_ulogic; + a : IN signed (bitNb-1 DOWNTO 0); + b : IN signed (bitNb-1 DOWNTO 0); + sum : OUT signed (bitNb-1 DOWNTO 0); + cOut : OUT std_ulogic + ); + END COMPONENT; + +BEGIN + + b <= to_signed(1, b'length); + + adder: pipelineAdder + GENERIC MAP ( + bitNb => countOut'length, + stageNb => stageNb + ) + PORT MAP ( + reset => reset, + clock => clock, + cIn => '0', + a => sum, + b => b, + sum => sum, + cOut => open + ); + + countOut <= unsigned(sum); + +END ARCHITECTURE studentVersion; diff --git a/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_parallelAdder_studentVersion.vhd._fpf b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_parallelAdder_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_parallelAdder_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_paralleladder_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_paralleladder_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_paralleladder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_noPipe.vhd._fpf b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_noPipe.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_noPipe.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_studentVersion.vhd._fpf b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineCounter_studentVersion.vhd._fpf b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineCounter_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineCounter_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineadder_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineadder_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineadder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelinecounter_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelinecounter_entity.vhg._fpf new file mode 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100644 index 0000000..ce32375 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hdl/parallelAdder_tester_test.vhd @@ -0,0 +1,48 @@ +ARCHITECTURE test OF parallelAdder_tester IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + signal sReset: std_uLogic := '1'; + + constant aMax: signed(a'range) := (a'high => '0', others => '1'); + constant aIncr: signed(a'range) := shift_right(aMax, 4)+1; + constant bIncr: signed(b'range) := shift_right(aMax, 4)+1; + signal a_int, b_int, sum_int: signed(a'range); + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + sReset <= '1', '0' after 2*clockPeriod; + + ------------------------------------------------------------------------------ + -- test sequence + process + begin + a_int <= (a_int'high => '1', others => '0'); + b_int <= (b_int'high => '1', others => '0'); + wait until sReset = '0'; + -- data values + while a_int < aMax-aIncr loop + a_int <= a_int + aIncr; + b_int <= b_int + bIncr; + wait until rising_edge(sClock); + assert sum = a_int + b_int + report "sum is wrong !" + severity error; + end loop; + -- stop simulation + assert false + report cr & cr & + "End of Simulation" & + cr + severity failure; + wait; + end process; + + cIn <= '0'; + a <= a_int; + b <= b_int; + sum_int <= a_int + b_int; + +END ARCHITECTURE test; diff --git a/10-PipelinedOperators/PipelinedOperators_test/hdl/pipelineAdder_tester_test.vhd b/10-PipelinedOperators/PipelinedOperators_test/hdl/pipelineAdder_tester_test.vhd new file mode 100644 index 0000000..2388559 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hdl/pipelineAdder_tester_test.vhd @@ -0,0 +1,68 @@ +ARCHITECTURE test OF pipelineAdder_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + signal sReset: std_uLogic := '1'; + + constant pipeDelay: positive := 4; + constant aMax: signed(a'range) := (a'high => '0', others => '1'); + constant aIncr: signed(a'range) := shift_right(aMax, 3)+1 + 32; + constant bIncr: signed(b'range) := shift_right(aMax, 3)+1 + 32; + signal a_int, b_int, sumNoPipe: signed(a'range); + + type sumArrayType is array(1 to stageNb-1) of signed(sumNoPipe'range); + signal sumArray : sumArrayType := (others => (others => '0')); + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + sReset <= '1', '0' after 2*clockPeriod; + reset <= sReset; + + ------------------------------------------------------------------------------ + -- test sequence + process + begin + a_int <= (a_int'high => '1', others => '0'); + b_int <= (b_int'high => '1', others => '0'); + wait until sReset = '0'; + -- data values + while a_int < aMax-aIncr loop + a_int <= a_int + aIncr; + b_int <= b_int + bIncr; + wait until rising_edge(sClock); + end loop; + -- stop simulation + for index in 1 to pipeDelay loop + wait until rising_edge(sClock); + end loop; + assert false + report cr & cr & + "End of Simulation" & + cr + severity failure; + wait; + end process; + + cIn <= '0'; + a <= a_int; + b <= b_int; + sumNoPipe <= a_int + b_int; + + ------------------------------------------------------------------------------ + -- delay sum + process(sClock) + begin + if rising_edge(sClock) then + sumArray(1) <= sumNoPipe; + sumArray(2 to sumArray'length) <= sumArray(1 to sumArray'length-1); + assert sum = sumArray(sumArray'length-1) + report "sum is wrong !" + severity error; + end if; + end process; + +END ARCHITECTURE test; diff --git a/10-PipelinedOperators/PipelinedOperators_test/hdl/pipelineCounter_tester_test.vhd b/10-PipelinedOperators/PipelinedOperators_test/hdl/pipelineCounter_tester_test.vhd new file mode 100644 index 0000000..b6f992b --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hdl/pipelineCounter_tester_test.vhd @@ -0,0 +1,24 @@ +-- +-- VHDL Architecture PipelinedOperators_test.PipelineCounter_tester.test +-- +-- Created: +-- by - zas.UNKNOWN (ZELL) +-- at - 16:00:38 02/20/2020 +-- +-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5) +-- +ARCHITECTURE test OF PipelineCounter_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal sClock: std_uLogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- clock and reset + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + reset <= '1', '0' after 2*clockPeriod; + +END ARCHITECTURE test; + diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_parallelAdder_tester_test.vhd._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_parallelAdder_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_parallelAdder_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_struct.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tester_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tester_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineAdder_tester_test.vhd._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineAdder_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineAdder_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineCounter_tester_test.vhd._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineCounter_tester_test.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineCounter_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_struct.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tester_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tester_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_struct.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tester_entity.vhg._fpf b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tester_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tester_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/@d@a@c_tester_1/interface b/10-PipelinedOperators/PipelinedOperators_test/hds/@d@a@c_tester_1/interface new file mode 100644 index 0000000..b372831 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/@d@a@c_tester_1/interface @@ -0,0 +1,1035 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +packageRefs [ +(PackageRef +library "ieee" +unitName "std_logic_1164" +itemName "all" +) +(PackageRef +library "ieee" +unitName "numeric_std" +itemName "all" +) +] +) +version "15.1" +appVersion "2002.1a (Build 22)" +model (Symbol +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "D:\\Users\\ELN_labs\\VHDL_gen" +) +(vvPair +variable "SideDataDesignDir" +value "U:\\SEm_curves\\Test\\@d@a@c_tester\\interface.info" +) +(vvPair +variable "SideDataUserDir" +value "U:\\SEm_curves\\Test\\@d@a@c_tester\\interface.user" +) +(vvPair +variable "SourceDir" +value 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positive := 32; +constant pipelineStageNb: positive := 4; +constant clockFrequency : real := 60.0E6; +--constant clockFrequency : real := 66.0E6;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,12300,8500,13200" +st "Diagram Signals:" +blo "0,13000" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "0,5600,5500,6500" +st "Post User:" +blo "0,6300" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "0,5600,0,5600" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 24,0 +usingSuid 1 +emptyRow *72 (LEmptyRow +) +uid 1321,0 +optionalChildren [ +*73 (RefLabelRowHdr +) +*74 (TitleRowHdr +) +*75 (FilterRowHdr +) +*76 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*77 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*78 (GroupColHdr +tm "GroupColHdrMgr" +) +*79 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*80 (ModeColHdr +tm "BlockDiagramModeColHdrMgr" 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(LogicalDM +emptyRow *112 (LEmptyRow +) +uid 1350,0 +optionalChildren [ +*113 (RefLabelRowHdr +) +*114 (TitleRowHdr +) +*115 (FilterRowHdr +) +*116 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*117 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*118 (GroupColHdr +tm "GroupColHdrMgr" +) +*119 (NameColHdr +tm "GenericNameColHdrMgr" +) +*120 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*121 (InitColHdr +tm "GenericValueColHdrMgr" +) +*122 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*123 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 1362,0 +optionalChildren [ +*124 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *125 (MRCItem +litem &112 +pos 0 +dimension 20 +) +uid 1364,0 +optionalChildren [ +*126 (MRCItem +litem &113 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b/10-PipelinedOperators/PipelinedOperators_test/hds/pipeline@adder_tb/symbol.sb new file mode 100644 index 0000000..b00baa6 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/pipeline@adder_tb/symbol.sb @@ -0,0 +1,1216 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2001,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 105,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 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1363,0 +vaOverrides [ +] +) +] +) +uid 1349,0 +type 1 +) +activeModelName "BlockDiag" +) diff --git a/10-PipelinedOperators/PipelinedOperators_test/hds/pipeline@counter_tb/symbol.sb b/10-PipelinedOperators/PipelinedOperators_test/hds/pipeline@counter_tb/symbol.sb new file mode 100644 index 0000000..5cd8928 --- /dev/null +++ b/10-PipelinedOperators/PipelinedOperators_test/hds/pipeline@counter_tb/symbol.sb @@ -0,0 +1,1243 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2001,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 105,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 106,0 +optionalChildren [ +*14 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *15 (MRCItem +litem &1 +pos 3 +dimension 20 +) +uid 53,0 +optionalChildren [ +*16 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 56,0 +) +*17 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 58,0 +) +*18 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 60,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 54,0 +optionalChildren [ +*19 (MRCItem +litem &5 +pos 0 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"VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,9,0" +) +xt "0,750,3600,1950" +st "Buffer0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +) +DeclarativeBlock *22 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44300,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,5200,44000,6200" +st "User:" +blo "42000,6000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6200,44000,6200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 126,0 +) diff --git a/10-PipelinedOperators/Prefs/hds.hdp b/10-PipelinedOperators/Prefs/hds.hdp new file mode 100644 index 0000000..e8e0234 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds.hdp @@ -0,0 +1,28 @@ +[Concat] +Board = $HDS_PROJECT_DIR/../Board/concat +[ModelSim] +Board = $SCRATCH_DIR/Board +Lattice = $SCRATCH_DIR/Lattice +PipelinedOperators = $SCRATCH_DIR/PipelinedOperators +PipelinedOperators_test = $SCRATCH_DIR/PipelinedOperators_test +[hdl] +Board = $HDS_PROJECT_DIR/../Board/hdl +ieee = $HDS_HOME/hdl_libs/ieee/hdl +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hdl +PipelinedOperators = $HDS_PROJECT_DIR/../PipelinedOperators/hdl +PipelinedOperators_test = $HDS_PROJECT_DIR/../PipelinedOperators_test/hdl +std = $HDS_HOME/hdl_libs/std/hdl +[hds] +Board = $HDS_PROJECT_DIR/../Board/hds +ieee = $HDS_HOME/hdl_libs/ieee/hds +Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hds +PipelinedOperators = $HDS_PROJECT_DIR/../PipelinedOperators/hds +PipelinedOperators_test = $HDS_PROJECT_DIR/../PipelinedOperators_test/hds +std = $HDS_HOME/hdl_libs/std/hds +[hds_settings] +design_root = Board.pipelineCounter_ebs3(struct)pipeline@counter_ebs3/struct.bd +[library_type] +ieee = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/10-PipelinedOperators/Prefs/hds_team/shared.hdp b/10-PipelinedOperators/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..41c9387 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_team/shared.hdp @@ -0,0 +1,23 @@ +[hds_settings] +version = 1 +project_description = The standard HDS shared project +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +synopsys = $HDS_HOME/hdl_libs/synopsys/hds +verilog = $HDS_HOME/hdl_libs/verilog/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds + +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +synopsys = $HDS_HOME/hdl_libs/synopsys/hdl +verilog = $HDS_HOME/hdl_libs/verilog/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl + +[library_type] +ieee = standard +std = standard +synopsys = standard +verilog = standard +vital2000 = standard diff --git a/10-PipelinedOperators/Prefs/hds_team/v2018.1/hds_team_prefs b/10-PipelinedOperators/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/10-PipelinedOperators/Prefs/hds_team/v2018.1/title_block.tmpl b/10-PipelinedOperators/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg 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"65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/10-PipelinedOperators/Prefs/hds_team/v2019.2/hds_team_prefs b/10-PipelinedOperators/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/10-PipelinedOperators/Prefs/hds_team/v2019.2/title_block.tmpl b/10-PipelinedOperators/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/10-PipelinedOperators/Prefs/hds_team/v2019.3/hds_team_prefs b/10-PipelinedOperators/Prefs/hds_team/v2019.3/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_team/v2019.3/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/10-PipelinedOperators/Prefs/hds_team/v2019.3/title_block.tmpl b/10-PipelinedOperators/Prefs/hds_team/v2019.3/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_team/v2019.3/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/hds_user_prefs b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/hds_user_prefs new file mode 100644 index 0000000..437abb4 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/hds_user_prefs @@ -0,0 +1,6094 @@ +version "49.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Atom" +second "atom %(p):%(l)" +) +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl %(p):%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Sublime" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/ElN_cursor.hdp" +"/home/francois/Favorites/ElN_local/Labs/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SVN/ElN_cursor/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs_SI/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/ElN/Labs/ElN_labs/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/04-Lissajous/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/Labs/SEm_labs/10-PipelinedOperators/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/SEm_labs/10-PipelinedOperators/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "$HDS_TEAM_VER/title_block.tmpl" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "courier,8,1" +) +teamPrefsPath "" +remoteSimPath "$HDS_TEAM_VER/remote" +mwMVL4 1 +mwVerilogUseSynthesisPragmas 0 +mwVhdlUseBusSlicesChkBox 0 +mwVerilogUseBusSlicesChkBox 0 +vmCheckInDesc "" +userVariables [ +(pair +first "concat_file" +second "concatenated" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +] +defaultCategoryTemplates [ +1 +"architecture.vhd" +] +defaultCategoryTemplatesPrefs [ +1 +0 +] +tasksOrder [ +"USER:Generate" +"USER:ModelSim Compile" +"USER:ModelSim Simulate" +"USER:ModelSim Flow" +"USER:Prepare for Synthesis" +"USER:Xilinx Project Navigator" +] +tasksToolbarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +"\"USER:Prepare for Synthesis\"" +"\"USER:Xilinx Project Navigator\"" +] +tasksMenubarOrder [ +"USER:Generate" +"\"USER:ModelSim Flow\"" +] +tasksShortcutbarOrder [ +"Setup DesignChecker" +"\"USER:ModelSim Compile\"" +"\"USER:ModelSim Flow\"" +"\"USER:ModelSim Simulate\"" +"USER:Generate" +"\"USER:Prepare for Synthesis\"" +] +taskPreferences [ +(TaskPref +taskName "\"USER:Actel Place and Route\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera MegaWizard\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:Altera SOPC Builder\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:C/C++ Wrapper Generator\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:DesignChecker Flow\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "true" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "true" +) +] +) +(TaskPref +taskName "\"USER:DesignChecker Flow\" USER:DesignChecker" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:DesignChecker Flow\" USER:Generate" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:FPGA Library Compile\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:FPGA Technology Setup\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "3" +) +(pair +first "onPulldownMenu" +second "" +) +(pair +first "onShortcutBar" +second "true" +) +(pair +first "onToolbar" +second "" +) +] +) +(TaskPref +taskName "\"USER:I/O Design Flow\"" +taskPrefStringMap [ +(pair +first "enabled" +second "" +) +(pair +first "hierLevel" +second "1" +) +(pair +first "onPulldownMenu" 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"H(A(C(Files),C(DesignUnits),C(LogicalObjects)),A(C(DesignHierarchy)))" +) +(Viewpoint_v2 +name "Logical Objects" +TreeListVPDatas [ +(TreeListVPData +theList "Design Units" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Language" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +ShowSymbols 1 +accessRights 2 +) +(TreeListVPData +theList "HDL Files" +columns [ +(TreeListVPData_Column +name "Type" +displayName "" +width 140 +) +(TreeListVPData_Column +name "Extends" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Size" +displayName "" +width 100 +) +(TreeListVPData_Column +name "Time Stamp" +displayName "" +width 120 +) +] +filterString "" +accessRights 2 +) +(TreeListVPData +theList "Hierarchy" +columns [ +(TreeListVPData_Column +name "Design Unit Name" +displayName "" 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a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk new file mode 100644 index 0000000..0b7cc38 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7a023d8 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/pipelineCounter.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..4eeef16 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..6cd6247 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,114 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "/usr/opt/HDS/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update Project" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilinx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$SYNTHESIS_BASE_DIR/../../Scripts/update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR/$DESIGN_NAME.vhd $CONCAT_DIR/$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"/usr/bin/perl" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"$SYNTHESIS_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$SYNTHESIS_HOME/bin/lin64/ise" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exePath" +"/usr/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/hds_user_prefs b/10-PipelinedOperators/Prefs/hds_user/v2018.1/hds_user_prefs new file mode 100644 index 0000000..9186cf1 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/hds_user_prefs @@ -0,0 +1,6831 @@ +version "48.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "log" +Description "Log File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\log.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad" +Description "Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "dly" +Description "Delay Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "syr" +Description "Xilinx Synthesis Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "par" +Description "Xilinx Place and Route Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "twr" +Description "Xilinx Static Timing Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "drc" +Description "Xilinx Design Rule Checking Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "bgn" +Description "Xilinx Bitstream Generation Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mrp" +Description "Xilinx Mapping Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pad_txt" +Description "Xilinx Pad Report" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncf" +Description "Xilinx Netlist Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "xcf" +Description "Xilinx Synthesis Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "pcf" +Description "Xilinx Place and Route Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ucf" +Description "Xilinx User Constraints File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ncd" +Description "Xilinx Floorplanner File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\ncd.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState 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+Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "js" +Description "Javascript" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jsFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "xml" +Description "xml file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "ipxact" +Description "IP-XACT file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xmlFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "css" +Description "HTML style sheet" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cssFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "gif" +Description "GIF image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\gifFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "jpg" +Description "JPG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\jpgFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "png" +Description "PNG image" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\pngFile.bmp" +DefaultAction "Open" +Actions [ +] +) +(FileTypeState +Extension "svap" +Description "SVAssistant project file" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\svapFile.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "Open" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +(ActionState +Name "View" +Tool "USER:SVAssistant Flow" +Arguments "project %(p)" +) +] +) +] +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l)" +) +(pair +first "Sublime Text" +second "sublime_text.exe \"%(p)\" -n%(l)" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l) -ro" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Notepad++" +win32DefaultViewer "Notepad++" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +defaultLanguage 11 +defaultVhdlDialect 11 +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 4 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "$TEMP" +projectPaths [ +"hds.hdp" +"D:\\Labs\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\Users\\oliver.gubler\\eda\\VHDL\\labs\\ELN_cursor\\Prefs\\hds.hdp" +"R:\\SYND\\Ele_2131\\ELN\\Labs\\Cursor\\ELN_cursor\\Prefs\\hds.hdp" +"C:\\work\\git\\Education\\Projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\projects\\Cursor_trial\\Prefs\\cursor.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\eln_labs.hdp" +"C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Prefs\\hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +" +defaultVerilogPackages "" +defaultFont "Verdana,9,0" +tableFont "Tahoma,10,0" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +printerName "FinePrint" +pageSizes [ +(PageSizeInfo +name "Letter" +width 783 +height 1013 +) +(PageSizeInfo +name "Letter Small" +type 2 +width 783 +height 1013 +) +(PageSizeInfo +name "Tabloid" +type 3 +width 1013 +height 1566 +) +(PageSizeInfo +name "Ledger" +type 4 +width 1013 +height 1566 +) +(PageSizeInfo +name "Legal" +type 5 +width 783 +height 1290 +) +(PageSizeInfo +name "Statement" +type 6 +width 506 +height 783 +) +(PageSizeInfo +name "Executive" +type 7 +width 667 +height 967 +) +(PageSizeInfo +name "A3" +type 8 +width 1077 +height 1523 +) +(PageSizeInfo +name "A4" +type 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+alignment 0 +) +(SmartTableVPData_Column +name "Type" +width 140 +alignment 0 +) +(SmartTableVPData_Column +name "Don't Touch Indicator" +width 20 +alignment 0 +) +(SmartTableVPData_Column +name "Name" +width 250 +alignment 0 +) +(SmartTableVPData_Column +name "Extends" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Language" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Size" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Time Stamp" +width 120 +alignment 0 +) +(SmartTableVPData_Column +name "Requirement References" +width -1 +alignment 0 +) +] +filterNames [ +"Architectures and Modules" +"Configurations" +"Entities" +"Files" +"Packages" +"SV Classes" +"SV Interfaces" +"SV Packages" +"SV Program Blocks" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" +) +] +WorkTabs [ +(WorkTab +name "Cursor" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Cursor" +primaryName "cursorCircuit" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Cursor_test" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Cursor_test" +primaryName "cursor_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Board" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Board" +primaryName "FPGA_cursor" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "LCD" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" 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"0,32768,49152" +) +tBlockLineVaSet (VaSet +vasetType 3 +) +tBlockConditionVaSet (VaSet +) +tBlockActionsVaSet (VaSet +) +tPriorityRadius 40 +tPriorityPadding 100 +tPriorityShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +tPriorityNameVaSet (VaSet +) +transitionShapeVaSet (VaSet +vasetType 3 +) +localDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +localDeclValueVaSet (VaSet +font "Courier New,8,0" +) +processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/generate.tsk b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..4490ea2 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,96 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR\\IND.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/hds_user_prefs b/10-PipelinedOperators/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..5228a7c --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6870 @@ +version "49.1" +SaPreferences [ +(CustomizeUserPreferences +version "1.0" +FileTypes [ +(FileTypeState +Extension "c" +Description "C Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\c_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "cpp" +Description "C++ Source File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\cpp_source.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +(ActionState +Name "Generate" +Tool "USER:C/C++ Wrapper Generator" +Arguments "" +) +] +) +(FileTypeState +Extension "xdb" +Description "Mentor Graphics Binary Synthesis File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\xdb.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "None" +Arguments "" +) +] +) +(FileTypeState +Extension "sdf" +Description "Standard Delay Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdf.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "mif" +Description "Memory Initialization File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\mif.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "hex" +Description "HEX-Format File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\hex.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "sdc" +Description "Synopsys Design Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "ctr" +Description "Constraint File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\sdc.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name "Open" +Tool "" +Arguments "" +) +] +) +(FileTypeState +Extension "rep" +Description "Report File" +Bitmap "$HDS_HOME\\resources\\bitmaps\\types\\rep.bmp" +DefaultAction "Open" +Actions [ +(ActionState +Name "New" +Tool "" +Arguments "" +) +(ActionState +Name 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+openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "WaveformGenerator" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "WaveformGenerator_test" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "Board" +showingHierarchy 0 +openLibs [ +"Board" +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "PipelinedOperators" +showingHierarchy 0 +openLibs [ +"PipelinedOperators" +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "PipelinedOperators_test" +showingHierarchy 0 +openLibs [ +"PipelinedOperators_test" +] +declHierarchy [ +] +activeViewpointIdx 0 +) +] +ViewpointsOnOutlookBar [ +"Requirements" +"Default Viewpoint" +"Version Management" +"HDL Files" +"Logical Objects" +"All Views" +] +lastActiveViewpoint "Default Viewpoint" +expandedTemplateNodes [ +] +taskTemplatePage 0 +SplitterClientPrefs [ +"mainSplitter" +(SplitterPreference +hidden 0 +expand 0 +size 180 +) +] +displayHierarchy 0 +xPos 0 +yPos 0 +width 1936 +height 1056 +activeSidePanelTab 2 +activeLibraryTab 1 +sidePanelSize 278 +showUnixHiddenFiles 0 +componentBrowserXpos -1351 +componentBrowserYpos 300 +componentBrowserWidth 300 +componentBrowserHeight 340 +componentBrowserLibraryNames [ +"Board" +] +) +(SmPreferences +version "1.1" +defaultSaveName "fsm" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 0 +gridSnapping 0 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +visibilityPrefs [ +(StringToBool +display "Architecture Declarations (VHDL)" +status 1 +) +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Concurrent Statements" +status 1 +) +(StringToBool +display "Global Actions" +status 1 +) +(StringToBool +display "Module Declarations (Verilog)" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +(StringToBool +display "Process Declarations (VHDL)" +status 1 +) +(StringToBool +display "Signal Status" +status 1 +) +(StringToBool +display "State Register Statements" +status 1 +) +] +clockNameVaSet (VaSet +) +clockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +resetNameVaSet (VaSet +) +resetShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +enableNameVaSet (VaSet +) +enableShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +) +ccondNameVaSet (VaSet +) +ccondShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,32768,49152" +) +recoveryShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +stateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +stateNameVaSet (VaSet +font "Verdana,12,1" +) +stateEncodingVaSet (VaSet +font "Verdana,9,1" +) +stateActionsVaSet (VaSet +) +stateActionShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +stateCaseVaSet (VaSet +font "Verdana,9,1" +) +cStateShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "0,0,32768" +lineWidth 2 +) +cStateNameVaSet (VaSet +font "Verdana,10,1" +) +junctionShapeVaSet (VaSet +vasetType 1 +fg "59904,39936,65280" +) +junctionNameVaSet (VaSet +font "Verdana,9,1" +) +junctionSymbolVaSet (VaSet +font "Verdana,10,1" +) +entryPointShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +) +interruptPointShapeVaSet (VaSet +vasetType 1 +fg "65535,0,0" +) +linkShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +linkNameVaSet (VaSet +font "Verdana,9,1" +) +exitPointShapeVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +) +wStateShapeVaSet (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "26368,26368,26368" +lineWidth 2 +) +wStateTextVaSet (VaSet +fg "0,0,32768" +font "Verdana,12,1" +) +tBlockShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +tBlockLineVaSet (VaSet +vasetType 3 +) +tBlockConditionVaSet (VaSet +) +tBlockActionsVaSet (VaSet +) +tPriorityRadius 40 +tPriorityPadding 100 +tPriorityShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +tPriorityNameVaSet (VaSet +) +transitionShapeVaSet (VaSet +vasetType 3 +) +localDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +localDeclValueVaSet (VaSet +font "Courier New,8,0" +) +processDeclLabelVaSet (VaSet +font "Verdana,9,1" +) +processDeclValueVaSet (VaSet +font "Courier New,8,0" +) +globalActionsLabelVaSet (VaSet +font "Verdana,9,1" +) +globalActionsValueVaSet (VaSet +) +stateRegBlkLabelVaSet (VaSet +font "Verdana,9,1" +) +stateRegBlkValueVaSet (VaSet +) +signalsGenStatusVaSet (VaSet +font "Verdana,9,1" +) +signalsGenStatusValueVaSet (VaSet +font "Courier New,8,0" +) +archConcurrentStatementBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +archConcurrentStatementBlockValueVaSet (VaSet +) +outputSignalStatus 1 +internalSignalStatus 2 +showPropsDlgMsg 1 +) +(H2gPreferences +filesAdded [ +] +h2gFileListHistory [ +] +libraryNames [ +] +librarySearchPath [ +] +embeddedSM 1 +searchLibraries [ +] +) +(TtPreferences +version "1.1" +defaultSaveName "tbl" +gridVisible 0 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +) +CompDirValueVaSet (VaSet +) +defaultPanelName "" +textVaSet (VaSet +) +highlightVaSet (VaSet +vasetType 0 +fg "65535,0,0" +bg "65535,0,0" +) +inputExpressionVaSet (VaSet +vasetType 0 +fg "39936,56832,65280" +bg "39936,56832,65280" +) +inputColumnVaSet (VaSet +vasetType 0 +fg "0,65535,65535" +bg "0,65535,65535" +) +outputExpressionVaSet (VaSet +vasetType 0 +fg "65535,65535,37120" +bg "65535,65535,37120" +) +outputColumnVaSet (VaSet +vasetType 0 +fg "65280,65280,46080" +bg "65280,65280,46080" +) +) +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 2147483647 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(SymbolPreferences +version "1.1" +defaultSaveName "" +packageListLabelVaSet (VaSet +font "Verdana,9,1" +) +packageListFontVaSet (VaSet +) +commentTextFontVaSet (VaSet +fg "0,0,32768" +) +commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "arial,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "65535,0,0" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "Verdana,9,1" +) +CompDirValueVaSet (VaSet +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "Verdana,9,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "Verdana,9,1" +) +cptPortFontVaSet (VaSet +font "Verdana,12,0" +) +genericInterfaceFontVaSet (VaSet +font "Courier New,8,0" +) +portRowVaSet (VaSet +vasetType 4 +font "Tahoma,10,0" +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +font "Tahoma,10,0" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +font "Tahoma,10,0" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +font "Tahoma,10,0" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +font "Tahoma,10,0" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "unsigned" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "Verdana,9,1" +) +DeclarativeBlockValueVaSet (VaSet +font "Courier New,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "Courier New,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk new file mode 100644 index 0000000..43e7dbe --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Diamond Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Diamond synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.ldf" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Diamond project .prjx file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$DIAMOND_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Diamond Project IDE" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Diamond tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\start_diamond.pl $DESIGN_NAME.ldf" +"captureOutput" +"1" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$LIBERO_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/generate.tsk b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..215aac5 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 2 +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..687aa77 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"64bit" +"0" +"compAlways" +"0" +"covSwitch" +"" +"coverNoSub" +"" +"dontAskAgain" +"0" +"enableMFCU" +"1" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"logFile" +"" +"logicalLib" +"1" +"mapAllLib" +"0" +"mapQuartusIPs" +"1" +"masterCov" +"0" +"peSe" +"EE" +"prevOnly" +"0" +"quartusSimDir" +"$HDS_PROJECT_DIR/QuartusIPSimLibs" +"replayScriptPath" +"" +"saveReplayScript" +"0" +"server" +"" +"showCmd" +"0" +"transcript" +"1" +"useFlatLibrary" +"0" +"useRemote" +"0" +"useShortName" +"0" +"vhdlSwitches" +" -nologo" +"vlogSwitches" +" -nologo" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..35db922 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,83 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "$MODELSIM_HOME" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..7a023d8 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,98 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Arguments1" +"do controller.do" +"Arguments2" +"controller.do" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/pipelineCounter.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"0" +"excludePSL" +"0" +"exepath" +"$MODELSIM_HOME" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk new file mode 100644 index 0000000..afac4f8 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk @@ -0,0 +1,162 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Prepare for Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp" +hasBitmap 1 +tooltip "generates a single file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "comment out library declarations for singles file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$CONCAT_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..0ea6209 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,163 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Xilinx Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Update.xise" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Update file references in the Xilnx project .xise file" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"$ISE_WORK_DIR" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$HDS_HOME\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"$DESIGN_NAME.xise" +"captureOutput" +"0" +"customPrompt" +"" +"descriptiveName" +"FPGA Technology Setup Plugin" +"initialDir" +"$ISE_WORK_DIR" +"isHierarchical" +"0" +"needsSave" +"0" +"pluginInfo" +"FPGA Technology Setup Plug-in v2.0 +For additional information, exceptions, compatibility issues and updates, visit SupportNet." +"pluginVersion" +"2.0" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"$ISE_HOME\\bin\\nt64\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"InputFile" +"U:/ELN_board/Board/concat/cursor.vhd" +"RunFromPlugin" +"False" +"RunInteractiveFromPlugIn" +"True" +"createAsciiFile" +"False" +"createBinaryFile" +"False" +"createFiles" +"True" +"createScriptFile" +"False" +"device" +"xc2vp7" +"edifngcPath" +"U:/ELN_board/Board/concat/cursor.vhd" +"effortLevel" +"Standard" +"family" +"virtex2p" +"familyName" +"virtex2p" +"netlist" +"other" +"netlistDefaultView" +"True" +"package" +"fg456" +"simulationModelLanguage" +"Modelsim_VHDL" +"speed" +"-7" +"synthTool" +"Xilinx XST" +"ucfPath" +"" +"vendor" +"xilinx" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt new file mode 100644 index 0000000..8e54448 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: new_document.txt +DESCRIPTION_START +This is the default template used for the creation of Text Document files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +# +# Created: +# by - %(user).%(group) (%(host)) +# at - %(time) %(date) +# +# using Mentor Graphics HDL Designer(TM) %(version) +# + diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/10-PipelinedOperators/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/10-PipelinedOperators/Scripts/cleanGenerated.bash b/10-PipelinedOperators/Scripts/cleanGenerated.bash new file mode 100755 index 0000000..ca088c6 --- /dev/null +++ b/10-PipelinedOperators/Scripts/cleanGenerated.bash @@ -0,0 +1,38 @@ +#!/bin/bash + +#================================================================================ +# cleanGenerated.bash - Clean intermediate files form folder +# +base_directory="$(dirname "$(readlink -f "$0")")" +pushd $base_directory +base_directory="$base_directory/.." + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#------------------------------------------------------------------------------- +# Remove generated and cache files +# +find $base_directory -type f -name '.cache.dat' | xargs -r rm -v +find $base_directory -type f -name '*.bak' | xargs -r rm -v +find $base_directory -type f -name '*.lck' | xargs -r rm -v +find $base_directory -type f -name '*.vhd.info' | xargs -r rm -v +find $base_directory -type f -name 'default_view' | xargs -r rm -v +find $base_directory -type f -name '*_entity.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_struct.vhd' | xargs -r rm -v +find $base_directory -type f -name '*_fsm.vhd' | xargs -r rm -v +find $base_directory -type f -name '*.vhg' | xargs -r rm -v +find $base_directory -type f -name '*.DS_Store' | xargs -r rm -v +find $base_directory -type d -name '.xrf' | xargs -r rm -Rv + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd diff --git a/10-PipelinedOperators/Scripts/cleanGenerated.bat b/10-PipelinedOperators/Scripts/cleanGenerated.bat new file mode 100644 index 0000000..0084edb --- /dev/null +++ b/10-PipelinedOperators/Scripts/cleanGenerated.bat @@ -0,0 +1,42 @@ +::============================================================================== +:: cleanGenerated.bat +:: Clean intermediate files from folder +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR="--------------------------------------------------------------------------------" + set INDENT=" " + + echo %SEPARATOR% + echo "-- %~nx0 Started!" + echo. +::------------------------------------------------------------------------------ +:: Delete intermediate files +:: +set base_directory="%cmd_location:"=%.." + +echo "Delete intermediate files in: %base_directory%" +del /f /s /a %base_directory%\*cache.dat +del /f /s /a %base_directory%\*.bak +del /f /s /a %base_directory%\*.lck +del /f /s /a %base_directory%\*.vhd.info +del /f /s /a %base_directory%\default_view +del /f /s /a %base_directory%\*_entity.vhd +del /f /s /a %base_directory%\*_struct.vhd +del /f /s /a %base_directory%\*_fsm.vhd +del /f /s /a %base_directory%\*.vhg +del /f /s /a %base_directory%\*.DS_Store + +echo "Delete intermediate directories in: %base_directory%" +for /d /r "%base_directory:"=%\" %%a in (.xrf\) do if exist "%%a" rmdir /s /q "%%a" + +:end + echo. + echo "-- %~nx0 Finished!" + echo %SEPARATOR% + popd + endlocal + goto:eof \ No newline at end of file diff --git a/10-PipelinedOperators/Scripts/cleanScratch.bat b/10-PipelinedOperators/Scripts/cleanScratch.bat new file mode 100644 index 0000000..098bf97 --- /dev/null +++ b/10-PipelinedOperators/Scripts/cleanScratch.bat @@ -0,0 +1,39 @@ +::============================================================================== +:: cleanScratch.bat +:: Clean scratch directory +:: +:start + @echo off + setlocal + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +if "%SCRATCH_DIR%" == "" ( + set SCRATCH_DIR=C:\temp\eda\ +) + +echo Delete scratch directory %SCRATCH_DIR% +if exist %SCRATCH_DIR% ( + echo Scratch directory found, deleting! + rmdir /S /Q "%SCRATCH_DIR%" +) else ( + echo Scratch directory not found! +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof \ No newline at end of file diff --git a/10-PipelinedOperators/Scripts/generateSSHKey.bash b/10-PipelinedOperators/Scripts/generateSSHKey.bash new file mode 100644 index 0000000..c906a16 --- /dev/null +++ b/10-PipelinedOperators/Scripts/generateSSHKey.bash @@ -0,0 +1,42 @@ +#!/bin/bash + +#============================================================================== +# generates an SSH key under default user location ~/.ssh/ +# and add the public key to the clipboard +# +# the email could be given when calling the script or be prompted later + +email='' +filename=$(hostname) +user=$(whoami) + +usage='Usage: generateSSH.bash [-e email]' + +# handle options +while getopts 'e:v' flag; do + case "${flag}" in + e) email=${OPTARG};; + esac +done + +# if the mail is not given, prompt it +if [ -z "$email" ] +then + echo -n "Please enter your mail: " + read email +fi +# generates the key-couple +# cat /dev/zero create an empty file to be filled by the key +# then ssh-keygen is called with: +# -q to call it silently (no verbose) +# -N with empty string to set no-password +# -t to specify the type of key +# -C to set the user mail +cat /dev/zero | ssh-keygen -q -N "" -t ed25519 -C "${user}@${filename}" -f ~/.ssh/$filename + +# then copy the public key into the clipboard +clip < ~/.ssh/${filename}.pub + +# print output for user +echo -e "\nThe keyfiles are generated under ~/.ssh/" +echo -e "\nThe public key is in your clipboard, ready to be added to your Github account." \ No newline at end of file diff --git a/10-PipelinedOperators/Scripts/hdlDesigner.bash b/10-PipelinedOperators/Scripts/hdlDesigner.bash new file mode 100755 index 0000000..4b54b46 --- /dev/null +++ b/10-PipelinedOperators/Scripts/hdlDesigner.bash @@ -0,0 +1,154 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer +# +base_directory="$(dirname "$(readlink -f "$0")")" +base_directory="$base_directory/.." +pushd $base_directory + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + +echo "$SEPARATOR" +echo "-- ${0##*/} Started!" +echo "" + +#-------------------------------------------------------------------------------- +# Parse command line options +# +command_switches='n:d:p:m:i:u:t:s:c:y:vh' +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + # set name and base directory +design_name=`basename $0 .bash` +design_directory=`dirname ${BASH_SOURCE[0]}` + +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + esac +done + # continue with preferences directory +prefs_directory="$design_directory/Prefs" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) design_name=$OPTARG;; + d ) design_directory=$OPTARG;; + p ) prefs_directory=$OPTARG;; + esac +done + # finish with other parameters +library_matchings="$design_name.hdp" +library_matchings='hds.hdp' +simulation_directory="$design_directory/Simulation" +user_prefs_directory="$prefs_directory/hds_user-linux" +team_prefs_directory="$prefs_directory/hds_team" +scratch_directory='/tmp/eda/' +synthesis_subdirectory="Board/ise" +concat_directory="$design_directory/Board/concat" + +OPTIND=1 +while getopts $command_switches options; do + case $options in + n ) ;; + d ) ;; + m ) library_matchings=$OPTARG;; + i ) simulation_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + t ) team_prefs_directory=$OPTARG;; + s ) scratch_directory=$OPTARG;; + c ) concat_directory=$OPTARG;; + y ) synthesis_subdirectory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + +design_directory=`realpath $design_directory` +library_matchings=`realpath $prefs_directory/$library_matchings` +simulation_directory=`realpath $simulation_directory` +user_prefs_directory=`realpath $user_prefs_directory` +team_prefs_directory=`realpath $team_prefs_directory` +concat_directory=`realpath $concat_directory` +mkdir -p $scratch_directory +scratch_directory=`realpath $scratch_directory` + +#================================================================================ +# Main script +# + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export MODELSIM_HOME=/usr/opt/Modelsim/modeltech/bin/ +export SYNTHESIS_HOME=/usr/opt/Xilinx/ISE_DS/ISE +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export DESIGN_NAME=$design_name +export HDS_LIBS=$library_matchings +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME=$team_prefs_directory +export SIMULATION_DIR=$simulation_directory +export SCRATCH_DIR=$scratch_directory +export CONCAT_DIR=$concat_directory +export SYNTHESIS_BASE_DIR=`realpath $design_directory/$synthesis_subdirectory` +export SYNTHESIS_WORK_DIR=$scratch_directory/$synthesis_subdirectory + +#------------------------------------------------------------------------------- +# Display info +# +if [ -n "$verbose" ] ; then + echo "Environment variables:" + echo "${INDENT}Design name is $DESIGN_NAME" + echo "${INDENT}Lib matchings file is $HDS_LIBS" + echo "${INDENT}Simulation directory is $SIMULATION_DIR" + echo "${INDENT}User prefs directory is $HDS_USER_HOME" + echo "${INDENT}Team prefs directory is $HDS_TEAM_HOME" + echo "${INDENT}Scratch directory is $SCRATCH_DIR" + echo "${INDENT}Concat directory is $CONCAT_DIR" + echo "${INDENT}HDS location is $HDS_HOME" + echo "${INDENT}Modelsim location is $MODELSIM_HOME" + echo "${INDENT}Synthesis app location is $SYNTHESIS_HOME" + echo "${INDENT}Synthesis base directory is $SYNTHESIS_BASE_DIR" + echo "${INDENT}Synthesis work directory is $SYNTHESIS_WORK_DIR" +fi + +#------------------------------------------------------------------------------- +# Copy synthesis data to scratch +# +if true; then + echo "Copying" + echo "${INDENT}$SYNTHESIS_BASE_DIR" + echo "${INDENT}-> $SYNTHESIS_WORK_DIR" +fi +if [ -e "$SYNTHESIS_BASE_DIR" ]; then + rm -Rf $SYNTHESIS_WORK_DIR + mkdir -p $SYNTHESIS_WORK_DIR + cp -pr $SYNTHESIS_BASE_DIR/* $SYNTHESIS_WORK_DIR/ +fi + +#------------------------------------------------------------------------------- +# Launch application +# +hdl_designer & + +#------------------------------------------------------------------------------- +# Exit +# +echo "" +echo "-- ${0##*/} Finished!" +echo "$SEPARATOR" +popd \ No newline at end of file diff --git a/10-PipelinedOperators/Scripts/hdlDesigner.bat b/10-PipelinedOperators/Scripts/hdlDesigner.bat new file mode 100644 index 0000000..2a612a6 --- /dev/null +++ b/10-PipelinedOperators/Scripts/hdlDesigner.bat @@ -0,0 +1,301 @@ +::============================================================================== +:: hdl_designer.bash - Starts HDL designer +:: +:start + setlocal EnableExtensions EnableDelayedExpansion + set cmd_location=%~dp0 + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +:: ----------------------------------------------------------------------------- +:: Define default environment variables +IF NOT DEFINED REQUIRE_LIBS SET "REQUIRE_LIBS=0" +IF NOT DEFINED REQUIRE_HDS SET "REQUIRE_HDS=0" +IF NOT DEFINED REQUIRE_MODELSIM SET "REQUIRE_MODELSIM=0" +IF NOT DEFINED REQUIRE_ISE SET "REQUIRE_ISE=0" +IF NOT DEFINED REQUIRE_LIBERO SET "REQUIRE_LIBERO=0" +IF NOT DEFINED REQUIRE_DIAMOND SET "REQUIRE_DIAMOND=0" +IF NOT DEFINED REQUIRE_ICECUBE2 SET "REQUIRE_ICECUBE2=0" +:: +::remove trailing backslash +if %cmd_location:~-1%==\ set design_directory=%design_directory:~0,-1% + +set design_name=%~n0 +set hpd_name=hds + +if "%ISE_VERSION%"== "" ( + set ISE_VERSION=14.7 +) +set prefs_directory="%design_directory:"=%\Prefs" +set library_matchings="%hpd_name%.hdp" +set simulation_directory="%design_directory:"=%\Simulation" +set user_prefs_directory="%prefs_directory:"=%\hds_user" +set team_prefs_directory="%prefs_directory:"=%\hds_team" +if "%SCRATCH_DIR%" == "" ( + set scratch_directory=C:\temp\eda\%username% +) else ( + set scratch_directory=%SCRATCH_DIR% +) + +set synthesis_subdirectory="" +if %REQUIRE_ISE% == 1 ( + set synthesis_subdirectory="Board\ise" +) +if %REQUIRE_LIBERO% == 1 ( + set synthesis_subdirectory="Board\libero" +) +if %REQUIRE_DIAMOND% == 1 ( + set synthesis_subdirectory="Board\diamond" +) +if %REQUIRE_ICECUBE2% == 1 ( + set synthesis_subdirectory="Board\icecube2" +) +set concat_directory="%design_directory:"=%\Board\concat" + +::------------------------------------------------------------------------------ +:: Parse command line options +:: +:parse +set usage1="Usage: hdl_designer.bat [-v] [-h]" +set usage2=" [-n designName] [-d designDirectory]" +set usage3=" [-p prefsDirectory] [-u userPrefsDirectory] [-t teamPrefsDirectory]" +set usage4=" [-s scratchDirectory] [-c concatDirectory]" +set usage5=" [-y synthesisDirectory] [-m library_matchings]" + +echo Search Commandline Parameters +:parseloop +if not "%1"=="" ( + if "%1"=="-v" ( + set VERBOSE=1 + echo %INDENT:"=%verbose enabled + shift + ) + if "%1"=="-h" ( + goto :HELP + shift + ) + if "%1"=="-n" ( + set design_name=%2 + echo %INDENT:"=%design_name=!design_name:"=! + shift & shift + ) + if "%1"=="-d" ( + set design_directory=%2 + echo %INDENT:"=%design_directory=!design_directory:"=! + shift & shift + ) + if "%1"=="-p" ( + set prefs_directory=%2 + echo %INDENT:"=%prefs_directory=!prefs_directory:"=! + shift & shift + ) + if "%1"=="-u" ( + set user_prefs_directory=%2 + echo %INDENT:"=%user_prefs_directory=%user_prefs_directory:"=% + shift & shift + ) + if "%1"=="-t" ( + set team_prefs_directory=%2 + echo %INDENT:"=%team_prefs_directory=%team_prefs_directory:"=% + shift & shift + ) + if "%1"=="-s" ( + set scratch_directory=%2 + echo %INDENT:"=%scratch_directory=%scratch_directory:"=% + shift & shift + ) + if "%1"=="-c" ( + set concat_directory=%2 + echo "%INDENT:"=%concat_directory=%concat_directory:"=% " + shift & shift + ) + if "%1"=="-y" ( + set synthesis_subdirectory=%2 + echo %INDENT:"=%synthesis_subdirectory=%synthesis_subdirectory:"=% + shift & shift + ) + if "%1"=="-m" ( + set set library_matchings="%2.hdp" + echo %INDENT:"=%library_matchings=%library_matchings:"=% + shift & shift + ) + goto :parseloop +) +echo. + +:: Setting all concurrent variables +set prefs_directory="!design_directory:"=!\Prefs" +set user_prefs_directory="!prefs_directory:"=!\hds_user" +set team_prefs_directory="!prefs_directory:"=!\hds_team" +set library_matchings=!prefs_directory:"=!\!library_matchings:"=! +set simulation_directory="!design_directory:"=!\Simulation" +set concat_directory="!design_directory:"=!\Board\concat" + +:: Getting realpath +:: TODO + +:: create scratch dir +if not exist "%scratch_directory%" ( + mkdir "%scratch_directory:"=%" +) + +::================================================================================ +:: Main script +:: +echo. +call "./searchPaths.bat" + +::------------------------------------------------------------------------------ +:: Project environment variables +:: +set DESIGN_NAME=%design_name:"=% +set HDS_LIBS=%library_matchings:"=% +set HDS_USER_HOME=%user_prefs_directory:"=% +set HDS_TEAM_HOME=%team_prefs_directory:"=% +set SIMULATION_DIR=%simulation_directory:"=% +:: Changing Slashed (Needed for Modelsim) +set SIMULATION_DIR=%SIMULATION_DIR:\=/% +set SCRATCH_DIR=%scratch_directory:"=% +set CONCAT_DIR=%concat_directory:"=% +set ISE_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ISE_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set LIBERO_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set LIBERO_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set DIAMOND_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set DIAMOND_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_BASE_DIR=%design_directory:"=%\%synthesis_subdirectory:"=% +set ICECUBE2_WORK_DIR=%scratch_directory:"=%\%DESIGN_NAME:"=%\%synthesis_subdirectory:"=% + +::------------------------------------------------------------------------------ +:: Display info +:: +if !VERBOSE! == 1 ( + echo Program Parameters + echo %INDENT:"=%DESIGN_NAME is %DESIGN_NAME:"=% + echo %INDENT:"=%HEI_LIBS_DIR is %HEI_LIBS_DIR:"=% + echo %INDENT:"=%HDS_LIBS is %HDS_LIBS:"=% + echo %INDENT:"=%SIMULATION_DIR is %SIMULATION_DIR:"=% + echo %INDENT:"=%HDS_USER_HOME is %HDS_USER_HOME:"=% + echo %INDENT:"=%HDS_TEAM_HOME is %HDS_TEAM_HOME:"=% + echo %INDENT:"=%SCRATCH_DIR is %SCRATCH_DIR:"=% + echo %INDENT:"=%CONCAT_DIR is %CONCAT_DIR:"=% + if %REQUIRE_HDS% == 1 ( + echo %INDENT:"=%HDS_HOME is %HDS_HOME:"=% + ) + if %REQUIRE_MODELSIM% == 1 ( + echo %INDENT:"=%MODELSIM_HOME is %MODELSIM_HOME:"=% + ) + if %REQUIRE_ISE% == 1 ( + echo %INDENT:"=%ISE_HOME is %ISE_HOME:"=% + echo %INDENT:"=%ISE_BASE_DIR is %ISE_BASE_DIR:"=% + echo %INDENT:"=%ISE_WORK_DIR is %ISE_WORK_DIR:"=% + ) + if %REQUIRE_LIBERO% == 1 ( + echo %INDENT:"=%LIBERO_HOME is %LIBERO_HOME:"=% + echo %INDENT:"=%LIBERO_BASE_DIR is %LIBERO_BASE_DIR:"=% + echo %INDENT:"=%LIBERO_WORK_DIR is %LIBERO_WORK_DIR:"=% + ) + if %REQUIRE_DIAMOND% == 1 ( + echo %INDENT:"=%DIAMOND_HOME is %DIAMOND_HOME:"=% + echo %INDENT:"=%DIAMOND_BASE_DIR is %DIAMOND_BASE_DIR:"=% + echo %INDENT:"=%DIAMOND_WORK_DIR is %DIAMOND_WORK_DIR:"=% + ) + if %REQUIRE_ICECUBE2% == 1 ( + echo %INDENT:"=%ICECUBE2_HOME is %ICECUBE2_HOME:"=% + echo %INDENT:"=%ICECUBE2_BASE_DIR is %ICECUBE2_BASE_DIR:"=% + echo %INDENT:"=%ICECUBE2_WORK_DIR is %ICECUBE2_WORK_DIR:"=% + ) + echo. +) + +::------------------------------------------------------------------------------ +:: Delete scratch directory +:: +echo. +call "./cleanScratch.bat" + +::------------------------------------------------------------------------------ +:: Copy synthesis data to scratch directory +:: +if %REQUIRE_ISE% == 1 ( + if exist %ISE_BASE_DIR% ( + echo %ISE_BASE_DIR:"=% + echo -> %ISE_WORK_DIR:"=% + if exist %ISE_WORK_DIR% ( + rmdir /S /Q "%ISE_WORK_DIR%" + ) + mkdir "%ISE_WORK_DIR%" + xcopy /Y "%ISE_BASE_DIR%" "%ISE_WORK_DIR%\" + ) +) + +if %REQUIRE_LIBERO% == 1 ( + if exist %LIBERO_BASE_DIR% ( + echo %LIBERO_BASE_DIR:"=% + echo -> %LIBERO_BASE_DIR:"=% + if exist %LIBERO_WORK_DIR% ( + rmdir /S /Q "%LIBERO_WORK_DIR%" + ) + mkdir "%LIBERO_WORK_DIR%" + xcopy /S /Y "%LIBERO_BASE_DIR%" "%LIBERO_WORK_DIR%\" + ) +) + +if %REQUIRE_DIAMOND% == 1 ( + if exist %DIAMOND_BASE_DIR% ( + echo %DIAMOND_BASE_DIR:"=% + echo -> %DIAMOND_BASE_DIR:"=% + if exist %DIAMOND_WORK_DIR% ( + rmdir /S /Q "%DIAMOND_WORK_DIR%" + ) + mkdir "%DIAMOND_WORK_DIR%" + xcopy /S /Y "%DIAMOND_BASE_DIR%" "%DIAMOND_WORK_DIR%\" + ) +) + +if %REQUIRE_ICECUBE2% == 1 ( + if exist %ICECUBE2_BASE_DIR% ( + echo %ICECUBE2_BASE_DIR:"=% + echo -> %ICECUBE2_BASE_DIR:"=% + if exist %ICECUBE2_WORK_DIR% ( + rmdir /S /Q "%ICECUBE2_WORK_DIR%" + ) + mkdir "%ICECUBE2_WORK_DIR%" + xcopy /S /Y "%ICECUBE2_BASE_DIR%" "%ICECUBE2_WORK_DIR%\" + ) +) + +::------------------------------------------------------------------------------ +:: Launch application +:: +echo -- Launching program +::echo %INDENT:"=%Waiting until programs finished... +::start /wait !HDS_HOME:"=!\bin\hdldesigner.exe +%windir%\system32\cmd.exe /c start !HDS_HOME!\bin\hdldesigner.exe +::echo -- Finished... YOU CAN CLOSE THIS WINDOW NOW! + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + endlocal + goto:eof + +::------------------------------------------------------------------------------ +:: Helper Functions +:: +:HELP + echo. + echo %usage1:"=% + echo %usage2:"=% + echo %usage3:"=% + echo %usage4:"=% + echo %usage5:"=% + echo.&pause&goto:eof diff --git a/10-PipelinedOperators/Scripts/searchPaths.bat b/10-PipelinedOperators/Scripts/searchPaths.bat new file mode 100644 index 0000000..9b37b1b --- /dev/null +++ b/10-PipelinedOperators/Scripts/searchPaths.bat @@ -0,0 +1,209 @@ +::============================================================================== +:: search_paths.bat - Search for Libraries and HDL Tools +:: + +:start + @echo off + set cmd_location="%~dp0" + pushd %cmd_location% + set SEPARATOR=-------------------------------------------------------------------------------- + set INDENT=" " + + echo %SEPARATOR% + echo -- %~nx0 Started! + echo. + +echo Search HEI Library +::------------------------------------------------------------------------------ +:: Search HEI library directory +:: +if !REQUIRE_LIBS! == 1 ( + if "%HEI_LIBS_DIR%" == "" ( + set HEI_LIBS_DIR=%design_directory:"=!%\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check at folder one level above project folder, as used on svn for boards libraries + set HEI_LIBS_DIR=%design_directory:"=!%\..\..\Libs + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for ET labs + set HEI_LIBS_DIR=R:\ETE\Ele1_8132\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + :: check on server, as used for SI labs + set HEI_LIBS_DIR=R:\SYND\Ele_2131\ELN\Labs\Libraries + if not exist !HEI_LIBS_DIR!\ ( + echo "ERROR: No valid libraries found: please verify your project setup." + pause&goto:end + ) + ) + ) + ) + ) + ) + if exist !HEI_LIBS_DIR!\ ( + echo %INDENT:"=%Found HEI_LIBS_DIR at !HEI_LIBS_DIR:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid HEI_LIBS_DIR found: please verify your HEI_LIBS_DIR settings. + pause&goto:eof + ) +) + + +echo Search Design Tools: HDL Designer, Modelsim, Xilinx ISE, Microsemi Libero, Lattice Diamond, Lattice IceCube2 +::------------------------------------------------------------------------------ +:: Search HDL Designer directory +:: +if !REQUIRE_HDS! == 1 ( + if "%HDS_HOME%" == "" ( + set HDS_HOME=C:\eda\MentorGraphics\HDS + if not exist !HDS_HOME!\ ( + set HDS_HOME=C:\tools\eda\HDS + if not exist !HDS_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !HDS_HOME! ( + echo %INDENT:"=%Found HDL-Designer at !HDS_HOME! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of HDL-Designer found: please verify your HDS_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Modelsim directory +:: +if !REQUIRE_MODELSIM! == 1 ( + if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\tools\eda\Modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause&goto:eof + ) + ) + ) + ) + ) + if exist !MODELSIM_HOME! ( + echo %INDENT:"=%Found ModelSim at !MODELSIM_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ModelSim found please verify your MODELSIM_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Xilinx ISE directory +:: + +if !REQUIRE_ISE! == 1 ( + if "%ISE_HOME%" == "" ( + set ISE_HOME=C:\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + set ISE_HOME=C:\tools\eda\Xilinx\!ISE_VERSION:"=!\ISE_DS\ISE + if not exist !ISE_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !ISE_HOME! ( + echo %INDENT:"=%Found ISE at !ISE_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of ISE found please verify your ISE_HOME settings. + pause&goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Microsemi Libero directory +:: +if %REQUIRE_LIBERO% == 1 ( + if "%LIBERO_HOME%" == "" ( + set LIBERO_HOME=C:\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + set LIBERO_HOME=C:\tools\eda\Microsemi\Libero + if not exist !LIBERO_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause&goto:eof + ) + ) + ) + if exist !LIBERO_HOME! ( + echo %INDENT:"=%Found Libero at !LIBERO_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Libero found please verify your LIBERO_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice Diamond directory +:: +if %REQUIRE_DIAMOND% == 1 ( + if "%DIAMOND_HOME%" == "" ( + set DIAMOND_HOME=C:\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\tools\eda\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + set DIAMOND_HOME=C:\lscc\diamond\3.12 + if not exist !DIAMOND_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice Diamond found - please verify your DIAMOND_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !DIAMOND_HOME! ( + echo %INDENT:"=%Found Diamond at !DIAMOND_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of Diamond found - please verify your DIAMOND_HOME settings. + pause + goto:eof + ) +) + +::------------------------------------------------------------------------------ +:: Search Lattice IceCube2 directory +:: +if %REQUIRE_ICECUBE2% == 1 ( + if "%ICECUBE2_HOME%" == "" ( + set ICECUBE2_HOME=C:\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\tools\eda\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + set ICECUBE2_HOME=C:\lscc\iCEcube2.2020.12 + if not exist !ICECUBE2_HOME!\ ( + echo %INDENT:"=%ERROR: No valid installation of Lattice IceCube2 found - please verify your ICECUBE2_HOME settings. + pause&goto:eof + ) + ) + ) + ) + if exist !ICECUBE2_HOME! ( + echo %INDENT:"=%Found IceCube2 at !ICECUBE2_HOME:"=! + ) else ( + echo %INDENT:"=%ERROR: No valid installation of IceCube2 found - please verify your ICECUBE2_HOME settings. + pause + goto:eof + ) +) + +:end + echo. + echo -- %~nx0 Finished! + echo %SEPARATOR% + echo. && echo. + popd + goto:eof \ No newline at end of file diff --git a/10-PipelinedOperators/Scripts/trimLibs.pl b/10-PipelinedOperators/Scripts/trimLibs.pl new file mode 100644 index 0000000..76d8d36 --- /dev/null +++ b/10-PipelinedOperators/Scripts/trimLibs.pl @@ -0,0 +1,170 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# trimLibs +# Comment regular libraries in an concatenated file +# Help Parameter : +# Parameter : trimlibs.pl +# ------------------------------------------------------------------------------ +# Authors: +# cof: [François Corthay](francois.corthay@hevs.ch) +# guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +# zas: [Silvan Zahno](silvan.zahno@hevs.ch) +# gal: [Laurent Gauch] +# ama: [Amand Axel](axel.amand@hevs.ch) +# ------------------------------------------------------------------------------ +# Changelog: +# 2023.05.16 : ama +# * Add: ice40 libs support +# 2023.02.01 : ama +# * Add: ECP5U libs support +# 2019.08.23 : cof +# * Comment "omment "FOR xxxx : yyy USE ENTITY zzz;"" instead all "For All ... work" lines +# * Seen problems in ELN_Kart +# 2019.06.11 : zas +# * Comment "For All .... work."" instead all "For All" lines +# * Allow Outputfilename as Env var or as Script parameter +# 2015-08-25 : guo +# * added unisim to the list of excluded libraries +# 2015-05-08 : guo +# * added verbosity debug +# * changed this header +# * minor comment modifications +# 2013-08-13 : zas guo +# Handle error if environment variable not found, character'pos('$') -> ') +# was found as env var, added exception +# 2013-06-13 : cof zas guo +# Remove comments from testline +# 2013-01-09 : cof -- +# * Bugfix: no carriage return on commented "use" statements +# * Bugfix: more precise targeting of "library" statement +# * Bugfix: "Library" test after "use" test +# 2012-04-27 : zas +# * Bugfix: on feature added in version 2011-06-10 +# 2012-02-02 : zas +# * Write the output into a new file with the name defined in the +# * $DESIGN_NAME variable +# 2012-01-23 : zas +# * Replaces $env_var_name by the value of the found environmemnt variable. +# * Mostly used to replace $SIMULATION_DIR for initialise bram's from a file +# * placed in the Simulation Directory +# 2011-06-10 : zas +# Replaces +# library xxx;use xxx.yyy.all; +# with +# --library xxx; +# use work.yyy.all; +# 2005...2011 : cof +# Improvements +# 2005-01-29 : gal +# initlial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; +$hdlInFileSpec = $ARGV[0]; +if (defined $ARGV[1]) { + $hdlOutFileSpec = $ARGV[1]; +} +else { + $hdlOutFileSpec = 'trimmed.vhd'; +} + +$verbose = 1; +$debug = 0; + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $hdlOutFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Trimming library declarations from $hdlInFileSpec to $hdlOutFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(HDLFile, $hdlInFileSpec) || die "couldn't open $HDLFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + + # remove all comment for the test + my $testline = $line; + $testline =~ s/--.*//; + + # Replace 'use xxx.yyy' with 'use work.yyy', except if xxx is ieee or std or unisim or ecp5u or ice40 + if ($testline =~ m/use\s.*\.all\s*;/i) { + if ( not($testline =~ m/\bieee\./i) and + not($testline =~ m/\bstd\./i) and + not($testline =~ m/\bunisim\./i) and + not($testline =~ m/\becp5u\./i) and + not($testline =~ m/ice40.*\./i)) { + # if there is any char before "use" except \s, insert new line \n + if ( ($testline =~ m/[^\s]\s*use/i) ) { + $line =~ s/use\s+.*?\./\nuse work./i; + if ($debug == 1) { + print "TEST0099: ", $testline, "\n" + } + } + else { + $line =~ s/use\s+.*?\./use work./i; + if ($debug == 1) { + print "TEST0105: ", $testline, "\n" + } + } + } + } + + # Comment libraries which aren't ieee or std or unisim or ecp5u or ice40 + if (($testline =~ m/\slibrary\s+/i) or ($testline =~ m/\Alibrary\s+/i)) { + if ( not($testline =~ m/ieee/i) and + not($testline =~ m/std/i) and + not($testline =~ m/unisim/i) and + not($testline =~ m/ecp5u/i) and + not($testline =~ m/ice40/i)) { + $line = '-- ' . $line; + } + } + + # Comment "FOR xxxx : yyy USE ENTITY zzz; + if ($line =~ m/for\s+.+:.+\s+use\s+entity/i) { + $line = '-- ' . $line; + } + + # Search for $Env_Var_Names and replace them by the value of the env_var + if ($testline =~ m/(\$[^\s\/.'"\\]+)/i) { + $envvar = $1; + $envvar =~ s/^.//; + eval { + $line =~ s/\$$envvar/$ENV{$envvar}/; + }; + if ($@) { + print ("WARNING: Environment Variable not found: $envvar \n") + } + + } + + print tempFile ("$line\n"); +} + +close(tempFile); +close(HDLFile); + +#------------------------------------------------------------------------------- +# delete original file and rename temporary file +# +unlink($hdlOutFileSpec); +rename($tempFileSpec, $hdlOutFileSpec); + +if ($verbose == 1) { + print "$separator\n"; +} + +#if ($verbose == 1) { +# print $indent, "Hit any to continue"; +# $dummy = ; +#} diff --git a/10-PipelinedOperators/Scripts/update_ise.pl b/10-PipelinedOperators/Scripts/update_ise.pl new file mode 100644 index 0000000..1ce5756 --- /dev/null +++ b/10-PipelinedOperators/Scripts/update_ise.pl @@ -0,0 +1,91 @@ +#!/usr/bin/perl +# ------------------------------------------------------------------------------ +# update_ise +# replace ucf and vhd filelocation and name in the Xilinx xise project file +# Help Parameter : +# Parameter : update_ise.pl +# ------------------------------------------------------------------------------ +# Changelog: +# 2019-06-12 : zas +# * All parameters given with agruments instead of env variables +# 2015-05-26 : guo +# * update to environment from HELS v.15.0526 +# 2012-05-27 : cof +# * Initial release +# ------------------------------------------------------------------------------ + +$separator = '-' x 79; +$indent = ' ' x 2; + +$iseFileSpec = $ARGV[0]; +$vhdlFileSpec = $ARGV[1]; +$ucfFileSpec = $ARGV[2]; + +$verbose = 1; + +if ($verbose == 1) { + print "Script Parameters:\n"; + print " * iseFileSpec: $iseFileSpec\n"; + print " * vhdlFileSpec: $vhdlFileSpec\n"; + print " * ucfFileSpec: $ucfFileSpec\n"; +} + + +#------------------------------------------------------------------------------- +# program I/O files +# +$tempFileSpec = $iseFileSpec . '.tmp'; + +if ($verbose == 1) { + print "\n$separator\n"; + print "Updating file specifications in $iseFileSpec\n"; + print $indent, "temporary file spec: $tempFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# read original file, edit and save to temporary file +# +my $line; + +open(ISEFile, $iseFileSpec) || die "couldn't open $iseFileSpec!"; +open(tempFile, ">$tempFileSpec"); +while (chop($line = )) { + # replace VHDL files + if ($line =~ m/FILE_VHDL/i) { + $line =~ s/ '0'); + for index in hSel'range loop + mask := to_unsigned(ahbMemoryLocation(index).addressMask, mask'length); + if (hAddr and mask) = ahbMemoryLocation(index).baseAddress then + hSel(index) <= '1'; + end if; + end loop; + end process decodeAddress; + +END ARCHITECTURE RTL; diff --git a/Libs/AhbLite/hdl/ahbLite_pkg.vhd b/Libs/AhbLite/hdl/ahbLite_pkg.vhd new file mode 100644 index 0000000..363bdb8 --- /dev/null +++ b/Libs/AhbLite/hdl/ahbLite_pkg.vhd @@ -0,0 +1,59 @@ +LIBRARY ieee; + USE ieee.std_logic_1164.all; + +PACKAGE ahbLite IS + ------------------------------------------------------------------------------ + -- bus components sizes + constant ahbAddressBitNb : positive := 16; + constant ahbDataBitNb : positive := 16; + constant ahbSlaveNb : positive := 16; + + constant ahbTransBitNb : positive := 2; + constant ahbSizeBitNb : positive := 1; + constant ahbBurstBitNb : positive := 3; + constant ahbProtBitNb : positive := 4; + + ------------------------------------------------------------------------------ + -- bus data vector type + subtype ahbDataType is std_logic_vector(ahbDataBitNb-1 downto 0); + type ahbDataVector is array(1 to ahbSlaveNb) of ahbDataType; + + ------------------------------------------------------------------------------ + -- address decoder + type ahbMemoryLocationType is + record + baseAddress: natural; + addressMask: natural; + end record; + type ahbMemoryLocationVector is array(1 to ahbSlaveNb) of ahbMemoryLocationType; + + ------------------------------------------------------------------------------ + -- bus signals + subtype transferType is std_ulogic_vector(ahbTransBitNb-1 downto 0); + constant transIdle : transferType := "00"; + constant transBusy : transferType := "01"; + constant transNonSeq: transferType := "10"; + constant transSeq : transferType := "11"; + + subtype transferSizeType is std_ulogic_vector(ahbSizeBitNb-1 downto 0); + constant size8 : transferSizeType := "0"; + constant size16 : transferSizeType := "1"; + + subtype burstType is std_ulogic_vector(ahbBurstBitNb-1 downto 0); + constant burstSingle : burstType := "000"; + constant burstIncr : burstType := "001"; + constant burstWrap4 : burstType := "010"; + constant burstIncr4 : burstType := "011"; + constant burstWrap8 : burstType := "100"; + constant burstIncr8 : burstType := "101"; + constant burstWrap16 : burstType := "110"; + constant burstIncr16 : burstType := "111"; + + subtype protectionType is std_ulogic_vector(ahbProtBitNb-1 downto 0); + constant protDefault : protectionType := "0011"; + + ------------------------------------------------------------------------------ + -- log2 + function addressBitNb (addressNb : natural) return natural; + +END ahbLite; diff --git a/Libs/AhbLite/hdl/ahbLite_pkg_body.vhd b/Libs/AhbLite/hdl/ahbLite_pkg_body.vhd new file mode 100644 index 0000000..ecba504 --- /dev/null +++ b/Libs/AhbLite/hdl/ahbLite_pkg_body.vhd @@ -0,0 +1,15 @@ +PACKAGE BODY ahbLite IS + + function addressBitNb (addressNb : natural) return natural is + variable powerOfTwo, bitNb : natural; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo <= addressNb loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end addressBitNb; + +END ahbLite; diff --git a/Libs/AhbLite/hdl/ahbMasterInterface_RTL.vhd b/Libs/AhbLite/hdl/ahbMasterInterface_RTL.vhd new file mode 100644 index 0000000..4658305 --- /dev/null +++ b/Libs/AhbLite/hdl/ahbMasterInterface_RTL.vhd @@ -0,0 +1,70 @@ +ARCHITECTURE RTL OF ahbMasterInterface IS + + signal addressReg: unsigned(pAddress'range); + signal newAddress: std_ulogic; + signal writeReg: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + hReset_n <= not reset; + hClk <= clock; + + ------------------------------------------------------------------------------ + -- address and controls + newAddress <= pReadStrobe or pWriteStrobe; + + storeAddress: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + elsif rising_edge(clock) then + if newAddress = '1' then + addressReg <= pAddress; + end if; + end if; + end process storeAddress; + + hAddr <= pAddress when newAddress = '1' + else addressReg; + + storeWrite: process(reset, clock) + begin + if reset = '1' then + writeReg <= '0'; + elsif rising_edge(clock) then + if newAddress = '1' then + writeReg <= pWriteStrobe; + end if; + end if; + end process storeWrite; + + hWrite <= pWriteStrobe when newAddress = '1' + else writeReg; + + hTrans <= transNonSeq when newAddress = '1' + else transIdle; + + hSize <= size16; + hBurst <= burstSingle; + hProt <= protDefault; + hMastLock <= '0'; + + ------------------------------------------------------------------------------ + -- data out + delayData: process(reset, clock) + begin + if reset = '1' then + hWData <= (others => '0'); + elsif rising_edge(clock) then + if pWriteStrobe = '1' then + hWData <= pDataOut; + end if; + end if; + end process delayData; + + ------------------------------------------------------------------------------ + -- data in + pDataIn <= hRData; + +END ARCHITECTURE RTL; diff --git a/Libs/AhbLite/hdl/ahbMultiplexor_RTL.vhd b/Libs/AhbLite/hdl/ahbMultiplexor_RTL.vhd new file mode 100644 index 0000000..75eeec5 --- /dev/null +++ b/Libs/AhbLite/hdl/ahbMultiplexor_RTL.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE RTL OF ahbMultiplexor IS +BEGIN + + multiplexData: process(hSel, hRDataV, hReadyV, hRespV) + begin + hRData <= (others => '0'); + hReady <= '1'; + hResp <= '0'; + for index in hSel'range loop + if hSel(index) = '1' then + hRData <= std_ulogic_vector(hRDataV(index)); + hReady <= hReadyV(index); + hResp <= hRespV(index); + end if; + end loop; + end process multiplexData; + +END ARCHITECTURE RTL; diff --git a/Libs/AhbLite/hdl/ahbMuxConnector_RTL.vhd b/Libs/AhbLite/hdl/ahbMuxConnector_RTL.vhd new file mode 100644 index 0000000..2436719 --- /dev/null +++ b/Libs/AhbLite/hdl/ahbMuxConnector_RTL.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE RTL OF ahbMuxConnector IS +BEGIN + + hSel <= hSelV(index); + + hRDataV(index) <= std_logic_vector(hRData); + hReadyV(index) <= hReady; + hRespV(index) <= hResp; + + hRDataV <= (others => (others => 'Z')); + hReadyV <= (others => 'Z'); + hRespV <= (others => 'Z'); + +END ARCHITECTURE RTL; diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbDecoder_RTL.vhd._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbDecoder_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbDecoder_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbLite_pkg.vhd._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbLite_pkg.vhd._fpf new file mode 100644 index 0000000..19d6635 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbLite_pkg.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2002 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbLite_pkg_body.vhd._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbLite_pkg_body.vhd._fpf new file mode 100644 index 0000000..19d6635 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbLite_pkg_body.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2002 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbMasterInterface_RTL.vhd._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbMasterInterface_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbMasterInterface_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbMultiplexor_RTL.vhd._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbMultiplexor_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbMultiplexor_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbMuxConnector_RTL.vhd._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbMuxConnector_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbMuxConnector_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbdecoder_entity.vhg._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbdecoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbdecoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbmasterinterface_entity.vhg._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbmasterinterface_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbmasterinterface_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbmultiplexor_entity.vhg._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbmultiplexor_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbmultiplexor_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/.hdlsidedata/_ahbmuxconnector_entity.vhg._fpf b/Libs/AhbLite/hds/.hdlsidedata/_ahbmuxconnector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/AhbLite/hds/.hdlsidedata/_ahbmuxconnector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite/hds/_ahbdecoder._epf b/Libs/AhbLite/hds/_ahbdecoder._epf new file mode 100644 index 0000000..0281ad5 --- /dev/null +++ b/Libs/AhbLite/hds/_ahbdecoder._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom ahbDecoder_RTL.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/AhbLite/hds/_ahbmasterinterface._epf b/Libs/AhbLite/hds/_ahbmasterinterface._epf new file mode 100644 index 0000000..55f5c53 --- /dev/null +++ b/Libs/AhbLite/hds/_ahbmasterinterface._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom ahbMasterInterface_RTL.vhd diff --git a/Libs/AhbLite/hds/_ahbmultiplexor._epf b/Libs/AhbLite/hds/_ahbmultiplexor._epf new file mode 100644 index 0000000..518a2f8 --- /dev/null +++ b/Libs/AhbLite/hds/_ahbmultiplexor._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom ahbMultiplexor_RTL.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/AhbLite/hds/_ahbmuxconnector._epf b/Libs/AhbLite/hds/_ahbmuxconnector._epf new file mode 100644 index 0000000..fbb037a --- /dev/null +++ b/Libs/AhbLite/hds/_ahbmuxconnector._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom ahbMuxConnector_RTL.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/AhbLite/hds/ahb@decoder/symbol.sb b/Libs/AhbLite/hds/ahb@decoder/symbol.sb new file mode 100644 index 0000000..53abeba --- /dev/null +++ b/Libs/AhbLite/hds/ahb@decoder/symbol.sb @@ -0,0 +1,1448 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2064,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 320,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 1 +suid 2051,0 +) +) +uid 2524,0 +) +*15 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_ulogic_vector" +b "(1 to ahbSlaveNb)" +o 2 +suid 2053,0 +) +) +uid 2526,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 333,0 +optionalChildren [ +*16 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *17 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OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 11 +suid 2051,0 +) +) +) +*100 (CptPort +uid 2464,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2465,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,17625,63750,18375" +) +tg (CPTG +uid 2466,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2467,0 +va (VaSet +font "Verdana,12,0" +) +xt "56100,17300,62000,18700" +st "hWData" +ju 2 +blo "62000,18500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2468,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,25400,37500,26200" +st "hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 19 +suid 2053,0 +) +) +) +*101 (CptPort +uid 2469,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2579,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,31625,63750,32375" +) +tg (CPTG +uid 2471,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2472,0 +va (VaSet +font "Verdana,12,0" +) +xt "56600,31300,62000,32700" +st "hRData" +ju 2 +blo "62000,32500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2473,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,12600,37500,13400" +st "hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 4 +suid 2054,0 +) +) +) +*102 (CptPort +uid 2474,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2580,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,21625,63750,22375" +) +tg (CPTG +uid 2476,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2477,0 +va (VaSet +font "Verdana,12,0" +) +xt "57000,21300,62000,22700" +st "hWrite" +ju 2 +blo "62000,22500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2478,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,26200,21000,27000" +st "hWrite : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hWrite" +t "std_uLogic" +o 20 +suid 2055,0 +) +) +) +*103 (CptPort +uid 2479,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2480,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,23625,63750,24375" +) +tg (CPTG +uid 2481,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2482,0 +va (VaSet +font "Verdana,12,0" +) +xt "57800,23300,62000,24700" +st "hSize" +ju 2 +blo "62000,24500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2483,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23800,37500,24600" +st "hSize : OUT std_ulogic_vector (ahbSizeBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSize" +t "std_ulogic_vector" +b "(ahbSizeBitNb-1 DOWNTO 0)" +o 17 +suid 2056,0 +) +) +) +*104 (CptPort +uid 2484,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2485,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,25625,63750,26375" +) +tg (CPTG +uid 2486,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2487,0 +va (VaSet +font "Verdana,12,0" +) +xt "57100,25300,62000,26700" +st "hBurst" +ju 2 +blo "62000,26500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2488,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,19800,38000,20600" +st "hBurst : OUT std_ulogic_vector (ahbBurstBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hBurst" +t "std_ulogic_vector" +b "(ahbBurstBitNb-1 DOWNTO 0)" +o 12 +suid 2057,0 +) +) +) +*105 (CptPort +uid 2489,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2490,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,27625,63750,28375" +) +tg (CPTG +uid 2491,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2492,0 +va (VaSet +font "Verdana,12,0" +) +xt "57800,27300,62000,28700" +st "hProt" +ju 2 +blo "62000,28500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2493,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22200,37500,23000" +st "hProt : OUT std_ulogic_vector (ahbProtBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hProt" +t "std_ulogic_vector" +b "(ahbProtBitNb-1 DOWNTO 0)" +o 15 +suid 2058,0 +) +) +) +*106 (CptPort +uid 2494,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2495,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,19625,63750,20375" +) +tg (CPTG +uid 2496,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2497,0 +va (VaSet +font "Verdana,12,0" +) +xt "56900,19300,62000,20700" +st "hTrans" +ju 2 +blo "62000,20500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2498,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,24600,38000,25400" +st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 18 +suid 2059,0 +) +) +) +*107 (CptPort +uid 2499,0 +ps "OnEdgeStrategy" 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2508,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,13400,21000,14200" +st "hReady : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 5 +suid 2061,0 +) +) +) +*109 (CptPort +uid 2509,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2510,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,35625,63750,36375" +) +tg (CPTG +uid 2511,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2512,0 +va (VaSet +font "Verdana,12,0" +) +xt "57300,35300,62000,36700" +st "hResp" +ju 2 +blo "62000,36500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2513,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14200,21000,15000" +st "hResp : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 6 +suid 2062,0 +) +) +) +*110 (CptPort +uid 2514,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2515,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,37625,63750,38375" +) +tg (CPTG +uid 2516,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2517,0 +va (VaSet +font "Verdana,12,0" +) +xt "58500,37300,62000,38700" +st "hClk" +ju 2 +blo "62000,38500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2518,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,20600,21000,21400" +st "hClk : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hClk" +t "std_uLogic" +o 13 +suid 2063,0 +) +) +) +*111 (CptPort +uid 2519,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2520,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "63000,39625,63750,40375" +) +tg (CPTG +uid 2521,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2522,0 +va (VaSet +font "Verdana,12,0" +) +xt "55200,39300,62000,40700" +st "hReset_n" +ju 2 +blo "62000,40500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2523,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,23000,21000,23800" +st "hReset_n : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl 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138,0 +shape (Rectangle +uid 139,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,65000,78000,66000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 140,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,65000,71200,66000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*115 (CommentText +uid 141,0 +shape (Rectangle +uid 142,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "78000,61000,82000,62000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 143,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "78200,61000,81200,62000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*116 (CommentText +uid 144,0 +shape (Rectangle +uid 145,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,63000,78000,64000" +) +oxt "18000,68000,35000,69000" +text (MLText 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+ USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all;" +tm "PackageList" +) +] +) +windowSize "117,42,1419,895" +viewArea "-1100,-1100,74710,50630" +cachedDiagramExtent "0,0,73000,49000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 48 +yMargin 48 +paperWidth 761 +paperHeight 1077 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "A4" +windowsPaperName "A4" +windowsPaperType 9 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Courier New,9,0" +) +xt "750,1000,4250,2200" +st "Panel0" +blo "750,1900" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,47000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "29100,14700,32600,15700" +st "" +blo "29100,15500" +) +second (Text +va (VaSet +) +xt "29100,15700,31700,16700" +st "" +blo "29100,16500" +) +) +gi *89 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *90 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,10,1" +) +xt "0,9400,8600,10600" +st "Declarations" +blo "0,10400" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,10,1" +) +xt "0,10600,4200,11800" +st "Ports:" +blo "0,11600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,10,1" +) +xt "0,17400,3700,18600" +st "User:" +blo "0,18400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,10,1" +) +xt "0,9400,9400,10600" +st "Internal User:" +blo "0,10400" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18600,2000,18600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,9400,0,9400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 2790,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/Libs/AhbLite/hds/ahb@mux@connector/symbol.sb b/Libs/AhbLite/hds/ahb@mux@connector/symbol.sb new file mode 100644 index 0000000..6180f27 --- /dev/null +++ b/Libs/AhbLite/hds/ahb@mux@connector/symbol.sb @@ -0,0 +1,1835 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2068,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 320,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "hSelV" +t "std_ulogic_vector" +b "( 1 TO ahbSlaveNb )" +o 5 +suid 2051,0 +) +) +uid 2524,0 +) +*15 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hRDataV" +t "ahbDataVector" +o 1 +suid 2054,0 +) +) +uid 2528,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +suid 2061,0 +) +) +uid 2542,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 3 +suid 2062,0 +) +) +uid 2544,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +suid 2065,0 +) +) +uid 2643,0 +) +*19 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 2 +suid 2066,0 +) +) +uid 2645,0 +) +*20 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 4 +suid 2067,0 +) +) +uid 2647,0 +) +*21 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 8 +suid 2068,0 +) +) +uid 2796,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 333,0 +optionalChildren [ +*22 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *23 (MRCItem +litem &1 +pos 8 +dimension 20 +) +uid 254,0 +optionalChildren [ +*24 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 257,0 +) +*25 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 259,0 +) +*26 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 261,0 +) +*27 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 2525,0 +) +*28 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 2529,0 +) +*29 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 2543,0 +) +*30 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 2545,0 +) +*31 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 2644,0 +) +*32 (MRCItem +litem &19 +pos 5 +dimension 20 +uid 2646,0 +) +*33 (MRCItem +litem &20 +pos 6 +dimension 20 +uid 2648,0 +) +*34 (MRCItem +litem &21 +pos 7 +dimension 20 +uid 2797,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 255,0 +optionalChildren [ +*35 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 263,0 +) +*36 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 267,0 +) +*37 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 269,0 +) +*38 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 271,0 +) +*39 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 273,0 +) +*40 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 275,0 +) +*41 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 277,0 +) +*42 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 279,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 253,0 +vaOverrides [ +] +) +] +) +uid 319,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *43 (LEmptyRow +) +uid 335,0 +optionalChildren [ +*44 (RefLabelRowHdr +) +*45 (TitleRowHdr +) +*46 (FilterRowHdr +) +*47 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*48 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*49 (GroupColHdr +tm "GroupColHdrMgr" +) +*50 (NameColHdr +tm "GenericNameColHdrMgr" +) +*51 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*52 (InitColHdr +tm "GenericValueColHdrMgr" +) +*53 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*54 (EolColHdr +tm "GenericEolColHdrMgr" +) +*55 (LogGeneric +generic (GiElement +name "index" +type "positive" +value "1" +) +uid 2798,0 +) +] +) +pdm (PhysicalDM +uid 336,0 +optionalChildren [ +*56 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *57 (MRCItem +litem &43 +pos 1 +dimension 20 +) +uid 293,0 +optionalChildren [ +*58 (MRCItem +litem &44 +pos 0 +dimension 20 +uid 296,0 +) +*59 (MRCItem +litem &45 +pos 1 +dimension 23 +uid 298,0 +) +*60 (MRCItem +litem &46 +pos 2 +hidden 1 +dimension 20 +uid 300,0 +) +*61 (MRCItem +litem &55 +pos 0 +dimension 20 +uid 2799,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 294,0 +optionalChildren [ +*62 (MRCItem +litem &47 +pos 0 +dimension 20 +uid 302,0 +) +*63 (MRCItem +litem &49 +pos 1 +dimension 50 +uid 306,0 +) +*64 (MRCItem +litem &50 +pos 2 +dimension 199 +uid 308,0 +) +*65 (MRCItem +litem &51 +pos 3 +dimension 100 +uid 310,0 +) +*66 (MRCItem +litem &52 +pos 4 +dimension 50 +uid 312,0 +) +*67 (MRCItem +litem &53 +pos 5 +dimension 50 +uid 314,0 +) +*68 (MRCItem +litem &54 +pos 6 +dimension 309 +uid 316,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 292,0 +vaOverrides [ +] +) +] +) +uid 334,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "D:\\Labs\\Cansat\\..\\Libs\\AhbLite\\hdl" +) +(vvPair +variable "HDSDir" +value "D:\\Labs\\Cansat\\..\\Libs\\AhbLite\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "D:\\Labs\\Cansat\\..\\Libs\\AhbLite\\hds\\ahb@mux@connector\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "D:\\Labs\\Cansat\\..\\Libs\\AhbLite\\hds\\ahb@mux@connector\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "D:\\Labs\\Cansat\\..\\Libs\\AhbLite\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "asm_file" +value "nanoTest.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "D:\\Labs\\Cansat\\..\\Libs\\AhbLite\\hds\\ahb@mux@connector" +) +(vvPair +variable "d_logical" +value "D:\\Labs\\Cansat\\..\\Libs\\AhbLite\\hds\\ahbMuxConnector" +) +(vvPair +variable "date" +value "07.06.2013" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "07" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "ahbMuxConnector" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE3673" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "AhbLite" +) +(vvPair +variable "library_downstream_Concatenation" +value "U:/ELN_Board/Synthesis" +) +(vvPair +variable "library_downstream_Generic_1_file" +value "U:\\ELN_Board\\Synthesis" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value 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+okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/Libs/AhbLite_test/doc/AMBA_AHB-Lite_spec.pdf b/Libs/AhbLite_test/doc/AMBA_AHB-Lite_spec.pdf new file mode 100644 index 0000000..99e720c Binary files /dev/null and b/Libs/AhbLite_test/doc/AMBA_AHB-Lite_spec.pdf differ diff --git a/Libs/AhbLite_test/hdl/ahbLite_tester_test.vhd b/Libs/AhbLite_test/hdl/ahbLite_tester_test.vhd new file mode 100644 index 0000000..4bf43cd --- /dev/null +++ b/Libs/AhbLite_test/hdl/ahbLite_tester_test.vhd @@ -0,0 +1,145 @@ +ARCHITECTURE test OF ahbLite_tester IS + -- reset and clock + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + -- register access + signal registerAddress: natural; + signal registerData: integer; + signal registerWrite: std_uLogic; + signal registerRead: std_uLogic; + -- AHB lite registers + signal addressReg: unsigned(hAddr'range); + signal writeReg: std_uLogic; + signal selPeriph1Reg: std_uLogic; + signal selPeriph2Reg: std_uLogic; + signal hSel: std_uLogic; + constant registerNb: positive := 2*periph2BaseAddress; + subtype registerType is std_uLogic_vector(hWdata'range); + type registerArrayType is array (registerNb-1 downto 0) of registerType; + signal registerArray: registerArrayType; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 4*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9.0/10.0; + + + ------------------------------------------------------------------------------ + -- test sequence + testSequence: process + begin + registerAddress <= 0; + registerData <= 0; + registerWrite <= '0'; + registerRead <= '0'; + wait for 100 ns; + -- write periph1 register 0 + registerAddress <= 0; + registerData <= 1; + registerWrite <= '1', '0' after clockPeriod; + wait for 8*clockPeriod; + -- write periph1 register 1 + registerAddress <= 1; + registerData <= 2; + registerWrite <= '1', '0' after clockPeriod; + wait for 8*clockPeriod; + -- write periph2 register 0 + registerAddress <= periph2BaseAddress; + registerData <= periph2BaseAddress + 1; + registerWrite <= '1', '0' after clockPeriod; + wait for 2*clockPeriod; + -- write periph2 register 1 + registerAddress <= periph2BaseAddress + 1; + registerData <= periph2BaseAddress + 2; + registerWrite <= '1', '0' after clockPeriod; + wait for 8*clockPeriod; + -- read periph1 register 0 + registerAddress <= 0; + registerRead <= '1', '0' after clockPeriod; + wait for 8*clockPeriod; + -- read periph2 register 0 + registerAddress <= periph2BaseAddress; + registerRead <= '1', '0' after clockPeriod; + wait for 8*clockPeriod; + + wait; + end process testSequence; + + --============================================================================ + -- microprocessor bus access + busAccess: process + variable writeAccess: boolean; + begin + upAddress <= (others => '-'); + upDataOut <= (others => '-'); + upReadStrobe <= '0'; + upWriteStrobe <= '0'; + -- wait for transaction + wait on registerWrite, registerRead; + if not(hReset_n) = '0' then + writeAccess := false; + if rising_edge(registerWrite) then + writeAccess := true; + end if; + -- single-cycle bus access + wait until rising_edge(clock_int); + upAddress <= to_unsigned(registerAddress, hAddr'length); + if writeAccess then + upWriteStrobe <= '1'; + upDataOut <= std_uLogic_vector(to_signed(registerData, upDataOut'length)); + else + upReadStrobe <= '1'; + end if; + wait until rising_edge(clock_int); + end if; + end process; + + --============================================================================ + -- AHB bus access + hSel <= hSelPeriph1 or hSelPeriph2; + -- address and controls + storeControls: process(hReset_n, hClk) + begin + if not(hReset_n) = '1' then + addressReg <= (others => '0'); + writeReg <= '0'; + selPeriph1Reg <= '0'; + selPeriph2Reg <= '0'; + elsif rising_edge(hClk) then + writeReg <= '0'; + if (hSel = '1') and (hTrans = transNonSeq) then + addressReg <= hAddr; + writeReg <= hWrite; + selPeriph1Reg <= hSelPeriph1; + selPeriph2Reg <= hSelPeriph2; + end if; + end if; + end process storeControls; + -- write registers + storeRegisters: process(hReset_n, hClk) + begin + if not(hReset_n) = '1' then + registerArray <= (others => (others => '0')); + elsif rising_edge(hClk) then + if writeReg = '1' then + registerArray(to_integer(addressReg)) <= hWData; + end if; + end if; + end process storeRegisters; + -- read egisters + hRDataPeriph1 <= registerArray(to_integer(addressReg)) + when addressReg < periph2BaseAddress + else (others => '-'); + hReadyPeriph1 <= '1'; -- no wait state + hRespPeriph1 <= '0'; -- data OK + + hRDataPeriph2 <= registerArray(to_integer(addressReg)) + when addressReg >= periph2BaseAddress + else (others => '-'); + hReadyPeriph2 <= '1'; -- no wait state + hRespPeriph2 <= '0'; -- data OK + +END ARCHITECTURE test; diff --git a/Libs/AhbLite_test/hds/.hdlsidedata/_ahbLite_tester_test.vhd._fpf b/Libs/AhbLite_test/hds/.hdlsidedata/_ahbLite_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/AhbLite_test/hds/.hdlsidedata/_ahbLite_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/AhbLite_test/hds/_ahblite_tb._epf b/Libs/AhbLite_test/hds/_ahblite_tb._epf new file mode 100644 index 0000000..afa58fb --- /dev/null +++ b/Libs/AhbLite_test/hds/_ahblite_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom ahb@lite_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/AhbLite_test/hds/_ahblite_tester._epf b/Libs/AhbLite_test/hds/_ahblite_tester._epf new file mode 100644 index 0000000..27cb4f7 --- /dev/null +++ b/Libs/AhbLite_test/hds/_ahblite_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom ahbLite_tester_test.vhd diff --git a/Libs/AhbLite_test/hds/ahb@lite_tb/struct.bd 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"AhbLite" +blo "61100,68700" +tm "BdLibraryNameMgr" +) +*34 (Text +uid 12498,0 +va (VaSet +font "Verdana,10,0" +) +xt "61100,68900,73300,70100" +st "ahbMasterInterface" +blo "61100,69900" +tm "CptNameMgr" +) +*35 (Text +uid 12499,0 +va (VaSet +font "Verdana,10,0" +) +xt "61100,70100,65000,71300" +st "I_mst" +blo "61100,71100" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 12500,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 12501,0 +text (MLText +uid 12502,0 +va (VaSet +font "Courier New,8,0" +) +xt "61000,70400,61000,70400" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 13469,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "61250,66250,62750,67750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*36 (SaComponent +uid 12583,0 +optionalChildren [ +*37 (CptPort +uid 12592,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 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"100250,83625,101000,84375" +) +tg (CPTG +uid 12602,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12603,0 +va (VaSet +) +xt "102000,83400,106400,84600" +st "hReady" +blo "102000,84400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +) +) +) +*40 (CptPort +uid 12604,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12605,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "100250,85625,101000,86375" +) +tg (CPTG +uid 12606,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12607,0 +va (VaSet +) +xt "102000,85400,105800,86600" +st "hResp" +blo "102000,86400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hResp" +t "std_uLogic" +o 3 +) +) +) +*41 (CptPort +uid 12608,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12609,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "100250,81625,101000,82375" +) +tg (CPTG +uid 12610,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12611,0 +va (VaSet +) +xt "102000,81400,106400,82600" +st "hRData" +blo "102000,82400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +) +) +) +*42 (CptPort +uid 12612,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12613,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,83625,117750,84375" +) +tg (CPTG +uid 12614,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12615,0 +va (VaSet +) +xt "110800,83400,116000,84600" +st "hReadyV" +ju 2 +blo "116000,84400" +) +) +thePort (LogicalPort +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 2 +) +) +) +*43 (CptPort +uid 12616,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12617,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,85625,117750,86375" +) +tg (CPTG +uid 12618,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12619,0 +va (VaSet +) +xt "111400,85400,116000,86600" +st "hRespV" +ju 2 +blo "116000,86400" +) +) +thePort (LogicalPort +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 4 +) +) +) +] +shape (Rectangle +uid 12584,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "101000,74000,117000,90000" +) +oxt "40000,9000,56000,25000" +ttg (MlTextGroup +uid 12585,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*44 (Text +uid 12586,0 +va (VaSet +font "Verdana,10,0" +) +xt "101100,89700,105900,90900" +st "AhbLite" +blo "101100,90700" +tm "BdLibraryNameMgr" +) +*45 (Text +uid 12587,0 +va (VaSet +font "Verdana,10,0" +) +xt "101100,90900,110700,92100" +st "ahbMultiplexor" +blo "101100,91900" +tm "CptNameMgr" +) +*46 (Text +uid 12588,0 +va (VaSet +font "Verdana,10,0" +) +xt "101100,92100,105400,93300" +st "I_mux" +blo "101100,93100" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 12589,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 12590,0 +text (MLText +uid 12591,0 +va (VaSet +font "Courier New,8,0" +) +xt "101000,92400,101000,92400" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 13470,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "101250,88250,102750,89750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*47 (SaComponent +uid 12620,0 +optionalChildren [ +*48 (CptPort +uid 12629,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12630,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "100250,61625,101000,62375" +) +tg (CPTG +uid 12631,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12632,0 +va (VaSet +) +xt "102000,61400,105700,62600" +st "hAddr" +blo "102000,62400" +) +) +thePort (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "( ahbAddressBitNb-1 DOWNTO 0 )" +o 1 +) +) +) +*49 (CptPort +uid 12633,0 +ps "OnEdgeStrategy" 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"CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12657,0 +va (VaSet +) +xt "143600,57400,148000,58600" +st "hReady" +ju 2 +blo "148000,58400" +) +) +thePort (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +) +) +) +*57 (CptPort +uid 12658,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12659,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "149000,59625,149750,60375" +) +tg (CPTG +uid 12660,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12661,0 +va (VaSet +) +xt "144200,59400,148000,60600" +st "hResp" +ju 2 +blo "148000,60400" +) +) +thePort (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 3 +) +) +) +*58 (CptPort +uid 12662,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12663,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "149000,55625,149750,56375" +) +tg (CPTG +uid 12664,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12665,0 +va (VaSet +) +xt "143600,55400,148000,56600" +st "hRData" +ju 2 +blo "148000,56400" +) +) +thePort (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +) +) +) +*59 (CptPort +uid 12666,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12667,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "132250,57625,133000,58375" +) +tg (CPTG +uid 12668,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12669,0 +va (VaSet +) +xt "134000,57400,139200,58600" +st "hReadyV" +blo "134000,58400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 2 +) +) +) +*60 (CptPort +uid 12670,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12671,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "132250,59625,133000,60375" +) +tg (CPTG +uid 12672,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12673,0 +va (VaSet +) +xt "134000,59400,138600,60600" +st "hRespV" +blo "134000,60400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 4 +) +) +) +*61 (CptPort +uid 12674,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12675,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "149000,53625,149750,54375" +) +tg (CPTG +uid 12676,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12677,0 +va (VaSet +) +xt "145100,53400,148000,54600" +st "hSel" +ju 2 +blo "148000,54400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 8 +) +) +) +] +shape (Rectangle +uid 12638,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "133000,50000,149000,64000" +) +oxt "40000,11000,56000,25000" +ttg (MlTextGroup +uid 12639,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*62 (Text +uid 12640,0 +va (VaSet +font "Verdana,10,0" +) +xt "133100,63700,137900,64900" +st "AhbLite" +blo "133100,64700" +tm "BdLibraryNameMgr" +) +*63 (Text +uid 12641,0 +va (VaSet +font "Verdana,10,0" +) +xt "133100,64900,144500,66100" +st "ahbMuxConnector" +blo "133100,65900" +tm "CptNameMgr" +) +*64 (Text +uid 12642,0 +va (VaSet +font "Verdana,10,0" +) +xt "133100,66100,138200,67300" +st "I_connT" +blo "133100,67100" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 12643,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 12644,0 +text (MLText +uid 12645,0 +va (VaSet +font "Courier New,8,0" +) +xt "133000,66800,153500,67600" +st "index = periph1Index ( positive ) " +) +header "" +) +elements [ +(GiElement +name "index" +type "positive" +value "periph1Index" +) +] +) +viewicon (ZoomableIcon +uid 13472,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "133250,62250,134750,63750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*65 (SaComponent +uid 12678,0 +optionalChildren [ +*66 (CptPort +uid 12687,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12688,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "132250,87625,133000,88375" +) +tg (CPTG +uid 12689,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12690,0 +va (VaSet +) +xt "134000,87400,137700,88600" +st "hSelV" +blo "134000,88400" +) +) +thePort (LogicalPort +decl (Decl +n "hSelV" +t "std_ulogic_vector" +b "( 1 TO ahbSlaveNb )" +o 5 +) +) +) +*67 (CptPort +uid 12691,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12692,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "132250,89625,133000,90375" +) +tg (CPTG +uid 12693,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12694,0 +va (VaSet +) +xt "134000,89400,139200,90600" +st "hRDataV" +blo "134000,90400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRDataV" +t "ahbDataVector" +o 1 +) +) +) +*68 (CptPort +uid 12695,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12696,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "149000,91625,149750,92375" +) +tg (CPTG +uid 12697,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12698,0 +va (VaSet +) +xt "143600,91400,148000,92600" +st "hReady" +ju 2 +blo "148000,92400" +) +) +thePort (LogicalPort +decl (Decl +n "hReady" +t "std_uLogic" +o 7 +) +) +) +*69 (CptPort +uid 12699,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12700,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "149000,93625,149750,94375" +) +tg (CPTG +uid 12701,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12702,0 +va (VaSet +) +xt "144200,93400,148000,94600" +st "hResp" +ju 2 +blo "148000,94400" +) +) +thePort (LogicalPort +decl (Decl +n "hResp" +t "std_uLogic" +o 3 +) +) +) +*70 (CptPort +uid 12703,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12704,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "149000,89625,149750,90375" +) +tg (CPTG +uid 12705,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12706,0 +va (VaSet +) +xt "143600,89400,148000,90600" +st "hRData" +ju 2 +blo "148000,90400" +) +) +thePort (LogicalPort +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 6 +) +) +) +*71 (CptPort +uid 12707,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12708,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "132250,91625,133000,92375" +) +tg (CPTG +uid 12709,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12710,0 +va (VaSet +) +xt "134000,91400,139200,92600" +st "hReadyV" +blo "134000,92400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 2 +) +) +) +*72 (CptPort +uid 12711,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12712,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "132250,93625,133000,94375" +) +tg (CPTG +uid 12713,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 12714,0 +va (VaSet +) +xt "134000,93400,138600,94600" +st "hRespV" +blo "134000,94400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 to ahbSlaveNb)" +o 4 +) +) +) +*73 (CptPort +uid 12715,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 12716,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "149000,87625,149750,88375" +) +tg (CPTG +uid 12717,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 12718,0 +va (VaSet +) +xt "145100,87400,148000,88600" +st "hSel" +ju 2 +blo "148000,88400" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "hSel" +t "std_uLogic" +o 8 +) +) +) +] +shape (Rectangle +uid 12679,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "133000,84000,149000,98000" +) +oxt "40000,11000,56000,25000" +ttg (MlTextGroup +uid 12680,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*74 (Text +uid 12681,0 +va (VaSet +font "Verdana,10,0" +) +xt "133100,97700,137900,98900" +st "AhbLite" +blo "133100,98700" +tm "BdLibraryNameMgr" +) +*75 (Text +uid 12682,0 +va (VaSet +font "Verdana,10,0" +) +xt "133100,98900,144500,100100" +st "ahbMuxConnector" +blo "133100,99900" +tm "CptNameMgr" +) +*76 (Text +uid 12683,0 +va (VaSet +font "Verdana,10,0" +) +xt "133100,100100,139400,101300" +st "I_connAdc" +blo "133100,101100" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 12684,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 12685,0 +text (MLText +uid 12686,0 +va (VaSet +font "Courier New,8,0" +) +xt "133000,100800,153500,101600" +st "index = periph2Index ( positive ) " +) +header "" +) +elements [ +(GiElement +name "index" +type "positive" +value "periph2Index" +) +] +) +viewicon (ZoomableIcon +uid 13473,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "133250,96250,134750,97750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*77 (Net +uid 13077,0 +decl (Decl +n "reset" +t "std_ulogic" +o 27 +suid 107,0 +) +declText (MLText +uid 13078,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,200,44000,1400" +st "SIGNAL reset : std_ulogic" +) +) +*78 (Net +uid 13079,0 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 108,0 +) +declText (MLText +uid 13080,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,-2200,44000,-1000" +st "SIGNAL clock : std_ulogic" +) +) +*79 (Net +uid 13081,0 +decl (Decl +n "upAddress" +t "unsigned" +b "(ahbAddressBitNb-1 DOWNTO 0)" +o 28 +suid 109,0 +) +declText (MLText +uid 13082,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,163800,57500,165000" +st "SIGNAL upAddress : unsigned(ahbAddressBitNb-1 DOWNTO 0)" +) +) +*80 (Net +uid 13083,0 +decl (Decl +n "upDataOut" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 30 +suid 110,0 +) +declText (MLText +uid 13084,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,165400,60500,166600" +st "SIGNAL upDataOut : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*81 (Net +uid 13085,0 +decl (Decl +n "upDataIn" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 29 +suid 111,0 +) +declText (MLText +uid 13086,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,164600,60500,165800" +st "SIGNAL upDataIn : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*82 (Net +uid 13087,0 +decl (Decl +n "upReadStrobe" +t "std_uLogic" +o 31 +suid 112,0 +) +declText (MLText +uid 13088,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,166200,44000,167400" +st "SIGNAL upReadStrobe : std_uLogic" +) +) +*83 (Net +uid 13089,0 +decl (Decl +n "upWriteStrobe" +t "std_uLogic" +o 32 +suid 113,0 +) +declText (MLText +uid 13090,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,167000,44000,168200" +st "SIGNAL upWriteStrobe : std_uLogic" +) +) +*84 (Net +uid 13091,0 +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 DOWNTO 0)" +o 2 +suid 114,0 +) +declText (MLText +uid 13092,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,105400,57500,106600" +st "SIGNAL hAddr : unsigned(ahbAddressBitNb-1 DOWNTO 0)" +) +) +*85 (Net +uid 13093,0 +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 25 +suid 115,0 +) +declText (MLText +uid 13094,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,149400,60500,150600" +st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*86 (Net +uid 13095,0 +decl (Decl +n "hRData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 7 +suid 116,0 +) +declText (MLText +uid 13096,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,109400,60500,110600" +st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*87 (Net +uid 13097,0 +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 24 +suid 117,0 +) +declText (MLText +uid 13098,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,148600,61000,149800" +st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)" +) +) +*88 (Net +uid 13099,0 +decl (Decl +n "hSize" +t "std_ulogic_vector" +b "(ahbSizeBitNb-1 DOWNTO 0)" +o 23 +suid 118,0 +) +declText (MLText +uid 13100,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,147800,60500,149000" +st "SIGNAL hSize : std_ulogic_vector(ahbSizeBitNb-1 DOWNTO 0)" +) +) +*89 (Net +uid 13101,0 +decl (Decl +n "hBurst" +t "std_ulogic_vector" +b "(ahbBurstBitNb-1 DOWNTO 0)" +o 3 +suid 119,0 +) +declText (MLText +uid 13102,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,106200,61000,107400" +st "SIGNAL hBurst : std_ulogic_vector(ahbBurstBitNb-1 DOWNTO 0)" +) +) +*90 (Net +uid 13103,0 +decl (Decl +n "hProt" +t "std_ulogic_vector" +b "(ahbProtBitNb-1 DOWNTO 0)" +o 6 +suid 120,0 +) +declText (MLText +uid 13104,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,108600,60500,109800" +st "SIGNAL hProt : std_ulogic_vector(ahbProtBitNb-1 DOWNTO 0)" +) +) +*91 (Net +uid 13105,0 +decl (Decl +n "hWrite" +t "std_uLogic" +o 26 +suid 121,0 +) +declText (MLText +uid 13106,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,150200,44000,151400" +st "SIGNAL hWrite : std_uLogic" +) +) +*92 (Net +uid 13107,0 +decl (Decl +n "hReady" +t "std_uLogic" +o 11 +suid 122,0 +) +declText (MLText +uid 13108,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,119000,44000,120200" +st "SIGNAL hReady : std_uLogic" +) +) +*93 (Net +uid 13109,0 +decl (Decl +n "hMastLock" +t "std_uLogic" +o 5 +suid 123,0 +) +declText (MLText +uid 13110,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,107800,44000,109000" +st "SIGNAL hMastLock : std_uLogic" +) +) +*94 (Net +uid 13111,0 +decl (Decl +n "hResp" +t "std_uLogic" +o 16 +suid 124,0 +) +declText (MLText +uid 13112,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,129400,44000,130600" +st "SIGNAL hResp : std_uLogic" +) +) +*95 (Net +uid 13113,0 +decl (Decl +n "hClk" +t "std_uLogic" +o 4 +suid 125,0 +) +declText (MLText +uid 13114,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,107000,44000,108200" +st "SIGNAL hClk : std_uLogic" +) +) +*96 (Net +uid 13115,0 +decl (Decl +n "hReset_n" +t "std_uLogic" +o 15 +suid 126,0 +) +declText (MLText +uid 13116,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,128600,44000,129800" +st "SIGNAL hReset_n : std_uLogic" +) +) +*97 (Net +uid 13117,0 +decl (Decl +n "hSelV" +t "std_ulogic_vector" +b "(1 TO ahbSlaveNb)" +o 22 +suid 127,0 +) +declText (MLText +uid 13118,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,147000,56500,148200" +st "SIGNAL hSelV : std_ulogic_vector(1 TO ahbSlaveNb)" +) +) +*98 (Net +uid 13119,0 +decl (Decl +n "hRDataV" +t "ahbDataVector" +o 10 +suid 128,0 +) +declText (MLText +uid 13120,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,118200,45500,119400" +st "SIGNAL hRDataV : ahbDataVector" +) +) +*99 (Net +uid 13121,0 +decl (Decl +n "hReadyV" +t "std_logic_vector" +b "(1 TO ahbSlaveNb)" +o 14 +suid 129,0 +) +declText (MLText +uid 13122,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,127800,56000,129000" +st "SIGNAL hReadyV : std_logic_vector(1 TO ahbSlaveNb)" +) +) +*100 (Net +uid 13123,0 +decl (Decl +n "hRespV" +t "std_logic_vector" +b "(1 TO ahbSlaveNb)" +o 19 +suid 130,0 +) +declText (MLText +uid 13124,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "26000,138200,56000,139400" +st "SIGNAL hRespV : std_logic_vector(1 TO ahbSlaveNb)" +) +) +*101 (Blk +uid 13243,0 +shape (Rectangle +uid 13244,0 +va (VaSet +vasetType 1 +fg "39936,56832,65280" +lineColor "0,0,32768" +lineWidth 2 +) +xt "37000,106000,185000,114000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 13245,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*102 (Text +uid 13246,0 +va (VaSet +font "Verdana,12,0" +) +xt "36900,113900,46500,115300" +st "AhbLite_test" +blo "36900,115100" +tm "BdLibraryNameMgr" +) +*103 (Text +uid 13247,0 +va (VaSet +font "Verdana,12,0" +) +xt "36900,115300,47800,116700" +st "ahbLite_tester" +blo "36900,116500" +tm "BlkNameMgr" +) +*104 (Text +uid 13248,0 +va (VaSet +font "Verdana,12,0" +) +xt "36900,116700,42800,118100" +st "I_tester" +blo "36900,117900" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 13249,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 13250,0 +text (MLText +uid 13251,0 +va (VaSet +font "Courier New,8,0" +) +xt "37000,119200,65000,120800" +st "periph2BaseAddress = 16#10# ( natural ) +clockFrequency = clockFrequency ( real ) +" +) +header "" +) +elements [ +(GiElement +name "periph2BaseAddress" +type "natural" +value "16#10#" +) +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +] +) +viewicon (ZoomableIcon +uid 13474,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "37250,112250,38750,113750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +) +*105 (Net +uid 13414,0 +decl (Decl +n "hSelPeriph1" +t "std_uLogic" +o 20 +suid 142,0 +) +declText (MLText +uid 13415,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "0,0,18000,1200" +st "SIGNAL hSelPeriph1 : std_uLogic" +) +) +*106 (Net +uid 13416,0 +decl (Decl +n "hRDataPeriph1" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 8 +suid 143,0 +) +declText (MLText +uid 13417,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "0,0,34500,1200" +st "SIGNAL hRDataPeriph1 : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*107 (Net +uid 13418,0 +decl (Decl +n "hReadyPeriph1" +t "std_uLogic" +o 12 +suid 144,0 +) +declText (MLText +uid 13419,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "0,0,18000,1200" +st "SIGNAL hReadyPeriph1 : std_uLogic" +) +) +*108 (Net +uid 13420,0 +decl (Decl +n "hRespPeriph1" +t "std_uLogic" +o 17 +suid 145,0 +) +declText (MLText +uid 13421,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "0,0,18000,1200" +st "SIGNAL hRespPeriph1 : std_uLogic" +) +) +*109 (Net +uid 13422,0 +decl (Decl +n "hSelPeriph2" +t "std_uLogic" +o 21 +suid 146,0 +) +declText (MLText +uid 13423,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "0,0,18000,1200" +st "SIGNAL hSelPeriph2 : std_uLogic" +) +) +*110 (Net +uid 13424,0 +decl (Decl +n "hRDataPeriph2" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 9 +suid 147,0 +) +declText (MLText +uid 13425,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "0,0,34500,1200" +st "SIGNAL hRDataPeriph2 : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)" +) +) +*111 (Net +uid 13426,0 +decl (Decl +n "hReadyPeriph2" +t "std_uLogic" +o 13 +suid 148,0 +) +declText (MLText +uid 13427,0 +va (VaSet +isHidden 1 +font "Courier New,9,0" +) +xt "0,0,18000,1200" +st "SIGNAL hReadyPeriph2 : std_uLogic" +) +) +*112 (Net +uid 13428,0 +decl (Decl +n "hRespPeriph2" +t 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"122600,61600,123400,62400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 12830,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,54000,132250,62000" +pts [ +"117750,62000" +"123000,62000" +"123000,54000" +"132250,54000" +] +) +start &49 +end &54 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 12831,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12832,0 +va (VaSet +font "Verdana,12,0" +) +xt "118000,60600,122300,62000" +st "hSelV" +blo "118000,61800" +tm "WireNameMgr" +) +) +on &97 +) +*121 (Wire +uid 12835,0 +optionalChildren [ +*122 (BdJunction +uid 12839,0 +ps "OnConnectorStrategy" +shape (Circle +uid 12840,0 +va (VaSet +vasetType 1 +) +xt "122600,77600,123400,78400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 12836,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,62000,123000,78000" +pts [ +"123000,62000" +"123000,78000" +"117750,78000" +] +) +start &120 +end &37 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 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"123000,88000,132250,88000" +pts [ +"132250,88000" +"123000,88000" +] +) +start &66 +end &124 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 12855,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12856,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "127250,86600,131550,88000" +st "hSelV" +blo "127250,87800" +tm "WireNameMgr" +) +) +on &97 +) +*126 (Wire +uid 12857,0 +optionalChildren [ +*127 (BdJunction +uid 12861,0 +ps "OnConnectorStrategy" +shape (Circle +uid 12862,0 +va (VaSet +vasetType 1 +) +xt "124600,81600,125400,82400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 12858,0 +va (VaSet +vasetType 3 +) +xt "117750,56000,132250,82000" +pts [ +"117750,82000" +"125000,82000" +"125000,56000" +"132250,56000" +] +) +start &38 +end &55 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 12859,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12860,0 +va (VaSet +font "Verdana,12,0" +) +xt "119750,80600,125950,82000" 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"hReadyV" +blo "125250,91800" +tm "WireNameMgr" +) +) +on &99 +) +*136 (Wire +uid 12901,0 +optionalChildren [ +*137 (BdJunction +uid 12905,0 +ps "OnConnectorStrategy" +shape (Circle +uid 12906,0 +va (VaSet +vasetType 1 +) +xt "128600,85600,129400,86400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 12902,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,60000,132250,86000" +pts [ +"117750,86000" +"129000,86000" +"129000,60000" +"132250,60000" +] +) +start &43 +end &60 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 12903,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 12904,0 +va (VaSet +font "Verdana,12,0" +) +xt "119750,84600,125250,86000" +st "hRespV" +blo "119750,85800" +tm "WireNameMgr" +) +) +on &100 +) +*138 (Wire +uid 12907,0 +optionalChildren [ +*139 (BdJunction +uid 12913,0 +ps "OnConnectorStrategy" +shape (Circle +uid 12914,0 +va (VaSet +vasetType 1 +) +xt "128600,93600,129400,94400" +radius 400 +) +) +] +shape (OrthoPolyLine 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"0,5800,3200,7000" +st "User:" +blo "0,6800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,10,1" +) +xt "0,3400,7800,4600" +st "Internal User:" +blo "0,4400" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,7000,2000,7000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,3400,0,3400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 134,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/Libs/AhbLite_test/hds/ahb@lite_tester/interface b/Libs/AhbLite_test/hds/ahb@lite_tester/interface new file mode 100644 index 0000000..af57cd1 --- /dev/null +++ b/Libs/AhbLite_test/hds/ahb@lite_tester/interface @@ -0,0 +1,2685 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "AhbLite" +unitName "ahbLite" +) +] +libraryRefs [ +"ieee" +"AhbLite" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 147,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 200,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 127,0 +) +) +uid 1306,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 DOWNTO 0)" +o 2 +suid 128,0 +) +) +uid 1308,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "hClk" +t "std_uLogic" +o 4 +suid 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"SourceDir" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\..\\Libs\\AhbLite_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "interface" +) +(vvPair +variable "asm_file" +value "nanoTest.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\..\\Libs\\AhbLite_test\\hds\\ahb@lite_tester" +) +(vvPair +variable "d_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\..\\Libs\\AhbLite_test\\hds\\ahbLite_tester" +) +(vvPair +variable "date" +value "28.04.2023" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "ahbLite_tester" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "interface" +) +(vvPair +variable "f_logical" +value "interface" +) +(vvPair +variable "f_noext" +value "interface" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "28.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:16:10" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "AhbLite_test" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/AhbLite_test" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "ahbLite_tester" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\..\\Libs\\AhbLite_test\\hds\\ahb@lite_tester\\interface" +) +(vvPair +variable "p_logical" +value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\..\\Libs\\AhbLite_test\\hds\\ahbLite_tester\\interface" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "this_ext" +value "" +) +(vvPair +variable "this_file" +value "interface" +) +(vvPair +variable "this_file_logical" +value "interface" +) +(vvPair +variable "time" +value "15:16:10" +) +(vvPair +variable "unit" +value "ahbLite_tester" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "interface" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 198,0 +optionalChildren [ +*97 (SymbolBody +uid 8,0 +optionalChildren [ +*98 (CptPort +uid 1201,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1202,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34625,5250,35375,6000" +) +tg (CPTG +uid 1203,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1204,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "34300,7000,35700,10800" +st "clock" +ju 2 +blo "35500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1205,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,63500,10000" +st "clock : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 127,0 +) +) +) +*99 (CptPort +uid 1206,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1207,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "134625,5250,135375,6000" +) +tg (CPTG +uid 1208,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1209,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "134300,7000,135700,11500" +st "hAddr" +ju 2 +blo "135500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1210,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2000,77000,2800" +st "hAddr : IN unsigned (ahbAddressBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "hAddr" +t "unsigned" +b "(ahbAddressBitNb-1 DOWNTO 0)" +o 2 +suid 128,0 +) +) +) +*100 (CptPort +uid 1211,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1212,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60625,5250,61375,6000" +) +tg (CPTG +uid 1213,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1214,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "60300,7000,61700,10500" +st "hClk" +ju 2 +blo "61500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1215,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2800,63500,3600" +st "hClk : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hClk" +t "std_uLogic" +o 4 +suid 129,0 +) +) +) +*101 (CptPort +uid 1216,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1217,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "152625,5250,153375,6000" +) +tg (CPTG +uid 1218,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1219,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "152300,7000,153700,18000" +st "hRDataPeriph1" +ju 2 +blo "153500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1220,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10000,80000,10800" +st "hRDataPeriph1 : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRDataPeriph1" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 8 +suid 130,0 +) +) +) +*102 (CptPort +uid 1221,0 +ps "OnEdgeStrategy" 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"150300,7000,151700,18100" +st "hReadyPeriph1" +ju 2 +blo "151500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1230,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11600,63500,12400" +st "hReadyPeriph1 : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReadyPeriph1" +t "std_uLogic" +o 12 +suid 132,0 +) +) +) +*104 (CptPort +uid 1231,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1232,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "140625,5250,141375,6000" +) +tg (CPTG +uid 1233,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1234,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "140300,7000,141700,18100" +st "hReadyPeriph2" +ju 2 +blo "141500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1235,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12400,63500,13200" +st "hReadyPeriph2 : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hReadyPeriph2" +t "std_uLogic" +o 13 +suid 133,0 +) +) +) +*105 (CptPort +uid 1236,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1237,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58625,5250,59375,6000" +) +tg (CPTG +uid 1238,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1239,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "58300,7000,59700,13800" +st "hReset_n" +ju 2 +blo "59500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1240,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3600,63500,4400" +st "hReset_n : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hReset_n" +t "std_uLogic" +o 15 +suid 134,0 +) +) +) +*106 (CptPort +uid 1241,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1242,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "148625,5250,149375,6000" +) +tg (CPTG +uid 1243,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1244,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "148300,7000,149700,17300" +st "hRespPeriph1" +ju 2 +blo "149500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1245,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,13200,63500,14000" +st "hRespPeriph1 : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRespPeriph1" +t "std_uLogic" +o 17 +suid 135,0 +) +) +) +*107 (CptPort +uid 1246,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1247,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "138625,5250,139375,6000" +) +tg (CPTG +uid 1248,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1249,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "138300,7000,139700,17300" +st "hRespPeriph2" +ju 2 +blo "139500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1250,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14000,63500,14800" +st "hRespPeriph2 : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "hRespPeriph2" +t "std_uLogic" +o 18 +suid 136,0 +) +) +) +*108 (CptPort +uid 1251,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1252,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "154625,5250,155375,6000" +) +tg (CPTG +uid 1253,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1254,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "154300,7000,155700,16100" +st "hSelPeriph1" +ju 2 +blo "155500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1255,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4400,63500,5200" +st "hSelPeriph1 : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hSelPeriph1" +t "std_uLogic" +o 20 +suid 137,0 +) +) +) +*109 (CptPort +uid 1256,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1257,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "144625,5250,145375,6000" +) +tg (CPTG +uid 1258,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1259,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "144300,7000,145700,16100" +st "hSelPeriph2" +ju 2 +blo "145500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1260,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5200,63500,6000" +st "hSelPeriph2 : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hSelPeriph2" +t "std_uLogic" +o 21 +suid 138,0 +) +) +) +*110 (CptPort +uid 1261,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1262,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "130625,5250,131375,6000" +) +tg (CPTG +uid 1263,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1264,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "130300,7000,131700,12100" +st "hTrans" +ju 2 +blo "131500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1265,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,80500,6800" +st "hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "hTrans" +t "std_ulogic_vector" +b "(ahbTransBitNb-1 DOWNTO 0)" +o 24 +suid 139,0 +) +) +) +*111 (CptPort +uid 1266,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1267,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "132625,5250,133375,6000" +) +tg (CPTG +uid 1268,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1269,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "132300,7000,133700,12900" +st "hWData" +ju 2 +blo "133500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1270,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,80000,7600" +st "hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "hWData" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 25 +suid 140,0 +) +) +) +*112 (CptPort +uid 1271,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1272,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "128625,5250,129375,6000" +) +tg (CPTG +uid 1273,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1274,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "128300,7000,129700,12000" +st "hWrite" +ju 2 +blo "129500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1275,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7600,63500,8400" +st "hWrite : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "hWrite" +t "std_uLogic" +o 26 +suid 141,0 +) +) +) +*113 (CptPort +uid 1276,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1277,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36625,5250,37375,6000" +) +tg (CPTG +uid 1278,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1279,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "36300,7000,37700,11100" +st "reset" +ju 2 +blo "37500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1280,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14800,63500,15600" +st "reset : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "reset" +t "std_ulogic" +o 27 +suid 142,0 +) +) +) +*114 (CptPort +uid 1281,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1282,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "22625,5250,23375,6000" +) +tg (CPTG +uid 1283,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1284,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "22300,7000,23700,14500" +st "upAddress" +ju 2 +blo "23500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1285,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,15600,77000,16400" +st "upAddress : OUT unsigned (ahbAddressBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "upAddress" +t "unsigned" +b "(ahbAddressBitNb-1 DOWNTO 0)" +o 28 +suid 143,0 +) +) +) +*115 (CptPort +uid 1286,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1287,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "26625,5250,27375,6000" +) +tg (CPTG +uid 1288,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1289,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "26300,7000,27700,13700" +st "upDataIn" +ju 2 +blo "27500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1290,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,8400,80000,9200" +st "upDataIn : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "upDataIn" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 29 +suid 144,0 +) +) +) +*116 (CptPort +uid 1291,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1292,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24625,5250,25375,6000" +) +tg (CPTG +uid 1293,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1294,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "24300,7000,25700,14700" +st "upDataOut" +ju 2 +blo "25500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1295,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,16400,80000,17200" +st "upDataOut : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "upDataOut" +t "std_ulogic_vector" +b "(ahbDataBitNb-1 DOWNTO 0)" +o 30 +suid 145,0 +) +) +) +*117 (CptPort +uid 1296,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1297,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "28625,5250,29375,6000" +) +tg (CPTG +uid 1298,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1299,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "28300,7000,29700,17600" +st "upReadStrobe" +ju 2 +blo "29500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1300,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,17200,63500,18000" +st "upReadStrobe : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "upReadStrobe" +t "std_uLogic" +o 31 +suid 146,0 +) +) +) +*118 (CptPort +uid 1301,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1302,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30625,5250,31375,6000" +) +tg (CPTG +uid 1303,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1304,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "30300,7000,31700,17800" +st "upWriteStrobe" +ju 2 +blo "31500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1305,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,18000,62500,18800" +st "upWriteStrobe : OUT std_uLogic +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "upWriteStrobe" +t "std_uLogic" +o 32 +suid 147,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,163000,14000" +) +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +) +xt "84650,8800,92550,10000" +st "AhbLite_test" +blo "84650,9800" +) +second (Text +uid 12,0 +va (VaSet +) +xt "84650,10000,93350,11200" +st "ahbLite_tester" +blo "84650,11000" +) +) +gi *119 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "54000,6000,70000,9200" +st "Generic Declarations + +periph2BaseAddress natural +clockFrequency real " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "periph2BaseAddress" +type "natural" +value "" +) +(GiElement +name "clockFrequency" +type "real" +value "" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*120 (Grouping +uid 16,0 +optionalChildren [ +*121 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "36200,48000,47600,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*122 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*123 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*124 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*125 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "53200,45200,62600,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*126 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "57200,44000,58800,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*127 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "37350,44400,47650,45600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*128 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*129 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*130 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "36200,47000,49500,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "65535,0,0" +) +packageList *131 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*132 (Text +uid 49,0 +va (VaSet +font "Verdana,8,1" +) +xt "0,0,6900,1000" +st "Package List" +blo "0,800" +) +*133 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,17500,7000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY AhbLite; + USE AhbLite.ahbLite.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1017,690" +viewArea "-500,-500,71299,48094" +cachedDiagramExtent "0,0,163000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Courier New,9,0" +) +xt "1000,1000,4500,2200" +st "Panel0" +blo "1000,1900" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "AhbLite_test" +entityName "ahbLite_tb" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,55000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "32800,15000,37200,16000" +st "" +blo "32800,15800" +) +second (Text +va (VaSet +) +xt "32800,16000,36000,17000" +st "" +blo "32800,16800" +) +) +gi *134 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *135 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,0,49000,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,1000,45400,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,8,1" +) +xt "42000,18800,45000,19800" +st "User:" +blo "42000,19600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "42000,0,49600,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,19800,44000,19800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 1347,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/AhbLite_test/hds/hds/_cordic_tb._epf b/Libs/AhbLite_test/hds/hds/_cordic_tb._epf new file mode 100644 index 0000000..21b4705 --- /dev/null +++ b/Libs/AhbLite_test/hds/hds/_cordic_tb._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom cordic_tb/struct.bd diff --git a/Libs/AhbLite_test/hds/hds/_cordic_tester._epf b/Libs/AhbLite_test/hds/hds/_cordic_tester._epf new file mode 100644 index 0000000..571444e --- /dev/null +++ b/Libs/AhbLite_test/hds/hds/_cordic_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom cordic_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/AhbLite_test/hds/hds/_motherboard_tb._epf b/Libs/AhbLite_test/hds/hds/_motherboard_tb._epf new file mode 100644 index 0000000..b97c86e --- /dev/null +++ b/Libs/AhbLite_test/hds/hds/_motherboard_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom motherboard_tb/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/AhbLite_test/hds/hds/_motherboard_tester._epf b/Libs/AhbLite_test/hds/hds/_motherboard_tester._epf new file mode 100644 index 0000000..7fb5b51 --- /dev/null +++ b/Libs/AhbLite_test/hds/hds/_motherboard_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom motherboard_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Common/hdl/blinker_arch.vhd b/Libs/Common/hdl/blinker_arch.vhd new file mode 100644 index 0000000..3d29f7e --- /dev/null +++ b/Libs/Common/hdl/blinker_arch.vhd @@ -0,0 +1,89 @@ +-- filename: blinker.vhd +-- kind: vhdl file +-- first created: 18.06.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : zas 18.06.2012 -- Initial Version +-------------------------------------------------------------------------------- +-- Description: +-- For let blinking a LED with an signal event +-- Mode = 0 (reactive on rising edge) +-- ___________________________________________ +-- input ____/ +-- ___________________ +-- output ____/ \_______________________ +-- time 0s 0.5s 1s +-- +-- _ +-- input ____/ \_________________________________________ +-- ___________________ +-- output ____/ \_______________________ +-- time 0s 0.5s 1s +---- +-- Mode = 1 (reactive on falling edge) +-- _____ +-- input \__________________________________________ +-- ___________________ +-- output ______/ \_____________________ +-- time 0s 0.5s 1s +-- +-- _ +-- input ____/ \_________________________________________ +-- ___________________ +-- output ______ / \____________________ +-- time 0s 0.5s 1s +-- +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.NUMERIC_STD.all; + +LIBRARY Common; +USE Common.CommonLib.all; + + +ARCHITECTURE arch OF blinker IS + + constant c : integer := clockFrequency/2; -- 500ms blink + + signal cnt : unsigned(requiredBitNb(c)-1 downto 0); + signal en_delay : std_ulogic; + signal blink_int : std_ulogic; + +BEGIN + + process(reset, clock) + begin + if reset = '1' then + en_delay <= '0'; + blink_int <= '0'; + cnt <= (others => '0'); + elsif rising_edge(clock) then + en_delay <= en; + -- detect rising_edge + if mode = 0 then + if blink_int = '0' and en_delay = '0' and en = '1' then + blink_int <= '1'; + end if; + else + -- detect falling edge + if blink_int = '0' and en_delay = '1' and en = '0' then + blink_int <= '1'; + end if; + end if; + -- blink + if blink_int = '1' then + if (cnt < c) then + cnt <= cnt + 1; + else + cnt <= (others => '0'); + blink_int <= '0'; + end if; + end if; + end if; + end process; + + -- Set output + blink <= blink_int; +END ARCHITECTURE arch; diff --git a/Libs/Common/hdl/commonLib.vhd b/Libs/Common/hdl/commonLib.vhd new file mode 100644 index 0000000..223f0b5 --- /dev/null +++ b/Libs/Common/hdl/commonLib.vhd @@ -0,0 +1,68 @@ +-------------------------------------------------------------------------------- +-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch) +-------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-- ----------------------------------------------------------------------------- +-- Common Lib +-- +-- ----------------------------------------------------------------------------- +-- Authors: +-- cof: [François Corthay](francois.corthay@hevs.ch) +-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +-- ----------------------------------------------------------------------------- +-- Changelog: +-- 2016-06 : guo +-- added function sel +-- 2015-06 : guo +-- added counterBitNb +-- added documentation +-- ----------------------------------------------------------------------------- +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + +PACKAGE CommonLib IS + + ------------------------------------------------------------------------------ + -- Returns the number of bits needed to represent the given val + -- Examples: + -- requiredBitNb(1) = 1 (1) + -- requiredBitNb(2) = 2 (10) + -- requiredBitNb(3) = 2 (11) + function requiredBitNb(val : integer) return integer; + + ------------------------------------------------------------------------------ + -- Returns the number of bits needed to count val times (0 to val-1) + -- Examples: + -- counterBitNb(1) = 1 (0) + -- counterBitNb(2) = 1 (0->1) + -- counterBitNb(3) = 2 (0->1->10) + function counterBitNb(val : integer) return integer; + + ------------------------------------------------------------------------------ + -- Functions to return one or the other input based on a boolean. + -- Can be used to build conditional constants. + -- Example: + -- constant bonjour_c : string := sel(ptpRole = master, "fpga20", "fpga02"); + function sel(Cond : BOOLEAN; If_True, If_False : integer) + return integer; + function sel(Cond : BOOLEAN; If_True, If_False : string) + return string; + function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector) + return std_ulogic_vector; + function sel(Cond : BOOLEAN; If_True, If_False : unsigned) + return unsigned; + function sel(Cond : BOOLEAN; If_True, If_False : signed) + return signed; + +END CommonLib; diff --git a/Libs/Common/hdl/commonLib_body.vhd b/Libs/Common/hdl/commonLib_body.vhd new file mode 100644 index 0000000..58a33ee --- /dev/null +++ b/Libs/Common/hdl/commonLib_body.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch) +-------------------------------------------------------------------------------- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-- ----------------------------------------------------------------------------- +-- Often used functions +-- +-- ----------------------------------------------------------------------------- +-- Authors: +-- cof: [François Corthay](francois.corthay@hevs.ch) +-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch) +-- ----------------------------------------------------------------------------- +-- Changelog: +-- 2016-06 : guo +-- added function sel +-- 2015-06 : guo +-- added counterBitNb +-- ----------------------------------------------------------------------------- +PACKAGE BODY CommonLib IS + + function requiredBitNb (val : integer) return integer is + variable powerOfTwo, bitNb : integer; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo <= val loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end requiredBitNb; + + function counterBitNb (val : integer) return integer is + variable powerOfTwo, bitNb : integer; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo < val loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end counterBitNb; + + function sel(Cond : BOOLEAN; If_True, If_False : integer) + return integer is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : string) + return string is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector) + return std_ulogic_vector is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : unsigned) + return unsigned is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + + function sel(Cond : BOOLEAN; If_True, If_False : signed) + return signed is + begin + if (Cond = TRUE) then + return (If_True); + else + return (If_False); + end if; + end function sel; + +END CommonLib; diff --git a/Libs/Common/hdl/debounce_rtl.vhd b/Libs/Common/hdl/debounce_rtl.vhd new file mode 100644 index 0000000..83aae18 --- /dev/null +++ b/Libs/Common/hdl/debounce_rtl.vhd @@ -0,0 +1,112 @@ +-- filename: debounced.vhd +-- kind: vhdl file +-- first created: 11.01.2024 +-- created by: boy +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : boy 11.01.2024 -- Initial Version + +-------------------------------------------------------------------------------- +-- Description: +-- debounceds a button on both edges. +-- _ _ ____________________ _ _ +-- input ____/ \_/ \_/ \_/ \_/ \______ +-- _____________________________ +-- output __________________/ \____________ +-- +-------------------------------------------------------------------------------- +-- Generics: +-- g_debounceTime (time) : parameter to fix the debounce time. +-- g_minConsecutiveStateCount (integer) : The number of consecutive readings of the same state required to change the output. +-- g_clockFrequency (real) : Clock frequency of the system +-- g_activeState (std_ulogic) : The output will be reset in "inactive" state. +-------------------------------------------------------------------------------- +-- Input is read each g_debounceTime, and a constant value must appear for +-- g_minConsecutiveStateCount to be forwarded on the output. +-- To update the output, x consecutive samples needs to have +-- the exact same value. x is given with the "g_minConsecutiveStateCount" parameter +-------------------------------------------------------------------------------- +LIBRARY ieee; + USE ieee.math_real.all; +LIBRARY Common; + USE Common.CommonLib.all; + + +ARCHITECTURE rtl OF debounce IS + + -- Creates a vector of alternating 1's and 0's (0b...1010) + pure function alternating_ones_and_zeros(length : integer) return std_ulogic_vector is + variable ret_val : std_ulogic_vector(length - 1 downto 0); + BEGIN + for i in 0 to length - 1 loop + if i mod 2 = 1 then + ret_val(i) := '1'; + else + ret_val(i) := '0'; + end if; + end loop; + + return ret_val; + end function alternating_ones_and_zeros; + + -- To check if all bits are '1' + constant c_LOGICAL_HIGH_VALID: std_ulogic_vector((g_minConsecutiveStateCount-1) downto 0) := (others=>'1'); + -- To check if all bits are '0' + constant c_LOGICAL_LOW_VALID: std_ulogic_vector((g_minConsecutiveStateCount-1) downto 0) := (others=>'0'); + -- Alternating 1's and 0's for reset value + constant c_INIT_SAMPLE: std_ulogic_vector((g_minConsecutiveStateCount-1) downto 0) := alternating_ones_and_zeros(g_minConsecutiveStateCount); + -- Delay between two samplings + -- delay = (g_debounceTime * g_clockFrequency) / g_minConsecutiveStateCount - 1 + constant DELAY: positive := integer(ceil(((real(g_debounceTime / 1 ps) / 1.0e12) * g_clockFrequency) / real(g_minConsecutiveStateCount))) - 1; + + -- Holds the state of registered consecutive inputs + signal lvec_sample: std_ulogic_vector((g_minConsecutiveStateCount-1) downto 0); + -- Defines when we will sample (based on given DELAY) + signal lsig_samplePulse: std_ulogic := '0'; + -- Counter for the delay + signal lvec_count : unsigned(requiredBitNb(DELAY)-1 downto 0); + +BEGIN + + clockDivider: process(reset, clock) --Clock Divider + begin + if reset = '1' then + lvec_count <= (others => '0'); + lsig_samplePulse <= '0'; + elsif rising_edge(clock) then + if (lvec_count < DELAY) then + lvec_count <= lvec_count + 1; + lsig_samplePulse <= '0'; + else + lvec_count <= (others => '0'); + lsig_samplePulse <= '1'; + end if; + end if; + end process clockDivider; + + sampling: process(reset, clock) --Sampling Process + begin + if reset = '1' then + lvec_sample <= c_INIT_SAMPLE; + elsif rising_edge(clock) then + if lsig_samplePulse = '1' then + lvec_sample((g_minConsecutiveStateCount - 1) downto 1) <= lvec_sample((g_minConsecutiveStateCount - 2) downto 0); -- Left Shift + lvec_sample(0) <= input; + end if; + end if; + end process sampling; + + inputDebouncing: process(reset, clock) --Input Debouncing + begin + if reset = '1' then + debounced <= not g_activeState; + elsif rising_edge(clock) then + if lvec_sample = c_LOGICAL_HIGH_VALID then --Active High Constant Out + debounced <= '1'; + elsif lvec_sample = c_LOGICAL_LOW_VALID then + debounced <= '0'; + end if; + end if; + end process inputDebouncing; +END ARCHITECTURE rtl; + diff --git a/Libs/Common/hdl/debouncerULogicVector_RTL.vhd b/Libs/Common/hdl/debouncerULogicVector_RTL.vhd new file mode 100644 index 0000000..734485e --- /dev/null +++ b/Libs/Common/hdl/debouncerULogicVector_RTL.vhd @@ -0,0 +1,97 @@ +-- filename: debouncer.vhd +-- kind: vhdl file +-- first created: 05.03.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : zas 05.03.2012 -- Initial Version +-- v0.2 : cof 22.01.2013 -- synchronization to clock +-------------------------------------------------------------------------------- +-- Description: +-- Debounces a button on both edges. +-- _ _ ____________________ _ _ +-- input ____/ \_/ \_/ \_/ \_/ \______ +-- _____________________________ +-- output _____/ \____________ +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF debouncerULogicVector IS + + signal inputNormal : std_ulogic_vector(input'range); + signal inputSynch, inputDelayed, inputChanged : std_ulogic; + signal debounceCounter : unsigned(counterBitNb-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- adapt polarity + adaptPolarity: process(input) + begin + for index in input'range loop + inputNormal(index) <= input(index) xor invertInput; + end loop; + end process adaptPolarity; + + ------------------------------------------------------------------------------ + -- Synchronize input to clock + synchInput: process(reset, clock) + variable inputOr : std_ulogic; + begin + if reset = '1' then + inputSynch <= '0'; + elsif rising_edge(clock) then + inputOr := '0'; + for index in input'range loop + inputOr := inputOr or inputNormal(index); + end loop; + inputSynch <= inputOr; + end if; + end process synchInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputSynch; + end if; + end process delayInput; + + inputChanged <= '1' when inputDelayed /= inputSynch + else '0'; + + ------------------------------------------------------------------------------ + -- Debounce counter + countDeadTime: process(reset, clock) + begin + if reset = '1' then + debounceCounter <= (others => '0'); + elsif rising_edge(clock) then + if debounceCounter = 0 then + if inputChanged = '1' then + debounceCounter <= debounceCounter - 1; + end if; + else + debounceCounter <= debounceCounter - 1; + end if; + end if; + end process countDeadTime; + + ------------------------------------------------------------------------------ + -- Update output + updateOutput: process(reset, clock) + begin + if reset = '1' then + debounced <= (others => '0'); + elsif rising_edge(clock) then + if (inputChanged = '1') and (debounceCounter = 0) then + debounced <= inputNormal; + elsif debounceCounter = 1 then + debounced <= inputNormal; + end if; + end if; + end process updateOutput; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/debouncer_RTL.vhd b/Libs/Common/hdl/debouncer_RTL.vhd new file mode 100644 index 0000000..a74c383 --- /dev/null +++ b/Libs/Common/hdl/debouncer_RTL.vhd @@ -0,0 +1,83 @@ +-- filename: debouncer.vhd +-- kind: vhdl file +-- first created: 05.03.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : zas 05.03.2012 -- Initial Version +-- v0.2 : cof 22.01.2013 -- synchronization to clock +-- -- direct reaction on both edges +-------------------------------------------------------------------------------- +-- Description: +-- Debounces a button on both edges. +-- _ _ ____________________ _ _ +-- input ____/ \_/ \_/ \_/ \_/ \______ +-- _____________________________ +-- output _____/ \____________ +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF debouncer IS + + signal debounceCounter : unsigned(counterBitNb-1 downto 0); + signal inputSynch, inputDelayed, inputChanged : std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- Synchronize input to clock + synchInput: process(reset, clock) + begin + if reset = '1' then + inputSynch <= '0'; + elsif rising_edge(clock) then + inputSynch <= input xor invertInput; + end if; + end process synchInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputSynch; + end if; + end process delayInput; + + inputChanged <= '1' when inputDelayed /= inputSynch + else '0'; + + ------------------------------------------------------------------------------ + -- Debounce counter + countDeadTime: process(reset, clock) + begin + if reset = '1' then + debounceCounter <= (others => '0'); + elsif rising_edge(clock) then + if debounceCounter = 0 then + if inputChanged = '1' then + debounceCounter <= debounceCounter - 1; + end if; + else + debounceCounter <= debounceCounter - 1; + end if; + end if; + end process countDeadTime; + + ------------------------------------------------------------------------------ + -- Update output + updateOutput: process(reset, clock) + begin + if reset = '1' then + debounced <= '0'; + elsif rising_edge(clock) then + if (inputChanged = '1') and (debounceCounter = 0) then + debounced <= input; + elsif debounceCounter = 1 then + debounced <= input; + end if; + end if; + end process updateOutput; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/edgeDetector_rtl.vhd b/Libs/Common/hdl/edgeDetector_rtl.vhd new file mode 100644 index 0000000..a9ae99a --- /dev/null +++ b/Libs/Common/hdl/edgeDetector_rtl.vhd @@ -0,0 +1,48 @@ +-------------------------------------------------------------------------------- +-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch) +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program IS distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- You should have received a copy of the GNU General Public License along with +-- this program. If not, see +-------------------------------------------------------------------------------- +-- EdgeDetector +-- Detect rising and falling edges of a signal. +-- +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : guo 2014-04-02 -- Initial version +-- v1.0 : cof 2019-10-02 -- Updated symbol +-------------------------------------------------------------------------------- +ARCHITECTURE RTL OF edgeDetector IS + + SIGNAL pulse_delayed : std_ulogic; + SIGNAL rising_detected_s : std_ulogic; + SIGNAL falling_detected_s : std_ulogic; + +BEGIN + + -- delay pulse + reg : PROCESS (reset, clock) + BEGIN + IF reset = '1' THEN + pulse_delayed <= '0'; + ELSIF rising_edge(clock) THEN + pulse_delayed <= pulse; + END IF; + END PROCESS reg ; + + -- edge detection + rising <= '1' when (pulse = '1') and (pulse_delayed = '0') + else '0'; + falling <= '1' when (pulse = '0') and (pulse_delayed = '1') + else '0'; + +END ARCHITECTURE RTL; diff --git a/Libs/Common/hdl/rotaryToUnsigned_rtl.vhd b/Libs/Common/hdl/rotaryToUnsigned_rtl.vhd new file mode 100644 index 0000000..8f1a378 --- /dev/null +++ b/Libs/Common/hdl/rotaryToUnsigned_rtl.vhd @@ -0,0 +1,76 @@ +ARCHITECTURE rtl OF rotaryToUnsigned IS + + signal rotaryDelayed1, rotaryDelayed2, rotaryStable : unsigned(rotary'range); + signal rotary_changed : std_ulogic; + signal glitchDelayCounter : unsigned(counterBitNb-1 downto 0); + signal rotaryStableDelayed : unsigned(rotary'range); + signal numberMsbs : unsigned(number'length-rotary'length-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- synchronize input and detect changes + delayRotary: process(reset, clock) + begin + if reset = '1' then + rotaryDelayed1 <= (others => '0'); + rotaryDelayed2 <= (others => '0'); + elsif rising_edge(clock) then + rotaryDelayed1 <= rotary; + rotaryDelayed2 <= rotaryDelayed1; + end if; + end process delayRotary; + + rotary_changed <= '1' when rotaryDelayed1 /= rotaryDelayed2 + else '0'; + -- count dead time + countDeadTime: process(reset, clock) + begin + if reset = '1' then + glitchDelayCounter <= (others => '1'); + elsif rising_edge(clock) then + if rotary_changed = '1' then + glitchDelayCounter <= (others => '1'); + elsif glitchDelayCounter > 0 then + glitchDelayCounter <= glitchDelayCounter - 1; + end if; + end if; + end process countDeadTime; + -- store new rotary button value + storeRotary: process(reset, clock) + begin + if reset = '1' then + rotaryStable <= (others => '0'); + elsif rising_edge(clock) then + if glitchDelayCounter = 0 then + rotaryStable <= rotaryDelayed2; + end if; + end if; + end process storeRotary; + + ------------------------------------------------------------------------------ + -- keep previous value of stablilzed rotary + delayRotaryStable: process(reset, clock) + begin + if reset = '1' then + rotaryStableDelayed <= (others => '0'); + elsif rising_edge(clock) then + rotaryStableDelayed <= rotaryStable; + end if; + end process delayRotaryStable; + -- synchronize input and detect changes + updateMsbs: process(reset, clock) + begin + if reset = '1' then + numberMsbs <= (others => '0'); + elsif rising_edge(clock) then + if (rotaryStable = 0) and (rotaryStableDelayed+1 = 0) then + numberMsbs <= numberMsbs + 1; + elsif (rotaryStable+1 = 0) and (rotaryStableDelayed = 0) then + numberMsbs <= numberMsbs - 1; + end if; + end if; + end process updateMsbs; + + number <= numberMsbs & rotaryStableDelayed; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/spikeFilter_RTL.vhd b/Libs/Common/hdl/spikeFilter_RTL.vhd new file mode 100644 index 0000000..b176aa8 --- /dev/null +++ b/Libs/Common/hdl/spikeFilter_RTL.vhd @@ -0,0 +1,82 @@ +-------------------------------------------------------------------------------- +-- Description: +-- Filters short time spikes. +-- _ _ ____________________ _ _ +-- input ____/ \_/ \_/ \_/ \_/ \_________________ +-- _____________________________ +-- output ________________/ \____________ +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF spikeFilter IS + + signal filterCounter : unsigned(counterBitNb-1 downto 0); + signal inputSynch, inputDelayed, inputChanged : std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- Synchronize input to clock + synchInput: process(reset, clock) + begin + if reset = '1' then + inputSynch <= '0'; + elsif rising_edge(clock) then + inputSynch <= input xor invertInput; + end if; + end process synchInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputSynch; + end if; + end process delayInput; + + inputChanged <= '1' when inputDelayed /= inputSynch + else '0'; + + ------------------------------------------------------------------------------ + -- Debounce counter + countDeadTime: process(reset, clock) + begin + if reset = '1' then + filterCounter <= (others => '0'); + elsif rising_edge(clock) then + if filterCounter = 0 then + if inputChanged = '1' then + filterCounter <= filterCounter + 1; + end if; + elsif signed(filterCounter)+1 = 0 then + if inputChanged = '1' then + filterCounter <= filterCounter - 1; + end if; + else + if inputSynch = '0' then + filterCounter <= filterCounter - 1; + else + filterCounter <= filterCounter + 1; + end if; + end if; + end if; + end process countDeadTime; + + ------------------------------------------------------------------------------ + -- Update output + updateOutput: process(reset, clock) + begin + if reset = '1' then + filtered <= '0'; + elsif rising_edge(clock) then + if filterCounter = 0 then + filtered <= '0'; + elsif signed(filterCounter)+1 = 0 then + filtered <= '1'; + end if; + end if; + end process updateOutput; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hdl/toggler_RTL.vhd b/Libs/Common/hdl/toggler_RTL.vhd new file mode 100644 index 0000000..1b47128 --- /dev/null +++ b/Libs/Common/hdl/toggler_RTL.vhd @@ -0,0 +1,90 @@ +-- filename: toggler.vhd +-- kind: vhdl file +-- first created: 05.03.2012 +-- created by: zas +-------------------------------------------------------------------------------- +-- History: +-- v0.1 : cof 22.01.2013 -- Initial version +-------------------------------------------------------------------------------- +-- Description: +-- Debounces a button on both edges. +-- _ _ +-- input ____/ \__________________________/ \____________ +-- _____________________________ +-- output _____/ \____________ +-- +-- If the generic "counterBitNb" is greater than zero, a debouncer is placed on +-- the input signal. +-- +-------------------------------------------------------------------------------- + +ARCHITECTURE rtl OF toggler IS + + signal inputDebounced : std_ulogic; + signal inputDelayed, inputChangedTo1 : std_ulogic; + signal toggle_int : std_ulogic; + + COMPONENT debouncer + GENERIC ( + counterBitNb : positive := 18; + invertInput : std_ulogic := '0' + ); + PORT ( + reset : IN std_ulogic ; + clock : IN std_ulogic ; + input : IN std_ulogic ; + debounced : OUT std_ulogic + ); + END COMPONENT; + +BEGIN + ------------------------------------------------------------------------------ + -- Debounce input + useInputDirectly: if counterBitNb = 0 generate + inputDebounced <= input; + end generate useInputDirectly; + + debounceInput: if counterBitNb > 0 generate + I_debouncer : debouncer + GENERIC MAP ( + counterBitNb => counterBitNb, + invertInput => invertInput + ) + PORT MAP ( + reset => reset, + clock => clock, + input => input, + debounced => inputDebounced + ); + end generate debounceInput; + + ------------------------------------------------------------------------------ + -- Find edge on input + delayInput: process(reset, clock) + begin + if reset = '1' then + inputDelayed <= '0'; + elsif rising_edge(clock) then + inputDelayed <= inputDebounced; + end if; + end process delayInput; + + inputChangedTo1 <= '1' when (inputDebounced = '1') and (inputDelayed = '0') + else '0'; + + ------------------------------------------------------------------------------ + -- Toggle output + toggleOutput: process(reset, clock) + begin + if reset = '1' then + toggle_int <= '0'; + elsif rising_edge(clock) then + if inputChangedTo1 = '1' then + toggle_int <= not toggle_int; + end if; + end if; + end process toggleOutput; + + toggle <= toggle_int; + +END ARCHITECTURE rtl; diff --git a/Libs/Common/hds/.hdlsidedata/_blinker_arch.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_blinker_arch.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_blinker_arch.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_blinker_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_blinker_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_blinker_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_commonLib.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_commonLib.vhd._fpf new file mode 100644 index 0000000..2acce3d --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_commonLib.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_87 diff --git a/Libs/Common/hds/.hdlsidedata/_commonLib_body.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_commonLib_body.vhd._fpf new file mode 100644 index 0000000..2acce3d --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_commonLib_body.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_87 diff --git a/Libs/Common/hds/.hdlsidedata/_debounce_rtl.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debounce_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debounce_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Common/hds/.hdlsidedata/_debouncerULogicVector_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debouncerULogicVector_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncerULogicVector_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncer_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debouncer_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncer_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncer_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_debouncer_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncer_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_debouncerulogicvector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_edgeDetector_rtl.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_edgeDetector_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_edgeDetector_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_edgedetector_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_edgedetector_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_edgedetector_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_rotaryToUnsigned_rtl.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_rotaryToUnsigned_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_rotaryToUnsigned_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_rotarytounsigned_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_rotarytounsigned_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_rotarytounsigned_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_spikeFilter_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_spikeFilter_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_spikeFilter_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_spikefilter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_toggler_RTL.vhd._fpf b/Libs/Common/hds/.hdlsidedata/_toggler_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_toggler_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/.hdlsidedata/_toggler_entity.vhg._fpf b/Libs/Common/hds/.hdlsidedata/_toggler_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common/hds/.hdlsidedata/_toggler_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common/hds/_blinker._epf b/Libs/Common/hds/_blinker._epf new file mode 100644 index 0000000..87ea3e1 --- /dev/null +++ b/Libs/Common/hds/_blinker._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom arch +DEFAULT_FILE atom blinker_arch.vhd diff --git a/Libs/Common/hds/_debounce._epf b/Libs/Common/hds/_debounce._epf new file mode 100644 index 0000000..ec8784d --- /dev/null +++ b/Libs/Common/hds/_debounce._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom debounce_rtl.vhd diff --git a/Libs/Common/hds/_debouncer._epf b/Libs/Common/hds/_debouncer._epf new file mode 100644 index 0000000..641b0cc --- /dev/null +++ b/Libs/Common/hds/_debouncer._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom debouncer_RTL.vhd +DEFAULT_ARCHITECTURE atom rtl diff --git a/Libs/Common/hds/_edgedetector._epf b/Libs/Common/hds/_edgedetector._epf new file mode 100755 index 0000000..218e0ce --- /dev/null +++ b/Libs/Common/hds/_edgedetector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom edgeDetector_rtl.vhd diff --git a/Libs/Common/hds/_rotarytounsigned._epf b/Libs/Common/hds/_rotarytounsigned._epf new file mode 100755 index 0000000..7c92a28 --- /dev/null +++ b/Libs/Common/hds/_rotarytounsigned._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom rotaryToUnsigned_rtl.vhd +DEFAULT_ARCHITECTURE atom rtl diff --git a/Libs/Common/hds/_toggler._epf b/Libs/Common/hds/_toggler._epf new file mode 100644 index 0000000..ee14298 --- /dev/null +++ b/Libs/Common/hds/_toggler._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom toggler_RTL.vhd +DEFAULT_ARCHITECTURE atom rtl diff --git a/Libs/Common/hds/blinker/symbol.sb b/Libs/Common/hds/blinker/symbol.sb new file mode 100644 index 0000000..887db7c --- /dev/null +++ b/Libs/Common/hds/blinker/symbol.sb @@ -0,0 +1,1557 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "NUMERIC_STD" +) +(DmPackageRef +library "Common" +unitName "CommonLib" +) +] +libraryRefs [ +"ieee" +"Common" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 5,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +) +uid 108,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 2,0 +) +) +uid 110,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "blink" +t "std_ulogic" +o 1 +suid 3,0 +) +) +uid 112,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 4 +suid 5,0 +) +) +uid 133,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 66,0 +optionalChildren [ +*18 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *19 (MRCItem +litem &1 +pos 4 +dimension 20 +) +uid 68,0 +optionalChildren [ +*20 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 69,0 +) +*21 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 70,0 +) +*22 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 71,0 +) +*23 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 109,0 +) +*24 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 111,0 +) +*25 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 113,0 +) +*26 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 134,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 +) +uid 72,0 +optionalChildren [ +*27 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 73,0 +) +*28 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 74,0 +) +*29 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 75,0 +) +*30 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 76,0 +) +*31 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 77,0 +) +*32 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 78,0 +) +*33 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 79,0 +) +*34 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 80,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 67,0 +vaOverrides [ +] +) +] +) +uid 52,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *35 (LEmptyRow +) +uid 82,0 +optionalChildren [ +*36 (RefLabelRowHdr +) +*37 (TitleRowHdr +) +*38 (FilterRowHdr +) +*39 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*40 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*41 (GroupColHdr +tm "GroupColHdrMgr" +) +*42 (NameColHdr +tm "GenericNameColHdrMgr" +) +*43 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*44 (InitColHdr +tm "GenericValueColHdrMgr" +) +*45 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*46 (EolColHdr +tm "GenericEolColHdrMgr" +) +*47 (LogGeneric +generic (GiElement +name "clockFrequency" +type "positive" +value "106e6" +e "in Hz" +) +uid 131,0 +) +*48 (LogGeneric +generic (GiElement +name "mode" +type "integer" +value "0" +) +uid 165,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 94,0 +optionalChildren [ +*49 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *50 (MRCItem +litem &35 +pos 2 +dimension 20 +) +uid 96,0 +optionalChildren [ +*51 (MRCItem +litem &36 +pos 0 +dimension 20 +uid 97,0 +) +*52 (MRCItem +litem &37 +pos 1 +dimension 23 +uid 98,0 +) +*53 (MRCItem +litem &38 +pos 2 +hidden 1 +dimension 20 +uid 99,0 +) +*54 (MRCItem +litem &47 +pos 0 +dimension 20 +uid 132,0 +) +*55 (MRCItem +litem &48 +pos 1 +dimension 20 +uid 166,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 +) +uid 100,0 +optionalChildren [ +*56 (MRCItem +litem &39 +pos 0 +dimension 20 +uid 101,0 +) +*57 (MRCItem +litem &41 +pos 1 +dimension 50 +uid 102,0 +) +*58 (MRCItem +litem &42 +pos 2 +dimension 100 +uid 103,0 +) +*59 (MRCItem +litem &43 +pos 3 +dimension 100 +uid 104,0 +) +*60 (MRCItem +litem &44 +pos 4 +dimension 50 +uid 105,0 +) +*61 (MRCItem +litem &45 +pos 5 +dimension 50 +uid 106,0 +) +*62 (MRCItem +litem &46 +pos 6 +dimension 80 +uid 107,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 95,0 +vaOverrides [ +] +) +] +) +uid 81,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker/symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker/symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "blinker" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:43:32" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Common" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Common/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "blinker" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker/symbol.sb" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common/hds/blinker/symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "13:43:32" +) +(vvPair +variable "unit" +value "blinker" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 51,0 +optionalChildren [ +*63 (SymbolBody +uid 8,0 +optionalChildren [ +*64 (CptPort +uid 116,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 117,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,9625,15000,10375" +) +tg (CPTG +uid 118,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 119,0 +va (VaSet +) +xt "16000,9500,18100,10500" +st "clock" +blo "16000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 120,0 +va (VaSet +font "courier,8,0" +) +xt "44000,2000,58500,2900" +st "clock : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +) +) +*65 (CptPort +uid 121,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 122,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,7625,15000,8375" +) +tg (CPTG +uid 123,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 124,0 +va (VaSet +) +xt "16000,7500,17200,8500" +st "en" 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+activeModelName "Symbol" +) diff --git a/Libs/Common/hds/debouncer/symbol.sb b/Libs/Common/hds/debouncer/symbol.sb new file mode 100644 index 0000000..b4c91e8 --- /dev/null +++ b/Libs/Common/hds/debouncer/symbol.sb @@ -0,0 +1,1552 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "NUMERIC_STD" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 4,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm 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"25000,18600" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 126,0 +va (VaSet +font "courier,8,0" +) +xt "-9000,13400,6500,14300" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 3,0 +) +) +) +*65 (CptPort +uid 129,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 130,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "23250,11625,24000,12375" +) +tg (CPTG +uid 131,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 132,0 +va (VaSet +font "courier,12,0" +) +xt "25000,11350,28500,12650" +st "pulse" +blo "25000,12350" +tm "CptPortNameMgr" +) +s (Text +uid 398,0 +va (VaSet +font "courier,12,0" +) +xt "25000,12650,25000,12650" +blo "25000,12650" +tm "CptPortTypeMgr" +) +) +dt (MLText +uid 133,0 +va (VaSet +font "courier,8,0" +) +xt "-9000,12500,6500,13400" +st "pulse : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "pulse" +t "std_ulogic" +o 4 +suid 4,0 +) +) +) +*66 (CptPort +uid 399,0 +ps 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11,0 +va (VaSet +) +xt "24300,20400,27900,21400" +st "Common" +blo "24300,21200" +) +second (Text +uid 12,0 +va (VaSet +) +xt "24300,21400,32100,22400" +st "edgeDetector" +blo "24300,22200" +) +) +gi *67 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +) +xt "24000,23400,36600,24400" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +disp 1 +sTC 0 +sF 0 +) +portVis (PortSigDisplay +disp 1 +sTC 0 +sF 0 +) +) +*68 (Grouping +uid 223,0 +optionalChildren [ +*69 (CommentText +uid 225,0 +shape (Rectangle +uid 226,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "25000,48000,42000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 227,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "25200,48000,41400,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*70 (CommentText +uid 228,0 +shape (Rectangle +uid 229,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "42000,44000,46000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 230,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "42200,44000,45800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*71 (CommentText +uid 231,0 +shape (Rectangle +uid 232,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "25000,46000,42000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 233,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "25200,46000,41400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*72 (CommentText +uid 234,0 +shape (Rectangle +uid 235,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "21000,46000,25000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 236,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "21200,46000,24800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*73 (CommentText +uid 237,0 +shape (Rectangle +uid 238,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "42000,45000,62000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 239,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "42200,45200,55400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*74 (CommentText +uid 240,0 +shape (Rectangle +uid 241,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "46000,44000,62000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 242,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "46200,44000,48000,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*75 (CommentText +uid 243,0 +shape (Rectangle +uid 244,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "21000,44000,42000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 245,0 +va (VaSet +fg "32768,0,0" +) +xt "27000,44500,36000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*76 (CommentText +uid 246,0 +shape (Rectangle +uid 247,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "21000,47000,25000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 248,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "21200,47000,24200,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*77 (CommentText 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"14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "32768,32768,32768" +) +packageList *79 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*80 (Text +uid 127,0 +va (VaSet +font "courier,12,1" +) +xt "-11000,0,-2200,1500" +st "Package List" +blo "-11000,1200" +) +*81 (MLText +uid 128,0 +va (VaSet +font "courier,12,0" +) +xt "-11000,1500,10700,4100" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all;" +tm "PackageList" +) +] +) +windowSize "59,4,1688,1058" +viewArea "-12000,-1100,58300,44500" +cachedDiagramExtent "-11000,0,62000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "-11000,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +bg "65280,65280,65280" +lineColor "0,16384,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,16384,32768" +) +xt "200,200,2600,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "courier,10,1" +) +xt "1000,1000,4400,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32768,0" +lineWidth 2 +) +xt "15000,6000,51000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "courier,12,1" +) +xt "30500,14400,35500,15900" +st "" +blo "30500,15600" +) +second (Text +va (VaSet +font "courier,12,1" +) +xt "30500,15900,33900,17400" +st "" +blo "30500,17100" +) +) +gi *82 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *83 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,10,1" +) +xt "-11000,9200,-3600,10400" +st "Declarations" +blo "-11000,10200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,10,1" +) +xt "-11000,10400,-7500,11600" +st "Ports:" +blo "-11000,11400" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,10,1" +) +xt "-11000,16100,-8000,17100" +st "User:" +blo "-11000,16900" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,10,1" +) +xt "-11000,9200,-3200,10400" +st "Internal User:" +blo "-11000,10200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "-9000,17100,-9000,17100" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "-11000,9200,-11000,9200" +tm "SyDeclarativeTextMgr" +) +) +lastUid 429,0 +activeModelName "Symbol" +) diff --git a/Libs/Common/hds/rotary@to@unsigned/symbol.sb b/Libs/Common/hds/rotary@to@unsigned/symbol.sb new file mode 100644 index 0000000..b6c30d8 --- /dev/null +++ b/Libs/Common/hds/rotary@to@unsigned/symbol.sb @@ -0,0 +1,1602 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 10,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +lang 11 +m 1 +decl (Decl +n "number" +t "unsigned" +b "(outputBitNb-1 DOWNTO 0)" +o 3 +suid 1,0 +) +) +uid 158,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "rotary" +t "unsigned" +b "(rotaryBitNb-1 downto 0)" +o 4 +suid 2,0 +) +) +uid 160,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 3,0 +) +) +uid 162,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 9,0 +) +) +uid 174,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 66,0 +optionalChildren [ +*18 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *19 (MRCItem +litem &1 +pos 4 +dimension 20 +) +uid 68,0 +optionalChildren [ +*20 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 69,0 +) +*21 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 70,0 +) +*22 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 71,0 +) +*23 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 159,0 +) +*24 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 161,0 +) +*25 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 163,0 +) +*26 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 175,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +textAngle 90 +) +uid 72,0 +optionalChildren [ +*27 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 73,0 +) +*28 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 74,0 +) +*29 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 75,0 +) +*30 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 76,0 +) +*31 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 77,0 +) +*32 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 78,0 +) +*33 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 79,0 +) +*34 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 80,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 67,0 +vaOverrides [ +] +) +] +) +uid 52,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *35 (LEmptyRow +) +uid 82,0 +optionalChildren [ +*36 (RefLabelRowHdr +) +*37 (TitleRowHdr +) +*38 (FilterRowHdr +) +*39 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*40 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Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *84 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,7800,5400,8800" +st "Declarations" +blo "0,8600" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,8800,2700,9800" +st "Ports:" +blo "0,9600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,13400,2500,14300" +st "User:" +blo "0,14100" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,7800,5800,8800" +st "Internal User:" +blo "0,8600" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,14300,2000,14300" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,7800,0,7800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 302,0 +activeModelName "Symbol" +) diff --git a/Libs/Common_test/hdl/clockGenerator_sim.vhd b/Libs/Common_test/hdl/clockGenerator_sim.vhd new file mode 100644 index 0000000..b2e94be --- /dev/null +++ b/Libs/Common_test/hdl/clockGenerator_sim.vhd @@ -0,0 +1,13 @@ +ARCHITECTURE sim OF clockGenerator IS + + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + +BEGIN + + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9.0/10.0; + +END ARCHITECTURE sim; diff --git a/Libs/Common_test/hdl/commonLib_tb_test.vhd b/Libs/Common_test/hdl/commonLib_tb_test.vhd new file mode 100644 index 0000000..40a1b77 --- /dev/null +++ b/Libs/Common_test/hdl/commonLib_tb_test.vhd @@ -0,0 +1,26 @@ +LIBRARY Common; + USE Common.commonLib.all; +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF commonLib_tb IS + constant maxPowOf2: positive := 10; + constant indent: string(1 to 2) := (others => ' '); +BEGIN + + process + variable value, bitNb: positive; + BEGIN + print("testing function " & '"' & "requiredBitNb" & '"'); + for index in 1 to maxPowOf2 loop + for offset in -1 to 1 loop + value := 2**index + offset; + bitNb := requiredBitNb(value); + print(indent & "requiredBitNb(" & sprintf("%d", value) & ") = " & sprintf("%d", bitNb)); + end loop; + print(""); + end loop; + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/debounce_tester_test.vhd b/Libs/Common_test/hdl/debounce_tester_test.vhd new file mode 100644 index 0000000..2d3eac1 --- /dev/null +++ b/Libs/Common_test/hdl/debounce_tester_test.vhd @@ -0,0 +1,141 @@ +-- +-- VHDL Architecture Common_test.debounce_tester.test +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:30:08 12.01.2024 +-- +-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY std; + USE std.textio.ALL; + +LIBRARY ieee; + USE ieee.std_logic_textio.ALL; + USE ieee.math_real.all; + +LIBRARY Common_test; + USE Common_test.testutils.all; + +ARCHITECTURE test OF debounce_tester IS + + constant clockPeriod : time := 1.0/g_clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + constant DELAY: positive := integer(ceil(((real(g_debounceTime / 1 ps) / 1.0e12) * g_clockFrequency) / real(g_minConsecutiveStateCount))) - 1; + + signal testInfo : string(1 to 40) := (others => ' '); + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + -- startup + testInfo <= pad("Init", testInfo'length); + input <= '0'; + wait until reset = '0'; + wait until clock'event and clock = '1'; + + assert (debounced = not g_activeState) + report "Startup value should be " & to_string(not g_activeState) + severity failure; + assert (debounced = g_activeState) + report "Value OK" + severity note; + + -- transition 0 to 1 + testInfo <= pad("0 to 1", testInfo'length); + input <= '1'; + wait for (g_minConsecutiveStateCount/2) * DELAY * clockPeriod; + assert (debounced = not g_activeState) + report "Value should be " & to_string(not g_activeState) + severity failure; + assert (debounced = g_activeState) + report "Value OK" + severity note; + wait for ((g_minConsecutiveStateCount/2) + 1) * DELAY * clockPeriod; + assert (debounced = g_activeState) + report "Value should be " & to_string(g_activeState) + severity failure; + assert (debounced = not g_activeState) + report "Value OK" + severity note; + wait for 100*clockPeriod; + + -- transition 1 to 0 + testInfo <= pad("1 to 0", testInfo'length); + input <= '0'; + wait for (g_minConsecutiveStateCount/2) * DELAY * clockPeriod; + assert (debounced = g_activeState) + report "Value should be " & to_string(g_activeState) + severity failure; + assert (debounced = not g_activeState) + report "Value OK" + severity note; + wait for ((g_minConsecutiveStateCount/2) + 1) * DELAY * clockPeriod; + assert (debounced = not g_activeState) + report "Value should be " & to_string(not g_activeState) + severity failure; + assert (debounced = g_activeState) + report "Value OK" + severity note; + wait for 100*clockPeriod; + + + -- 0 w. glitches + testInfo <= pad("0 glitches", testInfo'length); + input <= '0', + '1' after (g_minConsecutiveStateCount/4) * DELAY * clockPeriod, + '0' after (g_minConsecutiveStateCount/2) * DELAY * clockPeriod, + '1' after ((g_minConsecutiveStateCount/4)*3) * DELAY * clockPeriod, + '0' after (g_minConsecutiveStateCount) * DELAY * clockPeriod; + wait for 2 * (g_minConsecutiveStateCount) * DELAY * clockPeriod; + assert (debounced = not g_activeState) + report "Value should be " & to_string(not g_activeState) + severity failure; + assert (debounced = g_activeState) + report "Value OK" + severity note; + + testInfo <= pad("Back to 1", testInfo'length); + input <= '1'; + wait for g_minConsecutiveStateCount * DELAY * clockPeriod; + assert (debounced = g_activeState) + report "Value should be " & to_string(g_activeState) + severity failure; + assert (debounced = not g_activeState) + report "Value OK" + severity note; + + -- 1 w. glitches + testInfo <= pad("1 glitches", testInfo'length); + input <= '1', + '0' after (g_minConsecutiveStateCount/4) * DELAY * clockPeriod, + '1' after (g_minConsecutiveStateCount/2) * DELAY * clockPeriod, + '0' after ((g_minConsecutiveStateCount/4)*3) * DELAY * clockPeriod, + '1' after (g_minConsecutiveStateCount) * DELAY * clockPeriod; + wait for 2 * (g_minConsecutiveStateCount) * DELAY * clockPeriod; + assert (debounced = g_activeState) + report "Value should be " & to_string(g_activeState) + severity failure; + assert (debounced = not g_activeState) + report "Value OK" + severity note; + + -- end of simulation + testInfo <= pad("End", testInfo'length); + wait for 10*clockPeriod; + assert false + report "End of simulation" + severity failure; + wait; + end process; + +END ARCHITECTURE test; + diff --git a/Libs/Common_test/hdl/debouncerULogicVector_tester_RTL.vhd b/Libs/Common_test/hdl/debouncerULogicVector_tester_RTL.vhd new file mode 100644 index 0000000..bca8093 --- /dev/null +++ b/Libs/Common_test/hdl/debouncerULogicVector_tester_RTL.vhd @@ -0,0 +1,57 @@ +ARCHITECTURE RTL OF debouncerULogicVector_tester IS + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + + constant longDelay : time := 2**(counterBitNb+1) * clockPeriod; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= (others => '0'); + wait for longDelay; + -- transition 0 to 1 + input(1) <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod, + '1' after 10*clockPeriod; + wait for longDelay; + -- transition to other bit + -- transition 1 to 0 + input(1) <= '0'; + wait for longDelay; + input(2) <= '1'; + wait for longDelay; + -- transition 1 to 0 + input(2) <= '0', + '1' after 1*clockPeriod, + '0' after 3*clockPeriod, + '1' after 5*clockPeriod, + '0' after 6*clockPeriod, + '1' after 8*clockPeriod, + '0' after 10*clockPeriod; + wait for longDelay; + -- short 1 pulse + input(3) <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod; + -- end of simulation + wait; + end process; + +END ARCHITECTURE RTL; diff --git a/Libs/Common_test/hdl/debouncer_tester_test.vhd b/Libs/Common_test/hdl/debouncer_tester_test.vhd new file mode 100644 index 0000000..b319ae6 --- /dev/null +++ b/Libs/Common_test/hdl/debouncer_tester_test.vhd @@ -0,0 +1,49 @@ +ARCHITECTURE test OF debouncer_tester IS + + constant clockFrequency : real := 66.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= '0'; + wait for 10*clockPeriod; + -- transition 0 to 1 + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod, + '1' after 10*clockPeriod; + wait for 50*clockPeriod; + -- transition 1 to 0 + input <= '0', + '1' after 1*clockPeriod, + '0' after 3*clockPeriod, + '1' after 5*clockPeriod, + '0' after 6*clockPeriod, + '1' after 8*clockPeriod, + '0' after 10*clockPeriod; + wait for 50*clockPeriod; + -- short 1 pulse + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod; + -- end of simulation + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/requiredBitNb.txt b/Libs/Common_test/hdl/requiredBitNb.txt new file mode 100644 index 0000000..5015db3 --- /dev/null +++ b/Libs/Common_test/hdl/requiredBitNb.txt @@ -0,0 +1,40 @@ +# testing function "requiredBitNb" +# requiredBitNb(1) = 1 +# requiredBitNb(2) = 2 +# requiredBitNb(3) = 2 +# +# requiredBitNb(3) = 2 +# requiredBitNb(4) = 3 +# requiredBitNb(5) = 3 +# +# requiredBitNb(7) = 3 +# requiredBitNb(8) = 4 +# requiredBitNb(9) = 4 +# +# requiredBitNb(15) = 4 +# requiredBitNb(16) = 5 +# requiredBitNb(17) = 5 +# +# requiredBitNb(31) = 5 +# requiredBitNb(32) = 6 +# requiredBitNb(33) = 6 +# +# requiredBitNb(63) = 6 +# requiredBitNb(64) = 7 +# requiredBitNb(65) = 7 +# +# requiredBitNb(127) = 7 +# requiredBitNb(128) = 8 +# requiredBitNb(129) = 8 +# +# requiredBitNb(255) = 8 +# requiredBitNb(256) = 9 +# requiredBitNb(257) = 9 +# +# requiredBitNb(511) = 9 +# requiredBitNb(512) = 10 +# requiredBitNb(513) = 10 +# +# requiredBitNb(1023) = 10 +# requiredBitNb(1024) = 11 +# requiredBitNb(1025) = 11 \ No newline at end of file diff --git a/Libs/Common_test/hdl/rotaryToUnsigned_tester_test.vhd b/Libs/Common_test/hdl/rotaryToUnsigned_tester_test.vhd new file mode 100644 index 0000000..70a3fbf --- /dev/null +++ b/Libs/Common_test/hdl/rotaryToUnsigned_tester_test.vhd @@ -0,0 +1,47 @@ +ARCHITECTURE test OF rotaryToUnsigned_tester IS + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + + constant stepPeriod : time := 100*clockPeriod; + signal rotary_int : unsigned(rotary'range); + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + turnRotary: process + begin + rotary_int <= (others => '0'); + wait for 10*stepPeriod; + -- count over max value + for index in 1 to 2**outputBitNb+2 loop + rotary_int <= rotary_int + 1; + wait for stepPeriod; + end loop; + -- count down again + for index in 1 to 2**outputBitNb+2 loop + rotary_int <= rotary_int - 1; + wait for stepPeriod; + end loop; + -- end of simulation + wait; + end process turnRotary; + + addGlitches: process + begin + wait on rotary_int; + rotary <= (others => '0'); + wait for clockPeriod; + rotary <= (others => '1'); + wait for clockPeriod; + rotary <= rotary_int; + end process addGlitches; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/spikeFilter_tester_test.vhd b/Libs/Common_test/hdl/spikeFilter_tester_test.vhd new file mode 100644 index 0000000..cd5468f --- /dev/null +++ b/Libs/Common_test/hdl/spikeFilter_tester_test.vhd @@ -0,0 +1,47 @@ +ARCHITECTURE test OF spikeFilter_tester IS + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= '0'; + wait for 10*clockPeriod; + -- loop on pulse width + for pulseWidth in 1 to 10 loop + -- send positive pulses train + for index in 1 to 8 loop + input <= '1'; + wait for pulseWidth * clockPeriod; + input <= '0'; + wait for pulseWidth * clockPeriod; + end loop; + -- set input high + input <= '1'; + wait for 100*clockPeriod; + -- send negative pulses train + for index in 1 to 8 loop + input <= '0'; + wait for pulseWidth * clockPeriod; + input <= '1'; + wait for pulseWidth * clockPeriod; + end loop; + -- set input low + input <= '0'; + wait for 100*clockPeriod; + end loop; + -- end of simulation + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/testUtils_pkg.vhd b/Libs/Common_test/hdl/testUtils_pkg.vhd new file mode 100644 index 0000000..4d275b9 --- /dev/null +++ b/Libs/Common_test/hdl/testUtils_pkg.vhd @@ -0,0 +1,127 @@ +LIBRARY std; + USE std.textio.all; +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +PACKAGE testUtils IS + + --============================================================================ + -- console output + -- + + procedure print(value : string); + + + --============================================================================ + -- string manipulation + -- + + -- conversion to lowercase + function lc(value : string) return string; + procedure lc(value : inout line); + -- conversion to uppercase + function uc(value : string) return string; + procedure uc(value : inout line); + -- expand a string to a given length + function pad( + value : string; + string_length : natural; + fill_char : character := ' '; + right_justify : boolean := false + ) return string; + -- remove separator characters at beginning and end of line + procedure rm_side_separators( + value : inout line; + separators : in string + ); + procedure rm_side_separators( + value : inout line + ); + -- remove multiple occurences of separator characters + procedure trim_line( + value : inout line; + separators : in string + ); + + procedure trim_line( + value : inout line + ); + -- remove all occurences of separator characters + procedure rm_all_separators( + value : inout line; + separators : in string + ); + + procedure rm_all_separators( + value : inout line + ); + -- find and remove first word + procedure read_first( + value : inout line; + separators : in string; + first : out line + ); + + procedure read_first( + value : inout line; + first : out line + ); + -- find and remove last word + procedure read_last( + value : inout line; + separators : in string; + last : out line + ); + + procedure read_last( + value : inout line; + last : out line + ); + + + --============================================================================ + -- formatted string output + -- + -- format codes: + -- code integer real std_logic std_(u)logic_vector (un)signed time + -- b v v v v binary + -- c character + -- d v v v v v decimal + -- e real numbers, with power of 10 exponent + -- f v v fixed point real numbers + -- s string + -- ts v time in seconds + -- tm v time in milliseconds + -- tu v time in microseconds + -- tn v time in nanoseconds + -- tp v time in picoseconds + -- x v v v v hexadecimal + -- X v v v v hexadecimal with upper-case letters + + function sprintf(format : string; value : integer ) return string; + function sprintf(format : string; value : real ) return string; + function sprintf(format : string; value : std_logic ) return string; + function sprintf(format : string; value : std_ulogic_vector) return string; + function sprintf(format : string; value : std_logic_vector ) return string; + function sprintf(format : string; value : unsigned ) return string; + function sprintf(format : string; value : signed ) return string; + function sprintf(format : string; value : time ) return string; + + --============================================================================ + -- formatted string input + -- + subtype nibbleUlogicType is std_ulogic_vector(3 downto 0); + subtype nibbleUnsignedType is unsigned(3 downto 0); + + function sscanf(value : character) return natural; + function sscanf(value : character) return nibbleUlogicType; + function sscanf(value : character) return nibbleUnsignedType; + function sscanf(value : string ) return natural; + function sscanf(value : string ) return unsigned; + function sscanf(value : string ) return std_ulogic_vector; + function sscanf(value : string ) return time; + + procedure sscanf(value : inout line; time_val : out time); + +END testUtils; diff --git a/Libs/Common_test/hdl/testUtils_pkg_body.vhd b/Libs/Common_test/hdl/testUtils_pkg_body.vhd new file mode 100644 index 0000000..88c6205 --- /dev/null +++ b/Libs/Common_test/hdl/testUtils_pkg_body.vhd @@ -0,0 +1,924 @@ +PACKAGE BODY testUtils IS + + --============================================================================ + -- console output + -- + + procedure print(value : string) is + variable my_line : line; + begin + write(my_line, value); + writeLine(output, my_line); + deallocate(my_line); + end print; + + + --============================================================================ + -- string manipulation + -- + + ------------------------------------------------------------------------------ + -- change to lowercase + ------------------------------------------------------------------------------ + procedure lc(value: inout line) is + variable out_line: line; + begin + for index in value'range loop + if (value(index) >= 'A') and (value(index) <= 'Z') then + value(index) := character'val(character'pos(value(index)) + - character'pos('A') + + character'pos('a') + ); + end if; + end loop; + end lc; + + function lc(value: string) return string is + variable out_line: line; + begin + write(out_line, value); + lc(out_line); + return(out_line.all); + end lc; + + ------------------------------------------------------------------------------ + -- change to uppercase + ------------------------------------------------------------------------------ + procedure uc(value: inout line) is + variable out_line: line; + begin + for index in value'range loop + if (value(index) >= 'a') and (value(index) <= 'z') then + value(index) := character'val(character'pos(value(index)) + - character'pos('a') + + character'pos('A') + ); + end if; + end loop; + end uc; + + function uc(value: string) return string is + variable out_line: line; + begin + write(out_line, value); + uc(out_line); + return(out_line.all); + end uc; + + ------------------------------------------------------------------------------ + -- formatted string output: padding and justifying + ------------------------------------------------------------------------------ + function pad( + value : string; + string_length : natural; + fill_char : character := ' '; + right_justify : boolean := false + ) return string is + variable value_line : line; + variable out_line : line; + variable value_length : natural; + variable shift_sign : boolean; + begin + write(value_line, value); + value_length := value_line.all'length; + if string_length = 0 then + write(out_line, value_line.all); + elsif string_length > value_length then + if right_justify then + if (value_line.all(value_line.all'left) <= '-') and not(fill_char = ' ') then + shift_sign := true; + write(out_line, value_line.all(value_line.all'left)); + end if; + for index in 1 to string_length-value_length loop + write(out_line, fill_char); + end loop; + end if; + if shift_sign then + write(out_line, value_line.all(value_line.all'left+1 to value_line.all'right)); + else + write(out_line, value_line.all); + end if; + if not right_justify then + for index in 1 to string_length-value_length loop + write(out_line, fill_char); + end loop; + end if; + elsif string_length < value_length then + write(out_line, '#'); + write(out_line, value_line.all(value_length-string_length+2 to value_length)); + else + write(out_line, value_line.all); + end if; + deallocate(value_line); + return(out_line.all); + end pad; + + ------------------------------------------------------------------------------ + -- remove separator characters at beginning and end of line + ------------------------------------------------------------------------------ + procedure rm_side_separators( + value : inout line; + separators : in string + ) is + variable input_line : line := value; + variable found : boolean := false; + variable position : integer := 0; + begin + -- remove all separators in the beginning + position := -1; + for character_index in input_line'range loop + found := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + found := true; + end if; + end loop; + if found then + position := character_index; + else + exit; + end if; + end loop; + if position > -1 then + input_line := new string'( input_line(position+1 to input_line'right) ); + end if; + + -- remove all separators in the end + position := -1; + for character_index in input_line'reverse_range loop + found := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + found := true; + end if; + end loop; + if found then + position := character_index; + else + exit; + end if; + end loop; + if position > -1 then + input_line := new string'( input_line(input_line'left to position-1) ); + end if; + + value := input_line; + end; + + procedure rm_side_separators(value : inout line) is + begin + rm_side_separators(value, " :" & ht); + end; + + ------------------------------------------------------------------------------ + -- remove multiple occurences of separator characters, keeping one single + ------------------------------------------------------------------------------ + procedure trim_line( + value : inout line; + separators : in string + ) is + variable input_line: line := value; + variable output_line: line := new string'(""); + variable is_separator, was_separator : boolean := false; + begin + rm_side_separators(input_line); + for character_index in input_line'range loop + is_separator := false; + for separator_index in separators'range loop + if input_line.all(character_index) = separators(separator_index) then + is_separator := true; + end if; + end loop; + if not (is_separator and was_separator) then + write(output_line, input_line.all(character_index)); + end if; + was_separator := is_separator; + end loop; + + value := output_line; + end; + + procedure trim_line(value : inout line) is + begin + trim_line(value, " :" & ht); + end; + + ------------------------------------------------------------------------------ + -- remove all occurences of separator characters + ------------------------------------------------------------------------------ + procedure rm_all_separators( + value : inout line; + separators : in string + ) is + variable input_line : line := value; + variable is_separator : boolean := false; + begin + + -- remove separators from beginn and end of the line + -- rm_separator_be(value, separators); + + -- empty output line + value := new string'(""); + + -- find all separator symbols + for character_index in input_line'range loop + is_separator := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + is_separator := true; + end if; + end loop; + if not is_separator then + write(value, input_line.all(character_index)); + end if; + end loop; + + end; + + procedure rm_all_separators(value : inout line) is + begin + rm_all_separators(value, " _." & ht); + end; + + ------------------------------------------------------------------------------ + -- read first "word" out of a line + ------------------------------------------------------------------------------ + procedure read_first( + value : inout line; + separators : in string; + first : out line + ) is + variable input_line: line; + variable position: natural := 0; + begin + input_line := value; + for character_index in input_line.all'reverse_range loop + for separator_index in separators'range loop + if input_line.all(character_index) = separators(separator_index) then + position := character_index; + end if; + end loop; + end loop; + if position > 1 then + first := new string'(input_line.all(input_line'left to position-1)); + value := new string'(input_line(position+1 to input_line'right)); + else + first := new string'(input_line.all); + value := new string'(""); + end if; + end; + + procedure read_first(value : inout line; first : out line) is + begin + read_first(value, " :" & ht, first); + end; + + ------------------------------------------------------------------------------ + -- read last "word" out of a line + ------------------------------------------------------------------------------ + procedure read_last( + value : inout line; + separators : in string; + last : out line + ) is + variable input_line: line := value; + variable position: natural := 0; + begin + for character_index in input_line'range loop + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + position := character_index; + end if; + end loop; + end loop; + if position <= input_line'right and + position > 0 then + value := new string'(input_line(input_line'left to position-1)); + last := new string'(input_line(position+1 to input_line'right)); + else + last := new string'(input_line.all); + end if; + end; + + procedure read_last(value : inout line; last : out line) is + begin + read_last(value, " :" & ht, last); + end; + + + --============================================================================ + -- formatted string output, internal functions + -- + + ------------------------------------------------------------------------------ + -- get format specification + ------------------------------------------------------------------------------ + procedure get_format_items( + format : string; + right_justify : out boolean; + add_sign : out boolean; + fill_char : out character; + total_length : out natural; + point_precision : out natural; + format_type : inout line + ) is + variable find_sign : boolean := false; + variable find_padding : boolean := false; + variable find_length : boolean := false; + variable find_precision : boolean := false; + variable find_type : boolean := false; + variable right_justify_int : boolean := true; + variable total_length_int : natural := 0; + variable point_precision_int : natural := 0; + begin + add_sign := false; + fill_char := ' '; + for index in 1 to format'length loop + if find_type then + write(format_type, format(index)); + end if; + if find_precision then + if (format(index) >= '0') and (format(index) <= '9') then + point_precision_int := 10*point_precision_int + character'pos(format(index)) - character'pos('0'); + if format(index+1) >= 'A' then + find_precision := false; + find_type := true; + end if; + end if; + end if; + if find_length then + if (format(index) >= '0') and (format(index) <= '9') then + total_length_int := 10*total_length_int + character'pos(format(index)) - character'pos('0'); + end if; + if format(index) = '.' then + find_length := false; + find_precision := true; + elsif format(index+1) >= 'A' then + find_length := false; + find_type := true; + end if; + end if; + if find_padding then + if format(index) = '0' then + if right_justify_int then + fill_char := '0'; + end if; + end if; + find_padding := false; + if format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + if find_sign then + if format(index) = '-' then + right_justify_int := false; + end if; + if format(index) = '+' then + add_sign := true; + end if; + find_sign := false; + if format(index+1) <= '-' then + find_sign := true; + elsif format(index+1) = '0' then + find_padding := true; + elsif format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + if format(index) = '%' then + if format(index+1) <= '-' then + find_sign := true; + elsif format(index+1) = '0' then + find_padding := true; + elsif format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + end loop; + right_justify := right_justify_int; + total_length := total_length_int; + point_precision := point_precision_int; + end get_format_items; + + + ------------------------------------------------------------------------------ + -- formatted string output: converting std_ulogic to character + ------------------------------------------------------------------------------ + function to_character(value: std_ulogic) return character is + variable out_value: character; + begin + case value is + when 'U' => out_value := 'U'; + when 'X' => out_value := 'X'; + when '0' => out_value := '0'; + when '1' => out_value := '1'; + when 'Z' => out_value := 'Z'; + when 'W' => out_value := 'W'; + when 'L' => out_value := 'L'; + when 'H' => out_value := 'H'; + when '-' => out_value := '-'; + end case; + return(out_value); + end to_character; + + ------------------------------------------------------------------------------ + -- formatted string output: binary integer + ------------------------------------------------------------------------------ + function sprintf_b(value: std_ulogic_vector) return string is + variable out_line : line; + begin + for index in value'range loop + write(out_line, to_character(value(index))); + end loop; + return(out_line.all); + end sprintf_b; + + ------------------------------------------------------------------------------ + -- formatted string output: decimal integer + ------------------------------------------------------------------------------ + function sprintf_d( + right_justify : boolean; + add_sign : boolean; + fill_char : character; + string_length : natural; + value : integer + ) return string is + variable value_line : line; + begin + if add_sign and (value >= 0) then + write(value_line, '+'); + end if; + write(value_line, value); + if string_length = 0 then + return(value_line.all); + else + return(pad(value_line.all, string_length, fill_char, right_justify)); + end if; + end sprintf_d; + + ------------------------------------------------------------------------------ + -- formatted string output: fixed point real + ------------------------------------------------------------------------------ + function sprintf_f( + right_justify : boolean; + add_sign : boolean; + fill_char : character; + string_length : natural; + point_precision : natural; + value : real + ) return string is + variable point_precision_int : natural; + variable integer_part : integer; + variable decimal_part : natural; + variable value_line : line; + begin + if point_precision = 0 then + point_precision_int := 6; + else + point_precision_int := point_precision; + end if; + if value >= 0.0 then + integer_part := integer(value-0.5); + else + integer_part := - integer(-value-0.5); + end if; + decimal_part := abs(integer((value-real(integer_part))*(10.0**point_precision_int))); + if add_sign and (value >= 0.0) then + write(value_line, '+'); + end if; + write(value_line, integer_part); + write(value_line, '.'); + write(value_line, sprintf_d(true, false, '0', point_precision_int, decimal_part)); + if string_length = 0 then + return(value_line.all); + else + return(pad(value_line.all, string_length, fill_char, right_justify)); + end if; + end sprintf_f; + + ------------------------------------------------------------------------------ + -- formatted string output: hexadecimal integer + ------------------------------------------------------------------------------ + function sprintf_X( + extend_unsigned : boolean; + value : std_ulogic_vector + ) return string is + variable bit_count : positive; + variable value_line : line; + variable out_line : line; + variable nibble: string(1 to 4); + begin + bit_count := value'length; + while (bit_count mod 4) /= 0 loop + if extend_unsigned then + write(value_line, to_character('0')); + else + write(value_line, to_character(value(value'high))); + end if; + bit_count := bit_count + 1; + end loop; + write(value_line, sprintf_b(value)); + for index in value_line.all'range loop + if (index mod 4) = 0 then + nibble := value_line.all(index-3 to index); + case nibble is + when "0000" => write(out_line, 0); + when "0001" => write(out_line, 1); + when "0010" => write(out_line, 2); + when "0011" => write(out_line, 3); + when "0100" => write(out_line, 4); + when "0101" => write(out_line, 5); + when "0110" => write(out_line, 6); + when "0111" => write(out_line, 7); + when "1000" => write(out_line, 8); + when "1001" => write(out_line, 9); + when "1010" => write(out_line, 'A'); + when "1011" => write(out_line, 'B'); + when "1100" => write(out_line, 'C'); + when "1101" => write(out_line, 'D'); + when "1110" => write(out_line, 'E'); + when "1111" => write(out_line, 'F'); + when others => write(out_line, 'X'); + end case; + end if; + end loop; + return(out_line.all); + end sprintf_X; + + + --============================================================================ + -- formatted string output, interface functions + -- + + ------------------------------------------------------------------------------ + -- integer + ------------------------------------------------------------------------------ + function sprintf(format : string; value : integer) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if format_type.all = "b" then + if string_length = 0 then + string_length := 8; + end if; + return(sprintf_b(std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0)))); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, string_length, value)); + elsif format_type.all = "f" then + return(sprintf_f(right_justify, add_sign, fill_char, + string_length, point_precision, real(value))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if string_length = 0 then + string_length := 8; + end if; + string_length := 4*string_length; + if format_type.all = "X" then + return(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0)))); + else + return(lc(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0))))); + end if; + else + return("Unhandled format type: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- real + ------------------------------------------------------------------------------ + function sprintf(format : string; value : real) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "d") or (point_precision = 0) then + return(sprintf_d(right_justify, add_sign, fill_char, + string_length, integer(value))); + elsif format_type.all = "f" then + return(sprintf_f(right_justify, add_sign, fill_char, + string_length, point_precision, value)); + else + return("Unhandled format type: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_logic + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_logic) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + variable logic_vector: std_logic_vector(1 to 1); + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + logic_vector(1) := value; + return(sprintf(format, std_ulogic_vector(logic_vector))); + else + return("Not a std_logic format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_ulogic_vector + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_ulogic_vector) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable bit_string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + bit_string_length, point_precision, format_type); + if format_type.all = "b" then + return(pad(sprintf_b(value), bit_string_length, fill_char, right_justify)); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(unsigned(value)))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if format_type.all = "X" then + return(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify)); + else + return(lc(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify))); + end if; + else + return("Not a std_ulogic_vector format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_logic_vector + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_logic_vector) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + return(sprintf(format, std_ulogic_vector(value))); + else + return("Not a std_logic_vector format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- unsigned + ------------------------------------------------------------------------------ + function sprintf(format : string; value : unsigned) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + return(sprintf(format, std_ulogic_vector(value))); + else + return("Not an unsigned format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- signed + ------------------------------------------------------------------------------ + function sprintf(format : string; value : signed) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable bit_string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + bit_string_length, point_precision, format_type); + if (fill_char = '0') and (value(value'left) = '1') then + fill_char := '1'; + end if; + if format_type.all = "b" then + return(pad(sprintf_b(std_ulogic_vector(value)), bit_string_length, fill_char, right_justify)); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(signed(value)))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if fill_char = '1' then + fill_char := 'F'; + end if; + if format_type.all = "X" then + return(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify)); + else + return(lc(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify))); + end if; + else + return("Not a signed format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- time + ------------------------------------------------------------------------------ + function sprintf(format : string; value : time) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + variable scaling : real; + variable base_time : time; + variable unit : string(1 to 3); + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if format_type.all(format_type.all'left) = 't' then + scaling := 10.0**point_precision; + if format_type.all = "tp" then + base_time := 1 ps; + unit := " ps"; + elsif format_type.all = "tn" then + base_time := 1 ns; + unit := " ns"; + elsif format_type.all = "tu" then + base_time := 1 us; + unit := " us"; + elsif format_type.all = "tm" then + base_time := 1 ms; + unit := " ms"; + elsif format_type.all = "ts" then + base_time := 1 sec; + unit := " s."; + else + return("Undefined time format: '" & format_type.all & "'"); + end if; + if point_precision = 0 then + return(sprintf_d(right_justify, add_sign, fill_char, + string_length, value/base_time) & unit); + else + return(sprintf_f(right_justify, add_sign, fill_char, string_length, + point_precision, real(scaling*value/base_time)/scaling) & unit); + end if; + else + return("Not a time format: '" & format_type.all & "'"); + end if; + end sprintf; + + + --============================================================================ + -- formatted string input + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- read a nibble out of a character + ------------------------------------------------------------------------------ + function sscanf(value : character) return natural is + begin + if (value >= '0') and (value <= '9') then + return(character'pos(value) - character'pos('0')); + elsif (value >= 'a') and (value <= 'f') then + return(character'pos(value) - character'pos('a') + 10); + elsif (value >= 'A') and (value <= 'F') then + return(character'pos(value) - character'pos('A') + 10); + else + return(0); + end if; + end sscanf; + + function sscanf(value : character) return nibbleUnsignedType is + begin + return(to_unsigned(sscanf(value), nibbleUnsignedType'length)); + end sscanf; + + function sscanf(value : character) return nibbleUlogicType is + variable unsigned_value : nibbleUnsignedType; + begin + unsigned_value := sscanf(value); + return(std_ulogic_vector(unsigned_value)); + end sscanf; + + ------------------------------------------------------------------------------ + -- read an binary word out of a string + ------------------------------------------------------------------------------ + function sscanf(value : string) return natural is + variable integer_value : natural; + begin + integer_value := 0; + for index in value'left to value'right loop + integer_value := integer_value*16 + sscanf(value(index)); + end loop; + return(integer_value); + end; + + function sscanf(value : string) return unsigned is + variable unsigned_value : unsigned(4*value'length-1 downto 0); + begin + unsigned_value := to_unsigned(0,unsigned_value'length); + for index in value'left to value'right loop + unsigned_value := shift_left(unsigned_value,4) + to_unsigned(sscanf(value(index)),4); + end loop; + return(unsigned_value); + end; + + function sscanf(value : string) return std_ulogic_vector is + variable unsigned_value : unsigned(4*value'length-1 downto 0); + begin + unsigned_value := sscanf(value); + return(std_ulogic_vector(unsigned_value)); + end; + + ------------------------------------------------------------------------------ + -- read time from a string + -- time can be formated as follows: + -- "1ps" or "1 ps" or " 1 ps " or " 1ps" + -- possible time units are: hr, min, sec, ms, us, ns, ps, fs + ------------------------------------------------------------------------------ + procedure sscanf( + value : inout line; + time_val : out time + ) is + variable time_line : line := value; + variable time_base : string(1 to 3); + variable time_value : integer; + variable time_int : time; + begin + -- remove all spaces and tabs + rm_all_separators(time_line); + + -- strip time base (3 last characters) + time_base := time_line(time_line'right-2 to time_line'right); + + -- separate time value and base + if time_base(2 to 3) = "hr" then + time_int := 1 hr; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base = "min" then + time_int := 1 min; + time_value := integer'value(time_line(time_line'left to time_line'right -3)); + elsif time_base = "sec" then + time_int := 1 sec; + time_value := integer'value(time_line(time_line'left to time_line'right -3)); + elsif time_base(2 to 3) = "ms" then + time_int := 1 ms; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "us" then + time_int := 1 us; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "ns" then + time_int := 1 ns; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "ps" then + time_int := 1 ps; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "fs" then + time_int := 1 fs; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + else + time_int := 0 ps; + time_value := 1; + end if; + + -- build time from value and base + time_val := time_int * time_value; + + end; + + function sscanf(value : string) return time is + variable value_line : line; + variable time_val : time; + begin + value_line := new string'(value); + sscanf(value_line, time_val); + return(time_val); + end; + +END testUtils; diff --git a/Libs/Common_test/hdl/testUtils_tb_test.vhd b/Libs/Common_test/hdl/testUtils_tb_test.vhd new file mode 100644 index 0000000..960d138 --- /dev/null +++ b/Libs/Common_test/hdl/testUtils_tb_test.vhd @@ -0,0 +1,102 @@ +LIBRARY std; + USE std.textio.all; +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF testUtils_tb IS +BEGIN + + process + variable test_line, result_line : LINE; + begin + + print("Integers, right justified"); + print(" |" & sprintf("%6d", 12) & "| 12|"); + print(" |" & sprintf("%06d", 12) & "|000012|"); + print(" |" & sprintf("%+6d", 12) & "| +12|"); + print(" |" & sprintf("%+06d", 12) & "|+00012|"); + print(" |" & sprintf("%6d", -12) & "| -12|"); + print(" |" & sprintf("%06d", -12) & "|-00012|"); + print("Integers, left justified"); + print(" |" & sprintf("%-6d", 12) & "|12 |"); + print(" |" & sprintf("%-06d", 12) & "|12 |"); + print(" |" & sprintf("%-+6d", 12) & "|+12 |"); + print(" |" & sprintf("%-+06d", 12) & "|+12 |"); + print(" |" & sprintf("%-6d", -12) & "|-12 |"); + print(" |" & sprintf("%-06d", -12) & "|-12 |"); + print("Integers, others"); + print(" |" & sprintf("%d", 12) & "|12|"); + print(" |" & sprintf("%6tu", 12) & "|"); + print(" |" & sprintf("%6d", 123456) & "|123456|"); + print(" |" & sprintf("%6d", 12345678) & "|#45678|"); + print(" |" & sprintf("%f", 12) & "|12.000000|"); + print(" |" & sprintf("%10f", 12) & "| 12.000000|"); + print(" |" & sprintf("%8.3f", 12) & "| 12.000|"); + print(" |" & sprintf("%b", 12) & "|00001100|"); + print(" |" & sprintf("%4b", 12) & "|1100|"); + print(" |" & sprintf("%6b", 12) & "|001100|"); + print(" |" & sprintf("%X", 12) & "|0000000C|"); + print(" |" & sprintf("%4x", 12) & "|000c|"); + print(" |" & sprintf("%2X", 12) & "|0C|"); + + print(cr & "Reals, integer rounding"); + print(" |" & sprintf("%6d", 1.3) & "| 1|"); + print(" |" & sprintf("%6d", 1.5) & "| 2|"); + print(" |" & sprintf("%6d", 1.7) & "| 2|"); + print("Reals, right justified"); + print(" |" & sprintf("%8.3f", 1.03) & "| 1.030|"); + print(" |" & sprintf("%8.3f", 1.07) & "| 1.070|"); + print(" |" & sprintf("%08.3f", 1.03) & "|0001.030|"); + print(" |" & sprintf("%+08.3f", 1.03) & "|+001.030|"); + print(" |" & sprintf("%8.3f", -1.03) & "| -1.030|"); + print(" |" & sprintf("%8.3f", -1.07) & "| -1.070|"); + print("Reals, left justified"); + print(" |" & sprintf("%-8.3f", 1.3) & "|1.300 |"); + print(" |" & sprintf("%-8.3f", 1.7) & "|1.700 |"); + print(" |" & sprintf("%-08.3f", 1.3) & "|1.300 |"); + print(" |" & sprintf("%-+08.3f", 1.3) & "|+1.300 |"); + print(" |" & sprintf("%-8.3f", -1.3) & "|-1.300 |"); + print(" |" & sprintf("%-8.3f", -1.7) & "|-1.700 |"); + + print(cr & "Logic values"); + print(" |" & sprintf("%b", '0') & "|0|"); + print(" |" & sprintf("%3b", '1') & "| 1|"); + print(" |" & sprintf("%-3d", '0') & "|0 |"); + print(" |" & sprintf("%3X", '1') & "| 1|"); + + print(cr & "Logic vectors, binary"); + print(" |" & sprintf("%b", std_ulogic_vector'("1100")) & "|1100|"); + print(" |" & sprintf("%3b", std_logic_vector'("1100")) & "|#00|"); + print(" |" & sprintf("%4b", unsigned'("1100")) & "|1100|"); + print(" |" & sprintf("%8b", signed'("1100")) & "| 1100|"); + print(" |" & sprintf("%-8b", signed'("1100")) & "|1100 |"); + print(" |" & sprintf("%08b", unsigned'("1100")) & "|00001100|"); + print(" |" & sprintf("%08b", signed'("1100")) & "|11111100|"); + print("Logic vectors, hexadecimal"); + print(" |" & sprintf("%X", std_ulogic_vector'("1100101011111110")) & "|CAFE|"); + print(" |" & sprintf("%3X", std_logic_vector'("1100101011111110")) & "|#FE|"); + print(" |" & sprintf("%4x", unsigned'("1100101011111110")) & "|cafe|"); + print(" |" & sprintf("%8X", signed'("1100101011111110")) & "| CAFE|"); + print(" |" & sprintf("%02X", unsigned'("1100")) & "|0C|"); + print(" |" & sprintf("%02X", signed'("1100")) & "|FC|"); + print("Logic vectors, decimal"); + print(" |" & sprintf("%d", std_ulogic_vector'("1100")) & "|12|"); + print(" |" & sprintf("%d", unsigned'("1100")) & "|12|"); + print(" |" & sprintf("%d", signed'("1100")) & "|-4|"); + print("Logic vectors, others"); + print(" |" & sprintf("%8tu", std_ulogic_vector'("1100")) & "|"); + + print(cr & "Time"); + print(" |" & sprintf("%9tu", 1.3 us) & "| 1 us|"); + print(" |" & sprintf("%9.3tu", 1.3 us) & "| 1.300 us|"); + print(" |" & sprintf("%10tu", 1.3 us) & "| 1 us|"); + + print(cr & "Lines"); + test_line := new string'("Hello brave new world!"); + read_first(test_line, result_line); + print(" |" & result_line.all & "¦"& test_line.all & "|Hello¦brave new world!|"); + + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hdl/toggler_tester_test.vhd b/Libs/Common_test/hdl/toggler_tester_test.vhd new file mode 100644 index 0000000..ba76bc0 --- /dev/null +++ b/Libs/Common_test/hdl/toggler_tester_test.vhd @@ -0,0 +1,56 @@ +ARCHITECTURE test OF toggler_tester IS + + constant clockFrequency : real := 66.0E6; + constant clockPeriod : time := 1.0/clockFrequency * 1 sec; + signal clock_int : std_ulogic := '1'; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 3*clockPeriod; + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- input signal + process + begin + input <= '0'; + wait for 10*clockPeriod; + -- transition 0 to 1 + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod, + '1' after 10*clockPeriod; + wait for 50*clockPeriod; + -- transition 1 to 0 + input <= '0', + '1' after 1*clockPeriod, + '0' after 3*clockPeriod, + '1' after 5*clockPeriod, + '0' after 6*clockPeriod, + '1' after 8*clockPeriod, + '0' after 10*clockPeriod; + wait for 50*clockPeriod; + -- short 1 pulse + input <= '1', + '0' after 1*clockPeriod, + '1' after 3*clockPeriod, + '0' after 5*clockPeriod, + '1' after 6*clockPeriod, + '0' after 8*clockPeriod; + wait for 50*clockPeriod; + -- further toggle commands + input <= '1', '0' after clockPeriod; + wait for 50*clockPeriod; + input <= '1', '0' after clockPeriod; + wait for 50*clockPeriod; + -- short 1 pulse + -- end of simulation + wait; + end process; + +END ARCHITECTURE test; diff --git a/Libs/Common_test/hds/.hdlsidedata/_clockGenerator_sim.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_clockGenerator_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_clockGenerator_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_commonLib_tb_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_commonLib_tb_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_commonLib_tb_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_debounce_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_debounce_tester_test.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_debounce_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Common_test/hds/.hdlsidedata/_debouncerULogicVector_tester_RTL.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_debouncerULogicVector_tester_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_debouncerULogicVector_tester_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_debouncer_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_debouncer_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_debouncer_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotaryToUnsigned_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotaryToUnsigned_tester_test.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotaryToUnsigned_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_entity.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_struct.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tb_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tester_entity.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tester_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_rotarytounsigned_tester_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_spikeFilter_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_spikeFilter_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_spikeFilter_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg.vhd._fpf new file mode 100644 index 0000000..b606e20 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2002 diff --git a/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg_body.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg_body.vhd._fpf new file mode 100644 index 0000000..b606e20 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_testUtils_pkg_body.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2002 diff --git a/Libs/Common_test/hds/.hdlsidedata/_testUtils_tb_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_testUtils_tb_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_testUtils_tb_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/.hdlsidedata/_toggler_tester_test.vhd._fpf b/Libs/Common_test/hds/.hdlsidedata/_toggler_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Common_test/hds/.hdlsidedata/_toggler_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Common_test/hds/_clockgenerator._epf b/Libs/Common_test/hds/_clockgenerator._epf new file mode 100644 index 0000000..8b8ac62 --- /dev/null +++ b/Libs/Common_test/hds/_clockgenerator._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom clockGenerator_sim.vhd +DEFAULT_ARCHITECTURE atom sim diff --git a/Libs/Common_test/hds/_commonlib_tb._epf b/Libs/Common_test/hds/_commonlib_tb._epf new file mode 100644 index 0000000..092da9c --- /dev/null +++ b/Libs/Common_test/hds/_commonlib_tb._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 1 +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom commonLib_tb_test.vhd diff --git a/Libs/Common_test/hds/_debounce_tb._epf b/Libs/Common_test/hds/_debounce_tb._epf new file mode 100644 index 0000000..7920295 --- /dev/null +++ b/Libs/Common_test/hds/_debounce_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom debounce_tb/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_debounce_tester._epf b/Libs/Common_test/hds/_debounce_tester._epf new file mode 100644 index 0000000..456e900 --- /dev/null +++ b/Libs/Common_test/hds/_debounce_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom debounce_tester_test.vhd diff --git a/Libs/Common_test/hds/_debouncer_tb._epf b/Libs/Common_test/hds/_debouncer_tb._epf new file mode 100644 index 0000000..1c7f3f7 --- /dev/null +++ b/Libs/Common_test/hds/_debouncer_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom debouncer_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_debouncer_tester._epf b/Libs/Common_test/hds/_debouncer_tester._epf new file mode 100644 index 0000000..967ba8a --- /dev/null +++ b/Libs/Common_test/hds/_debouncer_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom debouncer_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Common_test/hds/_debouncerulogicvector_tb._epf b/Libs/Common_test/hds/_debouncerulogicvector_tb._epf new file mode 100644 index 0000000..2101ec7 --- /dev/null +++ b/Libs/Common_test/hds/_debouncerulogicvector_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom debouncer@u@logic@vector_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_debouncerulogicvector_tester._epf b/Libs/Common_test/hds/_debouncerulogicvector_tester._epf new file mode 100644 index 0000000..89828c8 --- /dev/null +++ b/Libs/Common_test/hds/_debouncerulogicvector_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom debouncerULogicVector_tester_RTL.vhd diff --git a/Libs/Common_test/hds/_rotarytounsigned_tb._epf b/Libs/Common_test/hds/_rotarytounsigned_tb._epf new file mode 100755 index 0000000..2036a2a --- /dev/null +++ b/Libs/Common_test/hds/_rotarytounsigned_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom rotary@to@unsigned_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_rotarytounsigned_tester._epf b/Libs/Common_test/hds/_rotarytounsigned_tester._epf new file mode 100755 index 0000000..f758d03 --- /dev/null +++ b/Libs/Common_test/hds/_rotarytounsigned_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom rotaryToUnsigned_tester_test.vhd diff --git a/Libs/Common_test/hds/_spikefilter_tb._epf b/Libs/Common_test/hds/_spikefilter_tb._epf new file mode 100644 index 0000000..5050211 --- /dev/null +++ b/Libs/Common_test/hds/_spikefilter_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom spike@filter_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_testutils_tb._epf b/Libs/Common_test/hds/_testutils_tb._epf new file mode 100644 index 0000000..40137e1 --- /dev/null +++ b/Libs/Common_test/hds/_testutils_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom testUtils_tb_test.vhd +DEFAULT_ARCHITECTURE atom test +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_toggler_tb._epf b/Libs/Common_test/hds/_toggler_tb._epf new file mode 100644 index 0000000..94877cb --- /dev/null +++ b/Libs/Common_test/hds/_toggler_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom toggler_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Common_test/hds/_toggler_tester._epf b/Libs/Common_test/hds/_toggler_tester._epf new file mode 100644 index 0000000..17d8815 --- /dev/null +++ b/Libs/Common_test/hds/_toggler_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom toggler_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Common_test/hds/clock@generator/symbol.sb b/Libs/Common_test/hds/clock@generator/symbol.sb new file mode 100644 index 0000000..6c2577f --- /dev/null +++ b/Libs/Common_test/hds/clock@generator/symbol.sb @@ -0,0 +1,1499 @@ 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"/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Common_test/hds/clockGenerator" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "clockGenerator" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:43:51" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) 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"$SCRATCH_DIR/Libraries/Common_test/work" +) +(vvPair +variable "mm" +value "01" +) +(vvPair +variable "module_name" +value "debounce_tester" +) +(vvPair +variable "month" +value "janv." +) +(vvPair +variable "month_long" +value "janvier" +) +(vvPair +variable "p" +value "C:\\dev\\DiD\\eda-libs\\Prefs\\..\\Common_test\\hds\\debounce_tester\\interface" +) +(vvPair +variable "p_logical" +value "C:\\dev\\DiD\\eda-libs\\Prefs\\..\\Common_test\\hds\\debounce_tester\\interface" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "" +) +(vvPair +variable "this_file" +value "interface" +) +(vvPair +variable "this_file_logical" +value "interface" +) +(vvPair +variable "time" +value "08:30:58" +) +(vvPair +variable "unit" +value "debounce_tester" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" 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std_ulogic ;" +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "input" +t "std_ulogic" +o 1 +suid 19,0 +) +) +) +*71 (CptPort +uid 404,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 405,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "19625,5250,20375,6000" +) +tg (CPTG +uid 406,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 407,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "19300,7000,20700,11100" +st "reset" +ju 2 +blo "20500,7000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 408,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4800,60500,5600" +st "reset : OUT std_ulogic " +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 20,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,66000,16000" +) +oxt "15000,6000,25000,16000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first 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(Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *88 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,0,49400,1200" +st "Declarations" +blo "42000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,1200,45700,2400" +st "Ports:" +blo "42000,2200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,5600,45200,6800" +st "User:" +blo "42000,6600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,50200,1200" +st "Internal User:" +blo "42000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6800,44000,6800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 439,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/Common_test/hds/debouncer@u@logic@vector_tb/struct.bd b/Libs/Common_test/hds/debouncer@u@logic@vector_tb/struct.bd new file mode 100644 index 0000000..6cd630a --- /dev/null +++ b/Libs/Common_test/hds/debouncer@u@logic@vector_tb/struct.bd @@ -0,0 +1,2771 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_tb" +duLibraryName "Common_test" +duName "debouncerULogicVector_tester" +elements [ +(GiElement +name "inputBitNb" +type "positive" +value "inputBitNb" +) +(GiElement +name "counterBitNb" +type "positive" +value "counterBitNb" +) +] +mwi 0 +uid 377,0 +) +(Instance +name "I_filt" +duLibraryName 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+) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *80 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "42000,5600,44500,6500" +st "User:" +blo "42000,6300" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "44000,6500,44000,6500" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 311,0 +activeModelName "Symbol:CDM" +) diff --git a/Libs/Common_test/sim/debounce.do b/Libs/Common_test/sim/debounce.do new file mode 100644 index 0000000..bf5008c --- /dev/null +++ b/Libs/Common_test/sim/debounce.do @@ -0,0 +1,32 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {Clock and Reset} +add wave -noupdate -color Gray60 /debounce_tb/I_tb/testInfo +add wave -noupdate -color Gray50 /debounce_tb/clock +add wave -noupdate -color Gray50 /debounce_tb/reset +add wave -noupdate -divider Input +add wave -noupdate -color {Dark Orchid} /debounce_tb/input +add wave -noupdate -radix unsigned /debounce_tb/I_debouncer/DELAY +add wave -noupdate -radix unsigned /debounce_tb/I_debouncer/lvec_count +add wave -noupdate -radix binary -childformat {{/debounce_tb/I_debouncer/lvec_sample(9) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(8) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(7) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(6) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(5) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(4) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(3) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(2) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(1) -radix binary} {/debounce_tb/I_debouncer/lvec_sample(0) -radix binary}} -subitemconfig {/debounce_tb/I_debouncer/lvec_sample(9) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(8) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(7) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(6) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(5) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(4) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(3) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(2) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(1) {-radix binary} /debounce_tb/I_debouncer/lvec_sample(0) {-radix binary}} /debounce_tb/I_debouncer/lvec_sample +add wave -noupdate /debounce_tb/I_debouncer/lsig_samplePulse +add wave -noupdate -divider {Debonced input} +add wave -noupdate -color Gold /debounce_tb/debounced +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {59062638 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 265 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {86730947 ps} diff --git a/Libs/Common_test/sim/debouncerULogicVector.do b/Libs/Common_test/sim/debouncerULogicVector.do new file mode 100644 index 0000000..dc4bdbd --- /dev/null +++ b/Libs/Common_test/sim/debouncerULogicVector.do @@ -0,0 +1,24 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /debouncerulogicvector_tb/reset +add wave -noupdate /debouncerulogicvector_tb/clock +add wave -noupdate -expand /debouncerulogicvector_tb/input +add wave -noupdate -format Analog-Step -height 30 -max 15.0 -radix unsigned /debouncerulogicvector_tb/i_filt/debouncecounter +add wave -noupdate -expand /debouncerulogicvector_tb/debounced +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {8842679128 ps} 0} +configure wave -namecolwidth 285 +configure wave -valuecolwidth 42 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {2100 ns} diff --git a/Libs/Common_test/sim/rotaryToUnsigned.do b/Libs/Common_test/sim/rotaryToUnsigned.do new file mode 100644 index 0000000..36ec08a --- /dev/null +++ b/Libs/Common_test/sim/rotaryToUnsigned.do @@ -0,0 +1,26 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /rotarytounsigned_tb/reset +add wave -noupdate /rotarytounsigned_tb/clock +add wave -noupdate -format Analog-Step -height 50 -max 14.999999999999998 -radix unsigned -radixshowbase 0 /rotarytounsigned_tb/rotary +add wave -noupdate /rotarytounsigned_tb/I_DUT/glitchDelayCounter +add wave -noupdate -format Analog-Step -height 50 -max 14.999999999999998 -radix unsigned -childformat {{/rotarytounsigned_tb/I_DUT/rotaryStable(3) -radix unsigned} {/rotarytounsigned_tb/I_DUT/rotaryStable(2) -radix unsigned} {/rotarytounsigned_tb/I_DUT/rotaryStable(1) -radix unsigned} {/rotarytounsigned_tb/I_DUT/rotaryStable(0) -radix unsigned}} -radixshowbase 0 -subitemconfig {/rotarytounsigned_tb/I_DUT/rotaryStable(3) {-height 17 -radix unsigned -radixshowbase 0} /rotarytounsigned_tb/I_DUT/rotaryStable(2) {-height 17 -radix unsigned -radixshowbase 0} /rotarytounsigned_tb/I_DUT/rotaryStable(1) {-height 17 -radix unsigned -radixshowbase 0} /rotarytounsigned_tb/I_DUT/rotaryStable(0) {-height 17 -radix unsigned -radixshowbase 0}} /rotarytounsigned_tb/I_DUT/rotaryStable +add wave -noupdate -format Analog-Step -height 200 -max 63.0 -radix unsigned -radixshowbase 0 /rotarytounsigned_tb/number +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 243 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {210 us} diff --git a/Libs/Common_test/sim/spikeFilter.do b/Libs/Common_test/sim/spikeFilter.do new file mode 100644 index 0000000..be55526 --- /dev/null +++ b/Libs/Common_test/sim/spikeFilter.do @@ -0,0 +1,23 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /spikefilter_tb/reset +add wave -noupdate /spikefilter_tb/clock +add wave -noupdate /spikefilter_tb/input +add wave -noupdate /spikefilter_tb/filtered +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3129283489 ps} 0} +configure wave -namecolwidth 285 +configure wave -valuecolwidth 42 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {42 us} diff --git a/Libs/Lattice/hdl/ice40_sbIoOd_rtl.vhd b/Libs/Lattice/hdl/ice40_sbIoOd_rtl.vhd new file mode 100644 index 0000000..c7ef8f5 --- /dev/null +++ b/Libs/Lattice/hdl/ice40_sbIoOd_rtl.vhd @@ -0,0 +1,27 @@ +-- Allows to use RGB pins from ice40 FPGAs +-- as user I/Os +library sb_ice40_components_syn; + use sb_ice40_components_syn.components.all; + +ARCHITECTURE rtl OF ice40_sbIoOd IS +BEGIN + + ODInst : SB_IO_OD + generic map ( + NEG_TRIGGER => '0', -- FF's are rising edge + PIN_TYPE => "011001" -- 0110 = PIN_OUT, 01 = PIN_INPUT + ) + port map ( + DOUT1 => open, -- Output on falling edge + DOUT0 => '1', -- Output on rising edge + CLOCKENABLE => '1', -- Clock Enable common to input and output clocks + LATCHINPUTVALUE => '0', -- Not latching input value + INPUTCLK => clk, -- Clock for the input registers + DIN1 => open, -- Input on falling edge + DIN0 => rgbRd, -- Input value + OUTPUTENABLE => rgbWr, -- Output Pin Tristate/Enable control + OUTPUTCLK => clk, -- Clock for the output registers + PACKAGEPIN => rgbPin -- User’s Pin signal name + ); +END ARCHITECTURE rtl; + diff --git a/Libs/Lattice/hdl/pll_rtl.vhd b/Libs/Lattice/hdl/pll_rtl.vhd new file mode 100644 index 0000000..b8e3549 --- /dev/null +++ b/Libs/Lattice/hdl/pll_rtl.vhd @@ -0,0 +1,93 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc + +-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks + +library IEEE; + use IEEE.std_logic_1164.all; +library ECP5U; + use ECP5U.components.all; + +ENTITY pll IS + PORT( + clkIn100M : IN std_ulogic; + en75M : IN std_ulogic; + en50M : IN std_ulogic; + en10M : IN std_ulogic; + clk60MHz : OUT std_ulogic; + clk75MHz : OUT std_ulogic; + clk50MHz : OUT std_ulogic; + clk10MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll ; + +architecture rtl of pll is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOS3_t: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS3 : string; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000"; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "5"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of rtl : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60, + CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M, + ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked, + INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + + clk10MHz <= CLKOS3_t; + clk50MHz <= CLKOS2_t; + clk75MHz <= CLKOS_t; + clk60MHz <= CLKOP_t; +end rtl; diff --git a/Libs/Lattice/hdl/pll_vga_Structure.vhd b/Libs/Lattice/hdl/pll_vga_Structure.vhd new file mode 100644 index 0000000..12bde4f --- /dev/null +++ b/Libs/Lattice/hdl/pll_vga_Structure.vhd @@ -0,0 +1,70 @@ +library IEEE; +use IEEE.std_logic_1164.all; +library ECP5U; +use ECP5U.components.all; + +ENTITY pll_vga IS + PORT( + clkIn100M : IN std_ulogic; + clk25MHz : OUT std_ulogic; + pllLocked : OUT std_ulogic + ); + +-- Declarations + +END pll_vga ; + +architecture Structure of pll_vga is + + -- internal signal declarations + signal REFCLK: std_logic; + signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "25.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "6"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 25, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 26, CLKFB_DIV=> 1, + CLKI_DIV=> 4, FEEDBK_PATH=> "INT_OP") + port map (CLKI=>clkIn100M, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, + CLKOS2=>open, CLKOS3=>open, LOCK=>pllLocked, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>CLKFB_t); + + clk25MHz <= CLKOP_t; +end Structure; diff --git a/Libs/Lattice/hds/.hdlsidedata/_ice40_sbIoOd_rtl.vhd._fpf b/Libs/Lattice/hds/.hdlsidedata/_ice40_sbIoOd_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Lattice/hds/.hdlsidedata/_ice40_sbIoOd_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Lattice/hds/.hdlsidedata/_pll_rtl.vhd._fpf b/Libs/Lattice/hds/.hdlsidedata/_pll_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Lattice/hds/.hdlsidedata/_pll_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Lattice/hds/.hdlsidedata/_pll_vga_Structure.vhd._fpf b/Libs/Lattice/hds/.hdlsidedata/_pll_vga_Structure.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Lattice/hds/.hdlsidedata/_pll_vga_Structure.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Lattice/hds/_ice40_sbiood._epf b/Libs/Lattice/hds/_ice40_sbiood._epf new file mode 100644 index 0000000..223e683 --- /dev/null +++ b/Libs/Lattice/hds/_ice40_sbiood._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom ice40_sbIoOd_rtl.vhd diff --git a/Libs/Lattice/hds/_pll._epf b/Libs/Lattice/hds/_pll._epf new file mode 100644 index 0000000..c33d67a --- /dev/null +++ b/Libs/Lattice/hds/_pll._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom pll_rtl.vhd diff --git a/Libs/Lattice/hds/_pll_vga._epf b/Libs/Lattice/hds/_pll_vga._epf new file mode 100644 index 0000000..7739eee --- /dev/null +++ b/Libs/Lattice/hds/_pll_vga._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom Structure +DEFAULT_FILE atom pll_vga_Structure.vhd diff --git a/Libs/Lattice/hds/ice40_sb@io@od/symbol.sb b/Libs/Lattice/hds/ice40_sb@io@od/symbol.sb new file mode 100644 index 0000000..c9b8e59 --- /dev/null +++ b/Libs/Lattice/hds/ice40_sb@io@od/symbol.sb @@ -0,0 +1,1521 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +libraryRefs [ +"ieee" +"gates" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 4,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 53,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) 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"C:\\dev\\did-display\\Libs\\Lattice\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds\\pll_vga\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds\\pll_vga\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds\\pll_vga" +) +(vvPair +variable "d_logical" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds\\pll_vga" +) +(vvPair +variable "date" +value "03.04.2023" +) +(vvPair +variable "day" +value "lun." +) +(vvPair +variable "day_long" +value "lundi" +) +(vvPair +variable "dd" +value "03" +) +(vvPair +variable "entity_name" +value "pll_vga" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "03.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "14:31:31" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Lattice" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libraries/Lattice/work" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "pll_vga" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds\\pll_vga\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\dev\\did-display\\Libs\\Lattice\\hds\\pll_vga\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "14:31:31" +) +(vvPair +variable "unit" +value "pll_vga" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 72,0 +optionalChildren [ +*57 (SymbolBody +uid 8,0 +optionalChildren [ +*58 (CptPort +uid 51,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 52,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30000,23625,30750,24375" +) +tg (CPTG +uid 53,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 54,0 +va (VaSet +font "Verdana,12,0" +) +xt "22400,23300,29000,24700" +st "clk25MHz" +ju 2 +blo "29000,24500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 55,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3200,61500,4000" +st "clk25MHz : OUT std_ulogic ;" +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "clk25MHz" +t "std_ulogic" +o 2 +suid 1,0 +) +) +) +*59 (CptPort +uid 56,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 57,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,24625,15000,25375" +) +tg (CPTG +uid 58,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 59,0 +va (VaSet +font "Verdana,12,0" +) +xt "16000,24300,23100,25700" +st "clkIn100M" +blo "16000,25500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 60,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,2400,61500,3200" +st "clkIn100M : IN std_ulogic ;" +) +thePort (LogicalPort +lang 11 +decl (Decl +n "clkIn100M" +t "std_ulogic" +o 1 +suid 2,0 +) +) +) +*60 (CptPort +uid 61,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 62,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30000,25625,30750,26375" +) +tg (CPTG +uid 63,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 64,0 +va (VaSet +font "Verdana,12,0" +) +xt "22400,25300,29000,26700" +st "pllLocked" +ju 2 +blo "29000,26500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 65,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4000,60500,4800" +st "pllLocked : OUT std_ulogic " +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "pllLocked" +t "std_ulogic" +o 3 +suid 3,0 +) +) +) +] +shape (Rectangle +uid 152,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt 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+) +*68 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "57200,44000,58800,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*69 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "37350,44400,47650,45600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*70 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*71 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*72 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "36200,47000,44900,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "65535,0,0" +) +packageList *73 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*74 (Text +uid 49,0 +va (VaSet +font "Verdana,9,1" +) +xt "0,0,7600,1200" +st "Package List" +blo "0,1000" +) +*75 (MLText +uid 50,0 +va (VaSet +) +xt "0,1200,17000,6000" +st "library IEEE; +use IEEE.std_logic_1164.all; +library ECP5U; +use ECP5U.components.all;" +tm "PackageList" +) +] +) +windowSize "568,181,1584,871" +viewArea "12136,8572,57525,40943" +cachedDiagramExtent "-11000,-29000,73000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "-12000,-30000" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Verdana,9,1" +) +xt "1000,1000,5000,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,44000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,14800,32200,16000" +st "" +blo "26800,15800" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,16000,30700,17200" +st "" +blo "26800,17000" +) +) +gi *76 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *77 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,0,49400,1200" +st "Declarations" +blo "42000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,1200,45700,2400" +st "Ports:" +blo "42000,2200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,4800,45200,6000" +st "User:" +blo "42000,5800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,50200,1200" +st "Internal User:" +blo "42000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,6000,44000,6000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 152,0 +activeModelName "Symbol" +) diff --git a/Libs/Memory/hdl/bramBinASCIIInit_rtl.vhd b/Libs/Memory/hdl/bramBinASCIIInit_rtl.vhd new file mode 100644 index 0000000..2d90cc6 --- /dev/null +++ b/Libs/Memory/hdl/bramBinASCIIInit_rtl.vhd @@ -0,0 +1,39 @@ +USE std.textio.all; + +ARCHITECTURE rtl OF bramBinASCIIInit IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + -- Port A + process(clock) + begin + if clock'event and clock='1' then + if en = '1' then + if writeEn = '1' then + dataOut <= dataIn; + ramContent(to_integer(unsigned(addressIn))) := to_bitvector(dataIn,'0'); + else + dataOut <= to_stdulogicvector(ramContent(to_integer(unsigned(addressIn)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE rtl; diff --git a/Libs/Memory/hdl/bramDualportWritefirst_bhv.vhd b/Libs/Memory/hdl/bramDualportWritefirst_bhv.vhd new file mode 100644 index 0000000..09bf83a --- /dev/null +++ b/Libs/Memory/hdl/bramDualportWritefirst_bhv.vhd @@ -0,0 +1,54 @@ +USE std.textio.all; + +ARCHITECTURE bhv OF bramDualportWritefirst IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + -- Port A + process(clockA) + begin + if clockA'event and clockA='1' then + if enA = '1' then + if writeEnA = '1' then + dataOutA <= dataInA; + ramContent(to_integer(unsigned(addressA))) := to_bitvector(dataInA,'0'); + else + dataOutA <= to_stdulogicvector(ramContent(to_integer(unsigned(addressA)))); + end if; + end if; + end if; + end process; + + -- Port B + process(clockB) + begin + if clockB'event and clockB='1' then + if enB = '1' then +-- if writeEnB = '1' then +-- ramContent(to_integer(unsigned(addressB))) := to_bitvector(dataInB,'0'); +-- dataOutB <= dataInB; +-- else + dataOutB <= to_stdulogicvector(ramContent(to_integer(unsigned(addressB)))); +-- end if; + end if; + end if; + end process; + +END ARCHITECTURE bhv; diff --git a/Libs/Memory/hdl/bramDualport_bhv.vhd b/Libs/Memory/hdl/bramDualport_bhv.vhd new file mode 100644 index 0000000..303dec5 --- /dev/null +++ b/Libs/Memory/hdl/bramDualport_bhv.vhd @@ -0,0 +1,41 @@ +USE std.textio.all; + +ARCHITECTURE bhv OF bramDualport IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0); + + -- Declare ramContent signal + shared variable ramContent: ramContentType; + +BEGIN + -- Port A + process(clockA) + begin + if clockA'event and clockA='1' then + if enA = '1' then + if writeEnA = '1' then + dataOutA <= dataInA; + ramContent(to_integer(unsigned(addressA))) := to_bitvector(dataInA,'0'); + else + dataOutA <= to_stdulogicvector(ramContent(to_integer(unsigned(addressA)))); + end if; + end if; + end if; + end process; + + -- Port B + process(clockB) + begin + if clockB'event and clockB='1' then + if enB = '1' then + if writeEnB = '1' then + ramContent(to_integer(unsigned(addressB))) := to_bitvector(dataInB,'0'); + dataOutB <= dataInB; + else + dataOutB <= to_stdulogicvector(ramContent(to_integer(unsigned(addressB)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE bhv; diff --git a/Libs/Memory/hdl/bramHexASCIIInit_rtl.vhd b/Libs/Memory/hdl/bramHexASCIIInit_rtl.vhd new file mode 100644 index 0000000..3313cfd --- /dev/null +++ b/Libs/Memory/hdl/bramHexASCIIInit_rtl.vhd @@ -0,0 +1,42 @@ +library ieee; + use std.textio.all; + use ieee.std_logic_textio.all; + +ARCHITECTURE rtl OF bramHexASCIIInit IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of std_logic_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + HREAD(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + + -- Port A + process(clock) + begin + if clock'event and clock='1' then + if en = '1' then + if writeEn = '1' then + dataOut <= dataIn; + ramContent(to_integer(unsigned(addressIn))) := std_logic_vector(dataIn); + else + dataOut <= to_stdulogicvector(ramContent(to_integer(unsigned(addressIn)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE rtl; diff --git a/Libs/Memory/hdl/bram_actel.vhd b/Libs/Memory/hdl/bram_actel.vhd new file mode 100644 index 0000000..415edbd --- /dev/null +++ b/Libs/Memory/hdl/bram_actel.vhd @@ -0,0 +1,27 @@ +ARCHITECTURE actel OF bram IS + + subtype ramCellType is std_ulogic_vector(dataBitNb-1 DOWNTO 0); + type ramContentType is array(2**addressBitNb-1 downto 0) of ramCellType; + signal ramContent: ramContentType ; + +BEGIN + -- memory array + process(clock) + begin + if rising_edge(clock) then + if (en = '1') and (writeEn = '1') then + ramContent(to_integer(unsigned(addressIn))) <= dataIn; + end if; + end if; + end process; + -- read register + process(clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= ramContent(to_integer(unsigned(addressIn))); + end if; + end if; + end process; + +END ARCHITECTURE actel; diff --git a/Libs/Memory/hdl/bram_bhv.vhd b/Libs/Memory/hdl/bram_bhv.vhd new file mode 100644 index 0000000..b03583a --- /dev/null +++ b/Libs/Memory/hdl/bram_bhv.vhd @@ -0,0 +1,20 @@ +ARCHITECTURE bhv OF bram IS + + type ramContentType is array(2**addressBitNb-1 downto 0) of std_logic_vector(dataBitNb-1 DOWNTO 0); + shared variable ramContent: ramContentType ; + +BEGIN + + process(clock) + begin + if rising_edge(clock) then + if en = '1' then + if writeEn = '1' then + ramContent(to_integer(unsigned(addressIn))) := dataIn; + end if; + dataOut <= ramContent(to_integer(unsigned(addressIn))); + end if; + end if; + end process; + +END ARCHITECTURE bhv; diff --git a/Libs/Memory/hdl/bram_dualport_writefirst.vhd b/Libs/Memory/hdl/bram_dualport_writefirst.vhd new file mode 100644 index 0000000..8fd72bf --- /dev/null +++ b/Libs/Memory/hdl/bram_dualport_writefirst.vhd @@ -0,0 +1,55 @@ +USE std.textio.all; + +ARCHITECTURE bhv OF bramContentDualportWritefirst IS + -- Define ramContent type + type ramContentType is array(0 to (2**addr_bit_nb)-1) of bit_vector(data_bit_nb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(init_file); + +BEGIN + -- Port A + process(clockA) + begin + if clockA'event and clockA='1' then + if enA = '1' then + if writeEnA = '1' then + dataOutA <= dataInA; + ramContent(to_integer(unsigned(addressA))) := to_bitvector(dataInA,'0'); + else + dataOutA <= to_stdulogicvector(ramContent(to_integer(unsigned(addressA)))); + end if; + end if; + end if; + end process; + + -- Port B + process(clockB) + begin + if clockB'event and clockB='1' then + if enB = '1' then + if writeEnB = '1' then + ramContent(to_integer(unsigned(addressB))) := to_bitvector(dataInB,'0'); + dataOutB <= dataInB; + else + dataOutB <= to_stdulogicvector(ramContent(to_integer(unsigned(addressB)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE bhv; + diff --git a/Libs/Memory/hdl/bram_hexRead.vhd b/Libs/Memory/hdl/bram_hexRead.vhd new file mode 100644 index 0000000..f99b3c1 --- /dev/null +++ b/Libs/Memory/hdl/bram_hexRead.vhd @@ -0,0 +1,42 @@ +library ieee; + use std.textio.all; + use ieee.std_logic_textio.all; + +ARCHITECTURE hexRead OF bram IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of std_logic_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + HREAD(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + + -- Port A + process(clock) + begin + if clock'event and clock='1' then + if en = '1' then + if writeEn = '1' then + dataOut <= dataIn; + ramContent(to_integer(unsigned(addressIn))) := std_logic_vector(dataIn); + else + dataOut <= to_stdulogicvector(ramContent(to_integer(unsigned(addressIn)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE hexRead; diff --git a/Libs/Memory/hdl/bram_withInit.vhd b/Libs/Memory/hdl/bram_withInit.vhd new file mode 100644 index 0000000..c28eab9 --- /dev/null +++ b/Libs/Memory/hdl/bram_withInit.vhd @@ -0,0 +1,39 @@ +USE std.textio.all; + +ARCHITECTURE withInit OF bram IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of bit_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + -- Port A + process(clock) + begin + if clock'event and clock='1' then + if en = '1' then + if writeEn = '1' then + dataOut <= dataIn; + ramContent(to_integer(unsigned(addressIn))) := to_bitvector(dataIn,'0'); + else + dataOut <= to_stdulogicvector(ramContent(to_integer(unsigned(addressIn)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE withInit; diff --git a/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd new file mode 100644 index 0000000..9773ce4 --- /dev/null +++ b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd @@ -0,0 +1,73 @@ +-- ------------------------------------------------------------------------------ +-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch) +-- ------------------------------------------------------------------------------ +-- FIFO bridge with bus width adaption +-- A shift register that connects two FIFOs with different bus width. +-- Many IP blocks nowadays have FIFO or FIFO-like interfaces and often they +-- have to be connected. This block can the be used for this task, even if +-- the bus size of the two FIFO interfaces is different. +-- The Rx side bus width has to be a multiple of the Tx side bus width. +-- +-- Created on 2013-10-18 +-- +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-- +-- 2014-10-06: *modify introduction text +-- +add some comment +-- *change readRx to a pulse +-- *fix bug on shift of shiftreg_s +-- 2013-10-18: +intital release +-- ------------------------------------------------------------------------------ +-- + +library Common; + use Common.CommonLib.all; + +ARCHITECTURE behavioral OF fifoBridgeRxToTxBusWidthAdaptionRxBigger IS + + signal cnt_s: unsigned(requiredBitNb(dataBitNbRx)-1 downto 0); + signal shiftreg_s: std_ulogic_vector(dataBitNbRx-1 downto 0); + signal emptyRx_s: std_ulogic; -- internal empty signal + signal writeTx_s: std_ulogic; -- internal write signal + + constant ratio_rxtx_c: positive range 1 to dataBitNbRx/dataBitNbTx:= dataBitNbRx/dataBitNbTx; + +BEGIN + + rx0: process(clock, reset) + begin + if reset = '1' then + shiftreg_s <= (others => '0'); + emptyRx_s <= '1'; + cnt_s <= (others => '0'); + writeTx_s <= '0'; + dataTx <= (others => '0'); + readRx <= '0'; + elsif rising_edge(clock) then + writeTx_s <= '0'; + readRx <= '0'; + -- fetch data + if emptyRx_s = '1' and emptyRx = '0' then + emptyRx_s <= '0'; + shiftreg_s <= dataRx; + readRx <= '1'; + end if; + -- shift data and put out + -- after each write, wait one cylce to check if full gets high + if emptyRx_s = '0' and fullTx = '0' and writeTx_s = '0' then + shiftreg_s <= shiftreg_s(dataBitNbRx-dataBitNbTx-1 downto 0) & std_ulogic_vector(to_unsigned(0,dataBitNbTx)); + dataTx <= shiftreg_s(dataBitNbRx-1 downto dataBitNbRx-dataBitNbTx); + writeTx_s <= '1'; + cnt_s <= cnt_s +1; + if cnt_s >= ratio_rxtx_c-1 then + cnt_s <= (others => '0'); + emptyRx_s <= '1'; + end if; + end if; + end if; + end process; + + writeTx <= writeTx_s; + +END ARCHITECTURE behavioral; + diff --git a/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd new file mode 100644 index 0000000..c6217f8 --- /dev/null +++ b/Libs/Memory/hdl/fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd @@ -0,0 +1,75 @@ +-- ------------------------------------------------------------------------------ +-- Copyright 2013 HES-SO Valais Wallis (www.hevs.ch) +-- ------------------------------------------------------------------------------ +-- FIFO bridge with bus width adaption +-- A shift register that connects two FIFOs with different bus width. +-- Many IP blocks nowadays have FIFO or FIFO-like interface. But the bus width +-- varies often. This block can the be used to adapt the bus width to your own +-- needs. +-- The Tx side bus width has to be a multiple of the Rx side bus width. +-- +-- Created on 2013-10-21 +-- +-- Version: 1.0 +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-- ------------------------------------------------------------------------------ +-- + +library common; + use common.commonlib.all; + +ARCHITECTURE behavioral OF fifoBridgeRxToTxBusWidthAdaptionTxbigger IS + + constant ratio_txrx_c: positive range 1 to dataBitNbTx/dataBitNbRx:= dataBitNbTx/dataBitNbRx; + + signal cnt_s: unsigned(requiredBitNb(ratio_txrx_c-1)-1 downto 0); + signal shiftreg_s: std_ulogic_vector(dataBitNbTx-1 downto 0); + signal fullTx_s: std_ulogic; + signal emptyRx_s: std_ulogic; + +BEGIN + + rx0: process(clock, reset) + begin + if reset = '1' then + shiftreg_s <= (others => '0'); + readRx <= '1'; + emptyRx_s <= '1'; + cnt_s <= (others => '0'); + elsif rising_edge(clock) then + readRx <= NOT fullTx_s; + emptyRx_s <= '1'; + if emptyRx = '0' and fullTx_s = '0' then +-- shiftreg_s(((to_integer(cnt_s)+1)*dataBitNbRx)-1 downto to_integer(cnt_s)*dataBitNbRx) <= dataRx; + shiftreg_s <= shiftreg_s(dataBitNbTx-dataBitNbRx-1 downto 0) & dataRx; + readRx <= '1'; + cnt_s <= cnt_s +1; + if cnt_s >= ratio_txrx_c-1 then + cnt_s <= (others => '0'); + emptyRx_s <= '0'; + end if; + end if; + end if; + end process; + + tx0: process(clock, reset) + begin + if reset = '1' then + fullTx_s <= '1'; + writeTx <= '0'; + dataTx <= (others => '0'); + elsif rising_edge(clock) then + fullTx_s <= fullTx; + writeTx <= '0'; + -- no need to wait to check for full (in contrast to RxBigger) + -- because it will forcibly take several clocks to fill the shiftreg + if emptyRx_s = '0' and fullTx = '0' then + dataTx <= shiftreg_s; + writeTx <= '1'; + end if; + end if; + end process; + +END ARCHITECTURE behavioral; + + diff --git a/Libs/Memory/hdl/fifo_bram_rtl.vhd b/Libs/Memory/hdl/fifo_bram_rtl.vhd new file mode 100644 index 0000000..83336ca --- /dev/null +++ b/Libs/Memory/hdl/fifo_bram_rtl.vhd @@ -0,0 +1,165 @@ +library Common; + use Common.CommonLib.all; + +architecture RTL of FIFO_bram is + + subtype register_type is std_ulogic_vector(dataIn'high downto 0); + type memory_type is array (0 to depth-1) of register_type; + + signal writeCounter: unsigned(requiredBitNb(depth-1)-1 downto 0); + signal readCounter: unsigned(writeCounter'range); + signal memoryArray: memory_type; + + type fifoStateType is ( + sEmpty, sFull, + sRead, sWrite, sWriteFirst, + sReadWrite, sWait + ); + signal fifoState: fifoStateType; + signal emptyCondition, fullCondition, empty_int: std_ulogic; + +begin + ------------------------------------------------------------------------------ + -- read and write counters + updateWriteCounter: process(reset, clock) + begin + if reset = '1' then + writeCounter <= (others => '0'); + elsif rising_edge(clock) then + if (write = '1') and (fullCondition = '0') then + writeCounter <= writeCounter + 1; + end if; + end if; + end process updateWriteCounter; + + updateReadCounter: process(reset, clock) + begin + if reset = '1' then + readCounter <= (others => '0'); + elsif rising_edge(clock) then + if (read = '1') and (empty_int = '0') then + readCounter <= readCounter + 1; + end if; + end if; + end process updateReadCounter; + + ------------------------------------------------------------------------------ + -- memory access + writeMem: process(clock) + begin + if rising_edge(clock) then + if (write = '1') and (fullCondition = '0') then + memoryArray(to_integer(writeCounter)) <= dataIn; + end if; + end if; + end process writeMem; + + readMem: process(reset, clock) + begin + if reset = '1' then + dataOut <= (others => '0'); + elsif rising_edge(clock) then + if (read = '0') or (empty_int = '1') then + dataOut <= memoryArray(to_integer(readCounter)); + else + dataOut <= memoryArray(to_integer(readCounter+1)); + end if; + end if; + end process readMem; + + ------------------------------------------------------------------------------ + -- controls + emptyCondition <= '1' when + ( (fifoState = sRead) and (writeCounter = readCounter) ) or + (fifoState = sEmpty) + else '0'; + + fullCondition <= '1' when + ( (fifoState = sWrite) and (writeCounter = readCounter) ) or + (fifoState = sFull) + else '0'; + + + fifoControl: process(reset, clock) + begin + if reset = '1' then + fifoState <= sEmpty; + elsif rising_edge(clock) then + case fifoState is + when sEmpty => + if write = '1' then + fifoState <= sWriteFirst; + end if; + when sFull => + if (read = '1') then + fifoState <= sRead; + end if; + when sRead => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif write = '1' then + fifoState <= sWrite; + elsif emptyCondition = '1' then + fifoState <= sEmpty; + elsif read = '1' then + fifoState <= sRead; + else + fifoState <= sWait; + end if; + when sWriteFirst => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif write = '1' then + fifoState <= sWrite; + elsif read = '1' then + fifoState <= sRead; + else + fifoState <= sWait; + end if; + when sWrite => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif read = '1' then + fifoState <= sRead; + elsif fullCondition = '1' then + fifoState <= sFull; + elsif write = '1' then + fifoState <= sWrite; + else + fifoState <= sWait; + end if; + when sReadWrite => + if (read = '0') and (write = '0') then + fifoState <= sWait; + elsif (read = '1') and (write = '0') then + fifoState <= sRead; + elsif (write = '1') and (read = '0') then + fifoState <= sWrite; + end if; + when sWait => + if (read = '1') and (write = '1') then + fifoState <= sReadWrite; + elsif read = '1' then + fifoState <= sRead; + elsif write = '1' then + fifoState <= sWrite; + end if; + when others => null; + end case; + end if; + end process fifoControl; + + + full <= '1' when + (fifoState = sFull) or + (fullCondition = '1') + else '0'; + + empty_int <= '1' when + (fifoState = sEmpty) or + (fifoState = sWriteFirst) or + ( (emptyCondition = '1') and (fifoState = sRead) ) + else '0'; + empty <= empty_int; + +end RTL; diff --git a/Libs/Memory/hdl/fifo_minimal.vhd b/Libs/Memory/hdl/fifo_minimal.vhd new file mode 100644 index 0000000..915866c --- /dev/null +++ b/Libs/Memory/hdl/fifo_minimal.vhd @@ -0,0 +1,63 @@ +library Common; + use Common.CommonLib.all; + +architecture minimal of FIFO_bram is + + subtype register_type is std_ulogic_vector(dataIn'high downto 0); + type memory_type is array (0 to depth-1) of register_type; + + signal writeCounter: unsigned(requiredBitNb(depth)-1 downto 0); + signal readCounter: unsigned(writeCounter'range); + signal memoryArray : memory_type; + +begin + + updateWriteCounter: process(reset, clock) + begin + if reset = '1' then + writeCounter <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' then + writeCounter <= writeCounter + 1; + end if; + end if; + end process updateWriteCounter; + + updateReadCounter: process(reset, clock) + begin + if reset = '1' then + readCounter <= (others => '0'); + elsif rising_edge(clock) then + if read = '1' then + readCounter <= readCounter + 1; + end if; + end if; + end process updateReadCounter; + + writeMem: process(clock) + begin + if rising_edge(clock) then + if write = '1' then + memoryArray(to_integer(writeCounter)) <= dataIn; + end if; + end if; + end process writeMem; + + dataOut <= memoryArray(to_integer(readCounter)); + + checkStatus: process(readCounter, writeCounter) + begin + if readCounter = writeCounter then + empty <= '1'; + else + empty <= '0'; + end if; + if writeCounter+1 = readCounter then + full <= '1'; + else + full <= '0'; + end if; + end process checkStatus; + +end minimal; + diff --git a/Libs/Memory/hdl/fifo_oneRegister_rtl.vhd b/Libs/Memory/hdl/fifo_oneRegister_rtl.vhd new file mode 100644 index 0000000..244749d --- /dev/null +++ b/Libs/Memory/hdl/fifo_oneRegister_rtl.vhd @@ -0,0 +1,37 @@ +architecture oneRegister of FIFO_oneRegister is + + signal dataRegister: std_ulogic_vector(dataIn'range); + +begin + + writeReg: process(reset, clock) + begin + if reset = '1' then + dataRegister <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' then + dataRegister <= dataIn; + end if; + end if; + end process writeReg; + + dataOut <= dataRegister; + + manageFlags: process(reset, clock) + begin + if reset = '1' then + empty <= '1'; + full <= '0'; + elsif rising_edge(clock) then + if write = '1' then + empty <= '0'; + full <= '1'; + elsif read = '1' then + empty <= '1'; + full <= '0'; + end if; + end if; + end process manageFlags; + +end oneRegister; + diff --git a/Libs/Memory/hdl/fifo_pim.vhd b/Libs/Memory/hdl/fifo_pim.vhd new file mode 100644 index 0000000..81006e3 --- /dev/null +++ b/Libs/Memory/hdl/fifo_pim.vhd @@ -0,0 +1,118 @@ +library Common; + use Common.CommonLib.all; + +architecture pim of FIFO_bram is + + type mem_t is array (depth-1 downto 0) of std_ulogic_vector(dataIn'range); + subtype mem_range_r is natural range requiredBitNb(depth)-1 downto 0; + subtype ptr_range_r is natural range requiredBitNb(depth)+1-1 downto 0; + + signal mem : mem_t := (others => (others => '0')); + + signal full_int : std_logic; + signal empty_int : std_logic; + signal write_error : std_logic; + signal read_error : std_logic; + signal read_ptr : unsigned(ptr_range_r); + signal read_ptr_next : unsigned(ptr_range_r); + signal write_ptr : unsigned(ptr_range_r); + signal write_ptr_next : unsigned(ptr_range_r); + + signal used_int : unsigned(ptr_range_r); + +begin + ----------------------------------------------------------------------------- + -- Free / used + ----------------------------------------------------------------------------- + + fifo_count_proc: process(reset, clock) + begin + if reset = '1' then + used_int <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' and full_int = '0' then + used_int <= used_int + 1; + end if; + if read = '1' and empty_int = '0' then + used_int <= used_int - 1; + end if; + + -- Simultaneous read/write -> no change + -- ignore full_int, since it is valid + if write = '1' and read = '1' and empty_int = '0' then + used_int <= used_int; + end if; + end if; + end process; + + + ----------------------------------------------------------------------------- + -- FIFO status + ----------------------------------------------------------------------------- + + full_int <= '1' when (write_ptr(write_ptr'left) /= read_ptr(read_ptr'left)) + and ((write_ptr(mem_range_r) = read_ptr(mem_range_r))) + else '0'; + empty_int <= '1' when (write_ptr = read_ptr) else '0'; + + full <= full_int; + empty <= empty_int; + + write_ptr_next <= write_ptr + 1; + read_ptr_next <= read_ptr + 1; + + + ----------------------------------------------------------------------------- + -- FIFO pointers + ----------------------------------------------------------------------------- + + fifo_ptr_proc: process(reset, clock) + begin + if reset = '1' then + write_ptr <= (others => '0'); + read_ptr <= (others => '0'); + write_error <= '0'; + read_error <= '0'; + elsif rising_edge(clock) then + write_error <= '0'; + read_error <= '0'; + if write = '1' then + if full_int = '0' or read = '1' then + write_ptr <= write_ptr_next; + else + write_error <= '1'; + end if; + end if; + if read = '1' then + if empty_int = '0' then + read_ptr <= read_ptr_next; + else + read_error <= '1'; + end if; + end if; + end if; + end process; + + + ----------------------------------------------------------------------------- + -- FIFO RAM + ----------------------------------------------------------------------------- + + fifo_out_proc : process(clock) + begin + if rising_edge(clock) then + dataOut <= mem(to_integer(read_ptr(mem_range_r))); + end if; + end process; + + fifo_in_proc : process(clock) + begin + if rising_edge(clock) then + if write = '1' and full_int = '0' then + mem(to_integer(write_ptr(mem_range_r))) <= dataIn; + end if; + end if; + end process; + +end pim; + diff --git a/Libs/Memory/hdl/fifo_rtl_minimal.vhd b/Libs/Memory/hdl/fifo_rtl_minimal.vhd new file mode 100644 index 0000000..6fcccc8 --- /dev/null +++ b/Libs/Memory/hdl/fifo_rtl_minimal.vhd @@ -0,0 +1,97 @@ +-- +-- VHDL Architecture Memory.fifo_minimal +-- +-- Created: +-- by - uadmin.UNKNOWN (WE3877) +-- at - 13:54:33 11.07.2012 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) +-- +library Common; + use Common.CommonLib.all; + +architecture RTL_minimal of FIFO is + + subtype register_type is std_ulogic_vector(dataIn'high downto 0); + type memory_type is array (0 to depth-1) of register_type; + + signal writeCounter: unsigned(requiredBitNb(depth)-1 downto 0); + signal readCounter: unsigned(writeCounter'range); + signal memoryArray : memory_type; + +begin + + updateWriteCounter: process(reset, clock) + begin + if reset = '1' then + writeCounter <= (others => '0'); + elsif rising_edge(clock) then + if write = '1' then + writeCounter <= writeCounter + 1; + end if; + end if; + end process updateWriteCounter; + + updateReadCounter: process(reset, clock) + begin + if reset = '1' then + readCounter <= (others => '0'); + elsif rising_edge(clock) then + if read = '1' then + readCounter <= readCounter + 1; + end if; + end if; + end process updateReadCounter; + + writeMem: process(clock) + begin + if rising_edge(clock) then + if write = '1' then + memoryArray(to_integer(writeCounter)) <= dataIn; + end if; + end if; + end process writeMem; + + dataOut <= memoryArray(to_integer(readCounter)); + +-- checkStatus: process(reset, clock) +-- begin +-- if reset = '1' then +-- empty <= '1'; +-- full <= '0'; +-- elsif rising_edge(clock) then +-- if readCounter+1 = writeCounter then +-- if read = '1' then +-- empty <= '1'; +-- end if; +-- elsif writeCounter = readCounter then +-- if write = '1' then +-- empty <= '0'; +-- end if; +-- if read = '1' then +-- full <= '0'; +-- end if; +-- elsif writeCounter+1 = readCounter then +-- if write = '1' then +-- full <= '1'; +-- end if; +-- end if; +-- end if; +-- end process checkStatus; + + checkStatus: process(readCounter, writeCounter) + begin + if readCounter = writeCounter then + empty <= '1'; + else + empty <= '0'; + end if; + if writeCounter+1 = readCounter then + full <= '1'; + else + full <= '0'; + end if; + end process checkStatus; + +END ARCHITECTURE RTL_minimal; + diff --git a/Libs/Memory/hdl/fifobridgerxtotx_rtl.vhd b/Libs/Memory/hdl/fifobridgerxtotx_rtl.vhd new file mode 100644 index 0000000..5c20654 --- /dev/null +++ b/Libs/Memory/hdl/fifobridgerxtotx_rtl.vhd @@ -0,0 +1,84 @@ +-- ------------------------------------------------------------------------------ +-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch) +-- ------------------------------------------------------------------------------ +-- FIFO bridge with bus width adaptation +-- A register that connects two FIFOs. +-- Many IP blocks nowadays have FIFO or FIFO-like interfaces and often they +-- have to be connected. This block can the be used for this task. +-- +-- Created on 2012 +-- +-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch) +-- +-- 2016-04-01: fix bug in FWFT read when full +-- 2016-03-22: +add FirstWordFallThrough (FWFT) generic +-- 2012: +intital release +-- ------------------------------------------------------------------------------ +-- + +ARCHITECTURE RTL OF fifoBridgeRxToTx IS + + signal read1: std_ulogic; + signal read2: std_ulogic; + signal read: std_ulogic; + signal storedData: std_ulogic_vector(data1'range); + signal write: std_ulogic; + +BEGIN + + readControl: process(reset, clock) + begin + if reset = '1' then + read1 <= '0'; + read2 <= '0'; + elsif rising_edge(clock) then + if (empty1 = '0') and (full2 = '0') then + read1 <= '1'; + else + read1 <= '0'; + end if; + read2 <= read1; + end if; + end process readControl; + + read <= not empty1 and not full2 when firstWordFallThrough + else not empty1 and read1; + rd1 <= read; + + readData: process(reset, clock) + begin + if reset = '1' then + storedData <= (others => '0'); + elsif rising_edge(clock) then + if firstWordFallThrough then + storedData <= data1; + else + if read = '1' then + storedData <= data1; + end if; + end if; + end if; + end process readData; + + data2 <= storedData; + + writeControl: process(reset, clock) + begin + if reset = '1' then + write <= '0'; + elsif rising_edge(clock) then + if firstWordFallThrough then + write <= not empty1 and not full2; + else + if read = '1' then + write <= '1'; + else + write <= '0'; + end if; + end if; + end if; + end process writeControl; + + wr2 <= write; + +end RTL; diff --git a/Libs/Memory/hdl/flashController_RTL.vhd b/Libs/Memory/hdl/flashController_RTL.vhd new file mode 100644 index 0000000..f8f65c4 --- /dev/null +++ b/Libs/Memory/hdl/flashController_RTL.vhd @@ -0,0 +1,140 @@ +ARCHITECTURE RTL OF flashController IS + + signal addressReg: unsigned(flashAddr'range); + signal dataOutReg: std_ulogic_vector(flashDataOut'range); + signal dataInReg: std_ulogic_vector(flashDataIn'range); + type sequenceStateType is ( + idle, + waitForBus1, waitForBus0, + startAccess, waitAcccessEnd + ); + signal sequenceState: sequenceStateType; + signal read: std_ulogic; + signal startCounter: std_ulogic; + signal sequenceCounter: unsigned(3 downto 0); + signal endOfCount: std_ulogic; + signal readDataValid: std_ulogic; + signal flashCE: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- memory reset + memRst_n <= not '0'; + + ------------------------------------------------------------------------------ + -- address + storeAddress: process(reset, clock) + begin + if reset = '1' then + addressReg <= (others => '0'); + elsif rising_edge(clock) then + if (flashRd = '1') or (flashWr = '1') then + addressReg <= shift_left(flashAddr, 1); + end if; + end if; + end process storeAddress; + + memAddress <= std_ulogic_vector(addressReg); + + ------------------------------------------------------------------------------ + -- data out + storeDataOut: process(reset, clock) + begin + if reset = '1' then + dataOutReg <= (others => '0'); + elsif rising_edge(clock) then + if flashWr = '1' then + dataOutReg <= flashDataOut; + end if; + end if; + end process storeDataOut; + + memDataOut <= flashDataOut; + + ------------------------------------------------------------------------------ + -- data in + readDataValid <= '1' when (read = '1') and (endOfCount = '1') else '0'; + + storeDataIn: process(reset, clock) + begin + if reset = '1' then + dataInReg <= (others => '0'); + elsif rising_edge(clock) then + if readDataValid = '1' then + dataInReg <= memDataIn; + end if; + end if; + end process storeDataIn; + + flashDataIn <= dataInReg when readDataValid = '0' else memDataIn; + + ------------------------------------------------------------------------------ + -- read/write sequence + busAccessFsm: process(reset, clock) + begin + if reset = '1' then + read <= '0'; + sequenceState <= idle; + elsif rising_edge(clock) then + case sequenceState is + when idle => + if flashRd = '1' then + read <= '1'; + sequenceState <= waitForBus1; + elsif flashWr = '1' then + read <= '0'; + sequenceState <= waitForBus1; + end if; + when waitForBus1 => + if memBusEn_n = '1' then + sequenceState <= waitForBus0; + end if; + when waitForBus0 => + if memBusEn_n = '0' then + sequenceState <= startAccess; + end if; + when startAccess => + sequenceState <= waitAcccessEnd; + when waitAcccessEnd => + if endOfCount = '1' then + sequenceState <= idle; + end if; + end case; + end if; + end process busAccessFsm; + + + startCounter <= '1' when sequenceState = startAccess else '0'; + endOfCount <= '1' + when ( (sequenceCounter = rdWaitState) and (read = '1') ) or + ( (sequenceCounter = wrWaitState) and (read = '0') ) + else '0'; + + countSequence: process(reset, clock) + begin + if reset = '1' then + sequenceCounter <= (others => '0'); + elsif rising_edge(clock) then + if sequenceCounter = 0 then + if startCounter = '1' then + sequenceCounter <= sequenceCounter + 1; + end if; + else + if endOfCount = '1' then + sequenceCounter <= (others => '0'); + else + sequenceCounter <= sequenceCounter + 1; + end if; + end if; + end if; + end process countSequence; + + flashCE <= '0' when sequenceCounter = 0 else '1'; + flashCE_n <= not flashCE; + memWR_n <= not '1' when (read = '0') and (flashCE = '1') and (endOfCount = '0') + else not '0'; + memOE_n <= not '1' when (read = '1') and (flashCE = '1') else not '0'; + + flashDataValid <= endOfCount; + +END ARCHITECTURE RTL; diff --git a/Libs/Memory/hdl/sdramControllerBuildAddress_RTL.vhd b/Libs/Memory/hdl/sdramControllerBuildAddress_RTL.vhd new file mode 100644 index 0000000..c2ba793 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerBuildAddress_RTL.vhd @@ -0,0 +1,36 @@ +ARCHITECTURE RTL OF sdramControllerBuildAddress IS + + constant addressPrecharge: std_ulogic_vector(memAddress'range) + := (10=> '1', others => '-'); + constant addressModeRegU : unsigned(memAddress'range) + := resize("0" & "00" & "010" & "0" & "000", memAddress'length); + -- ll,10 = reserved, + -- 9 = '0' programmed burst length => burst length applicable for both rd and wr + -- 8,7 = Op mode = 00 => standard operation (all other states are reserved) + -- 6,5,4 = CAS latency = 010 => cas latency of 2 + -- 3 = Burst Type = '0' => Sequential (not interleaved) + -- 2,1,0 = Brust Length = 000 => brust length is 1 + constant addressModeReg : std_ulogic_vector(memAddress'range) + := std_ulogic_vector(addressModeRegU); + +BEGIN + + buildAddresses: process(ramAddr, addrSelPrecharge, addrSelModeReg, addrSelRow, addrSelCol) + begin + memBankAddress <= std_ulogic_vector(ramAddr(ramAddr'high downto ramAddr'high-memBankAddress'length+1)); + if addrSelPrecharge = '1' then + memAddress <= addressPrecharge; + elsif addrSelModeReg = '1' then + memAddress <= addressModeReg; + elsif addrSelRow = '1' then + memAddress <= std_ulogic_vector(ramAddr(rowAddressBitNb+colAddressBitNb-1 downto colAddressBitNb)); + elsif addrSelCol = '1' then + memAddress(memAddress'high downto colAddressBitNb) <= (others => '0'); + memAddress(10) <= '1'; + memAddress(colAddressBitNb-1 downto 0) <= std_ulogic_vector(ramAddr(colAddressBitNb-1 downto 0)); + else + memAddress <= (others => '-'); + end if; + end process buildAddresses; + +END ARCHITECTURE RTL; diff --git a/Libs/Memory/hdl/sdramControllerRefreshCounter_RTL.vhd b/Libs/Memory/hdl/sdramControllerRefreshCounter_RTL.vhd new file mode 100644 index 0000000..1392f04 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerRefreshCounter_RTL.vhd @@ -0,0 +1,48 @@ +ARCHITECTURE RTL OF sdramControllerRefreshCounter IS + + signal delayCounter: unsigned(delayCounterBitNb-1 downto 0); + signal endOfDelay: std_ulogic; + +BEGIN + + countDelay : process(reset, clock) + begin + if reset = '1' then + delayCounter <= (others => '0'); + elsif rising_edge(clock) then + if endOfDelay = '1' then + delayCounter <= to_unsigned(1, delayCounter'length); + else + delayCounter <= delayCounter + 1; + end if; + end if; + end process countDelay; + + findEndOfDelay: process(powerUpDone, delayCounter) + begin + endOfDelay <= '0'; + if powerUpDone = '0' then + if delayCounter+1 = 0 then + endOfDelay <= '1'; + end if; + else + if delayCounter+1 >= refreshPeriodNb then + endOfDelay <= '1'; + end if; + end if; + end process findEndOfDelay; + + endOfRefreshCount <= endOfDelay; + + signalRefresh: process(powerUpDone, delayCounter) + begin + selectRefresh <= '0'; + if (powerUpDone = '1') and (delayCounter < 1024) then + if (delayCounter <= 16) or (delayCounter(3 downto 0) = 0) then + selectRefresh <= '1'; + end if; + end if; + end process signalRefresh; + + +END ARCHITECTURE RTL; diff --git a/Libs/Memory/hdl/sdramControllerSR_RTL.vhd b/Libs/Memory/hdl/sdramControllerSR_RTL.vhd new file mode 100644 index 0000000..2ec5bc8 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerSR_RTL.vhd @@ -0,0 +1,18 @@ +ARCHITECTURE RTL OF sdramControllerSR IS +BEGIN + + setReset: process(reset, clock) + begin + if reset = '1' then + flag <= '0'; + elsif rising_edge(clock) then + if setFlag = '1' then + flag <= '1'; + elsif resetFlag = '1' then + flag <= '0'; + end if; + end if; + end process setReset; + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hdl/sdramControllerSampleDataIn_RTL.vhd b/Libs/Memory/hdl/sdramControllerSampleDataIn_RTL.vhd new file mode 100644 index 0000000..29bf09f --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerSampleDataIn_RTL.vhd @@ -0,0 +1,17 @@ +ARCHITECTURE RTL OF sdramControllerSampleDataIn IS +BEGIN + + sampleRamData: process(reset, clock) + begin + if reset = '1' then + ramDataIn <= (others => '0'); + elsif falling_edge(clock) then + if sampleData = '1' then + ramDataIn <= memDataIn; + end if; + end if; + end process sampleRamData; + + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hdl/sdramControllerStoreData_RTL.vhd b/Libs/Memory/hdl/sdramControllerStoreData_RTL.vhd new file mode 100644 index 0000000..d73bad4 --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerStoreData_RTL.vhd @@ -0,0 +1,14 @@ +ARCHITECTURE RTL OF sdramControllerStoreData IS +BEGIN + + storeData : process(reset, clock) + begin + if reset = '1' then + memDataOut <= (others => '0'); + elsif rising_edge(clock) then + memDataOut <= ramDataOut; + end if; + end process storeData; + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hdl/sdramControllerTimingsShiftRegister_RTL.vhd b/Libs/Memory/hdl/sdramControllerTimingsShiftRegister_RTL.vhd new file mode 100644 index 0000000..352ef4a --- /dev/null +++ b/Libs/Memory/hdl/sdramControllerTimingsShiftRegister_RTL.vhd @@ -0,0 +1,24 @@ +ARCHITECTURE RTL OF sdramControllerTimingsShiftRegister IS + + --constant leadingZeroesNb: positive := 2; + --constant leadingZeroes: std_ulogic_vector(1 to leadingZeroesNb) := (others => '0'); + --signal shiftReg: std_ulogic_vector(1 to timerDone'high-leadingZeroesNb); + signal shiftReg: std_ulogic_vector(1 to timerDone'high); + +BEGIN + + shiftToken : process(reset, clock) + begin + if reset = '1' then + shiftReg <= (others => '0'); + elsif rising_edge(clock) then + shiftReg(1) <= timerStart; + shiftReg(2 to shiftReg'right) <= shiftReg(1 to shiftReg'right-1); + end if; + end process shiftToken; + + --timerDone <= leadingZeroes & shiftReg; + timerDone <= shiftReg; + +END ARCHITECTURE RTL; + diff --git a/Libs/Memory/hds/.hdlsidedata/_bramBinASCIIInit_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bramBinASCIIInit_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramBinASCIIInit_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bramDualportWritefirst_bhv.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bramDualportWritefirst_bhv.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramDualportWritefirst_bhv.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bramDualport_bhv.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bramDualport_bhv.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramDualport_bhv.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bramHexASCIIInit_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bramHexASCIIInit_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramHexASCIIInit_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bram_actel.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bram_actel.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bram_actel.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bram_bhv.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bram_bhv.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bram_bhv.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bram_dualport_writefirst.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bram_dualport_writefirst.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bram_dualport_writefirst.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bram_hexRead.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bram_hexRead.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bram_hexRead.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Memory/hds/.hdlsidedata/_bram_withInit.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bram_withInit.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bram_withInit.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_bramdualportwritefirst_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionRxbigger_behavioral.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifoBridgeRxToTxBuswidthAdaptionTxbigger_behavioral.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_bram_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_bram_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_minimal.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_minimal.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_minimal.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_oneRegister_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_oneRegister_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_oneRegister_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_oneregister_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_pim.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_pim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_pim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl.vhd._fpf new file mode 100644 index 0000000..2acce3d --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_87 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_rtl_minimal.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl_minimal.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_rtl_minimal.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhg._fpf b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifo_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_fifobridgerxtotx_rtl.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_fifobridgerxtotx_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_fifobridgerxtotx_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_flashController_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_flashController_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_flashController_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerBuildAddress_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerBuildAddress_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerBuildAddress_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerRefreshCounter_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerRefreshCounter_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerRefreshCounter_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerSR_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSR_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSR_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerSampleDataIn_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSampleDataIn_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerSampleDataIn_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerStoreData_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerStoreData_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerStoreData_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/.hdlsidedata/_sdramControllerTimingsShiftRegister_RTL.vhd._fpf b/Libs/Memory/hds/.hdlsidedata/_sdramControllerTimingsShiftRegister_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory/hds/.hdlsidedata/_sdramControllerTimingsShiftRegister_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory/hds/@f@i@f@o/struct.bd b/Libs/Memory/hds/@f@i@f@o/struct.bd new file mode 100644 index 0000000..ed772dd --- /dev/null +++ b/Libs/Memory/hds/@f@i@f@o/struct.bd @@ -0,0 +1,4408 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +frameInstances [ +(FrameInstance +name "g0" +style 1 +insts [ +(Instance +name "I1" +duLibraryName "Memory" +duName "FIFO_oneRegister" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +mwi 0 +uid 530,0 +) +] +) +(FrameInstance +name "g1" +style 1 +insts [ +(Instance +name "I0" +duLibraryName "Memory" +duName "FIFO_bram" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "depth" +type "positive" +value "depth" +) +] +mwi 0 +uid 237,0 +) +] +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds\\@f@i@f@o\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds\\@f@i@f@o\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds\\@f@i@f@o" +) +(vvPair +variable "d_logical" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds\\FIFO" +) +(vvPair +variable "date" +value "04.04.2023" +) +(vvPair +variable "day" +value "mar." +) +(vvPair +variable "day_long" +value "mardi" +) +(vvPair +variable "dd" +value "04" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "FIFO" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "04.04.2023" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "13:26:06" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Memory" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libraries/Memory/work" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "FIFO" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds\\@f@i@f@o\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\did-inverter\\Libs\\Memory\\hds\\FIFO\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ActelPath" +value "$ACTEL_HOME" +) +(vvPair +variable "task_ActelProjectPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\BoardTester\\Board\\ise" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "C:\\eda\\MentorGraphics\\ModelSim\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "13:26:06" +) +(vvPair +variable "unit" +value "FIFO" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2023" +) +(vvPair +variable "yy" +value "23" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 148,0 +optionalChildren [ +*1 (PortIoIn +uid 9,0 +shape (CompositeShape +uid 10,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 11,0 +sl 0 +ro 270 +xt "35000,17625,36500,18375" +) +(Line +uid 12,0 +sl 0 +ro 270 +xt "36500,18000,37000,18000" +pts [ +"36500,18000" +"37000,18000" +] +) +] +) +stc 0 +tg (WTG +uid 13,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 14,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "30200,17300,34000,18700" +st "clock" +ju 2 +blo "34000,18500" +tm "WireNameMgr" +) +) +) +*2 (Net +uid 21,0 +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 1,0 +) +declText (MLText +uid 22,0 +va (VaSet +) +xt "-1000,8600,10600,9800" +st "clock : std_ulogic" +) +) +*3 (PortIoIn +uid 23,0 +shape (CompositeShape +uid 24,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 25,0 +sl 0 +ro 270 +xt "35000,9625,36500,10375" +) +(Line +uid 26,0 +sl 0 +ro 270 +xt "36500,10000,37000,10000" +pts [ +"36500,10000" +"37000,10000" +] +) +] +) +stc 0 +tg (WTG +uid 27,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 28,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "29000,9300,34000,10700" +st "dataIn" +ju 2 +blo "34000,10500" +tm "WireNameMgr" +) +) +) +*4 (Net +uid 35,0 +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 6 +suid 2,0 +) +declText (MLText +uid 36,0 +va (VaSet +) +xt "-1000,13400,28700,14600" +st "dataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*5 (PortIoOut +uid 37,0 +shape (CompositeShape +uid 38,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 39,0 +sl 0 +ro 270 +xt "85500,9625,87000,10375" +) +(Line +uid 40,0 +sl 0 +ro 270 +xt "85000,10000,85500,10000" +pts [ +"85000,10000" +"85500,10000" +] +) +] +) +stc 0 +tg (WTG +uid 41,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 42,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "88000,9300,94000,10700" +st "dataOut" +blo "88000,10500" +tm "WireNameMgr" +) +) +) +*6 (Net +uid 49,0 +decl (Decl +n "dataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 3,0 +) +declText (MLText +uid 50,0 +va (VaSet +) +xt "-1000,11000,29200,12200" +st "dataOut : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*7 (PortIoOut +uid 51,0 +shape (CompositeShape +uid 52,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 53,0 +sl 0 +ro 270 +xt "85500,11625,87000,12375" +) +(Line +uid 54,0 +sl 0 +ro 270 +xt "85000,12000,85500,12000" +pts [ +"85000,12000" +"85500,12000" +] +) +] +) +stc 0 +tg (WTG +uid 55,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 56,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "88000,11300,92700,12700" +st "empty" +blo "88000,12500" +tm "WireNameMgr" +) +) +) +*8 (Net +uid 63,0 +decl (Decl +n "empty" +t "std_ulogic" +o 7 +suid 4,0 +) +declText (MLText +uid 64,0 +va (VaSet +) +xt "-1000,14600,11000,15800" +st "empty : std_ulogic" +) +) +*9 (PortIoOut +uid 65,0 +shape (CompositeShape +uid 66,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 67,0 +sl 0 +ro 90 +xt "35000,11625,36500,12375" +) +(Line +uid 68,0 +sl 0 +ro 90 +xt "36500,12000,37000,12000" +pts [ +"37000,12000" +"36500,12000" +] +) +] +) +stc 0 +tg (WTG +uid 69,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 70,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "31400,11300,34000,12700" +st "full" +ju 2 +blo "34000,12500" +tm "WireNameMgr" +) +) +) +*10 (Net +uid 77,0 +decl (Decl +n "full" +t "std_ulogic" +o 8 +suid 5,0 +) +declText (MLText +uid 78,0 +va (VaSet +) +xt "-1000,15800,9700,17000" +st "full : std_ulogic" +) +) +*11 (PortIoIn +uid 79,0 +shape (CompositeShape +uid 80,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 81,0 +sl 0 +ro 90 +xt "85500,13625,87000,14375" +) +(Line +uid 82,0 +sl 0 +ro 90 +xt "85000,14000,85500,14000" +pts [ +"85500,14000" +"85000,14000" +] +) +] +) +stc 0 +tg (WTG +uid 83,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 84,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "88000,13300,91700,14700" +st "read" +blo "88000,14500" +tm "WireNameMgr" +) +) +) +*12 (Net +uid 91,0 +decl (Decl +n "read" +t "std_ulogic" +o 5 +suid 6,0 +) +declText (MLText +uid 92,0 +va (VaSet +) +xt "-1000,12200,10400,13400" +st "read : std_ulogic" +) +) +*13 (PortIoIn +uid 93,0 +shape (CompositeShape +uid 94,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 95,0 +sl 0 +ro 270 +xt "35000,19625,36500,20375" +) +(Line +uid 96,0 +sl 0 +ro 270 +xt "36500,20000,37000,20000" +pts [ +"36500,20000" +"37000,20000" +] +) +] +) +stc 0 +tg (WTG +uid 97,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 98,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "29900,19300,34000,20700" +st "reset" +ju 2 +blo "34000,20500" +tm "WireNameMgr" +) +) +) +*14 (Net +uid 105,0 +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 7,0 +) +declText (MLText +uid 106,0 +va (VaSet +) +xt "-1000,9800,10500,11000" +st "reset : std_ulogic" +) +) +*15 (PortIoIn +uid 107,0 +shape (CompositeShape +uid 108,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 109,0 +sl 0 +ro 270 +xt "35000,13625,36500,14375" +) +(Line +uid 110,0 +sl 0 +ro 270 +xt "36500,14000,37000,14000" +pts [ +"36500,14000" +"37000,14000" +] +) +] +) +stc 0 +tg (WTG +uid 111,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 112,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "30000,13300,34000,14700" +st "write" +ju 2 +blo "34000,14500" +tm "WireNameMgr" +) +) +) +*16 (Net +uid 119,0 +decl (Decl +n "write" +t "std_ulogic" +o 1 +suid 8,0 +) +declText (MLText +uid 120,0 +va (VaSet +) +xt "-1000,7400,10300,8600" +st "write : std_ulogic" +) +) +*17 (SaComponent +uid 237,0 +optionalChildren [ +*18 (CptPort +uid 205,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 206,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52250,13625,53000,14375" +) +tg (CPTG +uid 207,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 208,0 +va (VaSet +font "Verdana,8,0" +) +xt "54000,13500,56500,14500" +st "write" +blo "54000,14300" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*19 (CptPort +uid 209,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 210,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52250,17625,53000,18375" +) +tg (CPTG +uid 211,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 212,0 +va (VaSet +font "Verdana,8,0" +) +xt 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+activeModelName "Symbol" +) diff --git a/Libs/Memory/hds/@f@i@f@o_one@register/symbol.sb b/Libs/Memory/hds/@f@i@f@o_one@register/symbol.sb new file mode 100644 index 0000000..98aa032 --- /dev/null +++ b/Libs/Memory/hds/@f@i@f@o_one@register/symbol.sb @@ -0,0 +1,1828 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2008,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 299,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "dataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 4,0 +) +) +uid 300,0 +) +*3 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "empty" +t "std_ulogic" +o 7 +suid 7,0 +) +) +uid 301,0 +) +*4 (LogPort +port (LogicalPort +decl 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"62000,41000,62500,41000" +pts [ +"62000,41000" +"62500,41000" +] +) +] +) +tg (WTG +uid 778,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 779,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,40500,68500,41800" +st "txWr1" +blo "65000,41500" +tm "WireNameMgr" +) +) +) +*17 (Net +uid 786,0 +decl (Decl +n "txWr1" +t "std_ulogic" +o 13 +suid 13,0 +) +declText (MLText +uid 787,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,18000,10000,18900" +st "txWr1 : std_ulogic" +) +) +*18 (PortIoIn +uid 788,0 +shape (CompositeShape +uid 789,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 790,0 +sl 0 +ro 270 +xt "28000,12625,29500,13375" +) +(Line +uid 791,0 +sl 0 +ro 270 +xt "29500,13000,30000,13000" +pts [ +"29500,13000" +"30000,13000" +] +) +] +) +tg (WTG +uid 792,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 793,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "3900,12500,27000,13800" +st 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0 +ro 270 +xt "28000,14625,29500,15375" +) +(Line +uid 833,0 +sl 0 +ro 270 +xt "29500,15000,30000,15000" +pts [ +"29500,15000" +"30000,15000" +] +) +] +) +tg (WTG +uid 834,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 835,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "21400,14500,27000,15800" +st "rxEmpty1" +ju 2 +blo "27000,15500" +tm "WireNameMgr" +) +) +) +*25 (Net +uid 842,0 +decl (Decl +n "rxEmpty1" +t "std_ulogic" +o 5 +suid 17,0 +) +declText (MLText +uid 843,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,10800,10000,11700" +st "rxEmpty1 : std_ulogic" +) +) +*26 (PortIoOut +uid 844,0 +shape (CompositeShape +uid 845,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 846,0 +sl 0 +ro 270 +xt "62500,36625,64000,37375" +) +(Line +uid 847,0 +sl 0 +ro 270 +xt "62000,37000,62500,37000" +pts [ +"62000,37000" +"62500,37000" +] +) +] +) +tg (WTG +uid 848,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f 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(Net +uid 870,0 +decl (Decl +n "rxRd2" +t "std_ulogic" +o 10 +suid 19,0 +) +declText (MLText +uid 871,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,15300,10000,16200" +st "rxRd2 : std_ulogic" +) +) +*30 (PortIoIn +uid 872,0 +shape (CompositeShape +uid 873,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 874,0 +sl 0 +ro 270 +xt "28000,36625,29500,37375" +) +(Line +uid 875,0 +sl 0 +ro 270 +xt "29500,37000,30000,37000" +pts [ +"29500,37000" +"30000,37000" +] +) +] +) +tg (WTG +uid 876,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 877,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "3900,36500,27000,37800" +st "rxData2 : (dataBitNb-1 DOWNTO 0)" +ju 2 +blo "27000,37500" +tm "WireNameMgr" +) +) +) +*31 (Net +uid 884,0 +decl (Decl +n "rxData2" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 20,0 +) +declText (MLText +uid 885,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,9900,24500,10800" +st "rxData2 : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*32 (PortIoOut +uid 886,0 +shape (CompositeShape +uid 887,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 888,0 +sl 0 +ro 270 +xt "62500,12625,64000,13375" +) +(Line +uid 889,0 +sl 0 +ro 270 +xt "62000,13000,62500,13000" +pts [ +"62000,13000" +"62500,13000" +] +) +] +) +tg (WTG +uid 890,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 891,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,12500,88100,13800" +st "txData2 : (dataBitNb-1 DOWNTO 0)" +blo "65000,13500" +tm "WireNameMgr" +) +) +) +*33 (Net +uid 898,0 +decl (Decl +n "txData2" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 12 +suid 21,0 +) +declText (MLText +uid 899,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,17100,24500,18000" +st "txData2 : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*34 (PortIoIn +uid 900,0 +shape (CompositeShape +uid 901,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 902,0 +sl 0 +ro 90 +xt "62500,14625,64000,15375" +) +(Line +uid 903,0 +sl 0 +ro 90 +xt "62000,15000,62500,15000" +pts [ +"62500,15000" +"62000,15000" +] +) +] +) +tg (WTG +uid 904,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 905,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,14300,69900,15600" +st "txFull2" +blo "65000,15300" +tm "WireNameMgr" +) +) +) +*35 (Net +uid 912,0 +decl (Decl +n "txFull2" +t "std_ulogic" +o 8 +suid 22,0 +) +declText (MLText +uid 913,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,13500,10000,14400" +st "txFull2 : std_ulogic" +) +) +*36 (PortIoIn +uid 914,0 +shape (CompositeShape +uid 915,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 916,0 +sl 0 +ro 270 +xt "28000,38625,29500,39375" +) +(Line +uid 917,0 +sl 0 +ro 270 +xt "29500,39000,30000,39000" +pts [ +"29500,39000" +"30000,39000" +] +) +] +) +tg (WTG +uid 918,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 919,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "21400,38500,27000,39800" +st "rxEmpty2" +ju 2 +blo "27000,39500" +tm "WireNameMgr" +) +) +) +*37 (Net +uid 926,0 +decl (Decl +n "rxEmpty2" +t "std_ulogic" +o 6 +suid 23,0 +) +declText (MLText +uid 927,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,11700,10000,12600" +st "rxEmpty2 : std_ulogic" +) +) +*38 (PortIoOut +uid 928,0 +shape (CompositeShape +uid 929,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 930,0 +sl 0 +ro 270 +xt "62500,16625,64000,17375" +) +(Line +uid 931,0 +sl 0 +ro 270 +xt "62000,17000,62500,17000" +pts [ +"62000,17000" +"62500,17000" +] +) +] +) +tg (WTG +uid 932,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 933,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "65000,16500,68500,17800" +st "txWr2" +blo "65000,17500" +tm "WireNameMgr" +) +) +) +*39 (Net +uid 940,0 +decl (Decl +n "txWr2" +t "std_ulogic" +o 14 +suid 24,0 +) +declText (MLText +uid 941,0 +va (VaSet +font "courier,8,0" +) +xt "-1000,18900,10000,19800" +st "txWr2 : std_ulogic" +) +) +*40 (SaComponent +uid 1201,0 +optionalChildren [ +*41 (CptPort +uid 1169,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1170,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,20625,38000,21375" +) +tg (CPTG +uid 1171,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1172,0 +va (VaSet +font "courier,9,0" +) +xt "39000,20400,41500,21300" +st "clock" +blo "39000,21100" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*42 (CptPort +uid 1173,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1174,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,22625,38000,23375" +) +tg (CPTG +uid 1175,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1176,0 +va (VaSet +font "courier,9,0" +) +xt "39000,22400,41500,23300" +st "reset" +blo "39000,23100" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 2,0 +) +) +) +*43 (CptPort +uid 1177,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1178,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,12625,54750,13375" +) +tg (CPTG +uid 1179,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1180,0 +va (VaSet +font "courier,9,0" +) +xt "50500,12400,53000,13300" +st "data2" +ju 2 +blo "53000,13100" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "data2" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 3 +suid 3,0 +) +) +) +*44 (CptPort +uid 1181,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1182,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "54000,14625,54750,15375" +) +tg (CPTG +uid 1183,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1184,0 +va (VaSet +font "courier,9,0" +) +xt "50500,14400,53000,15300" +st "full2" +ju 2 +blo "53000,15100" +) +) +thePort (LogicalPort +decl (Decl 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"OnEdgeStrategy" +shape (Triangle +uid 1194,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,12625,38000,13375" +) +tg (CPTG +uid 1195,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1196,0 +va (VaSet +font "courier,9,0" +) +xt "39000,12400,41500,13300" +st "data1" +blo "39000,13100" +) +) +thePort (LogicalPort +decl (Decl +n "data1" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 6 +suid 7,0 +) +) +) +*48 (CptPort +uid 1197,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1198,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,16625,38000,17375" +) +tg (CPTG +uid 1199,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1200,0 +va (VaSet +font "courier,9,0" +) +xt "39000,16400,40500,17300" +st "rd1" +blo "39000,17100" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "rd1" +t "std_ulogic" +o 8 +suid 8,0 +) +) +) +] +shape (Rectangle +uid 1202,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "38000,9000,54000,25000" +) +oxt "35000,10000,51000,26000" +ttg (MlTextGroup +uid 1203,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*49 (Text +uid 1204,0 +va (VaSet +font "courier,9,1" +) +xt "38600,24800,41600,25700" +st "memory" +blo "38600,25500" +tm "BdLibraryNameMgr" +) +*50 (Text +uid 1205,0 +va (VaSet +font "courier,9,1" +) +xt "38600,26000,47100,26900" +st "fifoBridgeRxToTx" +blo "38600,26700" +tm "CptNameMgr" +) +*51 (Text +uid 1206,0 +va (VaSet +font "courier,9,1" +) +xt "38600,27200,42600,28100" +st "rx1ToTx2" +blo "38600,27900" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1207,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1208,0 +text (MLText +uid 1209,0 +va (VaSet +font "courier,8,0" +) +xt "38000,28400,103000,31100" +st "dataBitNb = dataBitNb ( positive ) +fifoDepth = fifoDepth ( positive ) +firstWordFallThrough = firstWordFallThrough ( boolean ) --first byte written into the FIFO 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(MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2600,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "courier,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" 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"-2000,11200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,11400,700,12400" +st "Ports:" +blo "-2000,12200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,28600,500,29500" +st "User:" +blo "-2000,29300" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "-2000,10400,3800,11400" +st "Internal User:" +blo "-2000,11200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "0,29500,0,29500" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "-2000,10400,-2000,10400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 800,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol:GEN" +) diff --git a/Libs/Memory/hds/sdram@controller/struct.bd b/Libs/Memory/hds/sdram@controller/struct.bd new file mode 100644 index 0000000..d8adef0 --- /dev/null +++ b/Libs/Memory/hds/sdram@controller/struct.bd @@ -0,0 +1,9775 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "U_5" +duLibraryName "memory" +duName "sdramControllerSR" +elements [ +] +mwi 0 +uid 2332,0 +) +(Instance +name "U_6" +duLibraryName "memory" +duName "sdramControllerSR" +elements [ +] +mwi 0 +uid 2398,0 +) +(Instance +name "U_2" +duLibraryName "memory" +duName "sdramControllerTimingsShiftRegister" +elements [ +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +] +mwi 0 +uid 3238,0 +) +(Instance +name "U_4" +duLibraryName "memory" +duName "sdramControllerStoreData" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +mwi 0 +uid 3306,0 +) +(Instance +name "U_7" +duLibraryName "memory" +duName "sdramControllerSampleDataIn" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +mwi 0 +uid 3336,0 +) +(Instance +name "U_1" +duLibraryName "memory" +duName "sdramControllerRefreshCounter" +elements [ +(GiElement +name "delayCounterBitNb" +type "positive" +value "delayCounterBitNb" +) +(GiElement +name "refreshPeriodNb" +type "positive" +value "refreshPeriodNb" +) +] +mwi 0 +uid 3568,0 +) +(Instance +name "U_3" +duLibraryName "memory" +duName "sdramControllerBuildAddress" +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "addressBitNb" +) +(GiElement +name "chipAddressBitNb" +type "positive" +value "chipAddressBitNb" +) +(GiElement +name "chipBankAddressBitNb" +type "positive" +value "chipBankAddressBitNb" +) +(GiElement +name "rowAddressBitNb" +type "positive" +value "rowAddressBitNb" +) +(GiElement +name "colAddressBitNb" +type "positive" +value "colAddressBitNb" +) +] +mwi 0 +uid 3925,0 +) +(Instance +name "U_0" +duLibraryName "memory" +duName "sdramControllerFsm" +elements [ +(GiElement +name "commandBusBitNb" +type "positive" +value "commandBusBitNb" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +] +mwi 0 +uid 4230,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +(EmbeddedInstance +name "eb2" +number "2" +) +] +libraryRefs [ +"ieee" +] +) +version "31.1" +appVersion "2018.1 (Build 12)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramController" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "sdramController" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:45:15" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Memory" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../Demo/designcheck" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Memory/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "sdramController" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller/struct.bd" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramController/struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "13:45:15" +) +(vvPair +variable "unit" +value "sdramController" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 356,0 +optionalChildren [ +*1 (PortIoOut +uid 51,0 +shape (CompositeShape +uid 52,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 53,0 +sl 0 +ro 270 +xt "162500,36625,164000,37375" +) +(Line +uid 54,0 +sl 0 +ro 270 +xt "162000,37000,162500,37000" +pts [ +"162000,37000" +"162500,37000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 55,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 56,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "165000,36300,174700,37700" +st "memAddress" +blo "165000,37500" +tm "WireNameMgr" +) +) +) +*2 (Net +uid 63,0 +decl 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"-8000,91800,7500,92700" +st "sdClk : std_ulogic" +) +) +*23 (PortIoOut +uid 219,0 +shape (CompositeShape +uid 220,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 221,0 +sl 0 +ro 270 +xt "122500,76625,124000,77375" +) +(Line +uid 222,0 +sl 0 +ro 270 +xt "122000,77000,122500,77000" +pts [ +"122000,77000" +"122500,77000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 223,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 224,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,76300,130500,77700" +st "sdCs_n" +blo "125000,77500" +tm "WireNameMgr" +) +) +) +*24 (Net +uid 231,0 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 18 +suid 16,0 +) +declText (MLText +uid 232,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,93000,7500,93900" +st "sdCs_n : std_ulogic" +) +) +*25 (PortIoOut +uid 261,0 +shape (CompositeShape +uid 262,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 263,0 +sl 0 +ro 270 +xt "122500,78625,124000,79375" +) +(Line +uid 264,0 +sl 0 +ro 270 +xt "122000,79000,122500,79000" +pts [ +"122000,79000" +"122500,79000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 265,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 266,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,78300,131200,79700" +st "sdRas_n" +blo "125000,79500" +tm "WireNameMgr" +) +) +) +*26 (Net +uid 273,0 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 20 +suid 19,0 +) +declText (MLText +uid 274,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,95400,7500,96300" +st "sdRas_n : std_ulogic" +) +) +*27 (Grouping +uid 313,0 +optionalChildren [ +*28 (CommentText +uid 315,0 +shape (Rectangle +uid 316,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "136000,123000,153000,124000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 317,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "136200,123000,151200,124000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*29 (CommentText +uid 318,0 +shape (Rectangle +uid 319,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "153000,119000,157000,120000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 320,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "153200,119000,156800,120000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*30 (CommentText +uid 321,0 +shape (Rectangle +uid 322,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "136000,121000,153000,122000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 323,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "136200,121000,152400,122000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*31 (CommentText +uid 324,0 +shape (Rectangle +uid 325,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,121000,136000,122000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 326,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "132200,121000,135800,122000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*32 (CommentText +uid 327,0 +shape (Rectangle +uid 328,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "153000,120000,173000,124000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 329,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "153200,120200,166400,121200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*33 (CommentText +uid 330,0 +shape (Rectangle +uid 331,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "157000,119000,173000,120000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 332,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "157200,119000,159000,120000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*34 (CommentText +uid 333,0 +shape (Rectangle +uid 334,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,119000,153000,121000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 335,0 +va (VaSet +fg "32768,0,0" +) +xt "138000,119500,147000,120500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*35 (CommentText +uid 336,0 +shape (Rectangle +uid 337,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,122000,136000,123000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 338,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "132200,122000,135200,123000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*36 (CommentText +uid 339,0 +shape (Rectangle +uid 340,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "132000,123000,136000,124000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 341,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "132200,123000,135800,124000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*37 (CommentText +uid 342,0 +shape (Rectangle +uid 343,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "136000,122000,153000,123000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 344,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "136200,122000,150600,123000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 314,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "132000,119000,173000,124000" +) +oxt "14000,66000,55000,71000" +) +*38 (PortIoIn +uid 599,0 +shape (CompositeShape +uid 600,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 601,0 +sl 0 +ro 270 +xt "52000,54625,53500,55375" +) +(Line +uid 602,0 +sl 0 +ro 270 +xt "53500,55000,54000,55000" +pts [ +"53500,55000" +"54000,55000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 603,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 604,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "47200,54300,51000,55700" +st "clock" +ju 2 +blo "51000,55500" +tm "WireNameMgr" +) +) +) +*39 (Net +uid 611,0 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 23,0 +) +declText (MLText +uid 612,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,72600,7500,73500" +st "clock : std_ulogic" +) +) +*40 (PortIoOut +uid 613,0 +shape (CompositeShape +uid 614,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 615,0 +sl 0 +ro 270 +xt "82500,52625,84000,53375" +) +(Line +uid 616,0 +sl 0 +ro 270 +xt "82000,53000,82500,53000" +pts [ +"82000,53000" +"82500,53000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 617,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 618,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "85000,52300,95000,53700" +st "ramDataValid" +blo "85000,53500" +tm "WireNameMgr" +) +) +) +*41 (Net +uid 625,0 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 24,0 +) +declText (MLText +uid 626,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,88200,7500,89100" +st "ramDataValid : std_ulogic" +) +) +*42 (PortIoIn +uid 627,0 +shape (CompositeShape +uid 628,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 629,0 +sl 0 +ro 270 +xt "128000,36625,129500,37375" +) +(Line +uid 630,0 +sl 0 +ro 270 +xt "129500,37000,130000,37000" +pts [ +"129500,37000" +"130000,37000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 631,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 632,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "120900,36300,127000,37700" +st "ramAddr" +ju 2 +blo "127000,37500" +tm "WireNameMgr" +) +) +) +*43 (Net +uid 639,0 +decl (Decl +n "ramAddr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 3 +suid 25,0 +) +declText (MLText +uid 640,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,75000,19000,75900" +st "ramAddr : unsigned(addressBitNb-1 DOWNTO 0)" +) +) +*44 (PortIoIn +uid 641,0 +shape (CompositeShape +uid 642,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 643,0 +sl 0 +ro 270 +xt "128000,60625,129500,61375" +) +(Line +uid 644,0 +sl 0 +ro 270 +xt "129500,61000,130000,61000" +pts [ +"129500,61000" +"130000,61000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 645,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 646,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "117700,60300,127000,61700" +st "ramDataOut" +ju 2 +blo "127000,61500" +tm "WireNameMgr" +) +) +) +*45 (Net +uid 653,0 +decl (Decl +n "ramDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 26,0 +) +declText (MLText +uid 654,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,76200,22000,77100" +st "ramDataOut : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*46 (PortIoOut +uid 655,0 +shape (CompositeShape +uid 656,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 657,0 +sl 0 +ro 90 +xt "48000,75625,49500,76375" +) +(Line +uid 658,0 +sl 0 +ro 90 +xt "49500,76000,50000,76000" +pts [ +"50000,76000" +"49500,76000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 659,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 660,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "39500,75300,47000,76700" +st "ramDataIn" +ju 2 +blo "47000,76500" +tm "WireNameMgr" +) +) +) +*47 (Net +uid 667,0 +decl (Decl +n "ramDataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 13 +suid 27,0 +) +declText (MLText +uid 668,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,87000,22000,87900" +st "ramDataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*48 (PortIoOut +uid 1316,0 +shape (CompositeShape +uid 1317,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1318,0 +sl 0 +ro 270 +xt "122500,84625,124000,85375" +) +(Line +uid 1319,0 +sl 0 +ro 270 +xt "122000,85000,122500,85000" +pts [ +"122000,85000" +"122500,85000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1320,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1321,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,84300,130100,85700" +st "sdDqm" +blo "125000,85500" +tm "WireNameMgr" +) +) +) +*49 (Net +uid 1328,0 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 19 +suid 28,0 +) +declText (MLText +uid 1329,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,94200,17000,95100" +st "sdDqm : std_ulogic_vector(1 DOWNTO 0)" +) +) +*50 (PortIoOut +uid 1330,0 +shape (CompositeShape +uid 1331,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1332,0 +sl 0 +ro 270 +xt "162500,38625,164000,39375" +) +(Line +uid 1333,0 +sl 0 +ro 270 +xt "162000,39000,162500,39000" +pts [ +"162000,39000" +"162500,39000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1334,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1335,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "165000,38300,177800,39700" +st "memBankAddress" +blo "165000,39500" +tm "WireNameMgr" +) +) +) +*51 (Net +uid 1342,0 +decl (Decl +n "memBankAddress" +t "std_ulogic_vector" +b "( chipBankAddressBitNb-1 DOWNTO 0 )" +o 10 +suid 29,0 +) +declText (MLText +uid 1343,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,83400,28500,84300" +st "memBankAddress : std_ulogic_vector( chipBankAddressBitNb-1 DOWNTO 0 )" +) +) +*52 (HdlText +uid 1607,0 +optionalChildren [ +*53 (EmbeddedText +uid 1613,0 +commentText (CommentText +uid 1614,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1615,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "138000,18000,154000,24000" +) +oxt "0,0,18000,5000" +text (MLText +uid 1616,0 +va (VaSet +font "courier,9,0" +) +xt "138200,18200,148200,20000" +st " +sdCke <= '1'; +sdClk <= not clock; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 6000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 1608,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "138000,17000,154000,25000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1609,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*54 (Text +uid 1610,0 +va (VaSet +font "courier,9,0" +) +xt "138150,25000,140150,26200" +st "eb1" +blo "138150,25900" +tm "HdlTextNameMgr" +) +*55 (Text +uid 1611,0 +va (VaSet +font "courier,9,0" +) +xt "138150,26200,139150,27400" +st "1" +blo "138150,27100" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 1612,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "138250,23250,139750,24750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*56 (Net +uid 1665,0 +decl (Decl +n "powerUpDone" +t "std_ulogic" +o 28 +suid 32,0 +) +declText (MLText +uid 1666,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,112600,11000,113500" +st "SIGNAL powerUpDone : std_ulogic" +) +) +*57 (Net +uid 1681,0 +decl (Decl +n "endOfRefreshCount" +t "std_ulogic" +o 27 +suid 35,0 +) +declText (MLText +uid 1682,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,111400,11000,112300" +st "SIGNAL endOfRefreshCount : std_ulogic" +) +) +*58 (Net +uid 1695,0 +decl (Decl +n "commandBus" +t "std_ulogic_vector" +b "(commandBusBitNb-1 DOWNTO 0)" +o 26 +suid 37,0 +) +declText (MLText +uid 1696,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,110200,28500,111100" +st "SIGNAL commandBus : std_ulogic_vector(commandBusBitNb-1 DOWNTO 0)" +) +) +*59 (HdlText +uid 1697,0 +optionalChildren [ +*60 (EmbeddedText +uid 1703,0 +commentText (CommentText +uid 1704,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1705,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "98000,74000,114000,82000" +) +oxt "0,0,18000,5000" +text (MLText +uid 1706,0 +va (VaSet +font "courier,9,0" +) +xt "98200,74200,114200,79600" +st " +sdCs_n <= commandBus(5); +sdRas_n <= commandBus(4); +sdCas_n <= commandBus(3); +memWr_n <= commandBus(2); +sdDqm <= commandBus(1 downto 0); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 1698,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "98000,73000,114000,89000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1699,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*61 (Text +uid 1700,0 +va (VaSet +font "courier,9,0" +) +xt "98150,89000,100150,90200" +st "eb2" +blo "98150,89900" +tm "HdlTextNameMgr" +) +*62 (Text +uid 1701,0 +va (VaSet +font "courier,9,0" +) +xt "98150,90200,99150,91400" +st "2" +blo "98150,91100" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 1702,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "98250,87250,99750,88750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*63 (Net +uid 1785,0 +decl (Decl +n "timerStart" +t "std_ulogic" +o 33 +suid 39,0 +) +declText (MLText +uid 1786,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,118600,11000,119500" +st "SIGNAL timerStart : std_ulogic" +) +) +*64 (Net +uid 1801,0 +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "(1 TO maxDelayPeriodNb)" +o 32 +suid 41,0 +) +declText (MLText +uid 1802,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,117400,26000,118300" +st "SIGNAL timerDone : std_ulogic_vector(1 TO maxDelayPeriodNb)" +) +) +*65 (Net +uid 1924,0 +decl (Decl +n "addrSelPrecharge" +t "std_ulogic" +o 24 +suid 43,0 +) +declText (MLText +uid 1925,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,107800,11000,108700" +st "SIGNAL addrSelPrecharge : std_ulogic" +) +) +*66 (Net +uid 2051,0 +decl (Decl +n "addrSelModeReg" +t "std_ulogic" +o 23 +suid 44,0 +) +declText (MLText +uid 2052,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,106600,11000,107500" +st "SIGNAL addrSelModeReg : std_ulogic" +) +) +*67 (Net +uid 2266,0 +decl (Decl +n "writeRequest" +t "std_ulogic" +o 35 +suid 45,0 +) +declText (MLText +uid 2267,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,121000,11000,121900" +st "SIGNAL writeRequest : std_ulogic" +) +) +*68 (Net +uid 2276,0 +decl (Decl +n "writeAck" +t "std_ulogic" +o 34 +suid 46,0 +) +declText (MLText +uid 2277,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,119800,11000,120700" +st "SIGNAL writeAck : std_ulogic" +) +) +*69 (SaComponent +uid 2332,0 +optionalChildren [ +*70 (CptPort +uid 2312,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2313,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "17250,32625,18000,33375" +) +tg (CPTG +uid 2314,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2315,0 +va (VaSet +) +xt "19000,32500,21100,33500" +st "clock" +blo "19000,33300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*71 (CptPort +uid 2316,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2317,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "17250,26625,18000,27375" +) +tg (CPTG +uid 2318,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2319,0 +va (VaSet +) +xt "19000,26500,22000,27500" +st "setFlag" +blo "19000,27300" +) +) +thePort (LogicalPort +decl (Decl +n "setFlag" +t "std_ulogic" +o 7 +suid 2,0 +) +) +) +*72 (CptPort +uid 2320,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2321,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "17250,34625,18000,35375" +) +tg (CPTG +uid 2322,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2323,0 +va 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"VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*89 (Net +uid 2456,0 +decl (Decl +n "readAck" +t "std_ulogic" +o 29 +suid 49,0 +) +declText (MLText +uid 2457,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,113800,11000,114700" +st "SIGNAL readAck : std_ulogic" +) +) +*90 (Net +uid 2458,0 +decl (Decl +n "readRequest" +t "std_ulogic" +o 30 +suid 50,0 +) +declText (MLText +uid 2459,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,115000,11000,115900" +st "SIGNAL readRequest : std_ulogic" +) +) +*91 (Net +uid 2516,0 +decl (Decl +n "sampleData" +t "std_ulogic" +o 31 +suid 52,0 +) +declText (MLText +uid 2517,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,116200,11000,117100" +st "SIGNAL sampleData : std_ulogic" +) +) +*92 (SaComponent +uid 3238,0 +optionalChildren [ +*93 (CptPort +uid 3222,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3223,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,60625,98000,61375" +) +tg (CPTG +uid 3224,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3225,0 +va (VaSet +) +xt "99000,60500,101100,61500" +st "clock" +blo "99000,61300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 5,0 +) +) +) +*94 (CptPort +uid 3226,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3227,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,62625,98000,63375" +) +tg (CPTG +uid 3228,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3229,0 +va (VaSet +) +xt "99000,62500,101100,63500" +st "reset" +blo "99000,63300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 6,0 +) +) +) +*95 (CptPort +uid 3230,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3231,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "114000,56625,114750,57375" +) +tg (CPTG +uid 3232,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3233,0 +va (VaSet +) +xt "109100,56500,113000,57500" +st "timerDone" +ju 2 +blo "113000,57300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "(1 TO maxDelayPeriodNb)" +o 25 +suid 7,0 +) +) +) +*96 (CptPort +uid 3234,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3235,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,56625,98000,57375" +) +tg (CPTG +uid 3236,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3237,0 +va (VaSet +) +xt "99000,56500,103100,57500" +st "timerStart" +blo "99000,57300" +) +) +thePort (LogicalPort +decl (Decl +n "timerStart" +t "std_ulogic" +o 24 +suid 8,0 +) +) +) +] +shape (Rectangle +uid 3239,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "98000,53000,114000,65000" +) +oxt "32000,16000,48000,28000" +ttg (MlTextGroup +uid 3240,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*97 (Text +uid 3241,0 +va (VaSet +font "courier,8,1" +) +xt "98400,65000,101700,66000" +st "memory" +blo "98400,65800" +tm "BdLibraryNameMgr" +) +*98 (Text +uid 3242,0 +va (VaSet +font "courier,8,1" +) +xt "98400,66000,113600,67000" +st "sdramControllerTimingsShiftRegister" +blo "98400,66800" +tm "CptNameMgr" +) +*99 (Text +uid 3243,0 +va (VaSet +font "courier,8,1" +) +xt "98400,67000,100200,68000" +st "U_2" +blo "98400,67800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3244,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3245,0 +text (MLText +uid 3246,0 +va (VaSet +font "courier,8,0" +) +xt "98000,68200,125000,69100" +st "maxDelayPeriodNb = maxDelayPeriodNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +] +) +viewicon (ZoomableIcon +uid 3247,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "98250,63250,99750,64750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*100 (SaComponent +uid 3306,0 +optionalChildren [ +*101 (CptPort +uid 3286,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3287,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,66625,138000,67375" +) +tg (CPTG +uid 3288,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3289,0 +va (VaSet +) +xt "139000,66500,141100,67500" +st "clock" +blo "139000,67300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 11,0 +) +) +) +*102 (CptPort +uid 3290,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3291,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "154000,60625,154750,61375" +) +tg (CPTG +uid 3292,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3293,0 +va (VaSet +) +xt "147800,60500,153000,61500" +st "memDataOut" +ju 2 +blo "153000,61300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 12,0 +) +) +) +*103 (CptPort +uid 3294,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3295,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,60625,138000,61375" +) +tg (CPTG +uid 3296,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3297,0 +va (VaSet +) +xt "139000,60500,143900,61500" +st "ramDataOut" +blo "139000,61300" +) +) +thePort (LogicalPort +decl (Decl +n "ramDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 13,0 +) +) +) +*104 (CptPort +uid 3298,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3299,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,62625,138000,63375" +) +tg (CPTG +uid 3300,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3301,0 +va (VaSet +) +xt "139000,62500,141700,63500" +st "ramWr" +blo "139000,63300" +) +) +thePort (LogicalPort +decl (Decl +n "ramWr" +t "std_ulogic" +o 7 +suid 14,0 +) +) +) +*105 (CptPort +uid 3302,0 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(Text +uid 3311,0 +va (VaSet +font "courier,8,1" +) +xt "138500,73000,140300,74000" +st "U_4" +blo "138500,73800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3312,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3313,0 +text (MLText +uid 3314,0 +va (VaSet +font "courier,8,0" +) +xt "138000,74600,158000,75500" +st "dataBitNb = dataBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +) +viewicon (ZoomableIcon +uid 3315,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "138250,69250,139750,70750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*109 (SaComponent +uid 3336,0 +optionalChildren [ +*110 (CptPort +uid 3316,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3317,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,81625,58000,82375" +) +tg (CPTG +uid 3318,0 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+st "dataBitNb = dataBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +] +) +viewicon (ZoomableIcon +uid 3345,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "58250,84250,59750,85750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*118 (SaComponent +uid 3568,0 +optionalChildren [ +*119 (CptPort +uid 3548,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3549,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "97250,40625,98000,41375" +) +tg (CPTG +uid 3550,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3551,0 +va (VaSet +) +xt "99000,40500,101100,41500" +st "clock" +blo "99000,41300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 6,0 +) +) +) +*120 (CptPort +uid 3552,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3553,0 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+) +tg (CPTG +uid 3562,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3563,0 +va (VaSet +) +xt "99000,42500,101100,43500" +st "reset" +blo "99000,43300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 9,0 +) +) +) +*123 (CptPort +uid 3564,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3565,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "114000,38625,114750,39375" +) +tg (CPTG +uid 3566,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3567,0 +va (VaSet +) +xt "107500,38500,113000,39500" +st "selectRefresh" +ju 2 +blo "113000,39300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "selectRefresh" +t "std_ulogic" +o 5 +suid 10,0 +) +) +) +] +shape (Rectangle +uid 3569,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "98000,33000,114000,45000" +) +oxt "32000,12000,48000,24000" +ttg (MlTextGroup +uid 3570,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*124 (Text +uid 3571,0 +va (VaSet +font "courier,8,1" +) +xt "98350,45000,101650,46000" +st "memory" +blo "98350,45800" +tm "BdLibraryNameMgr" +) +*125 (Text +uid 3572,0 +va (VaSet +font "courier,8,1" +) +xt "98350,46000,111650,47000" +st "sdramControllerRefreshCounter" +blo "98350,46800" +tm "CptNameMgr" +) +*126 (Text +uid 3573,0 +va (VaSet +font "courier,8,1" +) +xt "98350,47000,100150,48000" +st "U_1" +blo "98350,47800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3574,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3575,0 +text (MLText +uid 3576,0 +va (VaSet +font "courier,8,0" +) +xt "98000,48200,126000,50000" +st "delayCounterBitNb = delayCounterBitNb ( positive ) +refreshPeriodNb = refreshPeriodNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "delayCounterBitNb" +type "positive" +value "delayCounterBitNb" +) +(GiElement +name "refreshPeriodNb" +type "positive" +value "refreshPeriodNb" +) +] +) +viewicon (ZoomableIcon +uid 3577,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "98250,43250,99750,44750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*127 (Net +uid 3578,0 +decl (Decl +n "selectRefresh" +t "std_ulogic" +o 21 +suid 53,0 +) +declText (MLText +uid 3579,0 +va (VaSet +font "courier,9,0" +) +xt "-8000,96600,7500,97500" +st "selectRefresh : std_ulogic" +) +) +*128 (PortIoOut +uid 3586,0 +shape (CompositeShape +uid 3587,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 3588,0 +sl 0 +ro 270 +xt "122500,38625,124000,39375" +) +(Line +uid 3589,0 +sl 0 +ro 270 +xt "122000,39000,122500,39000" +pts [ +"122000,39000" +"122500,39000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 3590,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3591,0 +va (VaSet +isHidden 1 +font "courier,12,0" +) +xt "125000,38300,135100,39700" +st "selectRefresh" +blo "125000,39500" +tm "WireNameMgr" +) +) +) +*129 (SaComponent +uid 3925,0 +optionalChildren [ +*130 (CptPort +uid 3897,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3898,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,44625,138000,45375" +) +tg (CPTG +uid 3899,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3900,0 +va (VaSet +) +xt "139000,44500,143600,45500" +st "addrSelCol" +blo "139000,45300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelCol" +t "std_ulogic" +o 26 +suid 18,0 +) +) +) +*131 (CptPort +uid 3901,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3902,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,40625,138000,41375" +) +tg (CPTG +uid 3903,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3904,0 +va (VaSet +) +xt "139000,40500,145800,41500" +st "addrSelModeReg" +blo "139000,41300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelModeReg" +t "std_ulogic" +o 26 +suid 19,0 +) +) +) +*132 (CptPort +uid 3905,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3906,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,38625,138000,39375" +) +tg (CPTG +uid 3907,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3908,0 +va (VaSet +) +xt "139000,38500,146000,39500" +st "addrSelPrecharge" +blo "139000,39300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelPrecharge" +t "std_ulogic" +o 26 +suid 20,0 +) +) +) +*133 (CptPort +uid 3909,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3910,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,42625,138000,43375" +) +tg (CPTG +uid 3911,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3912,0 +va (VaSet +) +xt "139000,42500,143900,43500" +st "addrSelRow" +blo "139000,43300" +) +) +thePort (LogicalPort +decl (Decl +n "addrSelRow" +t "std_ulogic" +o 26 +suid 21,0 +) +) +) +*134 (CptPort +uid 3913,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3914,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "154000,36625,154750,37375" +) +tg (CPTG +uid 3915,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3916,0 +va (VaSet +) +xt "147800,36500,153000,37500" +st "memAddress" +ju 2 +blo "153000,37300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memAddress" +t "std_ulogic_vector" +b "( chipAddressBitNb-1 DOWNTO 0 )" +o 9 +suid 22,0 +) +) +) +*135 (CptPort +uid 3917,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3918,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "154000,38625,154750,39375" +) +tg (CPTG +uid 3919,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 3920,0 +va (VaSet +) +xt "146200,38500,153000,39500" +st "memBankAddress" +ju 2 +blo "153000,39300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memBankAddress" +t "std_ulogic_vector" +b "( chipBankAddressBitNb-1 DOWNTO 0 )" +o 10 +suid 23,0 +) +) +) +*136 (CptPort +uid 3921,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 3922,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "137250,36625,138000,37375" +) +tg (CPTG +uid 3923,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 3924,0 +va (VaSet +) +xt "139000,36500,142300,37500" +st "ramAddr" +blo "139000,37300" +) +) +thePort (LogicalPort +decl (Decl +n "ramAddr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 3 +suid 24,0 +) +) +) +] +shape (Rectangle +uid 3926,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "138000,33000,154000,49000" +) +oxt "34000,6000,50000,22000" +ttg (MlTextGroup +uid 3927,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*137 (Text +uid 3928,0 +va (VaSet +font "courier,8,1" +) +xt "137850,49500,141150,50500" +st "memory" +blo "137850,50300" +tm "BdLibraryNameMgr" +) +*138 (Text +uid 3929,0 +va (VaSet +font "courier,8,1" +) +xt "137850,50500,150150,51500" +st "sdramControllerBuildAddress" +blo "137850,51300" +tm "CptNameMgr" +) +*139 (Text +uid 3930,0 +va (VaSet +font "courier,8,1" +) +xt "137850,51500,139650,52500" +st "U_3" +blo "137850,52300" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 3931,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 3932,0 +text (MLText +uid 3933,0 +va (VaSet +font "courier,8,0" +) +xt "138000,53000,169000,57500" +st "addressBitNb = addressBitNb ( positive ) +chipAddressBitNb = chipAddressBitNb ( positive ) +chipBankAddressBitNb = chipBankAddressBitNb ( positive ) +rowAddressBitNb = rowAddressBitNb ( positive ) +colAddressBitNb = colAddressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "addressBitNb" +) +(GiElement +name "chipAddressBitNb" +type "positive" +value "chipAddressBitNb" +) +(GiElement +name "chipBankAddressBitNb" +type "positive" +value "chipBankAddressBitNb" +) +(GiElement +name "rowAddressBitNb" +type "positive" +value "rowAddressBitNb" +) +(GiElement +name "colAddressBitNb" +type "positive" +value "colAddressBitNb" +) +] +) +viewicon (ZoomableIcon +uid 3934,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "138250,47250,139750,48750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*140 (SaComponent +uid 4230,0 +optionalChildren [ +*141 (CptPort +uid 4158,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4159,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,46625,74750,47375" +) +tg (CPTG +uid 4160,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4161,0 +va (VaSet +) +xt "68400,46500,73000,47500" +st "addrSelCol" +ju 2 +blo "73000,47300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelCol" +t "std_ulogic" +o 8 +suid 149,0 +) +) +) +*142 (CptPort +uid 4162,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4163,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,42625,74750,43375" +) +tg (CPTG +uid 4164,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4165,0 +va (VaSet +) +xt "66200,42500,73000,43500" +st "addrSelModeReg" +ju 2 +blo "73000,43300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelModeReg" +t "std_ulogic" +o 9 +suid 150,0 +) +) +) +*143 (CptPort +uid 4166,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4167,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,40625,74750,41375" +) +tg (CPTG +uid 4168,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4169,0 +va (VaSet +) +xt "66000,40500,73000,41500" +st "addrSelPrecharge" +ju 2 +blo "73000,41300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelPrecharge" +t "std_ulogic" +o 10 +suid 151,0 +) +) +) +*144 (CptPort +uid 4170,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4171,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,44625,74750,45375" +) +tg (CPTG +uid 4172,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4173,0 +va (VaSet +) +xt "68100,44500,73000,45500" +st "addrSelRow" +ju 2 +blo "73000,45300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrSelRow" +t "std_ulogic" +o 11 +suid 152,0 +) +) +) +*145 (CptPort +uid 4174,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4175,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,54625,58000,55375" +) +tg (CPTG +uid 4176,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4177,0 +va (VaSet +) +xt "59000,54500,61100,55500" +st "clock" +blo "59000,55300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 153,0 +) +) +) +*146 (CptPort +uid 4178,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4179,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,54625,74750,55375" +) +tg (CPTG +uid 4180,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4181,0 +va (VaSet +) +xt "67700,54500,73000,55500" +st "commandBus" +ju 2 +blo "73000,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "commandBus" +t "std_ulogic_vector" +b "( commandBusBitNb-1 DOWNTO 0 )" +o 12 +suid 154,0 +) +) +) +*147 (CptPort +uid 4182,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4183,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,36625,58000,37375" +) +tg (CPTG +uid 4184,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4185,0 +va (VaSet +) +xt "59000,36500,66500,37500" +st "endOfRefreshCount" +blo "59000,37300" +) +) +thePort (LogicalPort +decl (Decl +n "endOfRefreshCount" +t "std_ulogic" +o 2 +suid 155,0 +) +) +) +*148 (CptPort +uid 4186,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4187,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,36625,74750,37375" +) +tg (CPTG +uid 4188,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4189,0 +va (VaSet +) +xt "67400,36500,73000,37500" +st "powerUpDone" +ju 2 +blo "73000,37300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "powerUpDone" +t "std_ulogic" +o 13 +suid 156,0 +) +) +) +*149 (CptPort +uid 4190,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4191,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,52625,74750,53375" +) +tg (CPTG +uid 4192,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4193,0 +va (VaSet +) +xt "67600,52500,73000,53500" +st "ramDataValid" +ju 2 +blo "73000,53300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 157,0 +) +) +) +*150 (CptPort +uid 4194,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4195,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,52625,58000,53375" +) +tg (CPTG +uid 4196,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4197,0 +va (VaSet +) +xt "59000,52500,61600,53500" +st "ramEn" +blo "59000,53300" +) +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 3 +suid 158,0 +) +) +) +*151 (CptPort +uid 4198,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4199,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,48625,58000,49375" +) +tg (CPTG +uid 4200,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4201,0 +va (VaSet +) +xt "59000,48500,62100,49500" +st "readAck" +blo "59000,49300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "readAck" +t "std_ulogic" +o 15 +suid 159,0 +) +) +) +*152 (CptPort +uid 4202,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4203,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,46625,58000,47375" +) +tg (CPTG +uid 4204,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4205,0 +va (VaSet +) +xt "59000,46500,64200,47500" +st "readRequest" +blo "59000,47300" +) +) +thePort (LogicalPort +decl (Decl +n "readRequest" +t "std_ulogic" +o 4 +suid 160,0 +) +) +) +*153 (CptPort +uid 4206,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4207,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,56625,58000,57375" +) +tg (CPTG +uid 4208,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4209,0 +va (VaSet +) +xt "59000,56500,61100,57500" +st "reset" +blo "59000,57300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 161,0 +) +) +) +*154 (CptPort +uid 4210,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4211,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,48625,74750,49375" +) +tg (CPTG +uid 4212,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4213,0 +va (VaSet +) +xt "68200,48500,73000,49500" +st "sampleData" +ju 2 +blo "73000,49300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sampleData" +t "std_ulogic" +o 16 +suid 162,0 +) +) +) +*155 (CptPort +uid 4214,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4215,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,38625,58000,39375" +) +tg (CPTG +uid 4216,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4217,0 +va (VaSet +) +xt "59000,38500,62900,39500" +st "timerDone" +blo "59000,39300" +) +) +thePort (LogicalPort +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "( 1 TO maxDelayPeriodNb )" +o 6 +suid 163,0 +) +) +) +*156 (CptPort +uid 4218,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4219,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "74000,38625,74750,39375" +) +tg (CPTG +uid 4220,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4221,0 +va (VaSet +) +xt "68900,38500,73000,39500" +st "timerStart" +ju 2 +blo "73000,39300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "timerStart" +t "std_ulogic" +o 17 +suid 164,0 +) +) +) +*157 (CptPort +uid 4222,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4223,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,44625,58000,45375" +) +tg (CPTG +uid 4224,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4225,0 +va (VaSet +) +xt "59000,44500,62200,45500" +st "writeAck" +blo "59000,45300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "writeAck" +t "std_ulogic" +o 18 +suid 165,0 +) +) +) +*158 (CptPort +uid 4226,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4227,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57250,42625,58000,43375" +) +tg (CPTG +uid 4228,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4229,0 +va (VaSet +) +xt "59000,42500,64300,43500" +st "writeRequest" +blo "59000,43300" +) +) +thePort (LogicalPort +decl (Decl +n "writeRequest" +t "std_ulogic" +o 7 +suid 166,0 +) +) +) +] +shape (Rectangle +uid 4231,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "58000,33000,74000,59000" +) +oxt "35000,6000,51000,32000" +ttg (MlTextGroup +uid 4232,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*159 (Text +uid 4233,0 +va (VaSet +font "courier,8,1" +) +xt "58750,59000,62050,60000" +st "memory" +blo "58750,59800" +tm "BdLibraryNameMgr" +) +*160 (Text +uid 4234,0 +va (VaSet +font "courier,8,1" +) +xt "58750,60000,67250,61000" +st "sdramControllerFsm" +blo "58750,60800" +tm "CptNameMgr" +) +*161 (Text +uid 4235,0 +va (VaSet +font "courier,8,1" +) +xt "58750,61000,60550,62000" +st "U_0" +blo "58750,61800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4236,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4237,0 +text (MLText +uid 4238,0 +va (VaSet +font "courier,8,0" +) +xt "39000,62000,85000,71000" +st "commandBusBitNb = commandBusBitNb ( positive ) +maxDelayPeriodNb = maxDelayPeriodNb ( positive ) +prechargeToRefreshPeriodNb = 2 ( positive ) --66MHz * 20 ns = 1.32 +refreshDelayPeriodNb = 5 ( positive ) --66MHz * 66ns = 4.356 +loadModeToActivePeriodNb = 1 ( positive ) --1 CK +activeToWritePeriodNb = 2 ( positive ) --66MHz * 20ns = 1.32 +writeToActivePeriodNb = 3 ( positive ) --1 CK + 66MHz * 20ns = 2.32 +activeToReadPeriodNb = 2 ( positive ) --66MHz * 20ns = 1.32 +readToSamplePeriodNb = 2 ( positive ) --2 CK with latency = 2 +readToActivePeriodNb = 3 ( positive ) --1 CK + 66MHz * 20ns = 2.32 " +) +header "" +) +elements [ +(GiElement +name "commandBusBitNb" +type "positive" +value "commandBusBitNb" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "maxDelayPeriodNb" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +] +) +viewicon (ZoomableIcon +uid 4239,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "58250,57250,59750,58750" +iconName "StateMachineViewIcon.png" +iconMaskName "StateMachineViewIcon.msk" +ftype 3 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*162 (Wire +uid 57,0 +shape (OrthoPolyLine +uid 58,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "154750,37000,162000,37000" +pts [ +"162000,37000" +"154750,37000" +] +) +start &1 +end &134 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 61,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 62,0 +va (VaSet +font "courier,12,0" +) +xt "156000,35600,165700,37000" +st "memAddress" +blo "156000,36800" +tm "WireNameMgr" +) +) +on &2 +) +*163 (Wire +uid 85,0 +shape (OrthoPolyLine +uid 86,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "74750,76000,83000,76000" +pts [ +"83000,76000" +"74750,76000" +] +) +start &3 +end &111 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 89,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 90,0 +va (VaSet +font "courier,12,0" +) +xt "76000,74600,84100,76000" +st "memDataIn" +blo "76000,75800" +tm "WireNameMgr" +) +) +on &4 +) +*164 (Wire +uid 99,0 +shape (OrthoPolyLine +uid 100,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "154750,61000,162000,61000" +pts [ +"162000,61000" +"154750,61000" +] +) +start &5 +end &102 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 103,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 104,0 +va (VaSet +font "courier,12,0" +) +xt "161000,59600,170900,61000" +st "memDataOut" +blo "161000,60800" +tm "WireNameMgr" +) +) +on &6 +) +*165 (Wire +uid 113,0 +shape (OrthoPolyLine +uid 114,0 +va (VaSet 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+sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 145,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 146,0 +va (VaSet +font "courier,12,0" +) +xt "10000,47600,14800,49000" +st "ramRd" +blo "10000,48800" +tm "WireNameMgr" +) +) +on &12 +) +*168 (Wire +uid 169,0 +shape (OrthoPolyLine +uid 170,0 +va (VaSet +vasetType 3 +) +xt "54000,57000,57250,57000" +pts [ +"54000,57000" +"57250,57000" +] +) +start &15 +end &153 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 173,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 174,0 +va (VaSet +font "courier,12,0" +) +xt "53000,55600,57100,57000" +st "reset" +blo "53000,56800" +tm "WireNameMgr" +) +) +on &16 +) +*169 (Wire +uid 183,0 +shape (OrthoPolyLine +uid 184,0 +va (VaSet +vasetType 3 +) +xt "114000,81000,122000,81000" +pts [ +"122000,81000" +"114000,81000" +] +) +start &17 +end &59 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 187,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 188,0 +va (VaSet +font "courier,12,0" +) +xt "117000,79600,123300,81000" +st "sdCas_n" +blo "117000,80800" +tm "WireNameMgr" +) +) +on &18 +) +*170 (Wire +uid 197,0 +shape (OrthoPolyLine +uid 198,0 +va (VaSet +vasetType 3 +) +xt "154000,19000,162000,19000" +pts [ +"162000,19000" +"154000,19000" +] +) +start &19 +end &52 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 201,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 202,0 +va (VaSet +font "courier,12,0" +) +xt "159000,17600,163700,19000" +st "sdCke" +blo "159000,18800" +tm "WireNameMgr" +) +) +on &20 +) +*171 (Wire +uid 211,0 +shape (OrthoPolyLine +uid 212,0 +va (VaSet +vasetType 3 +) +xt "154000,21000,162000,21000" +pts [ +"162000,21000" +"154000,21000" +] +) +start &21 +end &52 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 215,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 216,0 +va (VaSet +font "courier,12,0" +) +xt "159000,19600,163200,21000" +st "sdClk" +blo "159000,20800" +tm "WireNameMgr" +) +) +on &22 +) +*172 (Wire +uid 225,0 +shape (OrthoPolyLine +uid 226,0 +va (VaSet +vasetType 3 +) +xt "114000,77000,122000,77000" +pts [ +"122000,77000" +"114000,77000" +] +) +start &23 +end &59 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 229,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 230,0 +va (VaSet +font "courier,12,0" +) +xt "118000,75600,123500,77000" +st "sdCs_n" +blo "118000,76800" +tm "WireNameMgr" +) +) +on &24 +) +*173 (Wire +uid 267,0 +shape (OrthoPolyLine +uid 268,0 +va (VaSet +vasetType 3 +) +xt "114000,79000,122000,79000" +pts [ +"122000,79000" +"114000,79000" +] +) +start &25 +end &59 +sat 32 +eat 2 +st 0 +sf 1 +si 0 +tg (WTG +uid 271,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 272,0 +va (VaSet +font "courier,12,0" +) +xt "117000,77600,123200,79000" +st "sdRas_n" +blo "117000,78800" +tm "WireNameMgr" +) +) +on &26 +) +*174 (Wire +uid 605,0 +shape (OrthoPolyLine +uid 606,0 +va (VaSet +vasetType 3 +) +xt "54000,55000,57250,55000" +pts [ +"54000,55000" +"57250,55000" +] +) +start &38 +end &145 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 609,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 610,0 +va (VaSet +font "courier,12,0" +) +xt "54000,53600,57800,55000" +st "clock" +blo "54000,54800" +tm "WireNameMgr" +) +) +on &39 +) +*175 (Wire +uid 619,0 +shape (OrthoPolyLine +uid 620,0 +va (VaSet +vasetType 3 +) +xt "74750,53000,82000,53000" +pts [ +"74750,53000" +"82000,53000" +] +) +start &149 +end &40 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 623,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 624,0 +va (VaSet +font "courier,12,0" +) +xt "76000,51600,86000,53000" +st "ramDataValid" +blo "76000,52800" +tm "WireNameMgr" +) +) +on &41 +) +*176 (Wire +uid 633,0 +shape (OrthoPolyLine +uid 634,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "130000,37000,137250,37000" +pts [ +"130000,37000" +"137250,37000" +] +) +start &42 +end &136 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 637,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 638,0 +va (VaSet +font "courier,12,0" +) +xt "130000,35600,136100,37000" +st "ramAddr" +blo "130000,36800" +tm "WireNameMgr" +) +) +on &43 +) +*177 (Wire +uid 647,0 +shape (OrthoPolyLine +uid 648,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "130000,61000,137250,61000" +pts [ +"130000,61000" +"137250,61000" +] +) +start &44 +end &103 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 651,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 652,0 +va (VaSet +font "courier,12,0" +) +xt "129000,59600,138300,61000" +st "ramDataOut" +blo "129000,60800" +tm "WireNameMgr" +) +) +on &45 +) +*178 (Wire +uid 661,0 +shape (OrthoPolyLine +uid 662,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "50000,76000,57250,76000" +pts [ +"57250,76000" +"50000,76000" +] +) +start &112 +end &46 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 665,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 666,0 +va (VaSet +font "courier,12,0" +) +xt "50000,74600,57500,76000" +st "ramDataIn" +blo "50000,75800" +tm "WireNameMgr" +) +) +on &47 +) +*179 (Wire +uid 1322,0 +shape (OrthoPolyLine +uid 1323,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "114000,85000,122000,85000" +pts [ +"114000,85000" +"122000,85000" +] +) +start &59 +end &48 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1326,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1327,0 +va (VaSet +font "courier,12,0" +) +xt "117000,83600,122100,85000" +st "sdDqm" +blo "117000,84800" +tm "WireNameMgr" +) +) +on &49 +) +*180 (Wire +uid 1336,0 +shape (OrthoPolyLine +uid 1337,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "154750,39000,162000,39000" +pts [ +"154750,39000" +"162000,39000" +] +) +start &135 +end &50 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1340,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1341,0 +va (VaSet +font "courier,12,0" +) +xt "156000,37600,168800,39000" +st "memBankAddress" +blo "156000,38800" +tm "WireNameMgr" +) +) +on &51 +) +*181 (Wire +uid 1637,0 +shape (OrthoPolyLine +uid 1638,0 +va (VaSet +vasetType 3 +) +xt "94000,43000,97250,43000" +pts [ +"94000,43000" +"97250,43000" +] +) +end &122 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1643,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1644,0 +va (VaSet +font "courier,12,0" +) +xt "93000,41600,97100,43000" +st "reset" +blo "93000,42800" +tm "WireNameMgr" +) +) +on &16 +) +*182 (Wire +uid 1645,0 +shape (OrthoPolyLine +uid 1646,0 +va (VaSet +vasetType 3 +) +xt "94000,41000,97250,41000" +pts [ +"94000,41000" +"97250,41000" +] +) +end &119 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1651,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1652,0 +va (VaSet +font "courier,12,0" +) +xt "94000,39600,97800,41000" +st "clock" +blo "94000,40800" +tm "WireNameMgr" +) +) +on &39 +) +*183 (Wire +uid 1655,0 +shape (OrthoPolyLine +uid 1656,0 +va (VaSet +vasetType 3 +) +xt "74750,37000,97250,37000" +pts [ +"74750,37000" +"97250,37000" +] +) +start &148 +end &121 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1661,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1662,0 +va (VaSet +font "courier,12,0" +) +xt "76000,35600,86600,37000" +st "powerUpDone" +blo "76000,36800" +tm "WireNameMgr" +) +) +on &56 +) +*184 (Wire +uid 1671,0 +shape (OrthoPolyLine +uid 1672,0 +va (VaSet +vasetType 3 +) +xt "54000,29000,118000,37000" +pts [ +"114750,37000" +"118000,37000" +"118000,29000" +"54000,29000" +"54000,37000" +"57250,37000" +] +) +start &120 +end &147 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1677,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1678,0 +va (VaSet +font "courier,12,0" +) +xt "117000,35600,131000,37000" +st "endOfRefreshCount" +blo "117000,36800" +tm "WireNameMgr" +) +) +on &57 +) +*185 (Wire +uid 1687,0 +shape (OrthoPolyLine +uid 1688,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "74750,55000,98000,77000" +pts [ +"74750,55000" +"86000,55000" +"86000,77000" +"98000,77000" +] +) +start &146 +end &59 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1693,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1694,0 +va (VaSet +font "courier,12,0" +) +xt "88000,75600,97900,77000" +st "commandBus" +blo "88000,76800" +tm "WireNameMgr" +) +) +on &58 +) +*186 (Wire +uid 1761,0 +shape (OrthoPolyLine +uid 1762,0 +va (VaSet +vasetType 3 +) +xt "74750,39000,97250,57000" +pts [ +"74750,39000" +"90000,39000" +"90000,57000" +"97250,57000" +] +) +start &156 +end &96 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1767,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1768,0 +va (VaSet +font "courier,12,0" +) +xt "76000,37600,83900,39000" +st "timerStart" +blo "76000,38800" +tm "WireNameMgr" +) +) +on &63 +) +*187 (Wire +uid 1769,0 +shape (OrthoPolyLine +uid 1770,0 +va (VaSet +vasetType 3 +) +xt "94000,61000,97250,61000" +pts [ +"94000,61000" +"97250,61000" +] +) +end &93 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1775,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1776,0 +va (VaSet +font "courier,12,0" +) +xt "94000,59600,97800,61000" +st "clock" +blo "94000,60800" +tm "WireNameMgr" +) +) +on &39 +) +*188 (Wire +uid 1777,0 +shape (OrthoPolyLine +uid 1778,0 +va (VaSet +vasetType 3 +) +xt "94000,63000,97250,63000" +pts [ +"94000,63000" +"97250,63000" +] +) +end &94 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1783,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1784,0 +va (VaSet +font "courier,12,0" +) +xt "93000,61600,97100,63000" +st "reset" +blo "93000,62800" +tm "WireNameMgr" +) +) +on &16 +) +*189 (Wire +uid 1789,0 +shape (OrthoPolyLine +uid 1790,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "52000,27000,120000,57000" +pts [ +"114750,57000" +"120000,57000" +"120000,27000" +"52000,27000" +"52000,39000" +"57250,39000" +] +) +start &95 +end &155 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 1795,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1796,0 +va (VaSet +font "courier,12,0" +) +xt "117000,55600,124300,57000" +st "timerDone" +blo "117000,56800" +tm "WireNameMgr" +) +) +on &64 +) +*190 (Wire +uid 1916,0 +shape (OrthoPolyLine +uid 1917,0 +va (VaSet +vasetType 3 +) +xt "130000,39000,137250,39000" +pts [ +"130000,39000" +"137250,39000" +] +) +end &132 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 1922,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1923,0 +va (VaSet +font "courier,12,0" +) +xt "127000,37600,139800,39000" +st "addrSelPrecharge" +blo "127000,38800" +tm "WireNameMgr" +) +) +on &65 +) +*191 (Wire +uid 1926,0 +shape (OrthoPolyLine +uid 1927,0 +va (VaSet +vasetType 3 +) +xt "74750,41000,82000,41000" +pts [ +"74750,41000" +"82000,41000" +] +) +start &143 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 1932,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1933,0 +va (VaSet +font "courier,12,0" +) +xt "76000,39600,88800,41000" +st "addrSelPrecharge" +blo "76000,40800" +tm "WireNameMgr" +) +) +on &65 +) +*192 (Wire +uid 2043,0 +shape (OrthoPolyLine +uid 2044,0 +va (VaSet +vasetType 3 +) +xt "74750,43000,82000,43000" +pts [ +"74750,43000" +"82000,43000" +] +) +start &142 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 2049,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2050,0 +va (VaSet +font "courier,12,0" +) +xt "76000,41600,88200,43000" +st "addrSelModeReg" +blo "76000,42800" +tm "WireNameMgr" +) +) +on &66 +) +*193 (Wire +uid 2053,0 +shape (OrthoPolyLine +uid 2054,0 +va (VaSet +vasetType 3 +) +xt "130000,41000,137250,41000" +pts [ +"130000,41000" +"137250,41000" +] +) +end &131 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2059,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2060,0 +va (VaSet +font "courier,12,0" +) +xt "127000,39600,139200,41000" +st "addrSelModeReg" +blo "127000,40800" +tm "WireNameMgr" +) +) +on &66 +) +*194 (Wire +uid 2063,0 +shape (OrthoPolyLine +uid 2064,0 +va (VaSet +vasetType 3 +) +xt "130000,63000,137250,63000" +pts [ +"130000,63000" +"137250,63000" +] +) +end &104 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2069,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2070,0 +va (VaSet +font "courier,12,0" +) +xt "131000,61600,136000,63000" +st "ramWr" +blo "131000,62800" +tm "WireNameMgr" +) +) +on &14 +) +*195 (Wire +uid 2071,0 +shape (OrthoPolyLine +uid 2072,0 +va (VaSet +vasetType 3 +) +xt "134000,67000,137250,67000" +pts [ +"134000,67000" +"137250,67000" +] +) +end &101 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2077,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2078,0 +va (VaSet +font "courier,12,0" +) +xt "134000,65600,137800,67000" +st "clock" +blo "134000,66800" +tm "WireNameMgr" +) +) +on &39 +) +*196 (Wire +uid 2079,0 +shape (OrthoPolyLine +uid 2080,0 +va (VaSet +vasetType 3 +) +xt "134000,69000,137250,69000" +pts [ +"134000,69000" +"137250,69000" +] +) +end &105 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2085,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2086,0 +va (VaSet +font "courier,12,0" +) +xt "133000,67600,137100,69000" +st "reset" +blo "133000,68800" +tm "WireNameMgr" +) +) +on &16 +) +*197 (Wire +uid 2234,0 +shape (OrthoPolyLine +uid 2235,0 +va (VaSet +vasetType 3 +) +xt "10000,27000,17250,27000" +pts [ +"10000,27000" +"17250,27000" +] +) +start &13 +end &71 +es 0 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2240,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2241,0 +va (VaSet +font "courier,12,0" +) +xt "10000,25600,15000,27000" +st "ramWr" +blo "10000,26800" +tm "WireNameMgr" +) +) +on &14 +) +*198 (Wire +uid 2242,0 +shape (OrthoPolyLine +uid 2243,0 +va (VaSet +vasetType 3 +) +xt "14000,33000,17250,33000" +pts [ +"14000,33000" +"17250,33000" +] +) +end &70 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2248,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2249,0 +va (VaSet +font "courier,12,0" +) +xt "14000,31600,17800,33000" +st "clock" +blo "14000,32800" +tm "WireNameMgr" +) +) +on &39 +) +*199 (Wire +uid 2250,0 +shape (OrthoPolyLine +uid 2251,0 +va (VaSet +vasetType 3 +) +xt "14000,35000,17250,35000" +pts [ +"14000,35000" +"17250,35000" +] +) +end &72 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2256,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2257,0 +va (VaSet +font "courier,12,0" +) +xt "13000,33600,17100,35000" +st "reset" +blo "13000,34800" +tm "WireNameMgr" +) +) +on &16 +) +*200 (Wire +uid 2258,0 +shape (OrthoPolyLine +uid 2259,0 +va (VaSet +vasetType 3 +) +xt "34750,27000,42000,27000" +pts [ +"34750,27000" +"42000,27000" +] +) +start &74 +ss 0 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2264,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2265,0 +va (VaSet +font "courier,12,0" +) +xt "36000,25600,46000,27000" +st "writeRequest" +blo "36000,26800" +tm "WireNameMgr" +) +) +on &67 +) +*201 (Wire +uid 2268,0 +shape (OrthoPolyLine +uid 2269,0 +va (VaSet +vasetType 3 +) +xt "10000,29000,17250,29000" +pts [ +"17250,29000" +"10000,29000" +] +) +start &73 +ss 0 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2274,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2275,0 +va (VaSet +font "courier,12,0" +) +xt "11000,27600,17100,29000" +st "writeAck" +blo "11000,28800" +tm "WireNameMgr" +) +) +on &68 +) +*202 (Wire +uid 2342,0 +shape (OrthoPolyLine +uid 2343,0 +va (VaSet +vasetType 3 +) +xt "50000,45000,57250,45000" +pts [ +"57250,45000" +"50000,45000" +] +) +start &157 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2348,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2349,0 +va (VaSet +font "courier,12,0" +) +xt "49000,43600,55100,45000" +st "writeAck" +blo "49000,44800" +tm "WireNameMgr" +) +) +on &68 +) +*203 (Wire +uid 2350,0 +shape (OrthoPolyLine +uid 2351,0 +va (VaSet +vasetType 3 +) +xt "50000,43000,57250,43000" +pts [ +"57250,43000" +"50000,43000" +] +) +start &158 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2356,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2357,0 +va (VaSet +font "courier,12,0" +) +xt "48000,41600,58000,43000" +st "writeRequest" +blo "48000,42800" +tm "WireNameMgr" +) +) +on &67 +) +*204 (Wire +uid 2358,0 +shape (OrthoPolyLine +uid 2359,0 +va (VaSet +vasetType 3 +) +xt "74750,45000,82000,45000" +pts [ +"74750,45000" +"82000,45000" +] +) +start &144 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 2364,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2365,0 +va (VaSet +font "courier,12,0" +) +xt "76000,43600,85100,45000" +st "addrSelRow" +blo "76000,44800" +tm "WireNameMgr" +) +) +on &78 +) +*205 (Wire +uid 2368,0 +shape (OrthoPolyLine +uid 2369,0 +va (VaSet +vasetType 3 +) +xt "130000,43000,137250,43000" +pts [ +"130000,43000" +"137250,43000" +] +) +end &133 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2374,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2375,0 +va (VaSet +font "courier,12,0" +) +xt "128000,41600,137100,43000" +st "addrSelRow" +blo "128000,42800" +tm "WireNameMgr" +) +) +on &78 +) +*206 (Wire +uid 2376,0 +shape (OrthoPolyLine +uid 2377,0 +va (VaSet +vasetType 3 +) +xt "74750,47000,82000,47000" +pts [ +"74750,47000" +"82000,47000" +] +) +start &141 +sat 32 +eat 16 +st 0 +sf 1 +si 0 +tg (WTG +uid 2382,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2383,0 +va (VaSet +font "courier,12,0" +) +xt "76000,45600,84400,47000" +st "addrSelCol" +blo "76000,46800" +tm "WireNameMgr" +) +) +on &79 +) +*207 (Wire +uid 2386,0 +shape (OrthoPolyLine +uid 2387,0 +va (VaSet +vasetType 3 +) +xt "130000,45000,137250,45000" +pts [ +"130000,45000" +"137250,45000" +] +) +end &130 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2392,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2393,0 +va (VaSet +font "courier,12,0" +) +xt "128000,43600,136400,45000" +st "addrSelCol" +blo "128000,44800" +tm "WireNameMgr" +) +) +on &79 +) +*208 (Wire +uid 2428,0 +shape (OrthoPolyLine +uid 2429,0 +va (VaSet +vasetType 3 +) +xt "14000,57000,17250,57000" +pts [ +"14000,57000" +"17250,57000" +] +) +end &83 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2432,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2433,0 +va (VaSet +font "courier,12,0" +) +xt "13000,55600,17100,57000" +st "reset" +blo "13000,56800" +tm "WireNameMgr" +) +) +on &16 +) +*209 (Wire +uid 2434,0 +shape (OrthoPolyLine +uid 2435,0 +va (VaSet +vasetType 3 +) +xt "14000,55000,17250,55000" +pts [ +"14000,55000" +"17250,55000" +] +) +end &81 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2438,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2439,0 +va (VaSet +font "courier,12,0" +) +xt "14000,53600,17800,55000" +st "clock" +blo "14000,54800" +tm "WireNameMgr" +) +) +on &39 +) +*210 (Wire +uid 2440,0 +shape (OrthoPolyLine +uid 2441,0 +va (VaSet +vasetType 3 +) +xt "10000,51000,17250,51000" +pts [ +"17250,51000" +"10000,51000" +] +) +start &84 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2446,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2447,0 +va (VaSet +font "courier,12,0" +) +xt "11000,49600,16800,51000" +st "readAck" +blo "11000,50800" +tm "WireNameMgr" +) +) +on &89 +) +*211 (Wire +uid 2448,0 +shape (OrthoPolyLine +uid 2449,0 +va (VaSet +vasetType 3 +) +xt "34750,49000,42000,49000" +pts [ +"34750,49000" +"42000,49000" +] +) +start &85 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2454,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2455,0 +va (VaSet +font "courier,12,0" +) +xt "36000,47600,45700,49000" +st "readRequest" +blo "36000,48800" +tm "WireNameMgr" +) +) +on &90 +) +*212 (Wire +uid 2460,0 +shape (OrthoPolyLine +uid 2461,0 +va (VaSet +vasetType 3 +) +xt "50000,47000,57250,47000" +pts [ +"57250,47000" +"50000,47000" +] +) +start &152 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2466,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2467,0 +va (VaSet +font "courier,12,0" +) +xt "49000,45600,58700,47000" +st "readRequest" +blo "49000,46800" +tm "WireNameMgr" +) +) +on &90 +) +*213 (Wire +uid 2468,0 +shape (OrthoPolyLine +uid 2469,0 +va (VaSet +vasetType 3 +) +xt "50000,49000,57250,49000" +pts [ +"57250,49000" +"50000,49000" +] +) +start &151 +sat 32 +eat 16 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG 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(RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*351 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*352 (GroupColHdr +tm "GroupColHdrMgr" +) +*353 (NameColHdr +tm "GenericNameColHdrMgr" +) +*354 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*355 (InitColHdr +tm "GenericValueColHdrMgr" +) +*356 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*357 (EolColHdr +tm "GenericEolColHdrMgr" +) +*358 (LogGeneric +generic (GiElement +name "addressBitNb" +type "positive" +value "24" +) +uid 852,0 +) +*359 (LogGeneric +generic (GiElement +name "dataBitNb" +type "positive" +value "16" +) +uid 854,0 +) +*360 (LogGeneric +generic (GiElement +name "chipAddressBitNb" +type "positive" +value "12" +) +uid 1038,0 +) +*361 (LogGeneric +generic (GiElement +name "chipBankAddressBitNb" +type "positive" +value "2" +) +uid 1444,0 +) +*362 (LogGeneric +generic (GiElement +name "rowAddressBitNb" +type "positive" +value "12" +) +uid 3935,0 +) +*363 (LogGeneric +generic (GiElement +name "colAddressBitNb" +type "positive" +value "9" +) +uid 3937,0 +) +*364 (LogGeneric +generic (GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +uid 4122,0 +) +*365 (LogGeneric +generic (GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +uid 4124,0 +) +*366 (LogGeneric +generic (GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +uid 4126,0 +) +*367 (LogGeneric +generic (GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +uid 4128,0 +) +*368 (LogGeneric +generic (GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +uid 4130,0 +) +*369 (LogGeneric +generic (GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +uid 4132,0 +) +*370 (LogGeneric +generic (GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +uid 4134,0 +) +*371 (LogGeneric +generic (GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +uid 4136,0 +) +*372 (LogGeneric +generic (GiElement +name "delayCounterbitNb" +type "positive" +value "13" +e "66MHz * 100us = 6600 < 8K" +) +uid 4138,0 +) +*373 (LogGeneric +generic (GiElement +name "refreshPeriodNb" +type "positive" +value "1031" +e "66MHz * 64ms / 4096" +) +uid 4140,0 +) +*374 (LogGeneric +generic (GiElement +name "maxDelayPeriodNb" +type "positive" +value "5" +e "66MHz*66ns = 4.356" +) +uid 4341,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 399,0 +optionalChildren [ +*375 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *376 (MRCItem +litem &346 +pos 17 +dimension 20 +) +uid 401,0 +optionalChildren [ +*377 (MRCItem +litem &347 +pos 0 +dimension 20 +uid 402,0 +) +*378 (MRCItem +litem &348 +pos 1 +dimension 23 +uid 403,0 +) +*379 (MRCItem +litem &349 +pos 2 +hidden 1 +dimension 20 +uid 404,0 +) +*380 (MRCItem +litem &358 +pos 0 +dimension 20 +uid 851,0 +) +*381 (MRCItem +litem &359 +pos 1 +dimension 20 +uid 853,0 +) +*382 (MRCItem +litem &360 +pos 2 +dimension 20 +uid 1037,0 +) +*383 (MRCItem +litem &361 +pos 3 +dimension 20 +uid 1443,0 +) +*384 (MRCItem +litem &362 +pos 4 +dimension 20 +uid 3936,0 +) +*385 (MRCItem +litem &363 +pos 5 +dimension 20 +uid 3938,0 +) +*386 (MRCItem +litem &364 +pos 6 +dimension 20 +uid 4123,0 +) +*387 (MRCItem +litem &365 +pos 7 +dimension 20 +uid 4125,0 +) +*388 (MRCItem +litem &366 +pos 8 +dimension 20 +uid 4127,0 +) +*389 (MRCItem +litem &367 +pos 9 +dimension 20 +uid 4129,0 +) +*390 (MRCItem +litem &368 +pos 10 +dimension 20 +uid 4131,0 +) +*391 (MRCItem +litem &369 +pos 11 +dimension 20 +uid 4133,0 +) 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386,0 +type 1 +) +activeModelName "BlockDiag:GEN" +) diff --git a/Libs/Memory/hds/sdram@controller/symbol.sb b/Libs/Memory/hds/sdram@controller/symbol.sb new file mode 100644 index 0000000..0ae9d39 --- /dev/null +++ b/Libs/Memory/hds/sdram@controller/symbol.sb @@ -0,0 +1,2973 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 44,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 186,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm 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"57000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 321,0 +va (VaSet +font "courier,8,0" +) +xt "0,21400,33500,22300" +st "memDataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "memDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 26,0 +) +) +) +*135 (CptPort +uid 322,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 323,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,19625,58750,20375" +) +tg (CPTG +uid 324,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 325,0 +va (VaSet +) +xt "53200,19500,57000,20500" +st "memWr_n" +ju 2 +blo "57000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 326,0 +va (VaSet +font "courier,8,0" +) +xt "0,22300,19000,23200" +st "memWr_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "memWr_n" +t "std_ulogic" +o 12 +suid 27,0 +) +) +) +*136 (CptPort +uid 327,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 328,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,27625,42000,28375" +) +tg (CPTG +uid 329,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 330,0 +va (VaSet +) +xt "43000,27500,45600,28500" +st "ramEn" +blo "43000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 331,0 +va (VaSet +font "courier,8,0" +) +xt "0,16000,19000,16900" +st "ramEn : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 5 +suid 28,0 +) +) +) +*137 (CptPort +uid 332,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 333,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,11625,42000,12375" +) +tg (CPTG +uid 334,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 335,0 +va (VaSet +) +xt "43000,11500,45700,12500" +st "ramRd" +blo "43000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 336,0 +va (VaSet +font "courier,8,0" +) +xt "0,16900,19000,17800" +st "ramRd : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramRd" +t "std_ulogic" +o 6 +suid 29,0 +) +) +) +*138 (CptPort +uid 337,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 338,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,13625,42000,14375" +) +tg (CPTG +uid 339,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 340,0 +va (VaSet +) +xt "43000,13500,45700,14500" +st "ramWr" +blo "43000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 341,0 +va (VaSet +font "courier,8,0" +) +xt "0,17800,19000,18700" +st "ramWr : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramWr" +t "std_ulogic" +o 7 +suid 30,0 +) +) +) +*139 (CptPort +uid 342,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 343,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,31625,42000,32375" +) +tg (CPTG +uid 344,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 345,0 +va (VaSet +) +xt "43000,31500,45100,32500" +st "reset" +blo "43000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 346,0 +va (VaSet +font "courier,8,0" +) +xt "0,18700,19000,19600" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 31,0 +) +) +) +*140 (CptPort +uid 347,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 348,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,17625,58750,18375" +) +tg (CPTG +uid 349,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 350,0 +va (VaSet +) +xt "53600,17500,57000,18500" +st "sdCas_n" +ju 2 +blo "57000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 351,0 +va (VaSet +font "courier,8,0" +) +xt "0,25000,19000,25900" +st "sdCas_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCas_n" +t "std_ulogic" +o 15 +suid 32,0 +) +) +) +*141 (CptPort +uid 352,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 353,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,23625,58750,24375" +) +tg (CPTG +uid 354,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 355,0 +va (VaSet +) +xt "54500,23500,57000,24500" +st "sdCke" +ju 2 +blo "57000,24300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 356,0 +va (VaSet +font "courier,8,0" +) +xt "0,25900,19000,26800" +st "sdCke : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCke" +t "std_ulogic" +o 16 +suid 33,0 +) +) +) +*142 (CptPort +uid 357,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 358,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,25625,58750,26375" +) +tg (CPTG +uid 359,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 360,0 +va (VaSet +) +xt "54700,25500,57000,26500" +st "sdClk" +ju 2 +blo "57000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 361,0 +va (VaSet +font "courier,8,0" +) +xt "0,26800,19000,27700" +st "sdClk : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdClk" +t "std_ulogic" +o 17 +suid 34,0 +) +) +) +*143 (CptPort +uid 362,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 363,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,13625,58750,14375" +) +tg (CPTG +uid 364,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 365,0 +va (VaSet +) +xt "54000,13500,57000,14500" +st "sdCs_n" +ju 2 +blo "57000,14300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 366,0 +va (VaSet +font "courier,8,0" +) +xt "0,27700,19000,28600" +st "sdCs_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 18 +suid 35,0 +) +) +) +*144 (CptPort +uid 367,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 368,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,21625,58750,22375" +) +tg (CPTG +uid 369,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 370,0 +va (VaSet +) +xt "54100,21500,57000,22500" +st "sdDqm" +ju 2 +blo "57000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 371,0 +va (VaSet +font "courier,8,0" +) +xt "0,28600,28500,29500" +st "sdDqm : OUT std_ulogic_vector (1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 19 +suid 36,0 +) +) +) +*145 (CptPort +uid 377,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 378,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,15625,58750,16375" +) +tg (CPTG +uid 379,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 380,0 +va (VaSet +) +xt "53600,15500,57000,16500" +st "sdRas_n" +ju 2 +blo "57000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 381,0 +va (VaSet +font "courier,8,0" +) +xt "0,29500,19000,30400" +st "sdRas_n : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 20 +suid 38,0 +) +) +) +*146 (CptPort +uid 487,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 518,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41250,7625,42000,8375" +) +tg (CPTG +uid 489,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 490,0 +va (VaSet +) +xt "43000,7500,46900,8500" +st "ramDataIn" +blo "43000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 491,0 +va (VaSet +font "courier,8,0" +) +xt "0,23200,33500,24100" +st "ramDataIn : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 13 +suid 42,0 +) +) +) +*147 (CptPort +uid 548,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 549,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,7625,58750,8375" +) +tg (CPTG +uid 550,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 551,0 +va (VaSet +) +xt "50200,7500,57000,8500" +st "memBankAddress" +ju 2 +blo "57000,8300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 552,0 +va (VaSet +font "courier,8,0" +) +xt "0,20500,40000,21400" +st "memBankAddress : OUT std_ulogic_vector ( chipBankAddressBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "memBankAddress" +t "std_ulogic_vector" +b "( chipBankAddressBitNb-1 DOWNTO 0 )" +o 10 +suid 43,0 +) +) +) +*148 (CptPort +uid 651,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 652,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "58000,29625,58750,30375" +) +tg (CPTG +uid 653,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 654,0 +va (VaSet +) +xt "51500,29500,57000,30500" +st "selectRefresh" +ju 2 +blo "57000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 655,0 +va (VaSet +font "courier,8,0" +) +xt "0,30400,18000,31300" +st "selectRefresh : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "selectRefresh" +t "std_ulogic" +o 21 +suid 44,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "42000,2000,58000,34000" +) +oxt "15000,6000,31000,34000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "courier,8,1" +) +xt "42550,34500,45550,35400" +st "Memory" +blo "42550,35200" +) +second (Text +uid 12,0 +va (VaSet +font "courier,8,1" +) +xt "42550,35400,50550,36300" +st "sdramController" +blo "42550,36100" +) +) +gi *149 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "42000,38200,77500,55300" +st "Generic Declarations + +addressBitNb positive 24 +dataBitNb positive 16 +chipAddressBitNb positive 12 +chipBankAddressBitNb positive 2 +rowAddressBitNb positive 12 +colAddressBitNb positive 9 +activeToReadPeriodNb positive 2 --66MHz * 20ns = 1.32 +activeToWritePeriodNb positive 2 --66MHz * 20ns = 1.32 +loadModeToActivePeriodNb positive 1 --1 CK +prechargeToRefreshPeriodNb positive 2 --66MHz * 20 ns = 1.32 +readToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 +readToSamplePeriodNb positive 2 --2 CK with latency = 2 +refreshDelayPeriodNb positive 5 --66MHz * 66ns = 4.356 +writeToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 +delayCounterbitNb positive 13 --66MHz * 100us = 6600 < 8K +refreshPeriodNb positive 1031 --66MHz * 64ms / 4096 +maxDelayPeriodNb positive 5 --66MHz*66ns = 4.356 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "addressBitNb" +type "positive" +value "24" +) +(GiElement +name "dataBitNb" +type "positive" +value "16" +) +(GiElement +name "chipAddressBitNb" +type "positive" +value "12" +) +(GiElement +name "chipBankAddressBitNb" +type "positive" +value "2" +) +(GiElement +name "rowAddressBitNb" +type "positive" +value "12" +) +(GiElement +name "colAddressBitNb" +type "positive" +value "9" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "delayCounterbitNb" +type "positive" +value "13" +e "66MHz * 100us = 6600 < 8K" +) +(GiElement +name "refreshPeriodNb" +type "positive" +value "1031" +e "66MHz * 64ms / 4096" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "5" +e "66MHz*66ns = 4.356" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*150 (Grouping +uid 16,0 +optionalChildren [ +*151 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,48000,51000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,48000,49200,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*152 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,44000,55000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,44000,54800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*153 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,46000,51000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,46000,50400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*154 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,46000,34000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,46000,33800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*155 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,45000,71000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,45200,64400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) 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"/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "fsm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@fsm" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerFsm" +) +(vvPair +variable "date" +value "08/28/19" +) +(vvPair +variable "day" +value "Wed" +) +(vvPair +variable "day_long" +value "Wednesday" +) +(vvPair +variable "dd" +value "28" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "sdramControllerFsm" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "fsm.sm" +) +(vvPair +variable "f_logical" +value "fsm.sm" +) +(vvPair +variable "f_noext" +value "fsm" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/28/19" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphelia" +) +(vvPair +variable "graphical_source_time" +value "13:45:15" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphelia" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "Memory" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libs/Memory/work" +) +(vvPair +variable "mm" +value "08" +) +(vvPair +variable "module_name" +value "sdramControllerFsm" +) +(vvPair +variable "month" +value "Aug" +) +(vvPair +variable "month_long" +value "August" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdram@controller@fsm/fsm.sm" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/sdramControllerFsm/fsm.sm" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sm" +) +(vvPair +variable "this_file" +value "fsm" +) +(vvPair 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"106200,96000,109800,97000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*18 (CommentText +uid 149,0 +shape (Rectangle +uid 150,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "110000,95000,127000,96000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 151,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "110200,95000,126400,96000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 121,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "106000,92000,147000,97000" +) +oxt "14000,66000,55000,71000" +) +*19 (State +uid 229,0 +shape (Circle +uid 230,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,24000,30000,32000" +radius 4000 +) +name (Text +uid 231,0 +va (VaSet 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3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23600,29150,34400,29150" +pts [ +"23600,29150" +"34400,29150" +] +) +ttri (Triangle +uid 241,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,27925,23500,28275" +) +btri (Triangle +uid 242,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,26625,23500,26975" +) +entryActions (MLText +uid 243,0 +va (VaSet +) +xt "23600,28100,23600,28100" +tm "Actions" +) +inActions (MLText +uid 244,0 +va (VaSet +) +xt "23600,28500,38600,31500" +st "commandBus <= precharge; +addrSelPrecharge <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 245,0 +va (VaSet +) +xt "25000,26800,25000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 235,0 +ps "CenterOffsetStrategy" +text (MLText +uid 236,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt 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"43900,29900,44100,30100" +) +autoResize 1 +tline (Line +uid 295,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,29300,48850,29300" +pts [ +"39150,29300" +"48850,29300" +] +) +bline (Line +uid 296,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,28650,48850,28650" +pts [ +"39150,28650" +"48850,28650" +] +) +ttri (Triangle +uid 297,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,28925,39900,29275" +) +btri (Triangle +uid 298,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,26625,39900,26975" +) +entryActions (MLText +uid 299,0 +va (VaSet +) +xt "39150,29100,39150,29100" +tm "Actions" +) +inActions (MLText +uid 300,0 +va (VaSet +) +xt "39150,29500,48850,30500" +tm "Actions" +) +exitActions (MLText +uid 301,0 +va (VaSet +) +xt "40000,26800,40000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 291,0 +ps "CenterOffsetStrategy" +text (MLText +uid 292,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,29000,45900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*21 (State +uid 334,0 +shape (Circle +uid 335,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,24000,62000,32000" +radius 4000 +) +name (Text +uid 336,0 +va (VaSet +font "courier,10,1" +) +xt "55050,27400,60950,28600" +st "initialize3" +ju 0 +blo "58000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 337,0 +ps "CenterOffsetStrategy" +text (Text +uid 338,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,28300,61700,29500" +st "wait 2" +blo "58100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 339,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,29000,58000,29000" +blo "58000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 342,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 343,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56200,28900,67800,31100" +) +autoResize 1 +tline (Line +uid 344,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,28800,67700,28800" +pts [ +"56300,28800" +"67700,28800" +] +) +bline (Line +uid 345,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,28900,67700,28900" +pts [ +"56300,28900" +"67700,28900" +] +) +ttri (Triangle +uid 346,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,28425,56200,28775" +) +btri (Triangle +uid 347,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,26625,56200,26975" +) +entryActions (MLText +uid 348,0 +va (VaSet +) +xt "56300,28600,56300,28600" +tm "Actions" +) +inActions (MLText +uid 349,0 +va (VaSet +) +xt "56300,29000,72500,31000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 350,0 +va (VaSet +) +xt "58000,26800,58000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 340,0 +ps "CenterOffsetStrategy" +text (MLText +uid 341,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,29000,61900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*22 (State +uid 361,0 +shape (Circle +uid 362,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,24000,78000,32000" +radius 4000 +) +name (Text +uid 363,0 +va (VaSet +font "courier,10,1" +) +xt "71050,27400,76950,28600" +st "initialize4" +ju 0 +blo "74000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 364,0 +ps "CenterOffsetStrategy" +text (Text +uid 365,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,28300,77700,29500" +st "wait 2" +blo "74100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 366,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,29000,74000,29000" +blo "74000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 369,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 370,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,29900,78100,30100" +) +autoResize 1 +tline (Line +uid 371,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,28800,84300,28800" +pts [ +"71700,28800" +"84300,28800" +] +) +bline (Line +uid 372,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,28900,84300,28900" +pts [ +"71700,28900" +"84300,28900" +] +) +ttri (Triangle +uid 373,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,28425,73900,28775" +) +btri (Triangle +uid 374,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,26625,73900,26975" +) +entryActions (MLText +uid 375,0 +va (VaSet +) +xt "71700,28600,71700,28600" +tm "Actions" +) +inActions (MLText +uid 376,0 +va (VaSet +) +xt "71700,29000,84300,31000" +tm "Actions" +) +exitActions (MLText +uid 377,0 +va (VaSet +) +xt "74000,26800,74000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 367,0 +ps "CenterOffsetStrategy" +text (MLText +uid 368,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,29000,77900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*23 (State +uid 378,0 +shape (Circle +uid 379,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "86000,24000,94000,32000" +radius 4000 +) +name (Text +uid 380,0 +va (VaSet +font "courier,10,1" +) +xt "87050,27400,92950,28600" +st "initialize5" +ju 0 +blo "90000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 381,0 +ps "CenterOffsetStrategy" +text (Text +uid 382,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "90100,28300,93700,29500" +st "wait 2" +blo "90100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 383,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "90000,29000,90000,29000" +blo "90000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 386,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 387,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "88200,28900,99800,31100" +) +autoResize 1 +tline (Line +uid 388,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,28800,99700,28800" +pts [ +"88300,28800" +"99700,28800" +] +) +bline (Line +uid 389,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,28900,99700,28900" +pts [ +"88300,28900" +"99700,28900" +] +) +ttri (Triangle +uid 390,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,28425,88200,28775" +) +btri (Triangle +uid 391,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,26625,88200,26975" +) +entryActions (MLText +uid 392,0 +va (VaSet +) +xt "88300,28600,88300,28600" +tm "Actions" +) +inActions (MLText +uid 393,0 +va (VaSet +) +xt "88300,29000,104500,31000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 394,0 +va (VaSet +) +xt "90000,26800,90000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 384,0 +ps "CenterOffsetStrategy" +text (MLText +uid 385,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "88400,29000,93900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*24 (State +uid 415,0 +shape (Circle +uid 416,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "102000,24000,110000,32000" +radius 4000 +) +name (Text +uid 417,0 +va (VaSet +font "courier,10,1" +) +xt "103050,27400,108950,28600" +st "initialize6" +ju 0 +blo "106000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 418,0 +ps "CenterOffsetStrategy" +text (Text +uid 419,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "106100,28300,109700,29500" +st "wait 2" +blo "106100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 420,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "106000,29000,106000,29000" +blo "106000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 423,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 424,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "109900,29900,110100,30100" +) +autoResize 1 +tline (Line +uid 425,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,28800,116300,28800" +pts [ +"103700,28800" +"116300,28800" +] +) +bline (Line +uid 426,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,28900,116300,28900" +pts [ +"103700,28900" +"116300,28900" +] +) +ttri (Triangle +uid 427,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,28425,105900,28775" +) +btri (Triangle +uid 428,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,26625,105900,26975" +) +entryActions (MLText +uid 429,0 +va (VaSet +) +xt "103700,28600,103700,28600" +tm "Actions" +) +inActions (MLText +uid 430,0 +va (VaSet +) +xt "103700,29000,116300,31000" +tm "Actions" +) +exitActions (MLText +uid 431,0 +va (VaSet +) +xt "106000,26800,106000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 421,0 +ps "CenterOffsetStrategy" +text (MLText +uid 422,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "104400,29000,109900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*25 (State +uid 502,0 +shape (Circle +uid 503,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "118000,24000,126000,32000" +radius 4000 +) +name (Text +uid 504,0 +va (VaSet +font "courier,10,1" +) +xt "119050,27400,124950,28600" +st "initialize7" +ju 0 +blo "122000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 505,0 +ps "CenterOffsetStrategy" +text (Text +uid 506,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "122100,28300,125700,29500" +st "wait 2" +blo "122100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 507,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "122000,29000,122000,29000" +blo "122000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 510,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 511,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "119850,28400,132150,31600" +) +autoResize 1 +tline (Line +uid 512,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119950,28300,132050,28300" +pts [ +"119950,28300" +"132050,28300" +] +) +bline (Line +uid 513,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119950,29150,132050,29150" +pts [ +"119950,29150" +"132050,29150" +] +) +ttri (Triangle +uid 514,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119500,27925,119850,28275" +) +btri (Triangle +uid 515,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "119500,26625,119850,26975" +) +entryActions (MLText +uid 516,0 +va (VaSet +) +xt "119950,28100,119950,28100" +tm "Actions" +) +inActions (MLText +uid 517,0 +va (VaSet +) +xt "119950,28500,136150,31500" +st "commandBus <= loadModeReg; +timerStart <= '1'; +addrSelModeReg <= '1';" +tm "Actions" +) +exitActions (MLText +uid 518,0 +va (VaSet +) +xt "122000,26800,122000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 508,0 +ps "CenterOffsetStrategy" +text (MLText +uid 509,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "120400,29000,125900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*26 (State +uid 531,0 +shape (Circle +uid 532,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "134000,24000,142000,32000" +radius 4000 +) +name (Text +uid 533,0 +va (VaSet +font "courier,10,1" +) +xt "135050,27400,140950,28600" +st "initialize8" +ju 0 +blo "138000,28400" +tm "ONodeName" +) +wait (TextAssociate +uid 534,0 +ps "CenterOffsetStrategy" +text (Text +uid 535,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "138100,28300,141700,29500" +st "wait 2" +blo "138100,29300" +tm "SmWaitText" +) +) +encoding (Text +uid 536,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "138000,29000,138000,29000" +blo "138000,29000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 539,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 540,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "141900,29900,142100,30100" +) +autoResize 1 +tline (Line +uid 541,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "135700,28800,148300,28800" +pts [ +"135700,28800" +"148300,28800" +] +) +bline (Line +uid 542,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "135700,28900,148300,28900" +pts [ +"135700,28900" +"148300,28900" +] +) +ttri (Triangle +uid 543,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "137550,28425,137900,28775" +) +btri (Triangle +uid 544,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "137550,26625,137900,26975" +) +entryActions (MLText +uid 545,0 +va (VaSet +) +xt "135700,28600,135700,28600" +tm "Actions" +) +inActions (MLText +uid 546,0 +va (VaSet +) +xt "135700,29000,148300,31000" +tm "Actions" +) +exitActions (MLText +uid 547,0 +va (VaSet +) +xt "138000,26800,138000,26800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 537,0 +ps "CenterOffsetStrategy" +text (MLText +uid 538,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "136400,29000,141900,29900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*27 (State +uid 558,0 +shape (Circle +uid 559,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "6000,40000,14000,48000" +radius 4000 +) +name (Text +uid 560,0 +va (VaSet +font "courier,10,1" +) +xt "8800,43400,11200,44600" +st "idle" +ju 0 +blo "10000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 561,0 +ps "CenterOffsetStrategy" +text (Text +uid 562,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "10100,44300,13700,45500" +st "wait 2" +blo "10100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 563,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "10000,45000,10000,45000" +blo "10000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 566,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 567,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "11900,45900,12100,46100" +) +autoResize 1 +tline (Line +uid 568,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "8000,45300,16000,45300" +pts [ +"8000,45300" +"16000,45300" +] +) +bline (Line +uid 569,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "8000,44650,16000,44650" +pts [ +"8000,44650" +"16000,44650" +] +) +ttri (Triangle +uid 570,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "7550,44925,7900,45275" +) +btri (Triangle +uid 571,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "7550,42625,7900,42975" +) +entryActions (MLText +uid 572,0 +va (VaSet +) +xt "8000,45100,8000,45100" +tm "Actions" +) +inActions (MLText +uid 573,0 +va (VaSet +) +xt "8000,45500,16000,46500" +tm "Actions" +) +exitActions (MLText +uid 574,0 +va (VaSet +) +xt "8000,42800,8000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 564,0 +ps "CenterOffsetStrategy" +text (MLText +uid 565,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "8400,45000,13900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*28 (Junction +uid 575,0 +shape (Diamond +uid 576,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "8350,34350,11650,37650" +) +symbol (Text +uid 577,0 +va (VaSet +font "courier,10,1" +) +xt "9350,35400,10650,36600" +st "&" +ju 0 +blo "10000,36400" +) +name (TextAssociate +uid 578,0 +ps "CenterOffsetStrategy" +text (Text +uid 579,0 +va (VaSet +font "courier,8,1" +) +xt "11500,36500,11500,36500" +blo "11500,36500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 580,0 +ps "CenterOffsetStrategy" +text (MLText +uid 581,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "7650,37500,13150,38400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*29 (Junction +uid 592,0 +shape (Diamond +uid 593,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "136350,34350,139650,37650" +) +symbol (Text +uid 594,0 +va (VaSet +font "courier,10,1" +) +xt "137350,35400,138650,36600" +st "&" +ju 0 +blo "138000,36400" +) +name (TextAssociate +uid 595,0 +ps "CenterOffsetStrategy" +text (Text +uid 596,0 +va (VaSet +font "courier,8,1" +) +xt "139500,36500,139500,36500" +blo "139500,36500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 597,0 +ps "CenterOffsetStrategy" +text (MLText +uid 598,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "135650,37500,141150,38400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*30 (State +uid 629,0 +shape (Circle +uid 630,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,40000,30000,48000" +radius 4000 +) +name (Text +uid 631,0 +va (VaSet +font "courier,10,1" +) +xt "23650,43400,28350,44600" +st "refresh1" +ju 0 +blo "26000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 632,0 +ps "CenterOffsetStrategy" +text (Text +uid 633,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "26100,44300,29700,45500" +st "wait 2" +blo "26100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 634,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "26000,45000,26000,45000" +blo "26000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 637,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 638,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "23500,45400,34500,48600" +) +autoResize 1 +tline (Line +uid 639,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23600,45300,34400,45300" +pts [ +"23600,45300" +"34400,45300" +] +) +bline (Line +uid 640,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23600,46150,34400,46150" +pts [ +"23600,46150" +"34400,46150" +] +) +ttri (Triangle +uid 641,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,44925,23500,45275" +) +btri (Triangle +uid 642,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23150,43625,23500,43975" +) +entryActions (MLText +uid 643,0 +va (VaSet +) +xt "23600,45100,23600,45100" +tm "Actions" +) +inActions (MLText +uid 644,0 +va (VaSet +) +xt "23600,45500,38600,48500" +st "commandBus <= precharge; +addrSelPrecharge <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 645,0 +va (VaSet +) +xt "25000,43800,25000,43800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 635,0 +ps "CenterOffsetStrategy" +text (MLText +uid 636,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "24400,45000,29900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*31 (State +uid 656,0 +shape (Circle +uid 657,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "38000,40000,46000,48000" +radius 4000 +) +name (Text +uid 658,0 +va (VaSet +font "courier,10,1" +) +xt "39650,43400,44350,44600" +st "refresh2" +ju 0 +blo "42000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 659,0 +ps "CenterOffsetStrategy" +text (Text +uid 660,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "42100,44300,45700,45500" +st "wait 2" +blo "42100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 661,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,45000,42000,45000" +blo "42000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 664,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 665,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "43900,45900,44100,46100" +) +autoResize 1 +tline (Line +uid 666,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,45300,48850,45300" +pts [ +"39150,45300" +"48850,45300" +] +) +bline (Line +uid 667,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,44650,48850,44650" +pts [ +"39150,44650" +"48850,44650" +] +) +ttri (Triangle +uid 668,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,44925,39900,45275" +) +btri (Triangle +uid 669,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,42625,39900,42975" +) +entryActions (MLText +uid 670,0 +va (VaSet +) +xt "39150,45100,39150,45100" +tm "Actions" +) +inActions (MLText +uid 671,0 +va (VaSet +) +xt "39150,45500,48850,46500" +tm "Actions" +) +exitActions (MLText +uid 672,0 +va (VaSet +) +xt "40000,42800,40000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 662,0 +ps "CenterOffsetStrategy" +text (MLText +uid 663,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,45000,45900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*32 (State +uid 673,0 +shape (Circle +uid 674,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,40000,62000,48000" +radius 4000 +) +name (Text +uid 675,0 +va (VaSet +font "courier,10,1" +) +xt "55650,43400,60350,44600" +st "refresh3" +ju 0 +blo "58000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 676,0 +ps "CenterOffsetStrategy" +text (Text +uid 677,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,44300,61700,45500" +st "wait 2" +blo "58100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 678,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,45000,58000,45000" +blo "58000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 681,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 682,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56200,44900,67800,47100" +) +autoResize 1 +tline (Line +uid 683,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,44800,67700,44800" +pts [ +"56300,44800" +"67700,44800" +] +) +bline (Line +uid 684,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56300,44900,67700,44900" +pts [ +"56300,44900" +"67700,44900" +] +) +ttri (Triangle +uid 685,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,44425,56200,44775" +) +btri (Triangle +uid 686,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55850,42625,56200,42975" +) +entryActions (MLText +uid 687,0 +va (VaSet +) +xt "56300,44600,56300,44600" +tm "Actions" +) +inActions (MLText +uid 688,0 +va (VaSet +) +xt "56300,45000,72500,47000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 689,0 +va (VaSet +) +xt "58000,42800,58000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 679,0 +ps "CenterOffsetStrategy" +text (MLText +uid 680,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,45000,61900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*33 (State +uid 690,0 +shape (Circle +uid 691,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,40000,78000,48000" +radius 4000 +) +name (Text +uid 692,0 +va (VaSet +font "courier,10,1" +) +xt "71650,43400,76350,44600" +st "refresh4" +ju 0 +blo "74000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 693,0 +ps "CenterOffsetStrategy" +text (Text +uid 694,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,44300,77700,45500" +st "wait 2" +blo "74100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 695,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,45000,74000,45000" +blo "74000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 698,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 699,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,45900,78100,46100" +) +autoResize 1 +tline (Line +uid 700,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,44800,84300,44800" +pts [ +"71700,44800" +"84300,44800" +] +) +bline (Line +uid 701,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,44900,84300,44900" +pts [ +"71700,44900" +"84300,44900" +] +) +ttri (Triangle +uid 702,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,44425,73900,44775" +) +btri (Triangle +uid 703,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,42625,73900,42975" +) +entryActions (MLText +uid 704,0 +va (VaSet +) +xt "71700,44600,71700,44600" +tm "Actions" +) +inActions (MLText +uid 705,0 +va (VaSet +) +xt "71700,45000,84300,47000" +tm "Actions" +) +exitActions (MLText +uid 706,0 +va (VaSet +) +xt "74000,42800,74000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 696,0 +ps "CenterOffsetStrategy" +text (MLText +uid 697,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,45000,77900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*34 (State +uid 707,0 +shape (Circle +uid 708,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "86000,40000,94000,48000" +radius 4000 +) +name (Text +uid 709,0 +va (VaSet +font "courier,10,1" +) +xt "87650,43400,92350,44600" +st "refresh5" +ju 0 +blo "90000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 710,0 +ps "CenterOffsetStrategy" +text (Text +uid 711,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "90100,44300,93700,45500" +st "wait 2" +blo "90100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 712,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "90000,45000,90000,45000" +blo "90000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 715,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 716,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "88200,44900,99800,47100" +) +autoResize 1 +tline (Line +uid 717,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,44800,99700,44800" +pts [ +"88300,44800" +"99700,44800" +] +) +bline (Line +uid 718,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "88300,44900,99700,44900" +pts [ +"88300,44900" +"99700,44900" +] +) +ttri (Triangle +uid 719,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,44425,88200,44775" +) +btri (Triangle +uid 720,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87850,42625,88200,42975" +) +entryActions (MLText +uid 721,0 +va (VaSet +) +xt "88300,44600,88300,44600" +tm "Actions" +) +inActions (MLText +uid 722,0 +va (VaSet +) +xt "88300,45000,104500,47000" +st "commandBus <= autoRefresh; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 723,0 +va (VaSet +) +xt "90000,42800,90000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 713,0 +ps "CenterOffsetStrategy" +text (MLText +uid 714,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "88400,45000,93900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*35 (State +uid 724,0 +shape (Circle +uid 725,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "102000,40000,110000,48000" +radius 4000 +) +name (Text +uid 726,0 +va (VaSet +font "courier,10,1" +) +xt "102750,43400,109250,44600" +st "initialize13" +ju 0 +blo "106000,44400" +tm "ONodeName" +) +wait (TextAssociate +uid 727,0 +ps "CenterOffsetStrategy" +text (Text +uid 728,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "106100,44300,109700,45500" +st "wait 2" +blo "106100,45300" +tm "SmWaitText" +) +) +encoding (Text +uid 729,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "106000,45000,106000,45000" +blo "106000,45000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 732,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 733,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "109900,45900,110100,46100" +) +autoResize 1 +tline (Line +uid 734,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,44800,116300,44800" +pts [ +"103700,44800" +"116300,44800" +] +) +bline (Line +uid 735,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,44900,116300,44900" +pts [ +"103700,44900" +"116300,44900" +] +) +ttri (Triangle +uid 736,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,44425,105900,44775" +) +btri (Triangle +uid 737,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,42625,105900,42975" +) +entryActions (MLText +uid 738,0 +va (VaSet +) +xt "103700,44600,103700,44600" +tm "Actions" +) +inActions (MLText +uid 739,0 +va (VaSet +) +xt "103700,45000,116300,47000" +tm "Actions" +) +exitActions (MLText +uid 740,0 +va (VaSet +) +xt "106000,42800,106000,42800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 730,0 +ps "CenterOffsetStrategy" +text (MLText +uid 731,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "104400,45000,109900,45900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*36 (Junction +uid 791,0 +shape (Diamond +uid 792,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,34350,115650,37650" +) +symbol (Text +uid 793,0 +va (VaSet +font "courier,10,1" +) +xt "113350,35400,114650,36600" +st "&" +ju 0 +blo "114000,36400" +) +name (TextAssociate +uid 794,0 +ps "CenterOffsetStrategy" +text (Text +uid 795,0 +va (VaSet +font "courier,8,1" +) +xt "115500,36500,115500,36500" +blo "115500,36500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 796,0 +ps "CenterOffsetStrategy" +text (MLText +uid 797,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,37500,117150,38400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*37 (Junction +uid 798,0 +shape (Diamond +uid 799,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,42350,115650,45650" +) +symbol (Text +uid 800,0 +va (VaSet +font "courier,10,1" +) +xt "113350,43400,114650,44600" +st "&" +ju 0 +blo "114000,44400" +) +name (TextAssociate +uid 801,0 +ps "CenterOffsetStrategy" +text (Text +uid 802,0 +va (VaSet +font "courier,8,1" +) +xt "115500,44500,115500,44500" +blo "115500,44500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 803,0 +ps "CenterOffsetStrategy" +text (MLText +uid 804,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,45500,117150,46400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*38 (State +uid 870,0 +shape (Circle +uid 871,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,56000,30000,64000" +radius 4000 +) +name (Text +uid 872,0 +va (VaSet +font "courier,10,1" +) +xt "24150,59400,27850,60600" +st "write1" +ju 0 +blo "26000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 873,0 +ps "CenterOffsetStrategy" +text (Text +uid 874,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "26100,60300,29700,61500" +st "wait 2" +blo "26100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 875,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "26000,61000,26000,61000" +blo "26000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 878,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 879,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "24300,60900,33700,65100" +) +autoResize 1 +tline (Line +uid 880,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,60800,33600,60800" +pts [ +"24400,60800" +"33600,60800" +] +) +bline (Line +uid 881,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,62400,33600,62400" +pts [ +"24400,62400" +"33600,62400" +] +) +ttri (Triangle +uid 882,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,60425,24300,60775" +) +btri (Triangle +uid 883,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,59625,24300,59975" +) +entryActions (MLText +uid 884,0 +va (VaSet +) +xt "24400,60600,24400,60600" +tm "Actions" +) +inActions (MLText +uid 885,0 +va (VaSet +) +xt "24400,61000,37600,65000" +st "commandBus <= active; +writeAck <= '1'; +addrSelRow <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 886,0 +va (VaSet +) +xt "25000,59800,25000,59800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 876,0 +ps "CenterOffsetStrategy" +text (MLText +uid 877,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "24400,61000,29900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*39 (State +uid 887,0 +shape (Circle +uid 888,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "38000,56000,46000,64000" +radius 4000 +) +name (Text +uid 889,0 +va (VaSet +font "courier,10,1" +) +xt "40150,59400,43850,60600" +st "write2" +ju 0 +blo "42000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 890,0 +ps "CenterOffsetStrategy" +text (Text +uid 891,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "42100,60300,45700,61500" +st "wait 2" +blo "42100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 892,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,61000,42000,61000" +blo "42000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 895,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 896,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "43900,61900,44100,62100" +) +autoResize 1 +tline (Line +uid 897,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,61300,48850,61300" +pts [ +"39150,61300" +"48850,61300" +] +) +bline (Line +uid 898,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,60650,48850,60650" +pts [ +"39150,60650" +"48850,60650" +] +) +ttri (Triangle +uid 899,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,60925,39900,61275" +) +btri (Triangle +uid 900,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,58625,39900,58975" +) +entryActions (MLText +uid 901,0 +va (VaSet +) +xt "39150,61100,39150,61100" +tm "Actions" +) +inActions (MLText +uid 902,0 +va (VaSet +) +xt "39150,61500,48850,62500" +tm "Actions" +) +exitActions (MLText +uid 903,0 +va (VaSet +) +xt "40000,58800,40000,58800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 893,0 +ps "CenterOffsetStrategy" +text (MLText +uid 894,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,61000,45900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*40 (State +uid 904,0 +shape (Circle +uid 905,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,56000,62000,64000" +radius 4000 +) +name (Text +uid 906,0 +va (VaSet +font "courier,10,1" +) +xt "56150,59400,59850,60600" +st "write3" +ju 0 +blo "58000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 907,0 +ps "CenterOffsetStrategy" +text (Text +uid 908,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,60300,61700,61500" +st "wait 2" +blo "58100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 909,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,61000,58000,61000" +blo "58000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 912,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 913,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56450,60400,65550,63600" +) +autoResize 1 +tline (Line +uid 914,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56550,60300,65450,60300" +pts [ +"56550,60300" +"65450,60300" +] +) +bline (Line +uid 915,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56550,61150,65450,61150" +pts [ +"56550,61150" +"65450,61150" +] +) +ttri (Triangle +uid 916,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56100,59925,56450,60275" +) +btri (Triangle +uid 917,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56100,58625,56450,58975" +) +entryActions (MLText +uid 918,0 +va (VaSet +) +xt "56550,60100,56550,60100" +tm "Actions" +) +inActions (MLText +uid 919,0 +va (VaSet +) +xt "56550,60500,69150,63500" +st "commandBus <= write; +addrSelCol <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 920,0 +va (VaSet +) +xt "57000,58800,57000,58800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 910,0 +ps "CenterOffsetStrategy" +text (MLText +uid 911,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,61000,61900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*41 (State +uid 921,0 +shape (Circle +uid 922,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,56000,78000,64000" +radius 4000 +) +name (Text +uid 923,0 +va (VaSet +font "courier,10,1" +) +xt "72150,59400,75850,60600" +st "write4" +ju 0 +blo "74000,60400" +tm "ONodeName" +) +wait (TextAssociate +uid 924,0 +ps "CenterOffsetStrategy" +text (Text +uid 925,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,60300,77700,61500" +st "wait 2" +blo "74100,61300" +tm "SmWaitText" +) +) +encoding (Text +uid 926,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,61000,74000,61000" +blo "74000,61000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 929,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 930,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,61900,78100,62100" +) +autoResize 1 +tline (Line +uid 931,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,60800,84300,60800" +pts [ +"71700,60800" +"84300,60800" +] +) +bline (Line +uid 932,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,60900,84300,60900" +pts [ +"71700,60900" +"84300,60900" +] +) +ttri (Triangle +uid 933,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,60425,73900,60775" +) +btri (Triangle +uid 934,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,58625,73900,58975" +) +entryActions (MLText +uid 935,0 +va (VaSet +) +xt "71700,60600,71700,60600" +tm "Actions" +) +inActions (MLText +uid 936,0 +va (VaSet +) +xt "71700,61000,84300,63000" +tm "Actions" +) +exitActions (MLText +uid 937,0 +va (VaSet +) +xt "74000,58800,74000,58800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 927,0 +ps "CenterOffsetStrategy" +text (MLText +uid 928,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,61000,77900,61900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*42 (Junction +uid 978,0 +shape (Diamond +uid 979,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "8350,58350,11650,61650" +) +symbol (Text +uid 980,0 +va (VaSet +font "courier,10,1" +) +xt "9350,59400,10650,60600" +st "&" +ju 0 +blo "10000,60400" +) +name (TextAssociate +uid 981,0 +ps "CenterOffsetStrategy" +text (Text +uid 982,0 +va (VaSet +font "courier,8,1" +) +xt "11500,60500,11500,60500" +blo "11500,60500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 983,0 +ps "CenterOffsetStrategy" +text (MLText +uid 984,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "7650,61500,13150,62400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*43 (Junction +uid 999,0 +shape (Diamond +uid 1000,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,58350,115650,61650" +) +symbol (Text +uid 1001,0 +va (VaSet +font "courier,10,1" +) +xt "113350,59400,114650,60600" +st "&" +ju 0 +blo "114000,60400" +) +name (TextAssociate +uid 1002,0 +ps "CenterOffsetStrategy" +text (Text +uid 1003,0 +va (VaSet +font "courier,8,1" +) +xt "115500,60500,115500,60500" +blo "115500,60500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 1004,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1005,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,61500,117150,62400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*44 (State +uid 1026,0 +shape (Circle +uid 1027,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "22000,72000,30000,80000" +radius 4000 +) +name (Text +uid 1028,0 +va (VaSet +font "courier,10,1" +) +xt "24300,75400,27700,76600" +st "read1" +ju 0 +blo "26000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1029,0 +ps "CenterOffsetStrategy" +text (Text +uid 1030,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "26100,76300,29700,77500" +st "wait 2" +blo "26100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1031,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "26000,77000,26000,77000" +blo "26000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1034,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1035,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "24300,76900,33700,81100" +) +autoResize 1 +tline (Line +uid 1036,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,76800,33600,76800" +pts [ +"24400,76800" +"33600,76800" +] +) +bline (Line +uid 1037,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "24400,78400,33600,78400" +pts [ +"24400,78400" +"33600,78400" +] +) +ttri (Triangle +uid 1038,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,76425,24300,76775" +) +btri (Triangle +uid 1039,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "23950,75625,24300,75975" +) +entryActions (MLText +uid 1040,0 +va (VaSet +) +xt "24400,76600,24400,76600" +tm "Actions" +) +inActions (MLText +uid 1041,0 +va (VaSet +) +xt "24400,77000,37600,81000" +st "commandBus <= active; +readAck <= '1'; +addrSelRow <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 1042,0 +va (VaSet +) +xt "25000,75800,25000,75800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1032,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1033,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "24400,77000,29900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*45 (State +uid 1043,0 +shape (Circle +uid 1044,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "38000,72000,46000,80000" +radius 4000 +) +name (Text +uid 1045,0 +va (VaSet +font "courier,10,1" +) +xt "40300,75400,43700,76600" +st "read2" +ju 0 +blo "42000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1046,0 +ps "CenterOffsetStrategy" +text (Text +uid 1047,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "42100,76300,45700,77500" +st "wait 2" +blo "42100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1048,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,77000,42000,77000" +blo "42000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1051,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1052,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "43900,77900,44100,78100" +) +autoResize 1 +tline (Line +uid 1053,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,77300,48850,77300" +pts [ +"39150,77300" +"48850,77300" +] +) +bline (Line +uid 1054,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "39150,76650,48850,76650" +pts [ +"39150,76650" +"48850,76650" +] +) +ttri (Triangle +uid 1055,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,76925,39900,77275" +) +btri (Triangle +uid 1056,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "39550,74625,39900,74975" +) +entryActions (MLText +uid 1057,0 +va (VaSet +) +xt "39150,77100,39150,77100" +tm "Actions" +) +inActions (MLText +uid 1058,0 +va (VaSet +) +xt "39150,77500,48850,78500" +tm "Actions" +) +exitActions (MLText +uid 1059,0 +va (VaSet +) +xt "40000,74800,40000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1049,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1050,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "40400,77000,45900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*46 (State +uid 1060,0 +shape (Circle +uid 1061,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "54000,72000,62000,80000" +radius 4000 +) +name (Text +uid 1062,0 +va (VaSet +font "courier,10,1" +) +xt "56300,75400,59700,76600" +st "read3" +ju 0 +blo "58000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1063,0 +ps "CenterOffsetStrategy" +text (Text +uid 1064,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "58100,76300,61700,77500" +st "wait 2" +blo "58100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1065,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "58000,77000,58000,77000" +blo "58000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1068,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1069,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "56700,76400,65300,79600" +) +autoResize 1 +tline (Line +uid 1070,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56800,76300,65200,76300" +pts [ +"56800,76300" +"65200,76300" +] +) +bline (Line +uid 1071,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56800,77150,65200,77150" +pts [ +"56800,77150" +"65200,77150" +] +) +ttri (Triangle +uid 1072,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56350,75925,56700,76275" +) +btri (Triangle +uid 1073,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "56350,74625,56700,74975" +) +entryActions (MLText +uid 1074,0 +va (VaSet +) +xt "56800,76100,56800,76100" +tm "Actions" +) +inActions (MLText +uid 1075,0 +va (VaSet +) +xt "56800,76500,68800,79500" +st "commandBus <= read; +addrSelCol <= '1'; +timerStart <= '1';" +tm "Actions" +) +exitActions (MLText +uid 1076,0 +va (VaSet +) +xt "57000,74800,57000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1066,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1067,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "56400,77000,61900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*47 (State +uid 1077,0 +shape (Circle +uid 1078,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "70000,72000,78000,80000" +radius 4000 +) +name (Text +uid 1079,0 +va (VaSet +font "courier,10,1" +) +xt "72300,75400,75700,76600" +st "read4" +ju 0 +blo "74000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1080,0 +ps "CenterOffsetStrategy" +text (Text +uid 1081,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "74100,76300,77700,77500" +st "wait 2" +blo "74100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1082,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "74000,77000,74000,77000" +blo "74000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1085,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1086,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "77900,77900,78100,78100" +) +autoResize 1 +tline (Line +uid 1087,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,76800,84300,76800" +pts [ +"71700,76800" +"84300,76800" +] +) +bline (Line +uid 1088,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "71700,76900,84300,76900" +pts [ +"71700,76900" +"84300,76900" +] +) +ttri (Triangle +uid 1089,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,76425,73900,76775" +) +btri (Triangle +uid 1090,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "73550,74625,73900,74975" +) +entryActions (MLText +uid 1091,0 +va (VaSet +) +xt "71700,76600,71700,76600" +tm "Actions" +) +inActions (MLText +uid 1092,0 +va (VaSet +) +xt "71700,77000,84300,79000" +tm "Actions" +) +exitActions (MLText +uid 1093,0 +va (VaSet +) +xt "74000,74800,74000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1083,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1084,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "72400,77000,77900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*48 (Junction +uid 1094,0 +shape (Diamond +uid 1095,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "112350,74350,115650,77650" +) +symbol (Text +uid 1096,0 +va (VaSet +font "courier,10,1" +) +xt "113350,75400,114650,76600" +st "&" +ju 0 +blo "114000,76400" +) +name (TextAssociate +uid 1097,0 +ps "CenterOffsetStrategy" +text (Text +uid 1098,0 +va (VaSet +font "courier,8,1" +) +xt "115500,76500,115500,76500" +blo "115500,76500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 1099,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1100,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "111650,77500,117150,78400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*49 (Junction +uid 1151,0 +shape (Diamond +uid 1152,0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +) +xt "8350,74350,11650,77650" +) +symbol (Text +uid 1153,0 +va (VaSet +font "courier,10,1" +) +xt "9350,75400,10650,76600" +st "&" +ju 0 +blo "10000,76400" +) +name (TextAssociate +uid 1154,0 +ps "CenterOffsetStrategy" +text (Text +uid 1155,0 +va (VaSet +font "courier,8,1" +) +xt "11500,76500,11500,76500" +blo "11500,76500" +tm "JunctionName" +) +) +caseExpr (TextAssociate +uid 1156,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1157,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "7650,77500,13150,78400" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*50 (State +uid 1217,0 +shape (Circle +uid 1218,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "86000,72000,94000,80000" +radius 4000 +) +name (Text +uid 1219,0 +va (VaSet +font "courier,10,1" +) +xt "88300,75400,91700,76600" +st "read5" +ju 0 +blo "90000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1220,0 +ps "CenterOffsetStrategy" +text (Text +uid 1221,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "90100,76300,93700,77500" +st "wait 2" +blo "90100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1222,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "90000,77000,90000,77000" +blo "90000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1225,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1226,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "87800,76900,96200,79100" +) +autoResize 1 +tline (Line +uid 1227,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87900,76800,96100,76800" +pts [ +"87900,76800" +"96100,76800" +] +) +bline (Line +uid 1228,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87900,76900,96100,76900" +pts [ +"87900,76900" +"96100,76900" +] +) +ttri (Triangle +uid 1229,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87450,76425,87800,76775" +) +btri (Triangle +uid 1230,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "87450,74625,87800,74975" +) +entryActions (MLText +uid 1231,0 +va (VaSet +) +xt "87900,76600,87900,76600" +tm "Actions" +) +inActions (MLText +uid 1232,0 +va (VaSet +) +xt "87900,77000,100500,79000" +st "sampleData <= '1'; +ramDataValid <= '1';" +tm "Actions" +) +exitActions (MLText +uid 1233,0 +va (VaSet +) +xt "88000,74800,88000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1223,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1224,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "88400,77000,93900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*51 (State +uid 1234,0 +shape (Circle +uid 1235,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "102000,72000,110000,80000" +radius 4000 +) +name (Text +uid 1236,0 +va (VaSet +font "courier,10,1" +) +xt "104300,75400,107700,76600" +st "read6" +ju 0 +blo "106000,76400" +tm "ONodeName" +) +wait (TextAssociate +uid 1237,0 +ps "CenterOffsetStrategy" +text (Text +uid 1238,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "courier,10,1" +) +xt "106100,76300,109700,77500" +st "wait 2" +blo "106100,77300" +tm "SmWaitText" +) +) +encoding (Text +uid 1239,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "106000,77000,106000,77000" +blo "106000,77000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 1242,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1243,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "109900,77900,110100,78100" +) +autoResize 1 +tline (Line +uid 1244,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,76800,116300,76800" +pts [ +"103700,76800" +"116300,76800" +] +) +bline (Line +uid 1245,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth 2 +) +xt "103700,76900,116300,76900" +pts [ +"103700,76900" +"116300,76900" +] +) +ttri (Triangle +uid 1246,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,76425,105900,76775" +) +btri (Triangle +uid 1247,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "105550,74625,105900,74975" +) +entryActions (MLText +uid 1248,0 +va (VaSet +) +xt "103700,76600,103700,76600" +tm "Actions" +) +inActions (MLText +uid 1249,0 +va (VaSet +) +xt "103700,77000,116300,79000" +tm "Actions" +) +exitActions (MLText +uid 1250,0 +va (VaSet +) +xt "106000,74800,106000,74800" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 1240,0 +ps "CenterOffsetStrategy" +text (MLText +uid 1241,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "104400,77000,109900,77900" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*52 (Transition +uid 100,0 +shape (Spline +uid 101,0 +va (VaSet +vasetType 3 +) +xt "5500,15000,13000,15000" +pts [ +"5500,15000" +"13000,15000" +] +) +start &4 +end &5 +ss 0 +es 0 +cond "reset = '1'" +tb (TransitionBlock +uid 102,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 103,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "7250,14000,15450,16000" +) +autoResize 1 +lineShape (Line +uid 104,0 +va (VaSet +vasetType 3 +) +xt "7750,15400,14950,15400" +pts [ +"7750,15400" +"14950,15400" +] +) +condition (MLText +uid 105,0 +va (VaSet +) +xt "7750,14000,14950,15000" +st "reset = '1'" +tm "Condition" +) +actions (MLText +uid 106,0 +va (VaSet +isHidden 1 +) +xt "7150,15800,15550,16800" +st "< Automatic >" +tm "Actions" +) +) +tp (TransitionPriority +uid 107,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 108,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "5469,14219,7031,15781" +radius 781 +) +pr (Text +uid 109,0 +va (VaSet +isHidden 1 +) +xt "5850,14500,6650,15500" +st "1" +ju 0 +blo "6250,15300" +tm "TransitionPriority" +) +padding "100,100" +) +) +*53 (Transition +uid 110,0 +shape (Spline +uid 111,0 +va (VaSet +vasetType 3 +) +xt "5050,13000,13000,13000" +pts [ +"5050,13000" +"13000,13000" +] +) +start &6 +end &7 +ss 0 +es 0 +tb (TransitionBlock +uid 112,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 113,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "6825,12495,11225,13505" +) +autoResize 1 +lineShape (Line +uid 114,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "9025,13900,9025,13900" +pts [ +"9025,13900" +"9025,13900" +] +) +condition (MLText +uid 115,0 +va (VaSet +) +xt "7325,12500,10725,13500" +tm "Condition" +) +actions (MLText +uid 116,0 +va (VaSet +) +xt "9025,13900,9025,13900" +tm "Actions" +) +) +tp (TransitionPriority +uid 117,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 118,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "5064,12219,6626,13781" +radius 781 +) +pr (Text +uid 119,0 +va (VaSet +isHidden 1 +) +xt "5445,12500,6245,13500" +st "1" +ju 0 +blo "5845,13300" +tm "TransitionPriority" +) +padding "100,100" +) +) +*54 (Transition +uid 246,0 +shape (Spline +uid 247,0 +va (VaSet +vasetType 3 +) +xt "14000,27968,22000,27970" +pts [ +"14000,27970" +"22000,27968" +] +arrow 1 +) +start &2 +end &19 +cond "endOfRefreshCount = '1'" +tb (TransitionBlock +uid 248,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 249,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "11700,24550,22300,26550" +) +autoResize 1 +lineShape (Line +uid 250,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "12200,26450,21800,26450" +pts [ +"12200,26450" +"21800,26450" +] +) +condition (MLText +uid 251,0 +va (VaSet +) +xt "12200,25050,26600,26050" +st "endOfRefreshCount = '1'" +tm "Condition" +) +actions (MLText +uid 252,0 +va (VaSet +) +xt "12200,26450,21800,27450" +tm "Actions" +) +) +tp (TransitionPriority +uid 253,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 254,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "14019,27188,15581,28750" +radius 781 +) +pr (Text +uid 255,0 +va (VaSet +isHidden 1 +) +xt "14400,27469,15200,28469" +st "1" +ju 0 +blo "14800,28269" +tm "TransitionPriority" +) +padding "100,100" +) +) +*55 (Transition +uid 312,0 +shape (Spline +uid 313,0 +va (VaSet +vasetType 3 +) +xt "30000,28035,38000,28036" +pts [ +"30000,28035" +"38000,28036" +] +arrow 1 +) +start &19 +end &20 +tb (TransitionBlock +uid 314,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 315,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "33500,28031,37900,29041" +) +autoResize 1 +lineShape (Line +uid 316,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "35700,29436,35700,29436" +pts [ +"35700,29436" +"35700,29436" +] +) +condition (MLText +uid 317,0 +va (VaSet +) +xt "34000,28036,37400,29036" +tm "Condition" +) +actions (MLText +uid 318,0 +va (VaSet +) +xt "35700,29436,35700,29436" +tm "Actions" +) +) +tp (TransitionPriority +uid 319,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 320,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "30019,27254,31581,28816" +radius 781 +) +pr (Text +uid 321,0 +va (VaSet +isHidden 1 +) +xt "30400,27535,31200,28535" +st "1" +ju 0 +blo "30800,28335" +tm "TransitionPriority" +) +padding "100,100" +) +) +*56 (Transition +uid 351,0 +shape (Spline +uid 352,0 +va (VaSet +vasetType 3 +) +xt "46000,27955,54000,27955" +pts [ +"46000,27955" +"54000,27955" +] +arrow 1 +) +start &20 +end &21 +cond "unsigned(timerDone(1 to prechargeToRefreshPeriodNb)) = 0" +tb (TransitionBlock +uid 353,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 354,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "41950,25000,65350,27000" +) +autoResize 1 +lineShape (Line +uid 355,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "44150,26900,44150,26900" +pts [ +"44150,26900" +"44150,26900" +] +) +condition (MLText +uid 356,0 +va (VaSet +) +xt "42450,25500,76650,26500" +st "unsigned(timerDone(1 to prechargeToRefreshPeriodNb)) = 0" +tm "Condition" +) +actions (MLText +uid 357,0 +va (VaSet +) +xt "53650,26900,53650,26900" +tm "Actions" +) +) +tp (TransitionPriority +uid 358,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 359,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "46019,27174,47581,28736" +radius 781 +) +pr (Text +uid 360,0 +va (VaSet +isHidden 1 +) +xt "46400,27455,47200,28455" +st "1" +ju 0 +blo "46800,28255" +tm "TransitionPriority" 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(Spline +uid 939,0 +va (VaSet +vasetType 3 +) +xt "62000,60002,70000,60006" +pts [ +"62000,60006" +"70000,60002" +] +arrow 1 +) +start &40 +end &41 +es 0 +tb (TransitionBlock +uid 940,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 941,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "65500,59999,69900,61009" +) +autoResize 1 +lineShape (Line +uid 942,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "67700,61404,67700,61404" +pts [ +"67700,61404" +"67700,61404" +] +) +condition (MLText +uid 943,0 +va (VaSet +) +xt "66000,60004,69400,61004" +tm "Condition" +) +actions (MLText +uid 944,0 +va (VaSet +) +xt "67700,61404,67700,61404" +tm "Actions" +) +) +tp (TransitionPriority +uid 945,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 946,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "62019,59224,63581,60786" +radius 781 +) +pr (Text +uid 947,0 +va (VaSet +isHidden 1 +) +xt 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"15138,58747,15138,58747" +pts [ +"15138,58747" +"15138,58747" +] +) +condition (MLText +uid 973,0 +va (VaSet +) +xt "13438,57347,36838,58347" +st "(ramEn = '1') and (writeRequest = '1')" +tm "Condition" +) +actions (MLText +uid 974,0 +va (VaSet +) +xt "20488,58747,20488,58747" +tm "Actions" +) +) +tp (TransitionPriority +uid 975,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 976,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "11882,59194,13444,60756" +radius 781 +) +pr (Text +uid 977,0 +va (VaSet +) +xt "12263,59475,13063,60475" +st "1" +ju 0 +blo "12663,60275" +tm "TransitionPriority" +) +padding "100,100" +) +) +*78 (Transition +uid 985,0 +shape (Spline +uid 986,0 +va (VaSet +vasetType 3 +) +xt "10008,48000,10009,58358" +pts [ +"10009,48000" +"10008,58358" +] +arrow 1 +) +start &27 +end &42 +tb (TransitionBlock +uid 987,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 988,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" 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(Transition +uid 1016,0 +shape (Spline +uid 1017,0 +va (VaSet +vasetType 3 +) +xt "114010,45640,114015,58365" +pts [ +"114015,58365" +"114010,45640" +] +arrow 1 +) +start &43 +end &37 +tb (TransitionBlock +uid 1018,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1019,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "113512,51997,117912,53007" +) +autoResize 1 +lineShape (Line +uid 1020,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "115712,53402,115712,53402" +pts [ +"115712,53402" +"115712,53402" +] +) +condition (MLText +uid 1021,0 +va (VaSet +) +xt "114012,52002,117412,53002" +tm "Condition" +) +actions (MLText +uid 1022,0 +va (VaSet +) +xt "115712,53402,115712,53402" +tm "Actions" +) +) +tp (TransitionPriority +uid 1023,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 1024,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "113233,56312,114795,57874" +radius 781 +) +pr (Text +uid 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+) +localPreDecl *100 (SmLocalDecl +uid 1648,0 +stg "VerticalLayoutStrategy" +first (Text +uid 1649,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,0,13000,900" +st "Architecture Declarations" +blo "0,700" +) +second (MLText +uid 1650,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,900,0,900" +tm "LocalDeclTextMgr" +) +declType 1 +) +localDecl *101 (SmLocalDecl +uid 3,0 +stg "VerticalLayoutStrategy" +first (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "40000,-1400,53000,-500" +st "Architecture Declarations" +blo "40000,-700" +) +second (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "40000,-400,79500,18500" +st "-- 20120621 -- zas -- added to generics +--constant prechargeToRefreshPeriodNb: positive := 2; -- 66MHz * 20 ns = 1.32 +--constant refreshDelayPeriodNb: positive := 5; -- 66MHz * 66ns = 4.356 +--constant loadModeToActivePeriodNb: positive := 1; -- 1 CK +--constant activeToWritePeriodNb: positive := 2; -- 66MHz * 20ns = 1.32 +--constant writeToActivePeriodNb: positive := 3; -- 1 CK + 66MHz * 20ns = 2.32 +--constant activeToReadPeriodNb: positive := 2; -- 66MHz * 20ns = 1.32 +--constant readToSamplePeriodNb: positive := 2; -- 2 CK with latency = 2 +--constant readToActivePeriodNb: positive := 3; -- 1 CK + 66MHz * 20ns = 2.32 + +subtype commandBusType is std_ulogic_vector(commandBusBitNb-1 downto 0); +-- bits: 5 = cs, 4 = ras, 3 = cas, 2 = we, 1 = dqm(1), 0 = dqm(0) +constant inhibit : commandBusType := \"1-----\"; +constant nop : commandBusType := \"0111--\"; +constant active : commandBusType := \"0011--\"; +constant read : commandBusType := \"010100\"; +constant write : commandBusType := \"010000\"; +constant burstTerminate : commandBusType := \"0110--\"; +constant precharge : commandBusType := \"0010--\"; +constant autoRefresh : commandBusType := \"0001--\"; +constant loadModeReg : commandBusType := \"0000--\";" +tm "LocalDeclTextMgr" +) +declType 2 +) +localPostDecl *102 (SmLocalDecl +uid 1651,0 +stg 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+decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 153,0 +) +) +) +*113 (CptPort +uid 2595,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2596,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,27625,51750,28375" +) +tg (CPTG +uid 2597,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2598,0 +va (VaSet +) +xt "44700,27500,50000,28500" +st "commandBus" +ju 2 +blo "50000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2599,0 +va (VaSet +font "courier,8,0" +) +xt "0,20500,39000,21400" +st "commandBus : OUT std_ulogic_vector ( commandBusBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "commandBus" +t "std_ulogic_vector" +b "( commandBusBitNb-1 DOWNTO 0 )" +o 12 +suid 154,0 +) +) +) +*114 (CptPort +uid 2600,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2601,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,9625,35000,10375" +) +tg (CPTG +uid 2602,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2603,0 +va (VaSet +) +xt "36000,9500,43500,10500" +st "endOfRefreshCount" +blo "36000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2604,0 +va (VaSet +font "courier,8,0" +) +xt "0,11500,20500,12400" +st "endOfRefreshCount : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "endOfRefreshCount" +t "std_ulogic" +o 2 +suid 155,0 +) +) +) +*115 (CptPort +uid 2605,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2606,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,9625,51750,10375" +) +tg (CPTG +uid 2607,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2608,0 +va (VaSet +) +xt "44400,9500,50000,10500" +st "powerUpDone" +ju 2 +blo "50000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2609,0 +va (VaSet +font "courier,8,0" +) +xt "0,21400,20500,22300" +st "powerUpDone : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "powerUpDone" +t "std_ulogic" +o 13 +suid 156,0 +) +) +) +*116 (CptPort +uid 2610,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2611,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,25625,51750,26375" +) +tg (CPTG +uid 2612,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2613,0 +va (VaSet +) +xt "44600,25500,50000,26500" +st "ramDataValid" +ju 2 +blo "50000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2614,0 +va (VaSet +font "courier,8,0" +) +xt "0,22300,20500,23200" +st "ramDataValid : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 157,0 +) +) +) +*117 (CptPort +uid 2615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,25625,35000,26375" +) +tg (CPTG +uid 2617,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2618,0 +va (VaSet +) +xt "36000,25500,38600,26500" +st "ramEn" +blo "36000,26300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2619,0 +va (VaSet +font "courier,8,0" +) +xt "0,12400,20500,13300" +st "ramEn : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 3 +suid 158,0 +) +) +) +*118 (CptPort +uid 2620,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2621,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,21625,35000,22375" +) +tg (CPTG +uid 2622,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2623,0 +va (VaSet +) +xt "36000,21500,39100,22500" +st "readAck" +blo "36000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2624,0 +va (VaSet +font "courier,8,0" +) +xt "0,23200,20500,24100" +st "readAck : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "readAck" +t "std_ulogic" +o 15 +suid 159,0 +) +) +) +*119 (CptPort +uid 2625,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2626,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,19625,35000,20375" +) +tg (CPTG +uid 2627,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2628,0 +va (VaSet +) +xt "36000,19500,41200,20500" +st "readRequest" +blo "36000,20300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2629,0 +va (VaSet +font "courier,8,0" +) +xt "0,13300,20500,14200" +st "readRequest : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "readRequest" +t "std_ulogic" +o 4 +suid 160,0 +) +) +) +*120 (CptPort +uid 2630,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2631,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,29625,35000,30375" +) +tg (CPTG +uid 2632,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2633,0 +va (VaSet +) +xt "36000,29500,38100,30500" +st "reset" +blo "36000,30300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2634,0 +va (VaSet +font "courier,8,0" +) +xt "0,14200,20500,15100" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 161,0 +) +) +) +*121 (CptPort +uid 2635,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2636,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,21625,51750,22375" +) +tg (CPTG +uid 2637,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2638,0 +va (VaSet +) +xt "45200,21500,50000,22500" +st "sampleData" +ju 2 +blo "50000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2639,0 +va (VaSet +font "courier,8,0" +) +xt "0,24100,20500,25000" +st "sampleData : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "sampleData" +t "std_ulogic" +o 16 +suid 162,0 +) +) +) +*122 (CptPort +uid 2640,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2641,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,11625,35000,12375" +) +tg (CPTG +uid 2642,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2643,0 +va (VaSet +) +xt "36000,11500,39900,12500" +st "timerDone" +blo "36000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2644,0 +va (VaSet +font "courier,8,0" +) +xt "0,15100,36500,16000" +st "timerDone : IN std_ulogic_vector ( 1 TO maxDelayPeriodNb ) ;" +) +thePort (LogicalPort +decl (Decl +n "timerDone" +t "std_ulogic_vector" +b "( 1 TO maxDelayPeriodNb )" +o 6 +suid 163,0 +) +) +) +*123 (CptPort +uid 2645,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2646,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,11625,51750,12375" +) +tg (CPTG +uid 2647,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2648,0 +va (VaSet +) +xt "45900,11500,50000,12500" +st "timerStart" +ju 2 +blo "50000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2649,0 +va (VaSet +font "courier,8,0" +) +xt "0,25000,20500,25900" +st "timerStart : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "timerStart" +t "std_ulogic" +o 17 +suid 164,0 +) +) +) +*124 (CptPort +uid 2650,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2651,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,17625,35000,18375" +) +tg (CPTG +uid 2652,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2653,0 +va (VaSet +) +xt "36000,17500,39200,18500" +st "writeAck" +blo "36000,18300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2654,0 +va (VaSet +font "courier,8,0" +) +xt "0,25900,19500,26800" +st "writeAck : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "writeAck" +t "std_ulogic" +o 18 +suid 165,0 +) +) +) +*125 (CptPort +uid 2655,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2656,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "34250,15625,35000,16375" +) +tg (CPTG +uid 2657,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2658,0 +va (VaSet +) +xt "36000,15500,41300,16500" +st "writeRequest" +blo "36000,16300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 2659,0 +va (VaSet +font "courier,8,0" +) +xt "0,16000,20500,16900" +st "writeRequest : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "writeRequest" +t "std_ulogic" +o 7 +suid 166,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "35000,6000,51000,32000" +) +oxt "15000,6000,31000,30000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "courier,8,1" +) +xt "35750,32000,38750,32900" +st "Memory" +blo "35750,32700" +) +second (Text +uid 12,0 +va (VaSet +font "courier,8,1" +) +xt "35750,32900,45250,33800" +st "sdramControllerFsm" +blo "35750,33600" +) +) +gi *126 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "35000,35200,69500,46000" +st "Generic Declarations + +commandBusBitNb positive 6 +maxDelayPeriodNb positive 10 +prechargeToRefreshPeriodNb positive 2 --66MHz * 20 ns = 1.32 +refreshDelayPeriodNb positive 5 --66MHz * 66ns = 4.356 +loadModeToActivePeriodNb positive 1 --1 CK +activeToWritePeriodNb positive 2 --66MHz * 20ns = 1.32 +writeToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 +activeToReadPeriodNb positive 2 --66MHz * 20ns = 1.32 +readToSamplePeriodNb positive 2 --2 CK with latency = 2 +readToActivePeriodNb positive 3 --1 CK + 66MHz * 20ns = 2.32 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "commandBusBitNb" +type "positive" +value "6" +) +(GiElement +name "maxDelayPeriodNb" +type "positive" +value "10" +) +(GiElement +name "prechargeToRefreshPeriodNb" +type "positive" +value "2" +e "66MHz * 20 ns = 1.32" +) +(GiElement +name "refreshDelayPeriodNb" +type "positive" +value "5" +e "66MHz * 66ns = 4.356" +) +(GiElement +name "loadModeToActivePeriodNb" +type "positive" +value "1" +e "1 CK" +) +(GiElement +name "activeToWritePeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "writeToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +(GiElement +name "activeToReadPeriodNb" +type "positive" +value "2" +e "66MHz * 20ns = 1.32" +) +(GiElement +name "readToSamplePeriodNb" +type "positive" +value "2" +e "2 CK with latency = 2" +) +(GiElement +name "readToActivePeriodNb" +type "positive" +value "3" +e "1 CK + 66MHz * 20ns = 2.32" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*127 (Grouping +uid 16,0 +optionalChildren [ +*128 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,48000,51000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,48000,49200,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*129 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,44000,55000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,44000,54800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*130 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,46000,51000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,46000,50400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*131 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,46000,34000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,46000,33800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*132 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,45000,71000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,45200,64400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*133 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "55000,44000,71000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "55200,44000,57000,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*134 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,44000,51000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "36000,44500,45000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*135 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,47000,34000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,47000,33200,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*136 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,48000,34000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,48000,33800,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*137 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,47000,51000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,47000,50400,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "30000,44000,71000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *138 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*139 (Text +uid 49,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,0,3400,1000" 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(VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *82 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,16800,3400,17800" +st "Declarations" +blo "-2000,17600" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,17800,700,18800" +st "Ports:" +blo "-2000,18600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "-2000,22400,500,23300" +st "User:" +blo "-2000,23100" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "-2000,16800,3800,17800" +st "Internal User:" +blo "-2000,17600" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "0,23300,0,23300" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "-2000,16800,-2000,16800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 234,0 +activeModelName "Symbol" +) diff --git a/Libs/Memory_test/hdl/Flash_behav.vhd b/Libs/Memory_test/hdl/Flash_behav.vhd new file mode 100644 index 0000000..3400d3a --- /dev/null +++ b/Libs/Memory_test/hdl/Flash_behav.vhd @@ -0,0 +1,528 @@ +use std.textio.all; + +ARCHITECTURE behav OF flash_28F128J3A IS + -- controls + signal chipSelect : std_ulogic; + signal writePulse : std_ulogic; + signal writePulseDelayed : std_ulogic; + signal memoryCommand : unsigned(7 downto 0); + signal wordProgramBusy : std_ulogic := '0'; + signal blockEraseBusy : std_ulogic := '0'; + signal busy : std_ulogic; + signal readPulseCs : std_ulogic := '0'; + signal readPulseOe : std_ulogic := '0'; + signal readPulse : std_ulogic; + + signal memoryAddressDebug : unsigned(A'range); + + type state_type is ( + READ_ARRAY, + READ_ID_CODES, + READ_QUERY, + READ_STATUS, + WRITE_BUFFER, + WORD_PROGRAM_1, + WORD_PROGRAM_2, + BLOCK_ERASE_1, + BLOCK_ERASE_2, + CONFIG, + PROG_LOCK_BITS, + PROG_PROT, + BOTCH_LOCK,-- + BOTCH_LOCK_ERS_SUSP,-- + LOCK_DONE, + PROG_LOCK_BITS_ERS_SUSP,-- + LOCK_DONE_ERS_SUSP, + PROT_PROG_BUSY,-- + PROT_PROG_DONE,-- + WORD_PROGRAM_1_ERS_SUSP,-- + PROG_BUSY,-- + PROG_BUSY_ERS_SUSP,-- + READ_STATUS_PROG_SUSP,-- + READ_ARRAY_PROG_SUSP,-- + READ_CONFIG_PROG_SUSP,-- + READ_QUERY_PROG_SUSP,-- + PROGRAM_DONE,-- + PROGRAM_DONE_ERS_SUSP,-- + BOTCH_ERS,-- + ERASE_BUSY,-- + READ_STATUS_ERS_SUSP,-- + READ_ARRAY_ERS_SUSP,-- + READ_CONFIG_ERS_SUSP,-- + READ_QUERY_ERS_SUSP,-- + ERASE_DONE-- + ); + + signal currentState : state_type; + signal nextState : state_type; + -- storage + constant blockLength : positive:= 16#10000#; -- 64 Kword blocks + constant memoryLength: positive := 2**(A'length-1); +-- constant memoryLength : positive := 2*blockLength; + subtype memoryWord is std_ulogic_vector(DQ'range); + type memoryArray is array(0 to memoryLength-1) of memoryWord; + signal memoryDataWord : memoryWord; + +BEGIN + + --############################################################################ + -- Controls + ------------------------------------------------------------------------------ + + chipSelect <= ( (not CE(2)) and (not CE(1)) and (not CE(0)) ) or + ( CE(2) and ( (not CE(1)) or (not CE(0)) ) ); + writePulse <= chipSelect and not(WE_n); + writePulseDelayed <= writePulse after 1 ns; + + memoryCommand <= unsigned(DQ(memoryCommand'range)); + + process(chipSelect) + begin + if rising_edge(chipSelect) then + readPulseCs <= '1' after T_R3; + elsif falling_edge(chipSelect) then + readPulseCs <= '0' after T_R8; + end if; + end process; + + process(OE_n) + begin + if falling_edge(OE_n) then + readPulseOe <= '1' after T_R7; + elsif rising_edge(OE_n) then + readPulseOe <= '0' after T_R9; + end if; + end process; + + readPulse <= readPulseCs and readPulseOe; + + ------------------------------------------------------------------------------ + -- Programming delays + ------------------------------------------------------------------------------ + + wordProgramBusy <= '1', '0' after T_W16_program when currentState = WORD_PROGRAM_2; + blockEraseBusy <= '1', '0' after T_W16_erase when currentState = BLOCK_ERASE_2; + busy <= wordProgramBusy or blockEraseBusy; + + + ------------------------------------------------------------------------------ + -- FSM: find next state + ------------------------------------------------------------------------------ + -- Table 4 p. 12 + process(writePulse, busy) + begin + case currentState is + when READ_ARRAY | READ_ID_CODES | READ_QUERY | READ_STATUS => + case to_integer(memoryCommand) is + when 16#FF# => nextState <= READ_ARRAY; + when 16#90# => nextState <= READ_ID_CODES; + when 16#98# => nextState <= READ_QUERY; + when 16#70# => nextState <= READ_STATUS; + when 16#E8# => nextState <= WRITE_BUFFER; + when 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; + when 16#20# => nextState <= BLOCK_ERASE_1; + when 16#B8# => nextState <= CONFIG; + when 16#60# => nextState <= PROG_LOCK_BITS; + when 16#C0# => nextState <= PROG_PROT; + when others => nextState <= READ_ARRAY; + end case; + + when WORD_PROGRAM_1 => + nextState <= WORD_PROGRAM_2; + + when WORD_PROGRAM_2 => + nextState <= READ_ARRAY; + + when BLOCK_ERASE_1 => + if to_integer(memoryCommand) = 16#D0# then + nextState <= BLOCK_ERASE_2; + else + nextState <= READ_ARRAY; + end if; + + when BLOCK_ERASE_2 => + nextState <= READ_ARRAY; + +-- WHEN PROG_LOCK_BITS => +-- IF rising_edge(WENeg) THEN +-- -- SECOND CYCLE CHECK +-- IF data=16#D0# OR data=16#01# OR data=16#2F# THEN +-- nextState<=READ_ARRAY; +-- ELSE +-- nextState <= BOTCH_LOCK; +-- END IF; +-- END IF; +-- +-- WHEN PROG_LOCK_BITS_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- IF data=16#D0# OR data=16#01# OR data=16#2F# THEN +-- nextState<=READ_ARRAY_ERS_SUSP; +-- ELSE +-- nextState <= BOTCH_LOCK_ERS_SUSP; +-- END IF; +-- END IF; +-- +-- +-- WHEN LOCK_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN LOCK_DONE_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#70# => nextState <= READ_STATUS_ERS_SUSP; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN 16#D0# => nextState <= ERASE_BUSY; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- WHEN BOTCH_LOCK => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN BOTCH_LOCK_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => +-- nextState <= WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#70# => nextState <= READ_STATUS_ERS_SUSP; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- +-- WHEN BOTCH_ERS => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => +-- nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <=BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- +-- WHEN PROG_PROT => +-- IF rising_edge(WENeg) THEN +-- nextState <= PROT_PROG_BUSY; +-- END IF; +-- +-- WHEN PROT_PROG_BUSY => +-- IF S_Reg(7)='1' THEN +-- nextState <= PROT_PROG_DONE; +-- ELSE +-- nextState <= PROT_PROG_BUSY; +-- END IF; +-- +-- WHEN PROT_PROG_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN WORD_PROGRAM_1 => +-- IF rising_edge(WENeg) THEN +-- nextState <= PROG_BUSY; +-- END IF; +-- +-- WHEN WORD_PROGRAM_1_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- nextState <= PROG_BUSY_ERS_SUSP; +-- END IF; +-- +-- WHEN PROG_BUSY => +-- IF WDone THEN +-- nextState<=PROGRAM_DONE; +-- ELSIF rising_edge(WENeg) THEN +-- IF data= 16#B0# THEN +-- nextState <= READ_STATUS_PROG_SUSP; +-- ELSE +-- nextState <= PROG_BUSY; +-- END IF; +-- END IF; +-- +-- WHEN PROG_BUSY_ERS_SUSP => +-- IF WDone THEN +-- nextState<=PROGRAM_DONE_ERS_SUSP; +-- ELSIF rising_edge(WENeg) THEN +-- nextState <= PROG_BUSY_ERS_SUSP; +-- END IF; +-- +-- WHEN READ_STATUS_PROG_SUSP | READ_ARRAY_PROG_SUSP | +-- READ_CONFIG_PROG_SUSP | READ_QUERY_PROG_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- --WHEN 16#D0# => nextState <= READ_ARRAY_PROG_SUSP; +-- WHEN 16#D0# => nextState <= PROG_BUSY; +-- WHEN 16#B0# | 16#70# => nextState <= READ_STATUS_PROG_SUSP; +-- WHEN 16#90# => nextState <= READ_CONFIG_PROG_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_PROG_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_PROG_SUSP; +-- END CASE; +-- END IF; +-- +-- WHEN PROGRAM_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; +-- +-- WHEN PROGRAM_DONE_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#B0# | 16#70# => nextState <= READ_STATUS_ERS_SUSP; +-- WHEN 16#D0# => nextState <= ERASE_BUSY; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- +-- WHEN ERASE_BUSY => +-- IF rising_edge(WENeg) AND data= 16#B0# THEN +-- nextState <= READ_STATUS_ERS_SUSP; +-- ELSIF EDone AND ECount=31 THEN +-- nextState<=ERASE_DONE; +-- ELSE +-- nextState <= ERASE_BUSY; +-- END IF; +-- +-- WHEN READ_STATUS_ERS_SUSP | READ_ARRAY_ERS_SUSP | +-- READ_CONFIG_ERS_SUSP | READ_QUERY_ERS_SUSP => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <=WORD_PROGRAM_1_ERS_SUSP; +-- WHEN 16#B0# | 16#70# | 16#80# => +-- nextState<= READ_STATUS_ERS_SUSP; +-- WHEN 16#D0# => nextState <= ERASE_BUSY; +-- WHEN 16#90# => nextState <= READ_CONFIG_ERS_SUSP; +-- WHEN 16#98# => nextState <= READ_QUERY_ERS_SUSP; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS_ERS_SUSP; +-- WHEN OTHERS => nextState <= READ_ARRAY_ERS_SUSP; +-- END CASE; +-- END IF; +-- +-- WHEN ERASE_DONE => +-- IF rising_edge(WENeg) THEN +-- CASE data IS +-- WHEN 16#10# | 16#40# => nextState <= WORD_PROGRAM_1; +-- WHEN 16#20# => nextState <= BLOCK_ERASE_1; +-- WHEN 16#70# => nextState <= READ_STATUS; +-- WHEN 16#90# => nextState <= READ_CONFIG; +-- WHEN 16#98# => nextState <= READ_QUERY; +-- WHEN 16#60# => nextState <= PROG_LOCK_BITS; +-- WHEN 16#C0# => nextState <= PROG_PROT; +-- WHEN OTHERS => nextState <= READ_ARRAY; +-- END CASE; +-- END IF; + +when others => nextState <= READ_ARRAY; + + end case; + end process; + + + ------------------------------------------------------------------------------ + -- FSM: update state + ------------------------------------------------------------------------------ + process(RP_N, writePulseDelayed, busy) + begin + if RP_n = '0' then + currentState <= READ_ARRAY; + elsif falling_edge(writePulseDelayed) then + currentState <= nextState; + elsif falling_edge(busy) then + currentState <= nextState; + end if; + end process; + + + ------------------------------------------------------------------------------ + -- STS + ------------------------------------------------------------------------------ + process + begin + STS <= '1'; + wait on busy; + if rising_edge(busy) then + STS <= '0' after T_W13; + wait until falling_edge(busy); + end if; + end process; + + + --############################################################################ + -- Storage + ------------------------------------------------------------------------------ + process(writePulse, A) + variable memContent : memoryArray; -- much faster than using a signal + variable loadMemFromFile : boolean := true; + file memoryFile : text open read_mode is fileSpec; + variable srecLine : line; + variable srecChar : character; + variable srecType : natural; + variable srecAddrLength : natural; + variable srecWordAscii : string(8 downto 1); + variable srecLength : natural; + variable srecAddress : natural; + variable memoryAddress : natural; + variable srecData : natural; + + function readNumber(hexString: string) return natural is + variable currentCharPos: natural; + variable intValue: natural; + variable accValue: natural; + begin + accValue := 0; + for index in hexString'range loop + currentCharPos := character'pos(hexString(index)); + if currentCharPos <= character'pos('9') then + intValue := currentCharPos - character'pos('0'); + else + intValue := currentCharPos - character'pos('A') + 10; + end if; + accValue := accValue * 16 + intValue; + end loop; + return accValue; + end readNumber; + + begin + if loadMemFromFile then + -- only happens at simulation start + while not endfile(memoryFile) loop + readline(memoryFile, srecLine); + --report "-> " & srecLine.all; + -- trim leading whitespaces + while (not (srecLine'length=0)) and (srecLine(srecLine'left) = ' ') loop + read(srecLine, srecChar); + end loop; + -- get record type + if srecLine'length > 0 then + read(srecLine, srecChar); + if (srecChar = 'S') or (srecChar = 's') then + read(srecLine, srecChar); + srecType := character'pos(srecChar) - character'pos('0'); + --report "-> srec type: " & integer'image(srecType); + srecAddrLength := srecType + 1; + if (srecType >= 1) and (srecType <= 3) then + -- get record length + srecWordAscii := (others => '0'); + read(srecLine, srecWordAscii(2)); + read(srecLine, srecWordAscii(1)); + srecLength := readNumber(srecWordAscii); + -- get record base address + srecWordAscii := (others => '0'); + for index in 2*(srecAddrLength) downto 1 loop + read(srecLine, srecWordAscii(index)); + end loop; + srecAddress := readNumber(srecWordAscii); + memoryAddress := srecAddress/2; + -- get record data + for index1 in 1 to (srecLength - srecAddrLength - 1) / 2 loop + srecWordAscii := (others => '0'); + for index2 in 4 downto 1 loop + read(srecLine, srecWordAscii(index2)); + end loop; + srecData := readNumber(srecWordAscii); + if memoryAddress < memoryLength then + memContent(memoryAddress) := std_ulogic_vector(to_unsigned(srecData, memoryWord'length)); + end if; + memoryAddress := memoryAddress + 1; + end loop; + end if; + end if; + end if; + end loop; + loadMemFromFile := false; + else + -- normal functionality + if falling_edge(writePulse) then + -- program a word + if currentState = WORD_PROGRAM_1 then + memoryAddress := to_integer(A(A'high downto 1)); +memoryAddressDebug <= to_unsigned(memoryAddress, memoryAddressDebug'length); + memContent(memoryAddress) := std_ulogic_vector(DQ); + -- erase a block + elsif currentState = BLOCK_ERASE_1 then + memoryAddress := to_integer(A and not(to_unsigned(blockLength-1, A'length))); + for index in 0 to blockLength-1 loop + if memoryAddress < memoryLength then + memContent(memoryAddress) := (others => '1'); + memoryAddress := memoryAddress + 1; + end if; + end loop; + end if; + end if; + -- update readout data + if A'event then + memoryAddress := to_integer(A(A'high downto 1)); +memoryAddressDebug <= to_unsigned(memoryAddress, memoryAddressDebug'length); + memoryDataWord <= memContent(memoryAddress) after T_R2; + end if; + end if; + end process; + + process(memoryDataWord, readPulse) + begin + if readPulse = '1' then + DQ <= std_logic_vector(memoryDataWord); + else + DQ <= (others => 'Z'); + end if; + end process; + + + +END ARCHITECTURE behav; + diff --git a/Libs/Memory_test/hdl/bram_tester_test.vhd b/Libs/Memory_test/hdl/bram_tester_test.vhd new file mode 100644 index 0000000..36c3016 --- /dev/null +++ b/Libs/Memory_test/hdl/bram_tester_test.vhd @@ -0,0 +1,83 @@ +ARCHITECTURE test OF bram_tester IS + + constant clockFrequencyA: real := 66.0E6; + constant clockFrequencyB: real := 20.0E6; + constant clockPeriodA: time := (1.0/clockFrequencyA) * 1 sec; + constant clockPeriodB: time := (1.0/clockFrequencyB) * 1 sec; + signal clockA_int: std_uLogic := '1'; + signal clockB_int: std_uLogic := '1'; + + signal addressA_int: natural; + signal dataA_int: integer; + + signal addressB_int: natural; + signal dataB_int: integer; + +BEGIN + ------------------------------------------------------------------------------ + -- clocks + clockA_int <= not clockA_int after clockPeriodA/2; + clockA <= transport clockA_int after clockPeriodA*9/10; + + clockB_int <= not clockB_int after clockPeriodB/2; + clockB <= transport clockB_int after clockPeriodB*9/10; + + ------------------------------------------------------------------------------ + -- test sequence + portA: process + begin + enA <= '0'; + writeEnA <= '0'; + addressA_int <= 0; + dataA_int <= 0; + -- read initial BRAM data + wait for 5*clockPeriodA; + addressA_int <= 40; + enA <= '1'; + wait for clockPeriodA; + enA <= '0'; + -- write data on port A + wait for 10*clockPeriodA; + addressA_int <= 10; + dataA_int <= 5; + enA <= '1'; + writeEnA <= '1'; + wait for clockPeriodA; + enA <= '0'; + writeEnA <= '0'; + + wait; + end process portA; + + addressA <= std_ulogic_vector(to_unsigned(addressA_int, addressA'length)); + dataInA <= std_ulogic_vector(to_signed(dataA_int, dataInA'length)); + + portB: process + begin + enB <= '0'; + writeEnB <= '0'; + addressB_int <= 0; + dataB_int <= 0; + -- write data on port B + wait for 10*clockPeriodB; + addressB_int <= 20; + dataB_int <= 10; + enB <= '1'; + writeEnB <= '1'; + wait for clockPeriodB; + enB <= '0'; + writeEnB <= '0'; + -- read data written on port A + wait for 2*clockPeriodB; + addressB_int <= 10; + enB <= '1'; + wait for clockPeriodB; + enB <= '0'; + + wait; + end process portB; + + addressB <= std_ulogic_vector(to_unsigned(addressB_int, addressB'length)); + dataInB <= std_ulogic_vector(to_signed(dataB_int, dataInB'length)); + +END ARCHITECTURE test; diff --git a/Libs/Memory_test/hdl/fifo_tester_test.vhd b/Libs/Memory_test/hdl/fifo_tester_test.vhd new file mode 100644 index 0000000..388de8a --- /dev/null +++ b/Libs/Memory_test/hdl/fifo_tester_test.vhd @@ -0,0 +1,339 @@ +--LIBRARY std; +-- USE std.textio.ALL; +LIBRARY COMMON_TEST; + USE COMMON_TEST.testUtils.all; + +ARCHITECTURE test OF fifo_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_ulogic := '1'; + + constant testInterval: time := 10*clockPeriod; + signal dataIn_int: integer; + signal read_int: std_ulogic; + signal dataOffset: integer; + + signal dataValid: std_ulogic; + signal dataRead: integer; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- test sequence + process + variable readIndex: integer; + begin + write <= '0'; + read_int <= '0'; + dataOffset <= -16#10#; + wait for 5*clockPeriod; + print( + lf & lf & lf & + "----------------------------------------------------------------" & lf & + "Starting testbench" & lf & + lf & lf + ); + + --.......................................................................... + -- full write / read after end of write + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write direclty followed by full read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth-1 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + -- read FIFO + read_int <= '1'; + readIndex := 0; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- full write / read after some time + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write and delay before read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth-1 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + -- wait before read + wait for 4*clockPeriod; + -- read FIFO + read_int <= '1'; + readIndex := 0; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- write / read direct + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write with asynchronous direct read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1', '0' after 8*clockPeriod; + dataIn_int <= dataOffset + 16#00#, + dataOffset + 16#01# after 1*clockPeriod, + dataOffset + 16#02# after 2*clockPeriod, + dataOffset + 16#03# after 3*clockPeriod, + dataOffset + 16#04# after 4*clockPeriod, + dataOffset + 16#05# after 5*clockPeriod, + dataOffset + 16#06# after 6*clockPeriod, + dataOffset + 16#07# after 7*clockPeriod; + -- read FIFO + wait until empty = '0'; + read_int <= '1'; + readIndex := -1; + while empty = '0' loop + if readIndex >= 0 then + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + end if; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- write / read direct with clock period delay + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", full FIFO write with synchronous direct read" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1', '0' after 8*clockPeriod; + dataIn_int <= dataOffset + 16#00#, + dataOffset + 16#01# after 1*clockPeriod, + dataOffset + 16#02# after 2*clockPeriod, + dataOffset + 16#03# after 3*clockPeriod, + dataOffset + 16#04# after 4*clockPeriod, + dataOffset + 16#05# after 5*clockPeriod, + dataOffset + 16#06# after 6*clockPeriod, + dataOffset + 16#07# after 7*clockPeriod; + -- read FIFO + wait until empty = '0'; + wait until rising_edge(clock_int); + read_int <= '1'; + readIndex := 0; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + + --.......................................................................... + -- slow read sets FIFO full + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", slow reading sets FIFO full and requires waiting before writing on" & + lf & lf + ); + -- prepare slow FIFO reading + wait until rising_edge(clock_int); + wait for 2*clockPeriod; + read_int <= '1' after 4*clockPeriod, + '0' after 5*clockPeriod, + '1' after 14*clockPeriod, + '0' after 15*clockPeriod, + '1' after 24*clockPeriod, + '0' after 25*clockPeriod, + '1' after 34*clockPeriod, + '0' after 35*clockPeriod, + '1' after 44*clockPeriod, + '0' after (45+2*fifoDepth-5)*clockPeriod; + -- write 2*FIFO depth + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + for index in 0 to 2*fifoDepth-1 loop + dataIn_int <= dataOffset + index; + if full = '1' then + wait until full = '0'; + wait for clockPeriod/8; + end if; + write <= '1'; + wait until rising_edge(clock_int); + write <= '0'; + end loop; + + --.......................................................................... + -- write over full + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", attempt to write after FIFO full" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth+3 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + + --.......................................................................... + -- read FIFO once too much + print( + "At time " & sprintf("%9.3tu", now) & + ", attempt to read after FIFO empty" & + lf & lf + ); + read_int <= '1'; + wait for clockPeriod; + wait until empty = '1'; + wait for clockPeriod; + read_int <= '0'; + -- read when empty + wait until rising_edge(clock_int); + wait for 2*clockPeriod; + read_int <= '1'; + wait for 2*clockPeriod; + read_int <= '0'; + + --.......................................................................... + -- read constantly + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", reading FIFO constantly (data valid when empty = '0')" & + lf & lf + ); + + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + read_int <= '1'; + wait for 2*clockPeriod; + wait until rising_edge(clock_int); + readIndex := -1; + write <= '1'; + for index in 0 to fifoDepth-1 loop + if empty = '0' then + readIndex := readIndex + 1; + end if; + if (readIndex >= 0) and (empty = '0') then + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + end if; + dataIn_int <= dataOffset + index; + wait until rising_edge(clock_int); + end loop; + write <= '0'; + + wait until empty = '1'; + wait for 2*clockPeriod; + read_int <= '0'; + + --.......................................................................... + -- full write / read with breaks + wait for testInterval; + print( + "At time " & sprintf("%9.3tu", now) & + ", reading FIFO with breaks" & + lf & lf + ); + -- write FIFO + dataOffset <= dataOffset + 16#10#; + wait until rising_edge(clock_int); + write <= '1'; + for index in 0 to fifoDepth-1 loop + dataIn_int <= dataOffset + index; + wait for clockPeriod; + end loop; + write <= '0'; + -- wait before read + wait for 2*clockPeriod; + -- read FIFO + wait until rising_edge(clock_int); + readIndex := 0; + for index in 0 to fifoDepth/4-1 loop + read_int <= '1'; + for rdIndex in 1 to 2 loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + wait for 2*clockPeriod; + end loop; + read_int <= '1'; + while empty = '0' loop + assert unsigned(dataOut) = dataOffset + readIndex + report "FIFO readback error" + severity error; + readIndex := readIndex + 1; + wait until rising_edge(clock_int); + end loop; + read_int <= '0'; + --.......................................................................... + -- end of tests + wait for testInterval; + assert false + report "END SIMULATION" + severity failure; + wait; + end process; + + dataIn <= std_ulogic_vector(to_signed(dataIn_int, dataIn'length)); + read <= read_int; + + dataValid <= '1' when (read_int = '1') and (empty = '0') + else '0'; + dataRead <= to_integer(signed(dataOut)) when dataValid = '1' + else 0; + +END ARCHITECTURE test; diff --git a/Libs/Memory_test/hdl/flashController_tester_test.vhd b/Libs/Memory_test/hdl/flashController_tester_test.vhd new file mode 100644 index 0000000..77157e6 --- /dev/null +++ b/Libs/Memory_test/hdl/flashController_tester_test.vhd @@ -0,0 +1,88 @@ +LIBRARY BoardTester_test; + USE BoardTester_test.testUtils.all; + +ARCHITECTURE test OF flashController_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + + signal flashAddr_int: natural := 0; + signal flashDataOut_int: natural := 0; + + signal refreshEn: std_uLogic := '0'; + + constant separator : string(1 to 80) := (others => '-'); + constant indent : string(1 to 2) := (others => ' '); + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- flash access + process + begin + flashRd <= '0'; + flashWr <= '0'; + flashEn <= '1'; + wait for 1 us; + print(cr & separator); + -- erase block 0 + print(sprintf("%tu", now) & ": Erasing block 0"); + flashAddr_int <= 16#10000#; + flashDataOut_int <= 16#0020#; + flashWr <= '1', '0' after clockPeriod; + wait until falling_edge(flashDataValid); + wait for clockPeriod/10; + flashDataOut_int <= 16#00D0#; + flashWr <= '1', '0' after clockPeriod; + wait for 2 us; + -- program word + print(sprintf("%tu", now) & ": Writing data into Flash"); + flashAddr_int <= 16#0000#; + flashDataOut_int <= 16#0040#; + flashWr <= '1', '0' after clockPeriod; + wait until falling_edge(flashDataValid); + wait for clockPeriod/10; + flashAddr_int <= 16#0010#; + flashDataOut_int <= 16#CAFE#; + flashWr <= '1', '0' after clockPeriod; + wait for 2 us; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + flashAddr_int <= 16#0000#; + flashRd <= '1', '0' after clockPeriod; + wait for 1 us; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + flashAddr_int <= 16#000F#; + flashRd <= '1', '0' after clockPeriod; + wait for 500 ns; + flashAddr_int <= 16#0010#; + flashRd <= '1', '0' after clockPeriod; + wait for 500 ns; + flashAddr_int <= 16#0011#; + flashRd <= '1', '0' after clockPeriod; + wait for 500 ns; + + wait; + end process; + + ------------------------------------------------------------------------------ + -- address and data + flashAddr <= to_unsigned(flashAddr_int, flashAddr'length); + flashDataOut <= std_ulogic_vector(to_unsigned(flashDataOut_int, flashDataOut'length)); + + ------------------------------------------------------------------------------ + -- memory bus hold + refreshEn <= '1' after 15*clockPeriod when refreshEn = '0' + else '0' after clockPeriod; + memBusEn_n <= refreshEn; + +END ARCHITECTURE test; + diff --git a/Libs/Memory_test/hdl/flash_tester_test.vhd b/Libs/Memory_test/hdl/flash_tester_test.vhd new file mode 100644 index 0000000..023ea1a --- /dev/null +++ b/Libs/Memory_test/hdl/flash_tester_test.vhd @@ -0,0 +1,102 @@ +LIBRARY BoardTester_test; + USE BoardTester_test.testUtils.all; + +ARCHITECTURE test OF flash_tester IS + + constant T_W2: time := 0 ns; + constant T_W3: time := 70 ns; + constant T_W4: time := 50 ns; + constant T_W5: time := 55 ns; + constant T_W6: time := 10 ns; + constant T_R3: time := 120 ns; + + signal addr: natural; + signal data: integer; + + signal writeFlash: std_ulogic := '0'; + signal readFlash: std_ulogic := '0'; + + constant separator : string(1 to 80) := (others => '-'); + constant indent : string(1 to 2) := (others => ' '); + +BEGIN + + ------------------------------------------------------------------------------ + -- Test + ------------------------------------------------------------------------------ + process + begin + RP_n <= '1'; + wait for 1 us; + print(cr & separator); + -- erase block 0 + print(sprintf("%tu", now) & ": Erasing block 0"); + addr <= 16#10000#; + data <= 16#20#; + writeFlash <= '1', '0' after 1 ns; + wait for 100 ns; + data <= 16#D0#; + writeFlash <= '1', '0' after 1 ns; + wait for 2 us; + -- program word + print(sprintf("%tu", now) & ": Writing data into Flash"); + addr <= 16#0000#; + data <= 16#0040#; + writeFlash <= '1', '0' after 1 ns; + wait for 100 ns; + addr <= 16#0010#; + data <= 16#CAFE#; + writeFlash <= '1', '0' after 1 ns; + wait for 2 us; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + addr <= 16#0000#; + readFlash <= '1', '0' after 1 ns; + wait for 500 ns; + -- read word + print(sprintf("%tu", now) & ": Reading data from Flash"); + addr <= 16#0010#; + readFlash <= '1', '0' after 1 ns; + wait for 500 ns; + + wait; + end process; + + ------------------------------------------------------------------------------ + -- Board connections + ------------------------------------------------------------------------------ + CE(2 downto 1) <= (others => '0'); + BYTE_n <= '1'; + + + ------------------------------------------------------------------------------ + -- Write access + ------------------------------------------------------------------------------ + process + begin + CE(0) <= '1'; + WE_N <= '1'; + OE_N <= '1'; + DQ <= (others => 'Z'); + wait on writeFlash, readFlash; + if rising_edge(writeFlash) then + A <= to_unsigned(addr, A'length) after T_W3 - T_W5; + DQ <= std_logic_vector(to_unsigned(data, DQ'length)) after T_W3 - T_W4; + CE(0) <= '0'; + wait for T_W2; + WE_N <= '0'; + wait for T_W3; + WE_N <= '1'; + wait for T_W6; +-- CE(0) <= '1'; + elsif rising_edge(readFlash) then + OE_N <= '0'; + A <= to_unsigned(addr, A'length); + CE(0) <= '0'; + wait for T_R3 + 10 ns; +-- CE(0) <= '1'; + end if; + end process; + +END ARCHITECTURE test; + diff --git a/Libs/Memory_test/hdl/mti_pkg_pkg.vhd b/Libs/Memory_test/hdl/mti_pkg_pkg.vhd new file mode 100644 index 0000000..a83599d --- /dev/null +++ b/Libs/Memory_test/hdl/mti_pkg_pkg.vhd @@ -0,0 +1,18 @@ +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE std.textio.all; + +PACKAGE mti_pkg IS + + FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC; + FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER; + FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER; + FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER; + FUNCTION TO_INTEGER (input : STD_ULOGIC_VECTOR) RETURN INTEGER; + PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR); + + function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector; + procedure hexread(L : inout line; value:out bit_vector); + procedure hexread(L : inout line; value:out std_logic_vector); + +END mti_pkg; diff --git a/Libs/Memory_test/hdl/mti_pkg_pkg_body.vhd b/Libs/Memory_test/hdl/mti_pkg_pkg_body.vhd new file mode 100644 index 0000000..422a4ab --- /dev/null +++ b/Libs/Memory_test/hdl/mti_pkg_pkg_body.vhd @@ -0,0 +1,234 @@ +LIBRARY ieee; + USE ieee.numeric_std.all; + +PACKAGE BODY mti_pkg IS + + -- Convert BIT to STD_LOGIC + FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS + BEGIN + CASE s IS + WHEN '0' => RETURN ('0'); + WHEN '1' => RETURN ('1'); + WHEN OTHERS => RETURN ('0'); + END CASE; + END; + + -- Convert STD_LOGIC to INTEGER + FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + IF input = '1' THEN + result := weight; + ELSE + result := 0; -- if unknowns, default to logic 0 + END IF; + RETURN result; + END TO_INTEGER; + + -- Convert BIT_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Convert STD_LOGIC_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Convert STD_ULOGIC_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : STD_ULOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Conver INTEGER to BIT_VECTOR + PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS + VARIABLE work,offset,outputlen,j : INTEGER := 0; + BEGIN + --length of vector + IF output'LENGTH > 32 THEN --' + outputlen := 32; + offset := output'LENGTH - 32; --' + IF input >= 0 THEN + FOR i IN offset-1 DOWNTO 0 LOOP + output(output'HIGH - i) := '0'; --' + END LOOP; + ELSE + FOR i IN offset-1 DOWNTO 0 LOOP + output(output'HIGH - i) := '1'; --' + END LOOP; + END IF; + ELSE + outputlen := output'LENGTH; --' + END IF; + --positive value + IF (input >= 0) THEN + work := input; + j := outputlen - 1; + FOR i IN 1 to 32 LOOP + IF j >= 0 then + IF (work MOD 2) = 0 THEN + output(output'HIGH-j-offset) := '0'; --' + ELSE + output(output'HIGH-j-offset) := '1'; --' + END IF; + END IF; + work := work / 2; + j := j - 1; + END LOOP; + IF outputlen = 32 THEN + output(output'HIGH) := '0'; --' + END IF; + --negative value + ELSE + work := (-input) - 1; + j := outputlen - 1; + FOR i IN 1 TO 32 LOOP + IF j>= 0 THEN + IF (work MOD 2) = 0 THEN + output(output'HIGH-j-offset) := '1'; --' + ELSE + output(output'HIGH-j-offset) := '0'; --' + END IF; + END IF; + work := work / 2; + j := j - 1; + END LOOP; + IF outputlen = 32 THEN + output(output'HIGH) := '1'; --' + END IF; + END IF; + END TO_BITVECTOR; + + + function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is + variable tmp : std_logic_vector(w-1 downto 0); + begin + tmp := std_logic_vector(to_unsigned(i, w)); + return(tmp); + end; + + procedure char2hex(C: character; result: out bit_vector(3 downto 0); + good: out boolean; report_error: in boolean) is + begin + good := true; + case C is + when '0' => result := x"0"; + when '1' => result := x"1"; + when '2' => result := X"2"; + when '3' => result := X"3"; + when '4' => result := X"4"; + when '5' => result := X"5"; + when '6' => result := X"6"; + when '7' => result := X"7"; + when '8' => result := X"8"; + when '9' => result := X"9"; + when 'A' => result := X"A"; + when 'B' => result := X"B"; + when 'C' => result := X"C"; + when 'D' => result := X"D"; + when 'E' => result := X"E"; + when 'F' => result := X"F"; + + when 'a' => result := X"A"; + when 'b' => result := X"B"; + when 'c' => result := X"C"; + when 'd' => result := X"D"; + when 'e' => result := X"E"; + when 'f' => result := X"F"; + when others => + if report_error then + assert false report + "hexread error: read a '" & C & "', expected a hex character (0-F)."; + end if; + good := false; + end case; + end; + + procedure hexread(L:inout line; value:out bit_vector) is + variable OK: boolean; + variable C: character; + constant NE: integer := value'length/4; --' + variable BV: bit_vector(0 to value'length-1); --' + variable S: string(1 to NE-1); + begin + if value'length mod 4 /= 0 then --' + assert false report + "hexread Error: Trying to read vector " & + "with an odd (non multiple of 4) length"; + return; + end if; + + loop -- skip white space + read(L,C); + exit when ((C /= ' ') and (C /= CR) and (C /= HT)); + end loop; + + char2hex(C, BV(0 to 3), OK, false); + if not OK then + return; + end if; + + read(L, S, OK); +-- if not OK then +-- assert false report "hexread Error: Failed to read the STRING"; +-- return; +-- end if; + + for I in 1 to NE-1 loop + char2hex(S(I), BV(4*I to 4*I+3), OK, false); + if not OK then + return; + end if; + end loop; + value := BV; + end hexread; + + procedure hexread(L:inout line; value:out std_ulogic_vector) is + variable tmp: bit_vector(value'length-1 downto 0); --' + begin + hexread(L, tmp); + value := TO_X01(tmp); + end hexread; + + procedure hexread(L:inout line; value:out std_logic_vector) is + variable tmp: std_ulogic_vector(value'length-1 downto 0); --' + begin + hexread(L, tmp); + value := std_logic_vector(tmp); + end hexread; + +END mti_pkg; diff --git a/Libs/Memory_test/hdl/sdramController_tester_test.vhd b/Libs/Memory_test/hdl/sdramController_tester_test.vhd new file mode 100644 index 0000000..317fb6d --- /dev/null +++ b/Libs/Memory_test/hdl/sdramController_tester_test.vhd @@ -0,0 +1,82 @@ +ARCHITECTURE test OF sdramController_tester IS + + constant clockFrequency: real := 66.0E6; + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + + signal ramAddr_int: natural := 0; + signal ramDataOut_int: natural := 0; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- test sequence + process + begin + ramRd <= '0'; + ramWr <= '0'; + ramEn <= '1'; + -- wait for SDRAM ready + wait for 154.3 us - now; + -- write AAAA at address 000010 + ramAddr_int <= 16#000010#; + ramDataOut_int <= 16#AAAA#; + ramWr <= '1', '0' after clockPeriod; + -- wait for SDRAM ready + wait for 164.5 us - now; + -- write AAAA at address 000011 + ramAddr_int <= 16#000011#; + ramDataOut_int <= 16#BBBD#; + ramWr <= '1', '0' after clockPeriod; + -- wait for SDRAM ready + wait for 196.1 us - now; + -- read back from address 000010 + ramAddr_int <= 16#000010#; + ramRd <= '1', '0' after clockPeriod; +-- -- wait for SDRAM ready +-- wait for 130 us; +-- -- write AAAA at address 000010 +-- ramAddr_int <= 16#000010#; +-- ramDataOut_int <= 16#AAAA#; +-- ramWr <= '1', '0' after clockPeriod; +-- -- read back from same address +-- wait for 10*clockPeriod; +-- ramRd <= '1', '0' after clockPeriod; +-- -- wait for a refresh +-- wait for 140.3 us - now; +-- -- write 5555 at address 600010 +-- ramAddr_int <= 16#600020#; +-- ramDataOut_int <= 16#5555#; +-- ramWr <= '1', '0' after clockPeriod; +-- -- read back from same address +-- wait for 1*clockPeriod; +-- ramRd <= '1', '0' after clockPeriod; +-- -- read back from address 600010 +-- addr_from_up_int <= 16#600010#; +-- mem_read <= '1', '0' after clockPeriod; +-- wait for 10*clockPeriod; +-- -- wait for 3 refresh periods +-- wait until falling_edge(dram_busy); +-- wait until falling_edge(dram_busy); +-- wait until falling_edge(dram_busy); +-- -- read back from address 000010 +-- addr_from_up_int <= 16#000010#; +-- mem_read <= '1', '0' after clockPeriod; +-- wait for 10*clockPeriod; + -- end of tests + wait; + end process; + + ------------------------------------------------------------------------------ + -- address and data + ramAddr <= to_unsigned(ramAddr_int, ramAddr'length); + ramDataOut <= std_ulogic_vector(to_unsigned(ramDataOut_int, ramDataOut'length)); + +END ARCHITECTURE test; + diff --git a/Libs/Memory_test/hdl/sdram_mt48lc16m16a2_sim.vhd b/Libs/Memory_test/hdl/sdram_mt48lc16m16a2_sim.vhd new file mode 100644 index 0000000..a31c3fd --- /dev/null +++ b/Libs/Memory_test/hdl/sdram_mt48lc16m16a2_sim.vhd @@ -0,0 +1,1363 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT48LC16M16A2.VHD +-- Version: 0.0g +-- Date: June 29th, 2000 +-- Model: Behavioral +-- Simulator: Model Technology (PC version 5.3 PE) +-- +-- Dependencies: None +-- +-- Author: Son P. Huynh +-- Email: sphuynh@micron.com +-- Phone: (208) 368-3825 +-- Company: Micron Technology, Inc. +-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks) +-- +-- Description: Micron 256Mb SDRAM +-- +-- Limitation: - Doesn't check for 4096-cycle refresh --' +-- +-- Note: - Set simulator resolution to "ps" accuracy +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Phone Date Changes +-- ---- ---------------------------- ---------- ------------------------------------- +-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array +-- Micron Technology Inc. Modify tWR + tRAS timing check +-- +-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto) +-- Micron Technology Inc. Fix tWR = 15 ns (Manual) +-- Fix tRP (Autoprecharge to AutoRefresh) +-- +-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP +-- Micron Technology Inc. Fix tRC check in Load Mode Register +-- +-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model +-- Micron Technology Inc. +-- +----------------------------------------------------------------------------------------- + +--LIBRARY STD; +-- use std.textio.all; +--LIBRARY IEEE; +-- USE IEEE.STD_LOGIC_1164.ALL; +--LIBRARY WORK; +-- USE WORK.MTI_PKG.ALL; +LIBRARY memory_test; + USE memory_test.mti_pkg.all; + +--library grlib; +--use grlib.stdlib.all; +--library gaisler; +--use gaisler.sim.all; + +--ENTITY mt48lc16m16a2 IS +-- GENERIC ( +-- -- Timing Parameters for -75 (PC133) and CAS Latency = 2 +-- tAC : TIME := 6.0 ns; +-- tHZ : TIME := 7.0 ns; +-- tOH : TIME := 2.7 ns; +-- tMRD : INTEGER := 2; -- 2 Clk Cycles +-- tRAS : TIME := 44.0 ns; +-- tRC : TIME := 66.0 ns; +-- tRCD : TIME := 20.0 ns; +-- tRP : TIME := 20.0 ns; +-- tRRD : TIME := 15.0 ns; +-- tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +-- tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns) +-- +-- tAH : TIME := 0.8 ns; +-- tAS : TIME := 1.5 ns; +-- tCH : TIME := 2.5 ns; +-- tCL : TIME := 2.5 ns; +-- tCK : TIME := 10.0 ns; +-- tDH : TIME := 0.8 ns; +-- tDS : TIME := 1.5 ns; +-- tCKH : TIME := 0.8 ns; +-- tCKS : TIME := 1.5 ns; +-- tCMH : TIME := 0.8 ns; +-- tCMS : TIME := 1.5 ns; +-- +-- addr_bits : INTEGER := 13; +-- data_bits : INTEGER := 16; +-- col_bits : INTEGER := 9; +-- index : INTEGER := 0; +-- fname : string := "sdram.srec" -- File to read from +-- ); +-- PORT ( +-- Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); +-- Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); +-- Ba : IN STD_LOGIC_VECTOR := "00"; +-- Clk : IN STD_LOGIC := '0'; +-- Cke : IN STD_LOGIC := '1'; +-- Cs_n : IN STD_LOGIC := '1'; +-- Ras_n : IN STD_LOGIC := '1'; +-- Cas_n : IN STD_LOGIC := '1'; +-- We_n : IN STD_LOGIC := '1'; +-- Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00" +-- ); +--END mt48lc16m16a2; + +ARCHITECTURE sim OF sdram_mt48lc16m16a2 IS + + TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE); + TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER; + TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME; + TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT; + TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0); + TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0); + TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State; + SIGNAL Operation : State := NOP; + SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0'; + SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0'; + SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0'; + SIGNAL Ras_in, Cas_in, We_in : BIT := '0'; + SIGNAL Write_burst_mode : BIT := '0'; + SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0'; + + -- Checking internal wires + SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000"; + SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000"; + SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0'; + SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00"; + SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + +BEGIN + -- CS# Decode + WITH Cs_n SELECT + Cas_in <= TO_BIT (Cas_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + WITH Cs_n SELECT + Ras_in <= TO_BIT (Ras_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + WITH Cs_n SELECT + We_in <= TO_BIT (We_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + + -- Commands Decode + Active_enable <= NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= Ras_in AND Cas_in AND NOT(We_in); + Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in); + Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0)); + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + + -- Write Burst Mode + Write_burst_mode <= Mode_reg(9); + + -- RAS Clock for checking tWR and tRP + PROCESS + variable Clk0, Clk1 : integer := 0; + begin + RAS_clk <= '1'; + wait for 0.5 ns; + RAS_clk <= '0'; + wait for 0.5 ns; + if Clk0 > 100 or Clk1 > 100 then + wait; + else + if Clk = '1' and Cke = '1' then + Clk0 := 0; + Clk1 := Clk1 + 1; + elsif Clk = '0' and Cke = '1' then + Clk0 := Clk0 + 1; + Clk1 := 0; + end if; + end if; + END PROCESS; + + -- System Clock + int_clk : PROCESS (Clk) + begin + IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --' + CkeZ <= TO_BIT(Cke, '1'); + END IF; + Sys_clk <= CkeZ AND TO_BIT(Clk, '0'); + END PROCESS; + + state_register : PROCESS + -- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means + -- the location is in use. This will be checked when doing memory DUMP. + TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0); + TYPE ram_pntr IS ACCESS ram_type; + TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr; + VARIABLE Bank0 : ram_stor; + VARIABLE Bank1 : ram_stor; + VARIABLE Bank2 : ram_stor; + VARIABLE Bank3 : ram_stor; + VARIABLE Row_index, Col_index : INTEGER := 0; + VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0'); + + VARIABLE Col_addr : Array4xCBV; + VARIABLE Bank_addr : Array4x2BV; + VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00"; + + VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Burst_counter : INTEGER := 0; + + VARIABLE Command : Array_state; + VARIABLE Bank_precharge : Array4x2BV; + VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0); + + VARIABLE Data_in_enable, Data_out_enable : BIT := '0'; + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0'; + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0'; + + -- Timing Check + VARIABLE MRD_chk : INTEGER := 0; + VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0); + VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns); + VARIABLE RC_chk, RRD_chk : TIME := 0 ns; + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + + -- Load and Dumb variables + FILE file_load : TEXT open read_mode is fname; -- Data load + FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump + VARIABLE bank_load : bit_vector ( 1 DOWNTO 0); + VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0); + VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0); + VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0); + VARIABLE i, j : INTEGER; + VARIABLE good_load : BOOLEAN; + VARIABLE l : LINE; + variable load : std_logic := '1'; + variable dump : std_logic := '0'; + variable ch : character; + variable rectype : bit_vector(3 downto 0); + variable recaddr : bit_vector(31 downto 0); + variable reclen : bit_vector(7 downto 0); + variable recdata : bit_vector(0 to 16*8-1); + + -- Initialize empty rows + PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW ram_type; -- Open new row for access + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- Burst Counter + PROCEDURE Burst_decode IS + VARIABLE Col_int : INTEGER := 0; + VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance Burst Counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Col_int := TO_INTEGER(Col); + Col_int := Col_int + 1; + TO_BITVECTOR (Col_int, Col_temp); + ELSIF Mode_reg (3) = '1' THEN + TO_BITVECTOR (Burst_counter, Col_vec); + Col_temp (2) := Col_vec (2) XOR Col_brst (2); + Col_temp (1) := Col_vec (1) XOR Col_brst (1); + Col_temp (0) := Col_vec (0) XOR Col_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Col (0) := Col_temp (0); + ELSIF Burst_length_4 = '1' THEN + Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0); + ELSE + Col := Col_temp; + END IF; + + -- Burst Read Single Write + IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Data counter + IF Burst_length_1 = '1' THEN + IF Burst_counter >= 1 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk, RAS_clk; + IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --' + -- Internal Command Pipeline + Command(0) := Command(1); + Command(1) := Command(2); + Command(2) := Command(3); + Command(3) := NOP; + + Col_addr(0) := Col_addr(1); + Col_addr(1) := Col_addr(2); + Col_addr(2) := Col_addr(3); + Col_addr(3) := (OTHERS => '0'); + + Bank_addr(0) := Bank_addr(1); + Bank_addr(1) := Bank_addr(2); + Bank_addr(2) := Bank_addr(3); + Bank_addr(3) := "00"; + + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := "00"; + + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := '0'; + + -- Operation Decode (Optional for showing current command on posedge clock / debug feature) + IF Active_enable = '1' THEN + Operation <= ACT; + ELSIF Aref_enable = '1' THEN + Operation <= A_REF; + ELSIF Burst_term = '1' THEN + Operation <= BST; + ELSIF Mode_reg_enable = '1' THEN + Operation <= LMR; + ELSIF Prech_enable = '1' THEN + Operation <= PRECH; + ELSIF Read_enable = '1' THEN + IF Addr(10) = '0' THEN + Operation <= READ; + ELSE + Operation <= READ_A; + END IF; + ELSIF Write_enable = '1' THEN + IF Addr(10) = '0' THEN + Operation <= WRITE; + ELSE + Operation <= WRITE_A; + END IF; + ELSE + Operation <= NOP; + END IF; + + -- Dqm pipeline for Read + Dqm_reg0 := Dqm_reg1; + Dqm_reg1 := TO_BITVECTOR(Dqm); + + -- Read or Write with Auto Precharge Counter + IF Auto_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Auto_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Auto_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Auto_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- Auto Precharge Timer for tWR + if (Burst_length_1 = '1' OR Write_burst_mode = '1') then + if (Count_precharge(0) = 1) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 1) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 1) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 1) then + Count_time(3) := NOW; + end if; + elsif (Burst_length_2 = '1') then + if (Count_precharge(0) = 2) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 2) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 2) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 2) then + Count_time(3) := NOW; + end if; + elsif (Burst_length_4 = '1') then + if (Count_precharge(0) = 4) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 4) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 4) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 4) then + Count_time(3) := NOW; + end if; + elsif (Burst_length_8 = '1') then + if (Count_precharge(0) = 8) then + Count_time(0) := NOW; + end if; + if (Count_precharge(1) = 8) then + Count_time(1) := NOW; + end if; + if (Count_precharge(2) = 8) then + Count_time(2) := NOW; + end if; + if (Count_precharge(3) = 8) then + Count_time(3) := NOW; + end if; + end if; + + -- tMRD Counter + MRD_chk := MRD_chk + 1; + + -- tWR Counter + WR_counter(0) := WR_counter(0) + 1; + WR_counter(1) := WR_counter(1) + 1; + WR_counter(2) := WR_counter(2) + 1; + WR_counter(3) := WR_counter(3) + 1; + + + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Auto Refresh" + SEVERITY WARNING; + -- Precharge to Auto Refresh + ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + -- All banks must be idle before refresh + IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN + ASSERT (FALSE) + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + END IF; + -- Record current tRC time + RC_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + Mode_reg <= TO_BITVECTOR (Addr); + IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN + ASSERT (FALSE) + REPORT "All bank must be Precharge before Load Mode Register" + SEVERITY WARNING; + END IF; + -- REF to LMR + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Load Mode Register" + SEVERITY WARNING; + -- LMR to LMR + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + -- Record current tMRD time + MRD_chk := 0; + END IF; + + -- Active Block (latch Bank and Row Address) + IF Active_enable = '1' THEN + IF Ba = "00" AND Pc_b0 = '1' THEN + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := TO_BITVECTOR (Addr); + RCD_chk0 := NOW; + RAS_chk0 := NOW; + -- Precharge to Active Bank 0 + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" AND Pc_b1 = '1' THEN + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := TO_BITVECTOR (Addr); + RCD_chk1 := NOW; + RAS_chk1 := NOW; + -- Precharge to Active Bank 1 + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" AND Pc_b2 = '1' THEN + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := TO_BITVECTOR (Addr); + RCD_chk2 := NOW; + RAS_chk2 := NOW; + -- Precharge to Active Bank 2 + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" AND Pc_b3 = '1' THEN + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := TO_BITVECTOR (Addr); + RCD_chk3 := NOW; + RAS_chk3 := NOW; + -- Precharge to Active Bank 3 + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + ELSIF Ba = "00" AND Pc_b0 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 0 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "01" AND Pc_b1 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 1 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "10" AND Pc_b2 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 2 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "11" AND Pc_b3 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 3 is not Precharged" + SEVERITY WARNING; + END IF; + -- Active Bank A to Active Bank B + IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN + ASSERT (FALSE) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + -- LMR to ACT + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Activate" + SEVERITY WARNING; + -- AutoRefresh to Activate + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Activate" + SEVERITY WARNING; + -- Record variable for checking violation + RRD_chk := NOW; + Previous_bank := TO_BITVECTOR (Ba); + END IF; + + -- Precharge Block + IF Prech_enable = '1' THEN + IF Addr(10) = '1' THEN + Pc_b0 := '1'; + Pc_b1 := '1'; + Pc_b2 := '1'; + Pc_b3 := '1'; + Act_b0 := '0'; + Act_b1 := '0'; + Act_b2 := '0'; + Act_b3 := '0'; + RP_chk0 := NOW; + RP_chk1 := NOW; + RP_chk2 := NOW; + RP_chk3 := NOW; + -- Activate to Precharge all banks + ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS)) + REPORT "tRAS violation during Precharge all banks" + SEVERITY WARNING; + -- tWR violation check for Write + IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR + (NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN + ASSERT (FALSE) + REPORT "tWR violation during Precharge ALL banks" + SEVERITY WARNING; + END IF; + ELSIF Addr(10) = '0' THEN + IF Ba = "00" THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + -- Activate to Precharge bank 0 + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + -- Activate to Precharge bank 1 + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + -- Activate to Precharge bank 2 + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + -- Activate to Precharge bank 3 + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge bank 3" + SEVERITY WARNING; + END IF; + -- tWR violation check for Write + ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + -- Terminate a Write Immediately (if same bank or all banks) + IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN + Data_in_enable := '0'; + END IF; + -- Precharge Command Pipeline for READ + IF CAS_latency_3 = '1' THEN + Command(2) := PRECH; + Bank_precharge(2) := TO_BITVECTOR (Ba); + A10_precharge(2) := TO_BIT(Addr(10)); + ELSIF CAS_latency_2 = '1' THEN + Command(1) := PRECH; + Bank_precharge(1) := TO_BITVECTOR (Ba); + A10_precharge(1) := TO_BIT(Addr(10)); + END IF; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Terminate a Write immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + -- Terminate a Read depend on CAS Latency + IF CAS_latency_3 = '1' THEN + Command(2) := BST; + ELSIF CAS_latency_2 = '1' THEN + Command(1) := BST; + END IF; + END IF; + + -- Read, Write, Column Latch + IF Read_enable = '1' OR Write_enable = '1' THEN + -- Check to see if bank is open (ACT) for Read or Write + IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN + ASSERT (FALSE) + REPORT "Cannot Read or Write - Bank is not Activated" + SEVERITY WARNING; + END IF; + -- Activate to Read or Write + IF Ba = "00" THEN + ASSERT (NOW - RCD_chk0 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" THEN + ASSERT (NOW - RCD_chk1 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" THEN + ASSERT (NOW - RCD_chk2 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" THEN + ASSERT (NOW - RCD_chk3 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 3" + SEVERITY WARNING; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- CAS Latency Pipeline + IF Cas_latency_3 = '1' THEN + IF Addr(10) = '1' THEN + Command(2) := READ_A; + ELSE + Command(2) := READ; + END IF; + Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (2) := TO_BITVECTOR (Ba); + ELSIF Cas_latency_2 = '1' THEN + IF Addr(10) = '1' THEN + Command(1) := READ_A; + ELSE + Command(1) := READ; + END IF; + Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (1) := TO_BITVECTOR (Ba); + END IF; + + -- Read intterupt a Write (terminate Write immediately) + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Write Command + ELSIF Write_enable = '1' THEN + IF Addr(10) = '1' THEN + Command(0) := WRITE_A; + ELSE + Command(0) := WRITE; + END IF; + Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (0) := TO_BITVECTOR (Ba); + + -- Write intterupt a Write (terminate Write immediately) + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Write interrupt a Read (terminate Read immediately) + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- Interrupt a Write with Auto Precharge + IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1'; + END IF; + + -- Interrupt a Read with Auto Precharge + IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN + RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1'; + END IF; + + -- Read or Write with Auto Precharge + IF Addr(10) = '1' THEN + Auto_precharge (TO_INTEGER(Ba)) := '1'; + Count_precharge (TO_INTEGER(Ba)) := 0; + RW_Interrupt_Bank := TO_BitVector(Ba); + IF Read_enable = '1' THEN + Read_precharge (TO_INTEGER(Ba)) := '1'; + ELSIF Write_enable = '1' THEN + Write_precharge (TO_INTEGER(Ba)) := '1'; + END IF; + END IF; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. BL/2 cycles after command + -- and 2. Meet tRAS requirement + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR + (RW_interrupt_read(0) = '1')) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Auto_precharge(0) := '0'; + Read_precharge(0) := '0'; + RW_interrupt_read(0) := '0'; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR + (RW_interrupt_read(1) = '1')) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Auto_precharge(1) := '0'; + Read_precharge(1) := '0'; + RW_interrupt_read(1) := '0'; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR + (RW_interrupt_read(2) = '1')) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Auto_precharge(2) := '0'; + Read_precharge(2) := '0'; + RW_interrupt_read(2) := '0'; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR + (RW_interrupt_read(3) = '1')) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Auto_precharge(3) := '0'; + Read_precharge(3) := '0'; + RW_interrupt_read(3) := '0'; + END IF; + END IF; + + -- Internal Precharge or Bst + IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks + IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + + IF Data_out_enable = '0' THEN + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH; + END IF; + + -- Detect Read or Write Command + IF Command(0) = READ OR Command(0) = READ_A THEN + Bank := Bank_addr (0); + Col := Col_addr (0); + Col_brst := Col_addr (0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '0'; + Data_out_enable := '1'; + ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN + Bank := Bank_addr(0); + Col := Col_addr(0); + Col_brst := Col_addr(0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '1'; + Data_out_enable := '0'; + END IF; + + -- DQ (Driver / Receiver) + Row_index := TO_INTEGER (Row); + Col_index := TO_INTEGER (Col); + IF Data_in_enable = '1' THEN + IF Dqm /= "11" THEN + Init_mem (Bank, Row_index); + IF Bank = "00" THEN + Dq_temp := Bank0 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + ELSIF Bank = "01" THEN + Dq_temp := Bank1 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + ELSIF Bank = "10" THEN + Dq_temp := Bank2 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + ELSIF Bank = "11" THEN + Dq_temp := Bank3 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0)); + END IF; + WR_chkp(TO_INTEGER(Bank)) := NOW; + WR_counter(TO_INTEGER(Bank)) := 0; + END IF; + Burst_decode; + ELSIF Data_out_enable = '1' THEN + IF Dqm_reg0 /= "11" THEN + Init_mem (Bank, Row_index); + IF Bank = "00" THEN + Dq_temp := Bank0 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "01" THEN + Dq_temp := Bank1 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "10" THEN + Dq_temp := Bank2 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "11" THEN + Dq_temp := Bank3 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + END IF; + ELSE + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ; + END IF; + Burst_decode; + END IF; + ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --' + Operation <= LOAD_FILE; + load := '0'; +-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..." +-- SEVERITY NOTE; + WHILE NOT endfile(file_load) LOOP + readline(file_load, l); + read(l, ch); + if (ch /= 'S') or (ch /= 's') then + hexread(l, rectype); + hexread(l, reclen); + recaddr := (others => '0'); + case rectype is + when "0001" => + hexread(l, recaddr(15 downto 0)); + when "0010" => + hexread(l, recaddr(23 downto 0)); + when "0011" => + hexread(l, recaddr); + recaddr(31 downto 24) := (others => '0'); + when others => next; + end case; + if true then + hexread(l, recdata); + Bank_Load := recaddr(25 downto 24); + Rows_Load := recaddr(23 downto 11); + Cols_Load := recaddr(10 downto 2); + Init_Mem (Bank_Load, To_Integer(Rows_Load)); + + IF Bank_Load = "00" THEN + for i in 0 to 3 loop + Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + ELSIF Bank_Load = "01" THEN + for i in 0 to 3 loop + Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + ELSIF Bank_Load = "10" THEN + for i in 0 to 3 loop + Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + ELSIF Bank_Load = "11" THEN + for i in 0 to 3 loop + Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15)); + end loop; + END IF; + + END IF; + END IF; + END LOOP; + ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --' + Operation <= DUMP_FILE; + ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..." + SEVERITY NOTE; + WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --' + WRITELINE (file_dump, l); + WRITE (l, string'("# BA ROWS COLS DQ")); --' + WRITELINE (file_dump, l); + WRITE (l, string'("# -- ------------- --------- ----------------")); --' + WRITELINE (file_dump, l); + -- Dumping Bank 0 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank0 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank0 (i) (j) (data_bits) = '0'; + WRITE (l, string'("00"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + -- Dumping Bank 1 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank1 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank1 (i) (j) (data_bits) = '0'; + WRITE (l, string'("01"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + -- Dumping Bank 2 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank2 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank2 (i) (j) (data_bits) = '0'; + WRITE (l, string'("10"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + -- Dumping Bank 3 + FOR i IN 0 TO 2**addr_bits -1 LOOP + -- Check if ROW is NULL + IF Bank3 (i) /= NULL THEN + For j IN 0 TO 2**col_bits - 1 LOOP + -- Check if COL is NULL + NEXT WHEN Bank3 (i) (j) (data_bits) = '0'; + WRITE (l, string'("11"), right, 4); --' + WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1); + WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1); + WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1); + WRITELINE (file_dump, l); + END LOOP; + END IF; + END LOOP; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. tWR cycles after command + -- and 2. Meet tRAS requirement + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR + (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN + Auto_precharge(0) := '0'; + Write_precharge(0) := '0'; + RW_interrupt_write(0) := '0'; + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR + (RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN + Auto_precharge(1) := '0'; + Write_precharge(1) := '0'; + RW_interrupt_write(1) := '0'; + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR + (RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN + Auto_precharge(2) := '0'; + Write_precharge(2) := '0'; + RW_interrupt_write(2) := '0'; + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR + (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN + Auto_precharge(3) := '0'; + Write_precharge(3) := '0'; + RW_interrupt_write(3) := '0'; + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + END IF; + END IF; + + -- Checking internal wires (Optional for debug purpose) + Pre_chk (0) <= Pc_b0; + Pre_chk (1) <= Pc_b1; + Pre_chk (2) <= Pc_b2; + Pre_chk (3) <= Pc_b3; + Act_chk (0) <= Act_b0; + Act_chk (1) <= Act_b1; + Act_chk (2) <= Act_b2; + Act_chk (3) <= Act_b3; + Dq_in_chk <= Data_in_enable; + Dq_out_chk <= Data_out_enable; + Bank_chk <= Bank; + Row_chk <= Row; + Col_chk <= Col; + END PROCESS; + + + -- Clock timing checks +-- Clock_check : PROCESS +-- VARIABLE Clk_low, Clk_high : TIME := 0 ns; +-- BEGIN +-- WAIT ON Clk; +-- IF (Clk = '1' AND NOW >= 10 ns) THEN +-- ASSERT (NOW - Clk_low >= tCL) +-- REPORT "tCL violation" +-- SEVERITY WARNING; +-- ASSERT (NOW - Clk_high >= tCK) +-- REPORT "tCK violation" +-- SEVERITY WARNING; +-- Clk_high := NOW; +-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN +-- ASSERT (NOW - Clk_high >= tCH) +-- REPORT "tCH violation" +-- SEVERITY WARNING; +-- Clk_low := NOW; +-- END IF; +-- END PROCESS; + + -- Setup timing checks + Setup_check : PROCESS + BEGIN + wait; + WAIT ON Clk; + IF Clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tCKS) --' + REPORT "CKE Setup time violation -- tCKS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tCMS) --' + REPORT "CS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tCMS) --' + REPORT "CAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tCMS) --' + REPORT "RAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tCMS) --' + REPORT "WE# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT >= tCMS) --' + REPORT "Dqm Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tAS) --' + REPORT "ADDR Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tAS) --' + REPORT "BA Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Dq'LAST_EVENT >= tDS) --' + REPORT "Dq Setup time violation -- tDS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- Hold timing checks + Hold_check : PROCESS + BEGIN + wait; + WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH); + IF Clk'DELAYED (tCKH) = '1' THEN --' + ASSERT(Cke'LAST_EVENT > tCKH) --' + REPORT "CKE Hold time violation -- tCKH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tCMH) = '1' THEN --' + ASSERT(Cs_n'LAST_EVENT > tCMH) --' + REPORT "CS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT > tCMH) --' + REPORT "CAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT > tCMH) --' + REPORT "RAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT > tCMH) --' + REPORT "WE# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT > tCMH) --' + REPORT "Dqm Hold time violation -- tCMH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tAH) = '1' THEN --' + ASSERT(Addr'LAST_EVENT > tAH) --' + REPORT "ADDR Hold time violation -- tAH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT > tAH) --' + REPORT "BA Hold time violation -- tAH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tDH) = '1' THEN --' + ASSERT(Dq'LAST_EVENT > tDH) --' + REPORT "Dq Hold time violation -- tDH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END ARCHITECTURE sim; + diff --git a/Libs/Memory_test/hds/.hdlsidedata/_Flash_behav.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_Flash_behav.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_Flash_behav.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_bram_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_bram_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_bram_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_fifo_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_fifo_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_fifo_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_flashController_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_flashController_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_flashController_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_flash_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_flash_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_flash_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg.vhd._fpf new file mode 100644 index 0000000..5732f99 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_93 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg_body.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg_body.vhd._fpf new file mode 100644 index 0000000..5732f99 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_mti_pkg_pkg_body.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_93 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_sdramController_tester_test.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_sdramController_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_sdramController_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/.hdlsidedata/_sdram_mt48lc16m16a2_sim.vhd._fpf b/Libs/Memory_test/hds/.hdlsidedata/_sdram_mt48lc16m16a2_sim.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/Memory_test/hds/.hdlsidedata/_sdram_mt48lc16m16a2_sim.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/Memory_test/hds/_bram_tb._epf b/Libs/Memory_test/hds/_bram_tb._epf new file mode 100644 index 0000000..174551f --- /dev/null +++ b/Libs/Memory_test/hds/_bram_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom bram_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_bram_tester._epf b/Libs/Memory_test/hds/_bram_tester._epf new file mode 100644 index 0000000..559360f --- /dev/null +++ b/Libs/Memory_test/hds/_bram_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom bram_tester_test.vhd diff --git a/Libs/Memory_test/hds/_fifo_tb._epf b/Libs/Memory_test/hds/_fifo_tb._epf new file mode 100644 index 0000000..1b086f1 --- /dev/null +++ b/Libs/Memory_test/hds/_fifo_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom fifo_tb/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_flash_28f128j3a._epf b/Libs/Memory_test/hds/_flash_28f128j3a._epf new file mode 100644 index 0000000..ef7aef2 --- /dev/null +++ b/Libs/Memory_test/hds/_flash_28f128j3a._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom Flash_behav.vhd +DEFAULT_ARCHITECTURE atom behav diff --git a/Libs/Memory_test/hds/_flash_tb._epf b/Libs/Memory_test/hds/_flash_tb._epf new file mode 100644 index 0000000..99c6d2b --- /dev/null +++ b/Libs/Memory_test/hds/_flash_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom flash_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_flash_tester._epf b/Libs/Memory_test/hds/_flash_tester._epf new file mode 100644 index 0000000..a7aa7e2 --- /dev/null +++ b/Libs/Memory_test/hds/_flash_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom flash_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Memory_test/hds/_flashcontroller_tb._epf b/Libs/Memory_test/hds/_flashcontroller_tb._epf new file mode 100644 index 0000000..3f59750 --- /dev/null +++ b/Libs/Memory_test/hds/_flashcontroller_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom flash@controller_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_flashcontroller_tester._epf b/Libs/Memory_test/hds/_flashcontroller_tester._epf new file mode 100644 index 0000000..d81ef79 --- /dev/null +++ b/Libs/Memory_test/hds/_flashcontroller_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom flashController_tester_test.vhd diff --git a/Libs/Memory_test/hds/_sdramcontroller_tb._epf b/Libs/Memory_test/hds/_sdramcontroller_tb._epf new file mode 100644 index 0000000..318858b --- /dev/null +++ b/Libs/Memory_test/hds/_sdramcontroller_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom sdram@controller_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/Memory_test/hds/_sdramcontroller_tester._epf b/Libs/Memory_test/hds/_sdramcontroller_tester._epf new file mode 100644 index 0000000..cd1908b --- /dev/null +++ b/Libs/Memory_test/hds/_sdramcontroller_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom sdramController_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/Memory_test/hds/bram_tb/struct.bd b/Libs/Memory_test/hds/bram_tb/struct.bd new file mode 100644 index 0000000..cc5de3c --- /dev/null +++ b/Libs/Memory_test/hds/bram_tb/struct.bd @@ -0,0 +1,3661 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I1" +duLibraryName "memory_test" +duName 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a/Libs/Memory_test/hds/fifo_tb/struct.bd.info/msimSimulationReplay.sh b/Libs/Memory_test/hds/fifo_tb/struct.bd.info/msimSimulationReplay.sh new file mode 100644 index 0000000..c211a82 --- /dev/null +++ b/Libs/Memory_test/hds/fifo_tb/struct.bd.info/msimSimulationReplay.sh @@ -0,0 +1,3 @@ +# Script to replay the last simulation run +cd $HDS_PROJECT_DIR\..\Memory_test\work +"C:/eda/mentor/questasim64_10.1b/win64/vsim" -f hds_args.tmp diff --git a/Libs/Memory_test/hds/fifo_tb/symbol.sb b/Libs/Memory_test/hds/fifo_tb/symbol.sb new file mode 100644 index 0000000..33e507e --- /dev/null +++ b/Libs/Memory_test/hds/fifo_tb/symbol.sb @@ -0,0 +1,1256 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2001,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 107,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 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\"U:\\ELN_board\\Simulation\\sdram.srec\" ( string ) +tAC = 6 ns ( time ) +tHZ = 7 ns ( time ) +tOH = 2.7 ns ( time ) +tMRD = 2 ( integer ) +tRAS = 44 ns ( time ) +tRC = 66 ns ( time ) +tRCD = 20 ns ( time ) +tRP = 20 ns ( time ) +tRRD = 15 ns ( time ) +tWRa = 7.5 ns ( time ) +tWRp = 15 ns ( time ) +tAH = 0.8 ns ( time ) +tAS = 1.5 ns ( time ) +tCH = 2.5 ns ( time ) +tCL = 2.5 ns ( time ) +tCK = 10 ns ( time ) +tDH = 0.8 ns ( time ) +tDS = 1.5 ns ( time ) +tCKH = 0.8 ns ( time ) +tCKS = 1.5 ns ( time ) +tCMH = 0.8 ns ( time ) +tCMS = 1.5 ns ( time ) " +) +header "" +) +elements [ +(GiElement +name "addr_bits" +type "integer" +value "rowAddressBitNb" +) +(GiElement +name "data_bits" +type "integer" +value "dataBitNb" +) +(GiElement +name "col_bits" +type "integer" +value "colAddressBitNb" +) +(GiElement +name "index" +type "integer" +value "0" +) +(GiElement +name "fname" +type "string" +value "\"U:\\ELN_board\\Simulation\\sdram.srec\"" +) +(GiElement +name "tAC" +type "time" +value "6 ns" +) +(GiElement +name "tHZ" +type "time" +value "7 ns" +) +(GiElement +name "tOH" +type "time" +value "2.7 ns" +) +(GiElement +name "tMRD" +type "integer" +value "2" +) +(GiElement +name "tRAS" +type "time" +value "44 ns" +) +(GiElement +name "tRC" +type "time" +value "66 ns" +) +(GiElement +name "tRCD" +type "time" +value "20 ns" +) +(GiElement +name "tRP" +type "time" +value "20 ns" +) +(GiElement +name "tRRD" +type "time" +value "15 ns" +) +(GiElement +name "tWRa" +type "time" +value "7.5 ns" +) +(GiElement +name "tWRp" +type "time" +value "15 ns" +) +(GiElement +name "tAH" +type "time" +value "0.8 ns" +) +(GiElement +name "tAS" +type "time" +value "1.5 ns" +) +(GiElement +name "tCH" +type "time" +value "2.5 ns" +) +(GiElement +name "tCL" +type "time" +value "2.5 ns" +) +(GiElement +name "tCK" +type "time" +value "10 ns" +) +(GiElement +name "tDH" +type "time" +value "0.8 ns" +) +(GiElement +name "tDS" +type "time" +value "1.5 ns" +) +(GiElement +name "tCKH" +type "time" +value "0.8 ns" +) +(GiElement +name "tCKS" +type "time" +value "1.5 ns" +) +(GiElement +name "tCMH" +type "time" +value "0.8 ns" +) +(GiElement +name "tCMS" +type "time" +value "1.5 ns" +) +] +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*43 (Net +uid 5992,0 +decl (Decl +n "sdClk" +t "std_ulogic" +o 20 +suid 68,0 +) +declText (MLText +uid 5993,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdClk : std_ulogic" +) +) +*44 (Net +uid 5998,0 +decl (Decl +n "sdCke" +t "std_ulogic" +o 19 +suid 69,0 +) +declText (MLText +uid 5999,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdCke : std_ulogic" +) +) +*45 (Net +uid 6004,0 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "( 1 DOWNTO 0 )" +o 22 +suid 70,0 +) +declText (MLText +uid 6005,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,126000,1100" +st "SIGNAL sdDqm : std_ulogic_vector( 1 DOWNTO 0 )" +) +) +*46 (Net +uid 6010,0 +decl (Decl +n "memWr_n" +t "std_ulogic" +o 9 +suid 71,0 +) +declText (MLText +uid 6011,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL memWr_n : std_ulogic" +) +) +*47 (Net +uid 6016,0 +decl (Decl +n "sdCas_n" +t "std_ulogic" +o 18 +suid 72,0 +) +declText (MLText +uid 6017,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdCas_n : std_ulogic" +) +) +*48 (Net +uid 6022,0 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 23 +suid 73,0 +) +declText (MLText +uid 6023,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdRas_n : std_ulogic" +) +) +*49 (Net +uid 6028,0 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 21 +suid 74,0 +) +declText (MLText +uid 6029,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,115500,1100" +st "SIGNAL sdCs_n : std_ulogic" +) +) +*50 (Net +uid 6048,0 +decl (Decl +n "DQ" +t "std_logic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 1 +suid 75,0 +) +declText (MLText +uid 6049,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,129500,1100" +st "SIGNAL DQ : std_logic_vector(dataBitNb-1 DOWNTO 0)" +) +) +*51 (HdlText +uid 6058,0 +optionalChildren [ +*52 (EmbeddedText +uid 6063,0 +commentText (CommentText +uid 6064,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6065,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "73000,31000,89000,39000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6066,0 +va (VaSet +font "courier,9,0" +) +xt "73200,31200,89200,35700" +st " +memDataIn <= std_ulogic_vector(DQ); +DQ <= std_logic_vector(memDataOut) when memWr_n = '0' + else (others => 'Z'); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 6059,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "73000,30000,89000,40000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6060,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*53 (Text +uid 6061,0 +va (VaSet +) +xt "73400,40000,74600,41000" +st "eb1" +blo "73400,40800" +tm "HdlTextNameMgr" +) +*54 (Text +uid 6062,0 +va (VaSet +) +xt "73400,41000,73800,42000" +st "1" +blo "73400,41800" +tm "HdlTextNumberMgr" +) +] +) +) +*55 (HdlText +uid 6138,0 +optionalChildren [ +*56 (EmbeddedText +uid 6143,0 +commentText (CommentText +uid 6144,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 6145,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "128000,62000,170000,86000" +) +oxt "0,0,18000,5000" +text (MLText +uid 6146,0 +va (VaSet +font "courier,9,0" +) +xt "128200,62200,168200,79300" +st " +commandBus <= (sdCs_n, sdRas_n, sdCas_n, memWr_n, sdDqm(1), sdDqm(0)); + + ----------------------------------------------------------------------------- + -- debug information + commandDecode: process(commandBus) + begin + case commandBus is + when inhibit => commandString <= \"inhibit \"; + when nop => commandString <= \"nop \"; + when active => commandString <= \"active \"; + when read => commandString <= \"read \"; + when write => commandString <= \"write \"; + when burstTerminate => commandString <= \"burstTerminate \"; + when precharge => commandString <= \"precharge \"; + when autoRefresh => commandString <= \"autoRefresh \"; + when loadModeReg => commandString <= \"loadModeReg \"; + when others => commandString <= \"XXXXXXXXXXXXXXXX\"; + end case; + end process commandDecode; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 24000 +visibleWidth 42000 +) +) +) +] +shape (Rectangle +uid 6139,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "128000,61000,170000,87000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 6140,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*57 (Text +uid 6141,0 +va (VaSet +) +xt "128200,87000,129800,88000" +st "eb2" +blo "128200,87800" +tm "HdlTextNameMgr" +) +*58 (Text +uid 6142,0 +va (VaSet +) +xt "128200,88000,129000,89000" +st "2" +blo "128200,88800" +tm "HdlTextNumberMgr" +) +] +) +) +*59 (Net +uid 6195,0 +decl (Decl +n "commandBus" +t "commandBusType" +o 3 +suid 76,0 +) +declText (MLText +uid 6196,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,117500,1100" +st "SIGNAL commandBus : commandBusType" +) +) +*60 (Net +uid 6207,0 +decl (Decl +n "commandString" +t "string" +b "(1 TO 16)" +o 4 +suid 78,0 +) +declText (MLText +uid 6208,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "98000,200,118000,1100" +st "SIGNAL commandString : string(1 TO 16)" +) +) +*61 (SaComponent +uid 6647,0 +optionalChildren [ +*62 (CptPort +uid 6563,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6564,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,53625,25000,54375" +) +tg (CPTG +uid 6565,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6566,0 +va (VaSet +) +xt "26000,53500,28100,54500" +st "clock" +blo "26000,54300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 20,0 +) +) +) +*63 (CptPort +uid 6567,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6568,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,39625,25000,40375" +) +tg (CPTG +uid 6569,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6570,0 +va (VaSet +) +xt "26000,39500,31400,40500" +st "ramDataValid" +blo "26000,40300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ramDataValid" +t "std_ulogic" +o 14 +suid 21,0 +) +) +) +*64 (CptPort +uid 6571,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6572,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,29625,25000,30375" +) +tg (CPTG +uid 6573,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6574,0 +va (VaSet +) +xt "26000,29500,29300,30500" +st "ramAddr" +blo "26000,30300" +) +) +thePort (LogicalPort +decl (Decl +n "ramAddr" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 3 +suid 22,0 +) +) +) +*65 (CptPort +uid 6575,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6576,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,29625,41750,30375" +) +tg (CPTG +uid 6577,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6578,0 +va (VaSet +) +xt "34800,29500,40000,30500" +st "memAddress" +ju 2 +blo "40000,30300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memAddress" +t "std_ulogic_vector" +b "( chipAddressBitNb-1 DOWNTO 0 )" +o 9 +suid 23,0 +) +) +) +*66 (CptPort +uid 6579,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6580,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,33625,25000,34375" +) +tg (CPTG +uid 6581,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6582,0 +va (VaSet +) +xt "26000,33500,30900,34500" +st "ramDataOut" +blo "26000,34300" +) +) +thePort (LogicalPort +decl (Decl +n "ramDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 24,0 +) +) +) +*67 (CptPort +uid 6583,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6584,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,33625,41750,34375" +) +tg (CPTG +uid 6585,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6586,0 +va (VaSet +) +xt "35800,33500,40000,34500" +st "memDataIn" +ju 2 +blo "40000,34300" +) +) +thePort (LogicalPort +decl (Decl +n "memDataIn" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 2 +suid 25,0 +) +) +) +*68 (CptPort +uid 6587,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6588,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,35625,41750,36375" +) +tg (CPTG +uid 6589,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6590,0 +va (VaSet +) +xt "34800,35500,40000,36500" +st "memDataOut" +ju 2 +blo "40000,36300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memDataOut" +t "std_ulogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 11 +suid 26,0 +) +) +) +*69 (CptPort +uid 6591,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6592,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,43625,41750,44375" +) +tg (CPTG +uid 6593,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6594,0 +va (VaSet +) +xt "36200,43500,40000,44500" +st "memWr_n" +ju 2 +blo "40000,44300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "memWr_n" +t "std_ulogic" +o 12 +suid 27,0 +) +) +) +*70 (CptPort +uid 6595,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6596,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,51625,25000,52375" +) +tg (CPTG +uid 6597,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6598,0 +va (VaSet +) +xt "26000,51500,28600,52500" +st "ramEn" +blo "26000,52300" +) +) +thePort (LogicalPort +decl (Decl +n "ramEn" +t "std_ulogic" +o 5 +suid 28,0 +) +) +) +*71 (CptPort +uid 6599,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6600,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,35625,25000,36375" +) +tg (CPTG +uid 6601,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6602,0 +va (VaSet +) +xt "26000,35500,28700,36500" +st "ramRd" +blo "26000,36300" +) +) +thePort (LogicalPort +decl (Decl +n "ramRd" +t "std_ulogic" +o 6 +suid 29,0 +) +) +) +*72 (CptPort +uid 6603,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6604,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,37625,25000,38375" +) +tg (CPTG +uid 6605,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6606,0 +va (VaSet +) +xt "26000,37500,28700,38500" +st "ramWr" +blo "26000,38300" +) +) +thePort (LogicalPort +decl (Decl +n "ramWr" +t "std_ulogic" +o 7 +suid 30,0 +) +) +) +*73 (CptPort +uid 6607,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6608,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "24250,55625,25000,56375" +) +tg (CPTG +uid 6609,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6610,0 +va (VaSet +) +xt "26000,55500,28100,56500" +st "reset" +blo "26000,56300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 31,0 +) +) +) +*74 (CptPort +uid 6611,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6612,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,41625,41750,42375" +) +tg (CPTG +uid 6613,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6614,0 +va (VaSet +) +xt "36600,41500,40000,42500" +st "sdCas_n" +ju 2 +blo "40000,42300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCas_n" +t "std_ulogic" +o 15 +suid 32,0 +) +) +) +*75 (CptPort +uid 6615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,47625,41750,48375" +) +tg (CPTG +uid 6617,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6618,0 +va (VaSet +) +xt "37500,47500,40000,48500" +st "sdCke" +ju 2 +blo "40000,48300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCke" +t "std_ulogic" +o 16 +suid 33,0 +) +) +) +*76 (CptPort +uid 6619,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6620,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,49625,41750,50375" +) +tg (CPTG +uid 6621,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6622,0 +va (VaSet +) +xt "37700,49500,40000,50500" +st "sdClk" +ju 2 +blo "40000,50300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdClk" +t "std_ulogic" +o 17 +suid 34,0 +) +) +) +*77 (CptPort +uid 6623,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6624,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,37625,41750,38375" +) +tg (CPTG +uid 6625,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6626,0 +va (VaSet +) +xt "37000,37500,40000,38500" +st "sdCs_n" +ju 2 +blo "40000,38300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdCs_n" +t "std_ulogic" +o 18 +suid 35,0 +) +) +) +*78 (CptPort +uid 6627,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6628,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,45625,41750,46375" +) +tg (CPTG +uid 6629,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6630,0 +va (VaSet +) +xt "37100,45500,40000,46500" +st "sdDqm" +ju 2 +blo "40000,46300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdDqm" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 19 +suid 36,0 +) +) +) +*79 (CptPort +uid 6631,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6632,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41000,39625,41750,40375" +) +tg (CPTG +uid 6633,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6634,0 +va (VaSet +) +xt "36600,39500,40000,40500" +st "sdRas_n" +ju 2 +blo "40000,40300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "sdRas_n" +t "std_ulogic" +o 20 +suid 38,0 +) +) +) +*80 (CptPort +uid 6635,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 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"43750,43600" +tm "WireNameMgr" +) +) +on &46 +) +*104 (Wire +uid 6018,0 +shape (OrthoPolyLine +uid 6019,0 +va (VaSet +vasetType 3 +) +xt "41750,42000,56250,42000" +pts [ +"41750,42000" +"56250,42000" +] +) +start &74 +end &32 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 6020,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6021,0 +va (VaSet +font "courier,12,0" +) +xt "43750,40600,50050,42000" +st "sdCas_n" +blo "43750,41800" +tm "WireNameMgr" +) +) +on &47 +) +*105 (Wire +uid 6024,0 +shape (OrthoPolyLine +uid 6025,0 +va (VaSet +vasetType 3 +) +xt "41750,40000,56250,40000" +pts [ +"41750,40000" +"56250,40000" +] +) +start &79 +end &38 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 6026,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6027,0 +va (VaSet +font "courier,12,0" +) +xt "43750,38600,48650,39900" +st "sdRas_n" +blo "43750,39600" +tm "WireNameMgr" +) +) +on &48 +) +*106 (Wire +uid 6030,0 +shape (OrthoPolyLine +uid 6031,0 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100644 index 0000000..4d4ac8c --- /dev/null +++ b/Libs/NanoBlaze/hdl/alu_RTL.vhd @@ -0,0 +1,113 @@ +ARCHITECTURE RTL OF alu IS + + signal aluCodeInt: unsigned(aluCode'range); + signal aArith: signed(opA'high+1 downto 0); + signal bArith: signed(opA'high+1 downto 0); + signal cInArith: signed(1 downto 0); + signal cInShift: std_ulogic; + signal yArith: signed(aluOut'high+1 downto 0); + signal aluOutInt: signed(aluOut'range); + +BEGIN + ------------------------------------------------------------------------------ + -- clear aluCode don't care LSB for shifts + aluCodeInt(aluCode'high downto 1) <= unsigned(aluCode(aluCode'high downto 1)); + + cleanupLsb: process(aluCode) + begin + if aluCode(aluCode'high) = '1' then + aluCodeInt(0) <= '0'; + else + aluCodeInt(0) <= aluCode(0); + end if; + end process cleanupLsb; + + ------------------------------------------------------------------------------ + -- values for arithmetic operations + aArith <= signed(resize(unsigned(opA), aArith'length)); + bArith <= signed(resize(unsigned(opB), bArith'length)); + cInArith <= (0 => cIn, others => '0'); + + process(aluCode, cIn, opA) + begin + case aluCode(2 downto 1) is + when "00" => cInShift <= cIn; + when "01" => cInShift <= opA(opA'high); + when "10" => cInShift <= opA(opA'low); + when "11" => cInShift <= aluCode(0); + when others => cInShift <= '-'; + end case; + end process; + + ------------------------------------------------------------------------------ + -- alu operations + aluOperation: process( + aluCodeInt, + opA, opB, + aArith, bArith, cInArith, + cInShift, + yArith, aluOutInt + ) + variable xorAcc: std_ulogic; + begin + yArith <= (others => '-'); + cOut <= '-'; + aluOutInt <= (others => '-'); + case to_integer(aluCodeInt) is + when 0 => -- LOAD sX, kk + aluOutInt <= opB; + when 2 => -- INPUT sX, pp + aluOutInt <= opB; + when 3 => -- FETCH sX, ss + aluOutInt <= opB; + when 5 => -- AND sX, kk + aluOutInt <= opA and opB; + cOut <= '0'; + when 6 => -- OR sX, kk + aluOutInt <= opA or opB; + cOut <= '0'; + when 7 => -- XOR sX, kk + aluOutInt <= opA xor opB; + cOut <= '0'; + when 9 => -- TEST sX, kk + aluOutInt <= opA and opB; + xorAcc := '0'; + for index in aluOutInt'range loop + xorAcc := xorAcc xor aluOutInt(index); + end loop; + cOut <= xorAcc; + when 10 => -- COMPARE sX, kk + yArith <= aArith - bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 12 => -- ADD sX, kk + yArith <= aArith + bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 13 => -- ADDCY sX, kk + yArith <= (aArith + bArith) + cInArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 14 => -- SUB sX, kk + yArith <= aArith - bArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 15 => -- SUBCY sX, kk + yArith <= (aArith - bArith) - cInArith; + aluOutInt <= yArith(aluOut'range); + cOut <= yArith(yArith'high); + when 16 to 23 => -- SL sX + aluOutInt <= opA(opA'high-1 downto 0) & cInShift; + cOut <= opA(opA'high); + when 24 to 31 => -- SR sX + aluOutInt <= cInShift & opA(opA'high downto 1); + cOut <= opA(0); + when others => + aluOutInt <= (others => '-'); + end case; + end process aluOperation; + + aluOut <= aluOutInt; + zero <= '1' when aluOutInt = 0 else '0'; + +END ARCHITECTURE RTL; diff --git a/Libs/NanoBlaze/hdl/branchStack_RTL.vhd b/Libs/NanoBlaze/hdl/branchStack_RTL.vhd new file mode 100644 index 0000000..0a76765 --- /dev/null +++ b/Libs/NanoBlaze/hdl/branchStack_RTL.vhd @@ -0,0 +1,40 @@ +ARCHITECTURE RTL OF branchStack IS + + subtype progCounterType is unsigned(progCounter'range); + type progCounterArrayType is array (0 to 2**stackPointerBitNb) of progCounterType; + signal progCounterArray : progCounterArrayType; + + signal writePointer : unsigned(stackPointerBitNb-1 downto 0); + signal readPointer : unsigned(stackPointerBitNb-1 downto 0); + +BEGIN + ------------------------------------------------------------------------------ + -- stack pointers + updateStackPointer: process(reset, clock) + begin + if reset = '1' then + writePointer <= (others => '0'); + elsif rising_edge(clock) then + if storePC = '1' then + writePointer <= writePointer + 1; + elsif prevPC = '1' then + writePointer <= writePointer - 1; + end if; + end if; + end process updateStackPointer; + + readPointer <= writePointer - 1; + + ------------------------------------------------------------------------------ + -- program counters stack + updateStack: process(reset, clock) + begin + if rising_edge(clock) then + if storePc = '1' then + progCounterArray(to_integer(writePointer)) <= progCounter; + end if; + storedProgCounter <= progCounterArray(to_integer(readPointer)); + end if; + end process updateStack; + +END ARCHITECTURE RTL; diff --git a/Libs/NanoBlaze/hdl/controller_RTL.vhd b/Libs/NanoBlaze/hdl/controller_RTL.vhd new file mode 100644 index 0000000..fa8bc5c --- /dev/null +++ b/Libs/NanoBlaze/hdl/controller_RTL.vhd @@ -0,0 +1,236 @@ +ARCHITECTURE RTL OF controller IS + + signal en1, enInt: std_ulogic; + + constant opCodeLength : integer := 5; + subtype opCodeType is std_ulogic_vector(opCodeLength-1 downto 0); + constant opLoad : opCodeType := "00000"; + constant opInput : opCodeType := "00010"; + constant opFetch : opCodeType := "00011"; + constant opAnd : opCodeType := "00101"; + constant opOr : opCodeType := "00110"; + constant opXor : opCodeType := "00111"; + constant opTest : opCodeType := "01001"; + constant opComp : opCodeType := "01010"; + constant opAdd : opCodeType := "01100"; + constant opAddCy : opCodeType := "01101"; + constant opSub : opCodeType := "01110"; + constant opSubCy : opCodeType := "01111"; + constant opShRot : opCodeType := "10000"; + constant opRet : opCodeType := "10101"; + constant opOutput: opCodeType := "10110"; + constant opStore : opCodeType := "10111"; + constant opCall : opCodeType := "11000"; + constant opJump : opCodeType := "11010"; + constant opIntF : opCodeType := "11110"; + + constant branchConditionLength : integer := 3; + subtype branchConditionType is std_ulogic_vector(branchConditionLength-1 downto 0); + constant brAw : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + signal aluOpSel: std_ulogic; + signal regWriteEn: std_ulogic; + + signal flagsEn, flagsEnable: std_ulogic; + signal carrySaved: std_ulogic; + signal zeroSaved: std_ulogic; + + signal branchEnable1, branchEnable: std_ulogic; + signal discardOpCode: std_ulogic; + + signal updateIntFlag: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + -- Enable signal + buildEnable: process(reset, clock) + begin + if reset = '1' then + en1 <= '0'; + elsif rising_edge(clock) then + en1 <= '1'; + end if; + end process buildEnable; + + enInt <= en1 and en; -- don't enable very first instruction twice + + ------------------------------------------------------------------------------ + -- ALU controls + selectdataSource: process(opCode) + begin + aluOpSel <= '0'; + portInSel <= '0'; + scratchpadSel <= '0'; + case opCode(opCodeLength-1 downto 0) is + when opLoad => aluOpSel <= '1'; + when opInput => portInSel <= '1'; + when opFetch => scratchpadSel <= '1'; + when opAnd => aluOpSel <= '1'; + when opOr => aluOpSel <= '1'; + when opXor => aluOpSel <= '1'; + when opTest => aluOpSel <= '1'; + when opComp => aluOpSel <= '1'; + when opAdd => aluOpSel <= '1'; + when opAddCy => aluOpSel <= '1'; + when opSub => aluOpSel <= '1'; + when opSubCy => aluOpSel <= '1'; + when opShRot => aluOpSel <= '1'; + when others => aluOpSel <= '-'; + portInSel <= '-'; + scratchpadSel <= '-'; + end case; + end process selectdataSource; + + registerFileSel <= aluOpSel and twoRegInstr; + instrDataSel <= aluOpSel and (not twoRegInstr); + + regWriteEn <= enInt and (not discardOpCode); + + regWriteTable: process(opCode, regWriteEn) + begin + case opCode(opCodeLength-1 downto 0) is + when opLoad => regWrite <= regWriteEn; + when opInput => regWrite <= regWriteEn; + when opFetch => regWrite <= regWriteEn; + when opAnd => regWrite <= regWriteEn; + when opOr => regWrite <= regWriteEn; + when opXor => regWrite <= regWriteEn; + when opAdd => regWrite <= regWriteEn; + when opAddCy => regWrite <= regWriteEn; + when opSub => regWrite <= regWriteEn; + when opSubCy => regWrite <= regWriteEn; + when opShRot => regWrite <= regWriteEn; + when others => regWrite <= '0'; + end case; + end process regWriteTable; + + ------------------------------------------------------------------------------ + -- I/O controls + readStrobe <= enInt when (opCode = opInput) and (discardOpCode = '0') + else '0'; + writeStrobe <= enInt when (opCode = opOutput) and (discardOpCode = '0') + else '0'; + + ------------------------------------------------------------------------------ + -- scratchpad controls + scratchpadWrite <= '1' when opCode = opStore else '0'; + + ------------------------------------------------------------------------------ + -- Carry logic + flagsEn <= enInt and (not branchEnable); + + flagsEnableTable: process(opCode, flagsEn) + begin + case opCode(opCodeLength-1 downto 0) is + when opAnd => flagsEnable <= flagsEn; + when opOr => flagsEnable <= flagsEn; + when opXor => flagsEnable <= flagsEn; + when opTest => flagsEnable <= flagsEn; + when opComp => flagsEnable <= flagsEn; + when opAdd => flagsEnable <= flagsEn; + when opAddCy => flagsEnable <= flagsEn; + when opSub => flagsEnable <= flagsEn; + when opSubCy => flagsEnable <= flagsEn; + when opShRot => flagsEnable <= flagsEn; + when others => flagsEnable <= '0'; + end case; + end process flagsEnableTable; + + saveCarries: process(reset, clock) + begin + if reset = '1' then + carrySaved <= '0'; + zeroSaved <= '0'; + elsif rising_edge(clock) then + if flagsEnable = '1' then + carrySaved <= cOut; + zeroSaved <= zero; + end if; + end if; + end process saveCarries; + + cIn <= carrySaved; + + ------------------------------------------------------------------------------ + -- Program counter controls + checkBranchCondition: process(branchCond, zeroSaved, carrySaved) + begin + case branchCond(branchConditionLength-1 downto 0) is + when brAw => branchEnable1 <= '1'; + when brZ => branchEnable1 <= zeroSaved; + when brNZ => branchEnable1 <= not zeroSaved; + when brC => branchEnable1 <= carrySaved; + when brNC => branchEnable1 <= not carrySaved; + when others => branchEnable1 <= '-'; + end case; + end process checkBranchCondition; + + branchEnableTable: process(opCode, branchEnable1, discardOpCode) + begin + if discardOpCode = '0' then + case opCode(opCodeLength-1 downto 0) is + when opRet => branchEnable <= branchEnable1; + when opCall => branchEnable <= branchEnable1; + when opJump => branchEnable <= branchEnable1; + when others => branchEnable <= '0'; + end case; + else + branchEnable <= '0'; + end if; + end process branchEnableTable; + + progCounterControlTable: process(opCode, enInt, branchEnable) + begin + incPC <= enInt; + loadInstrAddress <= '0'; + loadStoredPC <= '0'; + case opCode(opCodeLength-1 downto 0) is + when opRet => incPC <= not branchEnable; + loadStoredPC <= enInt and branchEnable; + when opCall => incPC <= not branchEnable; + loadInstrAddress <= enInt and branchEnable; + when opJump => incPC <= not branchEnable; + loadInstrAddress <= enInt and branchEnable; + when others => null; + end case; + end process progCounterControlTable; + + -- If a branch condition is met, the next operation has to be discarded. + -- This is due to the synchronous operation of the program ROM: the + -- instructions are provided one clock period after the program counter. + -- so while the branch operation is processed, the next instruction is + -- already being fetched. + delayBranchEnable: process(reset, clock) + begin + if reset = '1' then + discardOpCode <= '0'; + elsif rising_edge(clock) then + discardOpCode <= branchEnable; + end if; + end process delayBranchEnable; + + ------------------------------------------------------------------------------ + -- Stack pointer controls + pcStackControlTable: process(discardOpCode, opCode, enInt) + begin + storePC <= '0'; + prevPC <= '0'; + if discardOpCode = '0' then + case opCode(opCodeLength-1 downto 0) is + when opRet => prevPC <= enInt; + when opCall => storePC <= enInt; + when others => null; + end case; + end if; + end process pcStackControlTable; + + + ------------------------------------------------------------------------------ + -- interrupt control + updateIntFlag <= '1' when opCode = opIntF else '0'; + +END ARCHITECTURE RTL; diff --git a/Libs/NanoBlaze/hdl/instructionDecoder_RTL.vhd b/Libs/NanoBlaze/hdl/instructionDecoder_RTL.vhd new file mode 100644 index 0000000..7c7203b --- /dev/null +++ b/Libs/NanoBlaze/hdl/instructionDecoder_RTL.vhd @@ -0,0 +1,56 @@ +ARCHITECTURE RTL OF instructionDecoder IS + + constant opCodeIndexH : integer := instruction'high; + constant opCodeIndexL : integer := opCodeIndexH - opCodeBitNb + 1; + + constant twoRegInstrIndex : integer := opCodeIndexL - 1; + constant ioAddrIndexed : integer := twoRegInstrIndex; + + constant addrAIndexH : integer := twoRegInstrIndex - 1; + constant addrAIndexL : integer := addrAIndexH - registerAddressBitNb + 1; + + constant immediateDataIndexH : integer := registerBitNb-1; + constant immediateDataIndexL : integer := 0; + constant addrBIndexH : integer := addrAIndexL - 1; + constant addrBIndexL : integer := addrBIndexH - registerAddressBitNb + 1; + + constant aluCodeIndexH : integer := opCodeIndexH; + constant aluCodeIndexL : integer := aluCodeIndexH - aluCodeBitNb + 1; + + constant portAddressH : integer := registerBitNb-1; + constant portAddressL : integer := portAddressH-portAddressBitNb+1; + constant spadAddressH : integer := registerBitNb-1; + constant spadAddressL : integer := spadAddressH-spadAddressBitNb+1; + + constant branchCondH : integer := opCodeIndexL-1; + constant branchCondL : integer := branchCondH-branchCondBitNb+1; + +BEGIN + ------------------------------------------------------------------------------ + -- ALU control + aluCode <= + instruction(aluCodeIndexH downto aluCodeIndexL) + when instruction(aluCodeIndexH) = '0' else + '1' & instruction(aluCodeBitNb-2 downto 0); + opCode <= instruction(opCodeIndexH downto opCodeIndexL); + twoRegInstr <= instruction(twoRegInstrIndex); + addrA <= unsigned(instruction(addrAIndexH downto addrAIndexL)); + addrB <= unsigned(instruction(addrBIndexH downto addrBIndexL)); + instrData <= signed(instruction(immediateDataIndexH downto immediateDataIndexL)); + + ------------------------------------------------------------------------------ + -- I/O control + portIndexedSel <= instruction(ioAddrIndexed); + portAddress <= unsigned(instruction(portAddressH downto portAddressL)); + + ------------------------------------------------------------------------------ + -- scratchpad control + spadIndexedSel <= instruction(ioAddrIndexed); + spadAddress <= unsigned(instruction(spadAddressH downto spadAddressL)); + + ------------------------------------------------------------------------------ + -- branch control + branchCond <= instruction(branchCondH downto branchCondL); + instrAddress <= unsigned(instruction(instrAddress'range)); + +END ARCHITECTURE RTL; diff --git a/Libs/NanoBlaze/hdl/nanoAsm.pl b/Libs/NanoBlaze/hdl/nanoAsm.pl new file mode 100644 index 0000000..c80bcf7 --- /dev/null +++ b/Libs/NanoBlaze/hdl/nanoAsm.pl @@ -0,0 +1,565 @@ +#!/usr/bin/env perl + +my $indent = ' ' x 2; +my $separator = '-' x 80; + +################################################################################ +# Input arguments +# +use Getopt::Std; +my %opts; +getopts('hva:d:r:kz', \%opts); + +die("\n". + "Usage: $0 [options] fileSpec\n". + "\n". + "Options:\n". + "${indent}-h display this help message\n". + "${indent}-v verbose\n". + "${indent}-a bitNb the number of program address bits\n". + "${indent}-d bitNb the number of data bits\n". + "${indent}-r bitNb the number of register address bits\n". + "${indent}-k keep source comments in VHDL code\n". + "${indent}-z zero don't care bits in VHDL ROM code\n". + "\n". + "Assemble code to VHDL for the nanoBlaze processor.\n". + "\n". + "More information with: perldoc $0\n". + "\n". + "" + ) if ($opts{h}); + +my $verbose = $opts{v}; +my $keepComments = $opts{k}; +my $zeroDontCares = $opts{z}; +my $addressBitNb = $opts{a} || 10; +my $registerBitNb = $opts{d} || 8; +my $registerAddressBitNb = $opts{r} || 4; + +my $asmFileSpec = $ARGV[0] || 'nanoTest.asm'; +my $outFileSpec = $ARGV[1] || 'rom_mapped.vhd'; + +#------------------------------------------------------------------------------- +# System constants +# +my $binaryOpCodeLength = 6; +my $binaryBranchLength = 5; +my $binaryBranchConditionLength = 3; + +my $opCodeBaseLength = 10; +my $vhdlAddressLength = 14; + +#------------------------------------------------------------------------------- +# Derived values +# + # file specs +my $baseFileSpec = $asmFileSpec; +$baseFileSpec =~ s/\..*//i; +my $asm1FileSpec = "$baseFileSpec.asm1"; # formatted assembly code +my $asm2FileSpec = "$baseFileSpec.asm2"; # code with addresses replaced +my $vhdlFileSpec = "$baseFileSpec.vhd"; + # instruction length +my $binaryOperationInstructionLength = + $binaryOpCodeLength + + $registerAddressBitNb + + $registerBitNb; +my $binaryBranchInstructionLength = + $binaryBranchLength + + $binaryBranchConditionLength + + $addressBitNb; +my $binaryInstructionLength = $binaryOperationInstructionLength; +if ($binaryBranchInstructionLength > $binaryInstructionLength) { + $binaryInstructionLength = $binaryBranchInstructionLength +} + # assembler string lengths +my $registerCharNb = int( ($registerBitNb-1)/4 ) + 1; +my $addressCharNb = int( ($addressBitNb-1)/4 ) + 1; + # vhdl string lengths +my $vhdlOpCodeLength = $binaryOpCodeLength + 4; +my $opCodeTotalLength = 22 + $registerCharNb; +my $vhdlOperand1Length = $registerAddressBitNb + 3; +my $vhdlOperand2Length = $registerBitNb + 4; +if ($addressBitNb + 3 > $vhdlOperand2Length) { + $vhdlOperand2Length = $addressBitNb + 3 +} +my $vhdlTotalLength = $vhdlOpCodeLength; +$vhdlTotalLength = $vhdlTotalLength + $vhdlOperand1Length + $vhdlOperand2Length; +$vhdlTotalLength = $vhdlTotalLength + 2*2; # '& ' +$vhdlTotalLength = $vhdlTotalLength + 1; # ',' + +#------------------------------------------------------------------------------- +# System variables +# +my %constants = (); +my %addresses = (); + +################################################################################ +# Functions +# + +#------------------------------------------------------------------------------- +# Find constant from "CONSTANT" statement +# +sub findNewConstant { + my ($codeLine) = @_; + + $codeLine =~ s/CONSTANT\s+//; + my ($name, $value) = split(/,\s*/, $codeLine); + $value = hex($value); + + return ($name, $value); +} + +#------------------------------------------------------------------------------- +# Find address from "ADDRESS" statement +# +sub findNewAddress { + my ($codeLine) = @_; + + $codeLine =~ s/ADDRESS\s*//; + my $address = hex($codeLine); + + return $address; +} + +#------------------------------------------------------------------------------- +# Format opcodes +# +sub prettyPrint { + my ($codeLine) = @_; + + my ($opcode, $arguments) = split(/ /, $codeLine, 2); + $opcode = $opcode . ' ' x ($opCodeBaseLength - length($opcode)); + $arguments =~ s/,*\s+/, /; + $codeLine = $opcode . $arguments; + + return $codeLine; +} + +#------------------------------------------------------------------------------- +# Format to binary +# +sub toBinary { + my ($operand, $bitNb) = @_; + + #$operand = sprintf("%0${bitNb}b", $operand); + + my $hexCharNb = int($bitNb/4) + 1; + $operand = sprintf("%0${hexCharNb}X", $operand); + $operand =~ s/0/0000/g; + $operand =~ s/1/0001/g; + $operand =~ s/2/0010/g; + $operand =~ s/3/0011/g; + $operand =~ s/4/0100/g; + $operand =~ s/5/0101/g; + $operand =~ s/6/0110/g; + $operand =~ s/7/0111/g; + $operand =~ s/8/1000/g; + $operand =~ s/9/1001/g; + $operand =~ s/A/1010/g; + $operand =~ s/B/1011/g; + $operand =~ s/C/1100/g; + $operand =~ s/D/1101/g; + $operand =~ s/E/1110/g; + $operand =~ s/F/1111/g; + $operand = substr($operand, length($operand)-$bitNb, $bitNb); + + return $operand; +} + +################################################################################ +# Program start +# + +#------------------------------------------------------------------------------- +# Display information +# +if ($verbose > 0) { + print "$separator\n"; + print "Assembling $asmFileSpec to $vhdlFileSpec\n"; +} + +#------------------------------------------------------------------------------- +# Calculate adresses, store address labels +# +if ($verbose > 0) { + print "${indent}Pass 1: from $asmFileSpec to $asm1FileSpec\n"; +} + +my $romAddress = 0; +open(asmFile, "<$asmFileSpec") or die "Unable to open file, $!"; +open(asm1File, ">$asm1FileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); + # split code and comment + my ($codeLine, $comment) = split(/;/, $line, 2); + # handle address label + if ($codeLine =~ m/:/) { + (my $label, $codeLine) = split(/:/, $codeLine); + $label =~ s/\s*//; + print asm1File "; _${label}_:\n"; + $addresses{$label} = sprintf("%0${addressCharNb}X", $romAddress); + } + # cleanup code + $codeLine =~ s/\s+/ /g; + $codeLine =~ s/\A\s//; + $codeLine =~ s/\s\Z//; + $codeLine =~ s/\s,/,/; + if ($codeLine) { + # handle ADDRESS declaration + if ($codeLine =~ m/ADDRESS/) { + $romAddress = findNewAddress($codeLine); + } + # handle CONSTANT declaration + elsif ($codeLine =~ m/CONSTANT/) { + ($name, $value) = findNewConstant($codeLine); + $constants{$name} = sprintf("%0${registerCharNb}X", $value); + } + # print cleaned-up code + else { + $codeLine = prettyPrint($codeLine); + print asm1File sprintf("%0${addressCharNb}X", $romAddress), ": $codeLine"; + if ($comment) { + print asm1File " ;$comment"; + } + print asm1File "\n"; + $romAddress = $romAddress + 1; + } + } + else { + print asm1File ";$comment\n"; + } +} +close(asmFile); +close(asm1File); + +#------------------------------------------------------------------------------- +# Replace constant values and address labels +# +if ($verbose > 0) { + print "${indent}Pass 2: from $asm1FileSpec to $asm2FileSpec\n"; +} + +open(asm2File, ">$asm2FileSpec") or die "Unable to open file, $!"; +open(asm1File, "<$asm1FileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); + # split code and comment + my ($opcode, $comment) = split(/;/, $line, 2); + if ( ($line =~ m/;/) and ($comment eq '') ) { + $comment = ' '; + } + # cleanup code + $opcode =~ s/\s+\Z//; + # replace constants + foreach my $name (keys %constants) { + $opcode =~ s/$name/$constants{$name}/g; + } + # replace addresses + foreach my $label (keys %addresses) { + $opcode =~ s/$label/$addresses{$label}/g; + } + # cleanup code + $opcode = uc($opcode); + $opcode =~ s/\sS([0-9A-F])/ s$1/g; + # print cleaned-up code + if ($comment) { + if ($opcode) { + $opcode = $opcode . ' ' x ($opCodeTotalLength - length($opcode)); + } + $comment =~ s/\s+\Z//; + print asm2File "$opcode;$comment\n"; + } + else { + print asm2File "$opcode\n"; + } +} +close(asm1File); +close(asm2File); + +#------------------------------------------------------------------------------- +# Write VHDL ROM code +# +if ($verbose > 0) { + print "${indent}Pass 3: from $asm2FileSpec to $vhdlFileSpec\n"; +} +open(vhdlFile, ">$vhdlFileSpec") or die "Unable to open file, $!"; +print vhdlFile < '0', others => '-'); + constant shRotR : shRotDirType := (0 => '1', others => '-'); + + subtype branchCodeType is std_ulogic_vector(4 downto 0); + constant brRet : branchCodeType := "10101"; + constant brCall : branchCodeType := "11000"; + constant brJump : branchCodeType := "11010"; + constant brReti : branchCodeType := "11100"; + constant brEni : branchCodeType := "11110"; + + subtype branchConditionType is std_ulogic_vector(2 downto 0); + constant brDo : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( +DONE +open(asm2File, "<$asm2FileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); + # split code and comment + my ($opcode, $comment) = split(/;/, $line, 2); + if ( ($line =~ m/;/) and ($comment eq '') ) { + $comment = ' '; + } + # addresses to VHDL + my $address; + if ($opcode) { + ($address, $opcode) = split(/:\s+/, $opcode, 2); + $address = '16#' . $address . '# =>'; + $address = ' ' x ($vhdlAddressLength - length($address)) . $address; + } + # opcode to VHDL + if ($opcode) { + if ($comment eq '') { + $comment = ' ' . $opcode; + } + else { + $comment = ' ' . $opcode . ';' . $comment; + } + # replace NOP + $opcode =~ s/\ANOP/LOAD s0, s0/; + # split opcodes and operands + $opcode =~ s/\s+/ /; + $opcode =~ s/\s+\Z//; + ($opcode, my $operand1, my $operand2) = split(/\s/, $opcode); + $operand1 =~ s/,//; + $operand1 =~ s/S/s/; + $operand2 =~ s/S/s/; + if ( ($opcode =~ m/\ASL/) or ($opcode =~ m/\ASR/) ) { + $operand2 = substr($opcode, 0, 3); + $opcode = 'SHIFT'; + } + if ( ($opcode =~ m/\ARL/) or ($opcode =~ m/\ARR/) ) { + $operand2 = substr($opcode, 0, 2); + $opcode = 'ROT'; + } + if ( ($opcode eq 'JUMP') or ($opcode eq 'CALL') or ($opcode eq 'RETURN') ) { + unless ($operand2) { + unless ($opcode eq 'RETURN') { + $operand2 = $operand1; + } + $operand1 = 'AW'; # AlWays + } + } + #........................................................................... + # opcodes to VHDL + $opcode =~ s/LOAD/opLoadC/; + $opcode =~ s/AND/opAndC/; + $opcode =~ s/XOR/opXorC/; + $opcode =~ s/ADDCY/opAddCyC/; + $opcode =~ s/SUBCY/opSubCyC/; + $opcode =~ s/ADD/opAddC/; + $opcode =~ s/SUB/opSubC/; + $opcode =~ s/SHIFT/opShRot/; + $opcode =~ s/ROT/opShRot/; + $opcode =~ s/COMPARE/opCompC/; + $opcode =~ s/TEST/opTestC/; + $opcode =~ s/FETCH/opFetchC/; + $opcode =~ s/STORE/opStoreC/; + $opcode =~ s/OR/opOrC/; + $opcode =~ s/INPUT/opInputC/; + $opcode =~ s/OUTPUT/opOutputC/; + $opcode =~ s/JUMP/brJump/; + $opcode =~ s/CALL/brCall/; + $opcode =~ s/RETURN/brRet/; + if ($operand2 =~ m/s[0-9A-F]/) { + $opcode =~ s/C\Z/R/; + } + $opcode = $opcode . ' ' x ($vhdlOpCodeLength - length($opcode)) . '& '; + #........................................................................... + # register as first operand + if ($operand1 =~ m/s[0-9A-F]/) { + $operand1 =~ s/\As//; + $operand1 = '"' . toBinary($operand1, $registerAddressBitNb) . '"'; + } + # test condition + $operand1 =~ s/NC/brNC/; + $operand1 =~ s/NZ/brNZ/; + $operand1 =~ s/\AC/brC/; + $operand1 =~ s/\AZ/brZ/; + $operand1 =~ s/AW/brDo/; + if ($opcode =~ m/brRet/) { + $operand2 = 0; + } + if ($operand2 eq '') { + $operand1 = $operand1 . ','; + } + $operand1 = $operand1 . ' ' x ($vhdlOperand1Length - length($operand1)); + unless ($operand2 eq '') { + $operand1 = $operand1 . '& '; + } +#print "|$opcode| |$operand1| |$operand2|\n"; + #........................................................................... + # register as second operand + $operand2 =~ s/\A\((.*)\)\Z/$1/; + if ($operand2 =~ m/s[0-9A-F]/) { + $operand2 =~ s/\As//; + $operand2 = toBinary($operand2, $registerAddressBitNb); + if ($registerBitNb > $registerAddressBitNb) { + $operand2 = $operand2 . '-' x ($registerBitNb - $registerAddressBitNb); + if ($zeroDontCares) { + $operand2 =~ s/\-/0/g; + } + } + } + # address as second operand + elsif ($opcode =~ m/\Abr/) { + my $fill = ''; + if ($binaryBranchInstructionLength < $binaryInstructionLength) { + $fill = '-' x ($binaryInstructionLength - $binaryBranchInstructionLength); + if ($zeroDontCares) { + $fill =~ s/\-/0/g; + } + } + if ( ($opcode =~ m/Ret/) ) { + $operand2 = $fill . '-' x $addressBitNb; + } + else { + $operand2 = $fill . toBinary(hex($operand2), $addressBitNb); + } + } + # shift and rotate operators + elsif ($opcode =~ m/opShRot/) { + $operand2 =~ s/SL0/shRotL & shRotLd0/; + $operand2 =~ s/SL1/shRotL & shRotLd1/; + $operand2 =~ s/SLX/shRotL & shRotLdL/; + $operand2 =~ s/SLA/shRotL & shRotLdC/; + $operand2 =~ s/SR0/shRotR & shRotLd0/; + $operand2 =~ s/SR1/shRotR & shRotLd1/; + $operand2 =~ s/SRX/shRotR & shRotLdM/; + $operand2 =~ s/SRA/shRotR & shRotLdC/; + $operand2 =~ s/RL/shRotL & shRotLdH/; + $operand2 =~ s/RR/shRotR & shRotLdL/; + } + # constant as second operand + else { + $operand2 = toBinary(hex($operand2), $registerBitNb); + if ($registerAddressBitNb > $registerBitNb) { + $operand2 = '-' x ($registerAddressBitNb - $registerBitNb) . $operand2; + } + } + unless ($opcode =~ m/opShRot/) { + $operand2 = '"' . $operand2 . '"'; + } + # add separator at end + if ($operand2) { + $operand2 = $operand2 . ','; + } + #........................................................................... + # concatenate opcode and operands + $opcode = $opcode . $operand1 . $operand2; + } + else { + $address = ' ' x $vhdlAddressLength; + } + # print VHDL code + if ($keepComments == 0) { + if ($opcode) { + print vhdlFile "$address $opcode\n"; + } + } + else { + $opcode = $opcode . ' ' x ($vhdlTotalLength - length($opcode)); + if ($comment) { + $comment =~ s/\s+\Z//; + print vhdlFile "$address $opcode--$comment\n"; + } + else { + print vhdlFile "$address $opcode\n"; + } + } +} +close(asm2File); +print vhdlFile < (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= memoryArray(to_integer(address)); + end if; + end if; + end process; + +END ARCHITECTURE mapped; +DONE +close(vhdlFile); + +#------------------------------------------------------------------------------- +# Delete original file and copy VHDL file +# +if ($verbose > 0) { + print "Copying $vhdlFileSpec to $outFileSpec\n"; +} + +use File::Copy; +unlink($outFileSpec); +copy($vhdlFileSpec, $outFileSpec) or die "File cannot be copied."; +#rename($vhdlFileSpec, $outFileSpec); + +if ($verbose > 0) { + print "$separator\n"; +} diff --git a/Libs/NanoBlaze/hdl/nanoPascal.pl b/Libs/NanoBlaze/hdl/nanoPascal.pl new file mode 100644 index 0000000..833836a --- /dev/null +++ b/Libs/NanoBlaze/hdl/nanoPascal.pl @@ -0,0 +1,1198 @@ +#!/usr/bin/perl + +my $indent = ' ' x 2; +my $separator = '-' x 80; + +################################################################################ +# Input arguments +# +use Getopt::Std; +my %opts; +getopts('hva:d:r:kc', \%opts); + +die("\n". + "Usage: $0 [options] fileSpec\n". + "\n". + "Options:\n". + "${indent}-h display this help message\n". + "${indent}-v verbose\n". + "${indent}-a bitNb the number of program address bits\n". + "${indent}-d bitNb the number of data bits\n". + "${indent}-r bitNb the number of register address bits\n". + "${indent}-k keep intermediate files\n". + "${indent}-c clean temporary work files\n". + "\n". + "Compiles a Pascal program to assembler code for the nanoBlaze processor.\n". + "\n". + "More information with: perldoc $0\n". + "\n". + "" + ) if ($opts{h}); + +my $verbose = $opts{v}; +my $keepIntermediateFiles= $opts{k}; +my $cleanTempFiles = $opts{c}; +my $addressBitNb = $opts{a} || 10; +my $registerBitNb = $opts{d} || 8; +my $registerAddressBitNb = $opts{r} || 4; + +my $pascalFileSpec = $ARGV[0] || 'nanoTest.pas'; +my $asmFileSpec = $ARGV[1] || 'nanoTest.asm'; + +#------------------------------------------------------------------------------- +# System constants +# +my $mainProgram = 'mainProgram'; +my $wordHexCharNb = 4; +my $firstRegister = 2; # reserve 2 registers for internal calculations +my $functionReturnRegister = 's0'; +my $conditionRegister = 's1'; +my $memoryAccessRegister = 's1'; +my $partialOperationRegister = 's1'; + +#------------------------------------------------------------------------------- +# Derived values +# + # file specs +my $baseFileSpec = $pascalFileSpec; +$baseFileSpec =~ s/\..*//i; +my $temp1FileSpec = "$baseFileSpec.tmp1"; +my $temp2FileSpec = "$baseFileSpec.tmp2"; +my $registersFileSpec = "${baseFileSpec}_registers.txt"; # register assignments +my $asm1FileSpec = "$baseFileSpec.asm1"; + +#------------------------------------------------------------------------------- +# Assembler file formatting constants +# +my $asmFirstIndent = ' ' x 24; +my $asmLineLength = 80; +my $commentStart = $asmFirstIndent . ';'; +my $separator1 = fillString($commentStart, '=', $asmLineLength); +my $separator2 = fillString($commentStart, '-', $asmLineLength); +my $opcodeLength = 10; +my $firstArgumentLength = 6; +my $constantMaxLength = 8; + +#------------------------------------------------------------------------------- +# System variables +# +my $currentPass = 0; +my %constants = (); +my %variables = (); +my %registers = (); +my @routines = (); + +################################################################################ +# Functions +# + +#------------------------------------------------------------------------------- +# Swap temporary filespecs from one pass to the other +# +sub swapTempFileSpecs { + my ($inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec) = @_; + # swap to tmp1 -> tmp2 + if ($outputFileSpec eq $temp1FileSpec) { + $inputFileSpec = $temp1FileSpec; + $outputFileSpec = $temp2FileSpec; + } + # swap to tmp2 -> tmp2 + else { + $inputFileSpec = $temp2FileSpec; + $outputFileSpec = $temp1FileSpec; + } + + return ($inputFileSpec, $outputFileSpec); +} + +#------------------------------------------------------------------------------- +# Fill string to a fixed length with a given character +# +sub fillString { + my ($string, $character, $length) = @_; + # fill string + $string .= $character x ($length - length($string)); + + return ($string); +} + +#------------------------------------------------------------------------------- +# Assign registers to all variables +# +sub buildConstants { + my ($mainProgram, %constants) = @_; + # loop on routines + foreach my $subroutine (keys(%constants)) { +#print "$subroutine:\n"; + # build array + $constants{$subroutine} =~ s/\s*\;\Z//; + $constants{$subroutine} =~ s/\s*=\s*/=/g; + my @procedureConstants = split(/\;/, $constants{$subroutine}); + # build hash + my %procedureConstants; + for my $index (0 .. $#procedureConstants) { + my ($name, $value) = split(/\=/, $procedureConstants[$index]); +#print "$name: $value\n"; + $value =~ s/\$([0-9A-Fa-f]+)/0x$1/g; + foreach my $alreadyDeclared (keys(%procedureConstants)) { + $value =~ s/$alreadyDeclared/($procedureConstants{$alreadyDeclared})/g; + } + $value = eval($value); + $procedureConstants{$name} = $value; +#print " $name = $procedureConstants{$name}\n"; + } + $constants{$subroutine} = \%procedureConstants; + } + # convert to hexadecimal + foreach my $subroutine (keys(%constants)) { + my $replacement_ref = $constants{$subroutine}; + foreach my $name (keys(%$replacement_ref)) { + my $value = $$replacement_ref{$name}; + $value = '$' . sprintf('%X', $value); + $$replacement_ref{$name} = $value; + } + } + foreach my $subroutine (keys(%constants)) { + $line =~ s/$name/$$replacement_ref{$name}/g; + } + + return (%constants); +} + +#------------------------------------------------------------------------------- +# Assign registers to variables within a routine +# +sub assignRegistersToRoutine { + my ($startIndex, $variables) = @_; + # build array + $variables =~ s/\;\Z//; + my @variables = split(/\;/, $variables); + # loop on variables + my $registerIndex = $startIndex; + for my $index (0 .. $#variables) { + $variables[$index] =~ s/word/s$registerIndex/; + $variables[$index] =~ s/uint8/s$registerIndex/; + $registerIndex = $registerIndex + 1; +#print " $variables[$index]\n"; + } + # assign registers to main program + + return ($registerIndex-1, join(';', @variables)); +} + +#------------------------------------------------------------------------------- +# Assign registers to all variables +# +sub assignRegisters { + my ($mainProgram, $firstRegister, %variables) = @_; + # loop on routines + my $registerMaxNb = 0; + foreach my $subroutine (keys(%variables)) { + # remove spaces + $variables{$subroutine} =~ s/\s*\:\s*/:/g; + $variables{$subroutine} =~ s/\s*\,\s*/,/g; + # distribute type definitions + my $type; + do { + $variables{$subroutine} =~ s/\,(.*?)\:(.*?)\;/:$2;$1:$2;/; + $type = $2; + } while ($type ne ''); + # assign registers to routine internal variables + if ($subroutine ne $mainProgram) { +#print "$subroutine:\n"; + my ($registerNb, $routineVariables) = assignRegistersToRoutine( + $firstRegister, + $variables{$subroutine} + ); + if ($registerNb > $registerMaxNb) { + $registerMaxNb = $registerNb; + } + $variables{$subroutine} = $routineVariables; +#print " $variables{$subroutine}\n"; + } + } + # assign registers to main program +#print "$mainProgram:\n"; + my ($registerNb, $routineVariables) = assignRegistersToRoutine( + $registerMaxNb + 1, + $variables{$mainProgram} + ); + $variables{$mainProgram} = $routineVariables; +#print " $variables{$mainProgram}\n"; + # build hash of hashes + foreach my $subroutine (keys(%variables)) { + my @registers = split(/\;/, $variables{$subroutine}); + my %assignedRegisters; + foreach my $variable (@registers) { + my ($var, $register) = split(/\:/, $variable); + $assignedRegisters{$var} = $register; + } + $variables{$subroutine} = \%assignedRegisters; + } + return (%variables); +} + +#------------------------------------------------------------------------------- +# Translate Pascal second operand to assembler source operand if possible +# +sub translateArgument { + my ($pascalOperand, $wordHexCharNb) = @_; + my $assemblerOperand = ''; + # register + if ($pascalOperand =~ m/\As(\d+)\Z/) { + $assemblerOperand = "s$1"; + } + # decimal numeric constant + elsif ($pascalOperand =~ m/\A(\d+)\Z/) { + $assemblerOperand = sprintf("%0${wordHexCharNb}X", $pascalOperand); + } + # hexadecimal numeric constant + elsif ($pascalOperand =~ m/\A\$([0-9A-Fa-f]+)\Z/) { + $assemblerOperand = sprintf("%0${wordHexCharNb}X", hex($1)); + } + # declared constant + else { + foreach my $routine (keys(%constants)) { + my $constants_ref = $constants{$routine}; + foreach my $constant (sort(keys(%$constants_ref))) { + if ($pascalOperand eq $constant) { + $assemblerOperand = $pascalOperand; + } + } + } + } + + return ($assemblerOperand); +} + +#------------------------------------------------------------------------------- +# Format assignment in ters of space characters +# +sub formatAssignment { + my ($assignment) = @_; + # unary operators + $assignment =~ s/\A\s*\-\s*/0 - /g; + # arithmetic operations + $assignment =~ s/\s*\+\s*/ + /g; + $assignment =~ s/\s*\-\s*/ - /g; + $assignment =~ s/\s*\*\s*/ * /g; + $assignment =~ s/\s*\/\s*/ \/ /g; + # logic operations + $assignment =~ s/\s+and\s+/ and /ig; + $assignment =~ s/\s+or\s+/ or /ig; + $assignment =~ s/\s+xor\s+/ xor /ig; + $assignment =~ s/\s+shl\s+/ shl /ig; + $assignment =~ s/\s+shr\s+/ shr /ig; + # parenthesis + $assignment =~ s/\(\s+/(/g; + $assignment =~ s/\s+\)/)/g; + $assignment =~ s/\s*\[\s+/[/g; + $assignment =~ s/\s+\]/]/g; + + return ($assignment); +} + +#------------------------------------------------------------------------------- +# Extract first argument of an assignment +# +sub extractFirsrtArgument { + my ($assignment) = @_; + my $operator = ''; + my $restOfAssignment = ''; + # starts with parenthesis + if ($assignment =~ m/\A\(/) { + my $index = 0; + my $level = 0; + my @characters = split(//, $assignment); + foreach my $character (@characters) { + if ($character eq '(') {$level = $level+1}; + if ($character eq '[') {$level = $level+1}; + if ($character eq ']') {$level = $level-1}; + if ($character eq ')') {$level = $level-1}; + if ($level == 0) { + last; + } + $index = $index+1; + } + $firstArgument = substr($assignment, 0, $index+1); + $restOfAssignment = substr($assignment, $index+1); + } + # to first whitespace + else { + my $index = 0; + my $level = 0; + my @characters = split(//, $assignment); + foreach my $character (@characters) { + if ($character eq '(') {$level = $level+1}; + if ($character eq '[') {$level = $level+1}; + if ($character eq ']') {$level = $level-1}; + if ($character eq ')') {$level = $level-1}; + if ( ($character eq ' ') and ($level == 0) ) { + last; + } + $index = $index+1; + } + $firstArgument = substr($assignment, 0, $index); + $restOfAssignment = substr($assignment, $index); + } + $restOfAssignment =~ s/\A //; +#print "|$firstArgument|$restOfAssignment|\n"; + # extract operator + if ($restOfAssignment ne '') { + ($operator, $restOfAssignment) = split(/ /, $restOfAssignment, 2); + } + + return ($firstArgument, $operator, $restOfAssignment); +} + +#------------------------------------------------------------------------------- +# Build expression out of argument and operator list +# +sub buildExpression { + my ($arguments_ref, $operators_ref) = @_; + my @arguments = @$arguments_ref; + my @operators = @$operators_ref; + # loop on list elements + my $expression = $arguments[0]; +#print "0: $expression\n"; + for my $index (1 .. $#arguments) { +#print "$index: $operators[$index] $arguments[$index]\n"; + $expression .= " $operators[$index] $arguments[$index]"; + } + return ($expression); +} + +#------------------------------------------------------------------------------- +# Expand operation to 2 lines +# +sub expandTwo { + my ($destinationRegister, $arguments_ref, $operators_ref) = @_; + my @arguments = @$arguments_ref; + my @operators = @$operators_ref; + my $line = ''; +#print " -> "; +#for my $index (0..scalar(@arguments)-1) { print "$operators[$index] $arguments[$index] ";} +#print "\n"; + # last argument is constant + my $lastArgument = $arguments[$#arguments]; + my $lastOperator = $operators[$#operators]; + my $isDeclaredConstant = 0; + foreach my $routine (keys(%constants)) { + my $constants_ref = $constants{$routine}; + foreach my $constant (sort(keys(%$constants_ref))) { + if ($lastArgument eq $constant) { + $isDeclaredConstant = 1; + } + } + } + if ( + ($lastArgument =~ m/\A\d+\Z/) or + ($lastArgument =~ m/\A\$[0-9A-Fa-f]+\Z/) or + ($isDeclaredConstant) + ) { + pop(@arguments); + pop(@operators); + my $firstArgument = buildExpression(\@arguments, \@operators); + if ($destinationRegister ne $firstArgument) { + $line = "$destinationRegister := $firstArgument;\n"; + } + $line .= "$destinationRegister := $destinationRegister $lastOperator $lastArgument;"; +#print "$line\n"; + } + # last argument is compund + elsif ($lastArgument =~ m/\A\((.+)\)\Z/) { + my $firstArgument = $1; + pop(@arguments); + pop(@operators); + $lastArgument = buildExpression(\@arguments, \@operators); + if ($firstArgument =~ m/ $destinationRegister /) { + $line = "$partialOperationRegister := $firstArgument;\n"; + $line .= "$destinationRegister := $destinationRegister $lastOperator $partialOperationRegister;"; + } + else { + $line = "$destinationRegister := $firstArgument;\n"; + $line .= "$destinationRegister := $destinationRegister $lastOperator $lastArgument;"; + } +#print "$line\n"; + } + + return ($line); +} + +#------------------------------------------------------------------------------- +# Expand assignment to multiple lines +# +sub expandAssignment { + my ($destinationRegister, $assignment) = @_; + # format assignment for treatment + $assignment = formatAssignment($assignment); + # default result + my $line = "$destinationRegister := $assignment;"; +#print "\n$line\n"; + # don't modify simple assignments and function calls + my $source = translateArgument($assignment, $wordHexCharNb); + my @arguments = (); + my @operators = (''); + if ( ($source eq '') and ($assignment !~ m/\Acall\s/) ){ + # analyse assignment +#print "\n $destinationRegister := $assignment\n"; + my $done = 0; + do { + my ($firstArgument, $operator, $restOfAssignment) = extractFirsrtArgument($assignment); +#print " $firstArgument $operator $restOfAssignment\n"; + if ($operator eq '') { + push(@arguments, $firstArgument); + $done = 1; + } + else { + push(@arguments, $firstArgument); + push(@operators, $operator); + $assignment = $restOfAssignment; + } + } until $done == 1; +#print " -> " . join(', ', @arguments) . "\n"; + # expand to 2 lines + my $newLine = expandTwo($destinationRegister, \@arguments, \@operators); + # modify code line + if ($newLine ne '') { + $line = $newLine; + } + } + + return ($line); +} + +################################################################################ +# Program start +# + +#------------------------------------------------------------------------------- +# Display information +# +if ($verbose > 0) { + print "$separator\n"; + print "Compiling $pascalFileSpec to $asmFileSpec\n"; +} + +# ============================================================================== +# Rewrite file for easier parsing +# +$currentPass = $currentPass + 1; +my $inputFileSpec = $pascalFileSpec; +my $outputFileSpec = $temp1FileSpec; +if ($verbose > 0) { + print "${indent}Pass $currentPass: placing line ends\n"; +} + # read input file +my $singleLine = ''; +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); +#print "$line\n"; + # remove leading and trailing spaces + $line =~ s/\A\s+//; + $line =~ s/\s+\Z//; + # remove single line comments + $line =~ s/\{.*?\}//g; + # write to single line string + if ($line ne '') { + $singleLine .= "$line "; + } +} +close(inputFile); + # remove extra spaces +$singleLine =~ s/\s+/ /g; +$singleLine =~ s/\s\Z//; + # split constructs into multiple lines +$singleLine =~ s/\s*;\s*/;\n/g; +$singleLine =~ s/\sconst\s/\nconst\n/g; +$singleLine =~ s/\svar\s/\nvar\n/g; +$singleLine =~ s/\sprocedure\s+/\nprocedure /g; +$singleLine =~ s/\sfunction\s+/\nfunction /g; +$singleLine =~ s/\sbegin\s/\nbegin\n/g; +$singleLine =~ s/\send\s*;\s/\nend;\n/g; +$singleLine =~ s/\selse\s/\nelse\n/g; +$singleLine =~ s/\srepeat\s/\nrepeat\n/g; +$singleLine =~ s/\sif\s/\nif /g; +$singleLine =~ s/\suntil\s/\nuntil /g; +$singleLine =~ s/\sfor\s/\nfor /g; +$singleLine =~ s/\swhile\s/\nwhile /g; +$singleLine =~ s/\sthen\s/ then\n/g; +$singleLine =~ s/\sdo\s/ do\n/g; + # take away new lines within parenthesis +my $parameters; +do { + $singleLine =~ s/\(([^\)]*?)\n([^\)]*?)\)/($1 $2)/m; + $parameters = $2; +#if ($parameters ne '') { print "--> $1 $parameters\n"; } +} while ($parameters ne ''); + # add begin/end to single-line blocks +my $singleLineBlock; +do { + $singleLine =~ s/\nif (.*?) then\n(?!begin)(.*?)\;/\nif $1 then\nbegin\n$2;\nend;/; + $singleLineBlock = $2; +#print "if $1 then begin $2; end;\n"; +} while ($singleLineBlock ne ''); +do { + $singleLine =~ s/\nfor (.*?) do\n(?!begin)(.*?)\;/\nfor $1 do\nbegin\n$2;\nend;/; + $singleLineBlock = $2; +} while ($singleLineBlock ne ''); + + # remove comments, part 1 +$singleLine =~ s/\s*\{\s*/\n{/g; +$singleLine =~ s/\s*\}\s*/}\n/g; + # write to output file +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; +print(outputFile "$singleLine\n"); +close(outputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + +# ============================================================================== +# Finish removing comments +# +$currentPass = $currentPass + 1; +($inputFileSpec, $outputFileSpec) = swapTempFileSpecs( + $inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec +); +if ($verbose > 0) { + print "${indent}Pass $currentPass: removing comments\n"; +} + # read input file +my $commentOut = 0; +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); + # remove comments, part 2 + if ($line =~ m/\{/) { $commentOut = 1; } + if ( ($commentOut == 0) and ($line ne '') ) { + print(outputFile "$line\n"); + } + if ($line =~ m/\}/) { $commentOut = 0; } +} +close(outputFile); +close(inputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + +# ============================================================================== +# Get constants and variables, indent code +# +$currentPass = $currentPass + 1; +($inputFileSpec, $outputFileSpec) = swapTempFileSpecs( + $inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec +); +if ($verbose > 0) { + print "${indent}Pass $currentPass: finding constants and variables\n"; +} +my $currentLevel = 0; +my $currentRoutine; +my $startOfProgramDeclatation = ''; +my $isStartOfProgramDeclatation = 1; +my $isConstantsDeclatation = 0; +my $isVariablesDeclatation = 0; +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); +#print "$line\n"; + # find program name + if ($line =~ m/\A\s*program\s+(.*)\s*;/i) { + $mainProgram = $1; +#print "Program name is |$mainProgram|\n"; + $currentRoutine = $mainProgram; + @routines = ($currentRoutine); + } + # find current function name + if ($line =~ m/\A(procedure|function)(\s|\Z)/i) { + $currentRoutine = $line; + $currentRoutine =~ s/\Aprocedure//i; + $currentRoutine =~ s/\Afunction//i; + $currentRoutine =~ s/\A\s+//; + $currentRoutine =~ s/;.*//; + $currentRoutine =~ s/\s*:.*//; + $currentRoutine =~ s/\(.*//; + push(@routines, $currentRoutine); + print(outputFile "\n"); +#print "$currentRoutine\n"; + $isStartOfProgramDeclatation = 0; + $isVariablesDeclatation = 0; + $isConstantsDeclatation = 0; + } + # find begin/end level + if ($line eq 'begin') { + $currentLevel = $currentLevel + 1; +#print "-> $currentLevel\n"; + if ( ($currentLevel == 1) and ($currentRoutine eq $mainProgram) ) { +#print "$currentRoutine\n"; + $isStartOfProgramDeclatation = 0; + print(outputFile "\n$startOfProgramDeclatation"); + } + $isVariablesDeclatation = 0; + $isConstantsDeclatation = 0; + } + if ($line eq 'end;') { + $currentLevel = $currentLevel - 1; +#print "-> $currentLevel\n"; + if ($currentLevel == 0) { + $currentRoutine = $mainProgram; + } + } + # find constants + if ($isConstantsDeclatation) { + if ($line ne 'var') { +#print "-> $line\n"; + $constants{$currentRoutine} .= $line; + } + } + if ($line eq 'const') { + $isConstantsDeclatation = 1; + $isVariablesDeclatation = 0; + } + # find variables + if ($isVariablesDeclatation) { +#print "-> $line\n"; + $variables{$currentRoutine} .= $line; + } + if ($line eq 'var') { + $isVariablesDeclatation = 1; + $isConstantsDeclatation = 0; + } + # determine indent level + my $indentLevel = $currentLevel; + if ($line eq 'begin') { $indentLevel = $indentLevel - 1; } + if ($isConstantsDeclatation) { $indentLevel = $indentLevel + 2; } + if ($isVariablesDeclatation) { $indentLevel = $indentLevel + 2; } + if ($line eq 'const') { $indentLevel = $indentLevel - 1; } + if ($line eq 'var') { $indentLevel = $indentLevel - 1; } + if ($line eq 'end.') { $indentLevel = $indentLevel - 1; } + # write to output file + my $indentedLine = ($indent x $indentLevel) . $line; + $indentedLine = sprintf('%2d: ', $indentLevel) . $indentedLine; + if ($isStartOfProgramDeclatation == 0) { + print(outputFile "$indentedLine\n"); + } else { + $startOfProgramDeclatation .= "$indentedLine\n"; + } +} +close(outputFile); +close(inputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + +# ------------------------------------------------------------------------------ +# Process constant declarations +# +%constants = buildConstants($mainProgram, %constants); + +# ------------------------------------------------------------------------------ +# Assign registers to variables +# +if ($verbose > 0) { + print $indent x 2 . "Writing registers assignments in \"$registersFileSpec\"\n"; +} +%variables = assignRegisters($mainProgram, $firstRegister, %variables); +open(registersFile, ">$registersFileSpec") or die "Unable to open file, $!"; +foreach my $subroutine (keys(%variables)) { + print(registersFile "$subroutine\n"); + my $registers_ref = $variables{$subroutine}; + my %registers = reverse(%$registers_ref); + foreach my $register (sort(keys(%registers))) { + print(registersFile "${indent}$register:$registers{$register}\n"); + } +} +close(registersFile); + +# ============================================================================== +# Process constants and variables and functions +# +$currentPass = $currentPass + 1; +($inputFileSpec, $outputFileSpec) = swapTempFileSpecs( + $inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec +); +if ($verbose > 0) { + print "${indent}Pass $currentPass: replacing constants and variables\n"; +} + # build main program variables hash +my $variables_ref = $variables{$mainProgram}; +%mainProgramVariables = %$variables_ref; + # loop on program code +my $currentRoutine; +my %localVariables; +my $printLine = 1; +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; + # write constants at beginning of file +foreach my $routine (keys(%constants)) { + my $replacement_ref = $constants{$routine}; + foreach my $constant (sort(keys(%$replacement_ref))) { + print(outputFile "const $constant = $$replacement_ref{$constant};\n"); + } +} +while(my $line = ) { + chomp($line); +#print "$line\n"; + # strip line nb and leading spaces + my $strippedLine = $line; + $strippedLine =~ s/\A\s*\d*\:*\s*//; +#print "$strippedLine\n"; + # find current function name + if ( + ($strippedLine =~ m/\Aprocedure /i) or + ($strippedLine =~ m/\Afunction /i) or + ($strippedLine =~ m/\Aprogram /i) + ) { + $currentRoutine = $strippedLine; + $currentRoutine =~ s/\A\S+\s+//; + $currentRoutine =~ s/\(.*//; + $currentRoutine =~ s/\;//; +#print "$currentRoutine\n"; + # build current variables hash + my $variables_ref = $variables{$currentRoutine}; + %localVariables = %$variables_ref; + } + # cut out constant and variable declarations of the program + if ($strippedLine =~ m/\Aconst\Z/) { + $printLine = 0; + } + if ($strippedLine =~ m/\Avar\Z/) { + $printLine = 0; + } + if ($strippedLine eq 'begin') { + $printLine = 1; + } + # replace variables + foreach my $variable (keys(%localVariables)) { + $line =~ s/$variable/$localVariables{$variable}/g; + } + foreach my $variable (keys(%mainProgramVariables)) { + $line =~ s/$variable/$mainProgramVariables{$variable}/g; + } + # write output + if ($printLine) { + print(outputFile "$line\n"); + } +} +close(outputFile); +close(inputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + +# ============================================================================== +# Label subroutines and loops +# +$currentPass = $currentPass + 1; +($inputFileSpec, $outputFileSpec) = swapTempFileSpecs( + $inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec +); +if ($verbose > 0) { + print "${indent}Pass $currentPass: labelling subroutines and loops\n"; +} + # loop on program code +my $previousWasElse = 0; +my $labelcount = 0; +my $blockKind; +my @labels; +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); +#print "$line\n"; + # get current level + my $currentLevel = $line; + $currentLevel =~ s/\A\s*(\d*)\:.*/$1/; + # strip level depth and leading spaces + $line =~ s/\A\s*\d*\:\s*//; +#print "$line\n"; + # remove "begin" statements + $line =~ s/\Abegin\Z//; + # assign labels to block statements + if ($line =~ m/\Aif /) { + if (not $previousWasElse) { + $labelcount = $labelcount + 1; + $labels[$currentLevel] = sprintf('if%02d', $labelcount); + } + $line = $labels[$currentLevel] . ': ' . $line; + } + if ($line =~ m/\Afor /) { + $labelcount = $labelcount + 1; + $labels[$currentLevel] = sprintf('for%02d', $labelcount); + $line = $labels[$currentLevel] . ': ' . $line; + } + if ($line =~ m/\Awhile /) { + $labelcount = $labelcount + 1; + $labels[$currentLevel] = sprintf('while%02d', $labelcount); + $line = $labels[$currentLevel] . ': ' . $line; + } + # assign labels to end of block statements + if ($line =~ m/\Aend\s*[;\.]/) { + if ($currentLevel == 0) { + $line = 'return;'; + } else { + $line = 'end ' . $labels[$currentLevel] . ';'; + } + } + # specify procedure calls + for my $routine (@routines) { + $line =~ s/$routine\s*\:\=\s*/$functionReturnRegister := /g; + $line =~ s/$routine([ \(\;])/call $routine$1/g; + } + $line =~ s/\A(program|procedure|function) call /$1 /g; + # store "previous line was else" + $previousWasElse = 0; + if ($line =~ m/\Aelse\Z/) { + $previousWasElse = 1; + } + # write output + if ($line ne '') { + if ($line =~ m/(program|procedure|function) /) { + print(outputFile "\n"); + } + my $indentedLine = ($indent x $currentLevel) . $line; + $indentedLine = sprintf('%2d: ', $currentLevel) . $indentedLine; + print(outputFile "$indentedLine\n"); + } +} +close(outputFile); +close(inputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + +# ============================================================================== +# Break compound operations +# +$currentPass = $currentPass + 1; +($inputFileSpec, $outputFileSpec) = swapTempFileSpecs( + $inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec +); +if ($verbose > 0) { + print "${indent}Pass $currentPass: breaking compound operations\n"; +} + # loop on program code +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); +#print "$line\n"; + # get current level + my $currentLevel = $line; + $currentLevel =~ s/\A\s*(\d*)\:.*/$1/; + # strip level depth and leading spaces + $line =~ s/\A\s*\d*\:\s*//; +#print "$line\n"; + # check assignments + if ($line =~ m/s(\d+)\s*\:\=\s*(.+)\s*\;/) { + my $destinationRegister = "s$1"; + my $assignment = $2; + $line = expandAssignment($destinationRegister, $assignment); + } + # write output + if ($line ne '') { + my $indentedLine = ($indent x $currentLevel) . $line; + $indentedLine = sprintf('%2d: ', $currentLevel) . $indentedLine; + print(outputFile "$indentedLine\n"); + } +} +close(outputFile); +close(inputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + + +# ============================================================================== +# Assembler file: constants, subroutines, memory access +# +$currentPass = $currentPass + 1; +($inputFileSpec, $outputFileSpec) = swapTempFileSpecs( + $inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec +); +if ($verbose > 0) { + print "${indent}Pass $currentPass: writing assembler for constants, subroutines, mem and nop\n"; +} +foreach my $routine (keys(%constants)) { + my $constants_ref = $constants{$routine}; + foreach my $constant (sort(keys(%$constants_ref))) { + my $length = length($constant); + if ($length > $constantMaxLength) { $constantMaxLength = $length; } + } +} + # assembler code header +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; +print(outputFile "$separator1\n"); +print(outputFile "$commentStart $mainProgram\n"); +print(outputFile "$separator1\n"); +print(outputFile "\n"); + # loop on program code +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); +#print "$line\n"; + # strip level depth and leading spaces + $line =~ s/\A\s*\d*\:\s*//; +#print "$line\n"; + # replace constants + if ($line =~ m/\Aconst (.*?)\s*\=\s*\$(.*?)\;/) { + my $constantName = fillString("$1,", ' ', $constantMaxLength+1); + my $constantValue = sprintf("%0${wordHexCharNb}X", hex($2)); + $line = "$asmFirstIndent CONSTANT $constantName $constantValue"; + } + # replace subroutines start + if ($line =~ m/\A(program|procedure|function) (.*?)\s*[\;\(]/) { + my $routineKind = $1; + my $routineName = $2; + print(outputFile "\n"); + print(outputFile "$separator2\n"); + print(outputFile "$commentStart $routineKind $routineName\n"); + print(outputFile "$separator2\n"); + print(outputFile ' ' x (length($asmFirstIndent) - length($routineName) - 2) . "$routineName: NOP\n"); + $line = ''; + } + # replace subroutines return + $line =~ s/\Areturn\;/${asmFirstIndent}RETURN/; + # replace subroutine calls with arguments + if ($line =~ m/call (.*?)\s*\((.*?)\s*\)\s*\;/) { + my $routineName = $1; + my $routineArguments = $2; + $routineArguments =~ s/var //g; + $routineArguments =~ s/\;/,/g; + $argumentText = 'argument'; + if($routineArguments =~ m/\,/) { + $argumentText .= 's'; + } + print( + outputFile + "$asmFirstIndent" + . fillString('CALL', ' ', $opcodeLength) + . "$routineName ; $argumentText: $routineArguments\n" + ); + if ($line =~ m/\A(.*?)\s*\:\=\s* call/) { + $returnRegister = $1; + $line = "$returnRegister := s0;\n"; + } else { + $line = ''; + } + } + # replace subroutine calls without arguments + if ($line =~ m/\Acall (.*?)\;/) { + $line = $asmFirstIndent . fillString('CALL', ' ', $opcodeLength) . $1; + } + # memory write + if ($line =~ m/mem\[(.+?)\]\s*\:\=\s*(.+)\s*\;/) { + my $opcode = fillString('OUTPUT', ' ', $opcodeLength); + $line = "$memoryAccessRegister := $1;"; + $line .= "\n${asmFirstIndent}${opcode}$2, ($memoryAccessRegister)"; + } + # memory read + if ($line =~ m/\s*(.+)\s*\:\=\s*mem\[(.+?)\]\s*\;/) { + my $opcode = fillString('INPUT', ' ', $opcodeLength); + $line = "$memoryAccessRegister := $2;"; + $line .= "\n${asmFirstIndent}${opcode}$memoryAccessRegister, ($memoryAccessRegister)" x 2; + $line .= "\n$1 := $memoryAccessRegister;"; + } + # NOP + if ($line =~ m/\s*noOperation\s*\;/) { + $line = "${asmFirstIndent}NOP"; + } + # write output + if ($line ne '') { + print(outputFile "$line\n"); + } +} +close(outputFile); +close(inputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + +# ============================================================================== +# Assembler file: register transfers +# +$currentPass = $currentPass + 1; +($inputFileSpec, $outputFileSpec) = swapTempFileSpecs( + $inputFileSpec, $outputFileSpec, $temp1FileSpec, $temp2FileSpec +); +if ($verbose > 0) { + print "${indent}Pass $currentPass: writing assembler for load, add, and sub\n"; +} + # loop on program code +open(inputFile, "<$inputFileSpec") or die "Unable to open file, $!"; +open(outputFile, ">$outputFileSpec") or die "Unable to open file, $!"; +while(my $line = ) { + chomp($line); +#print "$line\n"; + # LOAD + if ($line =~ m/s(\d+)\s*\:\=\s*(.+)\s*\;/) { + my $destinationRegister = fillString("s$1,", ' ', $firstArgumentLength); + my $source = translateArgument($2, $wordHexCharNb); + my $opcode = fillString('LOAD', ' ', $opcodeLength); + if ($source ne '') { + $line = "${asmFirstIndent}${opcode}${destinationRegister}$source"; + } + } + # ADD + if ($line =~ m/s(\d+)\s*\:\=\s*s(\d+)\s*\+\s*(.+)\s*\;/) { + if ($1 eq $2) { + my $destinationRegister = fillString("s$1,", ' ', $firstArgumentLength); + my $source = translateArgument($3, $wordHexCharNb); + my $opcode = fillString('ADD', ' ', $opcodeLength); + if ($source ne '') { + $line = "${asmFirstIndent}${opcode}${destinationRegister}$source"; + } + } + } + # SUB + if ($line =~ m/s(\d+)\s*\:\=\s*s(\d+)\s*\-\s*(.+)\s*\;/) { + if ($1 eq $2) { + my $destinationRegister = fillString("s$1,", ' ', $firstArgumentLength); + my $source = translateArgument($3, $wordHexCharNb); + my $opcode = fillString('SUB', ' ', $opcodeLength); + if ($source ne '') { + $line = "${asmFirstIndent}${opcode}${destinationRegister}$source"; + } + } + } + # AND + if ($line =~ m/s(\d+)\s*\:\=\s*s(\d+)\s*and\s*(.+)\s*\;/i) { + if ($1 eq $2) { + my $destinationRegister = fillString("s$1,", ' ', $firstArgumentLength); + my $source = translateArgument($3, $wordHexCharNb); + my $opcode = fillString('AND', ' ', $opcodeLength); + if ($source ne '') { + $line = "${asmFirstIndent}${opcode}${destinationRegister}$source"; + } + } + } + # OR + if ($line =~ m/s(\d+)\s*\:\=\s*s(\d+)\s*or\s*(.+)\s*\;/i) { + if ($1 eq $2) { + my $destinationRegister = fillString("s$1,", ' ', $firstArgumentLength); + my $source = translateArgument($3, $wordHexCharNb); + my $opcode = fillString('OR', ' ', $opcodeLength); + if ($source ne '') { + $line = "${asmFirstIndent}${opcode}${destinationRegister}$source"; + } + } + } + # write output + if ($line ne '') { + print(outputFile "$line\n"); + } +} +close(outputFile); +close(inputFile); + # keep intermediate file +if ($keepIntermediateFiles) { + my $textfile = "$baseFileSpec$currentPass.txt"; + use File::Copy; + unlink($textfile); + copy($outputFileSpec, $textfile) or die "File cannot be copied."; +} + +################################################################################ +# Documentation (access it with: perldoc ) +# +__END__ + +=head1 NAME + +nanoPascal.pl - Transforms a Pascal program into assembler code + +=head1 SYNOPSIS + +nanoPascal.pl [options] + +=head1 DESCRIPTION + +This is a simple parser which translates Pascal expressions into their assembler +code equivalents for the nanoBlaze processor. +The process doesn't optimize the code. +The expressions which couldn't be translated into assembler are left as Pascal +for the user to translate manually. + +=head1 OPTIONS + +=over 8 + +=item B<-h> + +Display a help message. + +=item B<-v> + +Be verbose. + +=item B<-k> + +Makes a copy of the intermediate files between the passes. + +=item B<-c> + +Cleans the temporary work files at the end of the process. + +Specify a username in the bridge's whitelist. + +=back + +=head1 Limitations + +There is currently no Pascal syntax error detection. + +The script doesn't distinguish between constants having the same name within +different procedures or functions. +This can be corrected in future versions. + +Procedure and function calls basically don't support passing parameters. +This would require a stack mechanism. +The only possible way to pass parameters is to declare global variables +and use these as parameters for the procedure and function calls. + +The Pascal C construct is either followed by a C +block or a single expression. +The script only handles single-line expressions. +Other more complex expressions (like a nested c need a +C structure. + +=head1 AUTHOR + +Francois Corthay, HEVs + +=head1 VERSION + +1.1, 2014 + +=cut diff --git a/Libs/NanoBlaze/hdl/nanoTest.asm b/Libs/NanoBlaze/hdl/nanoTest.asm new file mode 100644 index 0000000..2e9784b --- /dev/null +++ b/Libs/NanoBlaze/hdl/nanoTest.asm @@ -0,0 +1,342 @@ + ;=============================================================== + ; nanoTest.asm + ; Used for checking the NanoBlaze instruction set + ;=============================================================== + ; 1) Test logical operations with direct values + ;--------------------------------------------------------------- + LOAD s7, 01 + CONSTANT testPattern, 0F + ;--------------------------------------------------------------- + ; Test "LOAD", "AND" + ;--------------------------------------------------------------- + LOAD s0, testPattern + AND s0, 33 + COMPARE s0, 03 + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "OR" + ;--------------------------------------------------------------- + LOAD s1, testPattern + OR s1, 33 + COMPARE s1, 3F + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "XOR" + ;--------------------------------------------------------------- + LOAD s2, testPattern + XOR s2, 33 + COMPARE s2, 3C + JUMP NZ, error + ;=============================================================== + ; 2) Test logical operations with registers + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test "LOAD" + ;--------------------------------------------------------------- + LOAD s0, 33 + LOAD s3, s0 + COMPARE s3, 33 + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "AND" + ;--------------------------------------------------------------- + LOAD s0, 0F + AND s0, s3 + COMPARE s0, 03 + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "OR" + ;--------------------------------------------------------------- + LOAD s1, 0F + OR s1, s3 + COMPARE s1, 3F + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "XOR" + ;--------------------------------------------------------------- + LOAD s2, 0F + XOR s2, s3 + COMPARE s2, 3C + JUMP NZ, error + ;=============================================================== + ; 3) Test arithmetic operations with constants + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test "ADD" and "ADDCY" + ;--------------------------------------------------------------- + LOAD s0, 0F + ADD s0, 31 ; 40 + ADDCY s0, F0 ; 130 + ADDCY s0, F0 ; 121 + ADD s0, 0F ; 30 + COMPARE s0, 30 + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "SUB" and "SUBCY" + ;--------------------------------------------------------------- + LOAD s1, 0F + SUB s1, 0C ; 03 + SUBCY s1, F0 ; 113 + SUBCY s1, F0 ; 22 + SUB s1, 01 ; 21 + COMPARE s1, 21 + JUMP NZ, error + ;=============================================================== + ; 4) Test arithmetic operations with registers + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test "ADD" and "ADDCY" + ;--------------------------------------------------------------- + LOAD s0, 0F + LOAD s1, 31 + LOAD s2, F0 + LOAD s3, 0F + ADD s0, s1 ; 40 + ADDCY s0, s2 ; 130 + ADDCY s0, s2 ; 121 + ADD s0, s3 ; 30 + COMPARE s0, 30 + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "SUB" and "SUBCY" + ;--------------------------------------------------------------- + LOAD s1, 0F + LOAD s0, 0C + LOAD s2, F0 + LOAD s3, 01 + SUB s1, s0 ; 03 + SUBCY s1, s2 ; 113 + SUBCY s1, s2 ; 22 + SUB s1, s3 ; 21 + COMPARE s1, 21 + JUMP NZ, error + ;=============================================================== + ; 5) Test shifts + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test shift right + ;--------------------------------------------------------------- + LOAD s0, 0F ; 0F + SR0 s0 ; 07 + SRX s0 ; 03 + SR1 s0 ; 81 + SRX s0 ; C0, C=1 + SRA s0 ; E0, C=0 + SRA s0 ; 70 + COMPARE s0, 70 + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test shift left + ;--------------------------------------------------------------- + LOAD s1, F0 ; FO + SL0 s1 ; E0 + SLX s1 ; C0 + SL1 s1 ; 81 + SLX s1 ; 03, C=1 + SLA s1 ; 07, C=0 + SLA s1 ; 0E + COMPARE s1, 0E + JUMP NZ, error + ;=============================================================== + ; 6) Test comparison operators + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test "COMPARE" + ;--------------------------------------------------------------- + LOAD s0, 0F + COMPARE s0, F0 ; A < B => C=1 + JUMP NC, error + COMPARE s0, F0 ; A < B => Z=0 + JUMP Z, error + COMPARE s0, s0 ; A = B => Z=1 + JUMP NZ, error + COMPARE s0, 08 ; A > B => C=0 + JUMP C, error + COMPARE s0, 08 ; A > B => Z=0 + JUMP Z, error + ;--------------------------------------------------------------- + ; Test "TEST" + ;--------------------------------------------------------------- + LOAD s0, 0F + TEST s0, F0 ; AND is 00 => Z=1 + JUMP NZ, error + TEST s0, FF ; AND is 0F => Z=0 + JUMP Z, error + ;=============================================================== + ; 7) Test INPUT and OUTPUT operators + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test "INPUT" and "OUTPUT" direct + ; + ; The testbench should invert the word written at address FC. + ;--------------------------------------------------------------- + LOAD s0, AA + OUTPUT s0, FC + INPUT s1, FC + COMPARE s1, 55 + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "INPUT" and "OUTPUT" indexed + ;--------------------------------------------------------------- + LOAD s0, CC + LOAD s2, FC + OUTPUT s0, (s2) + INPUT s1, (s2) + COMPARE s1, 33 + JUMP NZ, error + ;=============================================================== + ; 8) Test STORE and FETCH operators + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test "STORE" and "FETCH" direct + ;--------------------------------------------------------------- + LOAD s0, 0F + STORE s0, 03 + FETCH s1, 03 + COMPARE s1, 0F + JUMP NZ, error + ;--------------------------------------------------------------- + ; Test "STORE" and "FETCH" indexed + ;--------------------------------------------------------------- + LOAD s0, F0 + LOAD s2, 04 + STORE s0, (s2) + FETCH s1, (s2) + COMPARE s1, F0 + JUMP NZ, error + ;=============================================================== + ; 9) Test JUMP instructions + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; Test "JUMP NC" + ;--------------------------------------------------------------- + LOAD s0, F0 + ADD s0, 00 ; s0=F0, C=0, Z=0 + JUMP NC, continue1 + JUMP error + ;--------------------------------------------------------------- + ; Test "JUMP NZ" + ;--------------------------------------------------------------- + continue1: ADD s0, 00 ; s0=F0, C=0, Z=0 + JUMP NZ, continue2 + JUMP error + ;--------------------------------------------------------------- + ; Test "JUMP C" + ;--------------------------------------------------------------- + continue2: ADD s0, F0 ; s0=E0, C=1, Z=0 + JUMP C, continue3 + JUMP error + ;--------------------------------------------------------------- + ; Test "JUMP Z" + ;--------------------------------------------------------------- + continue3: SUB s0, E0 ; s0=00, C=0, Z=1 + JUMP Z, continue4 + JUMP error + continue4: NOP + ;=============================================================== + ; 10) Test call instructions + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; define subroutine + ;--------------------------------------------------------------- + JUMP continue5 + subRetDo: ADD s0, 01 + RETURN + JUMP error + ;--------------------------------------------------------------- + ; Test "CALL" + ;--------------------------------------------------------------- + continue5: LOAD s0, 00 + LOAD s1, F0 + CALL subRetDo ; s0=01 + ;--------------------------------------------------------------- + ; Test "CALL NC" + ;--------------------------------------------------------------- + ADD s1, 00 ; s1=F0, C=0, Z=0 + CALL NC, subRetDo ; s0=02 + ;--------------------------------------------------------------- + ; Test "CALL NZ" + ;--------------------------------------------------------------- + ADD s1, 00 ; s1=F0, C=0, Z=0 + CALL NZ, subRetDo ; s0=03 + ;--------------------------------------------------------------- + ; Test "CALL C" + ;--------------------------------------------------------------- + ADD s1, F0 ; s0=E0, C=1, Z=0 + CALL C, subRetDo ; s0=04 + ;--------------------------------------------------------------- + ; Test "CALL Z" + ;--------------------------------------------------------------- + SUB s1, E0 ; s0=00, C=0, Z=1 + CALL Z, subRetDo ; s0=05 + COMPARE s0, 05 + jump nz, error + ;=============================================================== + ; 11) Test call return instructions + ;--------------------------------------------------------------- + ADD s7, 01 + ;--------------------------------------------------------------- + ; define subroutines + ;--------------------------------------------------------------- + JUMP continue6 + subRetNC: ADD s0, 01 + RETURN NC + JUMP error + subRetNZ: ADD s0, 01 + RETURN NZ + JUMP error + subRetC: ADD s0, 01 + RETURN C + JUMP error + subRetZ: ADD s0, 01 + RETURN Z + JUMP error + ;--------------------------------------------------------------- + ; Test "RETURN NC" + ;--------------------------------------------------------------- + continue6: LOAD s0, 00 ; increment will give C=0, Z=0 + CALL NC, subRetNC + ;--------------------------------------------------------------- + ; Test "RETURN NZ" + ;--------------------------------------------------------------- + LOAD s0, 00 ; increment will give C=0, Z=0 + CALL NZ, subRetNZ + ;--------------------------------------------------------------- + ; Test "RETURN C" + ;--------------------------------------------------------------- + LOAD s0, FF ; increment will give C=1, Z=1 + CALL C, subRetC + ;--------------------------------------------------------------- + ; Test "RETURN Z" + ;--------------------------------------------------------------- + LOAD s0, FF ; increment will give C=1, Z=1 + CALL Z, subRetZ + ;=============================================================== + ; End of tests + ; + ; The testbench should react if value 1 is written to address 00. + ;--------------------------------------------------------------- + LOAD s0, 01 + OUTPUT s0, 00 + JUMP endOfMemory + ;=============================================================== + ; Assert error + ; + ; The testbench should react if value 0 is written to address 00. + ;--------------------------------------------------------------- +ADDRESS 3FD + error: LOAD s0, 00 + OUTPUT s0, 00 + ;=============================================================== + ; End of instruction memory + ;--------------------------------------------------------------- + endOfMemory: JUMP endOfMemory diff --git a/Libs/NanoBlaze/hdl/nanoTest.pas b/Libs/NanoBlaze/hdl/nanoTest.pas new file mode 100644 index 0000000..eb6592e --- /dev/null +++ b/Libs/NanoBlaze/hdl/nanoTest.pas @@ -0,0 +1,368 @@ +{ + beamer.pas + + The beamer controller polls the UART to get commands and provides the + corresponding replies. +} + +program BeamerControl; + +{==============================================================================} +{ Constants } +{==============================================================================} + const + clockFrequency = 66E6; + gpioBaseAddress = $0000; + gpioDataOffset = $0000; + gpioEnableOffset = $0001; + uartBaseAddress = $0010; + uartBaudOffset = $0002; + uartStatusOffset = $0001; + uartDataReady = $0001; + uartSending = $0002; + uartBaudRate = 1E6; + uartBaudCount = clockFrequency / uartBaudRate; + uartPollDelay = uartBaudCount / 2; + uartTimeout = 10; + commandHeader = $AA; + commandNack = $00; + commandWriteMem = $03; + commandReadMem = $04; + commandWriteLength = 4; + commandReadLength = 2; + beamerBaseAddress = $0020; + beamerCtlOffset = $0000; + beamerSpeedOffset = $0001; + beamerCtlInit = $0401; + beamerSpeedInit = $0004; + commStIdle = $0000; + commStGetPacketId = $0001; + commStGetCommandId = $0002; + commStGetDataLength = $0003; + commStGetData = $0004; + commStGetChecksum = $0005; + commStExecuteCommand = $0006; + commStSendHeader = $0007; + commStSendPacketId = $0008; + commStSendCommandId = $0009; + commStSendDataLength = $000A; + commStSendData = $000B; + commStSendChecksum = $000C; + +{==============================================================================} +{ Variables } +{==============================================================================} + var + communicationState : word; + uartByte: uint8; + +{==============================================================================} +{ Procedures and functions } +{==============================================================================} + + {============================================================================} + { Register-level functions } + {============================================================================} + + {----------------------------------------------------------------------------} + { Registers initializations } + {----------------------------------------------------------------------------} + procedure initRegisters; + const + gpioValue = $AA; + gpioEnablemask = $0F; + begin + { initialize GPIO } + mem[gpioBaseAddress+gpioDataOffset] := gpioValue; + mem[gpioBaseAddress+gpioEnableOffset] := gpioEnablemask; + { initialize UART } + mem[uartBaseAddress+uartBaudOffset] := uartBaudCount; + { initialize beamer peripheral } + mem[beamerBaseAddress+beamerCtlOffset] := beamerCtlInit; + mem[beamerBaseAddress+beamerSpeedOffset] := beamerSpeedInit; + end; + + {----------------------------------------------------------------------------} + { Get byte from serial port with timeout } + {----------------------------------------------------------------------------} + function getSerialPortByte(var uartByte: uint8) : word; + var + dataReady: uint8; + pollCount: word; + begin + { poll until data byte available or timeout occured} + pollCount := uartPollDelay; + dataReady := 0; + while dataReady = 0 do + begin + { read status register } + dataReady := mem[uartBaseAddress+uartStatusOffset] and uartDataReady; + { spend time in order not to overcharge the AHB bus } + if dataReady = 0 then + begin + { check for timeout } + pollCount := pollCount -1; + if pollCount = 0 then + dataReady := $FF; + { spend time in order not to overcharge the system bus } + for index := 1 to uartPollDelay do + noOperation; + end; + end; + { function return } + if dataReady = $FF then + { return timeout } + getSerialPortByte := 1; + else + { read data register and return it } + begin + uartByte := mem[uartBaseAddress]; + getSerialPortByte := 0; + end; + end; + + {----------------------------------------------------------------------------} + { Send byte to serial port with timeout } + {----------------------------------------------------------------------------} + function sendSerialPort(var uartByte : uint8) : word; + var + dataReady: uint8; + statusByte: uint8; + pollCount: word; + begin + { poll until ready to send } + pollCount := uartPollDelay; + statusByte := mem[uartBaseAddress+uartStatusOffset] and uartSending; + while statusByte = 0 do + begin + { check for timeout } + pollCount := pollCount -1; + if pollCount = 0 then + dataReady := $FF; + { spend time in order not to overcharge the system bus } + for index := 1 to uartPollDelay do + noOperation; + { read status register } + statusByte := mem[uartBaseAddress+uartStatusOffset] and uartSending; + end; + { function return } + if dataReady = $FF then + { return timeout } + sendSerialPort := 1; + else + { write data register and return it } + begin + mem[uartBaseAddress] := uartByte; + sendSerialPort := 0; + end; + end; + + {============================================================================} + { Communication state machine } + {============================================================================} + procedure updateStateMachine( + var communicationState : word; + var uartByte: uint8 + ); + var + communicationNextState : word; + uartStatus: word; + packetId, commandId : uint8; + checksum : uint8; + dataLength, dataCount, data1, data2, data3, data4 : uint8; + memAddress, memData : word; + begin + { idle } + if communicationState = commStIdle then + begin + uartStatus := getSerialPortByte(var uartByte: uint8); + if (uartStatus = 0) and (uartByte = commandHeader) then + begin + checksum := uartByte; + communicationNextState := commStGetPacketId; + end; + end; + { get packet id } + else if communicationState = commStGetPacketId then + begin + uartStatus := getSerialPortByte(var uartByte: uint8); + if uartStatus = 0 then + begin + packetId := uartByte; + checksum := checksum + uartByte; + communicationNextState := commStGetCommandId; + end; + end; + { get command id } + else if communicationState = commStGetCommandId then + begin + uartStatus := getSerialPortByte(var uartByte: uint8); + if uartStatus = 0 then + begin + commandId := uartByte; + checksum := checksum + uartByte; + communicationNextState := commStGetDataLength; + end; + end; + { get data length } + else if communicationState = commStGetDataLength then + begin + uartStatus := getSerialPortByte(var uartByte: uint8); + if uartStatus = 0 then + begin + dataLength := uartByte; + checksum := checksum + uartByte; + dataCount := dataLength; + communicationNextState := commStGetData; + end; + end; + { get data } + else if communicationState = commStGetData then + begin + uartStatus := getSerialPortByte(var uartByte: uint8); + if uartStatus = 0 then + begin + data1 := data2; + data2 := data3; + data3 := data4; + data4 := uartByte; + checksum := checksum + uartByte; + dataCount := dataCount-1; + if dataCount = 0 then + communicationNextState := commStGetChecksum; + end; + end; + { get checksum } + else if communicationState = commStGetChecksum then + begin + uartStatus := getSerialPortByte(var uartByte: uint8); + if uartStatus = 0 then + begin + if uartByte = checksum then + communicationState := commStExecuteCommand; + else + begin + commandId := commandNack; + dataLength := 0; + communicationNextState := commStSendHeader; + end; + end; + end; + { execute command } + else if communicationState = commStExecuteCommand then +begin + if (commandId = commandWriteMem) and (dataLength = commandWriteLength) then + begin + memAddress := data1 + (data2 shl 8); + memData := data3 + (data4 shl 8); + mem[memAddress] := memData; + dataLength := 0; + communicationNextState := commStSendHeader; + end; + else if (commandId = commandReadMem) and (dataLength = commandReadLength) then + begin + memAddress := data3 + (data4 shl 8); + memData := mem[memAddress]; + dataLength := 2; + data1 := memData and $00FF; + data2 := memData shr 8; + communicationNextState := commStSendHeader; + end; + else + begin + commandId := commandNack; + dataLength := 0; + communicationNextState := commStSendHeader; + end; +end; + { send header } + else if communicationState = commStSendHeader then + begin + uartByte := commandHeader; + uartStatus := sendSerialPort(var uartByte: uint8); + if uartStatus = 0 then + begin + checksum := uartByte; + communicationNextState := commStSendPacketId; + end; + end; + { send packet id } + else if communicationState = commStSendPacketId then + begin + uartByte := packetId; + uartStatus := sendSerialPort(var uartByte: uint8); + if uartStatus = 0 then + begin + checksum := checksum + uartByte; + communicationNextState := commStSendCommandId; + end; + end; + { send command id } + else if communicationState = commStSendCommandId then + begin + uartByte := commandId; + uartStatus := sendSerialPort(var uartByte: uint8); + if uartStatus = 0 then + begin + checksum := checksum + uartByte; + communicationNextState := commStSendDataLength; + end; + end; + { send data length } + else if communicationState = commStSendDataLength then + begin + uartByte := dataLength; + dataCount := dataLength; + uartStatus := sendSerialPort(var uartByte: uint8); + if uartStatus = 0 then + begin + checksum := checksum + uartByte; + communicationNextState := commStSendData; + end; + end; + { send data } + else if communicationState = commStSendData then + begin + if dataCount > 0 then + begin + uartByte := data1; + data2 := data1; + data3 := data2; + data4 := data3; + uartStatus := sendSerialPort(var uartByte: uint8); + if uartStatus = 0 then + begin + checksum := checksum + uartByte; + dataCount := dataCount-1; + end; + end; + else + communicationNextState := commStSendChecksum; + end; + { send checksum } + else if communicationState = commStSendChecksum then + begin + uartByte := checksum and $00FF; + uartStatus := sendSerialPort(var uartByte: uint8); + if uartStatus = 0 then + communicationNextState := commStIdle; + end; + { update state } + communicationState := communicationNextState; + end; + +{==============================================================================} +{ Main program } +{==============================================================================} +begin + { initialize SoC registers } + initRegisters; + { initialize communication state machine } + communicationState := commStIdle; + { main loop } + while true do begin + { update communication state machine } + updateStateMachine(var communicationState : word; var uartByte : uint8); + { check for timeout } + end; +end. diff --git a/Libs/NanoBlaze/hdl/nanoTest.vhd b/Libs/NanoBlaze/hdl/nanoTest.vhd new file mode 100644 index 0000000..f018830 --- /dev/null +++ b/Libs/NanoBlaze/hdl/nanoTest.vhd @@ -0,0 +1,431 @@ +ARCHITECTURE mapped OF programRom IS + + subtype opCodeType is std_ulogic_vector(5 downto 0); + constant opLoadC : opCodeType := "000000"; + constant opLoadR : opCodeType := "000001"; + constant opInputC : opCodeType := "000100"; + constant opInputR : opCodeType := "000101"; + constant opFetchC : opCodeType := "000110"; + constant opFetchR : opCodeType := "000111"; + constant opAndC : opCodeType := "001010"; + constant opAndR : opCodeType := "001011"; + constant opOrC : opCodeType := "001100"; + constant opOrR : opCodeType := "001101"; + constant opXorC : opCodeType := "001110"; + constant opXorR : opCodeType := "001111"; + constant opTestC : opCodeType := "010010"; + constant opTestR : opCodeType := "010011"; + constant opCompC : opCodeType := "010100"; + constant opCompR : opCodeType := "010101"; + constant opAddC : opCodeType := "011000"; + constant opAddR : opCodeType := "011001"; + constant opAddCyC : opCodeType := "011010"; + constant opAddCyR : opCodeType := "011011"; + constant opSubC : opCodeType := "011100"; + constant opSubR : opCodeType := "011101"; + constant opSubCyC : opCodeType := "011110"; + constant opSubCyR : opCodeType := "011111"; + constant opShRot : opCodeType := "100000"; + constant opOutputC : opCodeType := "101100"; + constant opOutputR : opCodeType := "101101"; + constant opStoreC : opCodeType := "101110"; + constant opStoreR : opCodeType := "101111"; + + subtype shRotCinType is std_ulogic_vector(2 downto 0); + constant shRotLdC : shRotCinType := "00-"; + constant shRotLdM : shRotCinType := "01-"; + constant shRotLdL : shRotCinType := "10-"; + constant shRotLd0 : shRotCinType := "110"; + constant shRotLd1 : shRotCinType := "111"; + + constant registerAddressBitNb : positive := 4; + constant shRotPadLength : positive + := dataOut'length - opCodeType'length - registerAddressBitNb + - 1 - shRotCinType'length; + subtype shRotDirType is std_ulogic_vector(1+shRotPadLength-1 downto 0); + constant shRotL : shRotDirType := (0 => '0', others => '-'); + constant shRotR : shRotDirType := (0 => '1', others => '-'); + + subtype branchCodeType is std_ulogic_vector(4 downto 0); + constant brRet : branchCodeType := "10101"; + constant brCall : branchCodeType := "11000"; + constant brJump : branchCodeType := "11010"; + constant brReti : branchCodeType := "11100"; + constant brEni : branchCodeType := "11110"; + + subtype branchConditionType is std_ulogic_vector(2 downto 0); + constant brDo : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( + --=============================================================== + -- 1) Test logical operations with direct values + ----------------------------------------------------------------- + 16#000# => opLoadC & "0111" & "00000001", -- LOAD s7, 01 + ----------------------------------------------------------------- + -- Test "LOAD", "AND" + ----------------------------------------------------------------- + 16#001# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#002# => opAndC & "0000" & "00110011", -- AND s0, 33 + 16#003# => opCompC & "0000" & "00000011", -- COMPARE s0, 03 + 16#004# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "OR" + ----------------------------------------------------------------- + 16#005# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#006# => opOrC & "0001" & "00110011", -- OR s1, 33 + 16#007# => opCompC & "0001" & "00111111", -- COMPARE s1, 3F + 16#008# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "XOR" + ----------------------------------------------------------------- + 16#009# => opLoadC & "0010" & "00001111", -- LOAD s2, 0F + 16#00A# => opXorC & "0010" & "00110011", -- XOR s2, 33 + 16#00B# => opCompC & "0010" & "00111100", -- COMPARE s2, 3C + 16#00C# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 2) Test logical operations with registers + ----------------------------------------------------------------- + 16#00D# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "LOAD" + ----------------------------------------------------------------- + 16#00E# => opLoadC & "0000" & "00110011", -- LOAD s0, 33 + 16#00F# => opLoadR & "0011" & "0000----", -- LOAD s3, s0 + 16#010# => opCompC & "0011" & "00110011", -- COMPARE s3, 33 + 16#011# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "AND" + ----------------------------------------------------------------- + 16#012# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#013# => opAndR & "0000" & "0011----", -- AND s0, s3 + 16#014# => opCompC & "0000" & "00000011", -- COMPARE s0, 03 + 16#015# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "OR" + ----------------------------------------------------------------- + 16#016# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#017# => opOrR & "0001" & "0011----", -- OR s1, s3 + 16#018# => opCompC & "0001" & "00111111", -- COMPARE s1, 3F + 16#019# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "XOR" + ----------------------------------------------------------------- + 16#01A# => opLoadC & "0010" & "00001111", -- LOAD s2, 0F + 16#01B# => opXorR & "0010" & "0011----", -- XOR s2, s3 + 16#01C# => opCompC & "0010" & "00111100", -- COMPARE s2, 3C + 16#01D# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 3) Test arithmetic operations with constants + ----------------------------------------------------------------- + 16#01E# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "ADD" and "ADDCY" + ----------------------------------------------------------------- + 16#01F# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#020# => opAddC & "0000" & "00110001", -- ADD s0, 31 ; 40 + 16#021# => opAddCyC & "0000" & "11110000", -- ADDCY s0, F0 ; 130 + 16#022# => opAddCyC & "0000" & "11110000", -- ADDCY s0, F0 ; 121 + 16#023# => opAddC & "0000" & "00001111", -- ADD s0, 0F ; 30 + 16#024# => opCompC & "0000" & "00110000", -- COMPARE s0, 30 + 16#025# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "SUB" and "SUBCY" + ----------------------------------------------------------------- + 16#026# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#027# => opSubC & "0001" & "00001100", -- SUB s1, 0C ; 03 + 16#028# => opSubCyC & "0001" & "11110000", -- SUBCY s1, F0 ; 113 + 16#029# => opSubCyC & "0001" & "11110000", -- SUBCY s1, F0 ; 22 + 16#02A# => opSubC & "0001" & "00000001", -- SUB s1, 01 ; 21 + 16#02B# => opCompC & "0001" & "00100001", -- COMPARE s1, 21 + 16#02C# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 4) Test arithmetic operations with registers + ----------------------------------------------------------------- + 16#02D# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "ADD" and "ADDCY" + ----------------------------------------------------------------- + 16#02E# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#02F# => opLoadC & "0001" & "00110001", -- LOAD s1, 31 + 16#030# => opLoadC & "0010" & "11110000", -- LOAD s2, F0 + 16#031# => opLoadC & "0011" & "00001111", -- LOAD s3, 0F + 16#032# => opAddR & "0000" & "0001----", -- ADD s0, s1 ; 40 + 16#033# => opAddCyR & "0000" & "0010----", -- ADDCY s0, s2 ; 130 + 16#034# => opAddCyR & "0000" & "0010----", -- ADDCY s0, s2 ; 121 + 16#035# => opAddR & "0000" & "0011----", -- ADD s0, s3 ; 30 + 16#036# => opCompC & "0000" & "00110000", -- COMPARE s0, 30 + 16#037# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "SUB" and "SUBCY" + ----------------------------------------------------------------- + 16#038# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#039# => opLoadC & "0000" & "00001100", -- LOAD s0, 0C + 16#03A# => opLoadC & "0010" & "11110000", -- LOAD s2, F0 + 16#03B# => opLoadC & "0011" & "00000001", -- LOAD s3, 01 + 16#03C# => opSubR & "0001" & "0000----", -- SUB s1, s0 ; 03 + 16#03D# => opSubCyR & "0001" & "0010----", -- SUBCY s1, s2 ; 113 + 16#03E# => opSubCyR & "0001" & "0010----", -- SUBCY s1, s2 ; 22 + 16#03F# => opSubR & "0001" & "0011----", -- SUB s1, s3 ; 21 + 16#040# => opCompC & "0001" & "00100001", -- COMPARE s1, 21 + 16#041# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 5) Test shifts + ----------------------------------------------------------------- + 16#042# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test shift right + ----------------------------------------------------------------- + 16#043# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F ; 0F + 16#044# => opShRot & "0000" & shRotR & shRotLd0,-- SR0 s0 ; 07 + 16#045# => opShRot & "0000" & shRotR & shRotLdM,-- SRX s0 ; 03 + 16#046# => opShRot & "0000" & shRotR & shRotLd1,-- SR1 s0 ; 81 + 16#047# => opShRot & "0000" & shRotR & shRotLdM,-- SRX s0 ; C0, C=1 + 16#048# => opShRot & "0000" & shRotR & shRotLdC,-- SRA s0 ; E0, C=0 + 16#049# => opShRot & "0000" & shRotR & shRotLdC,-- SRA s0 ; 70 + 16#04A# => opCompC & "0000" & "01110000", -- COMPARE s0, 70 + 16#04B# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test shift left + ----------------------------------------------------------------- + 16#04C# => opLoadC & "0001" & "11110000", -- LOAD s1, F0 ; FO + 16#04D# => opShRot & "0001" & shRotL & shRotLd0,-- SL0 s1 ; E0 + 16#04E# => opShRot & "0001" & shRotL & shRotLdL,-- SLX s1 ; C0 + 16#04F# => opShRot & "0001" & shRotL & shRotLd1,-- SL1 s1 ; 81 + 16#050# => opShRot & "0001" & shRotL & shRotLdL,-- SLX s1 ; 03, C=1 + 16#051# => opShRot & "0001" & shRotL & shRotLdC,-- SLA s1 ; 07, C=0 + 16#052# => opShRot & "0001" & shRotL & shRotLdC,-- SLA s1 ; 0E + 16#053# => opCompC & "0001" & "00001110", -- COMPARE s1, 0E + 16#054# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 6) Test comparison operators + ----------------------------------------------------------------- + 16#055# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "COMPARE" + ----------------------------------------------------------------- + 16#056# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#057# => opCompC & "0000" & "11110000", -- COMPARE s0, F0 ; A < B => C=1 + 16#058# => brJump & brNC & "1111111101", -- JUMP NC, 3FD + 16#059# => opCompC & "0000" & "11110000", -- COMPARE s0, F0 ; A < B => Z=0 + 16#05A# => brJump & brZ & "1111111101", -- JUMP Z, 3FD + 16#05B# => opCompR & "0000" & "0000----", -- COMPARE s0, s0 ; A = B => Z=1 + 16#05C# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + 16#05D# => opCompC & "0000" & "00001000", -- COMPARE s0, 08 ; A > B => C=0 + 16#05E# => brJump & brC & "1111111101", -- JUMP C, 3FD + 16#05F# => opCompC & "0000" & "00001000", -- COMPARE s0, 08 ; A > B => Z=0 + 16#060# => brJump & brZ & "1111111101", -- JUMP Z, 3FD + ----------------------------------------------------------------- + -- Test "TEST" + ----------------------------------------------------------------- + 16#061# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#062# => opTestC & "0000" & "11110000", -- TEST s0, F0 ; AND is 00 => Z=1 + 16#063# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + 16#064# => opTestC & "0000" & "11111111", -- TEST s0, FF ; AND is 0F => Z=0 + 16#065# => brJump & brZ & "1111111101", -- JUMP Z, 3FD + --=============================================================== + -- 7) Test INPUT and OUTPUT operators + ----------------------------------------------------------------- + 16#066# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "INPUT" and "OUTPUT" direct + -- + -- The testbench should invert the word written at address FC. + ----------------------------------------------------------------- + 16#067# => opLoadC & "0000" & "10101010", -- LOAD s0, AA + 16#068# => opOutputC & "0000" & "11111100", -- OUTPUT s0, FC + 16#069# => opInputC & "0001" & "11111100", -- INPUT s1, FC + 16#06A# => opCompC & "0001" & "01010101", -- COMPARE s1, 55 + 16#06B# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "INPUT" and "OUTPUT" indexed + ----------------------------------------------------------------- + 16#06C# => opLoadC & "0000" & "11001100", -- LOAD s0, CC + 16#06D# => opLoadC & "0010" & "11111100", -- LOAD s2, FC + 16#06E# => opOutputR & "0000" & "0010----", -- OUTPUT s0, (S2) + 16#06F# => opInputR & "0001" & "0010----", -- INPUT s1, (S2) + 16#070# => opCompC & "0001" & "00110011", -- COMPARE s1, 33 + 16#071# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 8) Test STORE and FETCH operators + ----------------------------------------------------------------- + 16#072# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "STORE" and "FETCH" direct + ----------------------------------------------------------------- + 16#073# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#074# => opStoreC & "0000" & "00000011", -- STORE s0, 03 + 16#075# => opFetchC & "0001" & "00000011", -- FETCH s1, 03 + 16#076# => opCompC & "0001" & "00001111", -- COMPARE s1, 0F + 16#077# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "STORE" and "FETCH" indexed + ----------------------------------------------------------------- + 16#078# => opLoadC & "0000" & "11110000", -- LOAD s0, F0 + 16#079# => opLoadC & "0010" & "00000100", -- LOAD s2, 04 + 16#07A# => opStoreR & "0000" & "0010----", -- STORE s0, (S2) + 16#07B# => opFetchR & "0001" & "0010----", -- FETCH s1, (S2) + 16#07C# => opCompC & "0001" & "11110000", -- COMPARE s1, F0 + 16#07D# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 9) Test JUMP instructions + ----------------------------------------------------------------- + 16#07E# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "JUMP NC" + ----------------------------------------------------------------- + 16#07F# => opLoadC & "0000" & "11110000", -- LOAD s0, F0 + 16#080# => opAddC & "0000" & "00000000", -- ADD s0, 00 ; s0=F0, C=0, Z=0 + 16#081# => brJump & brNC & "0010000011", -- JUMP NC, 083 + 16#082# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "JUMP NZ" + ----------------------------------------------------------------- + -- _continue1_: + 16#083# => opAddC & "0000" & "00000000", -- ADD s0, 00 ; s0=F0, C=0, Z=0 + 16#084# => brJump & brNZ & "0010000110", -- JUMP NZ, 086 + 16#085# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "JUMP C" + ----------------------------------------------------------------- + -- _continue2_: + 16#086# => opAddC & "0000" & "11110000", -- ADD s0, F0 ; s0=E0, C=1, Z=0 + 16#087# => brJump & brC & "0010001001", -- JUMP C, 089 + 16#088# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "JUMP Z" + ----------------------------------------------------------------- + -- _continue3_: + 16#089# => opSubC & "0000" & "11100000", -- SUB s0, E0 ; s0=00, C=0, Z=1 + 16#08A# => brJump & brZ & "0010001100", -- JUMP Z, 08C + 16#08B# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _continue4_: + 16#08C# => opLoadR & "0000" & "0000----", -- NOP + --=============================================================== + -- 10) Test call instructions + ----------------------------------------------------------------- + 16#08D# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- define subroutine + ----------------------------------------------------------------- + 16#08E# => brJump & brDo & "0010010010", -- JUMP 092 + -- _subRetDo_: + 16#08F# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#090# => brRet & brDo & "----------", -- RETURN + 16#091# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "CALL" + ----------------------------------------------------------------- + -- _continue5_: + 16#092# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 + 16#093# => opLoadC & "0001" & "11110000", -- LOAD s1, F0 + 16#094# => brCall & brDo & "0010001111", -- CALL 08F ; s0=01 + ----------------------------------------------------------------- + -- Test "CALL NC" + ----------------------------------------------------------------- + 16#095# => opAddC & "0001" & "00000000", -- ADD s1, 00 ; s1=F0, C=0, Z=0 + 16#096# => brCall & brNC & "0010001111", -- CALL NC, 08F ; s0=02 + ----------------------------------------------------------------- + -- Test "CALL NZ" + ----------------------------------------------------------------- + 16#097# => opAddC & "0001" & "00000000", -- ADD s1, 00 ; s1=F0, C=0, Z=0 + 16#098# => brCall & brNZ & "0010001111", -- CALL NZ, 08F ; s0=03 + ----------------------------------------------------------------- + -- Test "CALL C" + ----------------------------------------------------------------- + 16#099# => opAddC & "0001" & "11110000", -- ADD s1, F0 ; s0=E0, C=1, Z=0 + 16#09A# => brCall & brC & "0010001111", -- CALL C, 08F ; s0=04 + ----------------------------------------------------------------- + -- Test "CALL Z" + ----------------------------------------------------------------- + 16#09B# => opSubC & "0001" & "11100000", -- SUB s1, E0 ; s0=00, C=0, Z=1 + 16#09C# => brCall & brZ & "0010001111", -- CALL Z, 08F ; s0=05 + 16#09D# => opCompC & "0000" & "00000101", -- COMPARE s0, 05 + 16#09E# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 11) Test call return instructions + ----------------------------------------------------------------- + 16#09F# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- define subroutines + ----------------------------------------------------------------- + 16#0A0# => brJump & brDo & "0010101101", -- JUMP 0AD + -- _subRetNC_: + 16#0A1# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0A2# => brRet & brDo & "----------", -- RETURN NC + 16#0A3# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _subRetNZ_: + 16#0A4# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0A5# => brRet & brDo & "----------", -- RETURN NZ + 16#0A6# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _subRetC_: + 16#0A7# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0A8# => brRet & brDo & "----------", -- RETURN C + 16#0A9# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _subRetZ_: + 16#0AA# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0AB# => brRet & brDo & "----------", -- RETURN Z + 16#0AC# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "RETURN NC" + ----------------------------------------------------------------- + -- _continue6_: + 16#0AD# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 ; increment will give C=0, Z=0 + 16#0AE# => brCall & brNC & "0010100001", -- CALL NC, 0A1 + ----------------------------------------------------------------- + -- Test "RETURN NZ" + ----------------------------------------------------------------- + 16#0AF# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 ; increment will give C=0, Z=0 + 16#0B0# => brCall & brNZ & "0010100100", -- CALL NZ, 0A4 + ----------------------------------------------------------------- + -- Test "RETURN C" + ----------------------------------------------------------------- + 16#0B1# => opLoadC & "0000" & "11111111", -- LOAD s0, FF ; increment will give C=1, Z=1 + 16#0B2# => brCall & brC & "0010100111", -- CALL C, 0A7 + ----------------------------------------------------------------- + -- Test "RETURN Z" + ----------------------------------------------------------------- + 16#0B3# => opLoadC & "0000" & "11111111", -- LOAD s0, FF ; increment will give C=1, Z=1 + 16#0B4# => brCall & brZ & "0010101010", -- CALL Z, 0AA + --=============================================================== + -- End of tests + -- + -- The testbench should react if value 1 is written to address 00. + ----------------------------------------------------------------- + 16#0B5# => opLoadC & "0000" & "00000001", -- LOAD s0, 01 + 16#0B6# => opOutputC & "0000" & "00000000", -- OUTPUT s0, 00 + 16#0B7# => brJump & brDo & "1111111111", -- JUMP 3FF + --=============================================================== + -- Assert error + -- + -- The testbench should react if value 0 is written to address 00. + ----------------------------------------------------------------- + -- _error_: + 16#3FD# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 + 16#3FE# => opOutputC & "0000" & "00000000", -- OUTPUT s0, 00 + --=============================================================== + -- End of instruction memory + ----------------------------------------------------------------- + -- _endOfMemory_: + 16#3FF# => brJump & brDo & "1111111111", -- JUMP 3FF + others => (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= memoryArray(to_integer(address)); + end if; + end if; + end process; + +END ARCHITECTURE mapped; diff --git a/Libs/NanoBlaze/hdl/programCounter_RTL.vhd b/Libs/NanoBlaze/hdl/programCounter_RTL.vhd new file mode 100644 index 0000000..d2c2312 --- /dev/null +++ b/Libs/NanoBlaze/hdl/programCounter_RTL.vhd @@ -0,0 +1,24 @@ +ARCHITECTURE RTL OF programCounter IS + + signal pCounter: unsigned(progCounter'range); + +BEGIN + + updateProgramCounter: process(reset, clock) + begin + if reset = '1' then + pCounter <= (others => '0'); + elsif rising_edge(clock) then + if incPC = '1' then + pCounter <= pCounter + 1; + elsif loadInstrAddress = '1' then + pCounter <= instrAddress; + elsif loadStoredPC = '1' then + pCounter <= storedProgCounter; + end if; + end if; + end process updateProgramCounter; + + progCounter <= pCounter; + +END ARCHITECTURE RTL; diff --git a/Libs/NanoBlaze/hdl/registerFile_RTL.vhd b/Libs/NanoBlaze/hdl/registerFile_RTL.vhd new file mode 100644 index 0000000..961b26c --- /dev/null +++ b/Libs/NanoBlaze/hdl/registerFile_RTL.vhd @@ -0,0 +1,26 @@ +ARCHITECTURE RTL OF registerFile IS + + subtype registerType is signed(registersIn'range); + type registerArrayType is array (0 to 2**registerAddressBitNb-1) of registerType; + signal registerArray : registerArrayType; + +BEGIN + ------------------------------------------------------------------------------ + -- write to registers + updateRegister: process(reset, clock) + begin + if reset = '1' then + registerArray <= (others => (others => '0')); + elsif rising_edge(clock) then + if regWrite = '1' then + registerArray(to_integer(addrA)) <= registersIn; + end if; + end if; + end process updateRegister; + + ------------------------------------------------------------------------------ + -- read from registers + opA <= registerArray(to_integer(addrA)); + opB <= registerArray(to_integer(addrB)); + +END ARCHITECTURE RTL; diff --git a/Libs/NanoBlaze/hdl/rom_empty.vhd b/Libs/NanoBlaze/hdl/rom_empty.vhd new file mode 100644 index 0000000..07d5f76 --- /dev/null +++ b/Libs/NanoBlaze/hdl/rom_empty.vhd @@ -0,0 +1,21 @@ +ARCHITECTURE empty OF programRom IS + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( + others => (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= (others => '0'); + end if; + end if; + end process; + +END ARCHITECTURE empty; diff --git a/Libs/NanoBlaze/hdl/rom_mapped.vhd b/Libs/NanoBlaze/hdl/rom_mapped.vhd new file mode 100644 index 0000000..f018830 --- /dev/null +++ b/Libs/NanoBlaze/hdl/rom_mapped.vhd @@ -0,0 +1,431 @@ +ARCHITECTURE mapped OF programRom IS + + subtype opCodeType is std_ulogic_vector(5 downto 0); + constant opLoadC : opCodeType := "000000"; + constant opLoadR : opCodeType := "000001"; + constant opInputC : opCodeType := "000100"; + constant opInputR : opCodeType := "000101"; + constant opFetchC : opCodeType := "000110"; + constant opFetchR : opCodeType := "000111"; + constant opAndC : opCodeType := "001010"; + constant opAndR : opCodeType := "001011"; + constant opOrC : opCodeType := "001100"; + constant opOrR : opCodeType := "001101"; + constant opXorC : opCodeType := "001110"; + constant opXorR : opCodeType := "001111"; + constant opTestC : opCodeType := "010010"; + constant opTestR : opCodeType := "010011"; + constant opCompC : opCodeType := "010100"; + constant opCompR : opCodeType := "010101"; + constant opAddC : opCodeType := "011000"; + constant opAddR : opCodeType := "011001"; + constant opAddCyC : opCodeType := "011010"; + constant opAddCyR : opCodeType := "011011"; + constant opSubC : opCodeType := "011100"; + constant opSubR : opCodeType := "011101"; + constant opSubCyC : opCodeType := "011110"; + constant opSubCyR : opCodeType := "011111"; + constant opShRot : opCodeType := "100000"; + constant opOutputC : opCodeType := "101100"; + constant opOutputR : opCodeType := "101101"; + constant opStoreC : opCodeType := "101110"; + constant opStoreR : opCodeType := "101111"; + + subtype shRotCinType is std_ulogic_vector(2 downto 0); + constant shRotLdC : shRotCinType := "00-"; + constant shRotLdM : shRotCinType := "01-"; + constant shRotLdL : shRotCinType := "10-"; + constant shRotLd0 : shRotCinType := "110"; + constant shRotLd1 : shRotCinType := "111"; + + constant registerAddressBitNb : positive := 4; + constant shRotPadLength : positive + := dataOut'length - opCodeType'length - registerAddressBitNb + - 1 - shRotCinType'length; + subtype shRotDirType is std_ulogic_vector(1+shRotPadLength-1 downto 0); + constant shRotL : shRotDirType := (0 => '0', others => '-'); + constant shRotR : shRotDirType := (0 => '1', others => '-'); + + subtype branchCodeType is std_ulogic_vector(4 downto 0); + constant brRet : branchCodeType := "10101"; + constant brCall : branchCodeType := "11000"; + constant brJump : branchCodeType := "11010"; + constant brReti : branchCodeType := "11100"; + constant brEni : branchCodeType := "11110"; + + subtype branchConditionType is std_ulogic_vector(2 downto 0); + constant brDo : branchConditionType := "000"; + constant brZ : branchConditionType := "100"; + constant brNZ : branchConditionType := "101"; + constant brC : branchConditionType := "110"; + constant brNC : branchConditionType := "111"; + + subtype memoryWordType is std_ulogic_vector(dataOut'range); + type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType := ( + --=============================================================== + -- 1) Test logical operations with direct values + ----------------------------------------------------------------- + 16#000# => opLoadC & "0111" & "00000001", -- LOAD s7, 01 + ----------------------------------------------------------------- + -- Test "LOAD", "AND" + ----------------------------------------------------------------- + 16#001# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#002# => opAndC & "0000" & "00110011", -- AND s0, 33 + 16#003# => opCompC & "0000" & "00000011", -- COMPARE s0, 03 + 16#004# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "OR" + ----------------------------------------------------------------- + 16#005# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#006# => opOrC & "0001" & "00110011", -- OR s1, 33 + 16#007# => opCompC & "0001" & "00111111", -- COMPARE s1, 3F + 16#008# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "XOR" + ----------------------------------------------------------------- + 16#009# => opLoadC & "0010" & "00001111", -- LOAD s2, 0F + 16#00A# => opXorC & "0010" & "00110011", -- XOR s2, 33 + 16#00B# => opCompC & "0010" & "00111100", -- COMPARE s2, 3C + 16#00C# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 2) Test logical operations with registers + ----------------------------------------------------------------- + 16#00D# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "LOAD" + ----------------------------------------------------------------- + 16#00E# => opLoadC & "0000" & "00110011", -- LOAD s0, 33 + 16#00F# => opLoadR & "0011" & "0000----", -- LOAD s3, s0 + 16#010# => opCompC & "0011" & "00110011", -- COMPARE s3, 33 + 16#011# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "AND" + ----------------------------------------------------------------- + 16#012# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#013# => opAndR & "0000" & "0011----", -- AND s0, s3 + 16#014# => opCompC & "0000" & "00000011", -- COMPARE s0, 03 + 16#015# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "OR" + ----------------------------------------------------------------- + 16#016# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#017# => opOrR & "0001" & "0011----", -- OR s1, s3 + 16#018# => opCompC & "0001" & "00111111", -- COMPARE s1, 3F + 16#019# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "XOR" + ----------------------------------------------------------------- + 16#01A# => opLoadC & "0010" & "00001111", -- LOAD s2, 0F + 16#01B# => opXorR & "0010" & "0011----", -- XOR s2, s3 + 16#01C# => opCompC & "0010" & "00111100", -- COMPARE s2, 3C + 16#01D# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 3) Test arithmetic operations with constants + ----------------------------------------------------------------- + 16#01E# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "ADD" and "ADDCY" + ----------------------------------------------------------------- + 16#01F# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#020# => opAddC & "0000" & "00110001", -- ADD s0, 31 ; 40 + 16#021# => opAddCyC & "0000" & "11110000", -- ADDCY s0, F0 ; 130 + 16#022# => opAddCyC & "0000" & "11110000", -- ADDCY s0, F0 ; 121 + 16#023# => opAddC & "0000" & "00001111", -- ADD s0, 0F ; 30 + 16#024# => opCompC & "0000" & "00110000", -- COMPARE s0, 30 + 16#025# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "SUB" and "SUBCY" + ----------------------------------------------------------------- + 16#026# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#027# => opSubC & "0001" & "00001100", -- SUB s1, 0C ; 03 + 16#028# => opSubCyC & "0001" & "11110000", -- SUBCY s1, F0 ; 113 + 16#029# => opSubCyC & "0001" & "11110000", -- SUBCY s1, F0 ; 22 + 16#02A# => opSubC & "0001" & "00000001", -- SUB s1, 01 ; 21 + 16#02B# => opCompC & "0001" & "00100001", -- COMPARE s1, 21 + 16#02C# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 4) Test arithmetic operations with registers + ----------------------------------------------------------------- + 16#02D# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "ADD" and "ADDCY" + ----------------------------------------------------------------- + 16#02E# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#02F# => opLoadC & "0001" & "00110001", -- LOAD s1, 31 + 16#030# => opLoadC & "0010" & "11110000", -- LOAD s2, F0 + 16#031# => opLoadC & "0011" & "00001111", -- LOAD s3, 0F + 16#032# => opAddR & "0000" & "0001----", -- ADD s0, s1 ; 40 + 16#033# => opAddCyR & "0000" & "0010----", -- ADDCY s0, s2 ; 130 + 16#034# => opAddCyR & "0000" & "0010----", -- ADDCY s0, s2 ; 121 + 16#035# => opAddR & "0000" & "0011----", -- ADD s0, s3 ; 30 + 16#036# => opCompC & "0000" & "00110000", -- COMPARE s0, 30 + 16#037# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "SUB" and "SUBCY" + ----------------------------------------------------------------- + 16#038# => opLoadC & "0001" & "00001111", -- LOAD s1, 0F + 16#039# => opLoadC & "0000" & "00001100", -- LOAD s0, 0C + 16#03A# => opLoadC & "0010" & "11110000", -- LOAD s2, F0 + 16#03B# => opLoadC & "0011" & "00000001", -- LOAD s3, 01 + 16#03C# => opSubR & "0001" & "0000----", -- SUB s1, s0 ; 03 + 16#03D# => opSubCyR & "0001" & "0010----", -- SUBCY s1, s2 ; 113 + 16#03E# => opSubCyR & "0001" & "0010----", -- SUBCY s1, s2 ; 22 + 16#03F# => opSubR & "0001" & "0011----", -- SUB s1, s3 ; 21 + 16#040# => opCompC & "0001" & "00100001", -- COMPARE s1, 21 + 16#041# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 5) Test shifts + ----------------------------------------------------------------- + 16#042# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test shift right + ----------------------------------------------------------------- + 16#043# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F ; 0F + 16#044# => opShRot & "0000" & shRotR & shRotLd0,-- SR0 s0 ; 07 + 16#045# => opShRot & "0000" & shRotR & shRotLdM,-- SRX s0 ; 03 + 16#046# => opShRot & "0000" & shRotR & shRotLd1,-- SR1 s0 ; 81 + 16#047# => opShRot & "0000" & shRotR & shRotLdM,-- SRX s0 ; C0, C=1 + 16#048# => opShRot & "0000" & shRotR & shRotLdC,-- SRA s0 ; E0, C=0 + 16#049# => opShRot & "0000" & shRotR & shRotLdC,-- SRA s0 ; 70 + 16#04A# => opCompC & "0000" & "01110000", -- COMPARE s0, 70 + 16#04B# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test shift left + ----------------------------------------------------------------- + 16#04C# => opLoadC & "0001" & "11110000", -- LOAD s1, F0 ; FO + 16#04D# => opShRot & "0001" & shRotL & shRotLd0,-- SL0 s1 ; E0 + 16#04E# => opShRot & "0001" & shRotL & shRotLdL,-- SLX s1 ; C0 + 16#04F# => opShRot & "0001" & shRotL & shRotLd1,-- SL1 s1 ; 81 + 16#050# => opShRot & "0001" & shRotL & shRotLdL,-- SLX s1 ; 03, C=1 + 16#051# => opShRot & "0001" & shRotL & shRotLdC,-- SLA s1 ; 07, C=0 + 16#052# => opShRot & "0001" & shRotL & shRotLdC,-- SLA s1 ; 0E + 16#053# => opCompC & "0001" & "00001110", -- COMPARE s1, 0E + 16#054# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 6) Test comparison operators + ----------------------------------------------------------------- + 16#055# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "COMPARE" + ----------------------------------------------------------------- + 16#056# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#057# => opCompC & "0000" & "11110000", -- COMPARE s0, F0 ; A < B => C=1 + 16#058# => brJump & brNC & "1111111101", -- JUMP NC, 3FD + 16#059# => opCompC & "0000" & "11110000", -- COMPARE s0, F0 ; A < B => Z=0 + 16#05A# => brJump & brZ & "1111111101", -- JUMP Z, 3FD + 16#05B# => opCompR & "0000" & "0000----", -- COMPARE s0, s0 ; A = B => Z=1 + 16#05C# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + 16#05D# => opCompC & "0000" & "00001000", -- COMPARE s0, 08 ; A > B => C=0 + 16#05E# => brJump & brC & "1111111101", -- JUMP C, 3FD + 16#05F# => opCompC & "0000" & "00001000", -- COMPARE s0, 08 ; A > B => Z=0 + 16#060# => brJump & brZ & "1111111101", -- JUMP Z, 3FD + ----------------------------------------------------------------- + -- Test "TEST" + ----------------------------------------------------------------- + 16#061# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#062# => opTestC & "0000" & "11110000", -- TEST s0, F0 ; AND is 00 => Z=1 + 16#063# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + 16#064# => opTestC & "0000" & "11111111", -- TEST s0, FF ; AND is 0F => Z=0 + 16#065# => brJump & brZ & "1111111101", -- JUMP Z, 3FD + --=============================================================== + -- 7) Test INPUT and OUTPUT operators + ----------------------------------------------------------------- + 16#066# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "INPUT" and "OUTPUT" direct + -- + -- The testbench should invert the word written at address FC. + ----------------------------------------------------------------- + 16#067# => opLoadC & "0000" & "10101010", -- LOAD s0, AA + 16#068# => opOutputC & "0000" & "11111100", -- OUTPUT s0, FC + 16#069# => opInputC & "0001" & "11111100", -- INPUT s1, FC + 16#06A# => opCompC & "0001" & "01010101", -- COMPARE s1, 55 + 16#06B# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "INPUT" and "OUTPUT" indexed + ----------------------------------------------------------------- + 16#06C# => opLoadC & "0000" & "11001100", -- LOAD s0, CC + 16#06D# => opLoadC & "0010" & "11111100", -- LOAD s2, FC + 16#06E# => opOutputR & "0000" & "0010----", -- OUTPUT s0, (S2) + 16#06F# => opInputR & "0001" & "0010----", -- INPUT s1, (S2) + 16#070# => opCompC & "0001" & "00110011", -- COMPARE s1, 33 + 16#071# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 8) Test STORE and FETCH operators + ----------------------------------------------------------------- + 16#072# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "STORE" and "FETCH" direct + ----------------------------------------------------------------- + 16#073# => opLoadC & "0000" & "00001111", -- LOAD s0, 0F + 16#074# => opStoreC & "0000" & "00000011", -- STORE s0, 03 + 16#075# => opFetchC & "0001" & "00000011", -- FETCH s1, 03 + 16#076# => opCompC & "0001" & "00001111", -- COMPARE s1, 0F + 16#077# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + ----------------------------------------------------------------- + -- Test "STORE" and "FETCH" indexed + ----------------------------------------------------------------- + 16#078# => opLoadC & "0000" & "11110000", -- LOAD s0, F0 + 16#079# => opLoadC & "0010" & "00000100", -- LOAD s2, 04 + 16#07A# => opStoreR & "0000" & "0010----", -- STORE s0, (S2) + 16#07B# => opFetchR & "0001" & "0010----", -- FETCH s1, (S2) + 16#07C# => opCompC & "0001" & "11110000", -- COMPARE s1, F0 + 16#07D# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 9) Test JUMP instructions + ----------------------------------------------------------------- + 16#07E# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- Test "JUMP NC" + ----------------------------------------------------------------- + 16#07F# => opLoadC & "0000" & "11110000", -- LOAD s0, F0 + 16#080# => opAddC & "0000" & "00000000", -- ADD s0, 00 ; s0=F0, C=0, Z=0 + 16#081# => brJump & brNC & "0010000011", -- JUMP NC, 083 + 16#082# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "JUMP NZ" + ----------------------------------------------------------------- + -- _continue1_: + 16#083# => opAddC & "0000" & "00000000", -- ADD s0, 00 ; s0=F0, C=0, Z=0 + 16#084# => brJump & brNZ & "0010000110", -- JUMP NZ, 086 + 16#085# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "JUMP C" + ----------------------------------------------------------------- + -- _continue2_: + 16#086# => opAddC & "0000" & "11110000", -- ADD s0, F0 ; s0=E0, C=1, Z=0 + 16#087# => brJump & brC & "0010001001", -- JUMP C, 089 + 16#088# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "JUMP Z" + ----------------------------------------------------------------- + -- _continue3_: + 16#089# => opSubC & "0000" & "11100000", -- SUB s0, E0 ; s0=00, C=0, Z=1 + 16#08A# => brJump & brZ & "0010001100", -- JUMP Z, 08C + 16#08B# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _continue4_: + 16#08C# => opLoadR & "0000" & "0000----", -- NOP + --=============================================================== + -- 10) Test call instructions + ----------------------------------------------------------------- + 16#08D# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- define subroutine + ----------------------------------------------------------------- + 16#08E# => brJump & brDo & "0010010010", -- JUMP 092 + -- _subRetDo_: + 16#08F# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#090# => brRet & brDo & "----------", -- RETURN + 16#091# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "CALL" + ----------------------------------------------------------------- + -- _continue5_: + 16#092# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 + 16#093# => opLoadC & "0001" & "11110000", -- LOAD s1, F0 + 16#094# => brCall & brDo & "0010001111", -- CALL 08F ; s0=01 + ----------------------------------------------------------------- + -- Test "CALL NC" + ----------------------------------------------------------------- + 16#095# => opAddC & "0001" & "00000000", -- ADD s1, 00 ; s1=F0, C=0, Z=0 + 16#096# => brCall & brNC & "0010001111", -- CALL NC, 08F ; s0=02 + ----------------------------------------------------------------- + -- Test "CALL NZ" + ----------------------------------------------------------------- + 16#097# => opAddC & "0001" & "00000000", -- ADD s1, 00 ; s1=F0, C=0, Z=0 + 16#098# => brCall & brNZ & "0010001111", -- CALL NZ, 08F ; s0=03 + ----------------------------------------------------------------- + -- Test "CALL C" + ----------------------------------------------------------------- + 16#099# => opAddC & "0001" & "11110000", -- ADD s1, F0 ; s0=E0, C=1, Z=0 + 16#09A# => brCall & brC & "0010001111", -- CALL C, 08F ; s0=04 + ----------------------------------------------------------------- + -- Test "CALL Z" + ----------------------------------------------------------------- + 16#09B# => opSubC & "0001" & "11100000", -- SUB s1, E0 ; s0=00, C=0, Z=1 + 16#09C# => brCall & brZ & "0010001111", -- CALL Z, 08F ; s0=05 + 16#09D# => opCompC & "0000" & "00000101", -- COMPARE s0, 05 + 16#09E# => brJump & brNZ & "1111111101", -- JUMP NZ, 3FD + --=============================================================== + -- 11) Test call return instructions + ----------------------------------------------------------------- + 16#09F# => opAddC & "0111" & "00000001", -- ADD s7, 01 + ----------------------------------------------------------------- + -- define subroutines + ----------------------------------------------------------------- + 16#0A0# => brJump & brDo & "0010101101", -- JUMP 0AD + -- _subRetNC_: + 16#0A1# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0A2# => brRet & brDo & "----------", -- RETURN NC + 16#0A3# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _subRetNZ_: + 16#0A4# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0A5# => brRet & brDo & "----------", -- RETURN NZ + 16#0A6# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _subRetC_: + 16#0A7# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0A8# => brRet & brDo & "----------", -- RETURN C + 16#0A9# => brJump & brDo & "1111111101", -- JUMP 3FD + -- _subRetZ_: + 16#0AA# => opAddC & "0000" & "00000001", -- ADD s0, 01 + 16#0AB# => brRet & brDo & "----------", -- RETURN Z + 16#0AC# => brJump & brDo & "1111111101", -- JUMP 3FD + ----------------------------------------------------------------- + -- Test "RETURN NC" + ----------------------------------------------------------------- + -- _continue6_: + 16#0AD# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 ; increment will give C=0, Z=0 + 16#0AE# => brCall & brNC & "0010100001", -- CALL NC, 0A1 + ----------------------------------------------------------------- + -- Test "RETURN NZ" + ----------------------------------------------------------------- + 16#0AF# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 ; increment will give C=0, Z=0 + 16#0B0# => brCall & brNZ & "0010100100", -- CALL NZ, 0A4 + ----------------------------------------------------------------- + -- Test "RETURN C" + ----------------------------------------------------------------- + 16#0B1# => opLoadC & "0000" & "11111111", -- LOAD s0, FF ; increment will give C=1, Z=1 + 16#0B2# => brCall & brC & "0010100111", -- CALL C, 0A7 + ----------------------------------------------------------------- + -- Test "RETURN Z" + ----------------------------------------------------------------- + 16#0B3# => opLoadC & "0000" & "11111111", -- LOAD s0, FF ; increment will give C=1, Z=1 + 16#0B4# => brCall & brZ & "0010101010", -- CALL Z, 0AA + --=============================================================== + -- End of tests + -- + -- The testbench should react if value 1 is written to address 00. + ----------------------------------------------------------------- + 16#0B5# => opLoadC & "0000" & "00000001", -- LOAD s0, 01 + 16#0B6# => opOutputC & "0000" & "00000000", -- OUTPUT s0, 00 + 16#0B7# => brJump & brDo & "1111111111", -- JUMP 3FF + --=============================================================== + -- Assert error + -- + -- The testbench should react if value 0 is written to address 00. + ----------------------------------------------------------------- + -- _error_: + 16#3FD# => opLoadC & "0000" & "00000000", -- LOAD s0, 00 + 16#3FE# => opOutputC & "0000" & "00000000", -- OUTPUT s0, 00 + --=============================================================== + -- End of instruction memory + ----------------------------------------------------------------- + -- _endOfMemory_: + 16#3FF# => brJump & brDo & "1111111111", -- JUMP 3FF + others => (others => '0') + ); + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if en = '1' then + dataOut <= memoryArray(to_integer(address)); + end if; + end if; + end process; + +END ARCHITECTURE mapped; diff --git a/Libs/NanoBlaze/hdl/scratchpad_RTL.vhd b/Libs/NanoBlaze/hdl/scratchpad_RTL.vhd new file mode 100644 index 0000000..7557a00 --- /dev/null +++ b/Libs/NanoBlaze/hdl/scratchpad_RTL.vhd @@ -0,0 +1,21 @@ +ARCHITECTURE RTL OF scratchpad IS + + subtype memoryWordType is signed(dataOut'range); + type memoryArrayType is array (0 to 2**addr'length-1) of memoryWordType; + + signal memoryArray : memoryArrayType; + +BEGIN + + process (clock) + begin + if rising_edge(clock) then + if write = '1' then + memoryArray(to_integer(addr)) <= dataIn; + end if; + end if; + end process; + + dataOut <= memoryArray(to_integer(addr)); + +END ARCHITECTURE RTL; diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_aluBOpSelector_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_aluBOpSelector_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_aluBOpSelector_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_alu_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_alu_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_alu_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_alu_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_alu_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_alu_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_aluandregs_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_aluandregs_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_aluandregs_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_aluandregs_struct.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_aluandregs_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_aluandregs_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_alubopselector_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_alubopselector_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_alubopselector_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_branchStack_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_branchStack_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_branchStack_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_branchstack_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_branchstack_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_branchstack_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_controller_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_controller_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_controller_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_controller_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_controller_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_controller_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_instructionDecoder_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_instructionDecoder_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_instructionDecoder_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_instructiondecoder_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_instructiondecoder_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_instructiondecoder_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_nanoTest.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoTest.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoTest.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_nanoblaze_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoblaze_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoblaze_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_nanoblaze_struct.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoblaze_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoblaze_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_nanoprocessor_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoprocessor_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoprocessor_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_nanoprocessor_struct.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoprocessor_struct.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_nanoprocessor_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_programCounter_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_programCounter_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_programCounter_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_programcounter_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_programcounter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_programcounter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_programrom_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_programrom_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_programrom_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_registerFile_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_registerFile_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_registerFile_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_registerfile_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_registerfile_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_registerfile_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_rom_empty.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_rom_empty.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_rom_empty.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_rom_mapped.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_rom_mapped.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_rom_mapped.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_scratchpad_RTL.vhd._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_scratchpad_RTL.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_scratchpad_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/.hdlsidedata/_scratchpad_entity.vhg._fpf b/Libs/NanoBlaze/hds/.hdlsidedata/_scratchpad_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/NanoBlaze/hds/.hdlsidedata/_scratchpad_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze/hds/_alu._epf b/Libs/NanoBlaze/hds/_alu._epf new file mode 100644 index 0000000..903076b --- /dev/null +++ b/Libs/NanoBlaze/hds/_alu._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom alu_RTL.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/NanoBlaze/hds/_aluandregs._epf b/Libs/NanoBlaze/hds/_aluandregs._epf new file mode 100644 index 0000000..442021e --- /dev/null +++ b/Libs/NanoBlaze/hds/_aluandregs._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom alu@and@regs/struct.bd diff --git a/Libs/NanoBlaze/hds/_alubopselector._epf b/Libs/NanoBlaze/hds/_alubopselector._epf new file mode 100644 index 0000000..8fd9406 --- /dev/null +++ b/Libs/NanoBlaze/hds/_alubopselector._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom aluBOpSelector_RTL.vhd diff --git a/Libs/NanoBlaze/hds/_branchstack._epf b/Libs/NanoBlaze/hds/_branchstack._epf new file mode 100644 index 0000000..4f1ef8e --- /dev/null +++ b/Libs/NanoBlaze/hds/_branchstack._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom branchStack_RTL.vhd diff --git a/Libs/NanoBlaze/hds/_controller._epf b/Libs/NanoBlaze/hds/_controller._epf new file mode 100644 index 0000000..4d80bb2 --- /dev/null +++ b/Libs/NanoBlaze/hds/_controller._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom controller_RTL.vhd diff --git a/Libs/NanoBlaze/hds/_instructiondecoder._epf b/Libs/NanoBlaze/hds/_instructiondecoder._epf new file mode 100644 index 0000000..bc9ab74 --- /dev/null +++ b/Libs/NanoBlaze/hds/_instructiondecoder._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom instructionDecoder_RTL.vhd diff --git a/Libs/NanoBlaze/hds/_nanoblaze._epf b/Libs/NanoBlaze/hds/_nanoblaze._epf new file mode 100644 index 0000000..943becd --- /dev/null +++ b/Libs/NanoBlaze/hds/_nanoblaze._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom nano@blaze/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/NanoBlaze/hds/_nanoprocessor._epf b/Libs/NanoBlaze/hds/_nanoprocessor._epf new file mode 100644 index 0000000..1028fa8 --- /dev/null +++ b/Libs/NanoBlaze/hds/_nanoprocessor._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom nano@processor/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/Libs/NanoBlaze/hds/_programcounter._epf b/Libs/NanoBlaze/hds/_programcounter._epf new file mode 100644 index 0000000..bb4bfe1 --- /dev/null +++ b/Libs/NanoBlaze/hds/_programcounter._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom programCounter_RTL.vhd diff --git a/Libs/NanoBlaze/hds/_programrom._epf b/Libs/NanoBlaze/hds/_programrom._epf new file mode 100644 index 0000000..04f9d0f --- /dev/null +++ b/Libs/NanoBlaze/hds/_programrom._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom rom_mapped.vhd +DEFAULT_ARCHITECTURE atom mapped diff --git a/Libs/NanoBlaze/hds/_registerfile._epf b/Libs/NanoBlaze/hds/_registerfile._epf new file mode 100644 index 0000000..a085908 --- /dev/null +++ b/Libs/NanoBlaze/hds/_registerfile._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom registerFile_RTL.vhd diff --git a/Libs/NanoBlaze/hds/_scratchpad._epf b/Libs/NanoBlaze/hds/_scratchpad._epf new file mode 100644 index 0000000..faf93aa --- /dev/null +++ b/Libs/NanoBlaze/hds/_scratchpad._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom RTL +DEFAULT_FILE atom scratchpad_RTL.vhd diff --git a/Libs/NanoBlaze/hds/alu/symbol.sb b/Libs/NanoBlaze/hds/alu/symbol.sb new file mode 100644 index 0000000..59d74d6 --- /dev/null +++ b/Libs/NanoBlaze/hds/alu/symbol.sb @@ -0,0 +1,1715 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2007.1a (Build 13)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 20,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 172,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "opA" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 1 +suid 3,0 +) +) +uid 140,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "cIn" +t "std_ulogic" +o 2 +suid 8,0 +) +) +uid 150,0 +) +*16 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "cOut" +t "std_ulogic" +o 3 +suid 11,0 +) +) +uid 156,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "aluCode" +t "std_ulogic_vector" +b "( aluCodeBitNb-1 DOWNTO 0 )" +o 4 +suid 13,0 +) +) +uid 160,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "opB" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 5 +suid 18,0 +) +) +uid 335,0 +) +*19 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "aluOut" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 6 +suid 19,0 +) +) +uid 337,0 +) +*20 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "zero" +t "std_ulogic" +o 7 +suid 20,0 +) +) +uid 393,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 185,0 +optionalChildren [ +*21 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *22 (MRCItem +litem &1 +pos 7 +dimension 20 +) +uid 187,0 +optionalChildren [ +*23 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 188,0 +) +*24 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 189,0 +) +*25 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 190,0 +) +*26 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 141,0 +) +*27 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 151,0 +) +*28 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 157,0 +) +*29 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 161,0 +) +*30 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 336,0 +) +*31 (MRCItem +litem &19 +pos 5 +dimension 20 +uid 338,0 +) +*32 (MRCItem +litem &20 +pos 6 +dimension 20 +uid 394,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 191,0 +optionalChildren [ +*33 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 192,0 +) +*34 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 193,0 +) +*35 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 194,0 +) +*36 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 195,0 +) +*37 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 196,0 +) +*38 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 197,0 +) +*39 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 198,0 +) +*40 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 199,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 186,0 +vaOverrides [ +] +) +] +) +uid 171,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *41 (LEmptyRow +) +uid 201,0 +optionalChildren [ +*42 (RefLabelRowHdr +) +*43 (TitleRowHdr +) +*44 (FilterRowHdr +) +*45 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*46 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*47 (GroupColHdr +tm "GroupColHdrMgr" +) +*48 (NameColHdr +tm "GenericNameColHdrMgr" +) +*49 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*50 (InitColHdr +tm "GenericValueColHdrMgr" +) +*51 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*52 (EolColHdr +tm "GenericEolColHdrMgr" +) +*53 (LogGeneric +generic (GiElement +name "aluCodeBitNb" +type "positive" +value "5" +) +uid 250,0 +) +*54 (LogGeneric +generic (GiElement +name "dataBitNb" +type "positive" +value "8" +) +uid 252,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 213,0 +optionalChildren [ +*55 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *56 (MRCItem +litem &41 +pos 2 +dimension 20 +) +uid 215,0 +optionalChildren [ +*57 (MRCItem +litem &42 +pos 0 +dimension 20 +uid 216,0 +) +*58 (MRCItem +litem &43 +pos 1 +dimension 23 +uid 217,0 +) +*59 (MRCItem +litem &44 +pos 2 +hidden 1 +dimension 20 +uid 218,0 +) +*60 (MRCItem +litem &53 +pos 0 +dimension 20 +uid 251,0 +) +*61 (MRCItem +litem &54 +pos 1 +dimension 20 +uid 253,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 219,0 +optionalChildren [ +*62 (MRCItem +litem &45 +pos 0 +dimension 20 +uid 220,0 +) +*63 (MRCItem +litem &47 +pos 1 +dimension 50 +uid 221,0 +) +*64 (MRCItem +litem &48 +pos 2 +dimension 100 +uid 222,0 +) +*65 (MRCItem +litem &49 +pos 3 +dimension 100 +uid 223,0 +) +*66 (MRCItem +litem &50 +pos 4 +dimension 50 +uid 224,0 +) +*67 (MRCItem +litem &51 +pos 5 +dimension 50 +uid 225,0 +) +*68 (MRCItem +litem &52 +pos 6 +dimension 80 +uid 226,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 214,0 +vaOverrides [ +] +) +] +) +uid 200,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\PicoBlaze\\Circuit\\Prefs\\..\\PicoBlaze\\hdl" +) +(vvPair +variable "HDSDir" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\PicoBlaze\\Circuit\\Prefs\\..\\PicoBlaze\\hds" +) +(vvPair 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(MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,20000,0,20000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "-2000,11400,-2000,11400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 394,0 +activeModelName "Symbol" +) diff --git a/Libs/NanoBlaze/hds/alu@and@regs/struct.bd b/Libs/NanoBlaze/hds/alu@and@regs/struct.bd new file mode 100644 index 0000000..669bf27 --- /dev/null +++ b/Libs/NanoBlaze/hds/alu@and@regs/struct.bd @@ -0,0 +1,6384 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_bSel" +duLibraryName "NanoBlaze" +duName "aluBOpSelector" +elements [ +(GiElement +name "registerBitNb" +type "positive" +value "registerBitNb" +) +] +mwi 0 +uid 1828,0 +) +(Instance +name "I_regs" +duLibraryName "NanoBlaze" +duName "registerFile" +elements [ +(GiElement +name "registerAddressBitNb" +type "positive" +value "registerAddressBitNb" +) +(GiElement +name "dataBitNb" +type "positive" +value "registerBitNb" +) +] +mwi 0 +uid 1870,0 +) +(Instance +name "I_ALU" +duLibraryName "NanoBlaze" +duName "alu" +elements [ +(GiElement +name "aluCodeBitNb" +type "positive" +value "aluCodeBitNb" +) +(GiElement +name "dataBitNb" +type "positive" +value "registerBitNb" +) +] +mwi 0 +uid 1908,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +(EmbeddedInstance +name "eb2" +number "2" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds\\alu@and@regs\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds\\alu@and@regs\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "nanoTest.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds\\alu@and@regs" +) +(vvPair +variable "d_logical" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds\\aluAndRegs" +) +(vvPair +variable "date" +value "11.11.2019" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "11" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "aluAndRegs" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "silvan.zahno" +) +(vvPair +variable "graphical_source_date" +value "11.11.2019" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE6996" +) +(vvPair +variable "graphical_source_time" +value "07:38:44" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE6996" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "NanoBlaze" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../NanoBlaze/designcheck" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/ElN/Libraries/NanoBlaze/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "aluAndRegs" +) +(vvPair +variable "month" +value "Nov" +) +(vvPair +variable "month_long" +value "November" +) +(vvPair +variable "p" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds\\alu@and@regs\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\NanoBlaze\\hds\\aluAndRegs\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "07:38:44" +) +(vvPair +variable "unit" +value "aluAndRegs" +) +(vvPair +variable "user" +value "silvan.zahno" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 356,0 +optionalChildren [ +*1 (PortIoIn +uid 9,0 +shape (CompositeShape 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"121000,47000,121500,47000" +pts [ +"121000,47000" +"121500,47000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 167,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 168,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "124000,46300,129700,47700" +st "portOut" +blo "124000,47500" +tm "WireNameMgr" +) +) +) +*24 (Net +uid 175,0 +decl (Decl +n "portOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 17 +suid 12,0 +) +declText (MLText +uid 176,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,27600,16000,28800" +st "portOut : signed( registerBitNb-1 DOWNTO 0 )" +) +) +*25 (PortIoIn +uid 177,0 +shape (CompositeShape +uid 178,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 179,0 +sl 0 +ro 90 +xt "77500,38625,79000,39375" +) +(Line +uid 180,0 +sl 0 +ro 90 +xt "77000,39000,77500,39000" +pts [ +"77500,39000" +"77000,39000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 181,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f 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"std_ulogic" +o 12 +suid 14,0 +) +declText (MLText +uid 204,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,21600,3500,22800" +st "reset : std_ulogic" +) +) +*29 (PortIoIn +uid 205,0 +shape (CompositeShape +uid 206,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 207,0 +sl 0 +ro 90 +xt "77500,32625,79000,33375" +) +(Line +uid 208,0 +sl 0 +ro 90 +xt "77000,33000,77500,33000" +pts [ +"77500,33000" +"77000,33000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 209,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 210,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "80000,32300,90400,33700" +st "scratchpadSel" +blo "80000,33500" +tm "WireNameMgr" +) +) +) +*30 (Net +uid 217,0 +decl (Decl +n "scratchpadSel" +t "std_ulogic" +o 13 +suid 15,0 +) +declText (MLText +uid 218,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,22800,3500,24000" +st "scratchpadSel : std_ulogic" +) +) +*31 (PortIoIn +uid 233,0 +shape (CompositeShape +uid 234,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 235,0 +sl 0 +ro 90 +xt "77500,30625,79000,31375" +) +(Line +uid 236,0 +sl 0 +ro 90 +xt "77000,31000,77500,31000" +pts [ +"77500,31000" +"77000,31000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 237,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 238,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "80000,30300,85200,31700" +st "spadIn" +blo "80000,31500" +tm "WireNameMgr" +) +) +) +*32 (Net +uid 245,0 +decl (Decl +n "spadIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 14 +suid 17,0 +) +declText (MLText +uid 246,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,24000,16000,25200" +st "spadIn : signed( registerBitNb-1 DOWNTO 0 )" +) +) +*33 (PortIoOut +uid 247,0 +shape (CompositeShape +uid 248,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 249,0 +sl 0 +ro 270 +xt "121500,48625,123000,49375" +) +(Line +uid 250,0 +sl 0 +ro 270 +xt "121000,49000,121500,49000" +pts [ +"121000,49000" +"121500,49000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 251,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 252,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "124000,48300,130200,49700" +st "spadOut" +blo "124000,49500" +tm "WireNameMgr" +) +) +) +*34 (Net +uid 259,0 +decl (Decl +n "spadOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 19 +suid 18,0 +) +declText (MLText +uid 260,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,30000,16000,31200" +st "spadOut : signed( registerBitNb-1 DOWNTO 0 )" +) +) +*35 (PortIoOut +uid 261,0 +shape (CompositeShape +uid 262,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 263,0 +sl 0 +ro 90 +xt "19000,54625,20500,55375" +) +(Line +uid 264,0 +sl 0 +ro 90 +xt "20500,55000,21000,55000" +pts [ +"21000,55000" +"20500,55000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 265,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 266,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "14400,54300,18000,55700" +st "zero" +ju 2 +blo "18000,55500" +tm "WireNameMgr" +) +) +) +*36 (Net +uid 273,0 +decl (Decl +n "zero" +t "std_ulogic" +o 20 +suid 19,0 +) +declText (MLText +uid 274,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,31200,3500,32400" +st "zero : std_ulogic" +) +) +*37 (Grouping +uid 313,0 +optionalChildren [ +*38 (CommentText +uid 315,0 +shape (Rectangle +uid 316,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "96000,98000,113000,99000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 317,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "96200,98500,96200,98500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*39 (CommentText +uid 318,0 +shape (Rectangle +uid 319,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "113000,94000,117000,95000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 320,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "113200,94500,113200,94500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*40 (CommentText +uid 321,0 +shape (Rectangle +uid 322,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "96000,96000,113000,97000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 323,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "96200,96500,96200,96500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*41 (CommentText +uid 324,0 +shape (Rectangle +uid 325,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "92000,96000,96000,97000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 326,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "92200,96500,92200,96500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*42 (CommentText +uid 327,0 +shape (Rectangle +uid 328,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "113000,95000,133000,99000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 329,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "113200,95200,127300,96400" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*43 (CommentText +uid 330,0 +shape (Rectangle +uid 331,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "117000,94000,133000,95000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 332,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "117200,94500,117200,94500" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*44 (CommentText +uid 333,0 +shape (Rectangle +uid 334,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "92000,94000,113000,96000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 335,0 +va (VaSet +fg "32768,0,0" +) +xt "97350,94400,107650,95600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*45 (CommentText +uid 336,0 +shape (Rectangle +uid 337,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "92000,97000,96000,98000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 338,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "92200,97500,92200,97500" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*46 (CommentText +uid 339,0 +shape (Rectangle +uid 340,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "92000,98000,96000,99000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 341,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "92200,98500,92200,98500" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*47 (CommentText +uid 342,0 +shape (Rectangle +uid 343,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "96000,97000,113000,98000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 344,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "96200,97500,96200,97500" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 314,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "92000,94000,133000,99000" +) +oxt "14000,66000,55000,71000" +) +*48 (PortIoIn +uid 699,0 +shape (CompositeShape +uid 700,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 701,0 +sl 0 +ro 270 +xt "67000,58625,68500,59375" +) +(Line +uid 702,0 +sl 0 +ro 270 +xt "68500,59000,69000,59000" +pts [ +"68500,59000" +"69000,59000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 703,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 704,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "59700,58500,66000,59900" +st "regWrite" +ju 2 +blo "66000,59700" +tm "WireNameMgr" +) +) +) +*49 (Net +uid 711,0 +decl (Decl +n "regWrite" +t "std_ulogic" +o 10 +suid 20,0 +) +declText (MLText +uid 712,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,19200,3500,20400" +st "regWrite : std_ulogic" +) +) +*50 (Net +uid 879,0 +decl (Decl +n "opA" +t "signed" +b "(registerBitNb-1 DOWNTO 0)" +o 22 +suid 21,0 +) +declText (MLText +uid 880,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,34600,18500,35800" +st "SIGNAL opA : signed(registerBitNb-1 DOWNTO 0)" +) +) +*51 (Net +uid 887,0 +decl (Decl +n "opB" +t "signed" +b "(registerBitNb-1 DOWNTO 0)" +o 23 +suid 22,0 +) +declText (MLText +uid 888,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,35800,18500,37000" +st "SIGNAL opB : signed(registerBitNb-1 DOWNTO 0)" +) +) +*52 (Net +uid 970,0 +decl (Decl +n "aluOut" +t "signed" +b "(registerBitNb-1 DOWNTO 0)" +o 21 +suid 23,0 +) +declText (MLText +uid 971,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,33400,18500,34600" +st "SIGNAL aluOut : signed(registerBitNb-1 DOWNTO 0)" +) +) +*53 (Net +uid 1269,0 +decl (Decl +n "registerFileIn" +t "signed" +b "(registerBitNb-1 DOWNTO 0)" +o 24 +suid 25,0 +) +declText (MLText +uid 1270,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,37000,18500,38200" +st "SIGNAL registerFileIn : signed(registerBitNb-1 DOWNTO 0)" +) +) +*54 (HdlText +uid 1431,0 +optionalChildren [ +*55 (EmbeddedText +uid 1437,0 +commentText (CommentText +uid 1438,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1439,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "101000,44000,113000,52000" +) +oxt "0,0,18000,5000" +text (MLText +uid 1440,0 +va (VaSet +) +xt "101200,44200,111300,46600" +st " +portOut <= opA; +spadOut <= opA; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 1432,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "101000,43000,113000,53000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1433,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*56 (Text +uid 1434,0 +va (VaSet +font "Arial,8,1" +) +xt "101150,53000,102850,54000" +st "eb1" +blo "101150,53800" +tm "HdlTextNameMgr" +) +*57 (Text +uid 1435,0 +va (VaSet +font "Arial,8,1" +) +xt "101150,54000,101950,55000" +st "1" +blo "101150,54800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 1436,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "101250,51250,102750,52750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*58 (HdlText +uid 1441,0 +optionalChildren [ +*59 (EmbeddedText +uid 1447,0 +commentText (CommentText +uid 1448,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 1449,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "101000,30000,113000,38000" +) +oxt "0,0,18000,5000" +text (MLText +uid 1450,0 +va (VaSet +) +xt "101200,30200,112600,37400" +st " +portAddr <= resize(unsigned(registerFileIn), portAddressBitNb); +scratchpadAddr <= resize(unsigned(registerFileIn), scratchpadAddressBitNb); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 12000 +) +) +) +] +shape (Rectangle +uid 1442,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "101000,29000,113000,39000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 1443,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*60 (Text +uid 1444,0 +va (VaSet +font "Arial,8,1" +) +xt "101150,39000,102850,40000" +st "eb2" +blo "101150,39800" +tm "HdlTextNameMgr" +) +*61 (Text +uid 1445,0 +va (VaSet +font "Arial,8,1" +) +xt "101150,40000,101950,41000" +st "2" +blo "101150,40800" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 1446,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "101250,37250,102750,38750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*62 (PortIoOut +uid 1494,0 +shape (CompositeShape +uid 1495,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 1496,0 +sl 0 +ro 270 +xt "121500,34625,123000,35375" +) +(Line +uid 1497,0 +sl 0 +ro 270 +xt "121000,35000,121500,35000" +pts [ +"121000,35000" +"121500,35000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 1498,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 1499,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "122000,35300,133400,36700" +st "scratchpadAddr" +blo "122000,36500" +tm "WireNameMgr" +) +) +) +*63 (Net +uid 1506,0 +decl (Decl +n "scratchpadAddr" +t "unsigned" +b "(scratchpadAddressBitNb-1 DOWNTO 0)" +o 18 +suid 26,0 +) +declText (MLText +uid 1507,0 +va (VaSet +font "Courier New,9,0" +) +xt "-12000,28800,20500,30000" +st "scratchpadAddr : unsigned(scratchpadAddressBitNb-1 DOWNTO 0)" +) +) +*64 (SaComponent +uid 1828,0 +optionalChildren [ +*65 (CptPort +uid 1792,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1793,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52250,24625,53000,25375" +) +tg (CPTG +uid 1794,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1795,0 +va (VaSet +) +xt "54000,24500,57500,25500" +st "instrData" +blo "54000,25300" +) +) +thePort (LogicalPort +decl (Decl +n "instrData" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 6 +suid 1,0 +) +) +) +*66 (CptPort +uid 1796,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1797,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52250,26625,53000,27375" +) +tg (CPTG +uid 1798,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text 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"68000,25300" +) +) +thePort (LogicalPort +decl (Decl +n "portIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 8 +suid 4,0 +) +) +) +*69 (CptPort +uid 1808,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1809,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "69000,26625,69750,27375" +) +tg (CPTG +uid 1810,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1811,0 +va (VaSet +) +xt "64600,26500,68000,27500" +st "portInSel" +ju 2 +blo "68000,27300" +) +) +thePort (LogicalPort +decl (Decl +n "portInSel" +t "std_ulogic" +o 9 +suid 5,0 +) +) +) +*70 (CptPort +uid 1812,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1813,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "69000,36625,69750,37375" +) +tg (CPTG +uid 1814,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1815,0 +va (VaSet +) +xt "62600,36500,68000,37500" +st "registerFileIn" +ju 2 +blo "68000,37300" +) +) +thePort (LogicalPort +decl (Decl +n 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"aluBOpSelector" +blo "53700,44800" +tm "CptNameMgr" +) +*76 (Text +uid 1833,0 +va (VaSet +font "Arial,8,1" +) +xt "53700,45000,56300,46000" +st "I_bSel" +blo "53700,45800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1834,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1835,0 +text (MLText +uid 1836,0 +va (VaSet +font "Courier New,8,0" +) +xt "53000,46200,78500,47000" +st "registerBitNb = registerBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "registerBitNb" +type "positive" +value "registerBitNb" +) +] +) +viewicon (ZoomableIcon +uid 1837,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "53250,41250,54750,42750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*77 (SaComponent +uid 1870,0 +optionalChildren [ +*78 (CptPort +uid 1838,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1839,0 +ro 90 +va (VaSet +vasetType 1 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1848,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1849,0 +va (VaSet +) +xt "84000,65000,88500,66000" +st "registersIn" +blo "84000,65800" +) +) +thePort (LogicalPort +decl (Decl +n "registersIn" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 22 +suid 3,0 +) +) +) +*81 (CptPort +uid 1850,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1851,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "76250,62625,77000,63375" +) +tg (CPTG +uid 1852,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1853,0 +va (VaSet +) +xt "78000,62500,80100,63500" +st "clock" +blo "78000,63300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 5 +suid 4,0 +) +) +) +*82 (CptPort +uid 1854,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1855,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80625,50250,81375,51000" +) +tg (CPTG +uid 1856,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1857,0 +va (VaSet +) +xt "80000,52000,81700,53000" +st "opA" +ju 2 +blo "81700,52800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "opA" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 21 +suid 5,0 +) +) +) +*83 (CptPort +uid 1858,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1859,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "88625,50250,89375,51000" +) +tg (CPTG +uid 1860,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1861,0 +va (VaSet +) +xt "88000,52000,89700,53000" +st "opB" +ju 2 +blo "89700,52800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "opB" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 22 +suid 6,0 +) +) +) +*84 (CptPort +uid 1862,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1863,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "76250,58625,77000,59375" +) +tg (CPTG +uid 1864,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1865,0 +va (VaSet +) +xt "78000,58500,81400,59500" +st "regWrite" +blo "78000,59300" +) +) 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"77550,68000,82450,69000" +st "registerFile" +blo "77550,68800" +tm "CptNameMgr" +) +*88 (Text +uid 1875,0 +va (VaSet +font "Arial,8,1" +) +xt "77550,69000,80150,70000" +st "I_regs" +blo "77550,69800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1876,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1877,0 +text (MLText +uid 1878,0 +va (VaSet +font "Courier New,8,0" +) +xt "77000,70200,109500,71800" +st "registerAddressBitNb = registerAddressBitNb ( positive ) +dataBitNb = registerBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "registerAddressBitNb" +type "positive" +value "registerAddressBitNb" +) +(GiElement +name "dataBitNb" +type "positive" +value "registerBitNb" +) +] +) +viewicon (ZoomableIcon +uid 1879,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "77250,65250,78750,66750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*89 (SaComponent +uid 1908,0 +optionalChildren [ +*90 (CptPort +uid 1880,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1881,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32625,50250,33375,51000" +) +tg (CPTG +uid 1882,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1883,0 +va (VaSet +) +xt "32000,51000,33700,52000" +st "opA" +blo "32000,51800" +) +) +thePort (LogicalPort +decl (Decl +n "opA" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 1 +suid 3,0 +) +) +) +*91 (CptPort +uid 1884,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1885,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "41801,56625,42551,57375" +) +tg (CPTG +uid 1886,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 1887,0 +va (VaSet +) +xt "39401,56500,40801,57500" +st "cIn" +ju 2 +blo "40801,57300" +) +) +thePort (LogicalPort +decl (Decl +n "cIn" +t "std_ulogic" +o 2 +suid 8,0 +) +) +) +*92 (CptPort +uid 1888,0 +ps "OnEdgeStrategy" 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+xt "40625,50250,41375,51000" +) +tg (CPTG +uid 1898,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1899,0 +va (VaSet +) +xt "40000,51000,41700,52000" +st "opB" +blo "40000,51800" +) +) +thePort (LogicalPort +decl (Decl +n "opB" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 5 +suid 18,0 +) +) +) +*95 (CptPort +uid 1900,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1901,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36625,61000,37375,61750" +) +tg (CPTG +uid 1902,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1903,0 +va (VaSet +) +xt "36000,60000,38600,61000" +st "aluOut" +blo "36000,60800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "aluOut" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 6 +suid 19,0 +) +) +) +*96 (CptPort +uid 1904,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1905,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "30384,54625,31134,55375" +) +tg (CPTG +uid 1906,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1907,0 +va (VaSet +) +xt "32134,54500,34034,55500" +st "zero" +blo "32134,55300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "zero" +t "std_ulogic" +o 7 +suid 20,0 +) +) +) +] +shape (Alu +uid 1909,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "29000,51000,45000,61000" +) +oxt "31000,13000,47000,23000" +ttg (MlTextGroup +uid 1910,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*97 (Text +uid 1911,0 +va (VaSet +font "Arial,8,1" +) +xt "38950,61000,43350,62000" +st "NanoBlaze" +blo "38950,61800" +tm "BdLibraryNameMgr" +) +*98 (Text +uid 1912,0 +va (VaSet +font "Arial,8,1" +) +xt "38950,62000,40450,63000" +st "alu" +blo "38950,62800" +tm "CptNameMgr" +) +*99 (Text +uid 1913,0 +va (VaSet +font "Arial,8,1" +) +xt "38950,63000,41550,64000" +st "I_ALU" +blo "38950,63800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1914,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1915,0 +text (MLText +uid 1916,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,64000,64000,65600" +st "aluCodeBitNb = aluCodeBitNb ( positive ) +dataBitNb = registerBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "aluCodeBitNb" +type "positive" +value "aluCodeBitNb" +) +(GiElement +name "dataBitNb" +type "positive" +value "registerBitNb" +) +] +) +viewicon (ZoomableIcon +uid 1917,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "29250,59250,30750,60750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*100 (Wire +uid 15,0 +shape (OrthoPolyLine +uid 16,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "69000,55000,76250,55000" +pts [ +"69000,55000" +"76250,55000" +] +) +start &1 +end &78 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 19,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 20,0 +va (VaSet +font "Verdana,12,0" +) +xt "70000,53600,74500,55000" +st "addrA" +blo "70000,54800" +tm "WireNameMgr" +) +) +on &2 +) +*101 (Wire +uid 29,0 +shape (OrthoPolyLine +uid 30,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "69000,57000,76250,57000" +pts [ +"69000,57000" +"76250,57000" +] +) +start &3 +end &79 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 33,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 34,0 +va (VaSet +font "Verdana,12,0" +) +xt "70000,55600,74500,57000" +st "addrB" +blo "70000,56800" +tm "WireNameMgr" +) +) +on &4 +) +*102 (Wire +uid 43,0 +shape (OrthoPolyLine +uid 44,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "43617,55000,53000,55000" +pts [ +"53000,55000" +"43617,55000" +] +) +start &5 +end &93 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 47,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 48,0 +va (VaSet +font "Verdana,12,0" +) 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+) +) +dt (MLText +uid 65,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,14400,20500,15200" +st "portInSel : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "portInSel" +t "std_ulogic" +o 9 +suid 3,0 +) +) +) +*105 (CptPort +uid 66,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 67,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,38625,41000,39375" +) +tg (CPTG +uid 68,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 69,0 +va (VaSet +) +xt "42000,38500,44100,39500" +st "reset" +blo "42000,39300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 70,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,16800,20500,17600" +st "reset : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 12 +suid 4,0 +) +) +) +*106 (CptPort +uid 71,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 72,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "65000,18625,65750,19375" +) +tg (CPTG +uid 73,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 74,0 +va (VaSet +) +xt "60700,18500,64000,19500" +st "portAddr" +ju 2 +blo "64000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 75,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,20000,34500,20800" +st "portAddr : OUT unsigned (portAddressBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "portAddr" +t "unsigned" +b "(portAddressBitNb-1 DOWNTO 0)" +o 16 +suid 5,0 +) +) +) +*107 (CptPort +uid 400,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 401,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48625,12250,49375,13000" +) +tg (CPTG +uid 402,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 403,0 +va (VaSet +) +xt "48200,14000,50600,15000" +st "addrA" +blo "48200,14800" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 404,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,8000,37500,8800" +st "addrA : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +decl (Decl +n "addrA" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 1 +suid 9,0 +) +) +) +*108 (CptPort +uid 405,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 406,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52625,12250,53375,13000" +) +tg (CPTG +uid 407,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 408,0 +va (VaSet +) +xt "52400,14000,54800,15000" +st "addrB" +blo "52400,14800" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 409,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,8800,37500,9600" +st "addrB : IN unsigned ( registerAddressBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +decl (Decl +n "addrB" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 2 +suid 10,0 +) +) +) +*109 (CptPort +uid 410,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 411,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60625,12250,61375,13000" +) +tg (CPTG +uid 412,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 413,0 +va (VaSet +) +xt "59300,14000,62800,15000" +st "instrData" +blo "59300,14800" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 414,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,33000,12800" +st "instrData : IN signed ( registerBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +decl (Decl +n "instrData" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 6 +suid 11,0 +) +) +) +*110 (CptPort +uid 421,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 422,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,18625,41000,19375" +) +tg (CPTG +uid 423,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 424,0 +va (VaSet +) +xt "42000,18500,47000,19500" +st "instrDataSel" +blo "42000,19300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 425,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12800,20500,13600" +st "instrDataSel : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "instrDataSel" +t "std_ulogic" +o 7 +suid 12,0 +) +) +) +*111 (CptPort +uid 426,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 427,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,16625,41000,17375" +) +tg (CPTG +uid 428,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 429,0 +va (VaSet +) +xt "42000,16500,47900,17500" +st "registerFileSel" +blo "42000,17300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 430,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,16000,20500,16800" +st "registerFileSel : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "registerFileSel" +t "std_ulogic" +o 11 +suid 13,0 +) +) +) +*112 (CptPort +uid 431,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 432,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,22625,41000,23375" +) +tg (CPTG +uid 433,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 434,0 +va (VaSet +) +xt "42000,22500,47600,23500" +st "scratchpadSel" +blo "42000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 435,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,17600,20500,18400" +st "scratchpadSel : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "scratchpadSel" +t "std_ulogic" +o 13 +suid 14,0 +) +) +) +*113 (CptPort +uid 436,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 437,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,28625,41000,29375" +) +tg (CPTG +uid 438,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 439,0 +va (VaSet +) +xt "42000,28500,43400,29500" +st "cIn" +blo "42000,29300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 440,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,10400,20500,11200" +st "cIn : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "cIn" +t "std_ulogic" +o 4 +suid 15,0 +) +) +) +*114 (CptPort +uid 441,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 493,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,30625,41000,31375" +) +tg (CPTG +uid 443,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 444,0 +va (VaSet +) +xt "42000,30500,44000,31500" +st "cOut" +blo "42000,31300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 445,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,19200,20500,20000" +st "cOut : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "cOut" +t "std_ulogic" +o 15 +suid 16,0 +) +) +) +*115 (CptPort +uid 446,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 447,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,32625,41000,33375" +) +tg (CPTG +uid 448,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 449,0 +va (VaSet +) +xt "42000,32500,43900,33500" +st "zero" +blo "42000,33300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 450,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,23200,19500,24000" +st "zero : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "zero" +t "std_ulogic" +o 20 +suid 17,0 +) +) +) +*116 (CptPort +uid 463,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 464,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "65000,20625,65750,21375" +) +tg (CPTG +uid 465,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 466,0 +va (VaSet +) +xt "61100,20500,64000,21500" +st "portOut" +ju 2 +blo "64000,21300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 467,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,20800,33000,21600" +st "portOut : OUT signed ( registerBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "portOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 17 +suid 18,0 +) +) +) +*117 (CptPort +uid 494,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 524,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "65000,22625,65750,23375" +) +tg (CPTG +uid 496,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 497,0 +va (VaSet +) +xt "61700,22500,64000,23500" +st "portIn" +ju 2 +blo "64000,23300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 498,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,13600,33000,14400" +st "portIn : IN signed ( registerBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +decl (Decl +n "portIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 8 +suid 19,0 +) +) +) +*118 (CptPort +uid 525,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 526,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "56625,41000,57375,41750" +) +tg (CPTG +uid 527,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 528,0 +va (VaSet +) +xt "56000,39000,59200,40000" +st "spadOut" +blo "56000,39800" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 529,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,22400,33000,23200" +st "spadOut : OUT signed ( registerBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "spadOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 19 +suid 20,0 +) +) +) +*119 (CptPort +uid 530,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 531,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60625,41000,61375,41750" +) +tg (CPTG +uid 532,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 533,0 +va (VaSet +) +xt "60000,39000,62600,40000" +st "spadIn" +blo "60000,39800" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 534,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,18400,33000,19200" +st "spadIn : IN signed ( registerBitNb-1 DOWNTO 0 ) ;" +) +thePort (LogicalPort +decl (Decl +n "spadIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 14 +suid 21,0 +) +) +) +*120 (CptPort +uid 621,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 622,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "40250,24625,41000,25375" +) +tg (CPTG +uid 623,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 624,0 +va (VaSet +) +xt "42000,24500,45400,25500" +st "regWrite" +blo "42000,25300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 625,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,15200,20500,16000" +st "regWrite : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "regWrite" +t "std_ulogic" +o 10 +suid 23,0 +) +) +) +*121 (CptPort +uid 674,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 675,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "65000,26625,65750,27375" +) +tg (CPTG +uid 676,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 677,0 +va (VaSet +) +xt "57900,26500,64000,27500" +st "scratchpadAddr" +ju 2 +blo "64000,27300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 678,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,21600,37500,22400" +st "scratchpadAddr : OUT unsigned (scratchpadAddressBitNb-1 DOWNTO 0) ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "scratchpadAddr" +t "unsigned" +b "(scratchpadAddressBitNb-1 DOWNTO 0)" +o 18 +suid 24,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "41000,13000,65000,41000" +) +oxt "15000,6000,31000,20000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "41600,41000,46000,42000" +st "NanoBlaze" +blo "41600,41800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "41600,42000,46900,43000" +st "aluAndRegs" +blo "41600,42800" +) +) +gi *122 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "41000,44200,60000,49800" +st "Generic Declarations + +registerBitNb positive 8 +registerAddressBitNb positive 4 +aluCodeBitNb positive 5 +portAddressBitNb positive 8 +scratchpadAddressBitNb natural 4 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "registerBitNb" +type "positive" +value "8" +) +(GiElement +name "registerAddressBitNb" +type "positive" +value "4" +) +(GiElement +name "aluCodeBitNb" +type "positive" +value "5" +) +(GiElement +name "portAddressBitNb" +type "positive" +value "8" +) +(GiElement +name "scratchpadAddressBitNb" +type "natural" +value "4" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*123 (Grouping +uid 16,0 +optionalChildren [ +*124 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,65000,75000,66000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "58200,65500,58200,65500" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*125 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "75000,61000,79000,62000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "75200,61500,75200,61500" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*126 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "58000,63000,75000,64000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "58200,63500,58200,63500" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*127 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "54000,63000,58000,64000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "54200,63500,54200,63500" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*128 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "75000,62000,95000,66000" +) +oxt "35000,67000,55000,71000" +text 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+variable "p" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller\\symbol.sb" +) +(vvPair +variable "p_logical" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\controller\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "D:\\Labs\\ElN\\BoardTester\\Board\\ise" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "C:\\EDA\\Modelsim\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "15:59:43" +) +(vvPair +variable "unit" +value "controller" +) +(vvPair +variable "user" +value "cof" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 219,0 +optionalChildren [ +*107 (SymbolBody +uid 8,0 +optionalChildren [ +*108 (CptPort +uid 51,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 52,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,57625,62750,58375" +) +tg (CPTG +uid 53,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 54,0 +va (VaSet +) +xt "56100,57500,61000,58500" +st "branchCond" +ju 2 +blo "61000,58300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 55,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,11800,40000,12600" +st "branchCond : IN std_ulogic_vector ( branchCondBitNb-1 DOWNTO 0 ) ; +" +) +thePort (LogicalPort +decl (Decl +n "branchCond" +t "std_ulogic_vector" +b "( branchCondBitNb-1 DOWNTO 0 )" +o 1 +suid 1,0 +) +) +) +*109 (CptPort +uid 56,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 57,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,95625,62750,96375" +) +tg (CPTG +uid 58,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 59,0 +va (VaSet +) +xt "59600,95500,61000,96500" +st "cIn" +ju 2 +blo "61000,96300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 60,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,19800,21000,20600" +st "cIn : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "cIn" +t "std_ulogic" +o 10 +suid 2,0 +) +) +) +*110 (CptPort +uid 61,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 62,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,122625,46000,123375" +) +tg (CPTG +uid 63,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 64,0 +va (VaSet +) +xt "47000,122500,49100,123500" +st "clock" +blo "47000,123300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 65,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,13400,21000,14200" +st "clock : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 3 +suid 3,0 +) +) +) +*111 (CptPort +uid 66,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 67,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,97625,62750,98375" +) +tg (CPTG +uid 68,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 69,0 +va (VaSet +) +xt "59000,97500,61000,98500" +st "cOut" +ju 2 +blo "61000,98300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 70,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,12600,21000,13400" +st "cOut : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "cOut" +t "std_ulogic" +o 2 +suid 4,0 +) +) +) +*112 (CptPort +uid 71,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 72,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,9625,62750,10375" +) +tg (CPTG +uid 73,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 74,0 +va (VaSet +) +xt "58100,9500,61000,10500" +st "prevPC" +ju 2 +blo "61000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 75,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,25400,21000,26200" +st "prevPC : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "prevPC" +t "std_ulogic" +o 11 +suid 5,0 +) +) +) +*113 (CptPort +uid 76,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 77,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,120625,46000,121375" +) +tg (CPTG +uid 78,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 79,0 +va (VaSet +) +xt "47000,120500,48200,121500" +st "en" +blo "47000,121300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 80,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,14200,21000,15000" +st "en : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 4 +suid 6,0 +) +) +) +*114 (CptPort +uid 81,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 82,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,31625,62750,32375" +) +tg (CPTG +uid 83,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 84,0 +va (VaSet +) +xt "58500,31500,61000,32500" +st "incPC" +ju 2 +blo "61000,32300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 85,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,20600,21000,21400" +st "incPC : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "incPC" +t "std_ulogic" +o 12 +suid 7,0 +) +) +) +*115 (CptPort +uid 86,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 87,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,85625,62750,86375" +) +tg (CPTG +uid 88,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 89,0 +va (VaSet +) +xt "56000,85500,61000,86500" +st "instrDataSel" +ju 2 +blo "61000,86300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 90,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,21400,21000,22200" +st "instrDataSel : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "instrDataSel" +t "std_ulogic" +o 13 +suid 8,0 +) +) +) +*116 (CptPort +uid 91,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 92,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,9625,46000,10375" +) +tg (CPTG +uid 93,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 94,0 +va (VaSet +) +xt "47000,9500,48200,10500" +st "int" +blo "47000,10300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 95,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,15000,21000,15800" +st "int : IN std_uLogic ; +" +) +thePort (LogicalPort +decl (Decl +n "int" +t "std_uLogic" +o 5 +suid 9,0 +) +) +) +*117 (CptPort +uid 96,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 97,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,11625,46000,12375" +) +tg (CPTG +uid 98,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 99,0 +va (VaSet +) +xt "47000,11500,49400,12500" +st "intAck" +blo "47000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 100,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,22200,21000,23000" +st "intAck : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "intAck" +t "std_ulogic" +o 14 +suid 10,0 +) +) +) +*118 (CptPort +uid 101,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 102,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,55625,62750,56375" +) +tg (CPTG +uid 103,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 104,0 +va (VaSet +) +xt "58000,55500,61000,56500" +st "intCode" +ju 2 +blo "61000,56300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 105,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,15800,38500,16600" +st "intCode : IN std_ulogic_vector ( intCodeBitNb-1 DOWNTO 0 ) ; +" +) +thePort (LogicalPort +decl (Decl +n "intCode" +t "std_ulogic_vector" +b "( intCodeBitNb-1 DOWNTO 0 )" +o 6 +suid 11,0 +) +) +) +*119 (CptPort +uid 106,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 107,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,33625,62750,34375" +) +tg (CPTG +uid 108,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 109,0 +va (VaSet +) +xt "54500,33500,61000,34500" +st "loadInstrAddress" +ju 2 +blo "61000,34300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 110,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,23000,21000,23800" +st "loadInstrAddress : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "loadInstrAddress" +t "std_ulogic" +o 15 +suid 12,0 +) +) +) +*120 (CptPort +uid 111,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 112,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,35625,62750,36375" +) +tg (CPTG +uid 113,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 114,0 +va (VaSet +) +xt "55500,35500,61000,36500" +st "loadStoredPC" +ju 2 +blo "61000,36300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 115,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,23800,21000,24600" +st "loadStoredPC : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "loadStoredPC" +t "std_ulogic" +o 16 +suid 13,0 +) +) +) +*121 (CptPort +uid 116,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 117,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,61625,62750,62375" +) +tg (CPTG +uid 118,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 119,0 +va (VaSet +) +xt "58000,61500,61000,62500" +st "opCode" +ju 2 +blo "61000,62300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 120,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,16600,37000,17400" +st "opCode : IN std_ulogic_vector (opCodeBitNb-1 DOWNTO 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "opCode" +t "std_ulogic_vector" +b "(opCodeBitNb-1 DOWNTO 0)" +o 7 +suid 14,0 +) +) +) +*122 (CptPort +uid 121,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 122,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,87625,62750,88375" +) +tg (CPTG +uid 123,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 124,0 +va (VaSet +) +xt "57600,87500,61000,88500" +st "portInSel" +ju 2 +blo "61000,88300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 125,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,24600,21000,25400" +st "portInSel : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "portInSel" +t "std_ulogic" +o 17 +suid 15,0 +) +) +) +*123 (CptPort +uid 126,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 127,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,73625,62750,74375" +) +tg (CPTG +uid 128,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 129,0 +va (VaSet +) +xt "56500,73500,61000,74500" +st "readStrobe" +ju 2 +blo "61000,74300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 130,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,26200,21000,27000" +st "readStrobe : OUT std_uLogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "readStrobe" +t "std_uLogic" +o 18 +suid 16,0 +) +) +) +*124 (CptPort +uid 131,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 132,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,83625,62750,84375" +) +tg (CPTG +uid 133,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 134,0 +va (VaSet +) +xt "55100,83500,61000,84500" +st "registerFileSel" +ju 2 +blo "61000,84300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 135,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,27800,21000,28600" +st "registerFileSel : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "registerFileSel" +t "std_ulogic" +o 20 +suid 17,0 +) +) +) +*125 (CptPort +uid 136,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 137,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45250,124625,46000,125375" +) +tg (CPTG +uid 138,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 139,0 +va (VaSet +) +xt "47000,124500,49100,125500" +st "reset" +blo "47000,125300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 140,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,17400,21000,18200" +st "reset : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 8 +suid 18,0 +) +) +) +*126 (CptPort +uid 141,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 142,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,89625,62750,90375" +) +tg (CPTG +uid 143,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 144,0 +va (VaSet +) +xt "55400,89500,61000,90500" +st "scratchpadSel" +ju 2 +blo "61000,90300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 145,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,28600,21000,29400" +st "scratchpadSel : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "scratchpadSel" +t "std_ulogic" +o 21 +suid 19,0 +) +) +) +*127 (CptPort +uid 146,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 147,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,119625,62750,120375" +) +tg (CPTG +uid 148,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 149,0 +va (VaSet +) +xt "54700,119500,61000,120500" +st "scratchpadWrite" +ju 2 +blo "61000,120300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 150,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,29400,21000,30200" +st "scratchpadWrite : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "scratchpadWrite" +t "std_ulogic" +o 22 +suid 20,0 +) +) +) +*128 (CptPort +uid 151,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 152,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,11625,62750,12375" +) +tg (CPTG +uid 153,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 154,0 +va (VaSet +) +xt "57800,11500,61000,12500" +st "storePC" +ju 2 +blo "61000,12300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 155,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,30200,21000,31000" +st "storePC : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "storePC" +t "std_ulogic" +o 23 +suid 21,0 +) +) +) +*129 (CptPort +uid 161,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 162,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,75625,62750,76375" +) +tg (CPTG +uid 163,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 164,0 +va (VaSet +) +xt "56400,75500,61000,76500" +st "writeStrobe" +ju 2 +blo "61000,76300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 165,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,31000,20000,31800" +st "writeStrobe : OUT std_uLogic +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "writeStrobe" +t "std_uLogic" +o 24 +suid 23,0 +) +) +) +*130 (CptPort +uid 166,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 167,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,99625,62750,100375" +) +tg (CPTG +uid 168,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 169,0 +va (VaSet +) +xt "59100,99500,61000,100500" +st "zero" +ju 2 +blo "61000,100300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 170,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,19000,21000,19800" +st "zero : IN std_ulogic ; +" +) +thePort (LogicalPort +decl (Decl +n "zero" +t "std_ulogic" +o 9 +suid 24,0 +) +) +) +*131 (CptPort +uid 326,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 327,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "62000,91625,62750,92375" +) +tg (CPTG +uid 328,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 329,0 +va (VaSet +) +xt "57600,91500,61000,92500" +st "regWrite" +ju 2 +blo "61000,92300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 330,0 +va (VaSet +font "Courier New,8,0" +) +xt "0,27000,21000,27800" +st "regWrite : OUT std_ulogic ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "regWrite" +t "std_ulogic" +o 19 +suid 25,0 +) +) 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+second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "46800,129000,51200,130000" +st "controller" +blo "46800,129800" +) +) +gi *133 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "46000,131200,61500,135200" +st "Generic Declarations + +intCodeBitNb positive 5 +branchCondBitNb positive 3 +opCodeBitNb positive 5 " +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "intCodeBitNb" +type "positive" +value "5" +) +(GiElement +name "branchCondBitNb" +type "positive" +value "3" +) +(GiElement +name "opCodeBitNb" +type "positive" +value "5" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +sF 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*134 (Grouping +uid 16,0 +optionalChildren [ +*135 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt 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"13000,22000,64000,30000" +) +*12 (Net +uid 3306,0 +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 7,0 +) +declText (MLText +uid 3307,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,-1200,41000,-400" +st "reset : std_ulogic" +) +) +*13 (PortIoIn +uid 7091,0 +shape (CompositeShape +uid 7092,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 7093,0 +sl 0 +ro 270 +xt "45000,36625,46500,37375" +) +(Line +uid 7094,0 +sl 0 +ro 270 +xt "46500,37000,47000,37000" +pts [ +"46500,37000" +"47000,37000" +] +) +] +) +tg (WTG +uid 7095,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 7096,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "39900,36300,44000,37700" +st "reset" +ju 2 +blo "44000,37500" +tm "WireNameMgr" +) +s (Text +uid 7097,0 +va (VaSet +font "Verdana,12,0" +) +xt "39900,37700,39900,37700" +ju 2 +blo "39900,37700" +tm "SignalTypeMgr" +) +) +) +*14 (PortIoOut +uid 16414,0 +shape (CompositeShape +uid 16415,0 +va (VaSet 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"79500,34625,81000,35375" +) +(Line +uid 16432,0 +sl 0 +ro 270 +xt "79000,35000,79500,35000" +pts [ +"79000,35000" +"79500,35000" +] +) +] +) +tg (WTG +uid 16433,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16434,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "82000,34500,91000,35900" +st "writeStrobe" +blo "82000,35700" +tm "WireNameMgr" +) +s (Text +uid 16435,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,35900,82000,35900" +blo "82000,35900" +tm "SignalTypeMgr" +) +) +) +*17 (Net +uid 16442,0 +decl (Decl +n "writeStrobe" +t "std_uLogic" +o 10 +suid 156,0 +) +declText (MLText +uid 16443,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,2800,41000,3600" +st "writeStrobe : std_uLogic" +) +) +*18 (PortIoOut +uid 16474,0 +shape (CompositeShape +uid 16475,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16476,0 +sl 0 +ro 270 +xt "79500,26625,81000,27375" +) +(Line +uid 16477,0 +sl 0 +ro 270 +xt "79000,27000,79500,27000" +pts [ +"79000,27000" +"79500,27000" +] +) +] +) +tg (WTG +uid 16478,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16479,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "82000,26500,113400,27900" +st "dataAddress : ( addressBitNb-1 DOWNTO 0 )" +blo "82000,27700" +tm "WireNameMgr" +) +s (Text +uid 16480,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,27900,82000,27900" +blo "82000,27900" +tm "SignalTypeMgr" +) +) +) +*19 (Net +uid 16487,0 +decl (Decl +n "dataAddress" +t "unsigned" +b "( addressBitNb-1 DOWNTO 0 )" +o 6 +suid 159,0 +) +declText (MLText +uid 16488,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,-400,54000,400" +st "dataAddress : unsigned( addressBitNb-1 DOWNTO 0 )" +) +) +*20 (PortIoOut +uid 16489,0 +shape (CompositeShape +uid 16490,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16491,0 +sl 0 +ro 270 +xt "79500,28625,81000,29375" +) +(Line +uid 16492,0 +sl 0 +ro 270 +xt "79000,29000,79500,29000" +pts [ +"79000,29000" +"79500,29000" +] +) +] +) +tg (WTG +uid 16493,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16494,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "82000,28500,108800,29900" +st "dataOut : (registerBitNb-1 DOWNTO 0)" +blo "82000,29700" +tm "WireNameMgr" +) +s (Text +uid 16495,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,29900,82000,29900" +blo "82000,29900" +tm "SignalTypeMgr" +) +) +) +*21 (Net +uid 16502,0 +decl (Decl +n "dataOut" +t "std_ulogic_vector" +b "(registerBitNb-1 DOWNTO 0)" +o 7 +suid 160,0 +) +declText (MLText +uid 16503,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,400,58000,1200" +st "dataOut : std_ulogic_vector(registerBitNb-1 DOWNTO 0)" +) +) +*22 (PortIoOut +uid 16504,0 +shape (CompositeShape +uid 16505,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16506,0 +sl 0 +ro 90 +xt "45000,22625,46500,23375" +) +(Line +uid 16507,0 +sl 0 +ro 90 +xt "46500,23000,47000,23000" +pts [ +"47000,23000" +"46500,23000" +] +) +] +) +tg (WTG +uid 16508,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16509,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "39500,22300,44000,23700" +st "intAck" +ju 2 +blo "44000,23500" +tm "WireNameMgr" +) +s (Text +uid 16510,0 +va (VaSet +font "Verdana,12,0" +) +xt "39500,23700,39500,23700" +ju 2 +blo "39500,23700" +tm "SignalTypeMgr" +) +) +) +*23 (Net +uid 16517,0 +decl (Decl +n "intAck" +t "std_ulogic" +o 8 +suid 161,0 +) +declText (MLText +uid 16518,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,1200,41000,2000" +st "intAck : std_ulogic" +) +) +*24 (PortIoIn +uid 16853,0 +shape (CompositeShape +uid 16854,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16855,0 +sl 0 +ro 270 +xt "45000,34625,46500,35375" +) +(Line +uid 16856,0 +sl 0 +ro 270 +xt "46500,35000,47000,35000" +pts [ +"46500,35000" +"47000,35000" +] +) +] +) +tg (WTG +uid 16857,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16858,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "40200,34500,44000,35900" +st "clock" +ju 2 +blo "44000,35700" +tm "WireNameMgr" +) +s (Text +uid 16859,0 +va (VaSet +font "Verdana,12,0" +) +xt "40200,35900,40200,35900" +ju 2 +blo "40200,35900" +tm "SignalTypeMgr" +) +) +) +*25 (Net +uid 16866,0 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 163,0 +) +declText (MLText +uid 16867,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,-4400,41000,-3600" +st "clock : std_ulogic" +) +) +*26 (PortIoIn +uid 16868,0 +shape (CompositeShape +uid 16869,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16870,0 +sl 0 +ro 90 +xt "79500,30625,81000,31375" +) +(Line +uid 16871,0 +sl 0 +ro 90 +xt "79000,31000,79500,31000" +pts [ +"79500,31000" +"79000,31000" +] +) +] +) +tg (WTG +uid 16872,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16873,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "82000,30300,107800,31700" +st "dataIn : (registerBitNb-1 DOWNTO 0)" +blo "82000,31500" +tm "WireNameMgr" +) +s (Text +uid 16874,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,31700,82000,31700" +blo "82000,31700" +tm "SignalTypeMgr" +) +) +) +*27 (Net +uid 16881,0 +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(registerBitNb-1 DOWNTO 0)" +o 2 +suid 164,0 +) +declText (MLText +uid 16882,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,-3600,58000,-2800" +st "dataIn : std_ulogic_vector(registerBitNb-1 DOWNTO 0)" +) +) +*28 (PortIoIn +uid 16883,0 +shape (CompositeShape +uid 16884,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16885,0 +sl 0 +ro 270 +xt "45000,32625,46500,33375" +) +(Line +uid 16886,0 +sl 0 +ro 270 +xt "46500,33000,47000,33000" +pts [ +"46500,33000" +"47000,33000" +] +) +] +) +tg (WTG +uid 16887,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16888,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "41600,32500,44000,33900" +st "en" +ju 2 +blo "44000,33700" +tm "WireNameMgr" +) +s (Text +uid 16889,0 +va (VaSet +font "Verdana,12,0" +) +xt "41600,33900,41600,33900" +ju 2 +blo "41600,33900" +tm "SignalTypeMgr" +) +) +) +*29 (Net +uid 16896,0 +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 165,0 +) +declText (MLText +uid 16897,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,-2800,41000,-2000" +st "en : std_ulogic" +) +) +*30 (PortIoIn +uid 16898,0 +shape (CompositeShape +uid 16899,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16900,0 +sl 0 +ro 270 +xt "45000,20625,46500,21375" +) +(Line +uid 16901,0 +sl 0 +ro 270 +xt "46500,21000,47000,21000" +pts [ +"46500,21000" +"47000,21000" +] +) +] +) +tg (WTG +uid 16902,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16903,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "41600,20500,44000,21900" +st "int" +ju 2 +blo "44000,21700" +tm "WireNameMgr" +) +s (Text +uid 16904,0 +va (VaSet +font "Verdana,12,0" +) +xt "41600,21900,41600,21900" +ju 2 +blo "41600,21900" +tm "SignalTypeMgr" +) +) +) +*31 (Net +uid 16911,0 +decl (Decl +n "int" +t "std_uLogic" +o 4 +suid 166,0 +) +declText (MLText +uid 16912,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,-2000,41000,-1200" +st "int : std_uLogic" +) +) +*32 (Net +uid 17771,0 +decl (Decl +n "programCounter" +t "unsigned" +b "(programCounterBitNb-1 DOWNTO 0)" +o 13 +suid 182,0 +) +declText (MLText +uid 17772,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,8400,60000,9200" +st "SIGNAL programCounter : unsigned(programCounterBitNb-1 DOWNTO 0)" +) +) +*33 (Net +uid 17779,0 +decl (Decl +n "instruction" +t "std_ulogic_vector" +b "(instructionBitNb-1 DOWNTO 0)" +o 11 +suid 183,0 +) +declText (MLText +uid 17780,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,6800,63000,7600" +st "SIGNAL instruction : std_ulogic_vector(instructionBitNb-1 DOWNTO 0)" +) +) +*34 (Net +uid 18127,0 +decl (Decl +n "logic1" +t "std_ulogic" +o 12 +suid 187,0 +) +declText (MLText +uid 18128,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,7600,44500,8400" +st "SIGNAL logic1 : std_ulogic" +) +) +*35 (HdlText +uid 18129,0 +optionalChildren [ +*36 (EmbeddedText +uid 18163,0 +commentText (CommentText +uid 18164,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 18165,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "80000,6000,96000,8000" +) +oxt "0,0,18000,5000" +text (MLText +uid 18166,0 +va (VaSet +) +xt "80200,6200,88400,7400" +st " +logic1 <= '1'; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 2000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 18130,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "80000,5000,96000,9000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 18131,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*37 (Text +uid 18132,0 +va (VaSet +) +xt "80400,9000,81600,10000" +st "eb1" +blo "80400,9800" +tm "HdlTextNameMgr" +) +*38 (Text +uid 18133,0 +va (VaSet +) +xt "80400,10000,80800,11000" +st "1" +blo "80400,10800" +tm "HdlTextNumberMgr" +) +] +) +) +*39 (SaComponent +uid 19000,0 +optionalChildren [ +*40 (CptPort +uid 18980,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18981,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94250,20625,95000,21375" +) +tg (CPTG +uid 18982,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18983,0 +va (VaSet +) +xt "96000,20500,99100,21500" +st "address" +blo "96000,21300" +) +) +thePort (LogicalPort +decl (Decl +n "address" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 1 +suid 1,0 +) +) +) +*41 (CptPort +uid 18984,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18985,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94250,26625,95000,27375" +) +tg (CPTG +uid 18986,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18987,0 +va (VaSet +) +xt "96000,26500,98100,27500" +st "clock" +blo "96000,27300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 2,0 +) +) +) +*42 (CptPort +uid 18988,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18989,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "111000,20625,111750,21375" +) +tg (CPTG +uid 18990,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 18991,0 +va (VaSet +) +xt "107000,20500,110000,21500" +st "dataOut" +ju 2 +blo "110000,21300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dataOut" +t "std_ulogic_vector" +b "( dataBitNb-1 DOWNTO 0 )" +o 5 +suid 3,0 +) +) +) +*43 (CptPort +uid 18992,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18993,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94250,24625,95000,25375" +) +tg (CPTG +uid 18994,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18995,0 +va (VaSet +) +xt "96000,24500,97200,25500" +st "en" +blo "96000,25300" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 4,0 +) +) +) +*44 (CptPort +uid 18996,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 18997,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94250,28625,95000,29375" +) +tg (CPTG +uid 18998,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 18999,0 +va (VaSet +) +xt "96000,28500,98100,29500" +st "reset" +blo "96000,29300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 4 +suid 5,0 +) +) +) +] +shape (Rectangle +uid 19001,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "95000,17000,111000,31000" +) +oxt "25000,17000,41000,31000" +ttg (MlTextGroup +uid 19002,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*45 (Text +uid 19003,0 +va (VaSet +font "Arial,8,1" +) +xt "95500,31000,99900,32000" +st "NanoBlaze" +blo "95500,31800" +tm "BdLibraryNameMgr" +) +*46 (Text +uid 19004,0 +va (VaSet +font "Arial,8,1" +) +xt "95500,32000,101300,33000" +st "programRom" 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"0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16855,0 +sl 0 +ro 270 +xt "51000,163625,52500,164375" +) +(Line +uid 16856,0 +sl 0 +ro 270 +xt "52500,164000,53000,164000" +pts [ +"52500,164000" +"53000,164000" +] +) +] +) +tg (WTG +uid 16857,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16858,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "46200,163500,50000,164900" +st "clock" +ju 2 +blo "50000,164700" +tm "WireNameMgr" +) +s (Text +uid 16859,0 +va (VaSet +font "Verdana,12,0" +) +xt "46200,164900,46200,164900" +ju 2 +blo "46200,164900" +tm "SignalTypeMgr" +) +) +) +*25 (Net +uid 16866,0 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 163,0 +) +declText (MLText +uid 16867,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,-400,42500,400" +st "clock : std_ulogic" +) +) +*26 (PortIoIn +uid 16868,0 +shape (CompositeShape +uid 16869,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16870,0 +sl 0 +ro 90 +xt "157500,130625,159000,131375" +) +(Line +uid 16871,0 +sl 0 +ro 90 +xt "157000,131000,157500,131000" +pts [ +"157500,131000" +"157000,131000" +] +) +] +) +tg (WTG +uid 16872,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16873,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "160000,130300,185800,131700" +st "dataIn : (registerBitNb-1 DOWNTO 0)" +blo "160000,131500" +tm "WireNameMgr" +) +s (Text +uid 16874,0 +va (VaSet +font "Verdana,12,0" +) +xt "160000,131700,160000,131700" +blo "160000,131700" +tm "SignalTypeMgr" +) +) +) +*27 (Net +uid 16881,0 +decl (Decl +n "dataIn" +t "std_ulogic_vector" +b "(registerBitNb-1 DOWNTO 0)" +o 2 +suid 164,0 +) +declText (MLText +uid 16882,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,400,59500,1200" +st "dataIn : std_ulogic_vector(registerBitNb-1 DOWNTO 0)" +) +) +*28 (PortIoIn +uid 16883,0 +shape (CompositeShape +uid 16884,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16885,0 +sl 0 +ro 270 +xt "51000,161625,52500,162375" +) +(Line +uid 16886,0 +sl 0 +ro 270 +xt "52500,162000,53000,162000" +pts [ +"52500,162000" +"53000,162000" +] +) +] +) +tg (WTG +uid 16887,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16888,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "47600,161500,50000,162900" +st "en" +ju 2 +blo "50000,162700" +tm "WireNameMgr" +) +s (Text +uid 16889,0 +va (VaSet +font "Verdana,12,0" +) +xt "47600,162900,47600,162900" +ju 2 +blo "47600,162900" +tm "SignalTypeMgr" +) +) +) +*29 (Net +uid 16896,0 +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 165,0 +) +declText (MLText +uid 16897,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,1200,42500,2000" +st "en : std_ulogic" +) +) +*30 (PortIoIn +uid 16898,0 +shape (CompositeShape +uid 16899,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 16900,0 +sl 0 +ro 270 +xt "51000,50625,52500,51375" +) +(Line +uid 16901,0 +sl 0 +ro 270 +xt "52500,51000,53000,51000" +pts [ +"52500,51000" +"53000,51000" +] +) +] +) +tg (WTG +uid 16902,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16903,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "47600,50500,50000,51900" +st "int" +ju 2 +blo "50000,51700" +tm "WireNameMgr" +) +s (Text +uid 16904,0 +va (VaSet +font "Verdana,12,0" +) +xt "47600,51900,47600,51900" +ju 2 +blo "47600,51900" +tm "SignalTypeMgr" +) +) +) +*31 (Net +uid 16911,0 +decl (Decl +n "int" +t "std_uLogic" +o 5 +suid 166,0 +) +declText (MLText +uid 16912,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,2800,42500,3600" +st "int : std_uLogic" +) +) +*32 (Net +uid 17292,0 +decl (Decl +n "registerFileSel" +t "std_ulogic" +o 36 +suid 167,0 +) +declText (MLText +uid 17293,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,34400,46000,35200" +st "SIGNAL registerFileSel : std_ulogic" +) +) +*33 (Net +uid 17300,0 +decl (Decl +n "instrDataSel" +t "std_ulogic" +o 22 +suid 168,0 +) +declText (MLText +uid 17301,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,23200,46000,24000" +st "SIGNAL instrDataSel : std_ulogic" +) +) +*34 (Net +uid 17308,0 +decl (Decl +n "portInSel" +t "std_ulogic" +o 29 +suid 169,0 +) +declText (MLText +uid 17309,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,28800,46000,29600" +st "SIGNAL portInSel : std_ulogic" +) +) +*35 (Net +uid 17316,0 +decl (Decl +n "scratchpadSel" +t "std_ulogic" +o 37 +suid 170,0 +) +declText (MLText +uid 17317,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,35200,46000,36000" +st "SIGNAL scratchpadSel : std_ulogic" +) +) +*36 (Net +uid 17324,0 +decl (Decl +n "cIn" +t "std_ulogic" +o 17 +suid 171,0 +) +declText (MLText +uid 17325,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,19200,46000,20000" +st "SIGNAL cIn : std_ulogic" +) +) +*37 (Net +uid 17332,0 +decl (Decl +n "cOut" +t "std_ulogic" +o 18 +suid 172,0 +) +declText (MLText +uid 17333,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,20000,46000,20800" +st "SIGNAL cOut : std_ulogic" +) +) +*38 (Net +uid 17340,0 +decl (Decl +n "zero" +t "std_ulogic" +o 48 +suid 173,0 +) +declText (MLText +uid 17341,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,44000,46000,44800" +st "SIGNAL zero : std_ulogic" +) +) +*39 (Net +uid 17579,0 +decl (Decl +n "intCode" +t "std_ulogic_vector" +b "( intCodeBitNb-1 DOWNTO 0 )" +o 24 +suid 174,0 +) +declText (MLText +uid 17580,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,24800,63500,25600" +st "SIGNAL intCode : std_ulogic_vector( intCodeBitNb-1 DOWNTO 0 )" +) +) +*40 (Net +uid 17595,0 +decl (Decl +n "opCode" +t "std_ulogic_vector" +b "( opCodeBitNb-1 DOWNTO 0 )" +o 27 +suid 176,0 +) +declText (MLText +uid 17596,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,27200,63000,28000" +st "SIGNAL opCode : std_ulogic_vector( opCodeBitNb-1 DOWNTO 0 )" +) +) +*41 (Net +uid 17603,0 +decl (Decl +n "aluCode" +t "std_ulogic_vector" +b "( aluCodeBitNb-1 DOWNTO 0 )" +o 15 +suid 177,0 +) +declText (MLText +uid 17604,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,17600,63500,18400" +st "SIGNAL aluCode : std_ulogic_vector( aluCodeBitNb-1 DOWNTO 0 )" +) +) +*42 (Net +uid 17609,0 +decl (Decl +n "addrA" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 13 +suid 178,0 +) +declText (MLText +uid 17610,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,16000,63000,16800" +st "SIGNAL addrA : unsigned( registerAddressBitNb-1 DOWNTO 0 )" +) +) +*43 (Net +uid 17615,0 +decl (Decl +n "addrB" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 14 +suid 179,0 +) +declText (MLText +uid 17616,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,16800,63000,17600" +st "SIGNAL addrB : unsigned( registerAddressBitNb-1 DOWNTO 0 )" +) +) +*44 (Net +uid 17621,0 +decl (Decl +n "instrData" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 21 +suid 180,0 +) +declText (MLText +uid 17622,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,22400,58500,23200" +st "SIGNAL instrData : signed( registerBitNb-1 DOWNTO 0 )" +) +) +*45 (PortIoOut +uid 17844,0 +shape (CompositeShape +uid 17845,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 17846,0 +sl 0 +ro 270 +xt "157500,72625,159000,73375" +) +(Line +uid 17847,0 +sl 0 +ro 270 +xt "157000,73000,157500,73000" +pts [ +"157000,73000" +"157500,73000" +] +) +] +) +tg (WTG +uid 17848,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17849,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "160000,72500,196700,73900" +st "progCounter : ( programCounterBitNb-1 DOWNTO 0 )" +blo "160000,73700" +tm "WireNameMgr" +) +s (Text +uid 17850,0 +va (VaSet +font "Verdana,12,0" +) +xt "160000,73900,160000,73900" +blo "160000,73900" +tm "SignalTypeMgr" +) +) +) +*46 (PortIoIn +uid 17859,0 +shape (CompositeShape +uid 17860,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 17861,0 +sl 0 +ro 90 +xt "157500,96625,159000,97375" +) +(Line +uid 17862,0 +sl 0 +ro 90 +xt "157000,97000,157500,97000" +pts [ +"157500,97000" +"157000,97000" +] +) +] +) +tg (WTG +uid 17863,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17864,0 +va (VaSet +isHidden 1 +font "Verdana,12,0" +) +xt "160000,96300,190700,97700" +st "instruction : (instructionBitNb-1 DOWNTO 0)" +blo "160000,97500" +tm "WireNameMgr" +) +s (Text +uid 17865,0 +va (VaSet +font "Verdana,12,0" +) +xt "160000,97700,160000,97700" +blo "160000,97700" +tm "SignalTypeMgr" +) +) +) +*47 (Net +uid 17872,0 +decl (Decl +n "instruction" +t "std_ulogic_vector" +b "(instructionBitNb-1 DOWNTO 0)" +o 4 +suid 183,0 +) +declText (MLText +uid 17873,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,2000,61000,2800" +st "instruction : std_ulogic_vector(instructionBitNb-1 DOWNTO 0)" +) +) +*48 (Net +uid 18051,0 +decl (Decl +n "instrAddress" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 20 +suid 184,0 +) +declText (MLText +uid 18052,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,21600,62500,22400" +st "SIGNAL instrAddress : unsigned( programCounterBitNb-1 DOWNTO 0 )" +) +) +*49 (Net +uid 18057,0 +decl (Decl +n "progCounter" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 10 +suid 185,0 +) +declText (MLText +uid 18058,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,6800,59000,7600" +st "progCounter : unsigned( programCounterBitNb-1 DOWNTO 0 )" +) +) +*50 (Net +uid 18205,0 +decl (Decl +n "loadStoredPC" +t "std_ulogic" +o 26 +suid 186,0 +) +declText (MLText +uid 18206,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,26400,46000,27200" +st "SIGNAL loadStoredPC : std_ulogic" +) +) +*51 (Net +uid 18213,0 +decl (Decl +n "loadInstrAddress" +t "std_ulogic" +o 25 +suid 187,0 +) +declText (MLText +uid 18214,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,25600,46000,26400" +st "SIGNAL loadInstrAddress : std_ulogic" +) +) +*52 (Net +uid 18221,0 +decl (Decl +n "incPC" +t "std_ulogic" +o 19 +suid 188,0 +) +declText (MLText +uid 18222,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,20800,46000,21600" +st "SIGNAL incPC : std_ulogic" +) +) +*53 (Net +uid 18274,0 +decl (Decl +n "storedProgCounter" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 46 +suid 189,0 +) +declText (MLText +uid 18275,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,42400,62500,43200" +st "SIGNAL storedProgCounter : unsigned( programCounterBitNb-1 DOWNTO 0 )" +) +) +*54 (Net +uid 18288,0 +decl (Decl +n "storePC" +t "std_ulogic" +o 45 +suid 191,0 +) +declText (MLText +uid 18289,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,41600,46000,42400" +st "SIGNAL storePC : std_ulogic" +) +) +*55 (HdlText +uid 18573,0 +optionalChildren [ +*56 (EmbeddedText +uid 18602,0 +commentText (CommentText +uid 18603,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 18604,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "133000,102000,149000,110000" +) +oxt "0,0,18000,5000" +text (MLText +uid 18605,0 +va (VaSet +) +xt "133200,102200,148300,107000" +st " +dataAddress <= portInstrAddress when portIndexedSel = '0' else portRegAddress; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 18574,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "133000,101000,149000,111000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 18575,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*57 (Text +uid 18576,0 +va (VaSet +) +xt "133400,111000,134600,112000" +st "eb1" +blo "133400,111800" +tm "HdlTextNameMgr" +) +*58 (Text +uid 18577,0 +va (VaSet +) +xt "133400,112000,133800,113000" +st "1" +blo "133400,112800" +tm "HdlTextNumberMgr" +) +] +) +) +*59 (Net +uid 18630,0 +decl (Decl +n "scratchpadWrite" +t "std_ulogic" +o 38 +suid 200,0 +) +declText (MLText +uid 18631,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,36000,46000,36800" +st "SIGNAL scratchpadWrite : std_ulogic" +) +) +*60 (Net +uid 18872,0 +decl (Decl +n "regWrite" +t "std_ulogic" +o 35 +suid 203,0 +) +declText (MLText +uid 18873,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,33600,46000,34400" +st "SIGNAL regWrite : std_ulogic" +) +) +*61 (HdlText +uid 18991,0 +optionalChildren [ +*62 (EmbeddedText +uid 18996,0 +commentText (CommentText +uid 18997,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 18998,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "133000,126000,149000,134000" +) +oxt "0,0,18000,5000" +text (MLText +uid 18999,0 +va (VaSet +) +xt "133200,126200,149000,131000" +st " +dataOut <= std_ulogic_vector(portOut); +portIn <= signed(dataIn); +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 18992,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "133000,125000,149000,135000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 18993,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*63 (Text +uid 18994,0 +va (VaSet +) +xt "133400,135000,135000,136000" +st "eb2" +blo "133400,135800" +tm "HdlTextNameMgr" +) +*64 (Text +uid 18995,0 +va (VaSet +) +xt "133400,136000,134200,137000" +st "2" +blo "133400,136800" +tm "HdlTextNumberMgr" +) +] +) +) +*65 (Net +uid 19000,0 +decl (Decl +n "portOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 32 +suid 204,0 +) +declText (MLText +uid 19001,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,31200,58500,32000" +st "SIGNAL portOut : signed( registerBitNb-1 DOWNTO 0 )" +) +) +*66 (Net +uid 19008,0 +decl (Decl +n "portIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 28 +suid 205,0 +) +declText (MLText +uid 19009,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,28000,58500,28800" +st "SIGNAL portIn : signed( registerBitNb-1 DOWNTO 0 )" +) +) +*67 (Net +uid 19792,0 +decl (Decl +n "spadIn" +t "signed" +b "(registerBitNb-1 DOWNTO 0)" +o 40 +suid 207,0 +) +declText (MLText +uid 19793,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,37600,57500,38400" +st "SIGNAL spadIn : signed(registerBitNb-1 DOWNTO 0)" +) +) +*68 (Net +uid 19794,0 +decl (Decl +n "spadOut" +t "signed" +b "(registerBitNb-1 DOWNTO 0)" +o 43 +suid 208,0 +) +declText (MLText +uid 19795,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,40000,57500,40800" +st "SIGNAL spadOut : signed(registerBitNb-1 DOWNTO 0)" +) +) +*69 (Net +uid 19800,0 +decl (Decl +n "portIndexedSel" +t "std_ulogic" +o 30 +suid 209,0 +) +declText (MLText +uid 19801,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,29600,46000,30400" +st "SIGNAL portIndexedSel : std_ulogic" +) +) +*70 (Net +uid 19804,0 +decl (Decl +n "portInstrAddress" +t "unsigned" +b "(addressBitNb-1 DOWNTO 0)" +o 31 +suid 210,0 +) +declText (MLText +uid 19805,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,30400,58000,31200" +st "SIGNAL portInstrAddress : unsigned(addressBitNb-1 DOWNTO 0)" +) +) +*71 (Net +uid 19812,0 +decl (Decl +n "spadInstrAddress" +t "unsigned" +b "(scratchpadAddressBitNb-1 DOWNTO 0)" +o 42 +suid 212,0 +) +declText (MLText +uid 19813,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,39200,63000,40000" +st "SIGNAL spadInstrAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0)" +) +) +*72 (Net +uid 19966,0 +decl (Decl +n "spadIndexedSel" +t "std_ulogic" +o 41 +suid 213,0 +) +declText (MLText +uid 19967,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,38400,46000,39200" +st "SIGNAL spadIndexedSel : std_ulogic" +) +) +*73 (HdlText +uid 19974,0 +optionalChildren [ +*74 (EmbeddedText +uid 19979,0 +commentText (CommentText +uid 19980,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 19981,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "133000,144000,149000,152000" +) +oxt "0,0,18000,5000" +text (MLText +uid 19982,0 +va (VaSet +) +xt "133200,144200,148700,149000" +st " +spadAddress <= spadInstrAddress when spadIndexedSel = '0' else spadRegAddress; +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 8000 +visibleWidth 16000 +) +) +) +] +shape (Rectangle +uid 19975,0 +va (VaSet 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"SIGNAL portRegAddress : unsigned(addressBitNb-1 DOWNTO 0)" +) +) +*79 (Net +uid 20262,0 +decl (Decl +n "spadAddress" +t "unsigned" +b "(scratchpadAddressBitNb-1 DOWNTO 0)" +o 39 +suid 219,0 +) +declText (MLText +uid 20263,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,36800,63000,37600" +st "SIGNAL spadAddress : unsigned(scratchpadAddressBitNb-1 DOWNTO 0)" +) +) +*80 (SaComponent +uid 21353,0 +optionalChildren [ +*81 (CptPort +uid 21321,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21322,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,80625,93000,81375" +) +tg (CPTG +uid 21323,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21324,0 +va (VaSet +) +xt "94000,80500,96100,81500" +st "clock" +blo "94000,81300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 3 +suid 17,0 +) +) +) +*82 (CptPort +uid 21325,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21326,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,72625,117750,73375" +) +tg (CPTG +uid 21327,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21328,0 +va (VaSet +) +xt "110900,72500,116000,73500" +st "progCounter" +ju 2 +blo "116000,73300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "progCounter" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 2 +suid 18,0 +) +) +) +*83 (CptPort +uid 21329,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21330,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "104625,68250,105375,69000" +) +tg (CPTG +uid 21331,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 21332,0 +va (VaSet +) +xt "99800,70000,107100,71000" +st "storedProgCounter" +ju 2 +blo "107100,70800" +) +) +thePort (LogicalPort +decl (Decl +n "storedProgCounter" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 1 +suid 24,0 +) +) +) +*84 (CptPort +uid 21333,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21334,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "104625,85000,105375,85750" +) +tg (CPTG +uid 21335,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21336,0 +va (VaSet +) +xt "101000,83000,106100,84000" +st "instrAddress" +blo "101000,83800" +) +) +thePort (LogicalPort +decl (Decl +n "instrAddress" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 4 +suid 27,0 +) +) +) +*85 (CptPort +uid 21337,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21338,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,82625,93000,83375" +) +tg (CPTG +uid 21339,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21340,0 +va (VaSet +) +xt "94000,82500,96100,83500" +st "reset" +blo "94000,83300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 28,0 +) +) +) +*86 (CptPort +uid 21341,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21342,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,72625,93000,73375" +) +tg (CPTG +uid 21343,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21344,0 +va (VaSet +) +xt "94000,72500,96500,73500" +st "incPC" +blo "94000,73300" +) +) +thePort (LogicalPort +decl (Decl +n "incPC" +t "std_ulogic" +o 6 +suid 29,0 +) +) +) +*87 (CptPort +uid 21345,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21346,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,74625,93000,75375" +) +tg (CPTG +uid 21347,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21348,0 +va (VaSet +) +xt "94000,74500,100500,75500" +st "loadInstrAddress" +blo "94000,75300" +) +) +thePort (LogicalPort +decl (Decl +n "loadInstrAddress" +t "std_ulogic" +o 7 +suid 30,0 +) +) +) +*88 (CptPort +uid 21349,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 21350,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,76625,93000,77375" +) +tg (CPTG +uid 21351,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 21352,0 +va (VaSet +) +xt "94000,76500,99500,77500" +st "loadStoredPC" +blo "94000,77300" +) +) +thePort (LogicalPort +decl (Decl +n "loadStoredPC" +t "std_ulogic" +o 8 +suid 31,0 +) +) +) +] +shape (Rectangle +uid 21354,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "93000,69000,117000,85000" +) +oxt "41000,25000,65000,41000" +ttg (MlTextGroup +uid 21355,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*89 (Text +uid 21356,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,85000,97900,86000" +st "nanoBlaze" +blo "93600,85800" +tm "BdLibraryNameMgr" +) +*90 (Text +uid 21357,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,86000,100700,87000" +st "programCounter" +blo "93600,86800" +tm "CptNameMgr" +) +*91 (Text +uid 21358,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,87000,95700,88000" +st "I_PC" +blo "93600,87800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 21359,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 21360,0 +text (MLText +uid 21361,0 +va (VaSet +font "Courier New,8,0" +) +xt "93000,88200,124500,89000" +st "programCounterBitNb = programCounterBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "programCounterBitNb" +type "positive" +value "programCounterBitNb" +) +] +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*92 (Net +uid 21553,0 +decl (Decl +n "branchCond" +t "std_ulogic_vector" +b "(branchCondBitNb-1 DOWNTO 0)" +o 16 +suid 220,0 +) +declText (MLText +uid 21554,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,18400,64000,19200" +st "SIGNAL branchCond : std_ulogic_vector(branchCondBitNb-1 DOWNTO 0)" +) +) +*93 (Net +uid 21555,0 +decl (Decl +n "twoRegInstr" +t "std_ulogic" +o 47 +suid 221,0 +) +declText (MLText +uid 21556,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,43200,46000,44000" +st "SIGNAL twoRegInstr : std_ulogic" +) +) +*94 (SaComponent +uid 22103,0 +optionalChildren [ +*95 (CptPort +uid 22003,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22004,0 +ro 270 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"60250,163625,61000,164375" +) +tg (CPTG +uid 22013,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22014,0 +va (VaSet +) +xt "62000,163500,64100,164500" +st "clock" +blo "62000,164300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 3 +suid 3,0 +) +) +) +*98 (CptPort +uid 22015,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22016,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,138625,77750,139375" +) +tg (CPTG +uid 22017,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22018,0 +va (VaSet +) +xt "74000,138500,76000,139500" +st "cOut" +ju 2 +blo "76000,139300" +) +) +thePort (LogicalPort +decl (Decl +n "cOut" +t "std_ulogic" +o 2 +suid 4,0 +) +) +) +*99 (CptPort +uid 22019,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22020,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,50625,77750,51375" +) +tg (CPTG +uid 22021,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22022,0 +va (VaSet +) +xt "73100,50500,76000,51500" +st "prevPC" +ju 2 +blo "76000,51300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "prevPC" +t "std_ulogic" +o 11 +suid 5,0 +) +) +) +*100 (CptPort +uid 22023,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22024,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60250,161625,61000,162375" +) +tg (CPTG +uid 22025,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22026,0 +va (VaSet +) +xt "62000,161500,63200,162500" +st "en" +blo "62000,162300" +) +) +thePort (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 4 +suid 6,0 +) +) +) +*101 (CptPort +uid 22027,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22028,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "77000,72625,77750,73375" +) +tg (CPTG +uid 22029,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22030,0 +va (VaSet +) +xt "73500,72500,76000,73500" +st "incPC" +ju 2 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22145,0 +decl (Decl +n "prevPC" +t "std_ulogic" +o 34 +suid 222,0 +) +declText (MLText +uid 22146,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,32800,46000,33600" +st "SIGNAL prevPC : std_ulogic" +) +) +*134 (Frame +uid 22468,0 +shape (RectFrame +uid 22469,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "28160,28160,28160" +lineStyle 2 +lineWidth 3 +) +xt "87000,155000,119000,174000" +) +title (TextAssociate +uid 22470,0 +ps "TopLeftStrategy" +text (MLText +uid 22471,0 +va (VaSet +) +xt "87350,153500,119850,154700" +st "g_scratchpad: IF scratchpadAddressBitNb > 0 GENERATE" +tm "FrameTitleTextMgr" +) +) +seqNum (FrameSequenceNumber +uid 22472,0 +ps "TopLeftStrategy" +shape (Rectangle +uid 22473,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +) +xt "87500,155200,88500,156800" +) +num (Text +uid 22474,0 +va (VaSet +) +xt "87800,155500,88200,156500" +st "1" +blo "87800,156300" +tm "FrameSeqNumMgr" +) +) +decls (MlTextGroup +uid 22475,0 +ps "BottomRightOffsetStrategy" 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"CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22548,0 +va (VaSet +) +xt "95300,122000,98500,123000" +st "aluCode" +blo "95300,122800" +) +) +thePort (LogicalPort +decl (Decl +n "aluCode" +t "std_ulogic_vector" +b "( aluCodeBitNb-1 DOWNTO 0 )" +o 3 +suid 2,0 +) +) +) +*140 (CptPort +uid 22549,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22550,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,128625,93000,129375" +) +tg (CPTG +uid 22551,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22552,0 +va (VaSet +) +xt "94000,128500,97400,129500" +st "portInSel" +blo "94000,129300" +) +) +thePort (LogicalPort +decl (Decl +n "portInSel" +t "std_ulogic" +o 9 +suid 3,0 +) +) +) +*141 (CptPort +uid 22553,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22554,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,146625,93000,147375" +) +tg (CPTG +uid 22555,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22556,0 +va (VaSet +) +xt "94000,146500,96100,147500" +st "reset" +blo "94000,147300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 12 +suid 4,0 +) +) +) +*142 (CptPort +uid 22557,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22558,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,126625,117750,127375" +) +tg (CPTG +uid 22559,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22560,0 +va (VaSet +) +xt "112700,126500,116000,127500" +st "portAddr" +ju 2 +blo "116000,127300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "portAddr" +t "unsigned" +b "(portAddressBitNb-1 DOWNTO 0)" +o 16 +suid 5,0 +) +) +) +*143 (CptPort +uid 22561,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22562,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "100625,120250,101375,121000" +) +tg (CPTG +uid 22563,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22564,0 +va (VaSet +) +xt "100200,122000,102600,123000" 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"111300,122800" +) +) +thePort (LogicalPort +decl (Decl +n "instrData" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 6 +suid 11,0 +) +) +) +*146 (CptPort +uid 22573,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22574,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,126625,93000,127375" +) +tg (CPTG +uid 22575,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22576,0 +va (VaSet +) +xt "94000,126500,99000,127500" +st "instrDataSel" +blo "94000,127300" +) +) +thePort (LogicalPort +decl (Decl +n "instrDataSel" +t "std_ulogic" +o 7 +suid 12,0 +) +) +) +*147 (CptPort +uid 22577,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22578,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,124625,93000,125375" +) +tg (CPTG +uid 22579,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22580,0 +va (VaSet +) +xt "94000,124500,99900,125500" +st "registerFileSel" +blo "94000,125300" +) +) +thePort (LogicalPort +decl (Decl +n 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"117000,128625,117750,129375" +) +tg (CPTG +uid 22599,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22600,0 +va (VaSet +) +xt "113100,128500,116000,129500" +st "portOut" +ju 2 +blo "116000,129300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "portOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 17 +suid 18,0 +) +) +) +*153 (CptPort +uid 22601,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22602,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,130625,117750,131375" +) +tg (CPTG +uid 22603,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22604,0 +va (VaSet +) +xt "113700,130500,116000,131500" +st "portIn" +ju 2 +blo "116000,131300" +) +) +thePort (LogicalPort +decl (Decl +n "portIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 8 +suid 19,0 +) +) +) +*154 (CptPort +uid 22605,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22606,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "108625,149000,109375,149750" +) +tg (CPTG +uid 22607,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22608,0 +va (VaSet +) +xt "108000,147000,111200,148000" +st "spadOut" +blo "108000,147800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "spadOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 19 +suid 20,0 +) +) +) +*155 (CptPort +uid 22609,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22610,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "112625,149000,113375,149750" +) +tg (CPTG +uid 22611,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22612,0 +va (VaSet +) +xt "112000,147000,114600,148000" +st "spadIn" +blo "112000,147800" +) +) +thePort (LogicalPort +decl (Decl +n "spadIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 14 +suid 21,0 +) +) +) +*156 (CptPort +uid 22613,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22614,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,132625,93000,133375" +) +tg (CPTG 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22623,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*158 (Text +uid 22624,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,149000,98000,150000" +st "NanoBlaze" +blo "93600,149800" +tm "BdLibraryNameMgr" +) +*159 (Text +uid 22625,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,150000,98900,151000" +st "aluAndRegs" +blo "93600,150800" +tm "CptNameMgr" +) +*160 (Text +uid 22626,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,151000,95700,152000" +st "I_alu" +blo "93600,151800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 22627,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 22628,0 +text (MLText +uid 22629,0 +va (VaSet +font "Courier New,8,0" +) +xt "93000,152200,127500,156200" +st "registerBitNb = registerBitNb ( positive ) +registerAddressBitNb = registerAddressBitNb ( positive ) +aluCodeBitNb = aluCodeBitNb ( positive ) +portAddressBitNb = addressBitNb ( positive ) +scratchpadAddressBitNb = scratchpadAddressBitNb ( natural ) " +) +header "" +) +elements [ +(GiElement +name "registerBitNb" +type "positive" +value "registerBitNb" +) +(GiElement +name "registerAddressBitNb" +type "positive" +value "registerAddressBitNb" +) +(GiElement +name "aluCodeBitNb" +type "positive" +value "aluCodeBitNb" +) +(GiElement +name "portAddressBitNb" +type "positive" +value "addressBitNb" +) +(GiElement +name "scratchpadAddressBitNb" +type "natural" +value "scratchpadAddressBitNb" +) +] +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*161 (SaComponent +uid 22654,0 +optionalChildren [ +*162 (CptPort +uid 22630,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22631,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,164625,93000,165375" +) +tg (CPTG +uid 22632,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22633,0 +va (VaSet +) +xt "94000,164500,96100,165500" +st "clock" +blo "94000,165300" +) +) +thePort (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*163 (CptPort +uid 22634,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22635,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,166625,93000,167375" +) +tg (CPTG +uid 22636,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22637,0 +va (VaSet +) +xt "94000,166500,96100,167500" +st "reset" +blo "94000,167300" +) +) +thePort (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 2 +suid 4,0 +) +) +) +*164 (CptPort +uid 22638,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22639,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "112625,156250,113375,157000" +) +tg (CPTG +uid 22640,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22641,0 +va (VaSet +) +xt "112000,158000,115000,159000" +st "dataOut" +blo "112000,158800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dataOut" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 6 +suid 20,0 +) +) +) +*165 (CptPort +uid 22642,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22643,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "108625,156250,109375,157000" +) +tg (CPTG +uid 22644,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22645,0 +va (VaSet +) +xt "108000,158000,110400,159000" +st "dataIn" +blo "108000,158800" +) +) +thePort (LogicalPort +decl (Decl +n "dataIn" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 5 +suid 21,0 +) +) +) +*166 (CptPort +uid 22646,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22647,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,160625,117750,161375" +) +tg (CPTG +uid 22648,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22649,0 +va (VaSet +) +xt "114100,160500,116000,161500" +st "addr" +ju 2 +blo "116000,161300" +) +) +thePort (LogicalPort +decl (Decl +n "addr" +t "unsigned" +b "( spadAddressBitNb-1 DOWNTO 0 )" +o 4 +suid 22,0 +) +) +) +*167 (CptPort +uid 22650,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22651,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,160625,93000,161375" +) +tg (CPTG +uid 22652,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22653,0 +va (VaSet +) +xt "94000,160500,96000,161500" +st "write" +blo "94000,161300" +) +) +thePort (LogicalPort +decl (Decl +n "write" +t "std_ulogic" +o 3 +suid 23,0 +) +) +) +] +shape (Rectangle +uid 22655,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "93000,157000,117000,169000" +) +oxt "38000,25000,62000,37000" +ttg (MlTextGroup +uid 22656,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*168 (Text +uid 22657,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,169000,98000,170000" +st "NanoBlaze" +blo "93600,169800" +tm "BdLibraryNameMgr" +) +*169 (Text +uid 22658,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,170000,98500,171000" +st "scratchpad" +blo "93600,170800" +tm "CptNameMgr" +) +*170 (Text +uid 22659,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,171000,96400,172000" +st "I_sPad" +blo "93600,171800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 22660,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 22661,0 +text (MLText +uid 22662,0 +va (VaSet +font "Courier New,8,0" +) +xt "93000,172200,124500,173800" +st "registerBitNb = registerBitNb ( positive ) +spadAddressBitNb = scratchpadAddressBitNb ( natural ) " +) +header "" +) +elements [ +(GiElement +name "registerBitNb" +type "positive" +value "registerBitNb" +) +(GiElement +name "spadAddressBitNb" +type "natural" +value "scratchpadAddressBitNb" +) +] +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*171 (SaComponent +uid 22782,0 +optionalChildren [ +*172 (CptPort +uid 22726,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22727,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "96625,109000,97375,109750" +) +tg (CPTG +uid 22728,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22729,0 +va (VaSet +) +xt "95000,107000,98200,108000" +st "aluCode" +blo "95000,107800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "aluCode" +t "std_ulogic_vector" +b "( aluCodeBitNb-1 DOWNTO 0 )" +o 4 +suid 2,0 +) +) +) +*173 (CptPort +uid 22730,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22731,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,98625,117750,99375" +) +tg (CPTG +uid 22732,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22733,0 +va (VaSet +) +xt "110300,98500,116000,99500" +st "portIndexedSel" +ju 2 +blo "116000,99300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "portIndexedSel" +t "std_ulogic" +o 6 +suid 5,0 +) +) +) +*174 (CptPort +uid 22734,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22735,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "100625,109000,101375,109750" +) +tg (CPTG +uid 22736,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22737,0 +va (VaSet +) +xt "100000,107000,102400,108000" +st "addrA" +blo "100000,107800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrA" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 2 +suid 9,0 +) +) +) +*175 (CptPort +uid 22738,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22739,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "104625,109000,105375,109750" +) +tg (CPTG +uid 22740,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22741,0 +va (VaSet +) +xt "104000,107000,106400,108000" +st "addrB" +blo "104000,107800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "addrB" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 3 +suid 10,0 +) +) +) +*176 (CptPort +uid 22742,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22743,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "112625,109000,113375,109750" +) +tg (CPTG +uid 22744,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22745,0 +va (VaSet +) +xt "111000,107000,114500,108000" +st "instrData" +blo "111000,107800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "instrData" +t "signed" +b "( registerBitNb-1 DOWNTO 0 )" +o 8 +suid 11,0 +) +) +) +*177 (CptPort +uid 22746,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22747,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,102625,93000,103375" +) +tg (CPTG +uid 22748,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22749,0 +va (VaSet +) +xt "94000,102500,97000,103500" +st "opCode" +blo "94000,103300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "opCode" +t "std_ulogic_vector" +b "( opCodeBitNb-1 DOWNTO 0 )" +o 10 +suid 16,0 +) +) +) +*178 (CptPort +uid 22750,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22751,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,100625,117750,101375" +) +tg (CPTG +uid 22752,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22753,0 +va (VaSet +) +xt "111100,100500,116000,101500" +st "portAddress" +ju 2 +blo "116000,101300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "portAddress" +t "unsigned" +b "(portAddressBitNb-1 DOWNTO 0)" +o 11 +suid 18,0 +) +) +) +*179 (CptPort +uid 22754,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22755,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,96625,117750,97375" +) +tg (CPTG +uid 22756,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22757,0 +va (VaSet +) +xt "111700,96500,116000,97500" +st "instruction" +ju 2 +blo "116000,97300" +) +) +thePort (LogicalPort +decl (Decl +n "instruction" +t "std_ulogic_vector" +b "( instructionBitNb-1 DOWNTO 0 )" +o 1 +suid 19,0 +) +) +) +*180 (CptPort +uid 22758,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22759,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "104625,92250,105375,93000" +) +tg (CPTG +uid 22760,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22761,0 +va (VaSet +) +xt "102000,94000,107100,95000" +st "instrAddress" +blo "102000,94800" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "instrAddress" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 7 +suid 24,0 +) +) +) +*181 (CptPort +uid 22762,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22763,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,98625,93000,99375" +) +tg (CPTG +uid 22764,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22765,0 +va (VaSet +) +xt "94000,98500,98900,99500" +st "branchCond" +blo "94000,99300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "branchCond" +t "std_ulogic_vector" +b "(branchCondBitNb-1 DOWNTO 0)" +o 5 +suid 25,0 +) +) +) +*182 (CptPort +uid 22766,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22767,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,96625,93000,97375" +) +tg (CPTG +uid 22768,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22769,0 +va (VaSet +) +xt "94000,96500,97000,97500" +st "intCode" +blo "94000,97300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "intCode" +t "std_ulogic_vector" +b "( intCodeBitNb-1 DOWNTO 0 )" +o 9 +suid 26,0 +) +) +) +*183 (CptPort +uid 22770,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22771,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,104625,117750,105375" +) +tg (CPTG +uid 22772,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22773,0 +va (VaSet +) +xt "110800,104500,116000,105500" +st "spadAddress" +ju 2 +blo "116000,105300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "spadAddress" +t "unsigned" +b "( spadAddressBitNb-1 DOWNTO 0 )" +o 12 +suid 28,0 +) +) +) +*184 (CptPort +uid 22774,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22775,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "117000,102625,117750,103375" +) +tg (CPTG +uid 22776,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 22777,0 +va (VaSet +) +xt "110000,102500,116000,103500" +st "spadIndexedSel" +ju 2 +blo "116000,103300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "spadIndexedSel" +t "std_ulogic" +o 13 +suid 29,0 +) +) +) +*185 (CptPort +uid 22778,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 22779,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92250,104625,93000,105375" +) +tg (CPTG +uid 22780,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 22781,0 +va (VaSet +) +xt "94000,104500,98900,105500" +st "twoRegInstr" +blo "94000,105300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "twoRegInstr" +t "std_ulogic" +o 14 +suid 30,0 +) +) +) +] +shape (Rectangle +uid 22783,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "93000,93000,117000,109000" +) +oxt "41000,25000,65000,41000" +ttg (MlTextGroup +uid 22784,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*186 (Text +uid 22785,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,109000,98000,110000" +st "NanoBlaze" +blo "93600,109800" +tm "BdLibraryNameMgr" +) +*187 (Text +uid 22786,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,110000,101600,111000" +st "instructionDecoder" +blo "93600,110800" +tm "CptNameMgr" +) +*188 (Text +uid 22787,0 +va (VaSet +font "Arial,8,1" +) +xt "93600,111000,96300,112000" +st "I_instr" +blo "93600,111800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 22788,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 22789,0 +text (MLText +uid 22790,0 +va (VaSet +font "Courier New,8,0" +) +xt "93000,112200,126500,120200" +st "registerBitNb = registerBitNb ( positive ) +registerAddressBitNb = registerAddressBitNb ( positive ) +aluCodeBitNb = aluCodeBitNb ( positive ) +instructionBitNb = instructionBitNb ( positive ) +programCounterBitNb = programCounterBitNb ( positive ) +opCodeBitNb = opCodeBitNb ( positive ) +branchCondBitNb = branchCondBitNb ( positive ) +intCodeBitNb = 5 ( positive ) +spadAddressBitNb = scratchpadAddressBitNb ( natural ) +portAddressBitNb = addressBitNb ( positive ) " +) +header "" +) +elements [ +(GiElement +name "registerBitNb" +type "positive" +value "registerBitNb" +) +(GiElement +name "registerAddressBitNb" +type "positive" +value "registerAddressBitNb" +) +(GiElement +name "aluCodeBitNb" +type "positive" +value "aluCodeBitNb" +) +(GiElement +name "instructionBitNb" +type "positive" +value "instructionBitNb" +) +(GiElement +name "programCounterBitNb" +type "positive" +value "programCounterBitNb" +) +(GiElement +name "opCodeBitNb" +type "positive" +value "opCodeBitNb" +) +(GiElement +name "branchCondBitNb" +type "positive" +value "branchCondBitNb" +) +(GiElement +name "intCodeBitNb" +type "positive" +value "5" +) +(GiElement +name "spadAddressBitNb" +type "natural" +value "scratchpadAddressBitNb" +) +(GiElement +name "portAddressBitNb" +type "positive" +value "addressBitNb" +) +] +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*189 (HdlText +uid 22854,0 +optionalChildren [ +*190 (EmbeddedText +uid 22859,0 +commentText (CommentText +uid 22860,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 22861,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "132000,-5000,156000,9000" +) +oxt "0,0,18000,5000" +text (MLText +uid 22862,0 +va (VaSet +) +xt "132200,-4800,156100,8400" +st " +-- pragma translate_off + +process(instruction) + + constant bitsPerHexDigit : positive := 4; + + function pad(inString : string; outLength : positive) return string is + variable outString : string(1 to outLength); + begin + outString := (others => ' '); + outString(inString'range) := inString; + return outString; + end function pad; + + function hexDigitNb(bitNb : positive) return positive is + begin + return (bitNb-1)/bitsPerHexDigit+1; + end function hexDigitNb; + + function to01(nineValued : unsigned) return unsigned is + variable twoValued : unsigned(nineValued'range); + begin + twoValued := (others => '0'); + for index in nineValued'range loop + if (nineValued(index) = '1') or (nineValued(index) = 'H') then + twoValued(index) := '1'; + end if; + end loop; + return twoValued; + end function to01; + + variable opCode : unsigned(1+opCodeBitNb-1 downto 0); + variable destRegister : unsigned(registerAddressBitNb-1 downto 0); + variable destRegisterString : string(1 to 1+hexDigitNb(registerAddressBitNb)); + variable sourceRegister : unsigned(registerAddressBitNb-1 downto 0); + variable sourceRegisterString : string(1 to 1+hexDigitNb(registerAddressBitNb)); + variable sourceConstant : unsigned(registerBitNb-1 downto 0); + variable sourceConstantString : string(1 to hexDigitNb(registerBitNb)); + variable branchAddress : unsigned(programCounterBitNb-1 downto 0); + variable branchAddressString : string(1 to hexDigitNb(programCounterBitNb)); + variable branchKind : unsigned(1 downto 0); + variable shRotCin : unsigned(2 downto 0); + variable shRotDir: std_ulogic; + + function toHexDigit(binary : unsigned(bitsPerHexDigit-1 downto 0)) return character is + begin + if binary <= 9 then + return character'val(character'pos('0') + to_integer(to01(binary))); + else + return character'val(character'pos('A') + to_integer(to01(binary)) - 10); + end if; + end function toHexDigit; + + function toHexString(binary : unsigned) return string is + variable hexString : string(1 to hexDigitNb(binary'length)); + begin + for index in hexString'high-1 downto 0 loop + hexString(hexString'high-index) := toHexDigit( + resize(shift_right(binary, bitsPerHexDigit*index), bitsPerHexDigit) + ); + end loop; + return hexString; + end function toHexString; + +begin + + opCode := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length), + opCode'length + ); + destRegister := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-destRegister'length), + destRegister'length + ); + destRegisterString := 's' & toHexDigit(destRegister); + sourceRegister := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-destRegister'length-sourceRegister'length), + sourceRegister'length + ); + sourceRegisterString := 's' & toHexDigit(sourceRegister); + sourceConstant := resize(unsigned(instruction), sourceConstant'length); + sourceConstantString := toHexString(sourceConstant); + branchKind := resize( + shift_right(unsigned(instruction), instruction'length-opCode'length-branchKind'length), + branchKind'length + ); + branchAddress := resize(unsigned(instruction), branchAddress'length); + branchAddressString := toHexString(branchAddress); + shRotCin := resize(shift_right(unsigned(instruction), 1), shRotCin'length); + shRotDir := instruction(0); + + case opCode is + when \"000000\" => instrString <= pad(\"LOAD \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"000001\" => instrString <= pad(\"LOAD \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"000100\" => instrString <= pad(\"INPUT \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"000101\" => instrString <= pad(\"INPUT \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"000110\" => instrString <= pad(\"FETCH \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"000111\" => instrString <= pad(\"FETCH \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"001010\" => instrString <= pad(\"AND \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"001011\" => instrString <= pad(\"AND \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"001100\" => instrString <= pad(\"OR \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"001101\" => instrString <= pad(\"OR \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"001110\" => instrString <= pad(\"XOR \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"001111\" => instrString <= pad(\"XOR \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"010010\" => instrString <= pad(\"TEST \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"010011\" => instrString <= pad(\"TEST \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"010100\" => instrString <= pad(\"COMP \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"010101\" => instrString <= pad(\"COMP \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"011000\" => instrString <= pad(\"ADD \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"011001\" => instrString <= pad(\"ADD \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"011010\" => instrString <= pad(\"ADDCY \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"011011\" => instrString <= pad(\"ADDCY \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"011100\" => instrString <= pad(\"SUB \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"011101\" => instrString <= pad(\"SUB \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"011110\" => instrString <= pad(\"SUBCY \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"011111\" => instrString <= pad(\"SUBCY \" & destRegisterString & \" \" & sourceRegisterString, instrString'length); + when \"100000\" => + case shRotCin is + when \"000\" => instrString <= pad(\"SLA \" & destRegisterString, instrString'length); + when \"001\" => instrString <= pad(\"RL \" & destRegisterString, instrString'length); + when \"010\" => instrString <= pad(\"SLX \" & destRegisterString, instrString'length); + when \"011\" => + case shRotDir is + when '0' => instrString <= pad(\"SL0 \" & destRegisterString, instrString'length); + when '1' => instrString <= pad(\"SL1 \" & destRegisterString, instrString'length); + when others => instrString <= pad(\"--------\", instrString'length); + end case; + when \"100\" => instrString <= pad(\"SRA \" & destRegisterString, instrString'length); + when \"101\" => instrString <= pad(\"SRX \" & destRegisterString, instrString'length); + when \"110\" => instrString <= pad(\"RR \" & destRegisterString, instrString'length); + when \"111\" => + case shRotDir is + when '0' => instrString <= pad(\"SR0 \" & destRegisterString, instrString'length); + when '1' => instrString <= pad(\"SR1 \" & destRegisterString, instrString'length); + when others => instrString <= pad(\"--------\", instrString'length); + end case; + when others => instrString <= pad(\"--------\", instrString'length); + end case; + when \"101100\" => instrString <= pad(\"OUTPUT \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"101101\" => instrString <= pad(\"OUTPUT \" & destRegisterString & \" (\" & sourceRegisterString & \")\", instrString'length); + when \"101110\" => instrString <= pad(\"STORE \" & destRegisterString & \" \" & sourceConstantString, instrString'length); + when \"101111\" => instrString <= pad(\"STORE \" & destRegisterString & \" (\" & sourceRegisterString & \")\", instrString'length); + when \"101010\" => instrString <= pad(\"RET\", instrString'length); + when \"101011\" => + case branchKind is + when \"00\" => instrString <= pad(\"RET Z\", instrString'length); + when \"01\" => instrString <= pad(\"RET NZ\", instrString'length); + when \"10\" => instrString <= pad(\"RET C\", instrString'length); + when \"11\" => instrString <= pad(\"RET NC\", instrString'length); + when others => instrString <= pad(\"--------\", instrString'length); + end case; + when \"110000\" => instrString <= pad(\"CALL \" & branchAddressString, instrString'length); + when \"110001\" => + case branchKind is + when \"00\" => instrString <= pad(\"CALL Z \" & branchAddressString, instrString'length); + when \"01\" => instrString <= pad(\"CALL NZ \" & branchAddressString, instrString'length); + when \"10\" => instrString <= pad(\"CALL C \" & branchAddressString, instrString'length); + when \"11\" => instrString <= pad(\"CALL NC \" & branchAddressString, instrString'length); + when others => instrString <= pad(\"--------\", instrString'length); + end case; + when \"110100\" => instrString <= pad(\"JUMP \" & branchAddressString, instrString'length); + when \"110101\" => + case branchKind is + when \"00\" => instrString <= pad(\"JUMP Z \" & branchAddressString, instrString'length); + when \"01\" => instrString <= pad(\"JUMP NZ \" & branchAddressString, instrString'length); + when \"10\" => instrString <= pad(\"JUMP C \" & branchAddressString, instrString'length); + when \"11\" => instrString <= pad(\"JUMP NC \" & branchAddressString, instrString'length); + when others => instrString <= pad(\"--------\", instrString'length); + end case; + when others => instrString <= pad(\"--------\", instrString'length); + end case; + +end process; + +-- pragma translate_on + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 14000 +visibleWidth 24000 +) +) +) +] +shape (Rectangle +uid 22855,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "132000,-6000,156000,10000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 22856,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*191 (Text +uid 22857,0 +va (VaSet +) +xt "132400,10000,134000,11000" +st "eb4" +blo "132400,10800" +tm "HdlTextNameMgr" +) +*192 (Text +uid 22858,0 +va (VaSet +) +xt "132400,11000,133200,12000" +st "4" +blo "132400,11800" +tm "HdlTextNumberMgr" +) +] +) +) +*193 (Net +uid 22879,0 +decl (Decl +n "instrString" +t "string" +b "(1 TO 16)" +o 23 +suid 223,0 +) +declText (MLText +uid 22880,0 +va (VaSet +font "Courier New,8,0" +) +xt "26000,24000,49000,24800" +st "SIGNAL instrString : string(1 TO 16)" +) +) +*194 (Wire +uid 6763,0 +shape (OrthoPolyLine +uid 6764,0 +va (VaSet +vasetType 3 +) +xt "53000,166000,60250,166000" +pts [ +"53000,166000" +"60250,166000" +] +) +start &13 +end &112 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 6767,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 6768,0 +va (VaSet +font "Verdana,12,0" +) +xt "53000,164600,57100,166000" +st "reset" +blo "53000,165800" +tm "WireNameMgr" +) +) +on &12 +) +*195 (Wire +uid 16421,0 +shape (OrthoPolyLine +uid 16422,0 +va (VaSet +vasetType 3 +) +xt "77750,115000,157000,115000" +pts [ +"77750,115000" +"157000,115000" +] +) +start &110 +end &14 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16425,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16426,0 +va (VaSet +font "Verdana,12,0" +) +xt "150000,113600,158700,115000" +st "readStrobe" +blo "150000,114800" +tm "WireNameMgr" +) +) +on &15 +) +*196 (Wire +uid 16436,0 +shape (OrthoPolyLine +uid 16437,0 +va (VaSet +vasetType 3 +) +xt "77750,117000,157000,117000" +pts [ +"77750,117000" +"157000,117000" +] +) +start &116 +end &16 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16440,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16441,0 +va (VaSet +font "Verdana,12,0" +) +xt "150000,115600,159000,117000" +st "writeStrobe" +blo "150000,116800" +tm "WireNameMgr" +) +) +on &17 +) +*197 (Wire +uid 16481,0 +shape (OrthoPolyLine +uid 16482,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "149000,105000,157000,105000" +pts [ +"149000,105000" +"157000,105000" +] +) +start &55 +end &18 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16485,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16486,0 +va (VaSet +font "Verdana,12,0" +) +xt "150000,103600,159600,105000" +st "dataAddress" +blo "150000,104800" +tm "WireNameMgr" +) +) +on &19 +) +*198 (Wire +uid 16496,0 +shape (OrthoPolyLine +uid 16497,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "149000,129000,157000,129000" +pts [ +"149000,129000" +"157000,129000" +] +) +start &61 +end &20 +sat 2 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16500,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16501,0 +va (VaSet +font "Verdana,12,0" +) +xt "152000,127600,158000,129000" +st "dataOut" +blo "152000,128800" +tm "WireNameMgr" +) +) +on &21 +) +*199 (Wire +uid 16511,0 +shape (OrthoPolyLine +uid 16512,0 +va (VaSet +vasetType 3 +) +xt "53000,53000,60250,53000" +pts [ +"60250,53000" +"53000,53000" +] +) +start &104 +end &22 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16515,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16516,0 +va (VaSet +font "Verdana,12,0" +) +xt "53000,51600,57500,53000" +st "intAck" +blo "53000,52800" +tm "WireNameMgr" +) +) +on &23 +) +*200 (Wire +uid 16860,0 +shape (OrthoPolyLine +uid 16861,0 +va (VaSet +vasetType 3 +) +xt "53000,164000,60250,164000" +pts [ +"53000,164000" +"60250,164000" +] +) +start &24 +end &97 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16864,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16865,0 +va (VaSet +font "Verdana,12,0" +) +xt "53000,162600,56800,164000" +st "clock" +blo "53000,163800" +tm "WireNameMgr" +) +) +on &25 +) +*201 (Wire +uid 16875,0 +shape (OrthoPolyLine +uid 16876,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "149000,131000,157000,131000" +pts [ +"157000,131000" +"149000,131000" +] +) +start &26 +end &61 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16879,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16880,0 +va (VaSet +font "Verdana,12,0" +) +xt "153000,129600,158000,131000" +st "dataIn" +blo "153000,130800" +tm "WireNameMgr" +) +) +on &27 +) +*202 (Wire +uid 16890,0 +shape (OrthoPolyLine +uid 16891,0 +va (VaSet +vasetType 3 +) +xt "53000,162000,60250,162000" +pts [ +"53000,162000" +"60250,162000" +] +) +start &28 +end &100 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16894,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16895,0 +va (VaSet +font "Verdana,12,0" +) +xt "53000,160600,55400,162000" +st "en" +blo "53000,161800" +tm "WireNameMgr" +) +) +on &29 +) +*203 (Wire +uid 16905,0 +shape (OrthoPolyLine +uid 16906,0 +va (VaSet +vasetType 3 +) +xt "53000,51000,60250,51000" +pts [ +"53000,51000" +"60250,51000" +] +) +start &30 +end &103 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 16909,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 16910,0 +va (VaSet +font "Verdana,12,0" +) +xt "53000,49600,55400,51000" +st "int" +blo "53000,50800" +tm "WireNameMgr" +) +) +on &31 +) +*204 (Wire +uid 17294,0 +shape (OrthoPolyLine +uid 17295,0 +va (VaSet +vasetType 3 +) +xt "77750,125000,92250,125000" +pts [ +"92250,125000" +"77750,125000" +] +) +start &147 +end &111 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 17298,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17299,0 +va (VaSet +font "Verdana,12,0" +) +xt "80000,123600,90500,125000" +st "registerFileSel" +blo "80000,124800" +tm "WireNameMgr" +) +) +on &32 +) +*205 (Wire +uid 17302,0 +shape (OrthoPolyLine +uid 17303,0 +va (VaSet +vasetType 3 +) +xt "77750,127000,92250,127000" +pts [ +"92250,127000" +"77750,127000" +] +) +start &146 +end &102 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 17306,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17307,0 +va (VaSet +font "Verdana,12,0" +) +xt "80000,125600,89300,127000" +st "instrDataSel" +blo "80000,126800" +tm "WireNameMgr" +) +) +on &33 +) +*206 (Wire +uid 17310,0 +shape (OrthoPolyLine +uid 17311,0 +va (VaSet +vasetType 3 +) +xt "77750,129000,92250,129000" +pts [ +"92250,129000" +"77750,129000" +] +) +start &140 +end &109 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 17314,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17315,0 +va (VaSet +font "Verdana,12,0" +) +xt "80000,127600,86600,129000" +st "portInSel" +blo "80000,128800" +tm "WireNameMgr" +) +) +on &34 +) +*207 (Wire +uid 17318,0 +shape (OrthoPolyLine +uid 17319,0 +va (VaSet +vasetType 3 +) +xt "77750,131000,92250,131000" +pts [ +"92250,131000" +"77750,131000" +] +) +start &148 +end &113 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 17322,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17323,0 +va (VaSet +font "Verdana,12,0" +) +xt "80000,129600,90400,131000" +st "scratchpadSel" +blo "80000,130800" +tm "WireNameMgr" +) +) +on &35 +) +*208 (Wire +uid 17326,0 +shape (OrthoPolyLine +uid 17327,0 +va (VaSet +vasetType 3 +) +xt "77750,137000,92250,137000" +pts [ +"92250,137000" +"77750,137000" +] +) +start &149 +end &96 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 17330,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17331,0 +va (VaSet +font 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"WireNameMgr" +) +) +on &38 +) +*211 (Wire +uid 17348,0 +shape (OrthoPolyLine +uid 17349,0 +va (VaSet +vasetType 3 +) +xt "89000,147000,92250,147000" +pts [ +"89000,147000" +"92250,147000" +] +) +end &141 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 17354,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17355,0 +va (VaSet +font "Verdana,12,0" +) +xt "88000,145600,92100,147000" +st "reset" +blo "88000,146800" +tm "WireNameMgr" +) +) +on &12 +) +*212 (Wire +uid 17356,0 +shape (OrthoPolyLine +uid 17357,0 +va (VaSet +vasetType 3 +) +xt "89000,145000,92250,145000" +pts [ +"89000,145000" +"92250,145000" +] +) +end &138 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 17362,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17363,0 +va (VaSet +font "Verdana,12,0" +) +xt "88000,143600,91800,145000" +st "clock" +blo "88000,144800" +tm "WireNameMgr" +) +) +on &25 +) +*213 (Wire +uid 17581,0 +shape (OrthoPolyLine +uid 17582,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "77750,97000,92250,97000" +pts [ +"92250,97000" +"77750,97000" +] +) +start &182 +end &105 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 17585,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17586,0 +va (VaSet +font "Verdana,12,0" +) +xt "85250,95600,90950,97000" +st "intCode" +blo "85250,96800" +tm "WireNameMgr" +) +) +on &39 +) +*214 (Wire +uid 17589,0 +shape (OrthoPolyLine +uid 17590,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "77750,99000,92250,99000" +pts [ +"92250,99000" +"77750,99000" +] +) +start &181 +end &95 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 17593,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17594,0 +va (VaSet +font "Verdana,12,0" +) +xt "82250,97600,91450,99000" +st "branchCond" +blo "82250,98800" +tm "WireNameMgr" +) +) +on &92 +) +*215 (Wire +uid 17597,0 +shape (OrthoPolyLine +uid 17598,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "77750,103000,92250,103000" +pts [ +"92250,103000" +"77750,103000" +] +) +start &177 +end &108 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 17601,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17602,0 +va (VaSet +font "Verdana,12,0" +) +xt "85250,101600,90950,103000" +st "opCode" +blo "85250,102800" +tm "WireNameMgr" +) +) +on &40 +) +*216 (Wire +uid 17605,0 +shape (OrthoPolyLine +uid 17606,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "97000,109750,97000,120250" +pts [ +"97000,109750" +"97000,120250" +] +) +start &172 +end &139 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 17607,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17608,0 +va (VaSet +font "Verdana,12,0" +) +xt "92000,118600,98000,120000" +st "aluCode" +blo "92000,119800" +tm "WireNameMgr" +) +) +on &41 +) +*217 (Wire +uid 17611,0 +shape (OrthoPolyLine +uid 17612,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "101000,109750,101000,120250" +pts [ +"101000,109750" +"101000,120250" +] +) +start &174 +end &143 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 17613,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17614,0 +va (VaSet +font "Verdana,12,0" +) +xt "101000,110600,105500,112000" +st "addrA" +blo "101000,111800" +tm "WireNameMgr" +) +) +on &42 +) +*218 (Wire +uid 17617,0 +shape (OrthoPolyLine +uid 17618,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "105000,109750,105000,120250" +pts [ +"105000,109750" +"105000,120250" +] +) +start &175 +end &144 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 17619,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17620,0 +va (VaSet +font "Verdana,12,0" +) +xt "105000,110600,109500,112000" +st "addrB" +blo "105000,111800" +tm "WireNameMgr" +) +) +on &43 +) +*219 (Wire +uid 17623,0 +shape (OrthoPolyLine +uid 17624,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "113000,109750,113000,120250" +pts [ +"113000,109750" +"113000,120250" +] +) +start &176 +end &145 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 17625,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17626,0 +va (VaSet +font "Verdana,12,0" +) +xt "114000,110600,120600,112000" +st "instrData" +blo "114000,111800" +tm "WireNameMgr" +) +) +on &44 +) +*220 (Wire +uid 17851,0 +optionalChildren [ +*221 (BdJunction +uid 18272,0 +ps "OnConnectorStrategy" +shape (Circle +uid 18273,0 +va (VaSet +vasetType 1 +) +xt "124600,72600,125400,73400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 17852,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,73000,157000,73000" +pts [ +"117750,73000" +"157000,73000" +] +) +start &82 +end &45 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 17855,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17856,0 +va (VaSet +font "Verdana,12,0" +) +xt "149000,71600,158600,73000" +st "progCounter" +blo "149000,72800" +tm "WireNameMgr" +) +) +on &49 +) +*222 (Wire +uid 17866,0 +shape (OrthoPolyLine +uid 17867,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,97000,157000,97000" +pts [ +"157000,97000" +"117750,97000" +] +) +start &46 +end &179 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 17870,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 17871,0 +va (VaSet +font "Verdana,12,0" +) +xt "151000,95600,159200,97000" +st "instruction" +blo "151000,96800" +tm "WireNameMgr" +) +) +on &47 +) +*223 (Wire +uid 18053,0 +shape (OrthoPolyLine +uid 18054,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "105000,85750,105000,92250" +pts [ +"105000,92250" +"105000,85750" +] +) +start &180 +end &84 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 18055,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18056,0 +va (VaSet +font "Verdana,12,0" +) +xt "106000,90600,115500,92000" +st "instrAddress" +blo "106000,91800" +tm "WireNameMgr" +) +) +on &48 +) +*224 (Wire +uid 18189,0 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+"77750,77000" +] +) +start &88 +end &107 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 18211,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18212,0 +va (VaSet +font "Verdana,12,0" +) +xt "80000,75600,90200,77000" +st "loadStoredPC" +blo "80000,76800" +tm "WireNameMgr" +) +) +on &50 +) +*227 (Wire +uid 18215,0 +shape (OrthoPolyLine +uid 18216,0 +va (VaSet +vasetType 3 +) +xt "77750,75000,92250,75000" +pts [ +"92250,75000" +"77750,75000" +] +) +start &87 +end &106 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 18219,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18220,0 +va (VaSet +font "Verdana,12,0" +) +xt "79000,73600,91400,75000" +st "loadInstrAddress" +blo "79000,74800" +tm "WireNameMgr" +) +) +on &51 +) +*228 (Wire +uid 18223,0 +shape (OrthoPolyLine +uid 18224,0 +va (VaSet +vasetType 3 +) +xt "77750,73000,92250,73000" +pts [ +"92250,73000" +"77750,73000" +] +) +start &86 +end &101 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 18227,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18228,0 +va (VaSet +font "Verdana,12,0" +) +xt "80000,71600,84200,73000" +st "incPC" +blo "80000,72800" +tm "WireNameMgr" +) +) +on &52 +) +*229 (Wire +uid 18268,0 +shape (OrthoPolyLine +uid 18269,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,51000,125000,73000" +pts [ +"125000,73000" +"125000,51000" +"117750,51000" +] +) +start &221 +end &125 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 18270,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18271,0 +va (VaSet +font "Verdana,12,0" +) +xt "119750,49600,129350,51000" +st "progCounter" +blo "119750,50800" +tm "WireNameMgr" +) +) +on &49 +) +*230 (Wire +uid 18276,0 +shape (OrthoPolyLine +uid 18277,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "105000,61750,105000,68250" +pts [ +"105000,61750" +"105000,68250" +] +) +start &126 +end &83 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 18278,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18279,0 +va (VaSet +font "Verdana,12,0" +) +xt "105000,62600,118700,64000" +st "storedProgCounter" +blo "105000,63800" +tm "WireNameMgr" +) +) +on &53 +) +*231 (Wire +uid 18290,0 +shape (OrthoPolyLine +uid 18291,0 +va (VaSet +vasetType 3 +) +xt "77750,53000,92250,53000" +pts [ +"92250,53000" +"77750,53000" +] +) +start &129 +end &115 +sat 32 +eat 32 +stc 0 +st 0 +si 0 +tg (WTG +uid 18294,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18295,0 +va (VaSet +font "Verdana,12,0" +) +xt "80000,51600,85800,53000" +st "storePC" +blo "80000,52800" +tm "WireNameMgr" +) +) +on &54 +) +*232 (Wire +uid 18296,0 +shape (OrthoPolyLine +uid 18297,0 +va (VaSet +vasetType 3 +) +xt "89000,59000,92250,59000" +pts [ +"89000,59000" +"92250,59000" +] +) +end &127 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 18302,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18303,0 +va (VaSet +font "Verdana,12,0" +) +xt "88000,57600,92100,59000" +st "reset" +blo "88000,58800" +tm "WireNameMgr" +) +) +on &12 +) +*233 (Wire +uid 18304,0 +shape (OrthoPolyLine +uid 18305,0 +va (VaSet +vasetType 3 +) +xt "89000,57000,92250,57000" +pts [ +"89000,57000" +"92250,57000" +] +) +end &124 +sat 16 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 18310,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18311,0 +va (VaSet +font "Verdana,12,0" +) +xt "88000,55600,91800,57000" +st "clock" +blo "88000,56800" +tm "WireNameMgr" +) +) +on &25 +) +*234 (Wire +uid 18565,0 +shape (OrthoPolyLine +uid 18566,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,101000,133000,105000" +pts [ +"117750,101000" +"129000,101000" +"129000,105000" +"133000,105000" +] +) +start &178 +end &55 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 18569,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18570,0 +va (VaSet +font "Verdana,12,0" +) +xt "120000,99600,132300,101000" +st "portInstrAddress" +blo "120000,100800" +tm "WireNameMgr" +) +) +on &70 +) +*235 (Wire +uid 18580,0 +shape (OrthoPolyLine +uid 18581,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,107000,133000,127000" +pts [ +"117750,127000" +"129000,127000" +"129000,107000" +"133000,107000" +] +) +start &142 +end &55 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 18584,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18585,0 +va (VaSet +font "Verdana,12,0" +) +xt "119750,125600,131450,127000" +st "portRegAddress" +blo "119750,126800" +tm "WireNameMgr" +) +) +on &78 +) +*236 (Wire +uid 18596,0 +shape (OrthoPolyLine +uid 18597,0 +va (VaSet +vasetType 3 +) +xt "117750,99000,141000,101000" +pts [ +"117750,99000" +"141000,99000" +"141000,101000" +] +) +start &173 +end &55 +sat 32 +eat 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 18600,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18601,0 +va (VaSet +font "Verdana,12,0" +) +xt "132000,97600,143300,99000" +st "portIndexedSel" +blo "132000,98800" +tm "WireNameMgr" +) +) +on &69 +) +*237 (Wire +uid 18610,0 +shape (OrthoPolyLine +uid 18611,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "117750,105000,133000,147000" +pts [ +"117750,105000" +"123000,105000" +"123000,147000" +"133000,147000" +] +) +start &183 +end &73 +sat 32 +eat 1 +sty 1 +stc 0 +st 0 +si 0 +tg (WTG +uid 18612,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18613,0 +va (VaSet +font "Verdana,12,0" +) +xt "123000,145600,135800,147000" +st "spadInstrAddress" +blo "123000,146800" +tm "WireNameMgr" +) +) +on &71 +) +*238 (Wire +uid 18614,0 +shape (OrthoPolyLine +uid 18615,0 +va (VaSet +vasetType 3 +) +xt "89000,167000,92250,167000" +pts [ +"89000,167000" +"92250,167000" +] +) +end &163 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 18620,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 18621,0 +va (VaSet +font "Verdana,12,0" +) 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+) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Courier New,9,0" +) +xt "1000,1000,4000,2200" +st "Panel0" +blo "1000,1900" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,47000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +) +xt "29100,14700,32200,15700" +st "" +blo "29100,15500" +) +second (Text +va (VaSet +) +xt "29100,15700,31300,16700" +st "" +blo "29100,16500" +) +) +gi *117 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVis (PortSigDisplay +sT 1 +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *118 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,10,1" +) +xt "0,9400,8600,10600" +st "Declarations" +blo "0,10400" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,10,1" +) +xt "0,10600,4200,11800" +st "Ports:" +blo "0,11600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,10,1" +) +xt "0,21400,3700,22600" +st "User:" +blo "0,22400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,10,1" +) +xt "0,9400,9400,10600" +st "Internal User:" +blo "0,10400" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,22600,2000,22600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,9400,0,9400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 2590,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/Libs/NanoBlaze/hds/program@counter/symbol.sb b/Libs/NanoBlaze/hds/program@counter/symbol.sb new file mode 100644 index 0000000..9836ab9 --- /dev/null +++ b/Libs/NanoBlaze/hds/program@counter/symbol.sb @@ -0,0 +1,1762 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2009.2 (Build 10)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 31,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 88,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 3 +suid 17,0 +) +) +uid 461,0 +) +*15 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "progCounter" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 2 +suid 18,0 +) +) +uid 468,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "storedProgCounter" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 1 +suid 24,0 +) +) +uid 658,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "instrAddress" +t "unsigned" +b "( programCounterBitNb-1 DOWNTO 0 )" +o 4 +suid 27,0 +) +) +uid 714,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 28,0 +) +) +uid 761,0 +) +*19 (LogPort +port (LogicalPort +decl (Decl +n "incPC" +t "std_ulogic" +o 6 +suid 29,0 +) +) +uid 763,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl +n "loadInstrAddress" +t "std_ulogic" +o 7 +suid 30,0 +) +) +uid 765,0 +) +*21 (LogPort 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130,0 +vaOverrides [ +] +) +] +) +uid 116,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hdl" +) +(vvPair +variable "HDSDir" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\program@counter\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\program@counter\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "boardTester" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\program@counter" +) +(vvPair +variable "d_logical" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\programCounter" +) +(vvPair +variable "date" +value "16.09.2010" +) +(vvPair +variable "day" +value "jeu." +) +(vvPair +variable "day_long" +value "jeudi" +) +(vvPair +variable "dd" +value "16" +) +(vvPair +variable "entity_name" +value "programCounter" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE3195" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "nanoBlaze" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../NanoBlaze/designcheck" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "D:/Labs/ElN/NanoBlaze/NanoBlaze/work" +) +(vvPair +variable "mm" +value "09" +) +(vvPair +variable "module_name" +value "programCounter" +) +(vvPair +variable "month" +value "sept." +) +(vvPair +variable "month_long" +value "septembre" +) +(vvPair +variable "p" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\program@counter\\symbol.sb" +) +(vvPair +variable "p_logical" +value "I:\\Filiere\\Cours\\Bachelor\\225_SEm\\COURS_COF\\NanoBlaze\\Circuit\\Prefs\\..\\NanoBlaze\\hds\\programCounter\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "D:\\Labs\\ElN\\BoardTester\\Board\\ise" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "C:\\EDA\\Modelsim\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "10:47:20" +) +(vvPair +variable "unit" +value "programCounter" +) +(vvPair +variable "user" +value "cof" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2010" +) +(vvPair +variable "yy" +value "10" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 86,0 +optionalChildren [ +*69 (SymbolBody +uid 8,0 +optionalChildren [ +*70 (CptPort +uid 446,0 +ps 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ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "6,79,1266,910" +viewArea "-2000,-1100,73993,51241" +cachedDiagramExtent "-1000,0,72000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "-1000,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *86 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *87 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "16000,200,21400,1200" +st "Declarations" +blo "16000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "16000,1200,18700,2200" +st "Ports:" +blo "16000,2000" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "16000,6200,18400,7200" +st "User:" +blo "16000,7000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "16000,200,21800,1200" +st "Internal User:" +blo "16000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "18000,7200,18000,7200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "16000,200,16000,200" +tm "SyDeclarativeTextMgr" +) +) +lastUid 245,0 +activeModelName "Symbol" +) diff --git a/Libs/NanoBlaze/hds/register@file/symbol.sb b/Libs/NanoBlaze/hds/register@file/symbol.sb new file mode 100644 index 0000000..3c6a15c --- /dev/null +++ b/Libs/NanoBlaze/hds/register@file/symbol.sb @@ -0,0 +1,1772 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "24.1" +appVersion "2007.1a (Build 13)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 8,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 109,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "addrA" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 1 +suid 1,0 +) +) +uid 91,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "addrB" +t "unsigned" +b "( registerAddressBitNb-1 DOWNTO 0 )" +o 2 +suid 2,0 +) +) +uid 93,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "registersIn" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 22 +suid 3,0 +) +) +uid 95,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 5 +suid 4,0 +) +) +uid 97,0 +) +*18 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "opA" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 21 +suid 5,0 +) +) +uid 99,0 +) +*19 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "opB" +t "signed" +b "( dataBitNb-1 DOWNTO 0 )" +o 22 +suid 6,0 +) +) +uid 101,0 +) +*20 (LogPort +port (LogicalPort +decl (Decl +n "regWrite" +t "std_ulogic" +o 10 +suid 7,0 +) +) +uid 103,0 +) +*21 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 12 +suid 8,0 +) +) +uid 105,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 122,0 +optionalChildren [ +*22 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *23 (MRCItem +litem &1 +pos 8 +dimension 20 +) +uid 124,0 +optionalChildren [ +*24 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 125,0 +) +*25 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 126,0 +) +*26 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 127,0 +) +*27 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 92,0 +) +*28 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 94,0 +) +*29 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 96,0 +) +*30 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 98,0 +) +*31 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 100,0 +) +*32 (MRCItem +litem &19 +pos 5 +dimension 20 +uid 102,0 +) +*33 (MRCItem +litem &20 +pos 6 +dimension 20 +uid 104,0 +) +*34 (MRCItem +litem &21 +pos 7 +dimension 20 +uid 106,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 128,0 +optionalChildren [ +*35 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 129,0 +) +*36 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 130,0 +) +*37 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 131,0 +) +*38 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 132,0 +) +*39 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 133,0 +) +*40 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 134,0 +) +*41 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 135,0 +) +*42 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 136,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 123,0 +vaOverrides [ +] +) +] +) +uid 108,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *43 (LEmptyRow +) +uid 138,0 +optionalChildren [ +*44 (RefLabelRowHdr +) +*45 (TitleRowHdr +) +*46 (FilterRowHdr +) +*47 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*48 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*49 (GroupColHdr +tm "GroupColHdrMgr" +) +*50 (NameColHdr +tm "GenericNameColHdrMgr" +) +*51 (TypeColHdr +tm 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clockPeriod*9.0/10.0; + + ------------------------------------------------------------------------------ + -- enable + en <= '1'; + + ------------------------------------------------------------------------------ + -- data + storeData: process(clock_int) + begin + if rising_edge(clock_int) then + if writeStrobe = '1' then + dataReg <= dataOut; + end if; + end if; + end process storeData; + + dataIn <= not dataReg; + + ------------------------------------------------------------------------------ + -- error checking + checkBus: process(clock_int) + begin + if rising_edge(clock_int) then + if writeStrobe = '1' then + if (dataAddress = 0) and (unsigned(dataOut) = 0) then + assert false + report "Testbench reports error (output value 0 at address 0)" + severity failure; + end if; + if (dataAddress = 0) and (unsigned(dataOut) = 1) then + assert false + report + cr & cr & + "--------------------------------------------------------------------------------" & cr & + "Testbench reports successful end of simulation (output value 1 at address 0)" & cr & + "--------------------------------------------------------------------------------" & cr & + cr + severity failure; + end if; + end if; + end if; + end process checkBus; + +END ARCHITECTURE test; diff --git a/Libs/NanoBlaze_test/hds/.hdlsidedata/_nanoBlaze_tester_test.vhd._fpf b/Libs/NanoBlaze_test/hds/.hdlsidedata/_nanoBlaze_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/NanoBlaze_test/hds/.hdlsidedata/_nanoBlaze_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/NanoBlaze_test/hds/_nanoblaze_tb._epf b/Libs/NanoBlaze_test/hds/_nanoblaze_tb._epf new file mode 100644 index 0000000..fab63fb --- /dev/null +++ b/Libs/NanoBlaze_test/hds/_nanoblaze_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom nano@blaze_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/NanoBlaze_test/hds/_nanoblaze_tester._epf b/Libs/NanoBlaze_test/hds/_nanoblaze_tester._epf new file mode 100644 index 0000000..c0b8b2d --- /dev/null +++ b/Libs/NanoBlaze_test/hds/_nanoblaze_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom nanoBlaze_tester_test.vhd diff --git a/Libs/NanoBlaze_test/hds/hds/_cordic_tb._epf b/Libs/NanoBlaze_test/hds/hds/_cordic_tb._epf new file mode 100644 index 0000000..21b4705 --- /dev/null +++ b/Libs/NanoBlaze_test/hds/hds/_cordic_tb._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom cordic_tb/struct.bd diff --git a/Libs/NanoBlaze_test/hds/hds/_cordic_tester._epf b/Libs/NanoBlaze_test/hds/hds/_cordic_tester._epf new file mode 100644 index 0000000..571444e --- /dev/null +++ b/Libs/NanoBlaze_test/hds/hds/_cordic_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom cordic_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/NanoBlaze_test/hds/hds/_motherboard_tb._epf b/Libs/NanoBlaze_test/hds/hds/_motherboard_tb._epf new file mode 100644 index 0000000..b97c86e --- /dev/null +++ b/Libs/NanoBlaze_test/hds/hds/_motherboard_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom motherboard_tb/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/NanoBlaze_test/hds/hds/_motherboard_tester._epf b/Libs/NanoBlaze_test/hds/hds/_motherboard_tester._epf new file mode 100644 index 0000000..7fb5b51 --- /dev/null +++ b/Libs/NanoBlaze_test/hds/hds/_motherboard_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom motherboard_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/NanoBlaze_test/hds/nano@blaze_tb/struct.bd b/Libs/NanoBlaze_test/hds/nano@blaze_tb/struct.bd new file mode 100644 index 0000000..e53ee7e --- /dev/null +++ b/Libs/NanoBlaze_test/hds/nano@blaze_tb/struct.bd @@ -0,0 +1,3457 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) 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(VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *101 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *102 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,10000,44400,11000" +st "User:" +blo "42000,10800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,11000,44000,11000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 413,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/NanoBlaze_test/sim/nanoBlaze.do b/Libs/NanoBlaze_test/sim/nanoBlaze.do new file mode 100644 index 0000000..1044918 --- /dev/null +++ b/Libs/NanoBlaze_test/sim/nanoBlaze.do @@ -0,0 +1,74 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /nanoblaze_tb/reset +add wave -noupdate /nanoblaze_tb/clock +add wave -noupdate /nanoblaze_tb/en +add wave -noupdate -divider Program +add wave -noupdate -format Analog-Step -height 30 -max 100.0 -radix hexadecimal /nanoblaze_tb/i_dut/programcounter +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/programcounter +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/instruction +add wave -noupdate /nanoblaze_tb/i_dut/i_up/instrstring +add wave -noupdate -divider Controller +add wave -noupdate /nanoblaze_tb/i_dut/i_up/opcode +add wave -noupdate /nanoblaze_tb/i_dut/i_up/tworeginstr +add wave -noupdate /nanoblaze_tb/i_dut/i_up/instrdatasel +add wave -noupdate /nanoblaze_tb/i_dut/i_up/registerfilesel +add wave -noupdate /nanoblaze_tb/i_dut/i_up/portinsel +add wave -noupdate /nanoblaze_tb/i_dut/i_up/scratchpadsel +add wave -noupdate /nanoblaze_tb/i_dut/i_up/regwrite +add wave -noupdate /nanoblaze_tb/i_dut/i_up/scratchpadwrite +add wave -noupdate -divider ALU +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/i_up/instrdata +add wave -noupdate /nanoblaze_tb/i_dut/i_up/alucode +add wave -noupdate -radix unsigned /nanoblaze_tb/i_dut/i_up/addra +add wave -noupdate -radix unsigned /nanoblaze_tb/i_dut/i_up/addrb +add wave -noupdate /nanoblaze_tb/i_dut/i_up/cin +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/i_up/i_alu/opa +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/i_up/i_alu/opb +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/i_up/i_alu/aluout +add wave -noupdate /nanoblaze_tb/i_dut/i_up/cout +add wave -noupdate /nanoblaze_tb/i_dut/i_up/zero +add wave -noupdate -divider {Register file} +add wave -noupdate -radix hexadecimal -subitemconfig {/nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(0) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(1) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(2) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(3) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(4) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(5) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(6) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(7) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(8) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(9) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(10) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(11) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(12) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(13) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(14) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray(15) {-radix hexadecimal}} /nanoblaze_tb/i_dut/i_up/i_alu/i_regs/registerarray +add wave -noupdate -divider I/O +add wave -noupdate -radix hexadecimal -subitemconfig {/nanoblaze_tb/dataaddress(7) {-radix hexadecimal} /nanoblaze_tb/dataaddress(6) {-radix hexadecimal} /nanoblaze_tb/dataaddress(5) {-radix hexadecimal} /nanoblaze_tb/dataaddress(4) {-radix hexadecimal} /nanoblaze_tb/dataaddress(3) {-radix hexadecimal} /nanoblaze_tb/dataaddress(2) {-radix hexadecimal} /nanoblaze_tb/dataaddress(1) {-radix hexadecimal} /nanoblaze_tb/dataaddress(0) {-radix hexadecimal}} /nanoblaze_tb/dataaddress +add wave -noupdate /nanoblaze_tb/readstrobe +add wave -noupdate /nanoblaze_tb/writestrobe +add wave -noupdate -radix hexadecimal /nanoblaze_tb/datain +add wave -noupdate -radix hexadecimal /nanoblaze_tb/dataout +add wave -noupdate -divider Scratchpad +add wave -noupdate -radix hexadecimal -subitemconfig {/nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(0) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(1) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(2) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(3) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(4) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(5) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(6) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(7) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(8) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(9) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(10) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(11) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(12) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(13) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(14) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray(15) {-radix hexadecimal}} /nanoblaze_tb/i_dut/i_up/g_scratchpad/i_spad/memoryarray +add wave -noupdate -divider Branch +add wave -noupdate /nanoblaze_tb/i_dut/i_up/branchcond +add wave -noupdate /nanoblaze_tb/i_dut/i_up/incpc +add wave -noupdate /nanoblaze_tb/i_dut/i_up/loadinstraddress +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/i_up/instraddress +add wave -noupdate /nanoblaze_tb/i_dut/i_up/loadstoredpc +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/i_up/storedprogcounter +add wave -noupdate /nanoblaze_tb/i_dut/i_up/progcounter +add wave -noupdate -divider Stack +add wave -noupdate /nanoblaze_tb/i_dut/i_up/storepc +add wave -noupdate /nanoblaze_tb/i_dut/i_up/prevpc +add wave -noupdate /nanoblaze_tb/i_dut/i_up/progcounter +add wave -noupdate -radix hexadecimal -subitemconfig {/nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(0) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(1) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(2) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(3) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(4) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(5) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(6) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(7) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(8) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(9) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(10) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(11) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(12) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(13) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(14) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(15) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(16) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(17) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(18) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(19) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(20) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(21) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(22) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(23) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(24) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(25) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(26) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(27) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(28) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(29) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(30) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(31) {-radix hexadecimal} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray(32) {-radix hexadecimal}} /nanoblaze_tb/i_dut/i_up/i_br/progcounterarray +add wave -noupdate -radix hexadecimal /nanoblaze_tb/i_dut/i_up/storedprogcounter +add wave -noupdate -divider Interrupts +add wave -noupdate /nanoblaze_tb/int +add wave -noupdate /nanoblaze_tb/intack +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {923600 ps} 0} +configure wave -namecolwidth 260 +configure wave -valuecolwidth 73 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1000 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {1050 ns} diff --git a/Libs/RS232/hdl/cmdRs232Mux_RTL.vhd b/Libs/RS232/hdl/cmdRs232Mux_RTL.vhd new file mode 100644 index 0000000..b29ab7b --- /dev/null +++ b/Libs/RS232/hdl/cmdRs232Mux_RTL.vhd @@ -0,0 +1,24 @@ +ARCHITECTURE RTL OF rs232Mux IS + + signal passThrough: std_ulogic; + +BEGIN + + passThrough <= not selOther; + + multiplexer: process(passThrough, txData, txFullF, TxWr, otherData, otherWr) + begin + if passThrough = '1' then + txDataF <= txData; + txWrF <= TxWr; + txFull <= txFullF; + otherFull <= '1'; + else + txDataF <= otherData; + txWrF <= otherWr; + otherFull <= txFullF; + txFull <= '1'; + end if; + end process multiplexer; + +END ARCHITECTURE RTL; diff --git a/Libs/RS232/hdl/serialPortReceiver_rtl.vhd b/Libs/RS232/hdl/serialPortReceiver_rtl.vhd new file mode 100644 index 0000000..2ea6a27 --- /dev/null +++ b/Libs/RS232/hdl/serialPortReceiver_rtl.vhd @@ -0,0 +1,151 @@ +--===========================================================================-- +-- Design units : CoCa.serialPortReceiver.rtl +-- +-- File name : serialPortReceiver_rtl.vhd +-- +-- Purpose : Decode data from UART into words +-- +-- Input : serial line data +-- +-- Output : +-- dataOut : word of data +-- dataValid : active when a new word of data is available +-- +-- +-- Limitations : +-- +-- +-- +-- Errors: : None known +-- +-- Library : Common +-- +-- Dependencies : None +-- +-- Author : +-- Haute école d'ingénierie (HEI/HES-SO) +-- Institut systèmes industriels (ISI) +-- Rue de l'industrie 23 +-- 1950 Sion +-- Switzerland (CH) +-- +-- Simulator : Mentor ModelSim V10.7c +------------------------------------------------ +-- Revision list +-- Version Author Date Changes +-- +-- V1.0 04.04.2022 - First version +--===========================================================================-- + +library Common; + use Common.CommonLib.all; + +architecture RTL of serialPortReceiver is + + signal dividerCounter: unsigned(requiredBitNb(baudRateDivide-1)-1 downto 0); + signal dividerCounterReset: std_uLogic; + signal rxDelayed: std_uLogic; + signal dividerCounterSynchronize: std_uLogic; + signal rxSample: std_uLogic; + signal rxShiftReg: std_ulogic_vector(dataBitNb-1 downto 0); + signal rxReceiving: std_uLogic; + signal rxDataValid: std_uLogic; + signal rxCounter: unsigned(requiredBitNb(dataBitNb)-1 downto 0); + +begin + + divide: process(reset, clock) + begin + if reset = '1' then + dividerCounter <= (others => '0'); + elsif rising_edge(clock) then + if dividerCounterSynchronize = '1' then + dividerCounter <= to_unsigned(baudRateDivide/2, dividerCounter'length); + elsif dividerCounterReset = '1' then + dividerCounter <= (others => '0'); + else + dividerCounter <= dividerCounter + 1; + end if; + end if; + end process divide; + + endOfCount: process(dividerCounter) + begin + if dividerCounter = baudRateDivide-1 then + dividerCounterReset <= '1'; + else + dividerCounterReset <= '0'; + end if; + end process endOfCount; + + delayRx: process(reset, clock) + begin + if reset = '1' then + rxDelayed <= '0'; + elsif rising_edge(clock) then + rxDelayed <= RxD; + end if; + end process delayRx; + + rxSynchronize: process(RxD, rxDelayed) + begin + if RxD /= rxDelayed then + dividerCounterSynchronize <= '1'; + else + dividerCounterSynchronize <= '0'; + end if; + end process rxSynchronize; + + rxSample <= dividerCounterReset and not dividerCounterSynchronize; + + shiftReg: process(reset, clock) + begin + if reset = '1' then + rxShiftReg <= (others => '0'); + elsif rising_edge(clock) then + if rxSample = '1' then + rxShiftReg(rxShiftReg'high-1 downto 0) <= rxShiftReg(rxShiftReg'high downto 1); + rxShiftReg(rxShiftReg'high) <= RxD; + end if; + end if; + end process shiftReg; + + detectReceive: process(reset, clock) + begin + if reset = '1' then + rxReceiving <= '0'; + rxDataValid <= '0'; + elsif rising_edge(clock) then + if rxSample = '1' then + if rxCounter = dataBitNb-1 then + rxDataValid <= '1'; + elsif RxD = '0' then + rxReceiving <= '1'; + end if; + elsif rxDataValid = '1' then + rxReceiving <= '0'; + rxDataValid <= '0'; + end if; + end if; + end process detectReceive; + + countRxBitNb: process(reset, clock) + begin + if reset = '1' then + rxCounter <= (others => '0'); + elsif rising_edge(clock) then + if rxSample = '1' then + if rxReceiving = '1' then + rxCounter <= rxCounter + 1; + else + rxCounter <= (others => '0'); + end if; + end if; + end if; + end process countRxBitNb; + + dataOut <= rxShiftReg; + dataValid <= rxDataValid; + +end RTL; + diff --git a/Libs/RS232/hdl/serialPortTransmitter_rtl.vhd b/Libs/RS232/hdl/serialPortTransmitter_rtl.vhd new file mode 100644 index 0000000..b85cd6f --- /dev/null +++ b/Libs/RS232/hdl/serialPortTransmitter_rtl.vhd @@ -0,0 +1,127 @@ +--===========================================================================-- +-- Design units : CoCa.serialPortTransmitter.rtl +-- +-- File name : serialPortTransmitter.vhd +-- +-- Purpose : Transmit a 8 bit data word over a serial line +-- add start and stop bits +-- +-- Parameters : dataBitNb : number of data bits +-- stopBitNb : number of stop bits +-- +-- +-- +-- Errors: : None known +-- +-- Library : Common +-- +-- Dependencies : None +-- +-- Author : +-- Haute ecole d'ingenierie (HEI/HES-SO) +-- Institut systemes industriels (ISI) +-- Rue de l'industrie 23 +-- 1950 Sion +-- Switzerland (CH) +-- +-- Simulator : Mentor ModelSim V10.7c +------------------------------------------------ +-- Revision list +-- Version Author Date Changes +-- +-- V1.0 04.04.2022 - First version +--===========================================================================-- + +library Common; + use Common.CommonLib.all; + +architecture RTL of serialPortTransmitter is + + signal dividerCounter: unsigned(requiredBitNb(baudRateDivide)-1 downto 0); + signal dividerCounterReset: std_uLogic; + signal txData: unsigned(dataBitNb-1 downto 0); + signal send1: std_uLogic; + signal txShiftEnable: std_uLogic; + signal txShiftReg: unsigned(dataBitNb+stopBitNb downto 0); + signal txSendingByte: std_uLogic; + signal txSendingByteAndStop: std_uLogic; + +begin + + divide: process(reset, clock) + begin + if reset = '1' then + dividerCounter <= (others => '0'); + elsif rising_edge(clock) then + if dividerCounterReset = '1' then + dividerCounter <= to_unsigned(1, dividerCounter'length); + else + dividerCounter <= dividerCounter + 1; + end if; + end if; + end process divide; + + endOfCount: process(dividerCounter, send1) + begin + if dividerCounter = baudRateDivide then + dividerCounterReset <= '1'; + elsif send1 = '1' then + dividerCounterReset <= '1'; + else + dividerCounterReset <= '0'; + end if; + end process endOfCount; + + txShiftEnable <= dividerCounterReset; + + storeData: process(reset, clock) + begin + if reset = '1' then + txData <= (others => '1'); + elsif rising_edge(clock) then + if send = '1' then + txData <= unsigned(dataIn); + end if; + end if; + end process storeData; + + delaySend: process(reset, clock) + begin + if reset = '1' then + send1 <= '0'; + elsif rising_edge(clock) then + send1 <= send; + end if; + end process delaySend; + + shiftReg: process(reset, clock) + begin + if reset = '1' then + txShiftReg <= (others => '1'); + elsif rising_edge(clock) then + if txShiftEnable = '1' then + if send1 = '1' then + txShiftReg <= (others => '1'); -- stop bits + txShiftReg(0) <= '0'; -- start bit + txShiftReg(txData'high+1 downto 1) <= txData; -- data + txShiftReg(txShiftReg'high) <= '0'; -- end flag + else + txShiftReg <= shift_right(txShiftReg, 1); + txShiftReg(txShiftReg'high) <= '1'; + end if; + end if; + end if; + end process shiftReg; + + txSendingByte <= '1' when + (txShiftReg(txShiftReg'high downto 1) /= (txShiftReg'high downto 1 => '1')) + else '0'; + + txSendingByteAndStop <= '1' when + txShiftReg /= (txShiftReg'high downto 0 => '1') + else '0'; + + TxD <= txShiftReg(0) when txSendingByte = '1' else '1'; + busy <= txSendingByteAndStop or send1 or send; + +end RTL; diff --git a/Libs/RS232/hds/.hdlsidedata/_cmdRs232Mux_RTL.vhd._fpf b/Libs/RS232/hds/.hdlsidedata/_cmdRs232Mux_RTL.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_cmdRs232Mux_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialPortReceiver_rtl.vhd._fpf b/Libs/RS232/hds/.hdlsidedata/_serialPortReceiver_rtl.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialPortReceiver_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialPortTransmitter_rtl.vhd._fpf b/Libs/RS232/hds/.hdlsidedata/_serialPortTransmitter_rtl.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialPortTransmitter_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialportfifo_entity.vhd._fpf b/Libs/RS232/hds/.hdlsidedata/_serialportfifo_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialportfifo_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialportfifo_struct.vhd._fpf b/Libs/RS232/hds/.hdlsidedata/_serialportfifo_struct.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialportfifo_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialportreceiver_entity.vhd._fpf b/Libs/RS232/hds/.hdlsidedata/_serialportreceiver_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialportreceiver_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialportreceiver_entity.vhg._fpf b/Libs/RS232/hds/.hdlsidedata/_serialportreceiver_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialportreceiver_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialporttransmitter_entity.vhd._fpf b/Libs/RS232/hds/.hdlsidedata/_serialporttransmitter_entity.vhd._fpf new file mode 100755 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialporttransmitter_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/.hdlsidedata/_serialporttransmitter_entity.vhg._fpf b/Libs/RS232/hds/.hdlsidedata/_serialporttransmitter_entity.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232/hds/.hdlsidedata/_serialporttransmitter_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232/hds/_rs232mux._epf b/Libs/RS232/hds/_rs232mux._epf new file mode 100644 index 0000000..798e692 --- /dev/null +++ b/Libs/RS232/hds/_rs232mux._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom cmdRs232Mux_RTL.vhd +DEFAULT_ARCHITECTURE atom RTL +TOP_MARKER atom 1 diff --git a/Libs/RS232/hds/_serialportfifo._epf b/Libs/RS232/hds/_serialportfifo._epf new file mode 100644 index 0000000..313265a --- /dev/null +++ b/Libs/RS232/hds/_serialportfifo._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom serial@port@f@i@f@o/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/RS232/hds/_serialportreceiver._epf b/Libs/RS232/hds/_serialportreceiver._epf new file mode 100755 index 0000000..38845ed --- /dev/null +++ b/Libs/RS232/hds/_serialportreceiver._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom serialPortReceiver_rtl.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/RS232/hds/_serialporttransmitter._epf b/Libs/RS232/hds/_serialporttransmitter._epf new file mode 100755 index 0000000..c6d4f61 --- /dev/null +++ b/Libs/RS232/hds/_serialporttransmitter._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom serialPortTransmitter_rtl.vhd +DEFAULT_ARCHITECTURE atom RTL diff --git a/Libs/RS232/hds/rs232@mux/symbol.sb b/Libs/RS232/hds/rs232@mux/symbol.sb new file mode 100644 index 0000000..3259f40 --- /dev/null +++ b/Libs/RS232/hds/rs232@mux/symbol.sb @@ -0,0 +1,1920 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName 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a/Libs/RS232/hds/serial@port@f@i@f@o/struct.bd b/Libs/RS232/hds/serial@port@f@i@f@o/struct.bd new file mode 100644 index 0000000..fae7621 --- /dev/null +++ b/Libs/RS232/hds/serial@port@f@i@f@o/struct.bd @@ -0,0 +1,5465 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_rx" +duLibraryName "RS232" +duName "serialPortReceiver" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "baudRateDivide" +type "positive" +value "baudRateDivide" +) +] +mwi 0 +uid 1663,0 +) +(Instance +name "I_tx" +duLibraryName "RS232" +duName "serialPortTransmitter" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "baudRateDivide" +type "positive" +value "baudRateDivide" +) +] +mwi 0 +uid 1696,0 +) +(Instance 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"library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Libraries/RS232/work" +) +(vvPair +variable "library_downstream_SpyGlass" +value "U:\\ELN_Board\\Synthesis" +) +(vvPair +variable "mm" +value "04" +) +(vvPair +variable "module_name" +value "serialPortFIFO" +) +(vvPair +variable "month" +value "avr." +) +(vvPair +variable "month_long" +value "avril" +) +(vvPair +variable "p" +value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serial@port@f@i@f@o\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\did-inverter\\Libs\\RS232\\hds\\serialPortFIFO\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_ActelPath" +value "$ACTEL_HOME" +) +(vvPair +variable "task_ActelProjectPath" +value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR" +) +(vvPair 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+ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 196,0 +va (VaSet +font "courier,9,0" +) +xt "35000,17400,38100,18600" +st "send" +blo "35000,18400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 197,0 +va (VaSet +font "courier,8,0" +) +xt "2000,11400,17000,12300" +st "send : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "send" +t "std_ulogic" +o 5 +suid 5,0 +) +) +) +*75 (CptPort +uid 216,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 298,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "33250,19625,34000,20375" +) +tg (CPTG +uid 218,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 219,0 +va (VaSet +font "courier,9,0" +) +xt "35000,19400,38100,20600" +st "busy" +blo "35000,20400" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 220,0 +va (VaSet +font "courier,8,0" +) +xt "2000,12300,16000,13200" +st "busy : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "busy" +t "std_ulogic" +o 6 +suid 6,0 +) +) +) +] +shape (Rectangle +uid 81,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "34000,12000,50000,28000" +) +oxt "15000,6000,35000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "courier,9,1" +) +xt "34600,27800,37100,28700" +st "RS232" +blo "34600,28500" +) +second (Text +uid 12,0 +va (VaSet +font "courier,9,1" +) +xt "34600,28700,45600,29600" +st "serialPortTransmitter" +blo "34600,29400" +) +) +gi *76 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "34000,30800,49500,35300" +st "Generic Declarations + +baudRateDivide positive 2083 +dataBitNb positive 8 +stopBitNb positive 1 +" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +(GiElement +name "baudRateDivide" +type "positive" +value "2083" +) +(GiElement +name "dataBitNb" +type "positive" +value "8" +) +(GiElement +name "stopBitNb" +type "positive" +value "1" +) +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*77 (Grouping +uid 16,0 +optionalChildren [ +*78 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,52400,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*79 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*80 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,52400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*81 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,35800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*82 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,66400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*83 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,72800,45000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*84 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "38000,44500,47000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*85 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,35200,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*86 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,35800,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*87 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,46400,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *88 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*89 (Text +uid 49,0 +va (VaSet +font "courier,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*90 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,18600,4000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "412,1239,1307,1980" +viewArea "-1900,-900,58580,50400" +cachedDiagramExtent "0,0,73000,49000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 49 +yMargin 49 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "Letter (8.5\" x 11\")" +windowsPaperName "A4" +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,9,0" +) +xt "200,200,2200,1100" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "courier,9,1" +) +xt "1000,1000,4400,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,35000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "courier,9,1" +) +xt "22600,14800,27400,16000" +st "" +blo "22600,15800" +) +second (Text +va (VaSet +font "courier,9,1" +) +xt "22600,16000,25900,17200" +st "" +blo "22600,17000" +) +) +gi *91 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *92 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,5800,5400,6800" +st "Declarations" +blo "0,6600" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,6800,2700,7800" +st "Ports:" +blo "0,7600" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,13200,2500,14100" +st "User:" +blo "0,13900" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,5800,5800,6800" +st "Internal User:" +blo "0,6600" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,14100,2000,14100" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,5800,0,5800" +tm "SyDeclarativeTextMgr" +) +) +lastUid 346,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/RS232_test/hdl/serialPortFIFO_tester_test.vhd b/Libs/RS232_test/hdl/serialPortFIFO_tester_test.vhd new file mode 100644 index 0000000..bbcaf84 --- /dev/null +++ b/Libs/RS232_test/hdl/serialPortFIFO_tester_test.vhd @@ -0,0 +1,211 @@ +ARCHITECTURE test OF serialPortFIFO_tester IS + -- reset and clock + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + -- RS232 speed + constant rs232Frequency: real := baudRate; + constant rs232Period: time := (1.0/rs232Frequency) * 1 sec; + constant rs232WriteInterval: time := 10*rs232Period; + -- RS232 Rx test + signal rs232OutString : string(1 to 32); + signal rs232SendOutString: std_uLogic; + signal rs232SendOutDone: std_uLogic; + signal rs232OutByte: character; + signal rs232SendOutByte: std_uLogic; + signal rs232OutByteReturned: std_ulogic_vector(rxData'range); + -- RS232 Tx test + signal rs232InString : string(1 to 32); + signal rs232SendInString: std_uLogic; + signal rs232SendInDone: std_uLogic; + signal rs232InByte: character; + signal rs232InByteReturned: character; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- RS232 Rx test + process + begin + rs232SendOutString <= '0'; + wait for 4*rs232Period; + + rs232OutString <= "test 1 "; + rs232SendOutString <= '1', '0' after 1 ns; + wait until rs232SendOutDone = '1'; + wait for rs232WriteInterval; + + rs232OutString <= "test 2 "; + rs232SendOutString <= '1', '0' after 1 ns; + wait until rs232SendOutDone = '1'; + wait for rs232WriteInterval; + + rs232OutString <= "test 3 "; + rs232SendOutString <= '1', '0' after 1 ns; + wait until rs232SendOutDone = '1'; + wait for rs232WriteInterval; + + rs232OutString <= "test 4 "; + rs232SendOutString <= '1', '0' after 1 ns; + wait until rs232SendOutDone = '1'; + wait for rs232WriteInterval; + + wait; + end process; + + readRxFifo: process + begin + rxRd <= '0'; + wait until falling_edge(rxEmpty); + rxRd <= '1'; + wait for clockPeriod; + rs232OutByteReturned <= rxData; + end process readRxFifo; + + + ------------------------------------------------------------------------------ + -- RS232 Tx test + process + begin + rs232SendInString <= '0'; + wait for 4*rs232Period; + + rs232InString <= "hello 1 "; + rs232SendInString <= '1', '0' after 1 ns; + wait until rs232SendInDone = '1'; + wait for rs232WriteInterval; + + rs232InString <= "hello 2 "; + rs232SendInString <= '1', '0' after 1 ns; + wait until rs232SendInDone = '1'; + wait for rs232WriteInterval; + + rs232InString <= "hello 3 "; + rs232SendInString <= '1', '0' after 1 ns; + wait until rs232SendInDone = '1'; + wait for rs232WriteInterval; + + rs232InString <= "hello 4 "; + rs232SendInString <= '1', '0' after 1 ns; + wait until rs232SendInDone = '1'; + wait for rs232WriteInterval; + + wait; + end process; + + --============================================================================ + -- RS232 send + rsSendSerialString: process + constant rs232BytePeriod : time := 15*rs232Period; + variable commandRight: natural; + begin + + rs232SendOutByte <= '0'; + rs232SendOutDone <= '0'; + + wait until rising_edge(rs232SendOutString); + + commandRight := rs232OutString'right; + while rs232OutString(commandRight) = ' ' loop + commandRight := commandRight-1; + end loop; + + for index in rs232OutString'left to commandRight loop + rs232OutByte <= rs232OutString(index); + rs232SendOutByte <= '1', '0' after 1 ns; + wait for rs232BytePeriod; + end loop; + + rs232OutByte <= cr; + rs232SendOutByte <= '1', '0' after 1 ns; + wait for rs232BytePeriod; + + rs232SendOutDone <= '1'; + wait for 1 ns; + + end process rsSendSerialString; + + rsSendSerialByte: process + variable txData: unsigned(7 downto 0); + begin + RxD <= '1'; + + wait until rising_edge(rs232SendOutByte); + txData := to_unsigned(character'pos(rs232OutByte), txData'length); + + RxD <= '0'; + wait for rs232Period; + + for index in txData'reverse_range loop + RxD <= txData(index); + wait for rs232Period; + end loop; + + end process rsSendSerialByte; + + rsSendParallelString: process + variable commandRight: natural; + begin + + rs232SendInDone <= '0'; + txWr <= '0'; + + wait until rising_edge(rs232SendInString); + + commandRight := rs232OutString'right; + while rs232InString(commandRight) = ' ' loop + commandRight := commandRight-1; + end loop; + + wait until rising_edge(clock_int); + for index in rs232InString'left to commandRight loop + wait until rising_edge(clock_int); + while txFull = '1' loop + txWr <= '0'; + wait until rising_edge(clock_int); + end loop; + rs232InByte <= rs232InString(index); + txWr <= '1'; + end loop; + wait until rising_edge(clock_int); + + while txFull = '1' loop + txWr <= '0'; + wait until rising_edge(clock_int); + end loop; + rs232InByte <= cr; + txWr <= '1'; + wait until rising_edge(clock_int); + txWr <= '0'; + + rs232SendInDone <= '1'; + wait for 1 ns; + + end process rsSendParallelString; + + txData <= std_ulogic_vector(to_unsigned(character'pos(rs232InByte), txData'length)); + + ------------------------------------------------------------------------------ + -- RS232 receive + rsReceiveByte: process + variable rxData: unsigned(7 downto 0); + begin + wait until falling_edge(TxD); + + wait for 1.5 * rs232Period; + + for index in rxData'reverse_range loop + rxData(index) := TxD; + wait for rs232Period; + end loop; + + rs232InByteReturned <= character'val(to_integer(rxData)); + + end process rsReceiveByte; + +END ARCHITECTURE test; diff --git a/Libs/RS232_test/hdl/serialPortTransmitter_tester_test.vhd b/Libs/RS232_test/hdl/serialPortTransmitter_tester_test.vhd new file mode 100644 index 0000000..a145049 --- /dev/null +++ b/Libs/RS232_test/hdl/serialPortTransmitter_tester_test.vhd @@ -0,0 +1,42 @@ +-- restart -f ; run 34 ms + +ARCHITECTURE test OF serialPortTransmitter_tester IS + -- reset and clock + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + -- Tx test + constant rs232Frequency: real := baudRate; + constant rs232Period: time := (1.0/rs232Frequency) * 1 sec; + constant rs232WriteInterval: time := 20*rs232Period; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- Tx test + process + begin + + dataIn <= (others => '0'); + send <= '0'; + wait for rs232Period; + + for index in 0 to 2**dataBitNb-1 loop + dataIn <= std_ulogic_vector(to_unsigned(index, dataIn'length)); + wait until rising_edge(clock_int); + send <= '1'; + wait until rising_edge(clock_int); + send <= '0'; + wait for rs232WriteInterval; + end loop; + + wait; + + end process; + +END ARCHITECTURE test; diff --git a/Libs/RS232_test/hdl/uvmRs232Driver_sim.vhd b/Libs/RS232_test/hdl/uvmRs232Driver_sim.vhd new file mode 100644 index 0000000..d3de233 --- /dev/null +++ b/Libs/RS232_test/hdl/uvmRs232Driver_sim.vhd @@ -0,0 +1,129 @@ +LIBRARY std; + USE std.TEXTIO.all; +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE RTL OF uvmRs232Driver IS + -- parameters + signal baudRate_int: real; + signal baudPeriod, characterPeriod: time; + constant uartDataBitNb: positive := 9; + constant maxStringLength: positive := driverTransaction'length; + -- Tx signals + signal outString : string(1 to maxStringLength); + signal sendString: std_uLogic := '0'; + signal outChar: character; + signal sendChar: std_ulogic := '0'; + signal sendParity, parityInit: std_ulogic := '0'; + -- debug + signal outChar_debug: unsigned(uartDataBitNb-1 downto 0); + + +BEGIN + ------------------------------------------------------------------------------ + -- interpret transaction + interpretTransaction: process + variable myLine : line; + variable commandPart : line; + variable baudRate_nat : natural; + file dataFile : text; + variable dataLine : line; + begin + wait on driverTransaction; + write(myLine, driverTransaction); + rm_side_separators(myLine); + read_first(myLine, commandPart); + if commandPart.all = "uart_baud" then + read(myLine, baudRate_nat); + baudRate_int <= real(baudRate_nat); + elsif commandPart.all = "uart_parity" then + sendParity <= '0'; + parityInit <= '0'; + if myLine.all = "even" then + sendParity <= '1'; + elsif myLine.all = "odd" then + sendParity <= '1'; + parityInit <= '1'; + end if; + elsif commandPart.all = "uart_send" then + outString <= pad(myLine.all, outString'length); + sendString <= '1', '0' after 1 ns; + elsif commandPart.all = "uart_send_file" then + file_open(dataFile, "$SIMULATION_DIR/" & myLine.all, read_mode); + while not endFile(dataFile) loop + readLine(dataFile, dataLine); +--print(dataLine.all); + outString <= pad(dataLine.all, outString'length); + sendString <= '1', '0' after 1 ns; + wait for (dataLine'length+8) * characterPeriod; + end loop; + file_close(dataFile); + end if; + deallocate(myLine); + end process interpretTransaction; + + baudRate <= baudRate_int; + baudPeriod <= 1.0/baudRate_int * 1 sec; + characterPeriod <= 15*baudPeriod; + + --============================================================================ + -- send string on RxD line + uartSendString: process + variable outStringRight: natural; + begin + -- wait for command + sendChar <= '0'; + wait until rising_edge(sendString); + -- find string length + outStringRight := outString'right; + while outString(outStringRight) = ' ' loop + outStringRight := outStringRight-1; + end loop; + -- send characters + for index in outString'left to outStringRight loop + outChar <= outString(index); +--print(sprintf("%2X", character'pos(outChar))); + sendChar <= '1', '0' after 1 ns; + wait for characterPeriod; + end loop; + -- send carriage return + outChar <= cr; + sendChar <= '1', '0' after 1 ns; + wait for characterPeriod; + + end process uartSendString; + + ------------------------------------------------------------------------------ + -- send character on RxD line + uartSendChar: process + variable outChar_unsigned: unsigned(uartDataBitNb-1 downto 0); + begin + -- wait for trigger + RxD <= '1'; + wait until rising_edge(sendChar); + -- transform char to bit vector + outChar_unsigned := to_unsigned( + character'pos(outChar), + outChar_unsigned'length + ); + outChar_unsigned(outChar_unsigned'high) := '1'; + if sendParity = '1' then + outChar_unsigned(outChar_unsigned'high) := parityInit; + for index in uartDataBitNb-2 downto 0 loop + outChar_unsigned(outChar_unsigned'high) + := outChar_unsigned(outChar_unsigned'high) + xor outChar_unsigned(index); + end loop; + end if; + outChar_debug <= outChar_unsigned; + -- send start bit + RxD <= '0'; + wait for baudPeriod; + -- send data bits + for index in outChar_unsigned'reverse_range loop + RxD <= outChar_unsigned(index); + wait for baudPeriod; + end loop; + end process uartSendChar; + +END ARCHITECTURE RTL; diff --git a/Libs/RS232_test/hdl/uvmRs232Monitor_sim.vhd b/Libs/RS232_test/hdl/uvmRs232Monitor_sim.vhd new file mode 100644 index 0000000..f0c217f --- /dev/null +++ b/Libs/RS232_test/hdl/uvmRs232Monitor_sim.vhd @@ -0,0 +1,79 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE RTL OF uvmRs232Monitor IS + + constant uartDataBitNb: positive := 8; + signal baudPeriod: time; + signal rxWord, txWord: natural; + signal startup, rxReceived, txReceived: std_ulogic; + +BEGIN + ------------------------------------------------------------------------------ + baudPeriod <= 1.0/baudRate * 1 sec; + + ------------------------------------------------------------------------------ + -- receive RxD + receiveRxD: process + variable rxData: unsigned(uartDataBitNb-1 downto 0); + begin + rxReceived <= '0'; + -- start bit + wait until falling_edge(RxD); + wait for 1.5 * baudPeriod; + -- data bits + for index in rxData'reverse_range loop + rxData(index) := RxD; + wait for baudPeriod; + end loop; + -- store information + rxWord <= to_integer(rxData); + rxReceived <= '1'; + wait for 0 ns; + end process receiveRxD; + + ------------------------------------------------------------------------------ + -- receive RxD + receiveTxD: process + variable txData: unsigned(uartDataBitNb-1 downto 0); + begin + txReceived <= '0'; + -- start bit + wait until falling_edge(TxD); + wait for 1.5 * baudPeriod; + -- data bits + for index in txData'reverse_range loop + txData(index) := TxD; + wait for baudPeriod; + end loop; + -- store information + txWord <= to_integer(txData); + txReceived <= '1'; + wait for 0 ns; + end process receiveTxD; + + --============================================================================ + -- monitor acesses + startup <= '1', '0' after 1 ns; + + reportBusAccess: process(startup, rxReceived, txReceived) + begin + if startup = '1' then + monitorTransaction <= pad( + "idle", + monitorTransaction'length + ); + elsif rising_edge(rxReceived) then + monitorTransaction <= pad( + reportStart & " sent " & sprintf("%02X", rxWord), + monitorTransaction'length + ); + elsif rising_edge(txReceived) then + monitorTransaction <= pad( + reportStart & " received " & sprintf("%02X", txWord), + monitorTransaction'length + ); + end if; + end process reportBusAccess; + +END ARCHITECTURE RTL; diff --git a/Libs/RS232_test/hdl/uvmRs232_tester_test.vhd b/Libs/RS232_test/hdl/uvmRs232_tester_test.vhd new file mode 100644 index 0000000..4457cc9 --- /dev/null +++ b/Libs/RS232_test/hdl/uvmRs232_tester_test.vhd @@ -0,0 +1,92 @@ +LIBRARY Common_test; + USE Common_test.testUtils.all; + +ARCHITECTURE test OF uvmRs232_tester IS + -- reset and clock + constant clockPeriod: time := (1.0/clockFrequency) * 1 sec; + signal clock_int: std_uLogic := '1'; + -- RS232 speed + constant rs232Period: time := (1.0/rs232BaudRate) * 1 sec; + -- RS232 Rx + signal rs232RxChar : character := ' '; + -- RS232 Tx + signal rs232TxString : string(1 to 32); + signal rs232SendString: std_uLogic; + signal rs232SendDone: std_uLogic; + +BEGIN + ------------------------------------------------------------------------------ + -- reset and clock + reset <= '1', '0' after 2*clockPeriod; + + clock_int <= not clock_int after clockPeriod/2; + clock <= transport clock_int after clockPeriod*9/10; + + ------------------------------------------------------------------------------ + -- Tx sequence + txSequence : process + begin + rs232SendString <= '0'; + rs232TxString <= (others => ' '); + wait for 500 us; + -- send 'Hi' + rs232TxString <= pad("Hi", rs232TxString'length); + rs232SendString <= '1', '0' after 1 ns; + wait until rs232SendDone = '1'; + -- end of transmission + wait; + end process txSequence; + + --============================================================================ + -- RS232 Rx + storeRxByte: process(clock_int) + begin + if rising_edge(clock_int) then + if dataValid = '1' then + rs232RxChar <= character'val(to_integer(unsigned(dataOut))); + end if; + end if; + end process storeRxByte; + + ------------------------------------------------------------------------------ + -- RS232 Tx + rsSendString: process + constant rs232CharPeriod : time := 15*rs232Period; + variable outStringRight: natural; + variable outchar: character; + begin + -- wait for command + send <= '0'; + dataIn <= (others => '0'); + rs232SendDone <= '0'; + wait until rising_edge(rs232SendString); + -- find string length + outStringRight := rs232TxString'right; + while rs232TxString(outStringRight) = ' ' loop + outStringRight := outStringRight-1; + end loop; + -- send characters + for index in rs232TxString'left to outStringRight loop + outchar := rs232TxString(index); + dataIn <= std_ulogic_vector(to_unsigned( + character'pos(outchar), dataIn'length + )); + wait until rising_edge(clock_int); + send <= '1', '0' after clockPeriod; + wait for rs232CharPeriod; + end loop; + -- send carriage return + outchar := cr; + dataIn <= std_ulogic_vector(to_unsigned( + character'pos(outchar), dataIn'length + )); + wait until rising_edge(clock_int); + send <= '1', '0' after clockPeriod; + wait for rs232CharPeriod; + -- signal end of sending + rs232SendDone <= '1'; + wait for 1 ns; + + end process rsSendString; + +END ARCHITECTURE test; diff --git a/Libs/RS232_test/hds/.hdlsidedata/_serialPortFIFO_tester_test.vhd._fpf b/Libs/RS232_test/hds/.hdlsidedata/_serialPortFIFO_tester_test.vhd._fpf new file mode 100644 index 0000000..80b1639 --- /dev/null +++ b/Libs/RS232_test/hds/.hdlsidedata/_serialPortFIFO_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2008 diff --git a/Libs/RS232_test/hds/.hdlsidedata/_serialPortTransmitter_tester_test.vhd._fpf b/Libs/RS232_test/hds/.hdlsidedata/_serialPortTransmitter_tester_test.vhd._fpf new file mode 100755 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RS232_test/hds/.hdlsidedata/_serialPortTransmitter_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232Driver_sim.vhd._fpf b/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232Driver_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232Driver_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232Monitor_sim.vhd._fpf b/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232Monitor_sim.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232Monitor_sim.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232_tester_test.vhd._fpf b/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232_tester_test.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RS232_test/hds/.hdlsidedata/_uvmRs232_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RS232_test/hds/_serialportfifo_tb._epf b/Libs/RS232_test/hds/_serialportfifo_tb._epf new file mode 100644 index 0000000..8e1dd6d --- /dev/null +++ b/Libs/RS232_test/hds/_serialportfifo_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom serial@port@f@i@f@o_tb/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/RS232_test/hds/_serialportfifo_tester._epf b/Libs/RS232_test/hds/_serialportfifo_tester._epf new file mode 100644 index 0000000..9cfc040 --- /dev/null +++ b/Libs/RS232_test/hds/_serialportfifo_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom serialPortFIFO_tester_test.vhd diff --git a/Libs/RS232_test/hds/_serialporttransmitter_tb._epf b/Libs/RS232_test/hds/_serialporttransmitter_tb._epf new file mode 100755 index 0000000..69fb538 --- /dev/null +++ b/Libs/RS232_test/hds/_serialporttransmitter_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom serial@port@transmitter_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/RS232_test/hds/_serialporttransmitter_tester._epf b/Libs/RS232_test/hds/_serialporttransmitter_tester._epf new file mode 100755 index 0000000..9cb3368 --- /dev/null +++ b/Libs/RS232_test/hds/_serialporttransmitter_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom serialPortTransmitter_tester_test.vhd diff --git a/Libs/RS232_test/hds/_uvmrs232_tb._epf b/Libs/RS232_test/hds/_uvmrs232_tb._epf new file mode 100644 index 0000000..52115b7 --- /dev/null +++ b/Libs/RS232_test/hds/_uvmrs232_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom uvm@rs232_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/RS232_test/hds/_uvmrs232_tester._epf b/Libs/RS232_test/hds/_uvmrs232_tester._epf new file mode 100644 index 0000000..c4afa6f --- /dev/null +++ b/Libs/RS232_test/hds/_uvmrs232_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom test +DEFAULT_FILE atom uvmRs232_tester_test.vhd diff --git a/Libs/RS232_test/hds/_uvmrs232agenthw._epf b/Libs/RS232_test/hds/_uvmrs232agenthw._epf new file mode 100644 index 0000000..afd781a --- /dev/null +++ b/Libs/RS232_test/hds/_uvmrs232agenthw._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom uvm@rs232@agent@hw/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/Libs/RS232_test/hds/_uvmrs232driver._epf b/Libs/RS232_test/hds/_uvmrs232driver._epf new file mode 100644 index 0000000..62531b0 --- /dev/null +++ b/Libs/RS232_test/hds/_uvmrs232driver._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE 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17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *100 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*101 (Text +uid 49,0 +va (VaSet +font "courier,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*102 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,18600,4000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "30,73,1194,622" +viewArea "-500,-500,84550,36130" +cachedDiagramExtent "0,0,75500,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg 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(Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,1500,1650" +st "In0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,8,0" +) +xt "0,750,3500,1650" +st "Buffer0" +blo "0,1450" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *104 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "42000,11000,44500,11900" +st "User:" +blo "42000,11700" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "44000,11900,44000,11900" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 415,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/RS232_test/hds/serial@port@transmitter_tb/_struct.bd._fpf b/Libs/RS232_test/hds/serial@port@transmitter_tb/_struct.bd._fpf new file mode 100755 index 0000000..f9fd1de --- /dev/null +++ b/Libs/RS232_test/hds/serial@port@transmitter_tb/_struct.bd._fpf @@ -0,0 +1,9 @@ +ARCHITECTURES list { + {serialporttransmitter_tb struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/serialPortTransmitter.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseCLI 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/Libs/RS232_test/hds/serial@port@transmitter_tb/struct.bd b/Libs/RS232_test/hds/serial@port@transmitter_tb/struct.bd new file mode 100644 index 0000000..c23de7a --- /dev/null +++ b/Libs/RS232_test/hds/serial@port@transmitter_tb/struct.bd @@ -0,0 +1,2995 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "RS232_test" +duName "serialPortTransmitter_tester" +elements [ +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +(GiElement +name "baudRate" +type "real" +value "baudRate" +) +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "stopBitNb" +type "positive" +value "stopBitNb" +) +] +mwi 0 +uid 1774,0 +) +(Instance +name "I_DUT" +duLibraryName "RS232" +duName "serialPortTransmitter" +elements [ +(GiElement +name "baudRateDivide" +type "positive" +value "integer(clockFrequency/baudRate)" +) +(GiElement +name "dataBitNb" +type "positive" +value "dataBitNb" +) +(GiElement +name "stopBitNb" +type "positive" +value "stopBitNb" +) +] +mwi 0 +uid 7225,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.3 (Build 4)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/Projets/Comet_Camera/FPGA/Prefs/../Libs/RS232_test/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/Projets/Comet_Camera/FPGA/Prefs/../Libs/RS232_test/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/Projets/Comet_Camera/FPGA/Prefs/../Libs/RS232_test/hds/serial@port@transmitter_tb/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/Projets/Comet_Camera/FPGA/Prefs/../Libs/RS232_test/hds/serial@port@transmitter_tb/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/Projets/Comet_Camera/FPGA/Prefs/../Libs/RS232_test/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Projets/Comet_Camera/FPGA/Prefs/../Libs/RS232_test/hds/serial@port@transmitter_tb" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Projets/Comet_Camera/FPGA/Prefs/../Libs/RS232_test/hds/serialPortTransmitter_tb" +) +(vvPair +variable "date" +value "08/07/23" +) +(vvPair +variable "day" +value "Mon" +) +(vvPair +variable "day_long" +value "Monday" +) +(vvPair +variable "dd" +value "07" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "serialPortTransmitter_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "08/07/23" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Hyperion" +) +(vvPair +variable "graphical_source_time" +value "15:47:43" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Hyperion" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "RS232_test" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\ELN_labs\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/RS232_test" +) +(vvPair +variable "mm" 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+library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "NUMERIC_STD" +) +] +instances [ +(Instance +name "I_file2trans" +duLibraryName "UVM" +duName "driverControl" +elements [ +(GiElement +name "driverFileSpec" +type "string" +value "driverFileSpec" +) +(GiElement +name "verbosity" +type "natural" +value "driverVerbosity" +) +] +mwi 0 +uid 1172,0 +) +(Instance +name "U_trans2File" +duLibraryName "UVM" +duName "monitorSupervision" +elements [ +(GiElement +name "monitorFileSpec" +type "string" +value "monitorFileSpec" +) +(GiElement +name "verbosity" +type "natural" +value "monitorVerbosity" +) +] +mwi 0 +uid 1186,0 +) +(Instance +name "I_mon" +duLibraryName "RS232_test" +duName "uvmRs232Monitor" +elements [ +] +mwi 0 +uid 1321,0 +) +(Instance +name "I_driv" +duLibraryName "RS232_test" +duName "uvmRs232Driver" +elements [ +] +mwi 0 +uid 1486,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.3 (Build 4)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds/uvm@rs232@agent@hw/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds/uvm@rs232@agent@hw/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds/uvm@rs232@agent@hw" +) +(vvPair +variable "d_logical" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds/uvmRs232AgentHw" +) +(vvPair +variable "date" +value "03/01/22" +) +(vvPair +variable "day" +value "Tue" +) +(vvPair +variable "day_long" +value "Tuesday" +) +(vvPair +variable "dd" +value "01" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "uvmRs232AgentHw" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "03/01/22" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphrodite" +) +(vvPair +variable "graphical_source_time" +value "08:51:20" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphrodite" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "RS232_test" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/RS232_test" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "uvmRs232AgentHw" +) +(vvPair +variable "month" +value "Mar" +) +(vvPair +variable "month_long" +value "March" +) +(vvPair +variable "p" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds/uvm@rs232@agent@hw/struct.bd" +) +(vvPair +variable "p_logical" +value "/home/francois/Documents/HEVs/Projects/CometCamera/FPGA/Prefs/../Libs/RS232_test/hds/uvmRs232AgentHw/struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_AsmPath" +value "$HDS_LIBS_DIR\\NanoBlaze\\hdl" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "08:51:20" +) +(vvPair +variable "unit" +value "uvmRs232AgentHw" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2019.3 (Build 4)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "72000,73000,89000,74000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "72200,73000,88400,74000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*3 (CommentText +uid 14,0 +shape (Rectangle +uid 15,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "89000,69000,93000,70000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 16,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt 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"Declarations" +blo "0,10200" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,10400,2700,11400" +st "Ports:" +blo "0,11200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,15000,2500,15900" +st "User:" +blo "0,15700" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,9400,5800,10400" +st "Internal User:" +blo "0,10200" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,15900,2000,15900" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,9400,0,9400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 3200,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/Libs/RS232_test/hds/uvm@rs232_tb/struct.bd b/Libs/RS232_test/hds/uvm@rs232_tb/struct.bd new file mode 100644 index 0000000..5bf3b06 --- /dev/null +++ b/Libs/RS232_test/hds/uvm@rs232_tb/struct.bd @@ -0,0 +1,3774 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "NUMERIC_STD" +) +] +instances [ +(Instance +name "I_tester" +duLibraryName "RS232_test" +duName "uvmRs232_tester" +elements [ +(GiElement +name "clockFrequency" +type "real" +value "clockFrequency" +) +(GiElement +name "rs232BitNb" +type "positive" +value "rs232BitNb" +) +(GiElement +name "rs232BaudRate" +type "positive" +value "rs232BaudRate" +) +] +mwi 0 +uid 1426,0 +) +(Instance +name "I_Rx" +duLibraryName "RS232" +duName "serialPortReceiver" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "rs232BitNb" +) +(GiElement +name "baudRateDivide" +type "positive" +value "integer(clockFrequency/rs232BaudRate + 0.5)" +) +] +mwi 0 +uid 1480,0 +) +(Instance +name "I_Tx" +duLibraryName "RS232" +duName "serialPortTransmitter" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "rs232BitNb" +) +(GiElement +name "baudRateDivide" +type "positive" +value "integer(clockFrequency/rs232BaudRate + 0.5)" +) +] +mwi 0 +uid 1514,0 +) +(Instance +name "U_DUT" +duLibraryName "RS232_test" +duName "uvmRs232AgentHw" +elements [ +(GiElement +name "driverVerbosity" +type "integer" +value "uvmDriverVerbosity" +) +(GiElement +name "driverFileSpec" +type "string" +value "uvmDriverFileSpec" +) +(GiElement +name "monitorVerbosity" +type "integer" +value "uvmMonitorVerbosity" +) +(GiElement +name "monitorFileSpec" +type "string" +value "uvmMonitorFileSpec" +) +] +mwi 0 +uid 1724,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.3 (Build 4)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds/uvm@rs232_tb/struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds/uvm@rs232_tb/struct.bd.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "asm_file" +value "beamer.asm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds/uvm@rs232_tb" +) +(vvPair +variable "d_logical" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds/uvmRs232_tb" +) +(vvPair +variable "date" +value "03/01/22" +) +(vvPair +variable "day" +value "Tue" +) +(vvPair +variable "day_long" +value "Tuesday" +) +(vvPair +variable "dd" +value "01" +) +(vvPair +variable "designName" +value "$DESIGN_NAME" +) +(vvPair +variable "entity_name" +value "uvmRs232_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "francois" +) +(vvPair +variable "graphical_source_date" +value "03/01/22" +) +(vvPair +variable "graphical_source_group" +value "francois" +) +(vvPair +variable "graphical_source_host" +value "Aphrodite" +) +(vvPair +variable "graphical_source_time" +value "08:18:54" +) +(vvPair +variable "group" +value "francois" +) +(vvPair +variable "host" +value "Aphrodite" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "RS232_test" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/RS232_test" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "uvmRs232_tb" +) +(vvPair +variable "month" +value "Mar" +) +(vvPair +variable "month_long" +value "March" +) +(vvPair +variable "p" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds/uvm@rs232_tb/struct.bd" +) +(vvPair +variable "p_logical" +value "/home/francois/Favorites/SEm_local/SEm_labs/05-Morse/../Libs/RS232_test/hds/uvmRs232_tb/struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_AsmPath" +value "$HDS_LIBS_DIR\\NanoBlaze\\hdl" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "$ISE_HOME" +) +(vvPair +variable "task_ISEPath" +value "$ISE_SCRATCH_WORK_DIR" +) +(vvPair +variable "task_ModelSimPath" +value "/usr/opt/Modelsim/modeltech/bin" +) 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"serialPortTransmitter" +blo "60600,25700" +tm "CptNameMgr" +) +*36 (Text +uid 1519,0 +va (VaSet +font "courier,9,1" +) +xt "60600,26200,62600,27100" +st "I_Tx" +blo "60600,26900" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 1520,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 1521,0 +text (MLText +uid 1522,0 +va (VaSet +font "courier,8,0" +) +xt "60000,28000,99500,29800" +st "dataBitNb = rs232BitNb ( positive ) +baudRateDivide = integer(clockFrequency/rs232BaudRate + 0.5) ( positive ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "rs232BitNb" +) +(GiElement +name "baudRateDivide" +type "positive" +value "integer(clockFrequency/rs232BaudRate + 0.5)" +) +] +) +viewicon (ZoomableIcon +uid 1523,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "60250,22250,61750,23750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*37 (Net +uid 1524,0 +decl (Decl +n "RxD" +t "std_uLogic" +o 1 +suid 24,0 +) +declText (MLText +uid 1525,0 +va (VaSet +font "courier,8,0" +) +xt "2000,19100,17000,20000" +st "SIGNAL RxD : std_uLogic" +) +) +*38 (Net +uid 1530,0 +decl (Decl +n "TxD" +t "std_uLogic" +o 2 +suid 25,0 +) +declText (MLText +uid 1531,0 +va (VaSet +font "courier,8,0" +) +xt "2000,20000,17000,20900" +st "SIGNAL TxD : std_uLogic" +) +) +*39 (Net +uid 1536,0 +decl (Decl +n "dataValid" +t "std_ulogic" +o 7 +suid 26,0 +) +declText (MLText +uid 1537,0 +va (VaSet +font "courier,8,0" +) +xt "2000,24500,17000,25400" +st "SIGNAL dataValid : std_ulogic" +) +) +*40 (Net +uid 1544,0 +decl (Decl +n "dataOut" +t "std_ulogic_vector" +b "(rs232BitNb-1 DOWNTO 0)" +o 6 +suid 27,0 +) +declText (MLText +uid 1545,0 +va (VaSet +font "courier,8,0" +) +xt "2000,23600,32000,24500" +st "SIGNAL dataOut : std_ulogic_vector(rs232BitNb-1 DOWNTO 0)" +) +) +*41 (Net +uid 1552,0 +decl (Decl +n "busy" +t "std_ulogic" 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+constant uvmDriverFileSpec: string := \"$SIMULATION_DIR/uartDriver.txt\"; +constant uvmMonitorFileSpec: string := \"$SIMULATION_DIR/uartMonitor.txt\";" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "courier,8,1" +) +xt "0,18200,8500,19100" +st "Diagram Signals:" +blo "0,18900" +) +postUserLabel (Text +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,7400,5500,8300" +st "Post User:" +blo "0,8100" +) +postUserText (MLText +uid 8,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,7400,0,7400" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 30,0 +usingSuid 1 +emptyRow *92 (LEmptyRow +) +uid 54,0 +optionalChildren [ +*93 (RefLabelRowHdr +) +*94 (TitleRowHdr +) +*95 (FilterRowHdr +) +*96 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*97 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*98 (GroupColHdr +tm "GroupColHdrMgr" +) +*99 (NameColHdr +tm "BlockDiagramNameColHdrMgr" +) +*100 (ModeColHdr +tm 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ieee.std_logic_1164.all; + USE ieee.NUMERIC_STD.all;" +tm "PackageList" +) +] +) +windowSize "24,390,1043,1080" +viewArea "-500,-500,70690,47560" +cachedDiagramExtent "0,0,99000,49000" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Verdana,9,1" +) +xt "1000,1000,5000,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "RS232_test" +entityName "uvmRs232_tb" +viewName "struct.bd" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,44000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,14800,32200,16000" +st "" +blo "26800,15800" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,16000,30700,17200" +st "" +blo "26800,17000" +) +) +gi *94 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *95 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,0,49400,1200" +st "Declarations" +blo "42000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,1200,45700,2400" +st "Ports:" +blo "42000,2200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,8000,45200,9200" +st "User:" +blo "42000,9000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,50200,1200" +st "Internal User:" +blo "42000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,44000,9200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 542,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/RS232_test/sim/serialPortTransmitter.do b/Libs/RS232_test/sim/serialPortTransmitter.do new file mode 100644 index 0000000..81ab60a --- /dev/null +++ b/Libs/RS232_test/sim/serialPortTransmitter.do @@ -0,0 +1,32 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /serialporttransmitter_tb/clock +add wave -noupdate /serialporttransmitter_tb/reset +add wave -noupdate -divider Controls +add wave -noupdate -radix hexadecimal -radixshowbase 0 /serialporttransmitter_tb/dataIn +add wave -noupdate /serialporttransmitter_tb/send +add wave -noupdate -divider Internals +add wave -noupdate /serialporttransmitter_tb/I_DUT/dividerCounterReset +add wave -noupdate /serialporttransmitter_tb/I_DUT/txSendingByte +add wave -noupdate /serialporttransmitter_tb/I_DUT/txSendingByteAndStop +add wave -noupdate -divider {Serial out} +add wave -noupdate /serialporttransmitter_tb/busy +add wave -noupdate /serialporttransmitter_tb/TxD +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {33909547739 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 142 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ms +update +WaveRestoreZoom {0 ps} {315 us} diff --git a/Libs/RS232_test/sim/uartDriver.txt b/Libs/RS232_test/sim/uartDriver.txt new file mode 100644 index 0000000..f3be4de --- /dev/null +++ b/Libs/RS232_test/sim/uartDriver.txt @@ -0,0 +1,9 @@ +at 1 us +info setting baud rate +uart_baud 115200 + +at 100 us +uart_send Hello + +wait 1 ms +uart_send world diff --git a/Libs/RS232_test/sim/uvmRs232.do b/Libs/RS232_test/sim/uvmRs232.do new file mode 100644 index 0000000..f509539 --- /dev/null +++ b/Libs/RS232_test/sim/uvmRs232.do @@ -0,0 +1,37 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group {Reset and clock} /uvmrs232_tb/reset +add wave -noupdate -group {Reset and clock} /uvmrs232_tb/clock +add wave -noupdate -expand -group {UART signals} /uvmrs232_tb/RxD +add wave -noupdate -expand -group {UART signals} /uvmrs232_tb/TxD +add wave -noupdate -expand -group {UART Tx} /uvmrs232_tb/I_tester/rs232TxString +add wave -noupdate -expand -group {UART Tx} /uvmrs232_tb/I_tester/rs232SendString +add wave -noupdate -expand -group {UART Tx} /uvmrs232_tb/dataIn +add wave -noupdate -expand -group {UART Tx} /uvmrs232_tb/send +add wave -noupdate -expand -group {UART Rx} /uvmrs232_tb/U_DUT/I_driv/outString +add wave -noupdate -expand -group {UART Rx} /uvmrs232_tb/U_DUT/I_driv/sendString +add wave -noupdate -expand -group {UART Rx} /uvmrs232_tb/U_DUT/I_driv/outChar +add wave -noupdate -expand -group {UART Rx} /uvmrs232_tb/U_DUT/I_driv/sendChar +add wave -noupdate -expand -group {UART Rx} /uvmrs232_tb/dataOut +add wave -noupdate -expand -group {UART Rx} /uvmrs232_tb/dataValid +add wave -noupdate -expand -group {UART Rx} /uvmrs232_tb/I_tester/rs232RxChar +add wave -noupdate -expand -group Transactions /uvmrs232_tb/U_DUT/driverTransaction +add wave -noupdate -expand -group Transactions /uvmrs232_tb/U_DUT/monitorTransaction +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 247 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {2100 us} diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd b/Libs/RiscV/HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd new file mode 100644 index 0000000..64f7d5a --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd @@ -0,0 +1,18 @@ + +ARCHITECTURE rtl OF instrDecoder IS +BEGIN + + decode : process(op) + begin + case op is + when "0000011" => immSrc <= "00"; -- lw + when "0100011" => immSrc <= "01"; -- sw + when "0110011" => immSrc <= "--"; -- R-type + when "1100011" => immSrc <= "10"; -- beq + when "0010011" => immSrc <= "00"; -- l-type ALU + when "1101111" => immSrc <= "11"; -- jal + when others => immSrc <= "--"; -- unknwon + end case; + end process decode; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hdl/instructionForwarder_rtl.vhd b/Libs/RiscV/HEIRV32/MultiCycle/hdl/instructionForwarder_rtl.vhd new file mode 100644 index 0000000..6438c9b --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hdl/instructionForwarder_rtl.vhd @@ -0,0 +1,26 @@ + +ARCHITECTURE rtl OF instructionForwarder IS + signal lvec_irMem : std_ulogic_vector(readData'range); +BEGIN + +-- forwardIR : process(rst, clk) +-- begin +-- if rst = '1' then +-- lvec_irMem <= (others => '0'); +-- elsif rising_edge(clk) then +-- if en = '1' and IRWrite = '1' then +-- lvec_irMem <= readData; +-- end if; +-- end if; +-- end process forwardIR; + + forwardIR : process(readData, irWrite) + begin + if irWrite = '1' then + lvec_irMem <= readData; + end if; + end process forwardIR; + + instruction <= lvec_irMem; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/_controlunit._epf b/Libs/RiscV/HEIRV32/MultiCycle/hds/_controlunit._epf new file mode 100644 index 0000000..d61749d --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/_controlunit._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom control@unit/struct.bd diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/_heirv32_mc._epf b/Libs/RiscV/HEIRV32/MultiCycle/hds/_heirv32_mc._epf new file mode 100644 index 0000000..ec27f95 --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/_heirv32_mc._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 1 +DEFAULT_FILE atom heirv32_mc/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/_instrdecoder._epf b/Libs/RiscV/HEIRV32/MultiCycle/hds/_instrdecoder._epf new file mode 100644 index 0000000..bb7952a --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/_instrdecoder._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom instrDecoder_rtl.vhd diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/_instructiondatamemory._epf b/Libs/RiscV/HEIRV32/MultiCycle/hds/_instructiondatamemory._epf new file mode 100644 index 0000000..d4472ca --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/_instructiondatamemory._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom instruction@data@memory/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/_instructionforwarder._epf b/Libs/RiscV/HEIRV32/MultiCycle/hds/_instructionforwarder._epf new file mode 100644 index 0000000..8c24fdd --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/_instructionforwarder._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom instructionForwarder_rtl.vhd diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/_mainfsm._epf b/Libs/RiscV/HEIRV32/MultiCycle/hds/_mainfsm._epf new file mode 100644 index 0000000..d9c4b8f --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/_mainfsm._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom fsm +DEFAULT_FILE atom main@f@s@m/fsm.sm diff --git a/Libs/RiscV/HEIRV32/MultiCycle/hds/control@unit/struct.bd b/Libs/RiscV/HEIRV32/MultiCycle/hds/control@unit/struct.bd new file mode 100644 index 0000000..f822d73 --- /dev/null +++ b/Libs/RiscV/HEIRV32/MultiCycle/hds/control@unit/struct.bd @@ -0,0 +1,6095 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +instances [ +(Instance +name "U_0" +duLibraryName "gates" +duName "or2" +elements [ +(GiElement +name "delay" +type "time" +value "gateDelay" +) +] +mwi 0 +uid 395,0 +) +(Instance +name "U_1" +duLibraryName "gates" +duName "and2" +elements [ +(GiElement +name "delay" +type "time" +value "gateDelay" +) +] +mwi 0 +uid 420,0 +) +(Instance +name "U_instrDecoder" +duLibraryName "HEIRV32_MC" +duName "instrDecoder" +elements [ +] +mwi 0 +uid 955,0 +) +(Instance +name "U_mainFSM" +duLibraryName "HEIRV32_MC" +duName "mainFSM" +elements [ +] +mwi 0 +uid 1230,0 +) +(Instance +name "U_aluDecoder" +duLibraryName "HEIRV32" +duName "aluDecoder" +elements [ +(GiElement +name "g_tDec" +type "time" +value "25 ps" +) +] +mwi 0 +uid 1415,0 +) +] +libraryRefs [ +"ieee" +"gates" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\controlUnit" +) +(vvPair +variable "date" +value "04.11.2022" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "04" +) +(vvPair +variable "entity_name" +value "controlUnit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "04.11.2022" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "11:25:25" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "HEIRV32_MC" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/MultiCycle/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "controlUnit" +) +(vvPair +variable "month" +value "nov." +) +(vvPair +variable "month_long" +value "novembre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\control@unit\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\controlUnit\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "11:25:25" +) +(vvPair +variable "unit" +value "controlUnit" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 310,0 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"c_dataWidth" +) +(GiElement +name "delay" +type "time" +value "gateDelay" +) +] +) +viewicon (ZoomableIcon +uid 831,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "26250,81250,27750,82750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +disp 1 +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*27 (Net +uid 858,0 +decl (Decl +n "adr" +t "unsigned" +b "(c_dataWidth-1 DOWNTO 0)" +o 18 +suid 30,0 +) +declText (MLText +uid 859,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,20000,50500,20800" +st "SIGNAL adr : unsigned(c_dataWidth-1 DOWNTO 0)" +) +) +*28 (Net +uid 906,0 +lang 11 +decl (Decl +n "writeData" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 35 +suid 33,0 +) +declText (MLText +uid 907,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,33600,55000,34400" +st "SIGNAL writeData : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*29 (Net +uid 1112,0 +lang 11 +decl (Decl +n "memWrite" +t "std_ulogic" +o 27 +suid 36,0 +) +declText (MLText +uid 1113,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,27200,39000,28000" +st "SIGNAL memWrite : std_ulogic" +) +) +*30 (Net +uid 1162,0 +lang 11 +decl (Decl +n "IRWrite" +t "std_ulogic" +o 12 +suid 37,0 +) +declText (MLText +uid 1163,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,15200,39000,16000" +st "SIGNAL IRWrite : std_ulogic" +) +) +*31 (Net +uid 1172,0 +lang 11 +decl (Decl +n "data" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 20 +suid 38,0 +) +declText (MLText +uid 1173,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,21600,55000,22400" +st "SIGNAL data : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*32 (Net +uid 1310,0 +lang 11 +decl (Decl +n "oldPC" +t "std_ulogic_vector" +b "(c_dataWidth - 1 DOWNTO 0)" +o 28 +suid 44,0 +) +declText (MLText +uid 1311,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,28000,56000,28800" +st "SIGNAL oldPC : std_ulogic_vector(c_dataWidth - 1 DOWNTO 0)" +) +) +*33 (Net +uid 1362,0 +lang 11 +decl (Decl +n "zero" +t "std_ulogic" +o 36 +suid 46,0 +) +declText (MLText +uid 1363,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,34400,39000,35200" +st "SIGNAL zero : std_ulogic" +) +) +*34 (Net +uid 1376,0 +lang 11 +decl (Decl +n "resultSrc" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 32 +suid 48,0 +) +declText (MLText +uid 1377,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,31200,49000,32000" +st "SIGNAL resultSrc : std_ulogic_vector(1 DOWNTO 0)" +) +) +*35 (Net +uid 1388,0 +lang 11 +decl (Decl +n "ALUControl" +t "std_ulogic_vector" +b "(2 DOWNTO 0)" +o 7 +suid 50,0 +) +declText (MLText +uid 1389,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,11200,49000,12000" +st "SIGNAL ALUControl : std_ulogic_vector(2 DOWNTO 0)" +) +) +*36 (Net +uid 1430,0 +lang 11 +decl (Decl +n "ALUSrcB" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 11 +suid 55,0 +) +declText (MLText +uid 1431,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,14400,49000,15200" +st "SIGNAL ALUSrcB : std_ulogic_vector(1 DOWNTO 0)" +) +) +*37 (Net +uid 1432,0 +lang 11 +decl (Decl +n "ALUSrcA" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 10 +suid 56,0 +) +declText (MLText +uid 1433,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,13600,49000,14400" +st "SIGNAL ALUSrcA : std_ulogic_vector(1 DOWNTO 0)" +) +) +*38 (Net +uid 1434,0 +lang 11 +decl (Decl +n "immSrc" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 25 +suid 57,0 +) +declText (MLText +uid 1435,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,25600,49000,26400" +st "SIGNAL immSrc : std_ulogic_vector(1 DOWNTO 0)" +) +) +*39 (Net +uid 1436,0 +lang 11 +decl (Decl +n "regwrite" +t "std_ulogic" +o 30 +suid 58,0 +) +declText (MLText +uid 1437,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,29600,39000,30400" +st "SIGNAL regwrite : std_ulogic" +) +) +*40 (Net +uid 1662,0 +lang 11 +decl (Decl +n "instruction" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 26 +suid 59,0 +) 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(VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "103250,40250,104750,41750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*47 (Net +uid 2450,0 +lang 11 +decl (Decl +n "srcA" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 33 +suid 74,0 +) +declText (MLText +uid 2451,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,32000,55000,32800" +st "SIGNAL srcA : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*48 (Net +uid 2452,0 +lang 11 +decl (Decl +n "srcB" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 34 +suid 75,0 +) +declText (MLText +uid 2453,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,32800,55000,33600" +st "SIGNAL srcB : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*49 (Net +uid 2595,0 +lang 11 +decl (Decl +n "ALUResult" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 9 +suid 79,0 +) +declText (MLText +uid 2596,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,12800,55000,13600" +st "SIGNAL ALUResult : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*50 (Net +uid 2763,0 +lang 11 +decl (Decl +n "ALUOut" +t "std_ulogic_vector" +b "(c_dataWidth - 1 DOWNTO 0)" +o 8 +suid 82,0 +) +declText (MLText +uid 2764,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,12000,56000,12800" +st "SIGNAL ALUOut : std_ulogic_vector(c_dataWidth - 1 DOWNTO 0)" +) +) +*51 (SaComponent +uid 2835,0 +optionalChildren [ +*52 (CptPort +uid 2827,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 2828,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "33000,100625,33750,101375" +) +tg (CPTG +uid 2829,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 2830,0 +va (VaSet +isHidden 1 +) +xt "30700,100100,33000,101300" +st "in1" +ju 2 +blo "33000,101100" +) +s (Text +uid 2845,0 +va (VaSet +isHidden 1 +) +xt "33000,101300,33000,101300" +ju 2 +blo "33000,101300" +) +) +thePort (LogicalPort +decl (Decl +n "in1" +t "std_uLogic_vector" +b "(dataBitNb-1 DOWNTO 0)" +o 1 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(Decl +n "clk" +t "std_ulogic" +o 1 +) +) +) +*83 (CptPort +uid 4086,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4087,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "52250,65625,53000,66375" +) +tg (CPTG +uid 4088,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4089,0 +va (VaSet +font "Verdana,8,0" +) +xt "53177,65530,54877,66530" +st "in1" +blo "53177,66330" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "in1" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 3 +) +) +) +*84 (CptPort +uid 4090,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4091,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "57000,65625,57750,66375" +) +tg (CPTG +uid 4092,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4093,0 +va (VaSet +font "Verdana,8,0" +) +xt "54612,65500,56912,66500" +st "out1" +ju 2 +blo "56912,66300" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "out1" +t "std_ulogic_vector" +b "(g_dataWidth - 1 DOWNTO 0)" +o 5 +) +) +) +*85 (CommentGraphic +uid 4094,0 +shape (PolyLine2D +pts [ +"55000,65000" +"57000,63000" +] +uid 4095,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "55000,63000,57000,65000" +) +oxt "15000,20000,17000,22000" +) +*86 (CommentGraphic +uid 4096,0 +shape (PolyLine2D +pts [ +"53000,63000" +"55000,65000" +] +uid 4097,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "53000,63000,55000,65000" +) +oxt "13000,20000,15000,22000" +) +] +shape (Rectangle +uid 4065,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "53000,63000,57000,70000" +fos 1 +) +oxt "13000,20000,17000,27000" +ttg (MlTextGroup +uid 4066,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*87 (Text +uid 4067,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "58050,66300,63050,67500" +st "HEIRV32" +blo "58050,67300" +tm "BdLibraryNameMgr" +) +*88 (Text +uid 4068,0 +va (VaSet +font "Verdana,9,1" +) +xt "58050,67500,69950,68700" +st "bufferStdULogEnable" +blo "58050,68500" +tm "CptNameMgr" +) +*89 (Text +uid 4069,0 +va (VaSet +font "Verdana,9,1" +) +xt "58050,68700,64950,69900" +st "U_pcBuffer" +blo "58050,69700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4070,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4071,0 +text (MLText +uid 4072,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "57000,76200,80500,77000" +st "g_dataWidth = c_dataWidth ( positive ) " +) +header "" +) +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +] +) +viewicon (ZoomableIcon +uid 4073,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "53250,68250,54750,69750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +sed 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*90 (Net +uid 4351,0 +lang 11 +decl (Decl +n "dbg_leds" +t "std_ulogic_vector" +b "(31 DOWNTO 0)" +o 5 +suid 93,0 +) +declText (MLText +uid 4352,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,5600,46000,6400" +st "dbg_leds : std_ulogic_vector(31 DOWNTO 0)" +) +) +*91 (PortIoOut +uid 4365,0 +shape (CompositeShape +uid 4366,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4367,0 +sl 0 +ro 270 +xt "173500,13625,175000,14375" +) +(Line +uid 4368,0 +sl 0 +ro 270 +xt "173000,14000,173500,14000" +pts [ +"173000,14000" +"173500,14000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4369,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4370,0 +va (VaSet +) +xt "176000,13400,181200,14600" +st "dbg_leds" +blo "176000,14400" +tm "WireNameMgr" +) +) +) +*92 (HdlText +uid 4373,0 +optionalChildren [ +*93 (EmbeddedText +uid 4478,0 +commentText (CommentText +uid 4479,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4480,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "118000,10000,170000,26000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4481,0 +va (VaSet +) +xt "118200,10200,170100,22200" +st " + + +dbg_leds(7 downto 0) <= std_ulogic_vector(adr(9 downto 2)); -- no need to read LSBs since does +4 each time + +dbg_leds(15 downto 8) <= std_ulogic_vector(instruction(7 downto 0)); + +dbg_leds(23 downto 16) <= std_ulogic_vector(ALUControl & \"000\" & resultSrc); + +dbg_leds(31 downto 24) <= std_ulogic_vector(regwrite & immSrc & '0' & ALUSrcB & ALUSrcA); + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 52000 +) +) +) +] +shape (Rectangle +uid 4374,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "118000,9000,170000,28000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4375,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*94 (Text +uid 4376,0 +va (VaSet +font "Verdana,9,1" +) +xt "127800,28800,130200,30000" +st "eb2" +blo "127800,29800" +tm "HdlTextNameMgr" +) +*95 (Text +uid 4377,0 +va (VaSet +font "Verdana,9,1" +) +xt "127800,30000,129000,31200" +st "2" +blo "127800,31000" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 4378,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "118250,26250,119750,27750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*96 (PortIoIn +uid 4490,0 +shape (CompositeShape +uid 4491,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4492,0 +sl 0 +ro 270 +xt "9000,41625,10500,42375" +) +(Line +uid 4493,0 +sl 0 +ro 270 +xt "10500,42000,11000,42000" +pts [ +"10500,42000" +"11000,42000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4494,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4495,0 +va (VaSet +) +xt "6100,41400,8000,42600" +st "en" +ju 2 +blo "8000,42400" +tm "WireNameMgr" +) +) +) +*97 (Net +uid 4496,0 +lang 11 +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 97,0 +) +declText (MLText +uid 4497,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,4000,35500,4800" +st "en : std_ulogic" +) +) +*98 (SaComponent +uid 4528,0 +optionalChildren [ +*99 (CptPort +uid 4516,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4517,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "14625,88000,15375,88750" +) +tg (CPTG +uid 4518,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4519,0 +ro 270 +va (VaSet +isHidden 1 +) +xt "14600,78500,15800,88000" +st "in1 : std_uLogic" +blo "15600,88000" +) +) +thePort (LogicalPort +decl (Decl +n "in1" +t "std_uLogic" +o 1 +suid 1,0 +) +) +) +*100 (CptPort +uid 4520,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4521,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "16625,88000,17375,88750" +) +tg (CPTG +uid 4522,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4523,0 +ro 270 +va (VaSet +isHidden 1 +) +xt "16600,78500,17800,88000" +st "in2 : std_uLogic" +blo "17600,88000" +) +) +thePort (LogicalPort +decl (Decl +n "in2" +t "std_uLogic" +o 2 +suid 2,0 +) +) +) +*101 (CptPort +uid 4524,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4525,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "15625,84300,16375,85050" +) +tg (CPTG +uid 4526,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4527,0 +ro 270 +va (VaSet +isHidden 1 +) +xt "15550,85000,16750,95200" +st "out1 : std_uLogic" +ju 2 +blo "16550,85000" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "out1" +t "std_uLogic" +o 3 +suid 3,0 +) +) +) +] +shape (And +uid 4529,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "14000,85000,18000,88000" +) +showPorts 0 +oxt "31000,13000,38000,19000" +ttg (MlTextGroup +uid 4530,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*102 (Text +uid 4531,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "15100,89200,18200,90200" +st "gates" +blo "15100,90000" +tm "BdLibraryNameMgr" +) +*103 (Text +uid 4532,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "15100,90200,18000,91200" +st "and2" +blo "15100,91000" +tm "CptNameMgr" +) +*104 (Text +uid 4533,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "15100,90200,19300,91200" +st "U_and1" +blo "15100,91000" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4534,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4535,0 +text (MLText +uid 4536,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "14500,93100,28600,94100" +st "delay = gateDelay ( time ) " +) +header "" +) +elements [ +(GiElement +name "delay" +type "time" +value "gateDelay" +) +] +) +viewicon (ZoomableIcon +uid 4537,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "14250,86250,15750,87750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sN 0 +sT 1 +) +archFileType "UNKNOWN" +) +*105 (Net +uid 4538,0 +decl (Decl +n "out1" +t "std_uLogic" +o 29 +suid 98,0 +) +declText (MLText +uid 4539,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,28800,39000,29600" +st "SIGNAL out1 : std_uLogic" +) +) +*106 (SaComponent +uid 4546,0 +optionalChildren [ +*107 (CptPort +uid 4556,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4557,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "55625,75000,56375,75750" +) +tg (CPTG +uid 4558,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4559,0 +ro 270 +va (VaSet +isHidden 1 +) +xt "49600,65500,50800,75000" +st "in1 : std_uLogic" +blo "50600,75000" +) +) +thePort (LogicalPort +decl (Decl +n "in1" +t "std_uLogic" +o 1 +) +) +) +*108 (CptPort +uid 4560,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4561,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "53625,75000,54375,75750" +) +tg (CPTG +uid 4562,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 4563,0 +ro 270 +va (VaSet +isHidden 1 +) +xt "47600,65500,48800,75000" +st "in2 : std_uLogic" +blo "48600,75000" +) +) +thePort (LogicalPort +decl (Decl +n "in2" +t "std_uLogic" +o 2 +) +) +) +*109 (CptPort +uid 4564,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 4565,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "54625,71300,55375,72050" +) +tg (CPTG +uid 4566,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 4567,0 +ro 270 +va (VaSet +isHidden 1 +) +xt "48550,72000,49750,82200" +st "out1 : std_uLogic" +ju 2 +blo "49550,72000" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "out1" +t "std_uLogic" +o 3 +) +) +) +] +shape (And +uid 4547,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "53000,72000,57000,75000" +) +showPorts 0 +oxt "31000,13000,38000,19000" +ttg (MlTextGroup +uid 4548,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*110 (Text +uid 4549,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "54100,76200,57200,77200" +st "gates" +blo "54100,77000" +tm "BdLibraryNameMgr" +) +*111 (Text +uid 4550,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "54100,77200,57000,78200" +st "and2" +blo "54100,78000" +tm "CptNameMgr" +) +*112 (Text +uid 4551,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "54100,77200,58300,78200" +st "U_and2" +blo "54100,78000" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 4552,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 4553,0 +text (MLText +uid 4554,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "53500,80100,67600,81100" +st "delay = gateDelay ( time ) " +) +header "" +) +elements [ +(GiElement +name "delay" +type "time" +value "gateDelay" +) +] +) +viewicon (ZoomableIcon +uid 4555,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "53250,73250,54750,74750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sN 0 +sT 1 +) +archFileType "UNKNOWN" +) +*113 (Net +uid 4586,0 +decl (Decl +n "en1" +t "std_uLogic" +o 21 +suid 100,0 +) +declText (MLText +uid 4587,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,22400,39000,23200" +st "SIGNAL en1 : std_uLogic" +) +) +*114 (Net +uid 5835,0 +lang 11 +decl (Decl +n "btns" +t "std_ulogic_vector" +b "(g_btnsNb-1 DOWNTO 0)" +o 1 +suid 101,0 +) +declText (MLText +uid 5836,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,2400,50000,3200" +st "btns : std_ulogic_vector(g_btnsNb-1 DOWNTO 0)" +) +) +*115 (PortIoIn +uid 5841,0 +shape (CompositeShape +uid 5842,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5843,0 +sl 0 +ro 180 +xt "72625,109500,73375,111000" +) +(Line +uid 5844,0 +sl 0 +ro 180 +xt "73000,109000,73000,109500" +pts [ +"73000,109500" +"73000,109000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5845,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5846,0 +ro 90 +va (VaSet +) +xt "72400,112000,73600,114900" +st "btns" +blo "72600,112000" +tm "WireNameMgr" +) +) +) +*116 (Net +uid 5847,0 +lang 11 +decl (Decl +n "leds" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 6 +suid 102,0 +) +declText (MLText +uid 5848,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,6400,51500,7200" +st "leds : std_ulogic_vector(g_dataWidth-1 DOWNTO 0)" +) +) +*117 (PortIoOut +uid 5853,0 +shape (CompositeShape +uid 5854,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5855,0 +sl 0 +xt "74625,109500,75375,111000" +) +(Line +uid 5856,0 +sl 0 +xt "75000,109000,75000,109500" +pts [ +"75000,109000" +"75000,109500" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5857,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5858,0 +ro 90 +va (VaSet +) +xt "74400,112000,75600,114800" +st "leds" +blo "74600,112000" +tm "WireNameMgr" +) +) +) +*118 (SaComponent +uid 6827,0 +optionalChildren [ +*119 (CptPort +uid 6799,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6800,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,79625,37000,80375" +) +tg (CPTG +uid 6801,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6802,0 +va (VaSet +font "Verdana,8,0" +) +xt "38000,79500,41600,80500" +st "address" +blo "38000,80300" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "address" +t "unsigned" +b "(g_dataWidth-1 DOWNTO 0)" +o 1 +suid 27,0 +) +) +) +*120 (CptPort +uid 6803,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6804,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "38625,77250,39375,78000" +) +tg (CPTG +uid 6805,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6806,0 +va (VaSet +font "Verdana,8,0" +) +xt "38480,78000,40080,79000" +st "clk" +blo "38480,78800" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "clk" +t "std_ulogic" +o 2 +suid 28,0 +) +) +) +*121 (CptPort +uid 6807,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6808,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "51000,80625,51750,81375" +) +tg (CPTG +uid 6809,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6810,0 +va (VaSet +font "Verdana,8,0" +) +xt "45800,80500,50000,81500" +st "readData" +ju 2 +blo "50000,81300" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "readData" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 6 +suid 29,0 +) +) +) +*122 (CptPort +uid 6811,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6812,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,81625,37000,82375" +) +tg (CPTG +uid 6813,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6814,0 +va (VaSet +font "Verdana,8,0" +) +xt "38000,81500,42400,82500" +st "writeData" +blo "38000,82300" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "writeData" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 4 +suid 31,0 +) +) +) +*123 (CptPort +uid 6815,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6816,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "43625,77250,44375,78000" +) +tg (CPTG +uid 6817,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6818,0 +ro 270 +va (VaSet +font "Verdana,8,0" +) +xt "43500,78000,44500,83700" +st "writeEnable" +ju 2 +blo "44300,78000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "writeEnable" +t "std_ulogic" +o 5 +suid 32,0 +) +) +) +*124 (CptPort +uid 6819,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6820,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "45625,77250,46375,78000" +) +tg (CPTG +uid 6821,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6822,0 +ro 270 +va (VaSet +font "Verdana,8,0" +) +xt "45500,79000,46500,80500" +st "en" +ju 2 +blo "46300,79000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 38,0 +) +) +) +*125 (CommentGraphic +uid 6823,0 +shape (PolyLine2D +pts [ +"38000,78000" +"39000,80000" +] +uid 6824,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "38000,78000,39000,80000" +) +oxt "20000,15000,21000,17000" +) +*126 (CommentGraphic +uid 6825,0 +shape (PolyLine2D +pts [ +"40000,78000" +"39000,80000" +] +uid 6826,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "39000,78000,40000,80000" +) +oxt "21000,15000,22000,17000" +) +] +shape (Rectangle +uid 6828,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "37000,78000,51000,85000" +fos 1 +) +oxt "19000,15000,33000,22000" +ttg (MlTextGroup +uid 6829,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*127 (Text +uid 6830,0 +va (VaSet +font "Verdana,9,1" +) +xt "36750,85800,44350,87000" +st "HEIRV32_MC" +blo "36750,86800" +tm "BdLibraryNameMgr" +) +*128 (Text +uid 6831,0 +va (VaSet +font "Verdana,9,1" +) +xt "36750,87000,50250,88200" +st "instructionDataMemory" +blo "36750,88000" +tm "CptNameMgr" +) +*129 (Text +uid 6832,0 +va (VaSet +font "Verdana,9,1" +) +xt "36750,88200,47850,89400" +st "U_instrDataMemory" +blo "36750,89200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 6833,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 6834,0 +text (MLText +uid 6835,0 +va (VaSet +font "Courier New,8,0" +) +xt "32000,90600,58500,93000" +st "g_dataWidth = c_dataWidth ( positive ) +g_addrWidth = c_bramAddrWidth ( positive ) +g_programFile = g_programFile ( string ) " +) +header "" +) +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_addrWidth" +type "positive" +value "c_bramAddrWidth" +) +(GiElement +name "g_programFile" +type "string" +value "g_programFile" +) +] +) +viewicon (ZoomableIcon +uid 6836,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "37250,83250,38750,84750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" +ftype 1 +) +sed 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*130 (SaComponent +uid 6849,0 +optionalChildren [ +*131 (CptPort +uid 6837,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6838,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "65000,84625,65750,85375" +) +tg (CPTG +uid 6839,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6840,0 +va (VaSet +font "Verdana,8,0" +) +xt "58900,84500,64000,85500" +st "instruction" +ju 2 +blo "64000,85300" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "instruction" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 3 +suid 1,0 +) +) +) +*132 (CptPort +uid 6841,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6842,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "60625,79250,61375,80000" +) +tg (CPTG +uid 6843,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6844,0 +ro 270 +va (VaSet +font "Verdana,8,0" +) +xt "60500,81000,61500,84100" +st "irWrite" +ju 2 +blo "61300,81000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl 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6853,0 +va (VaSet +font "Verdana,9,1" +) +xt "54850,88000,67150,89200" +st "instructionForwarder" +blo "54850,89000" +tm "CptNameMgr" +) +*136 (Text +uid 6854,0 +va (VaSet +font "Verdana,9,1" +) +xt "54850,89200,63750,90400" +st "U_instrForward" +blo "54850,90200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 6855,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 6856,0 +text (MLText +uid 6857,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "55000,91600,78500,92400" +st "g_dataWidth = c_dataWidth ( positive ) " +) +header "" +) +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +] +) +viewicon (ZoomableIcon +uid 6858,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "55250,84250,56750,85750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*137 (SaComponent +uid 6931,0 +optionalChildren [ +*138 (CptPort +uid 6859,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6860,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98000,45625,98750,46375" +) +tg (CPTG +uid 6861,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6862,0 +va (VaSet +font "Verdana,12,0" +) +xt "88400,45300,97000,46700" +st "ALUControl" +ju 2 +blo "97000,46500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "ALUControl" +t "std_ulogic_vector" +b "(2 DOWNTO 0)" +o 8 +suid 2,0 +) +) +) +*139 (CptPort +uid 6863,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6864,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98000,49625,98750,50375" +) +tg (CPTG +uid 6865,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6866,0 +va (VaSet +font "Verdana,12,0" +) +xt "91100,49300,97000,50700" +st "ALUSrcA" +ju 2 +blo "97000,50500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "ALUSrcA" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 9 +suid 3,0 +) +) +) +*140 (CptPort +uid 6867,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6868,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98000,47625,98750,48375" +) +tg (CPTG +uid 6869,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6870,0 +va (VaSet +font "Verdana,12,0" +) +xt "91100,47300,97000,48700" +st "ALUSrcB" +ju 2 +blo "97000,48500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "ALUSrcB" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 10 +suid 4,0 +) +) +) +*141 (CptPort +uid 6871,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6872,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98000,51625,98750,52375" +) +tg (CPTG +uid 6873,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6874,0 +va (VaSet +font "Verdana,12,0" +) +xt "91800,51300,97000,52700" +st "immSrc" +ju 2 +blo "97000,52500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "immSrc" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 14 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"OnEdgeStrategy" +shape (Triangle +uid 6884,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80250,46625,81000,47375" +) +tg (CPTG +uid 6885,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6886,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,46300,89200,47700" +st "memWrite" +blo "82000,47500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "memWrite" +t "std_ulogic" +o 15 +suid 8,0 +) +) +) +*145 (CptPort +uid 6887,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6888,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80250,42625,81000,43375" +) +tg (CPTG +uid 6889,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6890,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,42300,87900,43700" +st "PCWrite" +blo "82000,43500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "PCWrite" +t "std_ulogic" +o 12 +suid 9,0 +) +) +) +*146 (CptPort +uid 6891,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6892,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98000,53625,98750,54375" +) +tg (CPTG +uid 6893,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6894,0 +va (VaSet +font "Verdana,12,0" +) +xt "90900,53300,97000,54700" +st "regwrite" +ju 2 +blo "97000,54500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "regwrite" +t "std_ulogic" +o 16 +suid 10,0 +) +) +) +*147 (CptPort +uid 6895,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6896,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98000,43625,98750,44375" +) +tg (CPTG +uid 6897,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6898,0 +va (VaSet +font "Verdana,12,0" +) +xt "90700,43300,97000,44700" +st "resultSrc" +ju 2 +blo "97000,44500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "resultSrc" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 17 +suid 11,0 +) +) +) +*148 (CptPort +uid 6899,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6900,0 +va (VaSet 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"80250,55625,81000,56375" +) +tg (CPTG +uid 6909,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6910,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,55300,86700,56700" +st "funct7" +blo "82000,56500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "funct7" +t "std_ulogic" +o 4 +suid 14,0 +) +) +) +*151 (CptPort +uid 6911,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6912,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "84625,37250,85375,38000" +) +tg (CPTG +uid 6913,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6914,0 +va (VaSet +font "Verdana,12,0" +) +xt "83550,38450,85950,39850" +st "clk" +ju 2 +blo "85950,39650" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "clk" +t "std_ulogic" +o 1 +suid 15,0 +) +) +) +*152 (CptPort +uid 6915,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6916,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "88625,37250,89375,38000" +) +tg (CPTG +uid 6917,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6918,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "88300,39000,89700,41500" +st "rst" +ju 2 +blo "89500,39000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "rst" +t "std_ulogic" +o 6 +suid 16,0 +) +) +) +*153 (CptPort +uid 6919,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6920,0 +ro 270 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "80250,44625,81000,45375" +) +tg (CPTG +uid 6921,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 6922,0 +va (VaSet +font "Verdana,12,0" +) +xt "82000,44300,86800,45700" +st "adrSrc" +blo "82000,45500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "adrSrc" +t "std_uLogic" +o 13 +suid 17,0 +) +) +) +*154 (CptPort +uid 6923,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 6924,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91625,37250,92375,38000" +) +tg (CPTG +uid 6925,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 6926,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "91300,39000,92700,41400" +st "en" +ju 2 +blo "92500,39000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "en" +t "std_ulogic" +o 2 +suid 18,0 +) +) +) +*155 (CommentGraphic +uid 6927,0 +shape (PolyLine2D +pts [ +"83000,38000" +"85000,42000" +] +uid 6928,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "83000,38000,85000,42000" +) +oxt "4000,16000,6000,20000" +) +*156 (CommentGraphic +uid 6929,0 +shape (PolyLine2D +pts [ +"85000,42000" +"87000,38000" +] +uid 6930,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "85000,38000,87000,42000" +) +oxt "6000,16000,8000,20000" +) +] +shape (Rectangle +uid 6932,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "81000,38000,98000,59000" +fos 1 +) +oxt "2000,16000,19000,37000" +ttg (MlTextGroup +uid 6933,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*157 (Text +uid 6934,0 +va (VaSet +font "Verdana,9,1" +) +xt "76600,59800,84200,61000" +st "HEIRV32_MC" +blo "76600,60800" +tm "BdLibraryNameMgr" +) +*158 (Text +uid 6935,0 +va (VaSet +font "Verdana,9,1" +) +xt "76600,61000,83400,62200" +st "controlUnit" +blo "76600,62000" +tm "CptNameMgr" +) +*159 (Text +uid 6936,0 +va (VaSet +font "Verdana,9,1" +) +xt "76600,62200,84700,63400" +st "U_controlUnit" +blo "76600,63200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 6937,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 6938,0 +text (MLText +uid 6939,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "92000,62600,115500,63400" +st "g_datawidth = c_dataWidth ( positive ) " +) +header "" +) +elements [ +(GiElement +name "g_datawidth" +type "positive" +value "c_dataWidth" +) +] +) +viewicon (ZoomableIcon +uid 6940,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "81250,57250,82750,58750" +iconName "BlockDiagram.png" +iconMaskName "BlockDiagram.msk" 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8058,0 +shape (CustomPolygon +pts [ +"90001,95000" +"90001,92000" +"104999,89000" +"104999,95000" +"90001,95000" +] +uid 8059,0 +layer 0 +sl 0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "26368,26368,26368" +) +xt "90001,89000,104999,95000" +) +oxt "16001,10000,30999,16000" +) +] +shape (Rectangle +uid 8061,0 +va (VaSet +vasetType 1 +transparent 1 +lineColor "26368,26368,26368" +lineStyle 2 +) +xt "90000,89000,105000,95000" +fos 1 +) +oxt "16000,10000,31000,16000" +ttg (MlTextGroup +uid 8062,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*207 (Text +uid 8063,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "105500,92300,110500,93500" +st "HEIRV32" +blo "105500,93300" +tm "BdLibraryNameMgr" +) +*208 (Text +uid 8064,0 +va (VaSet +font "Verdana,9,1" +) +xt "105500,93500,109600,94700" +st "extend" +blo "105500,94500" +tm "CptNameMgr" +) +*209 (Text +uid 8065,0 +va (VaSet +font "Verdana,9,1" +) +xt "105500,94700,110900,95900" +st "U_extend" +blo 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+st "U_alu" +blo "141500,91700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 8096,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 8097,0 +text (MLText +uid 8098,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "136000,93600,159500,95200" +st "g_datawidth = c_dataWidth ( positive ) +g_tALU = 120 ps ( time ) " +) +header "" +) +elements [ +(GiElement +name "g_datawidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_tALU" +type "time" +value "120 ps" +) +] +) +viewicon (ZoomableIcon +uid 8099,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "136250,88250,137750,89750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*219 (SaComponent +uid 8152,0 +optionalChildren [ +*220 (CptPort +uid 8100,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8101,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "92625,70250,93375,71000" +) +tg (CPTG +uid 8102,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8103,0 +va (VaSet +font "Verdana,12,0" +) +xt "91424,71345,93824,72745" +st "clk" +ju 2 +blo "93824,72545" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "clk" +t "std_ulogic" +o 5 +suid 1,0 +) +) +) +*221 (CptPort +uid 8104,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8105,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "89250,75625,90000,76375" +) +tg (CPTG +uid 8106,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8107,0 +va (VaSet +font "Verdana,12,0" +) +xt "91000,75300,95500,76700" +st "addr1" +blo "91000,76500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "addr1" +t "std_ulogic_vector" +b "(4 DOWNTO 0)" +o 1 +suid 2,0 +) +) +) +*222 (CptPort +uid 8108,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8109,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "89250,82625,90000,83375" +) +tg (CPTG +uid 8110,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8111,0 +va (VaSet +font "Verdana,12,0" +) +xt "91000,82300,98000,83700" +st "writeData" +blo "91000,83500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "writeData" +t "std_ulogic_vector" +b "(g_dataWidth - 1 DOWNTO 0)" +o 4 +suid 3,0 +) +) +) +*223 (CptPort +uid 8112,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8113,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "107000,75625,107750,76375" +) +tg (CPTG +uid 8114,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8115,0 +va (VaSet +font "Verdana,12,0" +) +xt "102700,75300,106000,76700" +st "RD1" +ju 2 +blo "106000,76500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "RD1" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 8 +suid 4,0 +) +) +) +*224 (CptPort +uid 8116,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8117,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt 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"0,65535,0" +) +xt "95625,70250,96375,71000" +) +tg (CPTG +uid 8126,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8127,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "95300,72000,96700,74500" +st "rst" +ju 2 +blo "96500,72000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "rst" +t "std_ulogic" +o 7 +suid 7,0 +) +) +) +*227 (CptPort +uid 8128,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8129,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "89250,77625,90000,78375" +) +tg (CPTG +uid 8130,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8131,0 +va (VaSet +font "Verdana,12,0" +) +xt "91000,77300,95500,78700" +st "addr2" +blo "91000,78500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "addr2" +t "std_ulogic_vector" +b "(4 DOWNTO 0)" +o 2 +suid 8,0 +) +) +) +*228 (CptPort +uid 8132,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8133,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "89250,79625,90000,80375" +) +tg (CPTG +uid 8134,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8135,0 +va (VaSet +font "Verdana,12,0" +) +xt "91000,79300,95500,80700" +st "addr3" +blo "91000,80500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "addr3" +t "std_ulogic_vector" +b "(4 DOWNTO 0)" +o 3 +suid 9,0 +) +) +) +*229 (CptPort +uid 8136,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8137,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "102625,70250,103375,71000" +) +tg (CPTG +uid 8138,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 8139,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "102300,72000,103700,74400" +st "en" +ju 2 +blo "103500,72000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "en" +t "std_ulogic" +o 10 +suid 10,0 +) +) +) +*230 (CptPort +uid 8140,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8141,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "101625,85000,102375,85750" +) +tg (CPTG +uid 8142,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8143,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "101300,80400,102700,84000" +st "btns" +blo "102500,84000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "btns" +t "std_ulogic_vector" +b "(g_btnsNb-1 DOWNTO 0)" +o 11 +suid 11,0 +) +) +) +*231 (CptPort +uid 8144,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 8145,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "103625,85000,104375,85750" +) +tg (CPTG +uid 8146,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 8147,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "103300,80600,104700,84000" +st "leds" +blo "104500,84000" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "leds" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 12 +suid 12,0 +) +) +) +*232 (CommentGraphic +uid 8148,0 +shape (PolyLine2D +pts [ +"91000,71000" +"93000,74000" +] +uid 8149,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 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"131000,75000,131000,75000" +blo "131000,75000" +tm "SignalTypeMgr" +) +) +on &47 +) +*298 (Wire +uid 2444,0 +shape (OrthoPolyLine +uid 2445,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "129750,87000,135250,90000" +pts [ +"129750,90000" +"134000,90000" +"134000,87000" +"135250,87000" +] +) +start &177 +end &214 +sat 32 +eat 32 +sty 1 +stc 0 +sf 1 +si 0 +tg (WTG +uid 2448,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2449,0 +va (VaSet +) +xt "131000,88800,134000,90000" +st "srcB" +blo "131000,89800" +tm "WireNameMgr" +) +s (Text +uid 2926,0 +va (VaSet +) +xt "131000,90000,131000,90000" +blo "131000,90000" +tm "SignalTypeMgr" +) +) +on &48 +) +*299 (Wire +uid 2586,0 +shape (OrthoPolyLine +uid 2587,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "169000,90000,175250,90000" +pts [ +"175250,90000" +"169000,90000" +] +) +start &193 +sat 32 +eat 16 +sty 1 +stc 0 +sf 1 +si 0 +tg (WTG +uid 2592,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2593,0 +va (VaSet +) +xt "170000,88800,176600,90000" +st "four_zeros" +blo "170000,89800" +tm "WireNameMgr" +) +s (Text +uid 2594,0 +va (VaSet +) +xt "170000,90000,170000,90000" +blo "170000,90000" +tm "SignalTypeMgr" +) +) +on &58 +) +*300 (Wire +uid 2724,0 +shape (OrthoPolyLine +uid 2725,0 +va (VaSet +vasetType 3 +) +xt "156000,79000,156000,80250" +pts [ +"156000,79000" +"156000,80250" +] +) +end &64 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2728,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2729,0 +va (VaSet +) +xt "155059,77035,157259,78235" +st "clk" +blo "155059,78035" +tm "WireNameMgr" +) +) +on &16 +) +*301 (Wire +uid 2730,0 +shape (OrthoPolyLine +uid 2731,0 +va (VaSet +vasetType 3 +) +xt "150000,86000,153250,86000" +pts [ +"150000,86000" +"153250,86000" +] +) +end &62 +sat 16 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 2734,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2735,0 +va (VaSet +) +xt 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32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2767,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2768,0 +va (VaSet +) +xt "170000,86800,176100,88000" +st "ALUResult" +blo "170000,87800" +tm "WireNameMgr" +) +) +on &49 +) +*305 (Wire +uid 2849,0 +optionalChildren [ +*306 (BdJunction +uid 2859,0 +ps "OnConnectorStrategy" +shape (Circle +uid 2860,0 +va (VaSet +vasetType 1 +) +xt "69600,100600,70400,101400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 2850,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "33000,87000,183000,101000" +pts [ +"33000,101000" +"183000,101000" +"183000,87000" +"180750,87000" +] +) +start &52 +end &197 +sat 32 +eat 32 +sty 1 +stc 0 +sf 1 +si 0 +tg (WTG +uid 2851,0 +ps "ConnStartEndStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 2852,0 +va (VaSet +isHidden 1 +) +xt "35000,99800,38600,101000" +st "result" +blo "35000,100800" +tm "WireNameMgr" +) +s (Text +uid 2934,0 +va (VaSet +isHidden 1 +) +xt "35000,101000,35000,101000" +blo "35000,101000" +tm "SignalTypeMgr" +) +) +on &57 +) +*307 (Wire +uid 2855,0 +shape (OrthoPolyLine +uid 2856,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "70000,83000,89250,101000" +pts [ +"89250,83000" +"70000,83000" +"70000,101000" +] +) +start &222 +end &306 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 2857,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 2858,0 +va (VaSet +) +xt "84250,81800,87850,83000" +st "result" +blo "84250,82800" +tm "WireNameMgr" +) +) +on &57 +) +*308 (Wire +uid 3592,0 +shape (OrthoPolyLine +uid 3593,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "53000,81000,54250,81000" +pts [ +"53000,81000" +"54250,81000" +] +) +start &251 +end &133 +sat 32 +eat 32 +sty 1 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 3594,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 3595,0 +va (VaSet +isHidden 1 +) +xt "50250,79800,53150,81000" +st "data" +blo "50250,80800" +tm "WireNameMgr" +) +) +on &31 +) +*309 (Wire +uid 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"C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\instruction@data@memory\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\instruction@data@memory" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\instructionDataMemory" +) +(vvPair +variable "date" +value "03.11.2022" +) +(vvPair +variable "day" +value "jeu." +) +(vvPair +variable "day_long" +value "jeudi" +) +(vvPair +variable "dd" +value "03" +) +(vvPair +variable "entity_name" +value "instructionDataMemory" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "03.11.2022" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "16:12:32" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "HEIRV32_MC" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/MultiCycle/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "instructionDataMemory" +) +(vvPair +variable "month" +value "nov." +) +(vvPair +variable "month_long" +value "novembre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\instruction@data@memory\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\MultiCycle\\hds\\instructionDataMemory\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "16:12:32" +) +(vvPair +variable "unit" +value "instructionDataMemory" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" 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+(DmPackageRef +library "gates" +unitName "gates" +) +] +machine (Machine +name "csm" +children [ +(Machine +name "csm" +children [ +] +stateSignalName "current_state" +) +] +) +libraryRefs [ +"ieee" +"gates" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (StateMachine +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m\\fsm.sm.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m\\fsm.sm.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "fsm" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\mainFSM" +) +(vvPair +variable "date" +value "24.10.2022" +) +(vvPair +variable "day" +value "lun." +) +(vvPair +variable "day_long" +value "lundi" +) +(vvPair +variable "dd" +value "24" +) +(vvPair +variable "entity_name" +value "mainFSM" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "fsm.sm" +) +(vvPair +variable "f_logical" +value "fsm.sm" +) +(vvPair +variable "f_noext" +value "fsm" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "24.10.2022" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "15:37:29" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "HEIRV32" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/work" +) +(vvPair +variable "mm" +value "10" +) +(vvPair +variable "module_name" +value "mainFSM" +) +(vvPair +variable "month" +value "oct." +) +(vvPair +variable "month_long" +value "octobre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m\\fsm.sm" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\mainFSM\\fsm.sm" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "sm" +) +(vvPair +variable "this_file" +value "fsm" +) +(vvPair +variable "this_file_logical" +value "fsm" +) +(vvPair +variable "time" +value "15:37:29" +) +(vvPair +variable "unit" +value "mainFSM" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "fsm" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +uid 182,0 +optionalChildren [ +*1 (ConcurrentSM +uid 1,0 +topDiagram (StateDiagram +LanguageMgr "None" +uid 2,0 +optionalChildren [ +*2 (State +uid 43,0 +shape (Circle +uid 772,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "39997,13150,51403,24556" +radius 5703 +) +name (Text +uid 45,0 +va (VaSet +font "Verdana,12,1" +) +xt "42200,18153,49200,19553" +st "s0_Fetch" +ju 0 +blo "45700,19353" +tm "ONodeName" +) +wait (TextAssociate +uid 46,0 +ps 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+bg "0,0,0" +) +optionalChildren [ +(Pentagon +uid 89,0 +sl 0 +ro 270 +xt "8512,25314,10762,26314" +) +(Line +uid 90,0 +sl 0 +ro 270 +xt "8012,25814,8512,25814" +pts [ +"8012,25814" +"8512,25814" +] +) +] +) +name (TextAssociate +uid 91,0 +ps "CenterOffsetStrategy" +text (Text +uid 92,0 +va (VaSet +font "Verdana,9,1" +) +xt "11262,25314,16362,26514" +st "s0_Fetch" +blo "11262,26314" +tm "LinkName" +) +) +) +*6 (SmRecoveryStatePoint +uid 93,0 +shape (CompositeShape +uid 94,0 +va (VaSet +vasetType 1 +fg "65535,0,0" +) +optionalChildren [ +(Circle +uid 95,0 +sl 0 +xt "-5238,19914,-3438,21714" +radius 900 +) +(Line +uid 96,0 +sl 0 +va (VaSet +vasetType 3 +lineColor "65535,65535,0" +lineWidth 1 +) +xt "-4764,20388,-3912,21240" +pts [ +"-4764,21240" +"-3912,20388" +] +) +(Line +uid 97,0 +sl 0 +va (VaSet +vasetType 3 +lineColor "65535,65535,0" +lineWidth 1 +) +xt "-4764,20388,-3912,21240" +pts [ +"-3912,21240" +"-4764,20388" +] +) +] +) +) +*7 (Link +uid 98,0 +shape (CompositeShape +uid 99,0 +va (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +optionalChildren [ +(Pentagon +uid 100,0 +sl 0 +ro 270 +xt "8512,20314,10762,21314" +) +(Line +uid 101,0 +sl 0 +ro 270 +xt "8012,20814,8512,20814" +pts [ +"8012,20814" +"8512,20814" +] +) +] +) +name (TextAssociate +uid 102,0 +ps "CenterOffsetStrategy" +text (Text +uid 103,0 +va (VaSet +font "Verdana,9,1" +) +xt "11262,20314,16362,21514" +st "s0_Fetch" +blo "11262,21314" +tm "LinkName" +) +) +) +*8 (Grouping +uid 124,0 +optionalChildren [ +*9 (CommentText +uid 126,0 +shape (Rectangle +uid 127,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "94050,1990,111050,2990" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 128,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "94250,1990,105550,2990" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*10 (CommentText +uid 129,0 +shape (Rectangle +uid 130,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "111050,-2010,115050,-1010" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 131,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "111250,-2010,114250,-1010" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*11 (CommentText +uid 132,0 +shape (Rectangle +uid 133,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "94050,-10,111050,990" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 134,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "94250,-10,104250,990" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*12 (CommentText +uid 135,0 +shape (Rectangle +uid 136,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "90050,-10,94050,990" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 137,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "90250,-10,92350,990" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*13 (CommentText +uid 138,0 +shape (Rectangle +uid 139,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "111050,-1010,131050,2990" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 140,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "111250,-810,120650,190" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*14 (CommentText +uid 141,0 +shape (Rectangle +uid 142,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "115050,-2010,131050,-1010" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 143,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "115250,-2010,116850,-1010" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*15 (CommentText +uid 144,0 +shape (Rectangle +uid 145,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "90050,-2010,111050,-10" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 146,0 +va (VaSet +fg "32768,0,0" +) +xt "95400,-1610,105700,-410" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*16 (CommentText +uid 147,0 +shape (Rectangle +uid 148,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "90050,990,94050,1990" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 149,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "90250,990,92350,1990" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*17 (CommentText +uid 150,0 +shape (Rectangle +uid 151,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "90050,1990,94050,2990" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 152,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "90250,1990,92950,2990" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*18 (CommentText +uid 153,0 +shape (Rectangle +uid 154,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "94050,990,111050,1990" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 155,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "94250,990,103350,1990" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 125,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "90050,-2010,131050,2990" +) +oxt "14000,66000,55000,71000" +) +*19 (State +uid 285,0 +shape (Circle +uid 286,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "40111,29283,51517,40689" +radius 5703 +) +name (Text +uid 287,0 +va (VaSet +font "Verdana,12,1" +) +xt "41664,34286,49964,35686" +st "s1_Decode" +ju 0 +blo "45814,35486" +tm "ONodeName" +) +wait (TextAssociate +uid 288,0 +ps "CenterOffsetStrategy" +text (Text +uid 289,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "45564,35186,50664,36586" +st "wait 2" +blo "45564,36386" +tm "SmWaitText" +) +) +encoding (Text +uid 290,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "45814,36086,45814,36086" +blo "45814,36086" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 293,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 294,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "51978,30612,63378,34412" +) +autoResize 1 +tline (Line +uid 295,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "52078,30512,63278,30512" +pts [ +"52078,30512" +"63278,30512" +] +) +bline (Line +uid 296,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "52078,31712,63278,31712" +pts [ +"52078,31712" +"63278,31712" +] +) +ttri (Triangle +uid 297,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "51628,30137,51978,30487" +) +btri (Triangle +uid 298,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "51628,28937,51978,29287" +) +entryActions (MLText +uid 299,0 +va (VaSet +) +xt "52078,30312,52078,30312" +tm "Actions" +) +inActions (MLText +uid 300,0 +va (VaSet +) +xt "52078,30712,63278,34312" +st "ALUSrcA <= \"01\" ; +ALUSrcB <= \"01\" ; +ALUOp <= \"00\" ;" +tm "Actions" +) +exitActions (MLText +uid 301,0 +va (VaSet +) +xt "53678,29112,53678,29112" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 291,0 +ps "CenterOffsetStrategy" +text (MLText +uid 292,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "43714,36186,50414,37386" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*20 (State +uid 356,0 +shape (Circle +uid 357,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "-8849,48214,2557,59620" +radius 5703 +) +name (Text +uid 358,0 +va (VaSet +font "Verdana,12,1" +) +xt "-7546,53217,1254,54617" +st "s2_MemAdr" +ju 0 +blo "-3146,54417" +tm "ONodeName" +) +wait (TextAssociate +uid 359,0 +ps "CenterOffsetStrategy" +text (Text +uid 360,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "-3396,54117,1704,55517" +st "wait 2" +blo "-3396,55317" +tm "SmWaitText" +) +) +encoding (Text +uid 361,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "-3146,55017,-3146,55017" +blo "-3146,55017" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 364,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 365,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "3391,52423,14791,56223" +) +autoResize 1 +tline (Line +uid 366,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3491,52323,14691,52323" +pts [ +"3491,52323" +"14691,52323" +] +) +bline (Line +uid 367,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3491,53523,14691,53523" +pts [ +"3491,53523" +"14691,53523" +] +) +ttri (Triangle +uid 368,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3041,51948,3391,52298" +) +btri (Triangle +uid 369,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3041,50748,3391,51098" +) +entryActions (MLText +uid 370,0 +va (VaSet +) +xt "3491,52123,3491,52123" +tm "Actions" +) +inActions (MLText +uid 371,0 +va (VaSet +) +xt "3491,52523,14691,56123" +st "ALUSrcA <= \"10\" ; +ALUSrcB <= \"01\" ; +ALUOp <= \"00\" ;" +tm "Actions" +) +exitActions (MLText +uid 372,0 +va (VaSet +) +xt "5091,50923,5091,50923" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 362,0 +ps "CenterOffsetStrategy" +text (MLText +uid 363,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "-5246,55117,1454,56317" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*21 (State +uid 373,0 +shape (Circle +uid 374,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "15174,48213,26822,59861" +radius 5824 +) +name (Text +uid 375,0 +va (VaSet +font "Verdana,12,1" +) +xt "15798,53337,26198,54737" +st "s6_ExecuteR" +ju 0 +blo "20998,54537" +tm "ONodeName" +) +wait (TextAssociate +uid 376,0 +ps "CenterOffsetStrategy" +text (Text +uid 377,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "20748,54237,25848,55637" +st "wait 2" +blo "20748,55437" +tm "SmWaitText" +) +) +encoding (Text +uid 378,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "20998,55137,20998,55137" +blo "20998,55137" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 381,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 382,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "27535,52543,38935,56343" +) +autoResize 1 +tline (Line +uid 383,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27635,52443,38835,52443" +pts [ +"27635,52443" +"38835,52443" +] +) +bline (Line +uid 384,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27635,53643,38835,53643" +pts [ +"27635,53643" +"38835,53643" +] +) +ttri (Triangle +uid 385,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27185,52068,27535,52418" +) +btri (Triangle +uid 386,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27185,50868,27535,51218" +) +entryActions (MLText +uid 387,0 +va (VaSet +) +xt "27635,52243,27635,52243" +tm "Actions" +) +inActions (MLText +uid 388,0 +va (VaSet +) +xt "27635,52643,38835,56243" +st "ALUSrcA <= \"10\" ; +ALUSrcB <= \"00\" ; +ALUOp <= \"10\" ;" +tm "Actions" +) +exitActions (MLText +uid 389,0 +va (VaSet +) +xt "29235,51043,29235,51043" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 379,0 +ps "CenterOffsetStrategy" +text (MLText +uid 380,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "18898,55237,25598,56437" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*22 (State +uid 390,0 +shape (Circle +uid 391,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "40255,48478,51661,59884" +radius 5703 +) +name (Text +uid 392,0 +va (VaSet +font "Verdana,12,1" +) +xt "40908,53481,51008,54881" +st "s8_ExecuteI" +ju 0 +blo "45958,54681" +tm "ONodeName" +) +wait (TextAssociate +uid 393,0 +ps "CenterOffsetStrategy" +text (Text +uid 394,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "45708,54381,50808,55781" +st "wait 2" +blo "45708,55581" +tm "SmWaitText" +) +) +encoding (Text +uid 395,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "45958,55281,45958,55281" +blo "45958,55281" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 398,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 399,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "52495,52687,63895,56487" +) +autoResize 1 +tline (Line +uid 400,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "52595,52587,63795,52587" +pts [ +"52595,52587" +"63795,52587" +] +) +bline (Line +uid 401,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "52595,53787,63795,53787" +pts [ +"52595,53787" +"63795,53787" +] +) +ttri (Triangle +uid 402,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "52145,52212,52495,52562" +) +btri (Triangle +uid 403,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "52145,51012,52495,51362" +) +entryActions (MLText +uid 404,0 +va (VaSet +) +xt "52595,52387,52595,52387" +tm "Actions" +) +inActions (MLText +uid 405,0 +va (VaSet +) +xt "52595,52787,63795,56387" +st "ALUSrcA <= \"10\" ; +ALUSrcB <= \"01\" ; +ALUOp <= \"10\" ;" +tm "Actions" +) +exitActions (MLText +uid 406,0 +va (VaSet +) +xt "54195,51187,54195,51187" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 396,0 +ps "CenterOffsetStrategy" +text (MLText +uid 397,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "43858,55381,50558,56581" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*23 (State +uid 407,0 +shape (Circle +uid 408,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "65119,48694,76525,60100" +radius 5703 +) +name (Text +uid 409,0 +va (VaSet +font "Verdana,12,1" +) +xt "67922,53697,73722,55097" +st "s9_JAL" +ju 0 +blo "70822,54897" +tm "ONodeName" +) +wait (TextAssociate +uid 410,0 +ps "CenterOffsetStrategy" +text (Text +uid 411,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "70572,54597,75672,55997" +st "wait 2" +blo "70572,55797" +tm "SmWaitText" +) +) +encoding (Text +uid 412,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "70822,55497,70822,55497" +blo "70822,55497" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 415,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 416,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "77359,51703,88759,57903" +) +autoResize 1 +tline (Line +uid 417,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "77459,51603,88659,51603" +pts [ +"77459,51603" +"88659,51603" +] +) +bline (Line +uid 418,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "77459,54603,88659,54603" +pts [ +"77459,54603" +"88659,54603" +] +) +ttri (Triangle +uid 419,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "77009,51228,77359,51578" +) +btri (Triangle +uid 420,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "77009,51228,77359,51578" +) +entryActions (MLText +uid 421,0 +va (VaSet +) +xt "77459,51403,77459,51403" +tm "Actions" +) +inActions (MLText +uid 422,0 +va (VaSet +) +xt "77459,51803,88659,57803" +st "ALUSrcA <= \"01\" ; +ALUSrcB <= \"10\" ; +ALUOp <= \"00\" ; +resultSrc <= \"00\" ; +PCupdate <= '1' ;" +tm "Actions" +) +exitActions (MLText +uid 423,0 +va (VaSet +) +xt "79059,51403,79059,51403" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 413,0 +ps "CenterOffsetStrategy" +text (MLText +uid 414,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "68722,55597,75422,56797" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*24 (State +uid 424,0 +shape (Circle +uid 425,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "89284,48762,100690,60168" +radius 5703 +) +name (Text +uid 426,0 +va (VaSet +font "Verdana,12,1" +) +xt "91437,53765,98537,55165" +st "s10_BEQ" +ju 0 +blo "94987,54965" +tm "ONodeName" +) +wait (TextAssociate +uid 427,0 +ps "CenterOffsetStrategy" +text (Text +uid 428,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "94737,54665,99837,56065" +st "wait 2" +blo "94737,55865" +tm "SmWaitText" +) +) +encoding (Text +uid 429,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "94987,55565,94987,55565" +blo "94987,55565" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 432,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 433,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "101524,51771,112924,57971" +) +autoResize 1 +tline (Line +uid 434,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "101624,51671,112824,51671" +pts [ +"101624,51671" +"112824,51671" +] +) +bline (Line +uid 435,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "101624,54671,112824,54671" +pts [ +"101624,54671" +"112824,54671" +] +) +ttri (Triangle +uid 436,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "101174,51296,101524,51646" +) +btri (Triangle +uid 437,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "101174,51296,101524,51646" +) +entryActions (MLText +uid 438,0 +va (VaSet +) +xt "101624,51471,101624,51471" +tm "Actions" +) +inActions (MLText +uid 439,0 +va (VaSet +) +xt "101624,51871,112824,57871" +st "ALUSrcA <= \"10\" ; +ALUSrcB <= \"00\" ; +ALUOp <= \"01\" ; +resultSrc <= \"00\" ; +branch <= '1' ;" +tm "Actions" +) +exitActions (MLText +uid 440,0 +va (VaSet +) +xt "103224,51471,103224,51471" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 430,0 +ps "CenterOffsetStrategy" +text (MLText +uid 431,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "92887,55665,99587,56865" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*25 (CommentText +uid 451,0 +shape (Rectangle +uid 452,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "5155,35565,8155,37565" +) +oxt "0,0,15000,5000" +text (MLText +uid 453,0 +va (VaSet +fg "0,0,32768" +) +xt "5355,35765,7055,36965" +st " +lw +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 2600 +) +) +*26 (CommentText +uid 454,0 +shape (Rectangle +uid 455,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "14829,35185,17829,37185" +) +oxt "0,0,15000,5000" +text (MLText +uid 456,0 +va (VaSet +fg "0,0,32768" +) +xt "15029,35385,17029,36585" +st " +sw +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 2600 +) +) +*27 (CommentText +uid 467,0 +shape (Rectangle +uid 468,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "29246,44582,34246,46582" +) +oxt "0,0,15000,5000" +text (MLText +uid 469,0 +va (VaSet +fg "0,0,32768" +) +xt "29446,44782,33546,45982" +st " +R-type +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 4600 +) +) +*28 (CommentText +uid 480,0 +shape (Rectangle +uid 481,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "47750,46310,55750,48310" +) +oxt "0,0,15000,5000" +text (MLText +uid 482,0 +va (VaSet +fg "0,0,32768" +) +xt "47950,46510,55050,47710" +st " +I-type ALU +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 7600 +) +) +*29 (CommentText +uid 493,0 +shape (Rectangle +uid 494,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "67766,43718,70766,45718" +) +oxt "0,0,15000,5000" +text (MLText +uid 495,0 +va (VaSet +fg "0,0,32768" +) +xt "67966,43918,69866,45118" +st " +jal +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 2600 +) +) +*30 (CommentText +uid 506,0 +shape (Rectangle +uid 507,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "87998,39830,90998,41830" +) +oxt "0,0,15000,5000" +text (MLText +uid 508,0 +va (VaSet +fg "0,0,32768" +) +xt "88198,40030,90698,41230" +st " +beq +" +tm "CommentText" +wrapOption 3 +visibleHeight 1600 +visibleWidth 2600 +) +) +*31 (State +uid 536,0 +shape (Circle +uid 537,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "-9546,67294,2396,79236" +radius 5971 +) +name (Text +uid 538,0 +va (VaSet +font "Verdana,12,1" +) +xt "-8925,72565,1775,73965" +st "s3_MemRead" +ju 0 +blo "-3575,73765" +tm "ONodeName" +) +wait (TextAssociate +uid 539,0 +ps "CenterOffsetStrategy" +text (Text +uid 540,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "-3825,73465,1275,74865" +st "wait 2" +blo "-3825,74665" +tm "SmWaitText" +) +) +encoding (Text +uid 541,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "-3575,74365,-3575,74365" +blo "-3575,74365" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 544,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 545,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "3012,72371,14312,74971" +) +autoResize 1 +tline (Line +uid 546,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3112,72271,14212,72271" +pts [ +"3112,72271" +"14212,72271" +] +) +bline (Line +uid 547,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3112,72571,14212,72571" +pts [ +"3112,72571" +"14212,72571" +] +) +ttri (Triangle +uid 548,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "2662,71896,3012,72246" +) +btri (Triangle +uid 549,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "2662,70096,3012,70446" +) +entryActions (MLText +uid 550,0 +va (VaSet +) +xt "3112,72071,3112,72071" +tm "Actions" +) +inActions (MLText +uid 551,0 +va (VaSet +) +xt "3112,72471,14212,74871" +st "adrSrc <= '1' ; +resultSrc <= \"00\" ;" +tm "Actions" +) +exitActions (MLText +uid 552,0 +va (VaSet +) +xt "4662,70271,4662,70271" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 542,0 +ps "CenterOffsetStrategy" +text (MLText +uid 543,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "-5675,74465,1025,75665" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*32 (State +uid 553,0 +shape (Circle +uid 554,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "-9152,84238,2254,95644" +radius 5703 +) +name (Text +uid 555,0 +va (VaSet +font "Verdana,12,1" +) +xt "-7849,89241,951,90641" +st "s4_MemWB" +ju 0 +blo "-3449,90441" +tm "ONodeName" +) +wait (TextAssociate +uid 556,0 +ps "CenterOffsetStrategy" +text (Text +uid 557,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "-3699,90141,1401,91541" +st "wait 2" +blo "-3699,91341" +tm "SmWaitText" +) +) +encoding (Text +uid 558,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "-3449,91041,-3449,91041" +blo "-3449,91041" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 561,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 562,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "3138,89047,14438,91647" +) +autoResize 1 +tline (Line +uid 563,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3238,88947,14338,88947" +pts [ +"3238,88947" +"14338,88947" +] +) +bline (Line +uid 564,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "3238,89247,14338,89247" +pts [ +"3238,89247" +"14338,89247" +] +) +ttri (Triangle +uid 565,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "2788,88572,3138,88922" +) +btri (Triangle +uid 566,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "2788,86772,3138,87122" +) +entryActions (MLText +uid 567,0 +va (VaSet +) +xt "3238,88747,3238,88747" +tm "Actions" +) +inActions (MLText +uid 568,0 +va (VaSet +) +xt "3238,89147,14338,91547" +st "resultSrc <= \"01\" ; +regwrite <= '1' ;" +tm "Actions" +) +exitActions (MLText +uid 569,0 +va (VaSet +) +xt "4788,86947,4788,86947" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 559,0 +ps "CenterOffsetStrategy" +text (MLText +uid 560,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "-5549,91141,1151,92341" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*33 (State +uid 570,0 +shape (Circle +uid 571,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "14970,83798,27304,96132" +radius 6167 +) +name (Text +uid 572,0 +va (VaSet +font "Verdana,12,1" +) +xt "15587,89265,26687,90665" +st "s5_MemWrite" +ju 0 +blo "21137,90465" +tm "ONodeName" +) +wait (TextAssociate +uid 573,0 +ps "CenterOffsetStrategy" +text (Text +uid 574,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "20887,90165,25987,91565" +st "wait 2" +blo "20887,91365" +tm "SmWaitText" +) +) +encoding (Text +uid 575,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "21137,91065,21137,91065" +blo "21137,91065" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 578,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 579,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "27724,88471,39024,92271" +) +autoResize 1 +tline (Line +uid 580,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27824,88371,38924,88371" +pts [ +"27824,88371" +"38924,88371" +] +) +bline (Line +uid 581,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27824,89571,38924,89571" +pts [ +"27824,89571" +"38924,89571" +] +) +ttri (Triangle +uid 582,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27374,87996,27724,88346" +) +btri (Triangle +uid 583,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "27374,86796,27724,87146" +) +entryActions (MLText +uid 584,0 +va (VaSet +) +xt "27824,88171,27824,88171" +tm "Actions" +) +inActions (MLText +uid 585,0 +va (VaSet +) +xt "27824,88571,38924,92171" +st "adrSrc <= '1' ; +resultSrc <= \"00\" ; +memWrite <= '1' ;" +tm "Actions" +) +exitActions (MLText +uid 586,0 +va (VaSet +) +xt "29374,86971,29374,86971" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 576,0 +ps "CenterOffsetStrategy" +text (MLText +uid 577,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "19037,91165,25737,92365" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*34 (State +uid 587,0 +shape (Circle +uid 588,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "41172,84375,52578,95781" +radius 5703 +) +name (Text +uid 589,0 +va (VaSet +font "Verdana,12,1" +) +xt "42675,89378,51075,90778" +st "s7_ALUWB" +ju 0 +blo "46875,90578" +tm "ONodeName" +) +wait (TextAssociate +uid 590,0 +ps "CenterOffsetStrategy" +text (Text +uid 591,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "Verdana,12,1" +) +xt "46625,90278,51725,91678" +st "wait 2" +blo "46625,91478" +tm "SmWaitText" +) +) +encoding (Text +uid 592,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "46875,91178,46875,91178" +blo "46875,91178" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 595,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 596,0 +va (VaSet +vasetType 1 +transparent 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +fillStyle 1 +) +xt "53462,89184,64762,91784" +) +autoResize 1 +tline (Line +uid 597,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "53562,89084,64662,89084" +pts [ +"53562,89084" +"64662,89084" +] +) +bline (Line +uid 598,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "53562,89384,64662,89384" +pts [ +"53562,89384" +"64662,89384" +] +) +ttri (Triangle +uid 599,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "53112,88709,53462,89059" +) +btri (Triangle +uid 600,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "53112,86909,53462,87259" +) +entryActions (MLText +uid 601,0 +va (VaSet +) +xt "53562,88884,53562,88884" +tm "Actions" +) +inActions (MLText +uid 602,0 +va (VaSet +) +xt "53562,89284,64662,91684" +st "resultSrc <= \"00\" ; +regwrite <= '1' ;" +tm "Actions" +) +exitActions (MLText +uid 603,0 +va (VaSet +) +xt "55112,87084,55112,87084" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 593,0 +ps "CenterOffsetStrategy" +text (MLText +uid 594,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "44775,91278,51475,92478" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*35 (Link +uid 681,0 +shape (CompositeShape +uid 682,0 +va (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +optionalChildren [ +(Pentagon +uid 683,0 +sl 0 +ro 270 +xt "108001,94171,110251,95171" +) +(Line +uid 684,0 +sl 0 +ro 270 +xt "107501,94671,108001,94671" +pts [ +"107501,94671" +"108001,94671" +] +) +] +) +name (TextAssociate +uid 685,0 +ps "CenterOffsetStrategy" +text (Text +uid 686,0 +va (VaSet +font "Verdana,9,1" +) +xt "110751,94171,115851,95371" +st "s0_Fetch" +blo "110751,95171" +tm "LinkName" +) +) +) +*36 (Link +uid 727,0 +shape (CompositeShape +uid 728,0 +va (VaSet +vasetType 1 +fg "65535,65535,0" +bg "0,0,0" +) +optionalChildren [ +(Pentagon +uid 729,0 +sl 0 +ro 90 +xt "-12336,41365,-10086,42365" +) +(Line +uid 730,0 +sl 0 +ro 90 +xt "-10086,41865,-9586,41865" +pts [ +"-9586,41865" +"-10086,41865" +] +) +] +) +name (TextAssociate +uid 731,0 +ps "CenterOffsetStrategy" +text (Text +uid 732,0 +va (VaSet +font "Verdana,9,1" +) +xt "-17811,41253,-12711,42453" +st "s0_Fetch" +blo "-17811,42253" +tm "LinkName" +) +) +) +*37 (Transition +uid 104,0 +shape (Spline +uid 105,0 +va (VaSet +vasetType 3 +) +xt "-2988,25814,8012,25814" +pts [ +"-2988,25814" +"8012,25814" +] +) +start &4 +end &5 +ss 0 +es 0 +cond "rst = '1'" +tb (TransitionBlock +uid 106,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 107,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "-338,24714,5362,26914" +) +autoResize 1 +lineShape (Line +uid 108,0 +va (VaSet +vasetType 3 +) +xt "162,26314,4862,26314" +pts [ +"162,26314" +"4862,26314" +] +) +condition (MLText +uid 109,0 +va (VaSet +) +xt "162,24714,4862,25914" +st "rst = '1'" +tm "Condition" +) +actions (MLText +uid 110,0 +va (VaSet +isHidden 1 +) +xt "-1788,26714,6812,27914" +st "< Automatic >" +tm "Actions" +) +) +tp (TransitionPriority +uid 111,0 +ps "PercentageFromStartStrategy" +shape (Circle +uid 112,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "-2951,24751,-825,26877" +radius 1063 +) +pr (Text +uid 113,0 +va (VaSet +isHidden 1 +) +xt "-2588,25214,-1188,26414" +st "1" +ju 0 +blo "-1888,26214" +tm "TransitionPriority" +) +padding "100,100" +) +) +*38 (Transition +uid 114,0 +shape (Spline +uid 115,0 +va (VaSet +vasetType 3 +) +xt "-3438,20814,8012,20814" +pts [ +"-3438,20814" +"8012,20814" +] +) +start &6 +end &7 +ss 0 +es 0 +tb (TransitionBlock +uid 116,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 117,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "-863,20309,5437,21319" +) +autoResize 1 +lineShape (Line +uid 118,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "2287,21814,2287,21814" +pts [ +"2287,21814" +"2287,21814" +] +) +condition (MLText +uid 119,0 +va (VaSet +) +xt "-363,20214,4937,21414" +tm "Condition" +) +actions (MLText +uid 120,0 +va (VaSet +) +xt "2287,21814,2287,21814" +tm "Actions" +) +) +tp (TransitionPriority +uid 121,0 +ps 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(VaSet +vasetType 1 +fg "0,65535,0" +) +xt "25000,16625,25750,17375" +) +tg (CPTG +uid 108,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 109,0 +va (VaSet +font "Verdana,12,0" +) +xt "17700,16300,24000,17700" +st "resultSrc" +ju 2 +blo "24000,17500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 110,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,12800,70500,13600" +st "resultSrc : OUT std_ulogic_vector (1 DOWNTO 0) +" +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "resultSrc" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 14 +suid 12,0 +) +) +) +*92 (CptPort +uid 111,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 112,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "11250,22625,12000,23375" +) +tg (CPTG +uid 113,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 114,0 +va (VaSet +font "Verdana,12,0" +) +xt "13000,22300,15500,23700" +st "rst" +blo "13000,23500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 115,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,4800,61500,5600" +st "rst : IN std_ulogic ; +" +) +thePort (LogicalPort +lang 11 +decl (Decl +n "rst" +t "std_ulogic" +o 4 +suid 13,0 +) +) +) +*93 (CptPort +uid 339,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 340,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "11250,18625,12000,19375" +) +tg (CPTG +uid 341,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 342,0 +va (VaSet +font "Verdana,12,0" +) +xt "13000,18300,15400,19700" +st "en" +blo "13000,19500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 343,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3200,61500,4000" +st "en : IN std_ulogic ; +" +) +thePort (LogicalPort +lang 11 +decl (Decl +n "en" +t "std_ulogic" +o 2 +suid 14,0 +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "12000,6000,25000,26000" +) +oxt "15000,6000,23000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps 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"Arial,8,0" +) +xt "36200,48000,47500,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*97 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*98 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*99 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*100 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "53200,45200,62600,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*101 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "57200,44000,58800,45000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*102 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "37350,44400,47650,45600" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*103 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*104 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*105 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "36200,47000,46900,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "65535,0,0" +) +packageList *106 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*107 (Text +uid 49,0 +va (VaSet +font "Verdana,9,1" +) +xt "0,0,7600,1200" +st "Package List" +blo "0,1000" +) +*108 (MLText +uid 50,0 +va (VaSet +) +xt "0,1200,17500,7200" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1017,690" +viewArea "-11900,-400,33862,29064" +cachedDiagramExtent "0,0,73000,49000" +hasePageBreakOrigin 1 +pageBreakOrigin "-11000,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,3200,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Verdana,9,1" +) +xt "1000,1000,5000,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,44000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,14800,32200,16000" +st "" +blo "26800,15800" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,16000,30700,17200" +st "" +blo "26800,17000" +) +) +gi *109 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *110 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,0,49400,1200" +st "Declarations" +blo "42000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,1200,45700,2400" +st "Ports:" +blo "42000,2200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,13600,45200,14800" +st "User:" +blo "42000,14600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,50200,1200" +st "Internal User:" +blo "42000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,14800,44000,14800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 366,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +activeModelName "Symbol" +) diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hdl/dataMemory_rtl.vhd b/Libs/RiscV/HEIRV32/SingleCycle/hdl/dataMemory_rtl.vhd new file mode 100644 index 0000000..7db5dc7 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hdl/dataMemory_rtl.vhd @@ -0,0 +1,32 @@ + +ARCHITECTURE rtl OF dataMemory IS + + -- Bank of data + type t_dataBank is array (0 to (2**g_memoryNbBits)-1) of + std_ulogic_vector(g_dataWidth-1 downto 0); + -- A bank of data + signal larr_data: t_dataBank; + +BEGIN + + process(rst, clk) + begin + if rst = '1' then + larr_data <= (others => (others => '0')) after g_tMemWr; + elsif rising_edge(clk) then + if en = '1' and writeEn = '1' then + -- skip the two last bits (since we do only +4) + larr_data(to_integer(unsigned( + address(g_memoryNbBits+1 downto 2) + ))) <= writeData after (g_tMemWr + g_tSetup); + end if; + end if; + end process; + + -- Comb. read + -- skip the two last bits (since we do only +4) + readData <= larr_data(to_integer(unsigned( + address(g_memoryNbBits+1 downto 2) + ))) after g_tMemRd; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_bin.vhd b/Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_bin.vhd new file mode 100644 index 0000000..be4dcc9 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_bin.vhd @@ -0,0 +1,34 @@ +USE std.textio.all; + +ARCHITECTURE bin OF instrMemory IS + + -- Instructions type + type t_instrBank is array (g_memoryNbBits-1 downto 0) of + std_ulogic_vector(g_dataWidth-1 downto 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return t_instrBank is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : t_instrBank; + begin + for i in t_instrBank'range loop + readline(ramContentFile, ramContentFileLine); + read(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Program + constant larr_instr : t_instrBank := ReadRamContentFromFile(g_programFile); + +BEGIN + + -- Comb. read + process(PC) + begin + -- skip the two last bits (since we do only +4) + instruction <= larr_instr(to_integer(PC(g_memoryNbBits+1 downto 2))); + end process; + +END ARCHITECTURE bin; diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_hex.vhd b/Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_hex.vhd new file mode 100644 index 0000000..269f7fe --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_hex.vhd @@ -0,0 +1,36 @@ +library ieee; + use std.textio.all; + use ieee.std_logic_textio.all; + +ARCHITECTURE hex OF instrMemory IS + + -- Instructions type + type t_instrBank is array (0 to (2**g_memoryNbBits)-1) of + std_ulogic_vector(g_dataWidth-1 downto 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return t_instrBank is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : t_instrBank; + begin + for i in t_instrBank'range loop + readline(ramContentFile, ramContentFileLine); + HREAD(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Program + constant larr_instr : t_instrBank := ReadRamContentFromFile(g_programFile); + +BEGIN + + -- Comb. read + process(PC) + begin + -- skip the two last bits (since we do only +4) + instruction <= larr_instr(to_integer(PC(g_memoryNbBits+1 downto 2))) after g_tMemRd; + end process; + +END ARCHITECTURE hex; diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd b/Libs/RiscV/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd new file mode 100644 index 0000000..36ca583 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd @@ -0,0 +1,24 @@ + +ARCHITECTURE rtl OF mainDecoder IS + + signal lvec_controls : std_ulogic_vector(10 downto 0); + +BEGIN + + process(op) + begin + case op is + when "0000011" => lvec_controls <= "10010010000"; -- lw + when "0100011" => lvec_controls <= "00111000000"; -- sw + when "0110011" => lvec_controls <= "1--00000100"; -- R-type + when "1100011" => lvec_controls <= "01000001010"; -- beq + when "0010011" => lvec_controls <= "10010000100"; -- I-type ALU + when "1101111" => lvec_controls <= "11100100001"; -- jal + when others => lvec_controls <= "-----------"; -- not valid + end case; + end process; + + (regwrite, immSrc(1), immSrc(0), ALUSrc, memWrite, resultSrc(1), resultSrc(0), + branch, ALUOp(1), ALUOp(0), jump) <= lvec_controls after g_tDec; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_controlunit_masterversion.vhg._fpf b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_controlunit_masterversion.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_controlunit_masterversion.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_dataMemory_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_dataMemory_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_dataMemory_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_bin.vhd._fpf b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_bin.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_bin.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_hex.vhd._fpf b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_hex.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_hex.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_mainDecoder_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_mainDecoder_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_mainDecoder_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_rtl_instrMemory.vhd._fpf b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_rtl_instrMemory.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_rtl_instrMemory.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/_bin._epf b/Libs/RiscV/HEIRV32/SingleCycle/hds/_bin._epf new file mode 100644 index 0000000..d9dd11a --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/_bin._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom rtl_instrMemory.vhd +DEFAULT_ARCHITECTURE atom instrMemory diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/_controlunit._epf b/Libs/RiscV/HEIRV32/SingleCycle/hds/_controlunit._epf new file mode 100644 index 0000000..81ce754 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/_controlunit._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom masterVersion +DEFAULT_FILE atom control@unit/master@version.bd diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/_datamemory._epf b/Libs/RiscV/HEIRV32/SingleCycle/hds/_datamemory._epf new file mode 100644 index 0000000..c6adbf3 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/_datamemory._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom dataMemory_rtl.vhd diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/_heirv32_sc._epf b/Libs/RiscV/HEIRV32/SingleCycle/hds/_heirv32_sc._epf new file mode 100644 index 0000000..fda94d1 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/_heirv32_sc._epf @@ -0,0 +1,3 @@ +TOP_MARKER atom 1 +DEFAULT_FILE atom heirv32_sc/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/_instrmemory._epf b/Libs/RiscV/HEIRV32/SingleCycle/hds/_instrmemory._epf new file mode 100644 index 0000000..66e01ad --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/_instrmemory._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom hex +DEFAULT_FILE atom instrMemory_hex.vhd diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/_maindecoder._epf b/Libs/RiscV/HEIRV32/SingleCycle/hds/_maindecoder._epf new file mode 100644 index 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b/Libs/RiscV/HEIRV32/SingleCycle/hds/control@unit/master@version.bd new file mode 100644 index 0000000..62e6ff5 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/control@unit/master@version.bd @@ -0,0 +1,4969 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +instances [ +(Instance +name "U_1" +duLibraryName "gates" +duName "and2" +elements [ +(GiElement +name "delay" +type "time" +value "0 ps" +) +] +mwi 0 +uid 645,0 +) +(Instance +name "U_0" +duLibraryName "gates" +duName "or2" +elements [ +(GiElement +name "delay" +type "time" +value "0 ps" +) +] +mwi 0 +uid 667,0 +) +(Instance +name "U_mainDecoder" +duLibraryName "HEIRV32_SC" +duName "mainDecoder" +elements [ +(GiElement +name "g_tDec" +type "time" +value "g_tDec" +) +] +mwi 0 +uid 1321,0 +) +(Instance +name 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"C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\students@version.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "studentsVersion" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit" +) +(vvPair +variable "date" +value "03.11.2022" +) +(vvPair +variable "day" +value "jeu." +) +(vvPair +variable "day_long" +value "jeudi" +) +(vvPair +variable "dd" +value "03" +) +(vvPair +variable "entity_name" +value "controlUnit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value 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a/Libs/RiscV/HEIRV32/SingleCycle/hds/control@unit/symbol.sb b/Libs/RiscV/HEIRV32/SingleCycle/hds/control@unit/symbol.sb new file mode 100644 index 0000000..9a61122 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/control@unit/symbol.sb @@ -0,0 +1,2014 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +libraryRefs [ +"ieee" +"gates" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 15,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 151,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm 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"C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit" +) +(vvPair +variable "date" +value "04.11.2022" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "04" +) +(vvPair +variable "entity_name" +value "controlUnit" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "04.11.2022" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "11:20:59" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "HEIRV32_SC" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/SingleCycle/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "controlUnit" +) +(vvPair +variable "month" +value "nov." +) +(vvPair +variable "month_long" +value "novembre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "11:20:59" +) +(vvPair +variable "unit" +value "controlUnit" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 149,0 +optionalChildren [ +*75 (SymbolBody +uid 8,0 +optionalChildren [ +*76 (CptPort +uid 51,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 52,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "32000,27625,32750,28375" +) +tg (CPTG +uid 53,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 54,0 +va (VaSet +font "Verdana,8,0" +) +xt "25600,27500,31000,28500" +st "ALUControl" +ju 2 +blo "31000,28300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 55,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5600,72000,6400" +st "ALUControl : OUT std_ulogic_vector (2 DOWNTO 0) ;" +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "ALUControl" +t "std_ulogic_vector" +b "(2 DOWNTO 0)" +o 5 +suid 1,0 +) +) +) +*77 (CptPort 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(Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *101 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,0,49400,1200" +st "Declarations" +blo "42000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,1200,45700,2400" +st "Ports:" +blo "42000,2200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,8000,45200,9200" +st "User:" +blo "42000,9000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,50200,1200" +st "Internal User:" +blo "42000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,9200,44000,9200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 308,0 +activeModelName "Symbol:CDM" +) diff --git a/Libs/RiscV/HEIRV32/SingleCycle/hds/heirv32_sc/struct.bd b/Libs/RiscV/HEIRV32/SingleCycle/hds/heirv32_sc/struct.bd new file mode 100644 index 0000000..050c290 --- /dev/null +++ b/Libs/RiscV/HEIRV32/SingleCycle/hds/heirv32_sc/struct.bd @@ -0,0 +1,12244 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +instances [ +(Instance +name "U_pcMux" +duLibraryName "gates" +duName "mux2to1Unsigned" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +(GiElement +name "delay" +type "time" +value "c_tMux" +) +] +mwi 0 +uid 822,0 +) +(Instance +name "U_PCAdder" +duLibraryName "operators" +duName "addUnsigned" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +(GiElement +name "delay" +type "time" +value "c_tAdd" +) +] +mwi 0 +uid 7205,0 +) +(Instance +name "U_beqAdder" +duLibraryName "operators" +duName "addUnsigned" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +(GiElement +name "delay" +type "time" +value "c_tAdd" +) +] +mwi 0 +uid 7299,0 +) +(Instance +name "U_muxSrcB" +duLibraryName "gates" +duName "mux2to1ULogicVector" +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +(GiElement +name "delay" +type "time" +value "c_tMux" +) +] +mwi 0 +uid 7354,0 +) +(Instance +name "U_immextToUnsigned" +duLibraryName "gates" +duName "transUlogUnsigned" +elements [ +(GiElement +name "delay" +type "time" +value "0 ps" +) +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +] +mwi 0 +uid 7384,0 +) +(Instance +name "U_0" +duLibraryName "gates" +duName "transUnsignedUlog" +elements [ +(GiElement +name "delay" +type "time" +value "0 ps" +) +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +] +mwi 0 +uid 8891,0 +) +(Instance +name "U_extend" +duLibraryName "HEIRV32" +duName "extend" +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_tExt" +type "time" +value "c_tExt" +) +] +mwi 0 +uid 9502,0 +) +(Instance +name "U_pcBuffer" +duLibraryName "HEIRV32" +duName "bufferUnsignedEnable" +elements [ +(GiElement +name "g_bitNb" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_tPC" +type "time" +value "c_tPC" +) +] +mwi 0 +uid 9536,0 +) +(Instance +name "U_muxData" +duLibraryName "HEIRV32" +duName "mux4To1ULogVec" +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_tMux" +type "time" +value "c_tMux" +) +] +mwi 0 +uid 9604,0 +) +(Instance +name "U_alu" +duLibraryName "HEIRV32" +duName "ALU" +elements [ +(GiElement +name "g_datawidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_tALU" +type "time" +value "c_tALU" +) +] +mwi 0 +uid 9676,0 +) +(Instance +name "U_registerFile" +duLibraryName "HEIRV32" +duName "registerFile" +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_btnsNb" +type "positive" +value "g_btnsNb" +) +(GiElement +name "g_tRfRd" +type "time" +value "c_tRfRd" +) +(GiElement +name "g_tRfWr" +type "time" +value "c_tRfWr" +) +(GiElement +name "g_tSetup" +type "time" +value "c_tSetup" +) +] +mwi 0 +uid 9738,0 +) +(Instance +name "U_controlUnit" +duLibraryName "HEIRV32_SC" +duName "controlUnit" +elements [ +(GiElement +name "g_tDec" +type "time" +value "c_tDec" +) +] +mwi 0 +uid 9792,0 +) +(Instance +name "U_instrMemory" +duLibraryName "HEIRV32_SC" +duName "instrMemory" +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_memoryNbBits" +type "positive" +value "g_memoryNbBits" +) +(GiElement +name "g_programFile" +type "string" +value "g_programFile" +) +(GiElement +name "g_tMemRd" +type "time" +value "c_tMemRd" +) +] +mwi 0 +uid 9810,0 +) +(Instance +name "U_dataMemory" +duLibraryName "HEIRV32_SC" +duName "dataMemory" +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_memoryNbBits" +type "positive" +value "g_memoryNbBits" +) +(GiElement +name "g_tMemWr" +type "time" +value "c_tMemWr" +) +(GiElement +name "g_tMemRd" +type "time" +value "c_tMemRd" +) +(GiElement +name "g_tSetup" +type "time" +value "c_tSetup" +) +] +mwi 0 +uid 9909,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb2" +number "2" +) +] +libraryRefs [ +"ieee" +"gates" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\heirv32_sc\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\heirv32_sc\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\heirv32_sc" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\heirv32_sc" +) +(vvPair +variable "date" +value "07.11.2022" +) +(vvPair +variable "day" +value "lun." +) +(vvPair +variable "day_long" +value "lundi" +) +(vvPair +variable "dd" +value "07" +) +(vvPair +variable "entity_name" +value "heirv32_sc" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "07.11.2022" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "11:01:53" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "HEIRV32_SC" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/SingleCycle/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "heirv32_sc" +) +(vvPair +variable "month" +value "nov." +) +(vvPair +variable "month_long" +value "novembre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\heirv32_sc\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\heirv32_sc\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "11:01:53" +) +(vvPair +variable "unit" +value "heirv32_sc" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 +shape (Rectangle +uid 12,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "59000,4000,76000,5000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 13,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "59200,4000,70700,5000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*3 (CommentText +uid 14,0 +shape (Rectangle +uid 15,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "76000,0,80000,1000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 16,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "76200,0,79200,1000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*4 (CommentText +uid 17,0 +shape (Rectangle +uid 18,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "59000,2000,76000,3000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 19,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "59200,2000,69200,3000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*5 (CommentText +uid 20,0 +shape (Rectangle +uid 21,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "55000,2000,59000,3000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 22,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "55200,2000,57300,3000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*6 (CommentText +uid 23,0 +shape (Rectangle +uid 24,0 +sl 0 +va (VaSet +vasetType 1 +fg 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(VaSet +font "Courier New,8,0" +) +xt "22000,3200,37500,4000" +st "clk : std_ulogic" +) +) +*16 (SaComponent +uid 822,0 +optionalChildren [ +*17 (CptPort +uid 806,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 807,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "19250,78625,20000,79375" +) +tg (CPTG +uid 808,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 809,0 +va (VaSet +font "Verdana,8,0" +) +xt "20339,78427,22039,79427" +st "in0" +blo "20339,79227" +) +s (Text +uid 832,0 +va (VaSet +) +xt "20339,79427,20339,79427" +blo "20339,79427" +) +) +thePort (LogicalPort +decl (Decl +n "in0" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 1 +suid 1,0 +) +) +) +*18 (CptPort +uid 810,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 811,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "24000,79625,24750,80375" +) +tg (CPTG +uid 812,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 813,0 +va (VaSet +fg "65535,65535,65535" +font "Verdana,8,0" +) +xt "24300,78500,28000,79500" +st "muxOut" +ju 2 +blo "28000,79300" +) +s (Text +uid 833,0 +va (VaSet +) +xt "28000,79500,28000,79500" +ju 2 +blo "28000,79500" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "muxOut" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 3 +suid 2,0 +) +) +) +*19 (CptPort +uid 814,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 815,0 +ro 180 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "22625,77750,23375,78500" +) +tg (CPTG +uid 816,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 817,0 +ro 270 +va (VaSet +font "Verdana,8,0" +) +xt "22400,78833,23400,80433" +st "sel" +ju 2 +blo "23200,78833" +) +s (Text +uid 834,0 +ro 270 +va (VaSet +) +xt "23400,78833,23400,78833" +ju 2 +blo "23400,78833" +) +) +thePort (LogicalPort +decl (Decl +n "sel" +t "std_uLogic" +o 2 +suid 3,0 +) +) +) +*20 (CptPort +uid 818,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 819,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "19250,80625,20000,81375" +) +tg (CPTG +uid 820,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 821,0 +va (VaSet +font "Verdana,8,0" +) +xt "20367,80527,22067,81527" +st "in1" +blo "20367,81327" +) +s (Text +uid 835,0 +va (VaSet +) +xt "20367,81527,20367,81527" +blo "20367,81527" +) +) +thePort (LogicalPort +decl (Decl +n "in1" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 4 +suid 4,0 +) +) +) +] +shape (Mux +uid 823,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "20000,77000,24000,83000" +) +showPorts 0 +oxt "38000,2000,44000,18000" +ttg (MlTextGroup +uid 824,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*21 (Text +uid 825,0 +va (VaSet +isHidden 1 +font "Verdana,8,1" +) +xt "16600,82700,19700,83700" +st "gates" +blo "16600,83500" +tm "BdLibraryNameMgr" +) +*22 (Text +uid 826,0 +va (VaSet +font "Verdana,8,1" +) +xt "16600,83700,26300,84700" +st "mux2to1Unsigned" +blo "16600,84500" +tm "CptNameMgr" +) +*23 (Text +uid 827,0 +va (VaSet +font "Verdana,8,1" +) +xt "16600,84700,21500,85700" +st "U_pcMux" +blo "16600,85500" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 828,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 829,0 +text (MLText +uid 830,0 +va (VaSet +isHidden 1 +font "Verdana,8,0" +) +xt "16000,86000,34500,88000" +st "dataBitNb = c_dataWidth ( positive ) +delay = c_tMux ( time ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +(GiElement +name "delay" +type "time" +value "c_tMux" +) +] +) +viewicon (ZoomableIcon +uid 831,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "20250,81250,21750,82750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +disp 1 +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*24 (Net +uid 1362,0 +lang 11 +decl (Decl +n "zero" +t "std_ulogic" +o 30 +suid 46,0 +) +declText (MLText +uid 1363,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,39200,41000,40000" +st "SIGNAL zero : std_ulogic" +) +) +*25 (Net +uid 1376,0 +lang 11 +decl (Decl +n "resultSrc" +t "std_ulogic_vector" +b "(1 downto 0)" +o 26 +suid 48,0 +) +declText (MLText +uid 1377,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,36000,51000,36800" +st "SIGNAL resultSrc : std_ulogic_vector(1 downto 0)" +) +) +*26 (Net +uid 1388,0 +lang 11 +decl (Decl +n "ALUControl" +t "std_ulogic_vector" +b "(2 DOWNTO 0)" +o 7 +suid 50,0 +) +declText (MLText +uid 1389,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,20800,51000,21600" +st "SIGNAL ALUControl : std_ulogic_vector(2 DOWNTO 0)" +) +) +*27 (Net +uid 1434,0 +lang 11 +decl (Decl +n "immSrc" +t "std_ulogic_vector" +b "(1 DOWNTO 0)" +o 19 +suid 57,0 +) +declText (MLText +uid 1435,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,30400,51000,31200" +st "SIGNAL immSrc : std_ulogic_vector(1 DOWNTO 0)" +) +) +*28 (Net +uid 1436,0 +lang 11 +decl (Decl +n "regwrite" +t "std_ulogic" +o 24 +suid 58,0 +) +declText (MLText +uid 1437,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,34400,41000,35200" +st "SIGNAL regwrite : std_ulogic" +) +) +*29 (Net +uid 1662,0 +lang 11 +decl (Decl +n "instruction" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 20 +suid 59,0 +) +declText (MLText +uid 1663,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,31200,57000,32000" +st "SIGNAL instruction : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*30 (Net +uid 2122,0 +lang 11 +decl (Decl +n "immExt" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 18 +suid 65,0 +) +declText (MLText +uid 2123,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,29600,57000,30400" +st "SIGNAL immExt : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*31 (Net +uid 2450,0 +lang 11 +decl (Decl +n "srcA" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 27 +suid 74,0 +) +declText (MLText +uid 2451,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,36800,57000,37600" +st "SIGNAL srcA : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*32 (Net +uid 2452,0 +lang 11 +decl (Decl +n "srcB" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 28 +suid 75,0 +) +declText (MLText +uid 2453,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,37600,57000,38400" +st "SIGNAL srcB : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*33 (Net +uid 2595,0 +lang 11 +decl (Decl +n "ALUResult" +t "std_ulogic_vector" +b "(c_dataWidth-1 DOWNTO 0)" +o 8 +suid 79,0 +) +declText (MLText +uid 2596,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,21600,57000,22400" +st "SIGNAL ALUResult : std_ulogic_vector(c_dataWidth-1 DOWNTO 0)" +) +) +*34 (Net +uid 4351,0 +lang 11 +decl (Decl +n "dbg_leds" +t "std_ulogic_vector" +b "(31 DOWNTO 0)" +o 5 +suid 93,0 +) +declText (MLText +uid 4352,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,5600,48000,6400" +st "dbg_leds : std_ulogic_vector(31 DOWNTO 0)" +) +) +*35 (PortIoOut +uid 4365,0 +shape (CompositeShape +uid 4366,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4367,0 +sl 0 +ro 270 +xt "173500,13625,175000,14375" +) +(Line +uid 4368,0 +sl 0 +ro 270 +xt "173000,14000,173500,14000" +pts [ +"173000,14000" +"173500,14000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4369,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4370,0 +va (VaSet +) +xt "176000,13400,181200,14600" +st "dbg_leds" +blo "176000,14400" +tm "WireNameMgr" +) +) +) +*36 (HdlText +uid 4373,0 +optionalChildren [ +*37 (EmbeddedText +uid 4478,0 +commentText (CommentText +uid 4479,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 4480,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "118000,10000,170000,26000" +) +oxt "0,0,18000,5000" +text (MLText +uid 4481,0 +va (VaSet +) +xt "118200,10200,170000,24600" +st " + + +dbg_leds(7 downto 0) <= std_ulogic_vector(PC(9 downto 2)); -- no need to read LSBs since does +4 each time + +dbg_leds(14 downto 8) <= instruction(6 downto 0); -- op + +dbg_leds(17 downto 15) <= instruction(14 downto 12); -- funct3 + +dbg_leds(18) <= instruction(30); -- funct7 + +dbg_leds(31 downto 19) <= (others => '0'); -- not used + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 16000 +visibleWidth 52000 +) +) +) +] +shape (Rectangle +uid 4374,0 +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "118000,9000,170000,28000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 4375,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*38 (Text +uid 4376,0 +va (VaSet +font "Verdana,9,1" +) +xt "127800,28800,130200,30000" +st "eb2" +blo "127800,29800" +tm "HdlTextNameMgr" +) +*39 (Text +uid 4377,0 +va (VaSet +font "Verdana,9,1" +) +xt "127800,30000,129000,31200" +st "2" +blo "127800,31000" +tm "HdlTextNumberMgr" +) +] +) +viewicon (ZoomableIcon +uid 4378,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "118250,26250,119750,27750" +iconName "TextFile.png" +iconMaskName "TextFile.msk" +ftype 21 +) +viewiconposition 0 +) +*40 (PortIoIn +uid 4490,0 +shape (CompositeShape +uid 4491,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 4492,0 +sl 0 +ro 270 +xt "9000,41625,10500,42375" +) +(Line +uid 4493,0 +sl 0 +ro 270 +xt "10500,42000,11000,42000" +pts [ +"10500,42000" +"11000,42000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 4494,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 4495,0 +va (VaSet +) +xt "6100,41400,8000,42600" +st "en" +ju 2 +blo "8000,42400" +tm "WireNameMgr" +) +) +) +*41 (Net +uid 4496,0 +lang 11 +decl (Decl +n "en" +t "std_ulogic" +o 3 +suid 97,0 +) +declText (MLText +uid 4497,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,4000,37500,4800" +st "en : std_ulogic" +) +) +*42 (Net +uid 5835,0 +lang 11 +decl (Decl +n "btns" +t "std_ulogic_vector" +b "(g_btnsNb-1 DOWNTO 0)" +o 1 +suid 101,0 +) +declText (MLText +uid 5836,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,2400,52000,3200" +st "btns : std_ulogic_vector(g_btnsNb-1 DOWNTO 0)" +) +) +*43 (PortIoIn +uid 5841,0 +shape (CompositeShape +uid 5842,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5843,0 +sl 0 +ro 270 +xt "89000,87625,90500,88375" +) +(Line +uid 5844,0 +sl 0 +ro 270 +xt "90500,88000,91000,88000" +pts [ +"90500,88000" +"91000,88000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5845,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5846,0 +va (VaSet +) +xt "85100,87400,88000,88600" +st "btns" +ju 2 +blo "88000,88400" +tm "WireNameMgr" +) +) +) +*44 (Net +uid 5847,0 +lang 11 +decl (Decl +n "leds" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 6 +suid 102,0 +) +declText (MLText +uid 5848,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,6400,53500,7200" +st "leds : std_ulogic_vector(g_dataWidth-1 DOWNTO 0)" +) +) +*45 (PortIoOut +uid 5853,0 +shape (CompositeShape +uid 5854,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 5855,0 +sl 0 +ro 90 +xt "89000,88625,90500,89375" +) +(Line +uid 5856,0 +sl 0 +ro 90 +xt "90500,89000,91000,89000" +pts [ +"91000,89000" +"90500,89000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 5857,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 5858,0 +va (VaSet +) +xt "85200,88400,88000,89600" +st "leds" +ju 2 +blo "88000,89400" +tm "WireNameMgr" +) +) +) +*46 (Net +uid 7050,0 +lang 11 +decl (Decl +n "PCTarget" +t "unsigned" +b "(c_dataWidth - 1 downto 0)" +o 15 +suid 103,0 +) +declText (MLText +uid 7051,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,27200,53500,28000" +st "SIGNAL PCTarget : unsigned(c_dataWidth - 1 downto 0)" +) +) +*47 (Net +uid 7052,0 +lang 11 +decl (Decl +n "PCPlus4" +t "unsigned" +b "(c_dataWidth - 1 downto 0)" +o 12 +suid 104,0 +) +declText (MLText +uid 7053,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,24800,53500,25600" +st "SIGNAL PCPlus4 : unsigned(c_dataWidth - 1 downto 0)" +) +) +*48 (Net +uid 7054,0 +decl (Decl +n "PCNext" +t "unsigned" +b "(c_dataWidth-1 DOWNTO 0)" +o 11 +suid 105,0 +) +declText (MLText +uid 7055,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,24000,52500,24800" +st "SIGNAL PCNext : unsigned(c_dataWidth-1 DOWNTO 0)" +) +) +*49 (Net +uid 7170,0 +decl (Decl +n "PCSrc" +t "std_uLogic" +o 14 +suid 107,0 +) +declText (MLText +uid 7171,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,26400,41000,27200" +st "SIGNAL PCSrc : std_uLogic" +) +) +*50 (Net +uid 7180,0 +lang 11 +decl (Decl +n "PC" +t "unsigned" +b "(c_dataWidth - 1 DOWNTO 0)" +o 10 +suid 109,0 +) +declText (MLText +uid 7181,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,23200,53500,24000" +st "SIGNAL PC : unsigned(c_dataWidth - 1 DOWNTO 0)" +) +) +*51 (SaComponent +uid 7205,0 +optionalChildren [ +*52 (CptPort +uid 7190,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7191,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "40250,86625,41000,87375" +) +tg (CPTG +uid 7192,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7193,0 +va (VaSet +) +xt "41000,86400,43300,87600" +st "in1" +blo "41000,87400" +) +s (Text +uid 7194,0 +va (VaSet +) +xt "41000,87600,41000,87600" +blo "41000,87600" +) +) +thePort (LogicalPort +decl (Decl +n "in1" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 1 +suid 1,0 +) +) +) +*53 (CptPort +uid 7195,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7196,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "46000,88625,46750,89375" +) +tg (CPTG +uid 7197,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 7198,0 +va (VaSet +) +xt "43000,88400,46000,89600" +st "out1" +ju 2 +blo "46000,89400" +) +s (Text +uid 7199,0 +va (VaSet +) +xt "46000,89600,46000,89600" +ju 2 +blo "46000,89600" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "out1" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 2 +suid 2,0 +) +) +) +*54 (CptPort +uid 7200,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 7201,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,65535,0" +) +xt "40250,90625,41000,91375" +) +tg (CPTG +uid 7202,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 7203,0 +va (VaSet +) +xt "41000,90400,43300,91600" +st "in2" +blo "41000,91400" +) +s (Text +uid 7204,0 +va (VaSet +) +xt "41000,91600,41000,91600" +blo "41000,91600" +) +) +thePort (LogicalPort +decl (Decl +n "in2" +t "unsigned" +b "(dataBitNb-1 DOWNTO 0)" +o 3 +suid 2003,0 +) +) +) +] +shape (Alu +uid 7206,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "41000,85000,46000,93000" +) +showPorts 0 +oxt "35000,16000,40000,24000" +ttg (MlTextGroup +uid 7207,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*55 (Text +uid 7208,0 +va (VaSet +font "Arial,8,1" +) +xt "34910,91700,38910,92700" +st "operators" +blo "34910,92500" +tm "BdLibraryNameMgr" +) +*56 (Text +uid 7209,0 +va (VaSet +font "Arial,8,1" +) +xt "34910,92700,40710,93700" +st "addUnsigned" +blo "34910,93500" +tm "CptNameMgr" +) +*57 (Text +uid 7210,0 +va (VaSet +font "Arial,8,1" +) +xt "34910,93700,39610,94700" +st "U_PCAdder" +blo "34910,94500" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 7211,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 7212,0 +text (MLText +uid 7213,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "41000,95800,63500,97400" +st "dataBitNb = c_dataWidth ( positive ) +delay = c_tAdd ( time ) " +) +header "" +) +elements [ +(GiElement +name "dataBitNb" +type "positive" +value "c_dataWidth" +) +(GiElement +name "delay" +type "time" +value "c_tAdd" +) +] +) +viewicon (ZoomableIcon +uid 7214,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "41250,91250,42750,92750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +disp 1 +sTC 0 +sT 1 +) +archFileType "UNKNOWN" +) +*58 (SaComponent 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"VerticalLayoutStrategy" +textVec [ +*193 (Text +uid 9607,0 +va (VaSet +font "Verdana,9,1" +) +xt "176000,90800,181000,92000" +st "HEIRV32" +blo "176000,91800" +tm "BdLibraryNameMgr" +) +*194 (Text +uid 9608,0 +va (VaSet +font "Verdana,9,1" +) +xt "176000,92000,186000,93200" +st "mux4To1ULogVec" +blo "176000,93000" +tm "CptNameMgr" +) +*195 (Text +uid 9609,0 +va (VaSet +font "Verdana,9,1" +) +xt "176000,93200,182400,94400" +st "U_muxData" +blo "176000,94200" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 9610,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 9611,0 +text (MLText +uid 9612,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "176000,93600,199500,95200" +st "g_dataWidth = c_dataWidth ( positive ) +g_tMux = c_tMux ( time ) " +) +header "" +) +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_tMux" +type "time" +value "c_tMux" +) +] +) +viewicon (ZoomableIcon +uid 9613,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "178250,87250,179750,88750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*196 (SaComponent +uid 9676,0 +optionalChildren [ +*197 (CptPort +uid 9656,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9657,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "130625,73027,131375,73777" +) +tg (CPTG +uid 9658,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9659,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "130300,74777,131700,77477" +st "ctrl" +ju 2 +blo "131500,74777" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "ctrl" +t "std_ulogic_vector" +b "(2 DOWNTO 0)" +o 1 +suid 6,0 +) +) +) +*198 (CptPort +uid 9660,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9661,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "135000,79625,135750,80375" +) +tg (CPTG +uid 9662,0 +ps "CptPortTextPlaceStrategy" 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"CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 9671,0 +va (VaSet +font "Verdana,12,0" +) +xt "127000,82300,130400,83700" +st "srcB" +blo "127000,83500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "srcB" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 3 +suid 9,0 +) +) +) +*201 (CptPort +uid 9672,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9673,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "135000,77625,135750,78375" +) +tg (CPTG +uid 9674,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9675,0 +va (VaSet +font "Verdana,12,0" +) +xt "130400,77300,134000,78700" +st "zero" +ju 2 +blo "134000,78500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "zero" +t "std_ulogic" +o 5 +suid 10,0 +) +) +) +] +shape (Alu +uid 9677,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "126000,71000,135000,86000" +) +oxt "15000,9000,24000,24000" +ttg (MlTextGroup +uid 9678,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*202 (Text +uid 9679,0 +va (VaSet +font "Verdana,9,1" +) +xt "133500,83300,138500,84500" +st "HEIRV32" +blo "133500,84300" +tm "BdLibraryNameMgr" +) +*203 (Text +uid 9680,0 +va (VaSet +font "Verdana,9,1" +) +xt "133500,84500,136200,85700" +st "ALU" +blo "133500,85500" +tm "CptNameMgr" +) +*204 (Text +uid 9681,0 +va (VaSet +font "Verdana,9,1" +) +xt "133500,85700,136900,86900" +st "U_alu" +blo "133500,86700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 9682,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 9683,0 +text (MLText +uid 9684,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "126000,89600,149500,91200" +st "g_datawidth = c_dataWidth ( positive ) +g_tALU = c_tALU ( time ) " +) +header "" +) +elements [ +(GiElement +name "g_datawidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_tALU" +type "time" +value "c_tALU" +) +] +) +viewicon (ZoomableIcon +uid 9685,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "126250,84250,127750,85750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*205 (SaComponent +uid 9738,0 +optionalChildren [ +*206 (CptPort +uid 9686,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9687,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "84625,70250,85375,71000" +) +tg (CPTG +uid 9688,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9689,0 +va (VaSet +font "Verdana,12,0" +) +xt "83424,71345,85824,72745" +st "clk" +ju 2 +blo "85824,72545" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "clk" +t "std_ulogic" +o 5 +suid 1,0 +) +) +) +*207 (CptPort +uid 9690,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9691,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "81250,74625,82000,75375" +) +tg (CPTG +uid 9692,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 9693,0 +va (VaSet +font "Verdana,12,0" +) +xt "83000,74300,87500,75700" +st "addr1" +blo "83000,75500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "addr1" +t "std_ulogic_vector" +b "(4 DOWNTO 0)" +o 1 +suid 2,0 +) +) +) +*208 (CptPort +uid 9694,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9695,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "81250,82625,82000,83375" +) +tg (CPTG +uid 9696,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 9697,0 +va (VaSet +font "Verdana,12,0" +) +xt "83000,82300,90000,83700" +st "writeData" +blo "83000,83500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "writeData" +t "std_ulogic_vector" +b "(g_dataWidth - 1 DOWNTO 0)" +o 4 +suid 3,0 +) +) +) +*209 (CptPort +uid 9698,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9699,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "99000,75625,99750,76375" +) +tg (CPTG +uid 9700,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9701,0 +va (VaSet +font "Verdana,12,0" +) +xt "94700,75300,98000,76700" +st "RD1" +ju 2 +blo "98000,76500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "RD1" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 8 +suid 4,0 +) +) +) +*210 (CptPort +uid 9702,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9703,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "99000,79625,99750,80375" +) +tg (CPTG +uid 9704,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9705,0 +va (VaSet +font "Verdana,12,0" +) +xt "94700,79300,98000,80700" +st "RD2" +ju 2 +blo "98000,80500" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "RD2" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 9 +suid 5,0 +) +) +) +*211 (CptPort +uid 9706,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9707,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "91625,70250,92375,71000" +) +tg (CPTG +uid 9708,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9709,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "91300,72000,92700,81900" +st "writeEnable3" +ju 2 +blo "92500,72000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "writeEnable3" +t "std_ulogic" +o 6 +suid 6,0 +) +) +) +*212 (CptPort +uid 9710,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9711,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "87625,70250,88375,71000" +) +tg (CPTG +uid 9712,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9713,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "87300,72000,88700,74500" +st "rst" +ju 2 +blo "88500,72000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "rst" +t "std_ulogic" +o 7 +suid 7,0 +) +) +) +*213 (CptPort +uid 9714,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9715,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "81250,76625,82000,77375" +) +tg (CPTG +uid 9716,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 9717,0 +va (VaSet +font "Verdana,12,0" +) +xt "83000,76300,87500,77700" +st "addr2" +blo "83000,77500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "addr2" +t "std_ulogic_vector" +b "(4 DOWNTO 0)" +o 2 +suid 8,0 +) +) +) +*214 (CptPort +uid 9718,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9719,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "81250,78625,82000,79375" +) +tg (CPTG +uid 9720,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 9721,0 +va (VaSet +font "Verdana,12,0" +) +xt "83000,78300,87500,79700" +st "addr3" +blo "83000,79500" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "addr3" +t "std_ulogic_vector" +b "(4 DOWNTO 0)" +o 3 +suid 9,0 +) +) +) +*215 (CptPort +uid 9722,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9723,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "94625,70250,95375,71000" +) +tg (CPTG +uid 9724,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9725,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "94300,72000,95700,74400" +st "en" +ju 2 +blo "95500,72000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "en" +t "std_ulogic" +o 10 +suid 10,0 +) +) +) +*216 (CptPort +uid 9726,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9727,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "93625,85000,94375,85750" +) +tg (CPTG +uid 9728,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 9729,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "93300,80400,94700,84000" +st "btns" +blo "94500,84000" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "btns" +t "std_ulogic_vector" +b "(g_btnsNb-1 DOWNTO 0)" +o 11 +suid 11,0 +) +) +) +*217 (CptPort +uid 9730,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9731,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "95625,85000,96375,85750" +) +tg (CPTG +uid 9732,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 9733,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "95300,80600,96700,84000" +st "leds" +blo "96500,84000" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "leds" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 12 +suid 12,0 +) +) +) +*218 (CommentGraphic +uid 9734,0 +shape (PolyLine2D +pts [ +"83000,71000" +"85000,74000" +] +uid 9735,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "83000,71000,85000,74000" +) +oxt "17000,21000,19000,24000" +) +*219 (CommentGraphic +uid 9736,0 +shape (PolyLine2D +pts [ +"85000,74000" +"87000,71000" +] +uid 9737,0 +layer 8 +sl 0 +va (VaSet +vasetType 1 +transparent 1 +fg "49152,49152,49152" +) +xt "85000,71000,87000,74000" +) +oxt "19000,21000,21000,24000" +) +] +shape (Rectangle +uid 9739,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "82000,71000,99000,85000" +fos 1 +) +oxt "16000,21000,33000,35000" +ttg (MlTextGroup +uid 9740,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*220 (Text +uid 9741,0 +va (VaSet +font "Verdana,9,1" +) +xt "78050,85300,83050,86500" +st "HEIRV32" +blo "78050,86300" +tm "BdLibraryNameMgr" +) +*221 (Text +uid 9742,0 +va (VaSet +font "Verdana,9,1" +) +xt "78050,86500,84950,87700" +st "registerFile" +blo "78050,87500" +tm "CptNameMgr" +) +*222 (Text +uid 9743,0 +va (VaSet +font "Verdana,9,1" +) +xt "78050,87700,86250,88900" +st "U_registerFile" +blo "78050,88700" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 9744,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 9745,0 +text (MLText +uid 9746,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "83000,88600,106500,92600" +st "g_dataWidth = c_dataWidth ( positive ) +g_btnsNb = g_btnsNb ( positive ) +g_tRfRd = c_tRfRd ( time ) +g_tRfWr = c_tRfWr ( time ) +g_tSetup = c_tSetup ( time ) " +) +header "" +) +elements [ +(GiElement +name "g_dataWidth" +type "positive" +value "c_dataWidth" +) +(GiElement +name "g_btnsNb" +type "positive" +value "g_btnsNb" +) +(GiElement +name "g_tRfRd" +type "time" +value "c_tRfRd" +) +(GiElement +name "g_tRfWr" +type "time" +value "c_tRfWr" +) +(GiElement +name "g_tSetup" +type "time" +value "c_tSetup" +) +] +) +viewicon (ZoomableIcon +uid 9747,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "82250,83250,83750,84750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +sed 1 +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +sF 0 +) +archFileType "UNKNOWN" +) +*223 (SaComponent +uid 9792,0 +optionalChildren [ +*224 (CptPort +uid 9748,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 9749,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "98000,48625,98750,49375" +) +tg (CPTG +uid 9750,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 9751,0 +va (VaSet +font "Verdana,8,0" +) +xt "91600,48500,97000,49500" +st "ALUControl" +ju 2 +blo "97000,49300" +) +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n 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+constant c_tMemRd : time := 200 ps; +constant c_tMemWr : time := 60 ps; +constant c_tRfRd : time := 100 ps; +constant c_tRfWr : time := 60 ps; +constant c_tAdd : time := 100 ps;" +tm "BdDeclarativeTextMgr" +) +diagSignalLabel (Text +uid 6,0 +va (VaSet +font "Verdana,9,1" +) +xt "20000,19600,29500,20800" +st "Diagram Signals:" +blo "20000,20600" +) +postUserLabel (Text +uid 7,0 +va (VaSet +font "Verdana,9,1" +) +xt "20000,40000,26400,41200" +st "Post User:" +blo "20000,41000" +) +postUserText (MLText +uid 8,0 +va (VaSet +font "Courier New,8,0" +) +xt "22000,32400,40000,33200" +tm "BdDeclarativeTextMgr" +) +) +commonDM (CommonDM +ldm (LogicalDM +suid 139,0 +usingSuid 1 +emptyRow *355 (LEmptyRow +) +uid 54,0 +optionalChildren [ +*356 (RefLabelRowHdr +) +*357 (TitleRowHdr +) +*358 (FilterRowHdr +) +*359 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*360 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*361 (GroupColHdr +tm "GroupColHdrMgr" +) +*362 (NameColHdr +tm "BlockDiagramNameColHdrMgr" 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(SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,44000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,14800,32200,16000" +st "" +blo "26800,15800" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "26800,16000,30700,17200" +st "" +blo "26800,17000" +) +) +gi *96 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,2900,2150" +st "In0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "Verdana,12,0" +) +xt "0,750,5300,2150" +st "Buffer0" +blo "0,1950" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "unsigned" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *97 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,0,49400,1200" +st "Declarations" +blo "42000,1000" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,1200,45700,2400" +st "Ports:" +blo "42000,2200" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Verdana,9,1" +) +xt "42000,9600,45200,10800" +st "User:" +blo "42000,10600" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Verdana,9,1" +) +xt "42000,0,50200,1200" +st "Internal User:" +blo "42000,1000" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,10800,44000,10800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 287,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/RiscV/HEIRV32/hdl/ALU_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/ALU_rtl.vhd new file mode 100644 index 0000000..82927d7 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/ALU_rtl.vhd @@ -0,0 +1,40 @@ +-- Risc-V ed. 2022 page 250 (pdf page 273) + +ARCHITECTURE rtl OF ALU IS + + signal lvec_res : std_ulogic_vector(res'range); + signal lsig_zero : std_ulogic; + +BEGIN + + lsig_zero <= '1' when lvec_res = (lvec_res'range => '0') else '0'; + zero <= lsig_zero after g_tALU; + res <= lvec_res after g_tALU; + + alu : process(srcA, srcB, ctrl) + begin + case ctrl is + when "000" => -- add + lvec_res <= std_ulogic_vector(resize( + unsigned(srcA) + unsigned(srcB), lvec_res'length + )); + when "001" => -- substract + lvec_res <= std_ulogic_vector(resize( + unsigned(srcA) - unsigned(srcB), lvec_res'length + )); + when "010" => -- AND + lvec_res <= srcA and srcB; + when "011" => -- OR + lvec_res <= srcA or srcB; + when "101" => -- SLT + if srcA < srcB then + lvec_res <= (lvec_res'high downto 1 => '0') & '1'; + else + lvec_res <= (lvec_res'high downto 1 => '0') & '0'; + end if; + when others => -- unknown + lvec_res <= (others => '-'); + end case; + end process alu; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/hdl/aluDecoder_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/aluDecoder_rtl.vhd new file mode 100644 index 0000000..a380f66 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/aluDecoder_rtl.vhd @@ -0,0 +1,27 @@ + +ARCHITECTURE rtl OF aluDecoder IS + signal lsig_rTypeSub : std_ulogic; +BEGIN + lsig_rTypeSub <= funct7 and op; -- true for R-type substract + + decode : process(op, funct3, funct7, ALUOp, lsig_rTypeSub) + begin + case ALUOp is + when "00" => ALUControl <= "000" after g_tDec; -- addition + when "01" => ALUControl <= "001" after g_tDec; -- substraction + when others => + case funct3 is -- R-type or I-type + when "000" => + if lsig_rTypeSub = '1' then + ALUControl <= "001" after g_tDec; -- sub + else + ALUControl <= "000" after g_tDec; -- add, addi + end if; + when "010" => ALUControl <= "101" after g_tDec; -- slt, slti + when "110" => ALUControl <= "011" after g_tDec; -- or, ori + when "111" => ALUControl <= "010" after g_tDec; -- and, andi + when others => ALUControl <= "---" after g_tDec; -- unknown + end case; + end case; + end process decode; +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/hdl/bramAddrReducer_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/bramAddrReducer_rtl.vhd new file mode 100644 index 0000000..23da467 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/bramAddrReducer_rtl.vhd @@ -0,0 +1,6 @@ + +ARCHITECTURE rtl OF bramAddrReducer IS +BEGIN + -- +2 to srr(2) the address (as it makes +4) + addrOut <= std_ulogic_vector(addrIn(addrOut'high+2 downto addrOut'low+2)); +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/hdl/bufferStdULogEnable_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/bufferStdULogEnable_rtl.vhd new file mode 100644 index 0000000..f79b51b --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/bufferStdULogEnable_rtl.vhd @@ -0,0 +1,17 @@ + +ARCHITECTURE rtl OF bufferStdULogEnable IS +BEGIN + + buffering:process(rst, CLK) + begin + if rst = '1' then + out1 <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + out1 <= in1; + end if; + end if; + end process buffering; + +END ARCHITECTURE rtl; + diff --git a/Libs/RiscV/HEIRV32/hdl/bufferUnsignedEnable_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/bufferUnsignedEnable_rtl.vhd new file mode 100644 index 0000000..a7df21b --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/bufferUnsignedEnable_rtl.vhd @@ -0,0 +1,16 @@ + +ARCHITECTURE rtl OF bufferUnsignedEnable IS +BEGIN + + buffering:process(rst, CLK) + begin + if rst = '1' then + out1 <= (others=>'0') after g_tPC; + elsif rising_edge(CLK) then + if EN = '1' then + out1 <= in1 after g_tPC; + end if; + end if; + end process buffering; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/hdl/extend_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/extend_rtl.vhd new file mode 100644 index 0000000..d0d2010 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/extend_rtl.vhd @@ -0,0 +1,26 @@ + +ARCHITECTURE rtl OF extend IS +BEGIN + + extend : process(input, src) + begin + case src is + when "00" => -- I-type + extended <= (12 to 31 => input(31)) & + input(31 downto 20) after g_tExt; + when "01" => -- S-types (stores) + extended <= (12 to 31 => input(31)) & + input(31 downto 25) & input(11 downto 7) after g_tExt; + when "10" => -- B-type (branches) + extended <= (12 to 31 => input(31)) & input(7) & + input(30 downto 25) & input(11 downto 8) & '0' after g_tExt; + when "11" => -- J-type (jal) + extended <= (20 to 31 => input(31)) & + input(19 downto 12) & input(20) & + input(30 downto 21) & '0' after g_tExt; + when others => -- impossible + extended <= (others => '-') after g_tExt; + end case; + end process extend; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/hdl/mux4To1ULogVec_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/mux4To1ULogVec_rtl.vhd new file mode 100644 index 0000000..683819f --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/mux4To1ULogVec_rtl.vhd @@ -0,0 +1,16 @@ + +ARCHITECTURE rtl OF mux4To1ULogVec IS +BEGIN + + muxSelect: process(sel, in1, in2, in3, in4) + begin + case to_integer(unsigned(sel)) is + when 0 => out1 <= in1 after g_tMux; + when 1 => out1 <= in2 after g_tMux; + when 2 => out1 <= in3 after g_tMux; + when 3 => out1 <= in4 after g_tMux; + when others => out1 <= (others => 'X') after g_tMux; + end case; + end process muxSelect; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/hdl/registerFile_rtl.vhd b/Libs/RiscV/HEIRV32/hdl/registerFile_rtl.vhd new file mode 100644 index 0000000..0ab2793 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hdl/registerFile_rtl.vhd @@ -0,0 +1,53 @@ + +ARCHITECTURE rtl OF registerFile IS + -- Bank of register + type t_registersBank is array (31 downto 0) of + std_ulogic_vector(31 downto 0); + -- A bank of registers + signal larr_registers: t_registersBank; + signal lvec_btns : std_ulogic_vector(31 downto 0); +BEGIN + -- Special regs + process(rst, clk) + begin + if rst = '1' then + lvec_btns <= (others => '0'); + elsif rising_edge(clk) then + lvec_btns <= (btns'length to g_datawidth-1 => '0') & btns; + end if; + end process; + + -- Clocked write + process(rst, clk) begin + if rst = '1' then + larr_registers <= (others => (others => '0')) after g_tRfWr; + elsif rising_edge(clk) then + if writeEnable3 = '1' and en = '1' then + larr_registers(to_integer(unsigned(addr3))) <= writeData after (g_tRfWr + g_tSetup); + end if; + end if; + end process; + + -- Comb. read + -- Addr 0 wired to 0s + process(addr1, addr2) begin + if (to_integer(unsigned(addr1)) = 0) then + RD1 <= (others => '0') after g_tRfRd; + elsif (to_integer(unsigned(addr1)) = 31) then -- buttons + RD1 <= lvec_btns after g_tRfRd; + else + RD1 <= larr_registers(to_integer(unsigned(addr1))) after g_tRfRd; + end if; + + if (to_integer(unsigned(addr2)) = 0) then + RD2 <= (others => '0') after g_tRfRd; + elsif (to_integer(unsigned(addr2)) = 31) then -- buttons + RD2 <= lvec_btns after g_tRfRd; + else + RD2 <= larr_registers(to_integer(unsigned(addr2))) after g_tRfRd; + end if; + end process; + + leds <= larr_registers(30); + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_ALU_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_ALU_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_ALU_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bramAddrReducer_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bramAddrReducer_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bramAddrReducer_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferStdULogEnable_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferStdULogEnable_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferStdULogEnable_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferUnsignedEnable_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferUnsignedEnable_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferUnsignedEnable_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_extend_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_extend_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_extend_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mux4To1ULogVec_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mux4To1ULogVec_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mux4To1ULogVec_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_registerFile_rtl.vhd._fpf b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_registerFile_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/.hdlsidedata/_registerFile_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32/hds/@a@l@u/symbol.sb b/Libs/RiscV/HEIRV32/hds/@a@l@u/symbol.sb new file mode 100644 index 0000000..0391d81 --- /dev/null +++ b/Libs/RiscV/HEIRV32/hds/@a@l@u/symbol.sb @@ -0,0 +1,1641 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +(DmPackageRef +library "gates" +unitName "gates" +) +] +libraryRefs [ +"ieee" +"gates" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 10,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 88,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +lang 11 +decl (Decl +n "ctrl" +t "std_ulogic_vector" +b "(2 DOWNTO 0)" +o 1 +suid 6,0 +) +) +uid 214,0 +) +*15 (LogPort +port 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+uid 302,0 +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 129,0 +optionalChildren [ +*51 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *52 (MRCItem +litem &37 +pos 2 +dimension 20 +) +uid 131,0 +optionalChildren [ +*53 (MRCItem +litem &38 +pos 0 +dimension 20 +uid 132,0 +) +*54 (MRCItem +litem &39 +pos 1 +dimension 23 +uid 133,0 +) +*55 (MRCItem +litem &40 +pos 2 +hidden 1 +dimension 20 +uid 134,0 +) +*56 (MRCItem +litem &49 +pos 0 +dimension 20 +uid 224,0 +) +*57 (MRCItem +litem &50 +pos 1 +dimension 20 +uid 303,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 135,0 +optionalChildren [ +*58 (MRCItem +litem &41 +pos 0 +dimension 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+value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\@a@l@u" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\ALU" +) +(vvPair +variable "date" +value "04.11.2022" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "04" +) +(vvPair +variable "entity_name" +value "ALU" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "04.11.2022" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "11:16:47" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "HEIRV32" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../Board/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "ALU" +) +(vvPair +variable "month" +value "nov." +) +(vvPair +variable "month_long" +value "novembre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\@a@l@u\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\ALU\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "11:16:47" +) +(vvPair +variable "unit" +value "ALU" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 86,0 +optionalChildren [ +*65 (SymbolBody +uid 8,0 +optionalChildren [ +*66 (CptPort +uid 189,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 190,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "19625,11027,20375,11777" +) +tg (CPTG +uid 191,0 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(g_dataWidth-1 DOWNTO 0) ;" +) +thePort (LogicalPort +lang 11 +m 1 +decl (Decl +n "res" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 4 +suid 7,0 +) +) +) +*68 (CptPort +uid 199,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 200,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,11625,15000,12375" +) +tg (CPTG +uid 201,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 202,0 +va (VaSet +font "Verdana,12,0" +) +xt "16000,11300,19400,12700" +st "srcA" +blo "16000,12500" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 203,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3200,75000,4000" +st "srcA : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0) ;" +) +thePort (LogicalPort +lang 11 +decl (Decl +n "srcA" +t "std_ulogic_vector" +b "(g_dataWidth-1 DOWNTO 0)" +o 2 +suid 8,0 +) +) +) +*69 (CptPort +uid 204,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 205,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "14250,20625,15000,21375" +) +tg (CPTG +uid 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"$SCRATCH_DIR/CAr/RiscV/HEIRV32/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "registerFile" +) +(vvPair +variable "month" +value "nov." +) +(vvPair +variable "month_long" +value "novembre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\register@file\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\registerFile\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "11:19:02" +) +(vvPair +variable "unit" +value "registerFile" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 100,0 +optionalChildren [ +*85 (SymbolBody +uid 8,0 +optionalChildren [ +*86 (CptPort +uid 51,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 52,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "18625,20250,19375,21000" +) +tg (CPTG +uid 53,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 54,0 +va (VaSet +font "Verdana,12,0" +) +xt "17424,21345,19824,22745" +st "clk" +ju 2 +blo "19824,22545" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 55,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,5600,63000,6400" +st "clk : IN std_ulogic ;" +) +thePort (LogicalPort +lang 11 +decl (Decl +n "clk" +t "std_ulogic" +o 5 +suid 1,0 +) +) +) +*87 (CptPort +uid 56,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 57,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "15250,25625,16000,26375" +) +tg (CPTG +uid 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"writeEnable3 : IN std_ulogic ;" +) +thePort (LogicalPort +lang 11 +decl (Decl +n "writeEnable3" +t "std_ulogic" +o 6 +suid 6,0 +) +) +) +*92 (CptPort +uid 81,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 82,0 +ro 180 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "21625,20250,22375,21000" +) +tg (CPTG +uid 83,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 84,0 +ro 270 +va (VaSet +font "Verdana,12,0" +) +xt "21300,22000,22700,24500" +st "rst" +ju 2 +blo "22500,22000" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 85,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,7200,63000,8000" +st "rst : IN std_ulogic ;" +) +thePort (LogicalPort +lang 11 +decl (Decl +n "rst" +t "std_ulogic" +o 7 +suid 7,0 +) +) +) +*93 (CptPort +uid 184,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 185,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "15250,27625,16000,28375" +) +tg (CPTG +uid 186,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 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a/Libs/RiscV/HEIRV32_test/concat/concatenated.vhd b/Libs/RiscV/HEIRV32_test/concat/concatenated.vhd new file mode 100644 index 0000000..0df33fe --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/concat/concatenated.vhd @@ -0,0 +1,3275 @@ +-- VHDL Entity HEIRV32_test.heirv32_tb.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE2332101) +-- at - 14:52:58 18.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY heirv32_tb IS +-- Declarations + +END heirv32_tb ; + + + + + +-- VHDL Entity HEIRV32_test.universalTester.interface +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 16:01:58 24.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY universalTester IS + GENERIC( + c_btnsNb : positive := 2 + ); + PORT( + btns : OUT std_ulogic_vector (c_btnsNb-1 DOWNTO 0); + clk : OUT std_ulogic; + en : OUT std_ulogic; + rst : OUT std_ulogic + ); + +-- Declarations + +END universalTester ; + + + + + +LIBRARY std; + USE std.textio.all; +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +PACKAGE testUtils IS + + --============================================================================ + -- console output + -- + + procedure print(value : string); + + + --============================================================================ + -- string manipulation + -- + + -- conversion to lowercase + function lc(value : string) return string; + procedure lc(value : inout line); + -- conversion to uppercase + function uc(value : string) return string; + procedure uc(value : inout line); + -- expand a string to a given length + function pad( + value : string; + string_length : natural; + fill_char : character := ' '; + right_justify : boolean := false + ) return string; + -- remove separator characters at beginning and end of line + procedure rm_side_separators( + value : inout line; + separators : in string + ); + procedure rm_side_separators( + value : inout line + ); + -- remove multiple occurences of separator characters + procedure trim_line( + value : inout line; + separators : in string + ); + + procedure trim_line( + value : inout line + ); + -- remove all occurences of separator characters + procedure rm_all_separators( + value : inout line; + separators : in string + ); + + procedure rm_all_separators( + value : inout line + ); + -- find and remove first word + procedure read_first( + value : inout line; + separators : in string; + first : out line + ); + + procedure read_first( + value : inout line; + first : out line + ); + -- find and remove last word + procedure read_last( + value : inout line; + separators : in string; + last : out line + ); + + procedure read_last( + value : inout line; + last : out line + ); + + + --============================================================================ + -- formatted string output + -- + -- format codes: + -- code integer real std_logic std_(u)logic_vector (un)signed time + -- b v v v v binary + -- c character + -- d v v v v v decimal + -- e real numbers, with power of 10 exponent + -- f v v fixed point real numbers + -- s string + -- ts v time in seconds + -- tm v time in milliseconds + -- tu v time in microseconds + -- tn v time in nanoseconds + -- tp v time in picoseconds + -- x v v v v hexadecimal + -- X v v v v hexadecimal with upper-case letters + + function sprintf(format : string; value : integer ) return string; + function sprintf(format : string; value : real ) return string; + function sprintf(format : string; value : std_logic ) return string; + function sprintf(format : string; value : std_ulogic_vector) return string; + function sprintf(format : string; value : std_logic_vector ) return string; + function sprintf(format : string; value : unsigned ) return string; + function sprintf(format : string; value : signed ) return string; + function sprintf(format : string; value : time ) return string; + + --============================================================================ + -- formatted string input + -- + subtype nibbleUlogicType is std_ulogic_vector(3 downto 0); + subtype nibbleUnsignedType is unsigned(3 downto 0); + + function sscanf(value : character) return natural; + function sscanf(value : character) return nibbleUlogicType; + function sscanf(value : character) return nibbleUnsignedType; + function sscanf(value : string ) return natural; + function sscanf(value : string ) return unsigned; + function sscanf(value : string ) return std_ulogic_vector; + function sscanf(value : string ) return time; + + procedure sscanf(value : inout line; time_val : out time); + +END testUtils; + + + + +PACKAGE BODY testUtils IS + + --============================================================================ + -- console output + -- + + procedure print(value : string) is + variable my_line : line; + begin + write(my_line, value); + writeLine(output, my_line); + deallocate(my_line); + end print; + + + --============================================================================ + -- string manipulation + -- + + ------------------------------------------------------------------------------ + -- change to lowercase + ------------------------------------------------------------------------------ + procedure lc(value: inout line) is + variable out_line: line; + begin + for index in value'range loop + if (value(index) >= 'A') and (value(index) <= 'Z') then + value(index) := character'val(character'pos(value(index)) + - character'pos('A') + + character'pos('a') + ); + end if; + end loop; + end lc; + + function lc(value: string) return string is + variable out_line: line; + begin + write(out_line, value); + lc(out_line); + return(out_line.all); + end lc; + + ------------------------------------------------------------------------------ + -- change to uppercase + ------------------------------------------------------------------------------ + procedure uc(value: inout line) is + variable out_line: line; + begin + for index in value'range loop + if (value(index) >= 'a') and (value(index) <= 'z') then + value(index) := character'val(character'pos(value(index)) + - character'pos('a') + + character'pos('A') + ); + end if; + end loop; + end uc; + + function uc(value: string) return string is + variable out_line: line; + begin + write(out_line, value); + uc(out_line); + return(out_line.all); + end uc; + + ------------------------------------------------------------------------------ + -- formatted string output: padding and justifying + ------------------------------------------------------------------------------ + function pad( + value : string; + string_length : natural; + fill_char : character := ' '; + right_justify : boolean := false + ) return string is + variable value_line : line; + variable out_line : line; + variable value_length : natural; + variable shift_sign : boolean; + begin + write(value_line, value); + value_length := value_line.all'length; + if string_length = 0 then + write(out_line, value_line.all); + elsif string_length > value_length then + if right_justify then + if (value_line.all(value_line.all'left) <= '-') and not(fill_char = ' ') then + shift_sign := true; + write(out_line, value_line.all(value_line.all'left)); + end if; + for index in 1 to string_length-value_length loop + write(out_line, fill_char); + end loop; + end if; + if shift_sign then + write(out_line, value_line.all(value_line.all'left+1 to value_line.all'right)); + else + write(out_line, value_line.all); + end if; + if not right_justify then + for index in 1 to string_length-value_length loop + write(out_line, fill_char); + end loop; + end if; + elsif string_length < value_length then + write(out_line, '#'); + write(out_line, value_line.all(value_length-string_length+2 to value_length)); + else + write(out_line, value_line.all); + end if; + deallocate(value_line); + return(out_line.all); + end pad; + + ------------------------------------------------------------------------------ + -- remove separator characters at beginning and end of line + ------------------------------------------------------------------------------ + procedure rm_side_separators( + value : inout line; + separators : in string + ) is + variable input_line : line := value; + variable found : boolean := false; + variable position : integer := 0; + begin + -- remove all separators in the beginning + position := -1; + for character_index in input_line'range loop + found := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + found := true; + end if; + end loop; + if found then + position := character_index; + else + exit; + end if; + end loop; + if position > -1 then + input_line := new string'( input_line(position+1 to input_line'right) ); + end if; + + -- remove all separators in the end + position := -1; + for character_index in input_line'reverse_range loop + found := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + found := true; + end if; + end loop; + if found then + position := character_index; + else + exit; + end if; + end loop; + if position > -1 then + input_line := new string'( input_line(input_line'left to position-1) ); + end if; + + value := input_line; + end; + + procedure rm_side_separators(value : inout line) is + begin + rm_side_separators(value, " :" & ht); + end; + + ------------------------------------------------------------------------------ + -- remove multiple occurences of separator characters, keeping one single + ------------------------------------------------------------------------------ + procedure trim_line( + value : inout line; + separators : in string + ) is + variable input_line: line := value; + variable output_line: line := new string'(""); + variable is_separator, was_separator : boolean := false; + begin + rm_side_separators(input_line); + for character_index in input_line'range loop + is_separator := false; + for separator_index in separators'range loop + if input_line.all(character_index) = separators(separator_index) then + is_separator := true; + end if; + end loop; + if not (is_separator and was_separator) then + write(output_line, input_line.all(character_index)); + end if; + was_separator := is_separator; + end loop; + + value := output_line; + end; + + procedure trim_line(value : inout line) is + begin + trim_line(value, " :" & ht); + end; + + ------------------------------------------------------------------------------ + -- remove all occurences of separator characters + ------------------------------------------------------------------------------ + procedure rm_all_separators( + value : inout line; + separators : in string + ) is + variable input_line : line := value; + variable is_separator : boolean := false; + begin + + -- remove separators from beginn and end of the line + -- rm_separator_be(value, separators); + + -- empty output line + value := new string'(""); + + -- find all separator symbols + for character_index in input_line'range loop + is_separator := false; + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + is_separator := true; + end if; + end loop; + if not is_separator then + write(value, input_line.all(character_index)); + end if; + end loop; + + end; + + procedure rm_all_separators(value : inout line) is + begin + rm_all_separators(value, " _." & ht); + end; + + ------------------------------------------------------------------------------ + -- read first "word" out of a line + ------------------------------------------------------------------------------ + procedure read_first( + value : inout line; + separators : in string; + first : out line + ) is + variable input_line: line; + variable position: natural := 0; + begin + input_line := value; + for character_index in input_line.all'reverse_range loop + for separator_index in separators'range loop + if input_line.all(character_index) = separators(separator_index) then + position := character_index; + end if; + end loop; + end loop; + if position > 1 then + first := new string'(input_line.all(input_line'left to position-1)); + value := new string'(input_line(position+1 to input_line'right)); + else + first := new string'(input_line.all); + value := new string'(""); + end if; + end; + + procedure read_first(value : inout line; first : out line) is + begin + read_first(value, " :" & ht, first); + end; + + ------------------------------------------------------------------------------ + -- read last "word" out of a line + ------------------------------------------------------------------------------ + procedure read_last( + value : inout line; + separators : in string; + last : out line + ) is + variable input_line: line := value; + variable position: natural := 0; + begin + for character_index in input_line'range loop + for separator_index in separators'range loop + if input_line(character_index) = separators(separator_index) then + position := character_index; + end if; + end loop; + end loop; + if position <= input_line'right and + position > 0 then + value := new string'(input_line(input_line'left to position-1)); + last := new string'(input_line(position+1 to input_line'right)); + else + last := new string'(input_line.all); + end if; + end; + + procedure read_last(value : inout line; last : out line) is + begin + read_last(value, " :" & ht, last); + end; + + + --============================================================================ + -- formatted string output, internal functions + -- + + ------------------------------------------------------------------------------ + -- get format specification + ------------------------------------------------------------------------------ + procedure get_format_items( + format : string; + right_justify : out boolean; + add_sign : out boolean; + fill_char : out character; + total_length : out natural; + point_precision : out natural; + format_type : inout line + ) is + variable find_sign : boolean := false; + variable find_padding : boolean := false; + variable find_length : boolean := false; + variable find_precision : boolean := false; + variable find_type : boolean := false; + variable right_justify_int : boolean := true; + variable total_length_int : natural := 0; + variable point_precision_int : natural := 0; + begin + add_sign := false; + fill_char := ' '; + for index in 1 to format'length loop + if find_type then + write(format_type, format(index)); + end if; + if find_precision then + if (format(index) >= '0') and (format(index) <= '9') then + point_precision_int := 10*point_precision_int + character'pos(format(index)) - character'pos('0'); + if format(index+1) >= 'A' then + find_precision := false; + find_type := true; + end if; + end if; + end if; + if find_length then + if (format(index) >= '0') and (format(index) <= '9') then + total_length_int := 10*total_length_int + character'pos(format(index)) - character'pos('0'); + end if; + if format(index) = '.' then + find_length := false; + find_precision := true; + elsif format(index+1) >= 'A' then + find_length := false; + find_type := true; + end if; + end if; + if find_padding then + if format(index) = '0' then + if right_justify_int then + fill_char := '0'; + end if; + end if; + find_padding := false; + if format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + if find_sign then + if format(index) = '-' then + right_justify_int := false; + end if; + if format(index) = '+' then + add_sign := true; + end if; + find_sign := false; + if format(index+1) <= '-' then + find_sign := true; + elsif format(index+1) = '0' then + find_padding := true; + elsif format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + if format(index) = '%' then + if format(index+1) <= '-' then + find_sign := true; + elsif format(index+1) = '0' then + find_padding := true; + elsif format(index+1) >= 'A' then + find_type := true; + else + find_length := true; + end if; + end if; + end loop; + right_justify := right_justify_int; + total_length := total_length_int; + point_precision := point_precision_int; + end get_format_items; + + + ------------------------------------------------------------------------------ + -- formatted string output: converting std_ulogic to character + ------------------------------------------------------------------------------ + function to_character(value: std_ulogic) return character is + variable out_value: character; + begin + case value is + when 'U' => out_value := 'U'; + when 'X' => out_value := 'X'; + when '0' => out_value := '0'; + when '1' => out_value := '1'; + when 'Z' => out_value := 'Z'; + when 'W' => out_value := 'W'; + when 'L' => out_value := 'L'; + when 'H' => out_value := 'H'; + when '-' => out_value := '-'; + end case; + return(out_value); + end to_character; + + ------------------------------------------------------------------------------ + -- formatted string output: binary integer + ------------------------------------------------------------------------------ + function sprintf_b(value: std_ulogic_vector) return string is + variable out_line : line; + begin + for index in value'range loop + write(out_line, to_character(value(index))); + end loop; + return(out_line.all); + end sprintf_b; + + ------------------------------------------------------------------------------ + -- formatted string output: decimal integer + ------------------------------------------------------------------------------ + function sprintf_d( + right_justify : boolean; + add_sign : boolean; + fill_char : character; + string_length : natural; + value : integer + ) return string is + variable value_line : line; + begin + if add_sign and (value >= 0) then + write(value_line, '+'); + end if; + write(value_line, value); + if string_length = 0 then + return(value_line.all); + else + return(pad(value_line.all, string_length, fill_char, right_justify)); + end if; + end sprintf_d; + + ------------------------------------------------------------------------------ + -- formatted string output: fixed point real + ------------------------------------------------------------------------------ + function sprintf_f( + right_justify : boolean; + add_sign : boolean; + fill_char : character; + string_length : natural; + point_precision : natural; + value : real + ) return string is + variable point_precision_int : natural; + variable integer_part : integer; + variable decimal_part : natural; + variable value_line : line; + begin + if point_precision = 0 then + point_precision_int := 6; + else + point_precision_int := point_precision; + end if; + if value >= 0.0 then + integer_part := integer(value-0.5); + else + integer_part := - integer(-value-0.5); + end if; + decimal_part := abs(integer((value-real(integer_part))*(10.0**point_precision_int))); + if add_sign and (value >= 0.0) then + write(value_line, '+'); + end if; + write(value_line, integer_part); + write(value_line, '.'); + write(value_line, sprintf_d(true, false, '0', point_precision_int, decimal_part)); + if string_length = 0 then + return(value_line.all); + else + return(pad(value_line.all, string_length, fill_char, right_justify)); + end if; + end sprintf_f; + + ------------------------------------------------------------------------------ + -- formatted string output: hexadecimal integer + ------------------------------------------------------------------------------ + function sprintf_X( + extend_unsigned : boolean; + value : std_ulogic_vector + ) return string is + variable bit_count : positive; + variable value_line : line; + variable out_line : line; + variable nibble: string(1 to 4); + begin + bit_count := value'length; + while (bit_count mod 4) /= 0 loop + if extend_unsigned then + write(value_line, to_character('0')); + else + write(value_line, to_character(value(value'high))); + end if; + bit_count := bit_count + 1; + end loop; + write(value_line, sprintf_b(value)); + for index in value_line.all'range loop + if (index mod 4) = 0 then + nibble := value_line.all(index-3 to index); + case nibble is + when "0000" => write(out_line, 0); + when "0001" => write(out_line, 1); + when "0010" => write(out_line, 2); + when "0011" => write(out_line, 3); + when "0100" => write(out_line, 4); + when "0101" => write(out_line, 5); + when "0110" => write(out_line, 6); + when "0111" => write(out_line, 7); + when "1000" => write(out_line, 8); + when "1001" => write(out_line, 9); + when "1010" => write(out_line, 'A'); + when "1011" => write(out_line, 'B'); + when "1100" => write(out_line, 'C'); + when "1101" => write(out_line, 'D'); + when "1110" => write(out_line, 'E'); + when "1111" => write(out_line, 'F'); + when others => write(out_line, 'X'); + end case; + end if; + end loop; + return(out_line.all); + end sprintf_X; + + + --============================================================================ + -- formatted string output, interface functions + -- + + ------------------------------------------------------------------------------ + -- integer + ------------------------------------------------------------------------------ + function sprintf(format : string; value : integer) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if format_type.all = "b" then + if string_length = 0 then + string_length := 8; + end if; + return(sprintf_b(std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0)))); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, string_length, value)); + elsif format_type.all = "f" then + return(sprintf_f(right_justify, add_sign, fill_char, + string_length, point_precision, real(value))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if string_length = 0 then + string_length := 8; + end if; + string_length := 4*string_length; + if format_type.all = "X" then + return(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0)))); + else + return(lc(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0))))); + end if; + else + return("Unhandled format type: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- real + ------------------------------------------------------------------------------ + function sprintf(format : string; value : real) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "d") or (point_precision = 0) then + return(sprintf_d(right_justify, add_sign, fill_char, + string_length, integer(value))); + elsif format_type.all = "f" then + return(sprintf_f(right_justify, add_sign, fill_char, + string_length, point_precision, value)); + else + return("Unhandled format type: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_logic + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_logic) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + variable logic_vector: std_logic_vector(1 to 1); + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + logic_vector(1) := value; + return(sprintf(format, std_ulogic_vector(logic_vector))); + else + return("Not a std_logic format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_ulogic_vector + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_ulogic_vector) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable bit_string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + bit_string_length, point_precision, format_type); + if format_type.all = "b" then + return(pad(sprintf_b(value), bit_string_length, fill_char, right_justify)); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(unsigned(value)))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if format_type.all = "X" then + return(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify)); + else + return(lc(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify))); + end if; + else + return("Not a std_ulogic_vector format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- std_logic_vector + ------------------------------------------------------------------------------ + function sprintf(format : string; value : std_logic_vector) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + return(sprintf(format, std_ulogic_vector(value))); + else + return("Not a std_logic_vector format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- unsigned + ------------------------------------------------------------------------------ + function sprintf(format : string; value : unsigned) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if (format_type.all = "b") or (format_type.all = "d") or + (format_type.all = "X") or (format_type.all = "x") then + return(sprintf(format, std_ulogic_vector(value))); + else + return("Not an unsigned format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- signed + ------------------------------------------------------------------------------ + function sprintf(format : string; value : signed) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable bit_string_length : natural; + variable point_precision : natural; + variable format_type : line; + begin + get_format_items(format, right_justify, add_sign, fill_char, + bit_string_length, point_precision, format_type); + if (fill_char = '0') and (value(value'left) = '1') then + fill_char := '1'; + end if; + if format_type.all = "b" then + return(pad(sprintf_b(std_ulogic_vector(value)), bit_string_length, fill_char, right_justify)); + elsif format_type.all = "d" then + return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(signed(value)))); + elsif (format_type.all = "X") or (format_type.all = "x") then + if fill_char = '1' then + fill_char := 'F'; + end if; + if format_type.all = "X" then + return(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify)); + else + return(lc(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify))); + end if; + else + return("Not a signed format: '" & format_type.all & "'"); + end if; + end sprintf; + + ------------------------------------------------------------------------------ + -- time + ------------------------------------------------------------------------------ + function sprintf(format : string; value : time) return string is + variable right_justify : boolean; + variable add_sign : boolean; + variable fill_char : character; + variable string_length : natural; + variable point_precision : natural; + variable format_type : line; + variable scaling : real; + variable base_time : time; + variable unit : string(1 to 3); + begin + get_format_items(format, right_justify, add_sign, fill_char, + string_length, point_precision, format_type); + if format_type.all(format_type.all'left) = 't' then + scaling := 10.0**point_precision; + if format_type.all = "tp" then + base_time := 1 ps; + unit := " ps"; + elsif format_type.all = "tn" then + base_time := 1 ns; + unit := " ns"; + elsif format_type.all = "tu" then + base_time := 1 us; + unit := " us"; + elsif format_type.all = "tm" then + base_time := 1 ms; + unit := " ms"; + elsif format_type.all = "ts" then + base_time := 1 sec; + unit := " s."; + else + return("Undefined time format: '" & format_type.all & "'"); + end if; + if point_precision = 0 then + return(sprintf_d(right_justify, add_sign, fill_char, + string_length, value/base_time) & unit); + else + return(sprintf_f(right_justify, add_sign, fill_char, string_length, + point_precision, real(scaling*value/base_time)/scaling) & unit); + end if; + else + return("Not a time format: '" & format_type.all & "'"); + end if; + end sprintf; + + + --============================================================================ + -- formatted string input + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- read a nibble out of a character + ------------------------------------------------------------------------------ + function sscanf(value : character) return natural is + begin + if (value >= '0') and (value <= '9') then + return(character'pos(value) - character'pos('0')); + elsif (value >= 'a') and (value <= 'f') then + return(character'pos(value) - character'pos('a') + 10); + elsif (value >= 'A') and (value <= 'F') then + return(character'pos(value) - character'pos('A') + 10); + else + return(0); + end if; + end sscanf; + + function sscanf(value : character) return nibbleUnsignedType is + begin + return(to_unsigned(sscanf(value), nibbleUnsignedType'length)); + end sscanf; + + function sscanf(value : character) return nibbleUlogicType is + variable unsigned_value : nibbleUnsignedType; + begin + unsigned_value := sscanf(value); + return(std_ulogic_vector(unsigned_value)); + end sscanf; + + ------------------------------------------------------------------------------ + -- read an binary word out of a string + ------------------------------------------------------------------------------ + function sscanf(value : string) return natural is + variable integer_value : natural; + begin + integer_value := 0; + for index in value'left to value'right loop + integer_value := integer_value*16 + sscanf(value(index)); + end loop; + return(integer_value); + end; + + function sscanf(value : string) return unsigned is + variable unsigned_value : unsigned(4*value'length-1 downto 0); + begin + unsigned_value := to_unsigned(0,unsigned_value'length); + for index in value'left to value'right loop + unsigned_value := shift_left(unsigned_value,4) + to_unsigned(sscanf(value(index)),4); + end loop; + return(unsigned_value); + end; + + function sscanf(value : string) return std_ulogic_vector is + variable unsigned_value : unsigned(4*value'length-1 downto 0); + begin + unsigned_value := sscanf(value); + return(std_ulogic_vector(unsigned_value)); + end; + + ------------------------------------------------------------------------------ + -- read time from a string + -- time can be formated as follows: + -- "1ps" or "1 ps" or " 1 ps " or " 1ps" + -- possible time units are: hr, min, sec, ms, us, ns, ps, fs + ------------------------------------------------------------------------------ + procedure sscanf( + value : inout line; + time_val : out time + ) is + variable time_line : line := value; + variable time_base : string(1 to 3); + variable time_value : integer; + variable time_int : time; + begin + -- remove all spaces and tabs + rm_all_separators(time_line); + + -- strip time base (3 last characters) + time_base := time_line(time_line'right-2 to time_line'right); + + -- separate time value and base + if time_base(2 to 3) = "hr" then + time_int := 1 hr; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base = "min" then + time_int := 1 min; + time_value := integer'value(time_line(time_line'left to time_line'right -3)); + elsif time_base = "sec" then + time_int := 1 sec; + time_value := integer'value(time_line(time_line'left to time_line'right -3)); + elsif time_base(2 to 3) = "ms" then + time_int := 1 ms; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "us" then + time_int := 1 us; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "ns" then + time_int := 1 ns; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "ps" then + time_int := 1 ps; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + elsif time_base(2 to 3) = "fs" then + time_int := 1 fs; + time_value := integer'value(time_line(time_line'left to time_line'right -2)); + else + time_int := 0 ps; + time_value := 1; + end if; + + -- build time from value and base + time_val := time_int * time_value; + + end; + + function sscanf(value : string) return time is + variable value_line : line; + variable time_val : time; + begin + value_line := new string'(value); + sscanf(value_line, time_val); + return(time_val); + end; + +END testUtils; + + + + +LIBRARY std; + USE std.textio.ALL; + +LIBRARY ieee; + USE ieee.std_logic_textio.ALL; + +LIBRARY Common_test; + USE Common_test.testutils.all; + +ARCHITECTURE test OF universalTester IS + + constant clockPeriod : time := 1.0/66E6 * 1 sec; + signal sClock : std_uLogic := '1'; + signal sReset : std_uLogic ; + + signal testInfo : string(1 to 40) := (others => ' '); + +BEGIN + + ------------------------------------------------------------------------------ + -- reset and clock + sReset <= '1', '0' after 3.5*clockPeriod; + rst <= sReset; + + sClock <= not sClock after clockPeriod/2; + clk <= transport sClock after 0.9*clockPeriod; + + btns <= (others => '1'), (others=>'0') after 4.15 us; + + process + -- Wait list + -- 3 clk for beq + -- 4 clk for others + -- 5 clk for lw + begin + en <= '0'; + + testInfo <= pad("Wait reset", testInfo'length); + wait until rst = '0'; + + while true loop + en <= '1'; + + testInfo <= pad("Running", testInfo'length); + wait; + + end loop; + end process; + +END ARCHITECTURE test; + + + + + +-- VHDL Entity HEIRV32.heirv32.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 10:23:07 21.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY heirv32 IS + GENERIC( + g_programFile : string := "$SIMULATION_DIR/code.txt"; + g_btnsNb : positive := 2; + g_dataWidth : positive := 32 + ); + PORT( + btns : IN std_ulogic_vector (g_btnsNb-1 DOWNTO 0); + clk : IN std_ulogic; + en : IN std_ulogic; + rst : IN std_ulogic; + dbg_leds : OUT std_ulogic_vector (31 DOWNTO 0); + leds : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + +-- Declarations + +END heirv32 ; + + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +PACKAGE gates IS + +-- constant gateDelay: time := 1 ns; + constant gateDelay: time := 0.1 ns; + +END gates; + + + + +-- VHDL Entity gates.transUnsignedUlog.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 14:35:04 11.09.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; + USE gates.gates.all; + +ENTITY transUnsignedUlog IS + GENERIC( + delay : time := gateDelay; + dataBitNb : positive := 8 + ); + PORT( + in1 : IN unsigned (dataBitNb-1 DOWNTO 0); + out1 : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END transUnsignedUlog ; + + + + + +ARCHITECTURE sim OF transUnsignedUlog IS +BEGIN + out1 <= std_ulogic_vector(in1) after delay; +END ARCHITECTURE sim; + + + + +-- VHDL Entity HEIRV32.ALU.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 13:26:28 11.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY ALU IS + GENERIC( + g_datawidth : positive := 32 + ); + PORT( + ctrl : IN std_ulogic_vector (2 DOWNTO 0); + srcA : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + srcB : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + res : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + zero : OUT std_ulogic + ); + +-- Declarations + +END ALU ; + + + + + +-- Risc-V ed. 2022 page 250 (pdf page 273) + +ARCHITECTURE rtl OF ALU IS + + signal lvec_res : std_ulogic_vector(res'range); + +BEGIN + + zero <= '1' when lvec_res = (lvec_res'range => '0') else '0'; + res <= lvec_res; + + alu : process(srcA, srcB, ctrl) + begin + case ctrl is + when "000" => -- add + lvec_res <= std_ulogic_vector(resize( + unsigned(srcA) + unsigned(srcB), lvec_res'length + )); + when "001" => -- substract + lvec_res <= std_ulogic_vector(resize( + unsigned(srcA) - unsigned(srcB), lvec_res'length + )); + when "010" => -- AND + lvec_res <= srcA and srcB; + when "011" => -- OR + lvec_res <= srcA or srcB; + when "101" => -- SLT + if srcA < srcB then + lvec_res <= (lvec_res'high downto 1 => '0') & '1'; + else + lvec_res <= (lvec_res'high downto 1 => '0') & '0'; + end if; + when others => -- unknown + lvec_res <= (others => '-'); + end case; + end process alu; + +END ARCHITECTURE rtl; + + + + +-- VHDL Entity HEIRV32.bufferStdULogEnable.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:01:42 11.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY bufferStdULogEnable IS + GENERIC( + g_dataWidth : positive := 32 + ); + PORT( + clk : IN std_ulogic; + en : IN std_uLogic; + in1 : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + rst : IN std_ulogic; + out1 : OUT std_ulogic_vector (g_dataWidth - 1 DOWNTO 0) + ); + +-- Declarations + +END bufferStdULogEnable ; + + + + + + +ARCHITECTURE rtl OF bufferStdULogEnable IS +BEGIN + + buffering:process(rst, CLK) + begin + if rst = '1' then + out1 <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + out1 <= in1; + end if; + end if; + end process buffering; + +END ARCHITECTURE rtl; + + + + + +-- VHDL Entity gates.and2.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 14:34:52 11.09.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; +LIBRARY gates; + USE gates.gates.all; + +ENTITY and2 IS + GENERIC( + delay : time := gateDelay + ); + PORT( + in1 : IN std_uLogic; + in2 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END and2 ; + + + + + +ARCHITECTURE sim OF and2 IS +BEGIN + out1 <= in1 and in2 after delay; +END ARCHITECTURE sim; + + + + +-- VHDL Entity HEIRV32.controlUnit.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:37:23 24.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY controlUnit IS + GENERIC( + g_datawidth : positive := 32 + ); + PORT( + clk : IN std_ulogic; + en : IN std_ulogic; + funct3 : IN std_ulogic_vector (2 DOWNTO 0); + funct7 : IN std_ulogic; + op : IN std_ulogic_vector (6 DOWNTO 0); + rst : IN std_ulogic; + zero : IN std_ulogic; + ALUControl : OUT std_ulogic_vector (2 DOWNTO 0); + ALUSrcA : OUT std_ulogic_vector (1 DOWNTO 0); + ALUSrcB : OUT std_ulogic_vector (1 DOWNTO 0); + IRWrite : OUT std_ulogic; + PCWrite : OUT std_ulogic; + adrSrc : OUT std_uLogic; + immSrc : OUT std_ulogic_vector (1 DOWNTO 0); + memWrite : OUT std_ulogic; + regwrite : OUT std_ulogic; + resultSrc : OUT std_ulogic_vector (1 DOWNTO 0) + ); + +-- Declarations + +END controlUnit ; + + + + + +-- VHDL Entity gates.or2.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 14:35:09 11.09.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; +LIBRARY gates; + USE gates.gates.all; + +ENTITY or2 IS + GENERIC( + delay : time := gateDelay + ); + PORT( + in1 : IN std_uLogic; + in2 : IN std_uLogic; + out1 : OUT std_uLogic + ); + +-- Declarations + +END or2 ; + + + + + +ARCHITECTURE sim OF or2 IS +BEGIN + out1 <= in1 or in2 after delay; +END ARCHITECTURE sim; + + + + +-- VHDL Entity HEIRV32.aluDecoder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:46:03 04.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY aluDecoder IS + PORT( + ALUOp : IN std_ulogic_vector (1 DOWNTO 0); + funct3 : IN std_ulogic_vector (2 DOWNTO 0); + funct7 : IN std_ulogic; + op : IN std_ulogic; + ALUControl : OUT std_ulogic_vector (2 DOWNTO 0) + ); + +-- Declarations + +END aluDecoder ; + + + + + + +ARCHITECTURE rtl OF aluDecoder IS + signal lsig_rTypeSub : std_ulogic; +BEGIN + lsig_rTypeSub <= funct7 and op; -- true for R-type substract + + decode : process(op, funct3, funct7, ALUOp, lsig_rTypeSub) + begin + case ALUOp is + when "00" => ALUControl <= "000"; -- addition + when "01" => ALUControl <= "001"; -- substraction + when others => + case funct3 is -- R-type or I-type + when "000" => + if lsig_rTypeSub = '1' then + ALUControl <= "001"; -- sub + else + ALUControl <= "000"; -- add, addi + end if; + when "010" => ALUControl <= "101"; -- slt, slti + when "110" => ALUControl <= "011"; -- or, ori + when "111" => ALUControl <= "010"; -- and, andi + when others => ALUControl <= "---"; -- unknown + end case; + end case; + end process decode; +END ARCHITECTURE rtl; + + + + +-- VHDL Entity HEIRV32.instrDecoder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:47:22 04.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY instrDecoder IS + PORT( + op : IN std_ulogic_vector (6 DOWNTO 0); + immSrc : OUT std_ulogic_vector (1 DOWNTO 0) + ); + +-- Declarations + +END instrDecoder ; + + + + + + +ARCHITECTURE rtl OF instrDecoder IS +BEGIN + + decode : process(op) + begin + case op is + when "0000011" => immSrc <= "00"; -- lw + when "0100011" => immSrc <= "01"; -- sw + when "0110011" => immSrc <= "--"; -- R-type + when "1100011" => immSrc <= "10"; -- beq + when "0010011" => immSrc <= "00"; -- l-type ALU + when "1101111" => immSrc <= "11"; -- jal + when others => immSrc <= "--"; -- unknwon + end case; + end process decode; + +END ARCHITECTURE rtl; + + + + +-- VHDL Entity HEIRV32.mainFSM.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE2332101) +-- at - 09:29:07 18.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY mainFSM IS + PORT( + clk : IN std_ulogic; + en : IN std_ulogic; + op : IN std_ulogic_vector (6 DOWNTO 0); + rst : IN std_ulogic; + ALUOp : OUT std_ulogic_vector (1 DOWNTO 0); + ALUSrcA : OUT std_ulogic_vector (1 DOWNTO 0); + ALUSrcB : OUT std_ulogic_vector (1 DOWNTO 0); + IRWrite : OUT std_ulogic; + PCupdate : OUT std_uLogic; + adrSrc : OUT std_uLogic; + branch : OUT std_uLogic; + memWrite : OUT std_ulogic; + regwrite : OUT std_ulogic; + resultSrc : OUT std_ulogic_vector (1 DOWNTO 0) + ); + +-- Declarations + +END mainFSM ; + + + + + +-- +-- VHDL Architecture HEIRV32.mainFSM.fsm +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:37:29 24.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ARCHITECTURE fsm OF mainFSM IS + + TYPE STATE_TYPE IS ( + s0_Fetch, + s1_Decode, + s2_MemAdr, + s6_ExecuteR, + s8_ExecuteI, + s9_JAL, + s10_BEQ, + s3_MemRead, + s4_MemWB, + s5_MemWrite, + s7_ALUWB + ); + + -- Declare current and next state signals + SIGNAL current_state : STATE_TYPE; + SIGNAL next_state : STATE_TYPE; + +BEGIN + + ----------------------------------------------------------------- + clocked_proc : PROCESS ( + clk, + rst + ) + ----------------------------------------------------------------- + BEGIN + IF (rst = '1') THEN + current_state <= s0_Fetch; + ELSIF (clk'EVENT AND clk = '1') THEN + current_state <= next_state; + END IF; + END PROCESS clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : PROCESS ( + current_state, + en, + op + ) + ----------------------------------------------------------------- + BEGIN + CASE current_state IS + WHEN s0_Fetch => + IF (en = '1') THEN + next_state <= s1_Decode; + ELSE + next_state <= s0_Fetch; + END IF; + WHEN s1_Decode => + IF ((op = "0000011" OR op = "0100011") AND en = '1') THEN + next_state <= s2_MemAdr; + ELSIF (op = "0110011" AND en = '1') THEN + next_state <= s6_ExecuteR; + ELSIF (op = "0010011" AND en = '1') THEN + next_state <= s8_ExecuteI; + ELSIF (op = "1101111" AND en = '1') THEN + next_state <= s9_JAL; + ELSIF (op = "1100011" AND en = '1') THEN + next_state <= s10_BEQ; + ELSIF (en = '1') THEN + next_state <= s0_Fetch; + ELSE + next_state <= s1_Decode; + END IF; + WHEN s2_MemAdr => + IF (op = "0000011" AND en = '1') THEN + next_state <= s3_MemRead; + ELSIF (op = "0100011" AND en = '1') THEN + next_state <= s5_MemWrite; + ELSIF (en = '1') THEN + next_state <= s0_Fetch; + ELSE + next_state <= s2_MemAdr; + END IF; + WHEN s6_ExecuteR => + IF (en = '1') THEN + next_state <= s7_ALUWB; + ELSE + next_state <= s6_ExecuteR; + END IF; + WHEN s8_ExecuteI => + IF (en = '1') THEN + next_state <= s7_ALUWB; + ELSE + next_state <= s8_ExecuteI; + END IF; + WHEN s9_JAL => + IF (en = '1') THEN + next_state <= s7_ALUWB; + ELSE + next_state <= s9_JAL; + END IF; + WHEN s10_BEQ => + IF (en = '1') THEN + next_state <= s0_Fetch; + ELSE + next_state <= s10_BEQ; + END IF; + WHEN s3_MemRead => + IF (en = '1') THEN + next_state <= s4_MemWB; + ELSE + next_state <= s3_MemRead; + END IF; + WHEN s4_MemWB => + IF (en = '1') THEN + next_state <= s0_Fetch; + ELSE + next_state <= s4_MemWB; + END IF; + WHEN s5_MemWrite => + IF (en = '1') THEN + next_state <= s0_Fetch; + ELSE + next_state <= s5_MemWrite; + END IF; + WHEN s7_ALUWB => + IF (en = '1') THEN + next_state <= s0_Fetch; + ELSE + next_state <= s7_ALUWB; + END IF; + WHEN OTHERS => + next_state <= s0_Fetch; + END CASE; + END PROCESS nextstate_proc; + + ----------------------------------------------------------------- + output_proc : PROCESS ( + current_state + ) + ----------------------------------------------------------------- + BEGIN + -- Default Assignment + ALUOp <= "00"; + ALUSrcA <= "00"; + ALUSrcB <= "00"; + IRWrite <= '0'; + PCupdate <= '0'; + adrSrc <= '0'; + branch <= '0'; + memWrite <= '0'; + regwrite <= '0'; + resultSrc <= "00"; + + -- Combined Actions + CASE current_state IS + WHEN s0_Fetch => + adrSrc <= '0' ; + IRWrite <= '1' ; + ALUSrcA <= "00" ; + ALUSrcB <= "10" ; + ALUOp <= "00" ; + resultSrc <= "10" ; + PCupdate <= '1' ; + WHEN s1_Decode => + ALUSrcA <= "01" ; + ALUSrcB <= "01" ; + ALUOp <= "00" ; + WHEN s2_MemAdr => + ALUSrcA <= "10" ; + ALUSrcB <= "01" ; + ALUOp <= "00" ; + WHEN s6_ExecuteR => + ALUSrcA <= "10" ; + ALUSrcB <= "00" ; + ALUOp <= "10" ; + WHEN s8_ExecuteI => + ALUSrcA <= "10" ; + ALUSrcB <= "01" ; + ALUOp <= "10" ; + WHEN s9_JAL => + ALUSrcA <= "01" ; + ALUSrcB <= "10" ; + ALUOp <= "00" ; + resultSrc <= "00" ; + PCupdate <= '1' ; + WHEN s10_BEQ => + ALUSrcA <= "10" ; + ALUSrcB <= "00" ; + ALUOp <= "01" ; + resultSrc <= "00" ; + branch <= '1' ; + WHEN s3_MemRead => + adrSrc <= '1' ; + resultSrc <= "00" ; + WHEN s4_MemWB => + resultSrc <= "01" ; + regwrite <= '1' ; + WHEN s5_MemWrite => + adrSrc <= '1' ; + resultSrc <= "00" ; + memWrite <= '1' ; + WHEN s7_ALUWB => + resultSrc <= "00" ; + regwrite <= '1' ; + WHEN OTHERS => + NULL; + END CASE; + END PROCESS output_proc; + +END fsm; + + + + +-- +-- VHDL Architecture HEIRV32.controlUnit.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:37:23 24.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +LIBRARY HEIRV32; + +ARCHITECTURE struct OF controlUnit IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL ALUOp : std_ulogic_vector(1 DOWNTO 0); + SIGNAL PCupdate : std_uLogic; + SIGNAL branch : std_uLogic; + SIGNAL out1 : std_uLogic; + + + -- Component Declarations + COMPONENT and2 + GENERIC ( + delay : time := gateDelay + ); + PORT ( + in1 : IN std_uLogic ; + in2 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT or2 + GENERIC ( + delay : time := gateDelay + ); + PORT ( + in1 : IN std_uLogic ; + in2 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT aluDecoder + PORT ( + ALUOp : IN std_ulogic_vector (1 DOWNTO 0); + funct3 : IN std_ulogic_vector (2 DOWNTO 0); + funct7 : IN std_ulogic ; + op : IN std_ulogic ; + ALUControl : OUT std_ulogic_vector (2 DOWNTO 0) + ); + END COMPONENT; + COMPONENT instrDecoder + PORT ( + op : IN std_ulogic_vector (6 DOWNTO 0); + immSrc : OUT std_ulogic_vector (1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT mainFSM + PORT ( + clk : IN std_ulogic ; + en : IN std_ulogic ; + op : IN std_ulogic_vector (6 DOWNTO 0); + rst : IN std_ulogic ; + ALUOp : OUT std_ulogic_vector (1 DOWNTO 0); + ALUSrcA : OUT std_ulogic_vector (1 DOWNTO 0); + ALUSrcB : OUT std_ulogic_vector (1 DOWNTO 0); + IRWrite : OUT std_ulogic ; + PCupdate : OUT std_uLogic ; + adrSrc : OUT std_uLogic ; + branch : OUT std_uLogic ; + memWrite : OUT std_ulogic ; + regwrite : OUT std_ulogic ; + resultSrc : OUT std_ulogic_vector (1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : aluDecoder USE ENTITY HEIRV32.aluDecoder; + FOR ALL : and2 USE ENTITY gates.and2; + FOR ALL : instrDecoder USE ENTITY HEIRV32.instrDecoder; + FOR ALL : mainFSM USE ENTITY HEIRV32.mainFSM; + FOR ALL : or2 USE ENTITY gates.or2; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + U_1 : and2 + GENERIC MAP ( + delay => gateDelay + ) + PORT MAP ( + in1 => zero, + in2 => branch, + out1 => out1 + ); + U_0 : or2 + GENERIC MAP ( + delay => gateDelay + ) + PORT MAP ( + in1 => out1, + in2 => PCupdate, + out1 => PCWrite + ); + U_2 : aluDecoder + PORT MAP ( + ALUOp => ALUOp, + funct3 => funct3, + funct7 => funct7, + op => op(5), + ALUControl => ALUControl + ); + U_4 : instrDecoder + PORT MAP ( + op => op, + immSrc => immSrc + ); + U_mainFSM : mainFSM + PORT MAP ( + clk => clk, + en => en, + op => op, + rst => rst, + ALUOp => ALUOp, + ALUSrcA => ALUSrcA, + ALUSrcB => ALUSrcB, + IRWrite => IRWrite, + PCupdate => PCupdate, + adrSrc => adrSrc, + branch => branch, + memWrite => memWrite, + regwrite => regwrite, + resultSrc => resultSrc + ); + +END struct; + + + + +-- VHDL Entity HEIRV32.extend.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE2332101) +-- at - 12:47:32 18.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY extend IS + GENERIC( + g_dataWidth : positive := 32 + ); + PORT( + input : IN std_ulogic_vector (31 DOWNTO 7); + src : IN std_ulogic_vector (1 DOWNTO 0); + extended : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + +-- Declarations + +END extend ; + + + + + + +ARCHITECTURE rtl OF extend IS +BEGIN + + extend : process(input, src) + begin + case src is + when "00" => -- I-type + extended <= (12 to 31 => input(31)) & + input(31 downto 20); + when "01" => -- S-types (stores) + extended <= (12 to 31 => input(31)) & + input(31 downto 25) & input(11 downto 7); + when "10" => -- B-type (branches) + extended <= (12 to 31 => input(31)) & input(7) & + input(30 downto 25) & input(11 downto 8) & '0'; + when "11" => -- J-type (jal) + extended <= (20 to 31 => input(31)) & + input(19 downto 12) & input(20) & + input(30 downto 21) & '0'; + when others => -- impossible + extended <= (others => '-'); + end case; + end process extend; + +END ARCHITECTURE rtl; + + + + +-- VHDL Entity HEIRV32.instructionDataMemory.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 18:08:43 18.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY instructionDataMemory IS + GENERIC( + g_dataWidth : positive := 32; + g_addrWidth : positive := 10; + g_programFile : string := "" + ); + PORT( + address : IN unsigned (g_dataWidth-1 DOWNTO 0); + clk : IN std_ulogic; + en : IN std_ulogic; + writeData : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + writeEnable : IN std_ulogic; + readData : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + +-- Declarations + +END instructionDataMemory ; + + + + + +-- VHDL Entity Memory.bram.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:51:22 11.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY bram IS + GENERIC( + addressBitNb : positive := 8; + dataBitNb : positive := 8; + initFile : string := "bramInit.txt" + ); + PORT( + clock : IN std_ulogic; + en : IN std_ulogic; + writeEn : IN std_ulogic; + addressIn : IN std_ulogic_vector (addressBitNb-1 DOWNTO 0); + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END bram ; + + + + + +library ieee; + use std.textio.all; + use ieee.std_logic_textio.all; + +ARCHITECTURE hexRead OF bram IS + -- Define ramContent type + type ramContentType is array(0 to (2**addressBitNb)-1) of std_logic_vector(dataBitNb-1 DOWNTO 0); + + -- Define function to create initvalue signal + impure function ReadRamContentFromFile(ramContentFilenAme : in string) return ramContentType is + FILE ramContentFile : text is in ramContentFilenAme; + variable ramContentFileLine : line; + variable ramContent : ramContentType; + begin + for i in ramContentType'range loop + readline(ramContentFile, ramContentFileLine); + HREAD(ramContentFileLine, ramContent(i)); + end loop; + return ramContent; + end function; + + -- Declare ramContent signal + shared variable ramContent: ramContentType := ReadRamContentFromFile(initFile); + +BEGIN + + -- Port A + process(clock) + begin + if clock'event and clock='1' then + if en = '1' then + if writeEn = '1' then + dataOut <= dataIn; + ramContent(to_integer(unsigned(addressIn))) := std_logic_vector(dataIn); + else + dataOut <= to_stdulogicvector(ramContent(to_integer(unsigned(addressIn)))); + end if; + end if; + end if; + end process; + +END ARCHITECTURE hexRead; + + + + +-- VHDL Entity HEIRV32.bramAddrReducer.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE2332111) +-- at - 16:20:19 11.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY bramAddrReducer IS + GENERIC( + g_dataWidth : positive := 32; + g_addrWidth : positive := 10 + ); + PORT( + addrIn : IN unsigned (g_dataWidth-1 DOWNTO 0); + addrOut : OUT std_ulogic_vector (g_addrWidth-1 DOWNTO 0) + ); + +-- Declarations + +END bramAddrReducer ; + + + + + + +ARCHITECTURE rtl OF bramAddrReducer IS +BEGIN + -- +2 to srr(2) the address (as it makes +4) + addrOut <= std_ulogic_vector(addrIn(addrOut'high+2 downto addrOut'low+2)); +END ARCHITECTURE rtl; + + + + +-- +-- VHDL Architecture HEIRV32.instructionDataMemory.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:38:02 24.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +LIBRARY HEIRV32; +LIBRARY Memory; + +ARCHITECTURE struct OF instructionDataMemory IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL out1 : std_ulogic_vector(g_addrWidth-1 DOWNTO 0); + + + -- Component Declarations + COMPONENT bramAddrReducer + GENERIC ( + g_dataWidth : positive := 32; + g_addrWidth : positive := 10 + ); + PORT ( + addrIn : IN unsigned (g_dataWidth-1 DOWNTO 0); + addrOut : OUT std_ulogic_vector (g_addrWidth-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT bram + GENERIC ( + addressBitNb : positive := 8; + dataBitNb : positive := 8; + initFile : string := "bramInit.txt" + ); + PORT ( + clock : IN std_ulogic ; + en : IN std_ulogic ; + writeEn : IN std_ulogic ; + addressIn : IN std_ulogic_vector (addressBitNb-1 DOWNTO 0); + dataIn : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0); + dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : bram USE ENTITY Memory.bram; + FOR ALL : bramAddrReducer USE ENTITY HEIRV32.bramAddrReducer; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + U_bramAddrReducer : bramAddrReducer + GENERIC MAP ( + g_dataWidth => g_dataWidth, + g_addrWidth => g_addrWidth + ) + PORT MAP ( + addrIn => address, + addrOut => out1 + ); + U_bram : bram + GENERIC MAP ( + addressBitNb => g_addrWidth, + dataBitNb => g_dataWidth, + initFile => g_programFile + ) + PORT MAP ( + clock => clk, + en => en, + writeEn => writeEnable, + addressIn => out1, + dataIn => writeData, + dataOut => readData + ); + +END struct; + + + + +-- VHDL Entity HEIRV32.instructionForwarder.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE2332101) +-- at - 16:10:50 18.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY instructionForwarder IS + GENERIC( + g_dataWidth : positive := 32 + ); + PORT( + irWrite : IN std_ulogic; + readData : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + instruction : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + +-- Declarations + +END instructionForwarder ; + + + + + + +ARCHITECTURE rtl OF instructionForwarder IS + signal lvec_irMem : std_ulogic_vector(readData'range); +BEGIN + +-- forwardIR : process(rst, clk) +-- begin +-- if rst = '1' then +-- lvec_irMem <= (others => '0'); +-- elsif rising_edge(clk) then +-- if en = '1' and IRWrite = '1' then +-- lvec_irMem <= readData; +-- end if; +-- end if; +-- end process forwardIR; + + forwardIR : process(readData, irWrite) + begin + if irWrite = '1' then + lvec_irMem <= readData; + end if; + end process forwardIR; + + instruction <= lvec_irMem; + +END ARCHITECTURE rtl; + + + + +-- VHDL Entity HEIRV32.bufferUnsignedEnable.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 13:59:57 27.09.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY bufferUnsignedEnable IS + GENERIC( + g_bitNb : positive := 32 + ); + PORT( + clk : IN std_ulogic; + en : IN std_ulogic; + in1 : IN unsigned (g_bitNb - 1 DOWNTO 0); + rst : IN std_ulogic; + out1 : OUT unsigned (g_bitNb - 1 DOWNTO 0) + ); + +-- Declarations + +END bufferUnsignedEnable ; + + + + + + +ARCHITECTURE rtl OF bufferUnsignedEnable IS +BEGIN + + buffering:process(rst, CLK) + begin + if rst = '1' then + out1 <= (others=>'0'); + elsif rising_edge(CLK) then + if EN = '1' then + out1 <= in1; + end if; + end if; + end process buffering; + +END ARCHITECTURE rtl; + + + + +-- VHDL Entity gates.mux2to1Unsigned.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 14:35:12 11.09.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; + USE gates.gates.all; + +ENTITY mux2to1Unsigned IS + GENERIC( + dataBitNb : positive := 8; + delay : time := gateDelay + ); + PORT( + in0 : IN unsigned (dataBitNb-1 DOWNTO 0); + in1 : IN unsigned (dataBitNb-1 DOWNTO 0); + sel : IN std_uLogic; + muxOut : OUT unsigned (dataBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END mux2to1Unsigned ; + + + + + +ARCHITECTURE sim OF mux2to1Unsigned IS + + signal selInt: std_ulogic; + +BEGIN + + selInt <= to_X01(sel); + + muxSelect: process(selInt, in0, in1) + begin + if selInt = '0' then + muxOut <= in0 after delay; + elsif selInt = '1' then + muxOut <= in1 after delay; + elsif in0 = in1 then + muxOut <= in0 after delay; + else + muxOut <= (others => 'X') after delay; + end if; + end process muxSelect; + +END ARCHITECTURE sim; + + + + +-- VHDL Entity HEIRV32.registerFile.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 10:23:24 21.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY registerFile IS + GENERIC( + g_dataWidth : positive := 32; + g_btnsNb : positive := 2 + ); + PORT( + addr1 : IN std_ulogic_vector (4 DOWNTO 0); + addr2 : IN std_ulogic_vector (4 DOWNTO 0); + addr3 : IN std_ulogic_vector (4 DOWNTO 0); + btns : IN std_ulogic_vector (g_btnsNb-1 DOWNTO 0); + clk : IN std_ulogic; + en : IN std_ulogic; + rst : IN std_ulogic; + writeData : IN std_ulogic_vector (g_dataWidth - 1 DOWNTO 0); + writeEnable3 : IN std_ulogic; + RD1 : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + RD2 : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + leds : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + +-- Declarations + +END registerFile ; + + + + + + +ARCHITECTURE rtl OF registerFile IS + -- Bank of register + type t_registersBank is array (31 downto 0) of + std_ulogic_vector(31 downto 0); + -- A bank of registers + signal larr_registers: t_registersBank; +BEGIN + + -- Clocked write + process(rst, clk) begin + if rst = '1' then + larr_registers <= (others => (others => '0')); + elsif rising_edge(clk) then + if writeEnable3 = '1' and en = '1' then + larr_registers(to_integer(unsigned(addr3))) <= writeData; + end if; + end if; + end process; + + -- Comb. read + -- Addr 0 wired to 0s + process(addr1, addr2) begin + if (to_integer(unsigned(addr1)) = 0) then + RD1 <= (others => '0'); + elsif (to_integer(unsigned(addr1)) = 31) then -- buttons + RD1 <= (btns'length to g_datawidth-1 => '0') & btns; + else + RD1 <= larr_registers(to_integer(unsigned(addr1))); + end if; + + if (to_integer(unsigned(addr2)) = 0) then + RD2 <= (others => '0'); + elsif (to_integer(unsigned(addr2)) = 31) then -- buttons + RD2 <= (btns'length to g_datawidth-1 => '0') & btns; + else + RD2 <= larr_registers(to_integer(unsigned(addr2))); + end if; + end process; + + leds <= larr_registers(30); + +END ARCHITECTURE rtl; + + + + +-- VHDL Entity HEIRV32.mux4To1ULogVec.symbol +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 15:23:48 11.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +ENTITY mux4To1ULogVec IS + GENERIC( + g_dataWidth : positive := 32 + ); + PORT( + in1 : IN std_ulogic_vector (g_dataWidth - 1 DOWNTO 0); + in2 : IN std_ulogic_vector (g_dataWidth - 1 DOWNTO 0); + in3 : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + in4 : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + sel : IN std_ulogic_vector (1 DOWNTO 0); + out1 : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + +-- Declarations + +END mux4To1ULogVec ; + + + + + + +ARCHITECTURE rtl OF mux4To1ULogVec IS +BEGIN + + muxSelect: process(sel, in1, in2, in3, in4) + begin + case to_integer(unsigned(sel)) is + when 0 => out1 <= in1; + when 1 => out1 <= in2; + when 2 => out1 <= in3; + when 3 => out1 <= in4; + when others => out1 <= (others => 'X'); + end case; + end process muxSelect; + +END ARCHITECTURE rtl; + + + + +-- VHDL Entity gates.transUlogUnsigned.symbol +-- +-- Created: +-- by - silvan.zahno.UNKNOWN (WE6996) +-- at - 14:35:05 11.09.2019 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; + USE gates.gates.all; + +ENTITY transUlogUnsigned IS + GENERIC( + delay : time := gateDelay; + dataBitNb : positive := 8 + ); + PORT( + in1 : IN std_uLogic_vector (dataBitNb-1 DOWNTO 0); + out1 : OUT unsigned (dataBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END transUlogUnsigned ; + + + + + +ARCHITECTURE sim OF transUlogUnsigned IS +BEGIN + out1 <= unsigned(in1) after delay; +END ARCHITECTURE sim; + + + + +-- +-- VHDL Architecture HEIRV32.heirv32.struct +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 17:45:34 24.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; +LIBRARY gates; +USE gates.gates.all; + +LIBRARY HEIRV32; + +ARCHITECTURE struct OF heirv32 IS + + -- Architecture declarations + constant c_dataWidth : positive := g_dataWidth; + constant c_bramAddrWidth : positive := 10; + + -- Internal signal declarations + SIGNAL ALUControl : std_ulogic_vector(2 DOWNTO 0); + SIGNAL ALUOut : std_ulogic_vector(c_dataWidth - 1 DOWNTO 0); + SIGNAL ALUResult : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL ALUSrcA : std_ulogic_vector(1 DOWNTO 0); + SIGNAL ALUSrcB : std_ulogic_vector(1 DOWNTO 0); + SIGNAL IRWrite : std_ulogic; + SIGNAL PC : unsigned(c_dataWidth - 1 DOWNTO 0); + SIGNAL PCNext : unsigned(c_dataWidth - 1 DOWNTO 0); + SIGNAL PCWrite : std_ulogic; + SIGNAL PCu : std_ulogic_vector(c_dataWidth - 1 DOWNTO 0); + SIGNAL RD1 : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL adr : unsigned(c_dataWidth-1 DOWNTO 0); + SIGNAL adrSrc : std_uLogic; + SIGNAL data : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL en1 : std_uLogic; + SIGNAL four_four : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL four_zeros : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL immExt : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL immSrc : std_ulogic_vector(1 DOWNTO 0); + SIGNAL instruction : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL memWrite : std_ulogic; + SIGNAL oldPC : std_ulogic_vector(c_dataWidth - 1 DOWNTO 0); + SIGNAL out1 : std_uLogic; + SIGNAL regwrite : std_ulogic; + SIGNAL result : std_uLogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL resultSrc : std_ulogic_vector(1 DOWNTO 0); + SIGNAL srcA : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL srcB : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL writeData : std_ulogic_vector(c_dataWidth-1 DOWNTO 0); + SIGNAL zero : std_ulogic; + + + -- Component Declarations + COMPONENT and2 + GENERIC ( + delay : time := gateDelay + ); + PORT ( + in1 : IN std_uLogic ; + in2 : IN std_uLogic ; + out1 : OUT std_uLogic + ); + END COMPONENT; + COMPONENT mux2to1Unsigned + GENERIC ( + dataBitNb : positive := 8; + delay : time := gateDelay + ); + PORT ( + in0 : IN unsigned (dataBitNb-1 DOWNTO 0); + in1 : IN unsigned (dataBitNb-1 DOWNTO 0); + sel : IN std_uLogic ; + muxOut : OUT unsigned (dataBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT transUlogUnsigned + GENERIC ( + delay : time := gateDelay; + dataBitNb : positive := 8 + ); + PORT ( + in1 : IN std_uLogic_vector (dataBitNb-1 DOWNTO 0); + out1 : OUT unsigned (dataBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT transUnsignedUlog + GENERIC ( + delay : time := gateDelay; + dataBitNb : positive := 8 + ); + PORT ( + in1 : IN unsigned (dataBitNb-1 DOWNTO 0); + out1 : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT ALU + GENERIC ( + g_datawidth : positive := 32 + ); + PORT ( + ctrl : IN std_ulogic_vector (2 DOWNTO 0); + srcA : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + srcB : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + res : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + zero : OUT std_ulogic + ); + END COMPONENT; + COMPONENT bufferStdULogEnable + GENERIC ( + g_dataWidth : positive := 32 + ); + PORT ( + clk : IN std_ulogic ; + en : IN std_uLogic ; + in1 : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + rst : IN std_ulogic ; + out1 : OUT std_ulogic_vector (g_dataWidth - 1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT bufferUnsignedEnable + GENERIC ( + g_bitNb : positive := 32 + ); + PORT ( + clk : IN std_ulogic ; + en : IN std_ulogic ; + in1 : IN unsigned (g_bitNb - 1 DOWNTO 0); + rst : IN std_ulogic ; + out1 : OUT unsigned (g_bitNb - 1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT controlUnit + GENERIC ( + g_datawidth : positive := 32 + ); + PORT ( + clk : IN std_ulogic ; + en : IN std_ulogic ; + funct3 : IN std_ulogic_vector (2 DOWNTO 0); + funct7 : IN std_ulogic ; + op : IN std_ulogic_vector (6 DOWNTO 0); + rst : IN std_ulogic ; + zero : IN std_ulogic ; + ALUControl : OUT std_ulogic_vector (2 DOWNTO 0); + ALUSrcA : OUT std_ulogic_vector (1 DOWNTO 0); + ALUSrcB : OUT std_ulogic_vector (1 DOWNTO 0); + IRWrite : OUT std_ulogic ; + PCWrite : OUT std_ulogic ; + adrSrc : OUT std_uLogic ; + immSrc : OUT std_ulogic_vector (1 DOWNTO 0); + memWrite : OUT std_ulogic ; + regwrite : OUT std_ulogic ; + resultSrc : OUT std_ulogic_vector (1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT extend + GENERIC ( + g_dataWidth : positive := 32 + ); + PORT ( + input : IN std_ulogic_vector (31 DOWNTO 7); + src : IN std_ulogic_vector (1 DOWNTO 0); + extended : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT instructionDataMemory + GENERIC ( + g_dataWidth : positive := 32; + g_addrWidth : positive := 10; + g_programFile : string := "" + ); + PORT ( + address : IN unsigned (g_dataWidth-1 DOWNTO 0); + clk : IN std_ulogic ; + en : IN std_ulogic ; + writeData : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + writeEnable : IN std_ulogic ; + readData : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT instructionForwarder + GENERIC ( + g_dataWidth : positive := 32 + ); + PORT ( + irWrite : IN std_ulogic ; + readData : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + instruction : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT mux4To1ULogVec + GENERIC ( + g_dataWidth : positive := 32 + ); + PORT ( + in1 : IN std_ulogic_vector (g_dataWidth - 1 DOWNTO 0); + in2 : IN std_ulogic_vector (g_dataWidth - 1 DOWNTO 0); + in3 : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + in4 : IN std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + sel : IN std_ulogic_vector (1 DOWNTO 0); + out1 : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT registerFile + GENERIC ( + g_dataWidth : positive := 32; + g_btnsNb : positive := 2 + ); + PORT ( + addr1 : IN std_ulogic_vector (4 DOWNTO 0); + addr2 : IN std_ulogic_vector (4 DOWNTO 0); + addr3 : IN std_ulogic_vector (4 DOWNTO 0); + btns : IN std_ulogic_vector (g_btnsNb-1 DOWNTO 0); + clk : IN std_ulogic ; + en : IN std_ulogic ; + rst : IN std_ulogic ; + writeData : IN std_ulogic_vector (g_dataWidth - 1 DOWNTO 0); + writeEnable3 : IN std_ulogic ; + RD1 : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + RD2 : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0); + leds : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ALU USE ENTITY HEIRV32.ALU; + FOR ALL : and2 USE ENTITY gates.and2; + FOR ALL : bufferStdULogEnable USE ENTITY HEIRV32.bufferStdULogEnable; + FOR ALL : bufferUnsignedEnable USE ENTITY HEIRV32.bufferUnsignedEnable; + FOR ALL : controlUnit USE ENTITY HEIRV32.controlUnit; + FOR ALL : extend USE ENTITY HEIRV32.extend; + FOR ALL : instructionDataMemory USE ENTITY HEIRV32.instructionDataMemory; + FOR ALL : instructionForwarder USE ENTITY HEIRV32.instructionForwarder; + FOR ALL : mux2to1Unsigned USE ENTITY gates.mux2to1Unsigned; + FOR ALL : mux4To1ULogVec USE ENTITY HEIRV32.mux4To1ULogVec; + FOR ALL : registerFile USE ENTITY HEIRV32.registerFile; + FOR ALL : transUlogUnsigned USE ENTITY gates.transUlogUnsigned; + FOR ALL : transUnsignedUlog USE ENTITY gates.transUnsignedUlog; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + four_zeros <= (c_dataWidth - 1 downto 0 => '0'); + four_four <= std_ulogic_vector(to_unsigned(4, c_dataWidth)); + + -- HDL Embedded Text Block 2 eb2 + + + dbg_leds(7 downto 0) <= std_ulogic_vector(adr(9 downto 2)); -- no need to read LSBs since does +4 each time + + dbg_leds(15 downto 8) <= std_ulogic_vector(instruction(7 downto 0)); + + dbg_leds(23 downto 16) <= std_ulogic_vector(ALUControl & "000" & resultSrc); + + dbg_leds(31 downto 24) <= std_ulogic_vector(regwrite & immSrc & '0' & ALUSrcB & ALUSrcA); + + + -- Instance port mappings. + U_and1 : and2 + GENERIC MAP ( + delay => gateDelay + ) + PORT MAP ( + in1 => en, + in2 => PCWrite, + out1 => out1 + ); + U_and2 : and2 + GENERIC MAP ( + delay => gateDelay + ) + PORT MAP ( + in1 => en, + in2 => IRWrite, + out1 => en1 + ); + U_pcMux : mux2to1Unsigned + GENERIC MAP ( + dataBitNb => c_dataWidth, + delay => gateDelay + ) + PORT MAP ( + in0 => PC, + in1 => PCNext, + sel => adrSrc, + muxOut => adr + ); + U_resultToUnsigned : transUlogUnsigned + GENERIC MAP ( + delay => gateDelay, + dataBitNb => c_dataWidth + ) + PORT MAP ( + in1 => result, + out1 => PCNext + ); + U_0 : transUnsignedUlog + GENERIC MAP ( + delay => gateDelay, + dataBitNb => c_dataWidth + ) + PORT MAP ( + in1 => PC, + out1 => PCu + ); + U_alu : ALU + GENERIC MAP ( + g_datawidth => c_dataWidth + ) + PORT MAP ( + ctrl => ALUControl, + srcA => srcA, + srcB => srcB, + res => ALUResult, + zero => zero + ); + U_aluBuffer : bufferStdULogEnable + GENERIC MAP ( + g_dataWidth => c_dataWidth + ) + PORT MAP ( + clk => clk, + en => en, + in1 => ALUResult, + rst => rst, + out1 => ALUOut + ); + U_pcBuffer : bufferStdULogEnable + GENERIC MAP ( + g_dataWidth => c_dataWidth + ) + PORT MAP ( + clk => clk, + en => en1, + in1 => PCu, + rst => rst, + out1 => oldPC + ); + U_pcLoadBuffer : bufferUnsignedEnable + GENERIC MAP ( + g_bitNb => c_dataWidth + ) + PORT MAP ( + clk => clk, + en => out1, + in1 => PCNext, + rst => rst, + out1 => PC + ); + U_controlUnit : controlUnit + GENERIC MAP ( + g_datawidth => c_dataWidth + ) + PORT MAP ( + clk => clk, + en => en, + funct3 => instruction(14 DOWNTO 12), + funct7 => instruction(30), + op => instruction(6 DOWNTO 0), + rst => rst, + zero => zero, + ALUControl => ALUControl, + ALUSrcA => ALUSrcA, + ALUSrcB => ALUSrcB, + IRWrite => IRWrite, + PCWrite => PCWrite, + adrSrc => adrSrc, + immSrc => immSrc, + memWrite => memWrite, + regwrite => regwrite, + resultSrc => resultSrc + ); + U_extend : extend + GENERIC MAP ( + g_dataWidth => c_dataWidth + ) + PORT MAP ( + input => instruction(31 DOWNTO 7), + src => immSrc, + extended => immExt + ); + U_instrDataMemory : instructionDataMemory + GENERIC MAP ( + g_dataWidth => c_dataWidth, + g_addrWidth => c_bramAddrWidth, + g_programFile => g_programFile + ) + PORT MAP ( + address => adr, + clk => clk, + en => en, + writeData => writeData, + writeEnable => memWrite, + readData => data + ); + U_instrForward : instructionForwarder + GENERIC MAP ( + g_dataWidth => c_dataWidth + ) + PORT MAP ( + irWrite => IRWrite, + readData => data, + instruction => instruction + ); + U_resultSel : mux4To1ULogVec + GENERIC MAP ( + g_dataWidth => c_dataWidth + ) + PORT MAP ( + in1 => ALUOut, + in2 => data, + in3 => ALUResult, + in4 => four_zeros, + sel => resultSrc, + out1 => result + ); + U_srcASel : mux4To1ULogVec + GENERIC MAP ( + g_dataWidth => c_dataWidth + ) + PORT MAP ( + in1 => PCu, + in2 => oldPC, + in3 => RD1, + in4 => four_zeros, + sel => ALUSrcA, + out1 => srcA + ); + U_srcBSel : mux4To1ULogVec + GENERIC MAP ( + g_dataWidth => c_dataWidth + ) + PORT MAP ( + in1 => writeData, + in2 => immExt, + in3 => four_four, + in4 => four_zeros, + sel => ALUSrcB, + out1 => srcB + ); + U_registerFile : registerFile + GENERIC MAP ( + g_dataWidth => c_dataWidth, + g_btnsNb => g_btnsNb + ) + PORT MAP ( + addr1 => instruction(19 DOWNTO 15), + addr2 => instruction(24 DOWNTO 20), + addr3 => instruction(11 DOWNTO 7), + btns => btns, + clk => clk, + en => en, + rst => rst, + writeData => result, + writeEnable3 => regwrite, + RD1 => RD1, + RD2 => writeData, + leds => leds + ); + +END struct; + + + + +-- +-- VHDL Architecture HEIRV32_test.heirv32_tb.universal +-- +-- Created: +-- by - axel.amand.UNKNOWN (WE7860) +-- at - 16:01:58 24.10.2022 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +LIBRARY HEIRV32; +LIBRARY HEIRV32_test; + +ARCHITECTURE universal OF heirv32_tb IS + + -- Architecture declarations + constant c_btnsNb : positive := 4; + + -- Internal signal declarations + SIGNAL btns : std_ulogic_vector(c_btnsNb-1 DOWNTO 0); + SIGNAL clk : std_ulogic; + SIGNAL en : std_ulogic; + SIGNAL rst : std_ulogic; + + + -- Component Declarations + COMPONENT heirv32 + GENERIC ( + g_programFile : string := "$SIMULATION_DIR/code.txt"; + g_btnsNb : positive := 2; + g_dataWidth : positive := 32 + ); + PORT ( + btns : IN std_ulogic_vector (g_btnsNb-1 DOWNTO 0); + clk : IN std_ulogic ; + en : IN std_ulogic ; + rst : IN std_ulogic ; + dbg_leds : OUT std_ulogic_vector (31 DOWNTO 0); + leds : OUT std_ulogic_vector (g_dataWidth-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT universalTester + GENERIC ( + c_btnsNb : positive := 2 + ); + PORT ( + btns : OUT std_ulogic_vector (c_btnsNb-1 DOWNTO 0); + clk : OUT std_ulogic ; + en : OUT std_ulogic ; + rst : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : heirv32 USE ENTITY HEIRV32.heirv32; + FOR ALL : universalTester USE ENTITY HEIRV32_test.universalTester; + -- pragma synthesis_on + + +BEGIN + + -- Instance port mappings. + U_1 : heirv32 + GENERIC MAP ( + g_programFile => "$SIMULATION_DIR/code_bram.txt", + g_btnsNb => c_btnsNb, + g_dataWidth => 32 + ) + PORT MAP ( + btns => btns, + clk => clk, + en => en, + rst => rst, + dbg_leds => OPEN, + leds => OPEN + ); + U_0 : universalTester + GENERIC MAP ( + c_btnsNb => c_btnsNb + ) + PORT MAP ( + btns => btns, + clk => clk, + en => en, + rst => rst + ); + +END universal; + + + + diff --git a/Libs/RiscV/HEIRV32_test/hdl/heirv32_mc_tester_test.vhd b/Libs/RiscV/HEIRV32_test/hdl/heirv32_mc_tester_test.vhd new file mode 100644 index 0000000..92dc4f8 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hdl/heirv32_mc_tester_test.vhd @@ -0,0 +1,118 @@ +LIBRARY std; + USE std.textio.ALL; + +LIBRARY ieee; + USE ieee.std_logic_textio.ALL; + +LIBRARY Common_test; + USE Common_test.testutils.all; + +ARCHITECTURE test OF heirv32_mc_tester IS + + constant clockPeriod : time := 1.0/66E6 * 1 sec; + signal sClock : std_uLogic := '1'; + signal sReset : std_uLogic ; + + signal testInfo : string(1 to 40) := (others => ' '); + +BEGIN + + ------------------------------------------------------------------------------ + -- reset and clock + sReset <= '1', '0' after 3.5*clockPeriod; + rst <= sReset; + + sClock <= not sClock after clockPeriod/2; + clk <= transport sClock after 0.9*clockPeriod; + + btns <= (others => '0'); + + process + -- Wait list + -- 3 clk for beq + -- 4 clk for others + -- 5 clk for lw + begin + en <= '0'; + + testInfo <= pad("Wait reset", testInfo'length); + wait until rst = '0'; + + while true loop + en <= '1'; + + testInfo <= pad("Addi, addr. 00", testInfo'length); + wait until clk'event and clk = '1'; + wait for 3*clockPeriod; + + testInfo <= pad("Addi, addr. 04", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Addi, addr. 08", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Or, addr. 0C", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("And, addr. 10", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Add, addr. 14", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Beq, addr. 18", testInfo'length); + wait for 3*clockPeriod; + + testInfo <= pad("Slt, addr. 1C", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Beq, addr. 20", testInfo'length); + wait for 3*clockPeriod; + + --testInfo <= pad("Addi, addr. 24", testInfo'length); + --wait for 4*clockPeriod; + + testInfo <= pad("Slt, addr. 28", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Add, addr. 2C", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Sub, addr. 30", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Sw, addr. 34", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Lw, addr. 38", testInfo'length); + wait for 5*clockPeriod; + + testInfo <= pad("Add, addr. 3C", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Jal, addr. 40", testInfo'length); + wait for 4*clockPeriod; + + --testInfo <= pad("Addi, addr. 44", testInfo'length); + --wait for 4*clockPeriod; + + testInfo <= pad("Add, addr. 48", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Sw, addr.4C", testInfo'length); + wait for 4*clockPeriod; + + testInfo <= pad("Beq, addr. 50", testInfo'length); + wait for 2.8*clockPeriod; + + en <= '0'; + testInfo <= pad("Wait a bit, program should restart", testInfo'length); + wait for 9.2*clockPeriod; + testInfo <= pad("PC should go to 0 on clock", testInfo'length); + en <= '1'; + wait until clk'event and clk = '1'; + + end loop; + end process; + +END ARCHITECTURE test; diff --git a/Libs/RiscV/HEIRV32_test/hdl/heirv32_sc_tester_rtl.vhd b/Libs/RiscV/HEIRV32_test/hdl/heirv32_sc_tester_rtl.vhd new file mode 100644 index 0000000..1404d6b --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hdl/heirv32_sc_tester_rtl.vhd @@ -0,0 +1,116 @@ +LIBRARY std; + USE std.textio.ALL; + +LIBRARY ieee; + USE ieee.std_logic_textio.ALL; + +LIBRARY Common_test; + USE Common_test.testutils.all; + +ARCHITECTURE rtl OF heirv32_sc_tester IS + + constant clockPeriod : time := 1.0/66E6 * 1 sec; + signal sClock : std_uLogic := '1'; + signal sReset : std_uLogic ; + + signal testInfo : string(1 to 40) := (others => ' '); + +BEGIN + + ------------------------------------------------------------------------------ + -- reset and clock + sReset <= '1', '0' after 3.5*clockPeriod; + rst <= sReset; + + sClock <= not sClock after clockPeriod/2; + clk <= transport sClock after 0.9*clockPeriod; + + btns <= (others => '0'); + + process + -- Wait list + -- 1 for all + begin + en <= '0'; + + testInfo <= pad("Wait reset", testInfo'length); + wait until rst = '0'; + + while true loop + en <= '1'; + + testInfo <= pad("Addi, addr. 00", testInfo'length); + wait until clk'event and clk = '1'; + wait for clockPeriod; + + testInfo <= pad("Addi, addr. 04", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Addi, addr. 08", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Or, addr. 0C", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("And, addr. 10", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Add, addr. 14", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Beq, addr. 18", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Slt, addr. 1C", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Beq, addr. 20", testInfo'length); + wait for clockPeriod; + + --testInfo <= pad("Addi, addr. 24", testInfo'length); + --wait for clockPeriod; + + testInfo <= pad("Slt, addr. 28", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Add, addr. 2C", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Sub, addr. 30", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Sw, addr. 34", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Lw, addr. 38", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Add, addr. 3C", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Jal, addr. 40", testInfo'length); + wait for clockPeriod; + + --testInfo <= pad("Addi, addr. 44", testInfo'length); + --wait for clockPeriod; + + testInfo <= pad("Add, addr. 48", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Sw, addr.4C", testInfo'length); + wait for clockPeriod; + + testInfo <= pad("Beq, addr. 50", testInfo'length); + wait for 0.8*clockPeriod; + + en <= '0'; + testInfo <= pad("Wait a bit, PC should be 0", testInfo'length); + wait for 9.2*clockPeriod; + testInfo <= pad("Enabling system", testInfo'length); + en <= '1'; + wait until clk'event and clk = '1'; + + end loop; + end process; + +END ARCHITECTURE rtl; diff --git a/Libs/RiscV/HEIRV32_test/hdl/universalTester_test.vhd b/Libs/RiscV/HEIRV32_test/hdl/universalTester_test.vhd new file mode 100644 index 0000000..a651c16 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hdl/universalTester_test.vhd @@ -0,0 +1,51 @@ +LIBRARY std; + USE std.textio.ALL; + +LIBRARY ieee; + USE ieee.std_logic_textio.ALL; + +LIBRARY Common_test; + USE Common_test.testutils.all; + +ARCHITECTURE test OF universalTester IS + + constant clockPeriod : time := 1.0/66E6 * 1 sec; + signal sClock : std_uLogic := '1'; + signal sReset : std_uLogic ; + + signal testInfo : string(1 to 40) := (others => ' '); + +BEGIN + + ------------------------------------------------------------------------------ + -- reset and clock + sReset <= '1', '0' after 3.5*clockPeriod; + rst <= sReset; + + sClock <= not sClock after clockPeriod/2; + clk <= transport sClock after 0.9*clockPeriod; + + btns <= (others => '1'), (others=>'0') after 4.15 us; + + process + -- Wait list + -- 3 clk for beq + -- 4 clk for others + -- 5 clk for lw + begin + en <= '0'; + + testInfo <= pad("Wait reset", testInfo'length); + wait until rst = '0'; + + while true loop + en <= '1'; + + testInfo <= pad("Running", testInfo'length); + wait; + + end loop; + end process; + +END ARCHITECTURE test; + diff --git a/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_mc_tester_test.vhd._fpf b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_mc_tester_test.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_mc_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_rtl.vhd._fpf b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_rtl.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_rtl.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_test.vhd._fpf b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_test.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_test.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tb_universal.vhg._fpf b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tb_universal.vhg._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tb_universal.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tester_test.vhd._fpf b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tester_test.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tester_test.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_universalTester_test.vhd._fpf b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_universalTester_test.vhd._fpf new file mode 100644 index 0000000..0df95a8 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_universalTester_test.vhd._fpf @@ -0,0 +1,4 @@ +DIALECT atom VHDL_2008 +INCLUDE list { + DEFAULT atom 1 +} diff --git a/Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tb._epf b/Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tb._epf new file mode 100644 index 0000000..aa9a45f --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_FILE atom heirv32_mc_tb/struct.bd +DEFAULT_ARCHITECTURE atom struct +TOP_MARKER atom 1 diff --git a/Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tester._epf b/Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tester._epf new file mode 100644 index 0000000..3d43654 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom heirv32_mc_tester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tb._epf b/Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tb._epf new file mode 100644 index 0000000..e9fa4c5 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tb._epf @@ -0,0 +1,3 @@ +DEFAULT_ARCHITECTURE atom struct +DEFAULT_FILE atom heirv32_sc_tb/struct.bd +TOP_MARKER atom 1 diff --git a/Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tester._epf b/Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tester._epf new file mode 100644 index 0000000..3e6ffce --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tester._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom rtl +DEFAULT_FILE atom heirv32_sc_tester_rtl.vhd diff --git a/Libs/RiscV/HEIRV32_test/hds/_universaltester._epf b/Libs/RiscV/HEIRV32_test/hds/_universaltester._epf new file mode 100644 index 0000000..943475d --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/_universaltester._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom universalTester_test.vhd +DEFAULT_ARCHITECTURE atom test diff --git a/Libs/RiscV/HEIRV32_test/hds/heirv32_mc_tb/struct.bd b/Libs/RiscV/HEIRV32_test/hds/heirv32_mc_tb/struct.bd new file mode 100644 index 0000000..0682904 --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/heirv32_mc_tb/struct.bd @@ -0,0 +1,2807 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef 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96,0 +vaOverrides [ +] +) +] +) +uid 82,0 +type 1 +) +activeModelName "BlockDiag" +) diff --git a/Libs/RiscV/HEIRV32_test/hds/heirv32_mc_tb/symbol.sb b/Libs/RiscV/HEIRV32_test/hds/heirv32_mc_tb/symbol.sb new file mode 100644 index 0000000..bba87aa --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/heirv32_mc_tb/symbol.sb @@ -0,0 +1,1215 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +usingSuid 1 +emptyRow *1 (LEmptyRow +) +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm 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"44000,6800,44000,6800" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 433,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/RiscV/HEIRV32_test/hds/heirv32_sc_tb/struct.bd b/Libs/RiscV/HEIRV32_test/hds/heirv32_sc_tb/struct.bd new file mode 100644 index 0000000..6403e6d --- /dev/null +++ b/Libs/RiscV/HEIRV32_test/hds/heirv32_sc_tb/struct.bd @@ -0,0 +1,2820 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +instances [ +(Instance +name "U_tester" +duLibraryName "HEIRV32_test" +duName "heirv32_sc_tester" +elements [ +(GiElement +name "c_btnsNb" +type "positive" +value "c_btnsNb" +) +] +mwi 0 +uid 143,0 +) +(Instance +name "U_heirv32" +duLibraryName "HEIRV32_SC" +duName "heirv32_sc" +elements [ +(GiElement +name "g_programFile" +type "string" +value "\"$SIMULATION_DIR/code_sim_bram.txt\"" +) +(GiElement +name "g_btnsNb" +type "positive" +value "c_btnsNb" +) +(GiElement +name "g_dataWidth" +type "positive" +value "32" +) +(GiElement +name "g_memoryNbBits" +type "positive" +value "7" +) +] +mwi 0 +uid 248,0 +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds\\heirv32_sc_tb\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds\\heirv32_sc_tb\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "concatenated" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds\\heirv32_sc_tb" +) +(vvPair +variable "d_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds\\heirv32_sc_tb" +) +(vvPair +variable "date" +value "04.11.2022" +) +(vvPair +variable "day" +value "ven." +) +(vvPair +variable "day_long" +value "vendredi" +) +(vvPair +variable "dd" +value "04" +) +(vvPair +variable "entity_name" +value "heirv32_sc_tb" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "axel.amand" +) +(vvPair +variable "graphical_source_date" +value "04.11.2022" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE7860" +) +(vvPair +variable "graphical_source_time" +value "11:37:15" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE7860" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "HEIRV32_test" +) +(vvPair +variable "library_downstream_Concatenation" +value "$HDS_PROJECT_DIR/../RiscV/HEIRV32_test/concat" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/CAr//RiscV_test/HEIRV32_test/work" +) +(vvPair +variable "mm" +value "11" +) +(vvPair +variable "module_name" +value "heirv32_sc_tb" +) +(vvPair +variable "month" +value "nov." +) +(vvPair +variable "month_long" +value "novembre" +) +(vvPair +variable "p" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds\\heirv32_sc_tb\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32_test\\hds\\heirv32_sc_tb\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "11:37:15" +) +(vvPair +variable "unit" +value "heirv32_sc_tb" +) +(vvPair +variable "user" +value "axel.amand" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2022" +) +(vvPair +variable "yy" +value "22" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 52,0 +optionalChildren [ +*1 (Grouping +uid 9,0 +optionalChildren [ +*2 (CommentText +uid 11,0 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"42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 452,0 +activeModelName "Symbol:GEN" +) diff --git a/Libs/RiscV/NEORV32/LICENSE b/Libs/RiscV/NEORV32/LICENSE new file mode 100644 index 0000000..26fbfed --- /dev/null +++ b/Libs/RiscV/NEORV32/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2021, Stephan Nolting +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/Libs/RiscV/NEORV32/README.md b/Libs/RiscV/NEORV32/README.md new file mode 100644 index 0000000..9b4e82f --- /dev/null +++ b/Libs/RiscV/NEORV32/README.md @@ -0,0 +1,335 @@ +[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32) + +# The NEORV32 RISC-V Processor + +[![datasheet (pdf)](https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://github.com/stnolting/neorv32/releases/tag/nightly) +[![datasheet (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square)](https://stnolting.github.io/neorv32) +[![userguide (pdf)](https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://github.com/stnolting/neorv32/releases/tag/nightly) +[![userguide (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square)](https://stnolting.github.io/neorv32/ug) +[![doxygen](https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&style=flat-square&logo=Doxygen)](https://stnolting.github.io/neorv32/sw/files.html) +[![Gitter](https://img.shields.io/badge/Chat-on%20gitter-4db797.svg?longCache=true&style=flat-square&logo=gitter&logoColor=e8ecef)](https://gitter.im/neorv32/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) + +1. [Overview](#1-Overview) + * [Key Features](#Project-Key-Features) + * [Status](#status) +2. [Processor/SoC Features](#2-NEORV32-Processor-Features) + * [FPGA Implementation Results](#FPGA-Implementation-Results---Processor) +3. [CPU Features](#3-NEORV32-CPU-Features) + * [Available ISA Extensions](#Available-ISA-Extensions) + * [FPGA Implementation Results](#FPGA-Implementation-Results---CPU) + * [Performance](#Performance) +4. [Software Framework & Tooling](#4-Software-Framework-and-Tooling) +5. [**Getting Started**](#5-Getting-Started) :rocket: + + + +## 1. Overview + +![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png) + +The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** that is based on the RISC-V NEORV32 CPU. +The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone +custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. + +Special focus is paid on **execution safety** to provide defined and predictable behavior at any time. +Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions +are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions. + +:thinking: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale). + +:books: For detailed information take a look at the [NEORV32 documentation](https://stnolting.github.io/neorv32/) (online at GitHub-pages). + +:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md). +To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases). + +:package: [Exemplary setups](https://github.com/stnolting/neorv32/tree/master/setups) targeting +various FPGA boards and toolchains to get you started. + +:kite: Supported by upstream [Zephyr OS](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) and FreeRTOS. + +:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a +[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is +not working as expected. Or have a chat on our [gitter channel](https://gitter.im/neorv32/community). +See how to [contribute](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md). + +:rocket: Check out the [quick links below](#5-Getting-Started) or directly jump to the +[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started +setting up your NEORV32 setup! + + +### Project Key Features + +- [x] all-in-one package: [CPU](#3-NEORV32-CPU-Features) plus [SoC](#2-NEORV32-Processor-Features) plus [Software Framework & Tooling](#4-Software-Framework-and-Tooling) +- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc. +- [x] be as small as possible while being as RISC-V-compliant as possible +- [x] from zero to *printf("hello world!");* - completely open source and documented +- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box* + + +### Status + +[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases) +[![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32) +[![Documentation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Documentation/master?longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation) +\ +[![riscv-arch-test](https://img.shields.io/github/workflow/status/stnolting/neorv32/riscv-arch-test/master?longCache=true&style=flat-square&label=riscv-arch-test&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test) +[![Processor](https://img.shields.io/github/workflow/status/stnolting/neorv32/Processor/master?longCache=true&style=flat-square&label=Processor&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor) +[![Implementation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Implementation/master?longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation) +[![Windows](https://img.shields.io/github/workflow/status/stnolting/neorv32/Windows/master?longCache=true&style=flat-square&label=Windows&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows) + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + +## 2. NEORV32 Processor Features + +The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd)) +provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics +to allow a flexible customization according to your needs. Note that all modules listed below are _optional_. + +**Memory** + +* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) / +[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) & +cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache)) +* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface + * allows booting application code via UART or from external SPI flash + +**Timers** + +* machine system timer, 64-bit ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible +* general purpose 32-bit timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr)) +* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt)) + +**Input/Output** + +* standard serial interfaces +([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0), +[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi), +[TWI / I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi)) +* general purpose [GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio) and +[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm) +* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly drive _NeoPixel(TM)_ LEDs + +**SoC Connectivity** + +* 32-bit external bus interface, Wishbone b4 compatible +([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite)) + * [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface + * [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM master interface +* 32-bit stream link interface with up to 8 independent RX and TX links +([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink)) + * AXI4-Stream compatible +* external interrupt controller with up to 32 channels +([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq)) +* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs)) +for tightly-coupled custom co-processor extensions + +**Advanced** + +* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng)) +* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - implementing +the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec) +and compatible with *OpenOCD* and *gdb* +* bus keeper to monitor the CPU's bus transactions ([BUSKEEPER](https://stnolting.github.io/neorv32/#_internal_bus_monitor_buskeeper)) + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + +### FPGA Implementation Results - Processor + +The hardware resources used by a specific processor setup is defined by the implemented CPU extensions, +the configuration of the peripheral modules and some "glue logic". +Section [_FPGA Implementation Results - Processor Modules_](https://stnolting.github.io/neorv32/#_processor_modules) +of the online datasheet shows the resource utilization of each optional processor module to allow an +estimation of the actual setup's hardware requirements. + +The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA +setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different +SoC configurations. The latest utilization reports for those setups can be found in the report of the +[Implementation Workflow](https://github.com/stnolting/neorv32/actions/workflows/Implementation.yml). + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + + +## 3. NEORV32 CPU Features + +The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd)) +implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the +*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf) +and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf). +Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test) +(see [`sim/README`](sim/README.md)). + +The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture. +However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction execution) can work independently to increase performance. +Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine +interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions. +It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal +instruction, breakpoint, environment calls). + +:books: In-depth detailed information regarding the CPU can be found in the +[_Data Sheet: NEORV32 Central Processing Unit_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu). + + +### Available ISA Extensions + +Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according +documentation section). Note that the `X` extension is always enabled. + +**RV32 +[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/ +[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)] +[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)] +[[`B`](https://stnolting.github.io/neorv32/#_b_bit_manipulation_operations)] +[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)] +[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)] +[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)] +[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)] +[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)] +[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)] +[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)] +[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)] +[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)] +[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)] +[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)] +[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]** + +:warning: The `B`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no +upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic libraries_ for these extensions. + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + +### FPGA Implementation Results - CPU + +Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA** +using **Intel Quartus Prime Lite 20.1** ("balanced implementation, Slow 1200mV 0C Model"). + +| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs (9-bit) | f_max | +|:------------------------|:----:|:----:|:----:|:-:|:-------:| +| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz | +| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz | +| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz | + +:information_source: An incremental list of CPU extension's hardware utilization can found in the +[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu). + +:information_source: The CPU and SoC provide advanced options to optimize for performance, area or energy. +See [_User Guide: Application-Specific Processor Configuration_](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) +for more information. + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + +### Performance + +The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute). +The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the +available CPU extensions. + +The following table shows the performance results (scores and average CPI) for _exemplary_ CPU configurations executing +2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) CPU benchmark. + +| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI | +|:------------------------------------------------|:-----:|:----------:|:--------:| +| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** | +| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** | +| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** | + +:information_source: More information regarding the CPU performance can be found in the +[_Data Sheet: CPU Performance_](https://stnolting.github.io/neorv32/#_cpu_performance). + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + + +## 4. Software Framework and Tooling + +* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals +* application compilation based on GNU makefiles +* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt)) +* [SVD file](https://github.com/stnolting/neorv32/tree/master/sw/svd) for advanced debugging and IDE integration +* bootloader with UART interface console +* runtime environment for handling traps +* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life +* doxygen-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html) +* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future: "Verilog-to-Routing") - both, software and hardware can be +developed and debugged with open source tooling +* [continuous integration](https://github.com/stnolting/neorv32/actions) is available for: + * allowing users to see the expected execution/output of the tools + * ensuring specification compliance + * catching regressions + * providing ready-to-use and up-to-date bitstreams and documentation + +:books: Want to know more? Check out [_Data Sheet: Software Framework_](https://stnolting.github.io/neorv32/#_software_framework). + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + + +## 5. Getting Started + +This overview provides some *quick links* to the most important sections of the +[online Data Sheet](https://stnolting.github.io/neorv32) and the +[online User Guide](https://stnolting.github.io/neorv32/ug). + +### :electric_plug: Hardware Overview + +* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why, how come, what for + +* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC + * [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor + * [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options + * [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configuration + * [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available peripheral modules and memories + * [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG + +* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU + * [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not + * [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - hardware execution safety + * [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions + * [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers + * [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions + +### :floppy_disk: Software Overview + +* [Example Programs](https://github.com/stnolting/neorv32/tree/master/sw/example) - test program execution on your setup +* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals + * [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation +* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable +* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader + +### :rocket: User Guide + +* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup) - install and setup RISC-V gcc +* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project +* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework +* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make` +* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables +* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs +* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware +* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system* +* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC + * [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation + +### :copyright: Legal + +[![license](https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square)](https://github.com/stnolting/neorv32/blob/master/LICENSE) +[![DOI](https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg)](https://doi.org/10.5281/zenodo.5018888) + +* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, ... +* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information +* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint + +[[back to top](#The-NEORV32-RISC-V-Processor)] + + + +## Acknowledgements + +**A big shout-out goes to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:** + +[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free! + +Continuous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl). diff --git a/Libs/RiscV/NEORV32/docs/NEORV32.pdf b/Libs/RiscV/NEORV32/docs/NEORV32.pdf new file mode 100644 index 0000000..91f8906 Binary files /dev/null and b/Libs/RiscV/NEORV32/docs/NEORV32.pdf differ diff --git a/Libs/RiscV/NEORV32/docs/NEORV32_UserGuide.pdf b/Libs/RiscV/NEORV32/docs/NEORV32_UserGuide.pdf new file mode 100644 index 0000000..6bc54f3 Binary files /dev/null and b/Libs/RiscV/NEORV32/docs/NEORV32_UserGuide.pdf differ diff --git a/Libs/RiscV/NEORV32/hdl/.gitkeep b/Libs/RiscV/NEORV32/hdl/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/Libs/RiscV/NEORV32/hds/.gitkeep b/Libs/RiscV/NEORV32/hds/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/Libs/RiscV/NEORV32/rtl/README.md b/Libs/RiscV/NEORV32/rtl/README.md new file mode 100644 index 0000000..33e41ac --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/README.md @@ -0,0 +1,34 @@ +## VHDL Source Folders + + +### [`core`](https://github.com/stnolting/neorv32/tree/master/rtl/core) + +This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor. +When creating a new synthesis/simulation project make sure that all `*.vhd` files from this folder are added to a +*new design library* called `neorv32`. + +:warning: The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/master/rtl/core/mem) +contains the _platform-agnostic_ VHDL architectures of the processor-internal memories. +You can _replace_ inclusion of these files by platform-optimized memory architectures. + + +### [`processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates`) + +Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`. +These templates can be instantiated directly within a FPGA-specific board wrapper. + + +### [`system_integration`](https://github.com/stnolting/neorv32/tree/master/rtl/system_integration`) + +Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default +processor top entity from `core`, but feature a different interface type. +For example: an **AXI4-Lite**-compatible bus interface instead of the default Wishbone bus interface +or a top entity with _resolved_ port signal types. + + +### [`test_setups`](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups`) + +Minimal test setups (FPGA- and board-independent) for the processor. See the +[README](https://github.com/stnolting/neorv32/tree/master/rtl/test_setups) +in that folder for more information. Note that these test setups are used in the +[NEORV32 USer Guide](https://stnolting.github.io/neorv32/ug). diff --git a/Libs/RiscV/NEORV32/rtl/core/mem/README.md b/Libs/RiscV/NEORV32/rtl/core/mem/README.md new file mode 100644 index 0000000..588d5b6 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/mem/README.md @@ -0,0 +1,14 @@ +# Processor Memory Source Files + +This folder provides the architecture-only VHDL sources for the processor-internal memories +(instruction memory "IMEM", data memory "DMEM"). Different implementations are available - but +only **one** version of each (IMEM and DMEM) has to be added as actual source files. + +For the first implementation the `*.default.vhd` files should be selected. The HDL style for describing +memories used by these files has proven **platform-independence** across several FPGA architectures and toolchains. + +If synthesis fails to infer actual block RAM resources from these default files, try the legacy `*.cyclone2.vhd` files, which +provide a different HDL style. These files are intended for legacy support of older Intel/Altera Quartus versions (13.0 and older). However, +these files do **not** use platform-specific macros or primitives - so they might also work for other FPGAs and toolchains. + +:warning: Make sure to add the selected files from this folder also to the `neorv32` design library. diff --git a/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_dmem.cyclone2.vhd b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_dmem.cyclone2.vhd new file mode 100644 index 0000000..de18bd7 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_dmem.cyclone2.vhd @@ -0,0 +1,130 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal data memory (DMEM) >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +architecture neorv32_dmem_rtl of neorv32_dmem is + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(DMEM_SIZE); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + signal addr : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0); + signal addr_ff : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0); + + -- -------------------------------------------------------------------------------------------------------------- -- + -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- + -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- -------------------------------------------------------------------------------------------------------------- -- + + -- RAM - not initialized at all -- + signal mem_ram_b0 : mem8_t(0 to DMEM_SIZE/4-1); + signal mem_ram_b1 : mem8_t(0 to DMEM_SIZE/4-1); + signal mem_ram_b2 : mem8_t(0 to DMEM_SIZE/4-1); + signal mem_ram_b3 : mem8_t(0 to DMEM_SIZE/4-1); + + -- read data -- + signal mem_ram_b0_rd, mem_ram_b1_rd, mem_ram_b2_rd, mem_ram_b3_rd : std_ulogic_vector(7 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using CYCLONE-2-optimized HDL style DMEM." severity note; + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) & " bytes)." severity note; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + addr <= addr_i(index_size_f(DMEM_SIZE/4)+1 downto 2); -- word aligned + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + addr_ff <= addr; + if (acc_en = '1') then -- reduce switching activity when not accessed + if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= data_i(07 downto 00); + end if; + if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= data_i(15 downto 08); + end if; + if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= data_i(23 downto 16); + end if; + if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= data_i(31 downto 24); + end if; + end if; + end if; + end process mem_access; + + -- sync(!) read - alternative HDL style -- + mem_ram_b0_rd <= mem_ram_b0(to_integer(unsigned(addr_ff))); + mem_ram_b1_rd <= mem_ram_b1(to_integer(unsigned(addr_ff))); + mem_ram_b2_rd <= mem_ram_b2(to_integer(unsigned(addr_ff))); + mem_ram_b3_rd <= mem_ram_b3(to_integer(unsigned(addr_ff))); + + + -- Bus Feedback --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + bus_feedback: process(clk_i) + begin + if rising_edge(clk_i) then + rden <= acc_en and rden_i; + ack_o <= acc_en and (rden_i or wren_i); + end if; + end process bus_feedback; + + -- pack -- + rdata <= mem_ram_b3_rd & mem_ram_b2_rd & mem_ram_b1_rd & mem_ram_b0_rd; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_dmem_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_dmem.default.vhd b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_dmem.default.vhd new file mode 100644 index 0000000..99b7762 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_dmem.default.vhd @@ -0,0 +1,132 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal data memory (DMEM) >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +architecture neorv32_dmem_rtl of neorv32_dmem is + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(DMEM_SIZE); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + signal addr : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0); + + -- -------------------------------------------------------------------------------------------------------------- -- + -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- + -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- -------------------------------------------------------------------------------------------------------------- -- + + -- RAM - not initialized at all -- + signal mem_ram_b0 : mem8_t(0 to DMEM_SIZE/4-1); + signal mem_ram_b1 : mem8_t(0 to DMEM_SIZE/4-1); + signal mem_ram_b2 : mem8_t(0 to DMEM_SIZE/4-1); + signal mem_ram_b3 : mem8_t(0 to DMEM_SIZE/4-1); + + -- read data -- + signal mem_ram_b0_rd, mem_ram_b1_rd, mem_ram_b2_rd, mem_ram_b3_rd : std_ulogic_vector(7 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic DMEM." severity note; + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) & " bytes)." severity note; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + addr <= addr_i(index_size_f(DMEM_SIZE/4)+1 downto 2); -- word aligned + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- this RAM style should not require "no_rw_check" attributes as the read-after-write behavior + -- is intended to be defined implicitly via the if-WRITE-else-READ construct + if (acc_en = '1') then -- reduce switching activity when not accessed + if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= data_i(07 downto 00); + else + mem_ram_b0_rd <= mem_ram_b0(to_integer(unsigned(addr))); + end if; + if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= data_i(15 downto 08); + else + mem_ram_b1_rd <= mem_ram_b1(to_integer(unsigned(addr))); + end if; + if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= data_i(23 downto 16); + else + mem_ram_b2_rd <= mem_ram_b2(to_integer(unsigned(addr))); + end if; + if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= data_i(31 downto 24); + else + mem_ram_b3_rd <= mem_ram_b3(to_integer(unsigned(addr))); + end if; + end if; + end if; + end process mem_access; + + + -- Bus Feedback --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + bus_feedback: process(clk_i) + begin + if rising_edge(clk_i) then + rden <= acc_en and rden_i; + ack_o <= acc_en and (rden_i or wren_i); + end if; + end process bus_feedback; + + -- pack -- + rdata <= mem_ram_b3_rd & mem_ram_b2_rd & mem_ram_b1_rd & mem_ram_b0_rd; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_dmem_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_imem.cyclone2.vhd b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_imem.cyclone2.vhd new file mode 100644 index 0000000..2200e32 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_imem.cyclone2.vhd @@ -0,0 +1,176 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> # +-- # ********************************************************************************************* # +-- # This memory optionally includes the in-place executable image of the application. See the # +-- # processor's documentary to get more information. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; +use neorv32.neorv32_application_image.all; -- this file is generated by the image generator + +architecture neorv32_imem_rtl of neorv32_imem is + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0); + signal addr_ff : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0); + + -- --------------------------- -- + -- IMEM as pre-initialized ROM -- + -- --------------------------- -- + + -- application (image) size in bytes -- + constant imem_app_size_c : natural := (application_init_image'length)*4; + + -- ROM - initialized with executable code -- + constant mem_rom : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4); + + -- read data -- + signal mem_rom_rd : std_ulogic_vector(31 downto 0); + + -- -------------------------------------------------------------------------------------------------------------- -- + -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- + -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- -------------------------------------------------------------------------------------------------------------- -- + + -- RAM - not initialized at all -- + signal mem_ram_b0 : mem8_t(0 to IMEM_SIZE/4-1); + signal mem_ram_b1 : mem8_t(0 to IMEM_SIZE/4-1); + signal mem_ram_b2 : mem8_t(0 to IMEM_SIZE/4-1); + signal mem_ram_b3 : mem8_t(0 to IMEM_SIZE/4-1); + + -- read data -- + signal mem_b0_rd, mem_b1_rd, mem_b2_rd, mem_b3_rd : std_ulogic_vector(7 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using CYCLONE-2-optimized HDL style IMEM." severity note; + assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) & + " bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note; + -- + assert not (IMEM_AS_IROM = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as blank RAM (" & natural'image(IMEM_SIZE) & + " bytes)." severity note; + -- + assert not ((IMEM_AS_IROM = true) and (imem_app_size_c > IMEM_SIZE)) report "NEORV32 PROCESSOR CONFIG ERROR: Application (image = " & natural'image(imem_app_size_c) & + " bytes) does not fit into processor-internal IMEM (ROM = " & natural'image(IMEM_SIZE) & " bytes)!" severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned + + + -- Implement IMEM as pre-initialized ROM -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_rom: + if (IMEM_AS_IROM = true) generate + mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + if (acc_en = '1') then -- reduce switching activity when not accessed + mem_rom_rd <= mem_rom(to_integer(unsigned(addr))); + end if; + end if; + end process mem_access; + -- read data -- + rdata <= mem_rom_rd; + end generate; + + + -- Implement IMEM as not-initialized RAM -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_ram: + if (IMEM_AS_IROM = false) generate + mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + addr_ff <= addr; + if (acc_en = '1') then -- reduce switching activity when not accessed + if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= data_i(07 downto 00); + end if; + if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= data_i(15 downto 08); + end if; + if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= data_i(23 downto 16); + end if; + if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= data_i(31 downto 24); + end if; + end if; + end if; + end process mem_access; + -- sync(!) read - alternative HDL style -- + mem_b0_rd <= mem_ram_b0(to_integer(unsigned(addr_ff))); + mem_b1_rd <= mem_ram_b1(to_integer(unsigned(addr_ff))); + mem_b2_rd <= mem_ram_b2(to_integer(unsigned(addr_ff))); + mem_b3_rd <= mem_ram_b3(to_integer(unsigned(addr_ff))); + -- pack -- + rdata <= mem_b3_rd & mem_b2_rd & mem_b1_rd & mem_b0_rd; + end generate; + + + -- Bus Feedback --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + bus_feedback: process(clk_i) + begin + if rising_edge(clk_i) then + rden <= acc_en and rden_i; + if (IMEM_AS_IROM = true) then + ack_o <= acc_en and rden_i; + else + ack_o <= acc_en and (rden_i or wren_i); + end if; + end if; + end process bus_feedback; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_imem_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_imem.default.vhd b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_imem.default.vhd new file mode 100644 index 0000000..d0c924d --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/mem/neorv32_imem.default.vhd @@ -0,0 +1,179 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> # +-- # ********************************************************************************************* # +-- # This memory optionally includes the in-place executable image of the application. See the # +-- # processor's documentary to get more information. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; +use neorv32.neorv32_application_image.all; -- this file is generated by the image generator + +architecture neorv32_imem_rtl of neorv32_imem is + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0); + + -- --------------------------- -- + -- IMEM as pre-initialized ROM -- + -- --------------------------- -- + + -- application (image) size in bytes -- + constant imem_app_size_c : natural := (application_init_image'length)*4; + + -- ROM - initialized with executable code -- + constant mem_rom : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4); + + -- read data -- + signal mem_rom_rd : std_ulogic_vector(31 downto 0); + + -- -------------------------------------------------------------------------------------------------------------- -- + -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- + -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- + -- -------------------------------------------------------------------------------------------------------------- -- + + -- RAM - not initialized at all -- + signal mem_ram_b0 : mem8_t(0 to IMEM_SIZE/4-1); + signal mem_ram_b1 : mem8_t(0 to IMEM_SIZE/4-1); + signal mem_ram_b2 : mem8_t(0 to IMEM_SIZE/4-1); + signal mem_ram_b3 : mem8_t(0 to IMEM_SIZE/4-1); + + -- read data -- + signal mem_b0_rd, mem_b1_rd, mem_b2_rd, mem_b3_rd : std_ulogic_vector(7 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic IMEM." severity note; + assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) & + " bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note; + -- + assert not (IMEM_AS_IROM = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as blank RAM (" & natural'image(IMEM_SIZE) & + " bytes)." severity note; + -- + assert not ((IMEM_AS_IROM = true) and (imem_app_size_c > IMEM_SIZE)) report "NEORV32 PROCESSOR CONFIG ERROR: Application (image = " & natural'image(imem_app_size_c) & + " bytes) does not fit into processor-internal IMEM (ROM = " & natural'image(IMEM_SIZE) & " bytes)!" severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned + + + -- Implement IMEM as pre-initialized ROM -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_rom: + if (IMEM_AS_IROM = true) generate + mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + if (acc_en = '1') then -- reduce switching activity when not accessed + mem_rom_rd <= mem_rom(to_integer(unsigned(addr))); + end if; + end if; + end process mem_access; + -- read data -- + rdata <= mem_rom_rd; + end generate; + + + -- Implement IMEM as not-initialized RAM -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_ram: + if (IMEM_AS_IROM = false) generate + mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- this RAM style should not require "no_rw_check" attributes as the read-after-write behavior + -- is intended to be defined implicitly via the if-WRITE-else-READ construct + if (acc_en = '1') then -- reduce switching activity when not accessed + if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0 + mem_ram_b0(to_integer(unsigned(addr))) <= data_i(07 downto 00); + else + mem_b0_rd <= mem_ram_b0(to_integer(unsigned(addr))); + end if; + if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1 + mem_ram_b1(to_integer(unsigned(addr))) <= data_i(15 downto 08); + else + mem_b1_rd <= mem_ram_b1(to_integer(unsigned(addr))); + end if; + if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2 + mem_ram_b2(to_integer(unsigned(addr))) <= data_i(23 downto 16); + else + mem_b2_rd <= mem_ram_b2(to_integer(unsigned(addr))); + end if; + if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3 + mem_ram_b3(to_integer(unsigned(addr))) <= data_i(31 downto 24); + else + mem_b3_rd <= mem_ram_b3(to_integer(unsigned(addr))); + end if; + end if; + end if; + end process mem_access; + -- read data -- + rdata <= mem_b3_rd & mem_b2_rd & mem_b1_rd & mem_b0_rd; + end generate; + + + -- Bus Feedback --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + bus_feedback: process(clk_i) + begin + if rising_edge(clk_i) then + rden <= acc_en and rden_i; + if (IMEM_AS_IROM = true) then + ack_o <= acc_en and rden_i; + else + ack_o <= acc_en and (rden_i or wren_i); + end if; + end if; + end process bus_feedback; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_imem_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_application_image.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_application_image.vhd new file mode 100644 index 0000000..34b35ad --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_application_image.vhd @@ -0,0 +1,883 @@ +-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 +-- Auto-generated memory init file (for APPLICATION) from source file +-- Size: 3468 bytes + +library ieee; +use ieee.std_logic_1164.all; + +library neorv32; +use neorv32.neorv32_package.all; + +package neorv32_application_image is + + constant application_init_image : mem32_t := ( + 00000000 => x"00000037", + 00000001 => x"80002117", + 00000002 => x"ff810113", + 00000003 => x"80000197", + 00000004 => x"7f418193", + 00000005 => x"00000517", + 00000006 => x"12050513", + 00000007 => x"30551073", + 00000008 => x"34151073", + 00000009 => x"30001073", + 00000010 => x"30401073", + 00000011 => x"30601073", + 00000012 => x"ffa00593", + 00000013 => x"32059073", + 00000014 => x"b0001073", + 00000015 => x"b8001073", + 00000016 => x"b0201073", + 00000017 => x"b8201073", + 00000018 => x"00000093", + 00000019 => x"00000213", + 00000020 => x"00000293", + 00000021 => x"00000313", + 00000022 => x"00000393", + 00000023 => x"00000713", + 00000024 => x"00000793", + 00000025 => x"00000813", + 00000026 => x"00000893", + 00000027 => x"00000913", + 00000028 => x"00000993", + 00000029 => x"00000a13", + 00000030 => x"00000a93", + 00000031 => x"00000b13", + 00000032 => x"00000b93", + 00000033 => x"00000c13", + 00000034 => x"00000c93", + 00000035 => x"00000d13", + 00000036 => x"00000d93", + 00000037 => x"00000e13", + 00000038 => x"00000e93", + 00000039 => x"00000f13", + 00000040 => x"00000f93", + 00000041 => x"00000417", + 00000042 => x"d5c40413", + 00000043 => x"00000497", + 00000044 => x"f5448493", + 00000045 => x"00042023", + 00000046 => x"00440413", + 00000047 => x"fe941ce3", + 00000048 => x"80000597", + 00000049 => x"f4058593", + 00000050 => x"87418613", + 00000051 => x"00c5d863", + 00000052 => x"00058023", + 00000053 => x"00158593", + 00000054 => x"ff5ff06f", + 00000055 => x"00001597", + 00000056 => x"cb058593", + 00000057 => x"80000617", + 00000058 => x"f1c60613", + 00000059 => x"80000697", + 00000060 => x"f1468693", + 00000061 => x"00d65c63", + 00000062 => x"00058703", + 00000063 => x"00e60023", + 00000064 => x"00158593", + 00000065 => x"00160613", + 00000066 => x"fedff06f", + 00000067 => x"00000513", + 00000068 => x"00000593", + 00000069 => x"06c000ef", + 00000070 => x"34051073", + 00000071 => x"00000093", + 00000072 => x"00008463", + 00000073 => x"000080e7", + 00000074 => x"30047073", + 00000075 => x"10500073", + 00000076 => x"ffdff06f", + 00000077 => x"ff810113", + 00000078 => x"00812023", + 00000079 => x"00912223", + 00000080 => x"34202473", + 00000081 => x"02044663", + 00000082 => x"34102473", + 00000083 => x"00041483", + 00000084 => x"0034f493", + 00000085 => x"00240413", + 00000086 => x"34141073", + 00000087 => x"00300413", + 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00000754 => x"746c7561", + 00000755 => x"00000000", + 00000756 => x"656c6c49", + 00000757 => x"206c6167", + 00000758 => x"74736e69", + 00000759 => x"74637572", + 00000760 => x"006e6f69", + 00000761 => x"61657242", + 00000762 => x"696f706b", + 00000763 => x"0000746e", + 00000764 => x"64616f4c", + 00000765 => x"64646120", + 00000766 => x"73736572", + 00000767 => x"73696d20", + 00000768 => x"67696c61", + 00000769 => x"0064656e", + 00000770 => x"64616f4c", + 00000771 => x"63636120", + 00000772 => x"20737365", + 00000773 => x"6c756166", + 00000774 => x"00000074", + 00000775 => x"726f7453", + 00000776 => x"64612065", + 00000777 => x"73657264", + 00000778 => x"696d2073", + 00000779 => x"696c6173", + 00000780 => x"64656e67", + 00000781 => x"00000000", + 00000782 => x"726f7453", + 00000783 => x"63612065", + 00000784 => x"73736563", + 00000785 => x"75616620", + 00000786 => x"0000746c", + 00000787 => x"69766e45", + 00000788 => x"6d6e6f72", + 00000789 => x"20746e65", + 00000790 => x"6c6c6163", + 00000791 => x"6f726620", + 00000792 => x"2d55206d", + 00000793 => x"65646f6d", + 00000794 => x"00000000", + 00000795 => x"69766e45", + 00000796 => x"6d6e6f72", + 00000797 => x"20746e65", + 00000798 => x"6c6c6163", + 00000799 => x"6f726620", + 00000800 => x"2d4d206d", + 00000801 => x"65646f6d", + 00000802 => x"00000000", + 00000803 => x"6863614d", + 00000804 => x"20656e69", + 00000805 => x"74666f73", + 00000806 => x"65726177", + 00000807 => x"746e6920", + 00000808 => x"75727265", + 00000809 => x"00007470", + 00000810 => x"6863614d", + 00000811 => x"20656e69", + 00000812 => x"656d6974", + 00000813 => x"6e692072", + 00000814 => x"72726574", + 00000815 => x"00747075", + 00000816 => x"6863614d", + 00000817 => x"20656e69", + 00000818 => x"65747865", + 00000819 => x"6c616e72", + 00000820 => x"746e6920", + 00000821 => x"75727265", + 00000822 => x"00007470", + 00000823 => x"74736146", + 00000824 => x"746e6920", + 00000825 => x"75727265", + 00000826 => x"00207470", + 00000827 => x"6e6b6e55", + 00000828 => x"206e776f", + 00000829 => x"70617274", + 00000830 => x"75616320", + 00000831 => x"203a6573", + 00000832 => x"00000000", + 00000833 => x"49545b20", + 00000834 => x"554f454d", + 00000835 => x"52455f54", + 00000836 => x"00005d52", + 00000837 => x"45445b20", + 00000838 => x"45434956", + 00000839 => x"5252455f", + 00000840 => x"0000005d", + 00000841 => x"4d505b20", + 00000842 => x"52455f50", + 00000843 => x"00005d52", + 00000844 => x"50204020", + 00000845 => x"00003d43", + 00000846 => x"544d202c", + 00000847 => x"3d4c4156", + 00000848 => x"00000000", + 00000849 => x"522f3c20", + 00000850 => x"003e4554", + 00000851 => x"000007bc", + 00000852 => x"000007cc", + 00000853 => x"000007f4", + 00000854 => x"00000800", + 00000855 => x"0000080c", + 00000856 => x"00000818", + 00000857 => x"00000824", + 00000858 => x"00000830", + 00000859 => x"0000083c", + 00000860 => x"00000728", + 00000861 => x"00000728", + 00000862 => x"00000848", + 00000863 => x"33323130", + 00000864 => x"37363534", + 00000865 => x"42413938", + 00000866 => x"46454443" + ); + +end neorv32_application_image; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_boot_rom.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_boot_rom.vhd new file mode 100644 index 0000000..f80f20b --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_boot_rom.vhd @@ -0,0 +1,106 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal bootloader ROM (BOOTROM) >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; +use neorv32.neorv32_bootloader_image.all; -- this file is generated by the image generator + +entity neorv32_boot_rom is + generic ( + BOOTROM_BASE : std_ulogic_vector(31 downto 0) -- boot ROM base address + ); + port ( + clk_i : in std_ulogic; -- global clock line + rden_i : in std_ulogic; -- read enable + addr_i : in std_ulogic_vector(31 downto 0); -- address + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); +end neorv32_boot_rom; + +architecture neorv32_boot_rom_rtl of neorv32_boot_rom is + + -- determine required ROM size in bytes (expand to next power of two) -- + constant boot_rom_size_index_c : natural := index_size_f((bootloader_init_image'length)); -- address with (32-bit entries) + constant boot_rom_size_c : natural := (2**boot_rom_size_index_c)*4; -- size in bytes + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(boot_rom_max_size_c); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal rden : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal addr : std_ulogic_vector(boot_rom_size_index_c-1 downto 0); + + -- ROM - initialized with executable code -- + constant mem_rom : mem32_t(0 to boot_rom_size_c/4-1) := mem32_init_f(bootloader_init_image, boot_rom_size_c/4); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing internal bootloader ROM (" & natural'image(boot_rom_size_c) & " bytes)." severity note; + assert not (boot_rom_size_c > boot_rom_max_size_c) report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range! Max "& natural'image(boot_rom_max_size_c) & " bytes." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = BOOTROM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + addr <= addr_i(boot_rom_size_index_c+1 downto 2); -- word aligned + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + mem_file_access: process(clk_i) + begin + if rising_edge(clk_i) then + rden <= rden_i and acc_en; + if (acc_en = '1') then -- reduce switching activity when not accessed + rdata <= mem_rom(to_integer(unsigned(addr))); + end if; + end if; + end process mem_file_access; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + ack_o <= rden; + + +end neorv32_boot_rom_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_bootloader_image.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_bootloader_image.vhd new file mode 100644 index 0000000..f199802 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_bootloader_image.vhd @@ -0,0 +1,1026 @@ +-- The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 +-- Auto-generated memory init file (for BOOTLOADER) from source file +-- Size: 4040 bytes + +library ieee; +use ieee.std_logic_1164.all; + +library neorv32; +use neorv32.neorv32_package.all; + +package neorv32_bootloader_image is + + constant bootloader_init_image : mem32_t := ( + 00000000 => x"00000037", + 00000001 => x"80010117", + 00000002 => x"1f810113", + 00000003 => x"80010197", + 00000004 => x"7f418193", + 00000005 => x"00000517", + 00000006 => x"0d450513", + 00000007 => x"30551073", + 00000008 => x"34151073", + 00000009 => x"30001073", + 00000010 => x"30401073", + 00000011 => x"30601073", + 00000012 => x"ffa00593", + 00000013 => x"32059073", + 00000014 => x"b0001073", + 00000015 => x"b8001073", + 00000016 => x"b0201073", + 00000017 => x"b8201073", + 00000018 => x"00000093", + 00000019 => x"00000213", + 00000020 => x"00000293", + 00000021 => x"00000313", + 00000022 => x"00000393", + 00000023 => x"00000713", + 00000024 => x"00000793", + 00000025 => x"00010417", + 00000026 => x"d9c40413", + 00000027 => x"00010497", + 00000028 => x"f9448493", + 00000029 => x"00042023", + 00000030 => x"00440413", + 00000031 => x"fe941ce3", + 00000032 => x"80010597", + 00000033 => x"f8058593", + 00000034 => x"80818613", + 00000035 => x"00c5d863", + 00000036 => x"00058023", + 00000037 => x"00158593", + 00000038 => x"ff5ff06f", + 00000039 => x"00001597", + 00000040 => x"f2c58593", + 00000041 => x"80010617", + 00000042 => x"f5c60613", + 00000043 => x"80010697", + 00000044 => x"f5468693", + 00000045 => x"00d65c63", + 00000046 => x"00058703", + 00000047 => x"00e60023", + 00000048 => x"00158593", + 00000049 => x"00160613", + 00000050 => x"fedff06f", + 00000051 => x"00000513", + 00000052 => x"00000593", + 00000053 => x"060000ef", + 00000054 => x"34051073", + 00000055 => x"30047073", + 00000056 => x"10500073", + 00000057 => x"ffdff06f", + 00000058 => x"ff810113", + 00000059 => x"00812023", + 00000060 => x"00912223", + 00000061 => x"34202473", + 00000062 => x"02044663", + 00000063 => x"34102473", + 00000064 => x"00041483", + 00000065 => x"0034f493", + 00000066 => x"00240413", + 00000067 => x"34141073", + 00000068 => x"00300413", + 00000069 => x"00941863", + 00000070 => x"34102473", + 00000071 => x"00240413", + 00000072 => x"34141073", + 00000073 => x"00012403", + 00000074 => x"00412483", + 00000075 => x"00810113", + 00000076 => x"30200073", + 00000077 => x"fd010113", + 00000078 => x"02912223", + 00000079 => x"800004b7", + 00000080 => x"00048793", + 00000081 => x"02112623", + 00000082 => x"02812423", + 00000083 => x"03212023", + 00000084 => x"01312e23", + 00000085 => x"01412c23", + 00000086 => x"01512a23", + 00000087 => x"01612823", + 00000088 => x"01712623", + 00000089 => x"01812423", + 00000090 => x"01912223", + 00000091 => x"0007a023", + 00000092 => x"8001a223", + 00000093 => x"ffff07b7", + 00000094 => x"4ac78793", + 00000095 => x"30579073", + 00000096 => x"00000693", + 00000097 => x"00000613", + 00000098 => x"00000593", + 00000099 => x"00200513", + 00000100 => x"369000ef", + 00000101 => x"3fd000ef", + 00000102 => x"00048493", + 00000103 => x"00050863", + 00000104 => x"00100513", + 00000105 => x"00000593", + 00000106 => x"429000ef", + 00000107 => x"00005537", + 00000108 => x"00000613", + 00000109 => x"00000593", + 00000110 => x"b0050513", + 00000111 => x"1d9000ef", + 00000112 => x"19d000ef", + 00000113 => x"02050663", + 00000114 => x"305000ef", + 00000115 => x"fe002783", + 00000116 => x"0027d793", + 00000117 => x"00a78533", + 00000118 => x"00f537b3", + 00000119 => x"00b785b3", + 00000120 => x"18d000ef", + 00000121 => x"08000793", + 00000122 => x"30479073", + 00000123 => x"30046073", + 00000124 => x"ffff1537", + 00000125 => x"ef850513", + 00000126 => x"27d000ef", + 00000127 => x"f1302573", + 00000128 => x"23c000ef", + 00000129 => x"ffff1537", + 00000130 => x"f3050513", + 00000131 => x"269000ef", + 00000132 => x"fe002503", + 00000133 => x"228000ef", + 00000134 => x"ffff1537", + 00000135 => x"f3850513", + 00000136 => x"255000ef", + 00000137 => x"30102573", + 00000138 => x"214000ef", + 00000139 => x"ffff1537", + 00000140 => x"f4050513", + 00000141 => x"241000ef", + 00000142 => x"fe402503", + 00000143 => x"ffff1437", + 00000144 => x"1fc000ef", + 00000145 => x"ffff1537", + 00000146 => x"f4850513", + 00000147 => x"229000ef", + 00000148 => x"fe802503", + 00000149 => x"1e8000ef", + 00000150 => x"ffff1537", + 00000151 => x"f5050513", + 00000152 => x"215000ef", + 00000153 => x"ff802503", + 00000154 => x"1d4000ef", + 00000155 => x"f5840513", + 00000156 => x"205000ef", + 00000157 => x"ff002503", + 00000158 => x"1c4000ef", + 00000159 => x"ffff1537", + 00000160 => x"f6450513", + 00000161 => x"1f1000ef", + 00000162 => x"ffc02503", + 00000163 => x"1b0000ef", + 00000164 => x"f5840513", + 00000165 => x"1e1000ef", + 00000166 => x"ff402503", + 00000167 => x"1a0000ef", + 00000168 => x"0bd000ef", + 00000169 => x"06050663", + 00000170 => x"ffff1537", + 00000171 => x"f6c50513", + 00000172 => x"1c5000ef", + 00000173 => x"219000ef", + 00000174 => x"fe002403", + 00000175 => x"00341413", + 00000176 => x"00a40933", + 00000177 => x"00893433", + 00000178 => x"00b40433", + 00000179 => x"0b9000ef", + 00000180 => x"02051663", + 00000181 => x"1f9000ef", + 00000182 => x"fe85eae3", + 00000183 => x"00b41463", + 00000184 => x"ff2566e3", + 00000185 => x"00100513", + 00000186 => x"4c8000ef", + 00000187 => x"ffff1537", + 00000188 => x"f9450513", + 00000189 => x"181000ef", + 00000190 => x"0d4000ef", + 00000191 => x"16d000ef", + 00000192 => x"fc050ae3", + 00000193 => x"ffff1537", + 00000194 => x"f9850513", + 00000195 => x"169000ef", + 00000196 => x"0b0000ef", + 00000197 => x"ffff19b7", + 00000198 => x"ffff1a37", + 00000199 => x"07200a93", + 00000200 => x"06800b13", + 00000201 => x"07500b93", + 00000202 => x"07300c13", + 00000203 => x"ffff1937", + 00000204 => x"ffff1cb7", + 00000205 => x"fa498513", + 00000206 => x"13d000ef", + 00000207 => x"11d000ef", + 00000208 => x"00050413", + 00000209 => x"0e1000ef", + 00000210 => x"f94a0513", + 00000211 => x"129000ef", + 00000212 => x"0ed000ef", + 00000213 => x"fe051ee3", + 00000214 => x"01541863", + 00000215 => x"ffff02b7", + 00000216 => x"00028067", + 00000217 => x"fd1ff06f", + 00000218 => x"01641663", + 00000219 => x"054000ef", + 00000220 => x"fc5ff06f", + 00000221 => x"01741663", + 00000222 => x"438000ef", + 00000223 => x"fb9ff06f", + 00000224 => x"01841663", + 00000225 => x"65c000ef", + 00000226 => x"fadff06f", + 00000227 => x"06c00793", + 00000228 => x"00f41663", + 00000229 => x"00100513", + 00000230 => x"fe1ff06f", + 00000231 => x"06500793", + 00000232 => x"00f41c63", + 00000233 => x"0004a783", + 00000234 => x"f40798e3", + 00000235 => x"ea0c8513", + 00000236 => x"0c5000ef", + 00000237 => x"f81ff06f", + 00000238 => x"fac90513", + 00000239 => x"ff5ff06f", + 00000240 => x"ffff1537", + 00000241 => x"de050513", + 00000242 => x"0ad0006f", + 00000243 => x"ff010113", + 00000244 => x"00112623", + 00000245 => x"30047073", + 00000246 => x"ffff1537", + 00000247 => x"e4450513", + 00000248 => x"095000ef", + 00000249 => x"059000ef", + 00000250 => x"fe051ee3", + 00000251 => x"ff002783", + 00000252 => x"00078067", + 00000253 => x"0000006f", + 00000254 => x"ff010113", + 00000255 => x"00812423", + 00000256 => x"00050413", + 00000257 => x"ffff1537", + 00000258 => x"e5450513", + 00000259 => x"00112623", + 00000260 => x"065000ef", + 00000261 => x"03040513", + 00000262 => x"0ff57513", + 00000263 => x"009000ef", + 00000264 => x"30047073", + 00000265 => x"16d000ef", + 00000266 => x"00050863", + 00000267 => x"00100513", + 00000268 => x"00000593", + 00000269 => x"19d000ef", + 00000270 => x"0000006f", + 00000271 => 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x"75636578", + 00000938 => x"6c626174", + 00000939 => x"76612065", + 00000940 => x"616c6961", + 00000941 => x"2e656c62", + 00000942 => x"00000000", + 00000943 => x"74697257", + 00000944 => x"00002065", + 00000945 => x"74796220", + 00000946 => x"74207365", + 00000947 => x"5053206f", + 00000948 => x"6c662049", + 00000949 => x"20687361", + 00000950 => x"00783040", + 00000951 => x"7928203f", + 00000952 => x"20296e2f", + 00000953 => x"00000000", + 00000954 => x"616c460a", + 00000955 => x"6e696873", + 00000956 => x"2e2e2e67", + 00000957 => x"00000020", + 00000958 => x"3c0a0a0a", + 00000959 => x"454e203c", + 00000960 => x"3356524f", + 00000961 => x"6f422032", + 00000962 => x"6f6c746f", + 00000963 => x"72656461", + 00000964 => x"0a3e3e20", + 00000965 => x"444c420a", + 00000966 => x"4e203a56", + 00000967 => x"3220766f", + 00000968 => x"30322038", + 00000969 => x"480a3132", + 00000970 => x"203a5657", + 00000971 => x"00000020", + 00000972 => x"4b4c430a", + 00000973 => x"0020203a", + 00000974 => x"53494d0a", + 00000975 => x"00203a41", + 00000976 => x"5550430a", + 00000977 => x"0020203a", + 00000978 => x"434f530a", + 00000979 => x"0020203a", + 00000980 => x"454d490a", + 00000981 => x"00203a4d", + 00000982 => x"74796220", + 00000983 => x"40207365", + 00000984 => x"00000000", + 00000985 => x"454d440a", + 00000986 => x"00203a4d", + 00000987 => x"75410a0a", + 00000988 => x"6f626f74", + 00000989 => x"6920746f", + 00000990 => x"7338206e", + 00000991 => x"7250202e", + 00000992 => x"20737365", + 00000993 => x"2079656b", + 00000994 => x"61206f74", + 00000995 => x"74726f62", + 00000996 => x"00000a2e", + 00000997 => x"0000000a", + 00000998 => x"726f6241", + 00000999 => x"2e646574", + 00001000 => x"00000a0a", + 00001001 => x"444d430a", + 00001002 => x"00203e3a", + 00001003 => x"61766e49", + 00001004 => x"2064696c", + 00001005 => x"00444d43", + 00001006 => x"33323130", + 00001007 => x"37363534", + 00001008 => x"62613938", + 00001009 => x"66656463" + ); + +end neorv32_bootloader_image; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_bus_keeper.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_bus_keeper.vhd new file mode 100644 index 0000000..17d27df --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_bus_keeper.vhd @@ -0,0 +1,180 @@ +-- ################################################################################################# +-- # << NEORV32 - Bus Keeper (BUSKEEPER) >> # +-- # ********************************************************************************************* # +-- # This unit monitors the processor-internal bus. If the accessed module does not respond within # +-- # the defined number of cycles (VHDL package: max_proc_int_response_time_c) or issues an ERROR # +-- # conditions the BUS KEEPER asserts the error signal to inform the CPU. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_bus_keeper is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset, low-active, async + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error + -- bus monitoring -- + bus_addr_i : in std_ulogic_vector(31 downto 0); -- address + bus_rden_i : in std_ulogic; -- read enable + bus_wren_i : in std_ulogic; -- write enable + bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system + bus_err_i : in std_ulogic; -- transfer error from bus system + bus_tmo_i : in std_ulogic; -- transfer timeout (external interface) + bus_ext_i : in std_ulogic -- external bus access + ); +end neorv32_bus_keeper; + +architecture neorv32_bus_keeper_rtl of neorv32_bus_keeper is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(buskeeper_size_c); -- low address boundary bit + + -- Control register -- + constant ctrl_err_type_c : natural := 0; -- r/-: error type: 0=device error, 1=access timeout + constant ctrl_err_flag_c : natural := 31; -- r/c: bus error encountered, sticky; cleared by writing zero + + -- sticky error flags -- + signal err_flag : std_ulogic; + signal err_type : std_ulogic; + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- controller -- + type control_t is record + pending : std_ulogic; + timeout : std_ulogic_vector(index_size_f(max_proc_int_response_time_c) downto 0); + err_type : std_ulogic; + bus_err : std_ulogic; + end record; + signal control : control_t; + +begin + + -- Sanity Check -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (max_proc_int_response_time_c < 2) report "NEORV32 PROCESSOR CONFIG ERROR! Processor-internal bus timeout has to >= 2." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = buskeeper_base_c(hi_abb_c downto lo_abb_c)) else '0'; + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- bus handshake -- + ack_o <= wren or rden; + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + data_o(ctrl_err_type_c) <= err_type; + data_o(ctrl_err_flag_c) <= err_flag; + end if; + -- + if (control.bus_err = '1') then -- sticky error flag + err_flag <= '1'; + err_type <= control.err_type; + elsif ((wren or rden) = '1') then -- clear on or read or write + err_flag <= '0'; + err_type <= '0'; + end if; + end if; + end process rw_access; + + + -- Keeper --------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + keeper_control: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + control.pending <= '0'; + control.bus_err <= '0'; + control.err_type <= def_rst_val_c; + control.timeout <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + -- defaults -- + control.bus_err <= '0'; + + -- access monitor: IDLE -- + if (control.pending = '0') then + control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)+1)); + if (bus_rden_i = '1') or (bus_wren_i = '1') then + control.pending <= '1'; + end if; + -- access monitor: PENDING -- + else + control.timeout <= std_ulogic_vector(unsigned(control.timeout) - 1); -- countdown timer + if (bus_err_i = '1') then -- error termination by bus system + control.err_type <= '0'; -- device error + control.bus_err <= '1'; + control.pending <= '0'; + elsif ((or_reduce_f(control.timeout) = '0') and (bus_ext_i = '0')) or -- internal access timeout + (bus_tmo_i = '1') then -- external access timeout + control.err_type <= '1'; -- timeout error + control.bus_err <= '1'; + control.pending <= '0'; + elsif (bus_ack_i = '1') then -- normal termination by bus system + control.err_type <= '0'; -- don't care + control.bus_err <= '0'; + control.pending <= '0'; + end if; + end if; + end if; + end process keeper_control; + + -- signal bus error to CPU -- + err_o <= control.bus_err; + + +end neorv32_bus_keeper_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_busswitch.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_busswitch.vhd new file mode 100644 index 0000000..7868b41 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_busswitch.vhd @@ -0,0 +1,273 @@ +-- ################################################################################################# +-- # << NEORV32 - Bus Switch >> # +-- # ********************************************************************************************* # +-- # Allows to access a single peripheral bus ("p_bus") by two controller busses. Controller port # +-- # A ("ca_bus") has priority over controller port B ("cb_bus"). # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_busswitch is + generic ( + PORT_CA_READ_ONLY : boolean; -- set if controller port A is read-only + PORT_CB_READ_ONLY : boolean -- set if controller port B is read-only + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- controller interface a -- + ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable + ca_bus_we_i : in std_ulogic; -- write enable + ca_bus_re_i : in std_ulogic; -- read enable + ca_bus_lock_i : in std_ulogic; -- exclusive access request + ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge + ca_bus_err_o : out std_ulogic; -- bus transfer error + -- controller interface b -- + cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable + cb_bus_we_i : in std_ulogic; -- write enable + cb_bus_re_i : in std_ulogic; -- read enable + cb_bus_lock_i : in std_ulogic; -- exclusive access request + cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge + cb_bus_err_o : out std_ulogic; -- bus transfer error + -- peripheral bus -- + p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B + p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + p_bus_we_o : out std_ulogic; -- write enable + p_bus_re_o : out std_ulogic; -- read enable + p_bus_lock_o : out std_ulogic; -- exclusive access request + p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + p_bus_err_i : in std_ulogic -- bus transfer error + ); +end neorv32_busswitch; + +architecture neorv32_busswitch_rtl of neorv32_busswitch is + + -- access requests -- + signal ca_rd_req_buf, ca_wr_req_buf : std_ulogic; + signal cb_rd_req_buf, cb_wr_req_buf : std_ulogic; + signal ca_req_current, ca_req_buffered : std_ulogic; + signal cb_req_current, cb_req_buffered : std_ulogic; + + -- internal bus lines -- + signal ca_bus_ack, cb_bus_ack : std_ulogic; + signal ca_bus_err, cb_bus_err : std_ulogic; + signal p_bus_we, p_bus_re : std_ulogic; + + -- access arbiter -- + type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED); + type arbiter_t is record + state : arbiter_state_t; + state_nxt : arbiter_state_t; + bus_sel : std_ulogic; + re_trig : std_ulogic; + we_trig : std_ulogic; + end record; + signal arbiter : arbiter_t; + +begin + + -- Access Buffer -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + access_buffer: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ca_rd_req_buf <= '0'; + ca_wr_req_buf <= '0'; + cb_rd_req_buf <= '0'; + cb_wr_req_buf <= '0'; + elsif rising_edge(clk_i) then + + -- controller A requests -- + if (ca_rd_req_buf = '0') and (ca_wr_req_buf = '0') then -- idle + ca_rd_req_buf <= ca_bus_re_i; + ca_wr_req_buf <= ca_bus_we_i; + elsif (ca_bus_err = '1') or -- error termination + (ca_bus_ack = '1') then -- normal termination + ca_rd_req_buf <= '0'; + ca_wr_req_buf <= '0'; + end if; + + -- controller B requests -- + if (cb_rd_req_buf = '0') and (cb_wr_req_buf = '0') then + cb_rd_req_buf <= cb_bus_re_i; + cb_wr_req_buf <= cb_bus_we_i; + elsif (cb_bus_err = '1') or -- error termination + (cb_bus_ack = '1') then -- normal termination + cb_rd_req_buf <= '0'; + cb_wr_req_buf <= '0'; + end if; + + end if; + end process access_buffer; + + -- any current requests? -- + ca_req_current <= (ca_bus_re_i or ca_bus_we_i) when (PORT_CA_READ_ONLY = false) else ca_bus_re_i; + cb_req_current <= (cb_bus_re_i or cb_bus_we_i) when (PORT_CB_READ_ONLY = false) else cb_bus_re_i; + + -- any buffered requests? -- + ca_req_buffered <= (ca_rd_req_buf or ca_wr_req_buf) when (PORT_CA_READ_ONLY = false) else ca_rd_req_buf; + cb_req_buffered <= (cb_rd_req_buf or cb_wr_req_buf) when (PORT_CB_READ_ONLY = false) else cb_rd_req_buf; + + + -- Access Arbiter Sync -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + arbiter_sync: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + arbiter.state <= IDLE; + elsif rising_edge(clk_i) then + arbiter.state <= arbiter.state_nxt; + end if; + end process arbiter_sync; + + + -- Peripheral Bus Arbiter ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered, + ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf, p_bus_ack_i, p_bus_err_i) + begin + -- arbiter defaults -- + arbiter.state_nxt <= arbiter.state; + arbiter.bus_sel <= '0'; + arbiter.we_trig <= '0'; + arbiter.re_trig <= '0'; + + -- state machine -- + case arbiter.state is + + when IDLE => -- Controller a has full bus access + -- ------------------------------------------------------------ + p_bus_src_o <= '0'; -- access from port A + if (ca_req_current = '1') then -- current request? + arbiter.bus_sel <= '0'; + arbiter.state_nxt <= BUSY; + elsif (ca_req_buffered = '1') then -- buffered request? + arbiter.bus_sel <= '0'; + arbiter.state_nxt <= RETIRE; + elsif (cb_req_current = '1') then -- current request from controller b? + arbiter.bus_sel <= '1'; + arbiter.state_nxt <= BUSY_SWITCHED; + elsif (cb_req_buffered = '1') then -- buffered request from controller b? + arbiter.bus_sel <= '1'; + arbiter.state_nxt <= RETIRE_SWITCHED; + end if; + + when BUSY => -- transaction in progress + -- ------------------------------------------------------------ + p_bus_src_o <= '0'; -- access from port A + arbiter.bus_sel <= '0'; + if (p_bus_err_i = '1') or -- error termination + (p_bus_ack_i = '1') then -- normal termination + arbiter.state_nxt <= IDLE; + end if; + + when RETIRE => -- retire pending access + -- ------------------------------------------------------------ + p_bus_src_o <= '0'; -- access from port A + arbiter.bus_sel <= '0'; + if (PORT_CA_READ_ONLY = false) then + arbiter.we_trig <= ca_wr_req_buf; + end if; + arbiter.re_trig <= ca_rd_req_buf; + arbiter.state_nxt <= BUSY; + + when BUSY_SWITCHED => -- switched transaction in progress + -- ------------------------------------------------------------ + p_bus_src_o <= '1'; -- access from port B + arbiter.bus_sel <= '1'; + if (p_bus_err_i = '1') or -- error termination + (p_bus_ack_i = '1') then -- normal termination + if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A? + arbiter.state_nxt <= RETIRE; + else + arbiter.state_nxt <= IDLE; + end if; + end if; + + when RETIRE_SWITCHED => -- retire pending switched access + -- ------------------------------------------------------------ + p_bus_src_o <= '1'; -- access from port B + arbiter.bus_sel <= '1'; + if (PORT_CB_READ_ONLY = false) then + arbiter.we_trig <= cb_wr_req_buf; + end if; + arbiter.re_trig <= cb_rd_req_buf; + arbiter.state_nxt <= BUSY_SWITCHED; + + end case; + end process arbiter_comb; + + + -- Peripheral Bus Switch ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i; + p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else + ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i; + p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else + ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i; + p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i; + p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i; + p_bus_we_o <= (p_bus_we or arbiter.we_trig); + p_bus_re_o <= (p_bus_re or arbiter.re_trig); + p_bus_lock_o <= ca_bus_lock_i or cb_bus_lock_i; + + ca_bus_rdata_o <= p_bus_rdata_i; + cb_bus_rdata_o <= p_bus_rdata_i; + + ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel); + cb_bus_ack <= p_bus_ack_i and ( arbiter.bus_sel); + ca_bus_ack_o <= ca_bus_ack; + cb_bus_ack_o <= cb_bus_ack; + + ca_bus_err <= p_bus_err_i and (not arbiter.bus_sel); + cb_bus_err <= p_bus_err_i and ( arbiter.bus_sel); + ca_bus_err_o <= ca_bus_err; + cb_bus_err_o <= cb_bus_err; + + +end neorv32_busswitch_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cfs.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cfs.vhd new file mode 100644 index 0000000..66dd758 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cfs.vhd @@ -0,0 +1,257 @@ +-- ################################################################################################# +-- # << NEORV32 - Custom Functions Subsystem (CFS) >> # +-- # ********************************************************************************************* # +-- # For tightly-coupled custom co-processors. Provides 32x32-bit memory-mapped registers. # +-- # This is just an "example/illustration template". Modify this file to implement your own # +-- # custom design logic. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cfs is + generic ( + CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic + CFS_IN_SIZE : positive; -- size of CFS input conduit in bits + CFS_OUT_SIZE : positive -- size of CFS output conduit in bits + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active, use as async + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- word write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs + -- interrupt -- + irq_o : out std_ulogic; -- interrupt request + -- custom io (conduits) -- + cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE-1 downto 0); -- custom inputs + cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0) -- custom outputs + ); +end neorv32_cfs; + +architecture neorv32_cfs_rtl of neorv32_cfs is + + -- IO space: module base address (DO NOT MODIFY!) -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(cfs_size_c); -- low address boundary bit + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- default CFS interface registers -- + type cfs_regs_t is array (0 to 3) of std_ulogic_vector(31 downto 0); -- just implement 4 registers for this example + signal cfs_reg_wr : cfs_regs_t; -- interface registers for WRITE accesses + signal cfs_reg_rd : cfs_regs_t; -- interface registers for READ accesses + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- These assignments are required to check if the CFS is accessed at all. + -- DO NOT MODIFY this unless you really know what you are doing. + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; -- full 32-bit word write enable + rden <= acc_en and rden_i; -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU + + -- NOTE: Do not modify the CFS base address or the CFS' occupied address space as this might cause access + -- collisions with other modules. + + -- This module provides an ERROR signal to signal a faulty access operation to the CPU. + -- It can be used to indicate an invalid access (for example to an unused CFS register address) or to signal + -- a faulty state (like "not operational yet"). The error signal can be checked be checked by the applications + -- "bus access fault" exception handler (provided by the system's BUSKEEPER module). + -- This signal may only be set when the module is actually accessed! Tie to zero if not explicitly used. + err_o <= '0'; + + + -- CFS Generics --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- In its default version, the CFS provides the configuration generics. single generic: + -- CFS_IN_SIZE configures the size (in bits) of the CFS input conduit cfs_in_i + -- CFS_OUT_SIZE configures the size (in bits) of the CFS output conduit cfs_out_o + -- CFS_CONFIG is a blank 32-bit generic. It is intended as a "generic conduit" to propagate custom configuration flags from the top entity down to this entiy. + + + -- CFS IOs -------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor top entity. + -- These are intended as "conduits" to propagate custom signals this entity <=> processor top entity. + + cfs_out_o <= (others => '0'); -- not used for this minimal example + + + -- Reset System --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low. + -- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset. + -- + -- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO + -- to a specific "control register" located right at the beginning of the device's address space (so this register is cleared at first). + -- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS. + -- Make sure that this clearing does not cause any unintended actions in the CFS. + + + -- Clock System --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- The processor top unit implements a clock generator providing 8 "derived clocks" + -- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals. + -- clkgen_i is always synchronous to the main system clock (clk_i). + -- + -- The following clock divider rates are available: + -- clkgen_i(clk_div2_c) -> MAIN_CLK/2 + -- clkgen_i(clk_div4_c) -> MAIN_CLK/4 + -- clkgen_i(clk_div8_c) -> MAIN_CLK/8 + -- clkgen_i(clk_div64_c) -> MAIN_CLK/64 + -- clkgen_i(clk_div128_c) -> MAIN_CLK/128 + -- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024 + -- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048 + -- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096 + -- + -- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct: + -- + -- if (rstn_i = '0') then -- async and low-active reset (if required at all) + -- ... + -- elsif rising_edge(clk_i) then -- always use the main clock for all clock processes! + -- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable + -- ... + -- end if; + -- end if; + -- + -- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the SPI) requires the clocks generated by the + -- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high. + -- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated. + -- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption. + + clkgen_en_o <= '0'; -- not used for this minimal example + + + -- Interrupt ------------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + -- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1. + -- The interrupt is triggered by a one-shot rising edge. After triggering, the interrupt appears as "pending" in the CPU's mie register + -- ready to trigger execution of the according interrupt handler. The interrupt request signal should be triggered + -- whenever an interrupt condition is fulfilled. It is the task of the application to programmer to enable/clear the CFS interrupt + -- using the CPU's mie and mip registers when reuqired. + + irq_o <= '0'; -- not used for this minimal example + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO + -- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte) + -- will trigger a store bus access fault exception. + -- + -- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide + -- a for global control of the unit, a for reading/writing from/to a data FIFO, a + -- for issuing commands and a for status information. + -- + -- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later + -- if the module needs additional time; the maximum latency until an unacknowledged access will trigger a bus exception is defined via the package's + -- global "bus_timeout_c" constant). If no ACK is generated at all, the bus access will time out and cause a bus access fault exception. + + -- Host access: Read and write access to the interface registers + bus transfer acknowledge. + -- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not + -- associated with any writable or readable register - an access to those is simply ignored but still acknowledged. + + host_access: process(clk_i) + begin + if rising_edge(clk_i) then -- synchronous interface for reads and writes + -- transfer/access acknowledge -- + ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request; all r/w accesses (to any cfs_reg) will succeed +-- ack_o <= rden; -- use this construct if your CFS is read-only +-- ack_o <= wren; -- use this construct if your CFS is write-only +-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...) + + -- write access -- + if (wren = '1') then -- word-wide write-access only! + if (addr = cfs_reg0_addr_c) then -- make sure to use the internal "addr" signal for the read/write interface + cfs_reg_wr(0) <= data_i; -- for example: control register + end if; + if (addr = cfs_reg1_addr_c) then + cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo + end if; + if (addr = cfs_reg2_addr_c) then + cfs_reg_wr(2) <= data_i; -- for example: command fifo + end if; + if (addr = cfs_reg3_addr_c) then + cfs_reg_wr(3) <= data_i; -- for example: status register + end if; + end if; + + -- read access -- + data_o <= (others => '0'); -- the output has to be zero if there is no actual read access + if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU + case addr is -- make sure to use the internal 'addr' signal for the read/write interface + when cfs_reg0_addr_c => data_o <= cfs_reg_rd(0); + when cfs_reg1_addr_c => data_o <= cfs_reg_rd(1); + when cfs_reg2_addr_c => data_o <= cfs_reg_rd(2); + when cfs_reg3_addr_c => data_o <= cfs_reg_rd(3); + when others => data_o <= (others => '0'); -- the remaining registers are not implemented and will read as zero + end case; + end if; + end if; + end process host_access; + + + -- CFS Function Core ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- This is where the actual functionality can be implemented. + -- In this example we are just implementing four r/w registers that invert any value written to them. + + cfs_core: process(cfs_reg_wr) + begin + cfs_reg_rd(0) <= not cfs_reg_wr(0); -- just invert the written value + cfs_reg_rd(1) <= not cfs_reg_wr(1); + cfs_reg_rd(2) <= not cfs_reg_wr(2); + cfs_reg_rd(3) <= not cfs_reg_wr(3); + end process cfs_core; + + +end neorv32_cfs_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu.vhd new file mode 100644 index 0000000..b36dfd2 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu.vhd @@ -0,0 +1,444 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU Top Entity >> # +-- # ********************************************************************************************* # +-- # NEORV32 CPU: # +-- # * neorv32_cpu.vhd - CPU top entity # +-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit # +-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor # +-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor # +-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor # +-- # * neorv32_cpu_cp_shifter.vhd - Base ISA shifter unit # +-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit # +-- # * neorv32_cpu_control.vhd - CPU control and CSR system # +-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder # +-- # * neorv32_cpu_regfile.vhd - Data register file # +-- # * neorv32_package.vhd - Main CPU & Processor package file # +-- # # +-- # Check out the CPU's online documentation for more information: # +-- # HQ: https://github.com/stnolting/neorv32 # +-- # Data Sheet: https://stnolting.github.io/neorv32 # +-- # User Guide: https://stnolting.github.io/neorv32/ug # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu is + generic ( + -- General -- + HW_THREAD_ID : natural; -- hardware thread id (32-bit) + CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address + CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean; -- implement muld/div extension? + CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? + -- Extension Options -- + FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64) + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + sleep_o : out std_ulogic; -- cpu is in sleep mode when set + debug_o : out std_ulogic; -- cpu is in debug mode when set + -- instruction bus interface -- + i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + i_bus_we_o : out std_ulogic; -- write enable + i_bus_re_o : out std_ulogic; -- read enable + i_bus_lock_o : out std_ulogic; -- exclusive access request + i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + i_bus_err_i : in std_ulogic; -- bus transfer error + i_bus_fence_o : out std_ulogic; -- executed FENCEI operation + i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level + -- data bus interface -- + d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + d_bus_we_o : out std_ulogic; -- write enable + d_bus_re_o : out std_ulogic; -- read enable + d_bus_lock_o : out std_ulogic; -- exclusive access request + d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + d_bus_err_i : in std_ulogic; -- bus transfer error + d_bus_fence_o : out std_ulogic; -- executed FENCE operation + d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level + -- system time input from MTIME -- + time_i : in std_ulogic_vector(63 downto 0); -- current system time + -- interrupts (risc-v compliant) -- + msw_irq_i : in std_ulogic;-- machine software interrupt + mext_irq_i : in std_ulogic;-- machine external interrupt + mtime_irq_i : in std_ulogic;-- machine timer interrupt + -- fast interrupts (custom) -- + firq_i : in std_ulogic_vector(15 downto 0); + -- debug mode (halt) request -- + db_halt_req_i : in std_ulogic + ); +end neorv32_cpu; + +architecture neorv32_cpu_rtl of neorv32_cpu is + + -- local signals -- + signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + signal comparator : std_ulogic_vector(1 downto 0); -- comparator result + signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate + signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction + signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers + signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result + signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result + signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data + signal alu_idone : std_ulogic; -- iterative alu operation done + signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch + signal bus_d_wait : std_ulogic; -- wait for current bus data access + signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data + signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register + signal ma_instr : std_ulogic; -- misaligned instruction address + signal ma_load : std_ulogic; -- misaligned load data address + signal ma_store : std_ulogic; -- misaligned store data address + signal excl_state : std_ulogic; -- atomic/exclusive access lock status + signal be_instr : std_ulogic; -- bus error on instruction access + signal be_load : std_ulogic; -- bus error on load data access + signal be_store : std_ulogic; -- bus error on store data access + signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch + signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction) + signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next executed instruction) + signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags + + -- pmp interface -- + signal pmp_addr : pmp_addr_if_t; + signal pmp_ctrl : pmp_ctrl_if_t; + +begin + + -- CPU ISA Configuration --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report + "NEORV32 CPU ISA Configuration (MARCH): " & + cond_sel_string_f(CPU_EXTENSION_RISCV_E, "RV32E", "RV32I") & + cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_B, "B", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zicsr, "_Zicsr", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") & + cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_Debug", "") & + "" + severity note; + + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- hardware reset notifier -- + assert not (dedicated_reset_c = false) report "NEORV32 CPU CONFIG NOTE: Implementing NO dedicated hardware reset for uncritical registers (default, might reduce area). Set package constant = TRUE to configure a DEFINED reset value for all CPU registers." severity note; + assert not (dedicated_reset_c = true) report "NEORV32 CPU CONFIG NOTE: Implementing defined hardware reset for uncritical registers (non-default, reset-to-zero, might increase area)." severity note; + assert not ((def_rst_val_c /= '-') and (def_rst_val_c /= '0')) report "NEORV32 CPU CONFIG ERROR! Invalid configuration of package constant (has to be '-' or '0')." severity error; + + -- CSR system -- + assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when = false." severity warning; + + -- CPU counters (cycle and instret) -- + assert not ((CPU_EXTENSION_RISCV_Zicntr = true) and ((CPU_CNT_WIDTH < 0) or (CPU_CNT_WIDTH > 64))) report "NEORV32 CPU CONFIG ERROR! Invalid configuration. Has to be 0..64." severity error; + assert not ((CPU_EXTENSION_RISCV_Zicntr = true) and (CPU_CNT_WIDTH < 64)) report "NEORV32 CPU CONFIG WARNING! Implementing CPU and CSRs with reduced size (" & integer'image(CPU_CNT_WIDTH) & "-bit instead of 64-bit). This is not RISC-V compliant and might have unintended SW side effects." severity warning; + + -- U-extension requires Zicsr extension -- + assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires extension to be enabled." severity error; + + -- Instruction prefetch buffer size -- + assert not (is_power_of_two_f(CPU_IPB_ENTRIES) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer has to be a power of two." severity error; + + -- Co-processor timeout counter (for debugging only) -- + assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning; + + -- PMP regions check -- + assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range (0..64)." severity error; + -- PMP granularity -- + assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! has to be a power of two." severity error; + assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! has to be >= 8 bytes." severity error; + assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires extension to be enabled." severity error; + + -- HPM counters check -- + assert not ((CPU_EXTENSION_RISCV_Zihpm = true) and (HPM_NUM_CNTS > 29)) report "NEORV32 CPU CONFIG ERROR! Number of HPM counters out of valid range (0..29)." severity error; + assert not ((CPU_EXTENSION_RISCV_Zihpm = true) and ((HPM_CNT_WIDTH < 0) or (HPM_CNT_WIDTH > 64))) report "NEORV32 CPU CONFIG ERROR! HPM counter width has to be 0..64 bit." severity error; + assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_Zihpm = true)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors extension requires extension to be enabled." severity error; + + -- Mul-extension -- + assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! and extensions cannot co-exist!" severity error; + + -- Debug mode -- + assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires extension to be enabled." severity error; + assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires extension to be enabled." severity error; + + -- fast multiplication option -- + assert not (FAST_MUL_EN = true) report "NEORV32 CPU CONFIG NOTE: set. Trying to use DSP blocks for base ISA multiplications." severity note; + + -- fast shift option -- + assert not (FAST_SHIFT_EN = true) report "NEORV32 CPU CONFIG NOTE: set. Implementing full-parallel logic / barrel shifters." severity note; + + + -- Control Unit --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_control_inst: neorv32_cpu_control + generic map ( + -- General -- + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id + CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address + CPU_DEBUG_ADDR => CPU_DEBUG_ADDR, -- cpu debug mode start address + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode? + -- Extension Options -- + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + ctrl_o => ctrl, -- main control bus + -- status input -- + alu_idone_i => alu_idone, -- ALU iterative operation done + bus_i_wait_i => bus_i_wait, -- wait for bus + bus_d_wait_i => bus_d_wait, -- wait for bus + excl_state_i => excl_state, -- atomic/exclusive access lock status + -- data input -- + instr_i => instr, -- instruction + cmp_i => comparator, -- comparator status + alu_add_i => alu_add, -- ALU address result + rs1_i => rs1, -- rf source 1 + -- data output -- + imm_o => imm, -- immediate + fetch_pc_o => fetch_pc, -- PC for instruction fetch + curr_pc_o => curr_pc, -- current PC (corresponding to current instruction) + next_pc_o => next_pc, -- next PC (corresponding to next instruction) + csr_rdata_o => csr_rdata, -- CSR read data + -- FPU interface -- + fpu_flags_i => fpu_flags, -- exception flags + -- debug mode (halt) request -- + db_halt_req_i => db_halt_req_i, + -- interrupts (risc-v compliant) -- + msw_irq_i => msw_irq_i, -- machine software interrupt + mext_irq_i => mext_irq_i, -- machine external interrupt + mtime_irq_i => mtime_irq_i, -- machine timer interrupt + -- fast interrupts (custom) -- + firq_i => firq_i, -- fast interrupt trigger + -- system time input from MTIME -- + time_i => time_i, -- current system time + -- physical memory protection -- + pmp_addr_o => pmp_addr, -- addresses + pmp_ctrl_o => pmp_ctrl, -- configs + -- bus access exceptions -- + mar_i => mar, -- memory address register + ma_instr_i => ma_instr, -- misaligned instruction address + ma_load_i => ma_load, -- misaligned load data address + ma_store_i => ma_store, -- misaligned store data address + be_instr_i => be_instr, -- bus error on instruction access + be_load_i => be_load, -- bus error on load data access + be_store_i => be_store -- bus error on store data access + ); + + -- CPU is sleeping? -- + sleep_o <= ctrl(ctrl_sleep_c); -- set when CPU is sleeping (after WFI) + + -- CPU is in debug mode? -- + debug_o <= ctrl(ctrl_debug_running_c); + + + -- Register File -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_regfile_inst: neorv32_cpu_regfile + generic map ( + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension? + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + ctrl_i => ctrl, -- main control bus + -- data input -- + mem_i => mem_rdata, -- memory read data + alu_i => alu_res, -- ALU result + -- data output -- + rs1_o => rs1, -- operand 1 + rs2_o => rs2 -- operand 2 + ); + + + -- ALU ------------------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_alu_inst: neorv32_cpu_alu + generic map ( + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + ctrl_i => ctrl, -- main control bus + -- data input -- + rs1_i => rs1, -- rf source 1 + rs2_i => rs2, -- rf source 2 + pc_i => curr_pc, -- current PC + pc2_i => next_pc, -- next PC + imm_i => imm, -- immediate + csr_i => csr_rdata, -- CSR read data + -- data output -- + cmp_o => comparator, -- comparator status + res_o => alu_res, -- ALU result + add_o => alu_add, -- address computation result + fpu_flags_o => fpu_flags, -- FPU exception flags + -- status -- + idone_o => alu_idone -- iterative processing units done? + ); + + + -- Bus Interface Unit --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_bus_inst: neorv32_cpu_bus + generic map ( + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + ctrl_i => ctrl, -- main control bus + -- cpu instruction fetch interface -- + fetch_pc_i => fetch_pc, -- PC for instruction fetch + instr_o => instr, -- instruction + i_wait_o => bus_i_wait, -- wait for fetch to complete + -- + ma_instr_o => ma_instr, -- misaligned instruction address + be_instr_o => be_instr, -- bus error on instruction access + -- cpu data access interface -- + addr_i => alu_add, -- ALU.add result -> access address + wdata_i => rs2, -- write data + rdata_o => mem_rdata, -- read data + mar_o => mar, -- current memory address register + d_wait_o => bus_d_wait, -- wait for access to complete + -- + excl_state_o => excl_state, -- atomic/exclusive access status + ma_load_o => ma_load, -- misaligned load data address + ma_store_o => ma_store, -- misaligned store data address + be_load_o => be_load, -- bus error on load data access + be_store_o => be_store, -- bus error on store data access + -- physical memory protection -- + pmp_addr_i => pmp_addr, -- addresses + pmp_ctrl_i => pmp_ctrl, -- configurations + -- instruction bus -- + i_bus_addr_o => i_bus_addr_o, -- bus access address + i_bus_rdata_i => i_bus_rdata_i, -- bus read data + i_bus_wdata_o => i_bus_wdata_o, -- bus write data + i_bus_ben_o => i_bus_ben_o, -- byte enable + i_bus_we_o => i_bus_we_o, -- write enable + i_bus_re_o => i_bus_re_o, -- read enable + i_bus_lock_o => i_bus_lock_o, -- exclusive access request + i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge + i_bus_err_i => i_bus_err_i, -- bus transfer error + i_bus_fence_o => i_bus_fence_o, -- fence operation + -- data bus -- + d_bus_addr_o => d_bus_addr_o, -- bus access address + d_bus_rdata_i => d_bus_rdata_i, -- bus read data + d_bus_wdata_o => d_bus_wdata_o, -- bus write data + d_bus_ben_o => d_bus_ben_o, -- byte enable + d_bus_we_o => d_bus_we_o, -- write enable + d_bus_re_o => d_bus_re_o, -- read enable + d_bus_lock_o => d_bus_lock_o, -- exclusive access request + d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge + d_bus_err_i => d_bus_err_i, -- bus transfer error + d_bus_fence_o => d_bus_fence_o -- fence operation + ); + + -- current privilege level -- + i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c); + d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c); + + +end neorv32_cpu_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_alu.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_alu.vhd new file mode 100644 index 0000000..9226653 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_alu.vhd @@ -0,0 +1,349 @@ +-- ################################################################################################# +-- # << NEORV32 - Arithmetical/Logical Unit >> # +-- # ********************************************************************************************* # +-- # Main data and address ALU and co-processor interface/arbiter. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_alu is + generic ( + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + -- Extension Options -- + FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- data input -- + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC + pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- next PC + imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate + csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data + -- data output -- + cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result + add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result + fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags + -- status -- + idone_o : out std_ulogic -- iterative processing units done? + ); +end neorv32_cpu_alu; + +architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is + + -- comparator -- + signal cmp_opx : std_ulogic_vector(data_width_c downto 0); + signal cmp_opy : std_ulogic_vector(data_width_c downto 0); + signal cmp : std_ulogic_vector(1 downto 0); -- comparator status + + -- operands -- + signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0); + + -- results -- + signal addsub_res : std_ulogic_vector(data_width_c downto 0); + signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); + signal cp_res : std_ulogic_vector(data_width_c-1 downto 0); + + -- co-processor arbiter and interface -- + type cp_ctrl_t is record + cmd : std_ulogic; + cmd_ff : std_ulogic; + start : std_ulogic; + busy : std_ulogic; + timeout : std_ulogic_vector(9 downto 0); + end record; + signal cp_ctrl : cp_ctrl_t; + + -- co-processor interface -- + signal cp_start : std_ulogic_vector(3 downto 0); -- trigger co-processor i + signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done + signal cp_result : cp_data_if_t; -- co-processor result + +begin + + -- Comparator Unit (for conditional branches) --------------------------------------------- + -- ------------------------------------------------------------------------------------------- + cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i; + cmp_opy <= (rs2_i(rs2_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2_i; + + cmp(cmp_equal_c) <= '1' when (rs1_i = rs2_i) else '0'; + cmp(cmp_less_c) <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0'; + cmp_o <= cmp; + + + -- ALU Input Operand Mux ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + opa <= pc_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops + opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand) + + + -- Binary Adder/Subtracter ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + binary_arithmetic_core: process(ctrl_i, opa, opb) + variable cin_v : std_ulogic_vector(0 downto 0); + variable op_a_v : std_ulogic_vector(data_width_c downto 0); + variable op_b_v : std_ulogic_vector(data_width_c downto 0); + variable op_y_v : std_ulogic_vector(data_width_c downto 0); + variable res_v : std_ulogic_vector(data_width_c downto 0); + begin + -- operand sign-extension -- + op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa; + op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb; + -- add/sub(slt) select -- + if (ctrl_i(ctrl_alu_op0_c) = '1') then -- subtraction + op_y_v := not op_b_v; + cin_v(0) := '1'; + else -- addition + op_y_v := op_b_v; + cin_v(0) := '0'; + end if; + -- adder core -- + addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0))); + end process binary_arithmetic_core; + + -- direct output of adder result -- + add_o <= addsub_res(data_width_c-1 downto 0); + + + -- ALU Operation Select ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + alu_core: process(ctrl_i, addsub_res, rs1_i, opb) + begin + case ctrl_i(ctrl_alu_op2_c downto ctrl_alu_op0_c) is + when alu_op_add_c => alu_res <= addsub_res(data_width_c-1 downto 0); -- (default) + when alu_op_sub_c => alu_res <= addsub_res(data_width_c-1 downto 0); +-- when alu_op_mova_c => alu_res <= rs1_i; -- FIXME + when alu_op_slt_c => alu_res <= (others => '0'); alu_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow + when alu_op_movb_c => alu_res <= opb; + when alu_op_xor_c => alu_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc) + when alu_op_or_c => alu_res <= rs1_i or opb; + when alu_op_and_c => alu_res <= rs1_i and opb; + when others => alu_res <= addsub_res(data_width_c-1 downto 0); + end case; + end process alu_core; + + -- ALU Function Select -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + alu_function_mux: process(ctrl_i, alu_res, pc2_i, csr_i, cp_res) + begin + case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is + when alu_func_core_c => res_o <= alu_res; -- (default) + when alu_func_nxpc_c => res_o <= pc2_i; + when alu_func_csrr_c => res_o <= csr_i; + when alu_func_copro_c => res_o <= cp_res; + when others => res_o <= alu_res; -- undefined + end case; + end process alu_function_mux; + + + -- ************************************************************************************************************************** + -- Co-Processors + -- ************************************************************************************************************************** + + -- Co-Processor Arbiter ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Interface: + -- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data + -- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered + cp_arbiter: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + cp_ctrl.cmd_ff <= '0'; + cp_ctrl.busy <= '0'; + cp_ctrl.timeout <= (others => '0'); + elsif rising_edge(clk_i) then + cp_ctrl.cmd_ff <= cp_ctrl.cmd; + -- timeout counter -- + if (cp_ctrl.start = '1') then + cp_ctrl.busy <= '1'; + elsif (or_reduce_f(cp_valid) = '1') then + cp_ctrl.busy <= '0'; + end if; + if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then + cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1); + else + cp_ctrl.timeout <= (others => '0'); + end if; + if (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout + assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning; + end if; + end if; + end process cp_arbiter; + + -- is co-processor operation? -- + cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_copro_c) else '0'; + cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0'; + + -- co-processor select / star trigger -- + cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0'; + cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0'; + cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0'; + cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0'; + + -- co-processor operation done? -- + idone_o <= or_reduce_f(cp_valid); + + -- co-processor result - only the *actually selected* co-processor may output data != 0 -- + cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3); + + + -- Co-Processor 0: Shifter (CPU Core ISA) -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter + generic map ( + FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + ctrl_i => ctrl_i, -- main control bus + start_i => cp_start(0), -- trigger operation + -- data input -- + rs1_i => rs1_i, -- rf source 1 + shamt_i => opb(index_size_f(data_width_c)-1 downto 0), -- shift amount + -- result and status -- + res_o => cp_result(0), -- operation result + valid_o => cp_valid(0) -- data output valid + ); + + + -- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_cp_muldiv_inst_true: + if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate + neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv + generic map ( + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for faster multiplication + DIVISION_EN => CPU_EXTENSION_RISCV_M -- implement divider hardware + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + ctrl_i => ctrl_i, -- main control bus + start_i => cp_start(1), -- trigger operation + -- data input -- + rs1_i => rs1_i, -- rf source 1 + rs2_i => rs2_i, -- rf source 2 + -- result and status -- + res_o => cp_result(1), -- operation result + valid_o => cp_valid(1) -- data output valid + ); + end generate; + + neorv32_cpu_cp_muldiv_inst_false: + if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate + cp_result(1) <= (others => '0'); + cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access + end generate; + + + -- Co-Processor 2: Bit-Manipulation Unit ('B' Extension) ---------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_cp_bitmanip_inst_true: + if (CPU_EXTENSION_RISCV_B = true) generate + neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip + generic map ( + FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + ctrl_i => ctrl_i, -- main control bus + start_i => cp_start(2), -- trigger operation + -- data input -- + cmp_i => cmp, -- comparator status + rs1_i => rs1_i, -- rf source 1 + rs2_i => rs2_i, -- rf source 2 + shamt_i => opb(index_size_f(data_width_c)-1 downto 0), -- shift amount + -- result and status -- + res_o => cp_result(2), -- operation result + valid_o => cp_valid(2) -- data output valid + ); + end generate; + + neorv32_cpu_cp_bitmanip_inst_false: + if (CPU_EXTENSION_RISCV_B = false) generate + cp_result(2) <= (others => '0'); + cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access + end generate; + + + -- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) --------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_cp_fpu_inst_true: + if (CPU_EXTENSION_RISCV_Zfinx = true) generate + neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + ctrl_i => ctrl_i, -- main control bus + start_i => cp_start(3), -- trigger operation + -- data input -- + cmp_i => cmp, -- comparator status + rs1_i => rs1_i, -- rf source 1 + rs2_i => rs2_i, -- rf source 2 + -- result and status -- + res_o => cp_result(3), -- operation result + fflags_o => fpu_flags_o, -- exception flags + valid_o => cp_valid(3) -- data output valid + ); + end generate; + + neorv32_cpu_cp_fpu_inst_false: + if (CPU_EXTENSION_RISCV_Zfinx = false) generate + cp_result(3) <= (others => '0'); + fpu_flags_o <= (others => '0'); + cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access + end generate; + + +end neorv32_cpu_cpu_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_bus.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_bus.vhd new file mode 100644 index 0000000..56713c8 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_bus.vhd @@ -0,0 +1,509 @@ +-- ################################################################################################# +-- # << NEORV32 - Bus Interface Unit >> # +-- # ********************************************************************************************* # +-- # Instruction and data bus interfaces and physical memory protection (PMP). # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_bus is + generic ( + CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension? + CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension? + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic := '0'; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- cpu instruction fetch interface -- + fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch + instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction + i_wait_o : out std_ulogic; -- wait for fetch to complete + -- + ma_instr_o : out std_ulogic; -- misaligned instruction address + be_instr_o : out std_ulogic; -- bus error on instruction access + -- cpu data access interface -- + addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address + wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data + rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data + mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register + d_wait_o : out std_ulogic; -- wait for access to complete + -- + excl_state_o : out std_ulogic; -- atomic/exclusive access status + ma_load_o : out std_ulogic; -- misaligned load data address + ma_store_o : out std_ulogic; -- misaligned store data address + be_load_o : out std_ulogic; -- bus error on load data access + be_store_o : out std_ulogic; -- bus error on store data access + -- physical memory protection -- + pmp_addr_i : in pmp_addr_if_t; -- addresses + pmp_ctrl_i : in pmp_ctrl_if_t; -- configs + -- instruction bus -- + i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + i_bus_we_o : out std_ulogic; -- write enable + i_bus_re_o : out std_ulogic; -- read enable + i_bus_lock_o : out std_ulogic; -- exclusive access request + i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + i_bus_err_i : in std_ulogic; -- bus transfer error + i_bus_fence_o : out std_ulogic; -- fence operation + -- data bus -- + d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + d_bus_we_o : out std_ulogic; -- write enable + d_bus_re_o : out std_ulogic; -- read enable + d_bus_lock_o : out std_ulogic; -- exclusive access request + d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + d_bus_err_i : in std_ulogic; -- bus transfer error + d_bus_fence_o : out std_ulogic -- fence operation + ); +end neorv32_cpu_bus; + +architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is + + -- PMP modes -- + constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled) +--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range +--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region + constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes) + + -- PMP granularity -- + constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY); + + -- PMP configuration register bits -- + constant pmp_cfg_r_c : natural := 0; -- read permit + constant pmp_cfg_w_c : natural := 1; -- write permit + constant pmp_cfg_x_c : natural := 2; -- execute permit + constant pmp_cfg_al_c : natural := 3; -- mode bit low + constant pmp_cfg_ah_c : natural := 4; -- mode bit high + -- + constant pmp_cfg_l_c : natural := 7; -- locked entry + + -- data interface registers -- + signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0); + + -- data access -- + signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data + signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data + signal rdata_align : std_ulogic_vector(data_width_c-1 downto 0); -- read-data alignment + signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable + + -- misaligned access? -- + signal d_misaligned, i_misaligned : std_ulogic; + + -- bus arbiter -- + type bus_arbiter_t is record + rd_req : std_ulogic; -- read access in progress + wr_req : std_ulogic; -- write access in progress + err_align : std_ulogic; -- alignment error + err_bus : std_ulogic; -- bus access error + end record; + signal i_arbiter, d_arbiter : bus_arbiter_t; + + -- atomic/exclusive access - reservation controller -- + signal exclusive_lock : std_ulogic; + signal exclusive_lock_status : std_ulogic_vector(data_width_c-1 downto 0); -- read data + + -- physical memory protection -- + type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0); + type pmp_t is record + addr_mask : pmp_addr_t; + region_base : pmp_addr_t; -- region config base address + region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator + region_d_addr : pmp_addr_t; -- masked data access base address for comparator + i_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface + d_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface + if_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation + ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation + st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation + end record; + signal pmp : pmp_t; + + -- memory control signal buffer (when using PMP) -- + signal d_bus_we, d_bus_we_buf : std_ulogic; + signal d_bus_re, d_bus_re_buf : std_ulogic; + signal i_bus_re, i_bus_re_buf : std_ulogic; + + -- pmp faults anyone? -- + signal if_pmp_fault : std_ulogic; -- pmp instruction access fault + signal ld_pmp_fault : std_ulogic; -- pmp load access fault + signal st_pmp_fault : std_ulogic; -- pmp store access fault + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & + integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & + "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning; + + + -- Data Interface: Access Address --------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + mem_adr_reg: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + mar <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + if (ctrl_i(ctrl_bus_mo_we_c) = '1') then + mar <= addr_i; + end if; + end if; + end process mem_adr_reg; + + -- read-back for exception controller -- + mar_o <= mar; + + -- alignment check -- + misaligned_d_check: process(mar, ctrl_i) + begin + -- check data access -- + d_misaligned <= '0'; -- default + case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size + when "00" => -- byte + d_misaligned <= '0'; + when "01" => -- half-word + if (mar(0) /= '0') then + d_misaligned <= '1'; + end if; + when others => -- word + if (mar(1 downto 0) /= "00") then + d_misaligned <= '1'; + end if; + end case; + end process misaligned_d_check; + + + -- Data Interface: Write Data ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + mem_do_reg: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + mdo <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + if (ctrl_i(ctrl_bus_mo_we_c) = '1') then + mdo <= wdata_i; -- memory data output register (MDO) + end if; + end if; + end process mem_do_reg; + + -- byte enable and output data alignment -- + byte_enable: process(mar, mdo, ctrl_i) + begin + case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size + when "00" => -- byte + d_bus_wdata(07 downto 00) <= mdo(07 downto 00); + d_bus_wdata(15 downto 08) <= mdo(07 downto 00); + d_bus_wdata(23 downto 16) <= mdo(07 downto 00); + d_bus_wdata(31 downto 24) <= mdo(07 downto 00); + case mar(1 downto 0) is + when "00" => d_bus_ben <= "0001"; + when "01" => d_bus_ben <= "0010"; + when "10" => d_bus_ben <= "0100"; + when others => d_bus_ben <= "1000"; + end case; + when "01" => -- half-word + d_bus_wdata(31 downto 16) <= mdo(15 downto 00); + d_bus_wdata(15 downto 00) <= mdo(15 downto 00); + if (mar(1) = '0') then + d_bus_ben <= "0011"; -- low half-word + else + d_bus_ben <= "1100"; -- high half-word + end if; + when others => -- word + d_bus_wdata <= mdo; + d_bus_ben <= "1111"; -- full word + end case; + end process byte_enable; + + + -- Data Interface: Read Data -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + mem_di_reg: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + mdi <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + if (ctrl_i(ctrl_bus_mi_we_c) = '1') then + mdi <= d_bus_rdata; -- memory data input register (MDI) + end if; + end if; + end process mem_di_reg; + + -- input data alignment and sign extension -- + read_align: process(mdi, mar, ctrl_i) + variable byte_in_v : std_ulogic_vector(07 downto 0); + variable hword_in_v : std_ulogic_vector(15 downto 0); + begin + -- sub-word input -- + case mar(1 downto 0) is + when "00" => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0 + when "01" => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0 + when "10" => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1 + when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1 + end case; + -- actual data size -- + case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is + when "00" => -- byte + rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension + rdata_align(07 downto 00) <= byte_in_v; + when "01" => -- half-word + rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension + rdata_align(15 downto 00) <= hword_in_v; -- high half-word + when others => -- word + rdata_align <= mdi; -- full word + end case; + end process read_align; + + -- insert exclusive lock status for SC operations only -- + rdata_o <= exclusive_lock_status when (CPU_EXTENSION_RISCV_A = true) and (ctrl_i(ctrl_bus_ch_lock_c) = '1') else rdata_align; + + + -- Data Access Arbiter -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + data_access_arbiter: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + d_arbiter.wr_req <= '0'; + d_arbiter.rd_req <= '0'; + d_arbiter.err_align <= '0'; + d_arbiter.err_bus <= '0'; + elsif rising_edge(clk_i) then + -- data access request -- + if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle + d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c); + d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c); + d_arbiter.err_align <= d_misaligned; + d_arbiter.err_bus <= '0'; + else -- in progress + d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); + d_arbiter.err_bus <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and + (not ctrl_i(ctrl_bus_derr_ack_c)); + if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort + d_arbiter.wr_req <= '0'; + d_arbiter.rd_req <= '0'; + end if; + end if; + end if; + end process data_access_arbiter; + + -- wait for bus transaction to finish -- + d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i); + + -- output data access error to controller -- + ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align; + be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus; + ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align; + be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus; + + -- data bus (read/write)-- + d_bus_addr_o <= mar; + d_bus_wdata_o <= d_bus_wdata; + d_bus_ben_o <= d_bus_ben; + d_bus_we <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault + d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault + d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we; + d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re; + d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c); + d_bus_rdata <= d_bus_rdata_i; + + -- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c -- + pmp_dbus_buffer: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + d_bus_we_buf <= '0'; + d_bus_re_buf <= '0'; + elsif rising_edge(clk_i) then + d_bus_we_buf <= d_bus_we; + d_bus_re_buf <= d_bus_re; + end if; + end process pmp_dbus_buffer; + + + -- Reservation Controller (LR/SC [A extension]) ------------------------------------------- + -- ------------------------------------------------------------------------------------------- + exclusive_access_controller: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + exclusive_lock <= '0'; + elsif rising_edge(clk_i) then + if (CPU_EXTENSION_RISCV_A = true) then + if (ctrl_i(ctrl_trap_c) = '1') or (ctrl_i(ctrl_bus_de_lock_c) = '1') then -- remove lock if entering a trap or executing a non-load-reservate memory access + exclusive_lock <= '0'; + elsif (ctrl_i(ctrl_bus_lock_c) = '1') then -- set new lock + exclusive_lock <= '1'; + end if; + else + exclusive_lock <= '0'; + end if; + end if; + end process exclusive_access_controller; + + -- lock status for SC operation -- + exclusive_lock_status(data_width_c-1 downto 1) <= (others => '0'); + exclusive_lock_status(0) <= not exclusive_lock; + + -- output reservation status to control unit (to check if SC should write at all) -- + excl_state_o <= exclusive_lock; + + -- output to memory system -- + i_bus_lock_o <= '0'; -- instruction fetches cannot be locked + d_bus_lock_o <= exclusive_lock; + + + -- Instruction Fetch Arbiter -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ifetch_arbiter: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + i_arbiter.rd_req <= '0'; + i_arbiter.err_align <= '0'; + i_arbiter.err_bus <= '0'; + elsif rising_edge(clk_i) then + -- instruction fetch request -- + if (i_arbiter.rd_req = '0') then -- idle + i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c); + i_arbiter.err_align <= i_misaligned; + i_arbiter.err_bus <= '0'; + else -- in progres + i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); + i_arbiter.err_bus <= (i_arbiter.err_bus or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c)); + if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort + i_arbiter.rd_req <= '0'; + end if; + end if; + end if; + end process ifetch_arbiter; + + i_arbiter.wr_req <= '0'; -- instruction fetch is read-only + + -- wait for bus transaction to finish -- + i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i); + + -- output instruction fetch error to controller -- + ma_instr_o <= i_arbiter.err_align; + be_instr_o <= i_arbiter.err_bus; + + -- instruction bus (read-only) -- + i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions) + i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only + i_bus_ben_o <= (others => '0'); + i_bus_we_o <= '0'; + i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault + i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re; + i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c); + instr_o <= i_bus_rdata_i; + + -- check instruction access address alignment -- + i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension + '1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only + + -- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c -- + pmp_ibus_buffer: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + i_bus_re_buf <= '0'; + elsif rising_edge(clk_i) then + i_bus_re_buf <= i_bus_re; + end if; + end process pmp_ibus_buffer; + + + -- Physical Memory Protection (PMP) ------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- compute address masks (ITERATIVE!!!) -- + pmp_masks: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + pmp.addr_mask <= (others => (others => def_rst_val_c)); + elsif rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles + for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions + pmp.addr_mask(r) <= (others => '0'); + for i in pmp_g_c to data_width_c-1 loop + pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1)); + end loop; -- i + end loop; -- r + end if; + end process pmp_masks; + + + -- address access check -- + pmp_address_check: + for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions + pmp.region_i_addr(r) <= fetch_pc_i and pmp.addr_mask(r); + pmp.region_d_addr(r) <= mar and pmp.addr_mask(r); + pmp.region_base(r) <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r); + -- + pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0'; + pmp.d_match(r) <= '1' when (pmp.region_d_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0'; + end generate; -- r + + + -- check access type and region's permissions -- + pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i) + begin + for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions + if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode + (pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) and -- active entry + (ctrl_i(ctrl_debug_running_c) = '0') then -- disable PMP checks when in debug mode + pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission + pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission + pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission + else + pmp.if_fault(r) <= '0'; + pmp.ld_fault(r) <= '0'; + pmp.st_fault(r) <= '0'; + end if; + end loop; -- r + end process pmp_check_permission; + + + -- final PMP access fault signals -- + if_pmp_fault <= or_reduce_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0'; + ld_pmp_fault <= or_reduce_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0'; + st_pmp_fault <= or_reduce_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0'; + + +end neorv32_cpu_bus_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_control.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_control.vhd new file mode 100644 index 0000000..efea013 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_control.vhd @@ -0,0 +1,2835 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU Control >> # +-- # ********************************************************************************************* # +-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an # +-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction # +-- # words) and an execute engine (responsible for actually executing the instructions), a trap # +-- # handling controller and the RISC-V status and control register set (CSRs) including the # +-- # hardware performance monitor counters. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_control is + generic ( + -- General -- + HW_THREAD_ID : natural; -- hardware thread id (32-bit) + CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address + CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? + -- Extension Options -- + CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64) + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- status input -- + alu_idone_i : in std_ulogic; -- ALU iterative operation done + bus_i_wait_i : in std_ulogic; -- wait for bus + bus_d_wait_i : in std_ulogic; -- wait for bus + excl_state_i : in std_ulogic; -- atomic/exclusive access lock status + -- data input -- + instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction + cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status + alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + -- data output -- + imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate + fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch + curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction) + next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to next instruction) + csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data + -- FPU interface -- + fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags + -- debug mode (halt) request -- + db_halt_req_i : in std_ulogic; + -- interrupts (risc-v compliant) -- + msw_irq_i : in std_ulogic; -- machine software interrupt + mext_irq_i : in std_ulogic; -- machine external interrupt + mtime_irq_i : in std_ulogic; -- machine timer interrupt + -- fast interrupts (custom) -- + firq_i : in std_ulogic_vector(15 downto 0); + -- system time input from MTIME -- + time_i : in std_ulogic_vector(63 downto 0); -- current system time + -- physical memory protection -- + pmp_addr_o : out pmp_addr_if_t; -- addresses + pmp_ctrl_o : out pmp_ctrl_if_t; -- configs + -- bus access exceptions -- + mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register + ma_instr_i : in std_ulogic; -- misaligned instruction address + ma_load_i : in std_ulogic; -- misaligned load data address + ma_store_i : in std_ulogic; -- misaligned store data address + be_instr_i : in std_ulogic; -- bus error on instruction access + be_load_i : in std_ulogic; -- bus error on load data access + be_store_i : in std_ulogic -- bus error on store data access + ); +end neorv32_cpu_control; + +architecture neorv32_cpu_control_rtl of neorv32_cpu_control is + + -- CPU core counter ([m]cycle, [m]instret) width - high/low parts -- + constant cpu_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH < 32), CPU_CNT_WIDTH, 32)); + constant cpu_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH > 32), CPU_CNT_WIDTH-32, 0)); + + -- HPM counter width - high/low parts -- + constant hpm_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH < 32), HPM_CNT_WIDTH, 32)); + constant hpm_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH > 32), HPM_CNT_WIDTH-32, 0)); + + -- instruction fetch engine -- + type fetch_engine_state_t is (IFETCH_REQUEST, IFETCH_ISSUE); + type fetch_engine_t is record + state : fetch_engine_state_t; + state_nxt : fetch_engine_state_t; + state_prev : fetch_engine_state_t; + restart : std_ulogic; + restart_nxt : std_ulogic; + pc : std_ulogic_vector(data_width_c-1 downto 0); + pc_nxt : std_ulogic_vector(data_width_c-1 downto 0); + reset : std_ulogic; + bus_err_ack : std_ulogic; + end record; + signal fetch_engine : fetch_engine_t; + + -- instruction prefetch buffer (FIFO) interface -- + type ipb_t is record + wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data + we : std_ulogic; -- trigger write + free : std_ulogic; -- free entry available? + clear : std_ulogic; -- clear all entries + -- + rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data + re : std_ulogic; -- read enable + avail : std_ulogic; -- data available? + end record; + signal ipb : ipb_t; + + -- pre-decoder -- + signal ci_instr16 : std_ulogic_vector(15 downto 0); + signal ci_instr32 : std_ulogic_vector(31 downto 0); + signal ci_illegal : std_ulogic; + + -- instruction issue engine -- + type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN); + type issue_engine_t is record + state : issue_engine_state_t; + state_nxt : issue_engine_state_t; + align : std_ulogic; + align_nxt : std_ulogic; + buf : std_ulogic_vector(2+15 downto 0); + buf_nxt : std_ulogic_vector(2+15 downto 0); + end record; + signal issue_engine : issue_engine_t; + + -- instruction issue interface -- + type cmd_issue_t is record + data : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction + valid : std_ulogic; -- data word is valid when set + end record; + signal cmd_issue : cmd_issue_t; + + -- instruction decoding helper logic -- + type decode_aux_t is record + is_atomic_lr : std_ulogic; + is_atomic_sc : std_ulogic; + is_float_op : std_ulogic; + sys_env_cmd : std_ulogic_vector(11 downto 0); + is_m_mul : std_ulogic; + is_m_div : std_ulogic; + is_bitmanip_imm : std_ulogic; + is_bitmanip_reg : std_ulogic; + rs1_zero : std_ulogic; + rs2_zero : std_ulogic; + rd_zero : std_ulogic; + end record; + signal decode_aux : decode_aux_t; + + -- instruction execution engine -- + type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP_ENTER, TRAP_EXIT, TRAP_EXECUTE, EXECUTE, ALU_WAIT, + BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS); + type execute_engine_t is record + state : execute_engine_state_t; + state_nxt : execute_engine_state_t; + state_prev : execute_engine_state_t; + -- + i_reg : std_ulogic_vector(31 downto 0); + i_reg_nxt : std_ulogic_vector(31 downto 0); + i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction + -- + is_ci : std_ulogic; -- current instruction is de-compressed instruction + is_ci_nxt : std_ulogic; + is_ici : std_ulogic; -- current instruction is illegal de-compressed instruction + is_ici_nxt : std_ulogic; + -- + branch_taken : std_ulogic; -- branch condition fulfilled + pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction + pc_mux_sel : std_ulogic; -- source select for PC update + pc_we : std_ulogic; -- PC update enabled + next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed + next_pc_inc : std_ulogic_vector(data_width_c-1 downto 0); -- increment to get next PC + last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction + -- + sleep : std_ulogic; -- CPU in sleep mode + sleep_nxt : std_ulogic; + branched : std_ulogic; -- instruction fetch was reset + branched_nxt : std_ulogic; + end record; + signal execute_engine : execute_engine_t; + + -- trap controller -- + type trap_ctrl_t is record + exc_buf : std_ulogic_vector(exception_width_c-1 downto 0); + exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer + irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0); + irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer + exc_ack : std_ulogic; -- acknowledge all exceptions + cause : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR + cause_nxt : std_ulogic_vector(6 downto 0); + db_irq_fire : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer + db_irq_en : std_ulogic; -- set if IRQs are allowed in debug mode + -- + env_start : std_ulogic; -- start trap handler env + env_start_ack : std_ulogic; -- start of trap handler acknowledged + env_end : std_ulogic; -- end trap handler env + -- + instr_be : std_ulogic; -- instruction fetch bus error + instr_ma : std_ulogic; -- instruction fetch misaligned address + instr_il : std_ulogic; -- illegal instruction + env_call : std_ulogic; + break_point : std_ulogic; + end record; + signal trap_ctrl : trap_ctrl_t; + + -- CPU main control bus -- + signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); + + -- fast instruction fetch access -- + signal bus_fast_ir : std_ulogic; + + -- RISC-V control and status registers (CSRs) -- + type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0); + type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0); + type pmp_ctrl_rd_t is array (0 to 63) of std_ulogic_vector(7 downto 0); + type mhpmevent_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0); + type mhpmcnt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0); + type mhpmcnt_nxt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0); + type mhpmcnt_ovfl_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(0 downto 0); + type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(31 downto 0); + type csr_t is record + addr : std_ulogic_vector(11 downto 0); -- csr address + we : std_ulogic; -- csr write enable + we_nxt : std_ulogic; + wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data + rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data + -- + mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W) + mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W) + mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode + -- + mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W) + mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) + mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) + mie_firqe : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) + -- + mip_clr : std_ulogic_vector(15 downto 0); -- clear pending FIRQ + -- + mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode + mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode + mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode + -- + mcountinhibit_cy : std_ulogic; -- mcounterinhibit.cy: enable auto-increment for [m]cycle[h] + mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h] + mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h] + -- + privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode + privilege_rd : std_ulogic_vector(1 downto 0); -- hart's current privilege mode (effective) + priv_m_mode : std_ulogic; -- CPU in M-mode + priv_u_mode : std_ulogic; -- CPU in u-mode + -- + mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W) + mcause : std_ulogic_vector(5 downto 0); -- mcause: machine trap cause (R/W) + mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00 + mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or instruction (R/W) + -- + mhpmevent : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W) + -- + mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W) + -- + mcycle : std_ulogic_vector(31 downto 0); -- mcycle (R/W) + mcycle_nxt : std_ulogic_vector(32 downto 0); + mcycle_ovfl : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow + mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) + minstret : std_ulogic_vector(31 downto 0); -- minstret (R/W) + minstret_nxt : std_ulogic_vector(32 downto 0); + minstret_ovfl : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow + minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) + -- + mhpmcounter : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit + mhpmcounter_nxt : mhpmcnt_nxt_t; + mhpmcounter_ovfl : mhpmcnt_ovfl_t; -- counter low-to-high-word overflow + mhpmcounterh : mhpmcnt_t; -- mhpmcounter*h (R/W) + mhpmcounter_rd : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data + mhpmcounterh_rd : mhpmcnt_rd_t; -- mhpmcounter*h (R/W): actual read data + -- + pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers + pmpcfg_rd : pmp_ctrl_rd_t; -- physical memory protection - actual read data + pmpaddr : pmp_addr_t; -- physical memory protection - address registers + -- + frm : std_ulogic_vector(02 downto 0); -- frm (R/W): FPU rounding mode + fflags : std_ulogic_vector(04 downto 0); -- fflags (R/W): FPU exception flags + -- + dcsr_ebreakm : std_ulogic; -- dcsr.ebreakm (R/W): behavior of ebreak instruction on m-mode + dcsr_ebreaku : std_ulogic; -- dcsr.ebreaku (R/W): behavior of ebreak instruction on u-mode + dcsr_step : std_ulogic; -- dcsr.step (R/W): single-step mode + dcsr_prv : std_ulogic_vector(01 downto 0); -- dcsr.prv (R/W): current privilege level when entering debug mode + dcsr_cause : std_ulogic_vector(02 downto 0); -- dcsr.cause (R/-): why was debug mode entered + dcsr_rd : std_ulogic_vector(data_width_c-1 downto 0); -- dcsr (R/(W)): debug mode control and status register + dpc : std_ulogic_vector(data_width_c-1 downto 0); -- dpc (R/W): debug mode program counter + dscratch0 : std_ulogic_vector(data_width_c-1 downto 0); -- dscratch0 (R/W): debug mode scratch register 0 + end record; + signal csr : csr_t; + + -- debug mode controller -- + type debug_ctrl_state_t is (DEBUG_OFFLINE, DEBUG_PENDING, DEBUG_ONLINE, DEBUG_EXIT); + type debug_ctrl_t is record + state : debug_ctrl_state_t; + -- decoded state -- + running : std_ulogic; -- debug mode active + pending : std_ulogic; -- waiting to start debug mode + -- entering triggers -- + trig_break : std_ulogic; -- ebreak instruction + trig_halt : std_ulogic; -- external request + trig_step : std_ulogic; -- single-stepping mode + -- leave debug mode -- + dret : std_ulogic; -- executed DRET instruction + -- misc -- + ext_halt_req : std_ulogic; + end record; + signal debug_ctrl : debug_ctrl_t; + + -- (hpm) counter events -- + signal cnt_event : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0); + signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); + + -- illegal instruction check -- + signal illegal_opcode_lsbs : std_ulogic; -- opcode != rv32 + signal illegal_instruction : std_ulogic; + signal illegal_register : std_ulogic; -- illegal register (>x15) - E-extension + signal illegal_compressed : std_ulogic; -- illegal compressed instruction - C-extension + + -- access (privilege) check -- + signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights) + +begin + +-- **************************************************************************************************************************** +-- Instruction Fetch (always fetch 32-bit-aligned 32-bit chunks of data) +-- **************************************************************************************************************************** + + -- Fetch Engine FSM Sync ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + fetch_engine_fsm_sync: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + fetch_engine.state <= IFETCH_REQUEST; + fetch_engine.state_prev <= IFETCH_REQUEST; + fetch_engine.restart <= '1'; + fetch_engine.pc <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + fetch_engine.state <= fetch_engine.state_nxt; + fetch_engine.state_prev <= fetch_engine.state; + fetch_engine.restart <= fetch_engine.restart_nxt; + if (fetch_engine.restart = '1') then + fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC + else + fetch_engine.pc <= fetch_engine.pc_nxt; + end if; + end if; + end process fetch_engine_fsm_sync; + + -- PC output -- + fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned + + + -- Fetch Engine FSM Comb ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i) + begin + -- arbiter defaults -- + bus_fast_ir <= '0'; + fetch_engine.state_nxt <= fetch_engine.state; + fetch_engine.pc_nxt <= fetch_engine.pc; + fetch_engine.bus_err_ack <= '0'; + fetch_engine.restart_nxt <= fetch_engine.restart or fetch_engine.reset; + + -- instruction prefetch buffer interface -- + ipb.we <= '0'; + ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word + ipb.clear <= fetch_engine.restart; + + -- state machine -- + case fetch_engine.state is + + when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word + -- ------------------------------------------------------------ + if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request? + bus_fast_ir <= '1'; -- fast instruction fetch request + fetch_engine.state_nxt <= IFETCH_ISSUE; + end if; + if (fetch_engine.restart = '1') then -- reset request? + fetch_engine.restart_nxt <= '0'; + end if; + + when IFETCH_ISSUE => -- store instruction data to prefetch buffer + -- ------------------------------------------------------------ + fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors + if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response + fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); + ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset + if (fetch_engine.restart = '1') then -- reset request? + fetch_engine.restart_nxt <= '0'; + end if; + fetch_engine.state_nxt <= IFETCH_REQUEST; + end if; + + when others => -- undefined + -- ------------------------------------------------------------ + fetch_engine.state_nxt <= IFETCH_REQUEST; + + end case; + end process fetch_engine_fsm_comb; + + +-- **************************************************************************************************************************** +-- Instruction Prefetch Buffer +-- **************************************************************************************************************************** + + -- Instruction Prefetch Buffer (FIFO) ----------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + instr_prefetch_buffer: neorv32_fifo + generic map ( + FIFO_DEPTH => CPU_IPB_ENTRIES, -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH => ipb.wdata'length, -- size of data elements in fifo + FIFO_RSYNC => false, -- we NEED to read data asynchronously + FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control) + ) + port map ( + -- control -- + clk_i => clk_i, -- clock, rising edge + rstn_i => '1', -- async reset, low-active + clear_i => ipb.clear, -- sync reset, high-active + level_o => open, + half_o => open, + -- write port -- + wdata_i => ipb.wdata, -- write data + we_i => ipb.we, -- write enable + free_o => ipb.free, -- at least one entry is free when set + -- read port -- + re_i => ipb.re, -- read enable + rdata_o => ipb.rdata, -- read data + avail_o => ipb.avail -- data available when set + ); + + +-- **************************************************************************************************************************** +-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction) +-- **************************************************************************************************************************** + + -- Issue Engine FSM Sync ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + issue_engine_fsm_sync: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + issue_engine.state <= ISSUE_ACTIVE; + issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary + issue_engine.buf <= (others => '0'); + elsif rising_edge(clk_i) then + if (ipb.clear = '1') then + if (CPU_EXTENSION_RISCV_C = true) and (execute_engine.pc(1) = '1') then -- branch to unaligned address? + issue_engine.state <= ISSUE_REALIGN; + issue_engine.align <= '1'; -- aligned on 16-bit boundary + else + issue_engine.state <= issue_engine.state_nxt; + issue_engine.align <= '0'; -- always aligned on 32-bit boundaries + end if; + else + issue_engine.state <= issue_engine.state_nxt; + issue_engine.align <= issue_engine.align_nxt; + end if; + issue_engine.buf <= issue_engine.buf_nxt; + end if; + end process issue_engine_fsm_sync; + + + -- Issue Engine FSM Comb ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32) + begin + -- arbiter defaults -- + issue_engine.state_nxt <= issue_engine.state; + issue_engine.align_nxt <= issue_engine.align; + issue_engine.buf_nxt <= issue_engine.buf; + + -- instruction prefetch buffer interface defaults -- + ipb.re <= '0'; + + -- instruction issue interface defaults -- + -- cmd_issue.data = & & & <32-bit_instruction_word> + cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); + cmd_issue.valid <= '0'; + + -- state machine -- + case issue_engine.state is + + when ISSUE_ACTIVE => -- issue instruction if available + -- ------------------------------------------------------------ + if (ipb.avail = '1') then -- instructions available? + + if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word + if (execute_engine.state = DISPATCH) then -- ready to issue new command? + cmd_issue.valid <= '1'; + issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction + if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned" + ipb.re <= '1'; + cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); + else -- compressed + ipb.re <= '1'; + cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; + issue_engine.align_nxt <= '1'; + end if; + end if; + + else -- begin check in HIGH instruction half-word + if (execute_engine.state = DISPATCH) then -- ready to issue new command? + cmd_issue.valid <= '1'; + issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction + if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned" + ipb.re <= '1'; + cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0)); + else -- compressed + -- do not read from ipb here! + cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; + issue_engine.align_nxt <= '0'; + end if; + end if; + end if; + end if; + + when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address + -- ------------------------------------------------------------ + issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); + if (ipb.avail = '1') then -- instructions available? + ipb.re <= '1'; + issue_engine.state_nxt <= ISSUE_ACTIVE; + end if; + + when others => -- undefined + -- ------------------------------------------------------------ + issue_engine.state_nxt <= ISSUE_ACTIVE; + + end case; + end process issue_engine_fsm_comb; + + -- 16-bit instructions: half-word select -- + ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0); + + + -- Compressed Instructions Recoding ------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_decompressor_inst_true: + if (CPU_EXTENSION_RISCV_C = true) generate + neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor + port map ( + -- instruction input -- + ci_instr16_i => ci_instr16, -- compressed instruction input + -- instruction output -- + ci_illegal_o => ci_illegal, -- is an illegal compressed instruction + ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction + ); + end generate; + + neorv32_cpu_decompressor_inst_false: + if (CPU_EXTENSION_RISCV_C = false) generate + ci_instr32 <= (others => '0'); + ci_illegal <= '0'; + end generate; + + +-- **************************************************************************************************************************** +-- Instruction Execution +-- **************************************************************************************************************************** + + -- Immediate Generator -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imm_gen: process(rstn_i, clk_i) + variable opcode_v : std_ulogic_vector(6 downto 0); + begin + if (rstn_i = '0') then + imm_o <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + -- default: I-immediate: ALU-immediate, loads, jump-and-link with registers + imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension + imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); + imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21); + imm_o(00) <= execute_engine.i_reg(20); + + opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; + case opcode_v is -- save some bits here, the two LSBs are always "11" for rv32 + when opcode_store_c => -- S-immediate: store + imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension + imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); + imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08); + imm_o(00) <= execute_engine.i_reg(07); + when opcode_branch_c => -- B-immediate: conditional branches + imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension + imm_o(11) <= execute_engine.i_reg(07); + imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); + imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08); + imm_o(00) <= '0'; + when opcode_lui_c | opcode_auipc_c => -- U-immediate: lui, auipc + imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20); + imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12); + imm_o(11 downto 00) <= (others => '0'); + when opcode_jal_c => -- J-immediate: unconditional jumps + imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension + imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12); + imm_o(11) <= execute_engine.i_reg(20); + imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); + imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21); + imm_o(00) <= '0'; + when opcode_atomic_c => -- atomic memory access and everything else + if (CPU_EXTENSION_RISCV_A = true) then + imm_o <= (others => '0'); -- effective address is addr = reg + 0 = reg + else + NULL; -- use default + end if; + when others => -- I-immediate + NULL; -- use default + end case; + end if; + end process imm_gen; + + + -- Branch Condition Check ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + branch_check: process(execute_engine.i_reg, cmp_i) + begin + case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is + when funct3_beq_c => -- branch if equal + execute_engine.branch_taken <= cmp_i(cmp_equal_c); + when funct3_bne_c => -- branch if not equal + execute_engine.branch_taken <= not cmp_i(cmp_equal_c); + when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned) + execute_engine.branch_taken <= cmp_i(cmp_less_c); + when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned) + execute_engine.branch_taken <= not cmp_i(cmp_less_c); + when others => -- invalid + execute_engine.branch_taken <= '0'; + end case; + end process branch_check; + + + -- Execute Engine FSM Sync ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + execute_engine_fsm_sync: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + -- registers that DO require a specific reset state -- + execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned! + execute_engine.state <= SYS_WAIT; + execute_engine.sleep <= '0'; + execute_engine.branched <= '1'; -- reset is a branch from "somewhere" + -- no dedicated RESET required -- + execute_engine.state_prev <= SYS_WAIT; -- actual reset value is not relevant + execute_engine.i_reg <= (others => def_rst_val_c); + execute_engine.is_ci <= def_rst_val_c; + execute_engine.is_ici <= def_rst_val_c; + execute_engine.last_pc <= (others => def_rst_val_c); + execute_engine.i_reg_last <= (others => def_rst_val_c); + execute_engine.next_pc <= (others => def_rst_val_c); + ctrl <= (others => def_rst_val_c); + ctrl(ctrl_bus_rd_c) <= '0'; + ctrl(ctrl_bus_wr_c) <= '0'; + elsif rising_edge(clk_i) then + -- PC update -- + if (execute_engine.pc_we = '1') then + if (execute_engine.pc_mux_sel = '0') then + execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment OR trap enter/exit + else + execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch + end if; + end if; + + execute_engine.state <= execute_engine.state_nxt; + execute_engine.state_prev <= execute_engine.state; + execute_engine.sleep <= execute_engine.sleep_nxt; + execute_engine.branched <= execute_engine.branched_nxt; + execute_engine.i_reg <= execute_engine.i_reg_nxt; + execute_engine.is_ci <= execute_engine.is_ci_nxt; + execute_engine.is_ici <= execute_engine.is_ici_nxt; + + -- PC & IR of "last executed" instruction for trap handling -- + if (execute_engine.state = EXECUTE) then + execute_engine.last_pc <= execute_engine.pc; + execute_engine.i_reg_last <= execute_engine.i_reg; + end if; + + -- next PC -- + case execute_engine.state is + when TRAP_ENTER => -- ENTERING trap environment + if (CPU_EXTENSION_RISCV_DEBUG = false) then -- normal trapping + execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter + else -- DEBUG MODE enabled + if (trap_ctrl.cause(5) = '1') then -- trap cause: debug mode (re-)entry + execute_engine.next_pc <= CPU_DEBUG_ADDR; -- debug mode enter; start at "parking loop" + elsif (debug_ctrl.running = '1') then -- any other exception INSIDE debug mode + execute_engine.next_pc <= std_ulogic_vector(unsigned(CPU_DEBUG_ADDR) + 4); -- execute at "parking loop" + else -- normal trapping + execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter + end if; + end if; + when TRAP_EXIT => -- LEAVING trap environment + if (CPU_EXTENSION_RISCV_DEBUG = false) or (debug_ctrl.running = '0') then -- normal end of trap + execute_engine.next_pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit + else -- DEBUG MODE exiting + execute_engine.next_pc <= csr.dpc(data_width_c-1 downto 1) & '0'; -- debug mode exit + end if; + when EXECUTE => -- NORMAL pc increment + execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + unsigned(execute_engine.next_pc_inc)); -- next linear PC + when others => + NULL; + end case; + + -- main control bus -- + ctrl <= ctrl_nxt; + end if; + end process execute_engine_fsm_sync; + + + -- PC increment for next linear instruction (+2 for compressed instr., +4 otherwise) -- + execute_engine.next_pc_inc <= x"00000004" when ((execute_engine.is_ci = '0') or (CPU_EXTENSION_RISCV_C = false)) else x"00000002"; + + -- PC output -- + curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- current PC for ALU ops + next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- next PC for ALU ops + + -- CSR access address -- + csr.addr <= execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c); + + + -- CPU Control Bus Output ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine, csr, debug_ctrl) + begin + -- signals from execute engine -- + ctrl_o <= ctrl; + -- prevent commits if illegal instruction -- + ctrl_o(ctrl_rf_wb_en_c) <= ctrl(ctrl_rf_wb_en_c) and (not trap_ctrl.exc_buf(exception_iillegal_c)); + ctrl_o(ctrl_bus_rd_c) <= ctrl(ctrl_bus_rd_c) and (not trap_ctrl.exc_buf(exception_iillegal_c)); + ctrl_o(ctrl_bus_wr_c) <= ctrl(ctrl_bus_wr_c) and (not trap_ctrl.exc_buf(exception_iillegal_c)); + -- current privilege level -- + ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege_rd; + -- register addresses -- + ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c); + ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c); + ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c); + -- fast bus access requests -- + ctrl_o(ctrl_bus_if_c) <= bus_fast_ir; + -- bus error control -- + ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; -- instruction fetch bus access error ACK + ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack; -- data access bus error access ACK + -- memory access size / sign -- + ctrl_o(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) + ctrl_o(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size + -- alu.shifter -- + ctrl_o(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right) + ctrl_o(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift + -- instruction's function blocks (for co-processors) -- + ctrl_o(ctrl_ir_opcode7_6_c downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c); + ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c); + ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); + -- cpu status -- + ctrl_o(ctrl_sleep_c) <= execute_engine.sleep; -- cpu is in sleep mode + ctrl_o(ctrl_trap_c) <= trap_ctrl.env_start_ack; -- cpu is starting a trap handler + ctrl_o(ctrl_debug_running_c) <= debug_ctrl.running; -- cpu is currently in debug mode + -- FPU rounding mode -- + ctrl_o(ctrl_alu_frm2_c downto ctrl_alu_frm0_c) <= csr.frm; + end process ctrl_output; + + + -- Decoding Helper Logic ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + decode_helper: process(execute_engine) + variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0); + begin + -- defaults -- + decode_aux.is_atomic_lr <= '0'; + decode_aux.is_atomic_sc <= '0'; + decode_aux.is_float_op <= '0'; + decode_aux.is_m_mul <= '0'; + decode_aux.is_m_div <= '0'; + decode_aux.is_bitmanip_imm <= '0'; + decode_aux.is_bitmanip_reg <= '0'; + decode_aux.rs1_zero <= '0'; + decode_aux.rs2_zero <= '0'; + decode_aux.rd_zero <= '0'; + + -- is atomic load-reservate/store-conditional? -- + if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode + decode_aux.is_atomic_lr <= not execute_engine.i_reg(instr_funct5_lsb_c); + decode_aux.is_atomic_sc <= execute_engine.i_reg(instr_funct5_lsb_c); + end if; + + -- is BITMANIP instruction? -- + -- pretty complex as we have to extract this from the ALU/ALUI instruction space -- + -- immediate operation -- + if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001") and + ( + (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00000") or -- CLZ + (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00001") or -- CTZ + (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00010") or -- CPOP + (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00100") or -- SEXT.B + (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101") -- SEXT.H + ) + ) or + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00111")) or -- ORCB + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "11000")) then -- REV8 + decode_aux.is_bitmanip_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all? + end if; + -- register operation -- + if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U] + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- ZEXTH + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and + ( + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") -- XORN + ) + ) or + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010000") and + ( + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") or -- SH1ADD + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") or -- SH2ADD + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") -- SH3ADD + ) + ) then + decode_aux.is_bitmanip_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all? + end if; + + -- floating-point operations (Zfinx) -- + if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+3) = "0000")) or -- FADD.S / FSUB.S + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00010")) or -- FMUL.S + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- FCLASS.S + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FSGNJ[N/X].S + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_msb_c-1) = "00")) or -- FMIN.S / FMAX.S + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) or -- FCVT.S.W* + ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S + decode_aux.is_float_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all? + end if; + + -- system/environment instructions -- + sys_env_cmd_mask_v := funct12_ecall_c or funct12_ebreak_c or funct12_mret_c or funct12_wfi_c or funct12_dret_c; -- sum-up set bits + decode_aux.sys_env_cmd <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) and sys_env_cmd_mask_v; -- set unused bits to always-zero + + -- integer MUL (M/Zmmul) / DIV (M) operation -- + if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and + (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then + decode_aux.is_m_mul <= (not execute_engine.i_reg(instr_funct3_msb_c)) and (bool_to_ulogic_f(CPU_EXTENSION_RISCV_M) or bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul)); + decode_aux.is_m_div <= execute_engine.i_reg(instr_funct3_msb_c) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); + end if; + + -- register address checks -- + decode_aux.rs1_zero <= not or_reduce_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); + decode_aux.rs2_zero <= not or_reduce_f(execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c)); + decode_aux.rd_zero <= not or_reduce_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); + end process decode_helper; + + + -- Execute Engine FSM Comb ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + execute_engine_fsm_comb: process(execute_engine, debug_ctrl, trap_ctrl, decode_aux, fetch_engine, cmd_issue, + csr, ctrl, alu_idone_i, bus_d_wait_i, excl_state_i) + variable opcode_v : std_ulogic_vector(6 downto 0); + begin + -- arbiter defaults -- + execute_engine.state_nxt <= execute_engine.state; + execute_engine.i_reg_nxt <= execute_engine.i_reg; + execute_engine.is_ci_nxt <= execute_engine.is_ci; + execute_engine.is_ici_nxt <= '0'; + execute_engine.sleep_nxt <= execute_engine.sleep; + execute_engine.branched_nxt <= execute_engine.branched; + -- + execute_engine.pc_mux_sel <= '0'; + execute_engine.pc_we <= '0'; + + -- instruction dispatch -- + fetch_engine.reset <= '0'; + + -- trap environment control -- + trap_ctrl.env_start_ack <= '0'; + trap_ctrl.env_end <= '0'; + + -- leave debug mode -- + debug_ctrl.dret <= '0'; + + -- exception trigger -- + trap_ctrl.instr_be <= '0'; + trap_ctrl.instr_ma <= '0'; + trap_ctrl.env_call <= '0'; + trap_ctrl.break_point <= '0'; + + -- CSR access -- + csr.we_nxt <= '0'; + + -- CONTROL DEFAULTS -- + ctrl_nxt <= (others => '0'); -- default: all off + -- ALU main control -- + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; -- default ALU operation: ADD + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_core_c; -- default ALU operation: ADD + -- ALU sign control -- + if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops + ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU) + else -- branches + ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU) + end if; + -- atomic store-conditional instruction (evaluate lock status) -- + ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_atomic_sc; + + + -- state machine -- + case execute_engine.state is + + when SYS_WAIT => -- System delay cycle (to let side effects kick in) + -- ------------------------------------------------------------ + execute_engine.state_nxt <= DISPATCH; + + + when DISPATCH => -- Get new command from instruction issue engine + -- ------------------------------------------------------------ + -- PC update -- + execute_engine.pc_mux_sel <= '0'; -- linear next PC + -- IR update -- + execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate a de-compressed instruction + execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0); + -- + if (cmd_issue.valid = '1') then -- instruction available? + -- PC update -- + execute_engine.branched_nxt <= '0'; + execute_engine.pc_we <= not execute_engine.branched; -- update PC with linear next_pc if there was no actual branch + -- IR update - exceptions -- + trap_ctrl.instr_ma <= cmd_issue.data(33) and (not bool_to_ulogic_f(CPU_EXTENSION_RISCV_C)); -- misaligned instruction fetch address, if C disabled + trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instruction fetch + execute_engine.is_ici_nxt <= cmd_issue.data(35); -- invalid decompressed instruction + -- any reason to go to trap state? -- + if (execute_engine.sleep = '1') or -- enter sleep state + (trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (illegal instruction) + (trap_ctrl.env_start = '1') or -- pending trap (IRQ or exception) + ((cmd_issue.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address, if C disabled + (cmd_issue.data(34) = '1') then -- bus access fault during instruction fetch + execute_engine.state_nxt <= TRAP_ENTER; + else + execute_engine.state_nxt <= EXECUTE; + end if; + end if; + + + when TRAP_ENTER => -- Start trap environment - get xTVEC, stay here for sleep mode + -- ------------------------------------------------------------ + if (trap_ctrl.env_start = '1') then -- trap triggered? + trap_ctrl.env_start_ack <= '1'; + execute_engine.state_nxt <= TRAP_EXECUTE; + end if; + + + when TRAP_EXIT => -- Return from trap environment - get xEPC + -- ------------------------------------------------------------ + trap_ctrl.env_end <= '1'; + execute_engine.state_nxt <= TRAP_EXECUTE; + + + when TRAP_EXECUTE => -- Process trap environment -> jump to xTVEC / return from trap environment -> jump to xEPC + -- ------------------------------------------------------------ + execute_engine.pc_mux_sel <= '0'; -- next_PC + fetch_engine.reset <= '1'; + execute_engine.pc_we <= '1'; + execute_engine.sleep_nxt <= '0'; -- disable sleep mode + execute_engine.state_nxt <= SYS_WAIT; + + + when EXECUTE => -- Decode and execute instruction (control has to be here for exactly 1 cycle in any case!) + -- ------------------------------------------------------------ + opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32 + case opcode_v is + + when opcode_alu_c | opcode_alui_c => -- (register/immediate) ALU operation + -- ------------------------------------------------------------ + ctrl_nxt(ctrl_alu_opb_mux_c) <= not execute_engine.i_reg(instr_opcode_msb_c-1); -- use IMM as ALU.OPB for immediate operations + + -- ALU core operation -- + case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding) + when funct3_subadd_c => -- ADD(I)/SUB + if ((execute_engine.i_reg(instr_opcode_msb_c-1) = '1') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) then -- not an immediate op and funct7.6 set => SUB + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_sub_c; + else + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; + end if; + when funct3_slt_c | funct3_sltu_c => -- SLT(I), SLTU(I) + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_slt_c; + when funct3_xor_c => -- XOR(I) + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_xor_c; + when funct3_or_c => -- OR(I) + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_or_c; + when others => -- AND(I), multi-cycle / co-processor operations + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c; + end case; + + -- Check if single-cycle or multi-cycle (co-processor) operation -- + -- co-processor MULDIV operation? -- + if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV + ((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL + ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; + execute_engine.state_nxt <= ALU_WAIT; + -- co-processor BIT-MANIPULATION operation? -- + elsif (CPU_EXTENSION_RISCV_B = true) and + (((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- register operation + ((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation + ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; + execute_engine.state_nxt <= ALU_WAIT; + -- co-processor SHIFT operation? -- + elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then + ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- use SHIFTER CP (only relevant for shift operations) + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; + execute_engine.state_nxt <= ALU_WAIT; + -- ALU core operations (single-cycle) -- + else + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_core_c; + ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back + execute_engine.state_nxt <= DISPATCH; + end if; + + + when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC + -- ------------------------------------------------------------ + ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only) + ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB + if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_movb_c; -- actual ALU operation = MOVB + else -- AUIPC + ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; -- actual ALU operation = ADD + end if; + ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back + execute_engine.state_nxt <= DISPATCH; + + + when opcode_load_c | opcode_store_c | opcode_atomic_c => -- load/store / atomic memory access + -- ------------------------------------------------------------ + ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB + ctrl_nxt(ctrl_bus_mo_we_c) <= '1'; -- write to MAR and MDO (MDO only relevant for store) + execute_engine.state_nxt <= LOADSTORE_0; + + + when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register) + -- ------------------------------------------------------------ + if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR + ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base) + else -- JAL + ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base) + end if; + ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset) + execute_engine.state_nxt <= BRANCH; + + + when opcode_fence_c => -- fence operations + -- ------------------------------------------------------------ + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE + ctrl_nxt(ctrl_bus_fence_c) <= '1'; + execute_engine.state_nxt <= SYS_WAIT; + elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I + ctrl_nxt(ctrl_bus_fencei_c) <= '1'; + execute_engine.branched_nxt <= '1'; -- this is an actual branch + execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC) + else -- illegal fence instruction + execute_engine.state_nxt <= SYS_WAIT; + end if; + + + when opcode_syscsr_c => -- system/csr access + -- ------------------------------------------------------------ + if (CPU_EXTENSION_RISCV_Zicsr = true) then + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment + execute_engine.state_nxt <= SYS_ENV; + else -- CSR access + execute_engine.state_nxt <= CSR_ACCESS; + end if; + else + execute_engine.state_nxt <= SYS_WAIT; + end if; + + + when opcode_fop_c => -- floating-point operations + -- ------------------------------------------------------------ + if (CPU_EXTENSION_RISCV_Zfinx = true) then + ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; + execute_engine.state_nxt <= ALU_WAIT; + else + execute_engine.state_nxt <= SYS_WAIT; + end if; + + + when others => -- illegal opcode + -- ------------------------------------------------------------ + execute_engine.state_nxt <= SYS_WAIT; + + end case; + + + when SYS_ENV => -- system environment operation - execution + -- ------------------------------------------------------------ + execute_engine.state_nxt <= SYS_WAIT; -- default + if (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction + case decode_aux.sys_env_cmd is -- use a simplified input here (with hardwired zeros) + when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ECALL + when funct12_ebreak_c => trap_ctrl.break_point <= '1'; -- EBREAK + when funct12_mret_c => execute_engine.state_nxt <= TRAP_EXIT; -- MRET + when funct12_dret_c => -- DRET + if (CPU_EXTENSION_RISCV_DEBUG = true) then + execute_engine.state_nxt <= TRAP_EXIT; + debug_ctrl.dret <= '1'; + else + NULL; -- executed as NOP (and raise illegal instruction exception) + end if; + when funct12_wfi_c => -- WFI + if (CPU_EXTENSION_RISCV_DEBUG = true) and + ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- act as NOP when in debug-mode or during single-stepping + NULL; -- executed as NOP + else + execute_engine.sleep_nxt <= '1'; -- go to sleep mode + end if; + when others => NULL; -- undefined / execute as NOP + end case; + end if; + + + when CSR_ACCESS => -- read & write status and control register (CSR) + -- ------------------------------------------------------------ + -- CSR write access -- + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then -- CSRRW(I) + csr.we_nxt <= '1'; -- always write CSR + else -- CSRRS(I) / CSRRC(I) [invalid CSR instruction are already checked by the illegal instruction logic] + csr.we_nxt <= not decode_aux.rs1_zero; -- write CSR if rs1/imm is not zero + end if; + -- register file write back -- + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_csrr_c; + ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back + execute_engine.state_nxt <= DISPATCH; + + + when ALU_WAIT => -- wait for multi-cycle ALU operation (co-processor) to finish + -- ------------------------------------------------------------ + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c; + if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then -- completed or exception + ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back + execute_engine.state_nxt <= DISPATCH; + end if; + + + when BRANCH => -- update PC for taken branches and jumps + -- ------------------------------------------------------------ + -- get and store return address (only relevant for jump-and-link operations) -- + ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_nxpc_c; -- next PC + ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?) + -- destination address -- + execute_engine.pc_mux_sel <= '1'; -- PC <= alu.add = branch/jump destination + if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch + -- no need to check for illegal instructions here; the branch condition evaluation circuit will not set "branch_taken" if funct3 is invalid + execute_engine.pc_we <= '1'; -- update PC + execute_engine.branched_nxt <= '1'; -- this is an actual branch + fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC + execute_engine.state_nxt <= SYS_WAIT; + else + execute_engine.state_nxt <= DISPATCH; + end if; + + + when LOADSTORE_0 => -- trigger memory request + -- ------------------------------------------------------------ + ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_atomic_lr; -- atomic.LR: set lock + if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') then -- normal load or atomic load-reservate + ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request + else -- store + if (decode_aux.is_atomic_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request + ctrl_nxt(ctrl_bus_wr_c) <= '1'; + else -- evaluate lock state + ctrl_nxt(ctrl_bus_wr_c) <= excl_state_i; -- write request if lock is still ok + end if; + end if; + execute_engine.state_nxt <= LOADSTORE_1; + + + when LOADSTORE_1 => -- memory access latency + -- ------------------------------------------------------------ + ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for LOADs) + execute_engine.state_nxt <= LOADSTORE_2; + + + when LOADSTORE_2 => -- wait for bus transaction to finish + -- ------------------------------------------------------------ + ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load (and SC.W) operations) + ctrl_nxt(ctrl_rf_in_mux_c) <= '1'; -- RF input = memory input (only relevant for LOADs) + -- wait for memory response -- + if (trap_ctrl.env_start = '1') and (trap_ctrl.cause(6 downto 5) = "00") then -- abort if SYNC EXCEPTION (from bus or illegal cmd) / no IRQs and NOT DEBUG-MODE-related + execute_engine.state_nxt <= DISPATCH; + elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction + -- data write-back -- + if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load + (decode_aux.is_atomic_lr = '1') or -- atomic load-reservate + (decode_aux.is_atomic_sc = '1') then -- atomic store-conditional + ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; + end if; + -- remove atomic lock if this is NOT the LR.W instruction used to SET the lock -- + if (decode_aux.is_atomic_lr = '0') then -- execute and evaluate atomic store-conditional + ctrl_nxt(ctrl_bus_de_lock_c) <= '1'; + end if; + execute_engine.state_nxt <= DISPATCH; + end if; + + + when others => -- undefined + -- ------------------------------------------------------------ + execute_engine.state_nxt <= SYS_WAIT; + + end case; + end process execute_engine_fsm_comb; + + +-- **************************************************************************************************************************** +-- Invalid Instruction / CSR access check +-- **************************************************************************************************************************** + + -- CSR Access Check ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + csr_access_check: process(execute_engine.i_reg, decode_aux, csr, debug_ctrl) + variable csr_wacc_v : std_ulogic; -- actual CSR write +-- variable csr_racc_v : std_ulogic; -- actual CSR read + begin + -- is this CSR instruction really going to write to a CSR? -- + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then + csr_wacc_v := '1'; -- always write CSR +-- csr_racc_v := or_reduce_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read if rd != 0 + else -- clear/set + csr_wacc_v := not decode_aux.rs1_zero; -- write if rs1/uimm5 != 0 +-- csr_racc_v := '1'; -- always read CSR + end if; + + -- check CSR access -- + case csr.addr is + + -- floating-point CSRs -- + when csr_fflags_c | csr_frm_c | csr_fcsr_c => + csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- full access for everyone if FPU implemented + + -- machine trap setup/handling & counters -- + when csr_mstatus_c | csr_mstatush_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mip_c | csr_mtval_c | + csr_mcycle_c | csr_mcycleh_c | csr_minstret_c | csr_minstreth_c | csr_mcountinhibit_c => + -- NOTE: MISA and MTVAL are read-only in the NEORV32 but we do not cause an exception here for compatibility. + -- Machine-level code should read-back those CSRs after writing them to realize they are read-only. + csr_acc_valid <= csr.priv_m_mode; -- M-mode only + + -- machine information registers, read-only -- + when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c => + csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only + + -- user-mode registers -- + when csr_mcounteren_c | csr_menvcfg_c | csr_menvcfgh_c => + csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); + + -- physical memory protection (PMP) -- + when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c | -- address + csr_pmpaddr8_c | csr_pmpaddr9_c | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c | + csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c | + csr_pmpaddr24_c | csr_pmpaddr25_c | csr_pmpaddr26_c | csr_pmpaddr27_c | csr_pmpaddr28_c | csr_pmpaddr29_c | csr_pmpaddr30_c | csr_pmpaddr31_c | + csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c | + csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c | + csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c | + csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c | + csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c | -- configuration + csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c => + csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- M-mode only + + -- hardware performance monitors (HPM) -- + when csr_mhpmcounter3_c | csr_mhpmcounter4_c | csr_mhpmcounter5_c | csr_mhpmcounter6_c | csr_mhpmcounter7_c | csr_mhpmcounter8_c | -- counter LOW + csr_mhpmcounter9_c | csr_mhpmcounter10_c | csr_mhpmcounter11_c | csr_mhpmcounter12_c | csr_mhpmcounter13_c | csr_mhpmcounter14_c | + csr_mhpmcounter15_c | csr_mhpmcounter16_c | csr_mhpmcounter17_c | csr_mhpmcounter18_c | csr_mhpmcounter19_c | csr_mhpmcounter20_c | + csr_mhpmcounter21_c | csr_mhpmcounter22_c | csr_mhpmcounter23_c | csr_mhpmcounter24_c | csr_mhpmcounter25_c | csr_mhpmcounter26_c | + csr_mhpmcounter27_c | csr_mhpmcounter28_c | csr_mhpmcounter29_c | csr_mhpmcounter30_c | csr_mhpmcounter31_c | + csr_mhpmcounter3h_c | csr_mhpmcounter4h_c | csr_mhpmcounter5h_c | csr_mhpmcounter6h_c | csr_mhpmcounter7h_c | csr_mhpmcounter8h_c | -- counter HIGH + csr_mhpmcounter9h_c | csr_mhpmcounter10h_c | csr_mhpmcounter11h_c | csr_mhpmcounter12h_c | csr_mhpmcounter13h_c | csr_mhpmcounter14h_c | + csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c | + csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c | + csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c | + csr_mhpmevent3_c | csr_mhpmevent4_c | csr_mhpmevent5_c | csr_mhpmevent6_c | csr_mhpmevent7_c | csr_mhpmevent8_c | -- event configuration + csr_mhpmevent9_c | csr_mhpmevent10_c | csr_mhpmevent11_c | csr_mhpmevent12_c | csr_mhpmevent13_c | csr_mhpmevent14_c | + csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c | + csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c | + csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c => + csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- M-mode only + + -- user-level counters/timers (read-only) -- + when csr_cycle_c | csr_cycleh_c | csr_instret_c | csr_instreth_c | csr_time_c | csr_timeh_c => + case csr.addr(1 downto 0) is + when "00" => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- cyle[h]: M-mode, U-mode if authorized, implemented at all, read-only + when "01" => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- time[h]: M-mode, U-mode if authorized, implemented at all, read-only + when "10" => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- instret[h]: M-mode, U-mode if authorized, implemented at all read-only + when others => csr_acc_valid <= '0'; + end case; + + -- debug mode CSRs -- + when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c => + csr_acc_valid <= debug_ctrl.running and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- access only in debug-mode + + -- undefined / not implemented -- + when others => + csr_acc_valid <= '0'; -- invalid access + end case; + end process csr_access_check; + + + -- Illegal Instruction Check -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + illegal_instruction_check: process(execute_engine, decode_aux, csr, csr_acc_valid, debug_ctrl) + variable opcode_v : std_ulogic_vector(6 downto 0); + begin + -- illegal instructions are checked in the EXECUTE state + -- the execute engine should not commit any illegal instruction + if (execute_engine.state = EXECUTE) then + -- defaults -- + illegal_instruction <= '0'; + illegal_register <= '0'; + + -- check opcode for rv32 -- + if (execute_engine.i_reg(instr_opcode_lsb_c+1 downto instr_opcode_lsb_c) = "11") then + illegal_opcode_lsbs <= '0'; + else + illegal_opcode_lsbs <= '1'; + end if; + + -- check for illegal compressed instruction -- + if (CPU_EXTENSION_RISCV_C = true) then + illegal_compressed <= execute_engine.is_ici; + else + illegal_compressed <= '0'; + end if; + + -- check instructions -- + opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32 + case opcode_v is + + when opcode_lui_c | opcode_auipc_c | opcode_jal_c => -- check sufficient LUI, UIPC, JAL (only check actual OPCODE) + -- ------------------------------------------------------------ + illegal_instruction <= '0'; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and execute_engine.i_reg(instr_rd_msb_c); + + when opcode_alu_c => -- check ALU.funct3 & ALU.funct7 + -- ------------------------------------------------------------ + if (((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and + (execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')) or + (((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c)) and + (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) then -- valid base ALUI instruction? + illegal_instruction <= '0'; + elsif ((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = false)) and (decode_aux.is_m_mul = '1') then -- valid MUL instruction? + illegal_instruction <= '0'; + elsif (CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1') then -- valid DIV instruction? + illegal_instruction <= '0'; + elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_reg = '1') then -- valid BITMANIP instruction? + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c)); + + when opcode_alui_c => -- check ALUI.funct7 + -- ------------------------------------------------------------ + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c) or + ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and -- shift logical left + (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) or + ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and -- shift right + ((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0'))) then -- valid base ALUI instruction? + illegal_instruction <= '0'; + elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_imm = '1') then -- valid BITMANIP immediate instruction? + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); + + when opcode_load_c => -- check LOAD.funct3 + -- ------------------------------------------------------------ + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); + + when opcode_store_c => -- check STORE.funct3 + -- ------------------------------------------------------------ + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c)); + + when opcode_atomic_c => -- atomic instructions + -- ------------------------------------------------------------ + if (CPU_EXTENSION_RISCV_A = true) then + if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00010") then -- LR + illegal_instruction <= '0'; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); + elsif (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00011") then -- SC + illegal_instruction <= '0'; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); + else + illegal_instruction <= '1'; + end if; + else + illegal_instruction <= '1'; + end if; + + when opcode_branch_c => -- check BRANCH.funct3 + -- ------------------------------------------------------------ + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c)); + + when opcode_jalr_c => -- check JALR.funct3 + -- ------------------------------------------------------------ + if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); + + when opcode_fence_c => -- check FENCE.funct3 + -- ------------------------------------------------------------ + if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true)) or -- FENCE.I + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); + + when opcode_syscsr_c => -- check system instructions + -- ------------------------------------------------------------ + -- CSR access -- + if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or + (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c)) and + (csr_acc_valid = '1') then -- valid CSR access? + illegal_instruction <= '0'; + -- illegal E-CPU register? -- + if (CPU_EXTENSION_RISCV_E = true) then + if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR + illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); + else -- reg-imm CSR + illegal_register <= execute_engine.i_reg(instr_rd_msb_c); + end if; + end if; + -- ecall, ebreak, mret, wfi, dret -- + elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") and + (decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') and + ((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL + (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK + ((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) and (csr.priv_m_mode = '1')) or -- MRET (only allowed in M-mode) + ((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_dret_c) and (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1')) or -- DRET (only allowed in D-mode) + (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c)) then -- WFI (always allowed to execute) + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + + when opcode_fop_c => -- floating point operations - single/dual operands + -- ------------------------------------------------------------ + if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented + (execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only + (decode_aux.is_float_op = '1') then -- is correct/supported floating-point instruction + illegal_instruction <= '0'; + else + illegal_instruction <= '1'; + end if; + -- illegal E-CPU register? -- + -- FIXME: rs2 is not checked! + illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c)); + + when others => -- undefined instruction -> illegal! + -- ------------------------------------------------------------ + illegal_instruction <= '1'; + + end case; + else + illegal_opcode_lsbs <= '0'; + illegal_compressed <= '0'; + illegal_instruction <= '0'; + illegal_register <= '0'; + end if; + end process illegal_instruction_check; + + -- any illegal condition? -- + trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed; + + +-- **************************************************************************************************************************** +-- Exception and Interrupt (= Trap) Control +-- **************************************************************************************************************************** + + -- Trap Controller ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + trap_controller: process(rstn_i, clk_i) + variable mode_m_v, mode_u_v : std_ulogic; + begin + if (rstn_i = '0') then + trap_ctrl.exc_buf <= (others => '0'); + trap_ctrl.irq_buf <= (others => '0'); + trap_ctrl.exc_ack <= '0'; + trap_ctrl.env_start <= '0'; + trap_ctrl.cause <= (others => '0'); + elsif rising_edge(clk_i) then + if (CPU_EXTENSION_RISCV_Zicsr = true) then + + -- exception queue: misaligned load/store/instruction address -- + trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack); + trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack); + trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack); + + -- exception queue: load/store/instruction bus access error -- + trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack); + trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack); + trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack); + + -- exception queue: illegal instruction / environment calls -- + trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack); + trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack); + trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack); + + -- exception queue: break point -- + if (CPU_EXTENSION_RISCV_DEBUG = true) then + trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_ack) and (trap_ctrl.exc_buf(exception_break_c) or + ((trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- enable break to machine-trap-handler when in machine mode on "ebreak" + (trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running)))); -- enable break to machine-trap-handler when in user mode on "ebreak" + else + trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack); + end if; + + -- exception buffer: enter debug mode -- + trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_ack); + trap_ctrl.irq_buf(interrupt_db_halt_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt; + trap_ctrl.irq_buf(interrupt_db_step_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step; + + -- interrupt buffer: machine software/external/timer interrupt -- + trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and msw_irq_i; + trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and mext_irq_i; + trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and mtime_irq_i; + + -- interrupt queue: NEORV32-specific fast interrupts (FIRQ) -- + trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) <= (trap_ctrl.irq_buf(interrupt_firq_15_c downto interrupt_firq_0_c) or (csr.mie_firqe and firq_i)) and (not csr.mip_clr); + + -- trap environment control -- + if (trap_ctrl.env_start = '0') then -- no started trap handler + if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception triggered! + ((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ + trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr) + trap_ctrl.exc_ack <= '1'; -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!) + trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler + end if; + else -- trap waiting to get started + if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine + trap_ctrl.exc_ack <= '0'; + trap_ctrl.env_start <= '0'; + end if; + end if; + end if; + end if; + end process trap_controller; + + -- any exception/interrupt? -- + trap_ctrl.exc_fire <= or_reduce_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked + trap_ctrl.irq_fire <= (or_reduce_f(trap_ctrl.irq_buf) and csr.mstatus_mie and trap_ctrl.db_irq_en) or trap_ctrl.db_irq_fire; -- interrupts CAN be masked (but not the DEBUG halt IRQ) + + -- debug mode (entry) interrupts -- + trap_ctrl.db_irq_en <= '0' when (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) else '1'; -- no interrupts when IN debug mode or IN single-step mode + trap_ctrl.db_irq_fire <= (trap_ctrl.irq_buf(interrupt_db_step_c) or trap_ctrl.irq_buf(interrupt_db_halt_c)) when (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; -- "NMI" for debug mode entry + + + -- Trap Priority Encoder ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + trap_priority: process(trap_ctrl) + begin + -- defaults -- + trap_ctrl.cause_nxt <= (others => '0'); + + -- NOTE: Synchronous exceptions (from trap_ctrl.exc_buf) have higher priority than asynchronous + -- exceptions (from trap_ctrl.irq_buf). + + -- ---------------------------------------------------------------------------------------- + -- the following traps are caused by *synchronous* exceptions; we do not need a + -- specific acknowledge mask since only _one_ exception (the one with highest priority) + -- is allowed to kick in at once + -- ---------------------------------------------------------------------------------------- + + -- exception: 0.0 instruction address misaligned -- + if (trap_ctrl.exc_buf(exception_ialign_c) = '1') then + trap_ctrl.cause_nxt <= trap_ima_c; + + -- exception: 0.1 instruction access fault -- + elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then + trap_ctrl.cause_nxt <= trap_iba_c; + + -- exception: 0.2 illegal instruction -- + elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then + trap_ctrl.cause_nxt <= trap_iil_c; + + + -- exception: 0.11 environment call from M-mode -- + elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then + trap_ctrl.cause_nxt <= trap_menv_c; + + -- exception: 0.8 environment call from U-mode -- + elsif (trap_ctrl.exc_buf(exception_u_envcall_c) = '1') then + trap_ctrl.cause_nxt <= trap_uenv_c; + + -- exception: 0.3 breakpoint -- + elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then + trap_ctrl.cause_nxt <= trap_brk_c; + + + -- exception: 0.6 store address misaligned - + elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then + trap_ctrl.cause_nxt <= trap_sma_c; + + -- exception: 0.4 load address misaligned -- + elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then + trap_ctrl.cause_nxt <= trap_lma_c; + + -- exception: 0.7 store access fault -- + elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then + trap_ctrl.cause_nxt <= trap_sbe_c; + + -- exception: 0.5 load access fault -- + elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then + trap_ctrl.cause_nxt <= trap_lbe_c; + + + -- ---------------------------------------------------------------------------------------- + -- (re-)enter debug mode requests; basically, these are standard traps that have some + -- special handling - they have the highest INTERRUPT priority in order to go to debug when requested + -- even if other IRQs are pending right now + -- ---------------------------------------------------------------------------------------- + + -- break instruction -- + elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.exc_buf(exception_db_break_c) = '1') then + trap_ctrl.cause_nxt <= trap_db_break_c; + + -- external halt request -- + elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then + trap_ctrl.cause_nxt <= trap_db_halt_c; + + -- single stepping -- + elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then + trap_ctrl.cause_nxt <= trap_db_step_c; + + + -- ---------------------------------------------------------------------------------------- + -- the following traps are caused by *asynchronous* exceptions (= interrupts) + -- ---------------------------------------------------------------------------------------- + + -- custom FAST interrupt requests -- + + -- interrupt: 1.16 fast interrupt channel 0 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq0_c; + + -- interrupt: 1.17 fast interrupt channel 1 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq1_c; + + -- interrupt: 1.18 fast interrupt channel 2 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq2_c; + + -- interrupt: 1.19 fast interrupt channel 3 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq3_c; + + -- interrupt: 1.20 fast interrupt channel 4 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_4_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq4_c; + + -- interrupt: 1.21 fast interrupt channel 5 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_5_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq5_c; + + -- interrupt: 1.22 fast interrupt channel 6 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_6_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq6_c; + + -- interrupt: 1.23 fast interrupt channel 7 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_7_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq7_c; + + -- interrupt: 1.24 fast interrupt channel 8 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_8_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq8_c; + + -- interrupt: 1.25 fast interrupt channel 9 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_9_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq9_c; + + -- interrupt: 1.26 fast interrupt channel 10 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_10_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq10_c; + + -- interrupt: 1.27 fast interrupt channel 11 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_11_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq11_c; + + -- interrupt: 1.28 fast interrupt channel 12 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_12_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq12_c; + + -- interrupt: 1.29 fast interrupt channel 13 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_13_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq13_c; + + -- interrupt: 1.30 fast interrupt channel 14 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_14_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq14_c; + + -- interrupt: 1.31 fast interrupt channel 15 -- + elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then + trap_ctrl.cause_nxt <= trap_firq15_c; + + + -- standard RISC-V interrupts -- + + -- interrupt: 1.11 machine external interrupt -- + elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then + trap_ctrl.cause_nxt <= trap_mei_c; + + -- interrupt: 1.3 machine SW interrupt -- + elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then + trap_ctrl.cause_nxt <= trap_msi_c; + + -- interrupt: 1.7 machine timer interrupt -- + elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then + trap_ctrl.cause_nxt <= trap_mti_c; + + end if; + end process trap_priority; + + +-- **************************************************************************************************************************** +-- Control and Status Registers (CSRs) +-- **************************************************************************************************************************** + + -- Control and Status Registers Write Data ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i) + variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0); + begin + -- CSR operand source -- + if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate + csr_operand_v := (others => '0'); + csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5 + else -- register + csr_operand_v := rs1_i; + end if; + -- tiny ALU for CSR write operations -- + case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is + when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I) + when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I) + when others => csr.wdata <= csr_operand_v; -- CSRRW(I) + end case; + end process csr_write_data; + + + -- Control and Status Registers - Write Access -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + csr_write_access: process(rstn_i, clk_i) + variable cause_v : std_ulogic_vector(6 downto 0); + begin + -- NOTE: If = true then evaluates to '-'. Register that reset to do + -- NOT actually have a real reset by default (def_rst_val_c = '-') and have to be explicitly initialized by software! + -- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845 + if (rstn_i = '0') then + csr.we <= '0'; + -- + csr.mstatus_mie <= '0'; + csr.mstatus_mpie <= '0'; + csr.mstatus_mpp <= (others => '0'); + csr.privilege <= priv_mode_m_c; -- start in MACHINE mode + csr.mie_msie <= def_rst_val_c; + csr.mie_meie <= def_rst_val_c; + csr.mie_mtie <= def_rst_val_c; + csr.mie_firqe <= (others => def_rst_val_c); + csr.mtvec <= (others => def_rst_val_c); + csr.mscratch <= x"19880704"; + csr.mepc <= (others => def_rst_val_c); + csr.mcause <= (others => def_rst_val_c); + csr.mtval <= (others => def_rst_val_c); + csr.mip_clr <= (others => def_rst_val_c); + -- + csr.pmpcfg <= (others => (others => '0')); + csr.pmpaddr <= (others => (others => def_rst_val_c)); + -- + csr.mhpmevent <= (others => (others => def_rst_val_c)); + -- + csr.mcounteren_cy <= def_rst_val_c; + csr.mcounteren_tm <= def_rst_val_c; + csr.mcounteren_ir <= def_rst_val_c; + -- + csr.mcountinhibit_cy <= def_rst_val_c; + csr.mcountinhibit_ir <= def_rst_val_c; + csr.mcountinhibit_hpm <= (others => def_rst_val_c); + -- + csr.fflags <= (others => def_rst_val_c); + csr.frm <= (others => def_rst_val_c); + -- + csr.dcsr_ebreakm <= '0'; + csr.dcsr_ebreaku <= '0'; + csr.dcsr_step <= '0'; + csr.dcsr_prv <= (others => def_rst_val_c); + csr.dcsr_cause <= (others => def_rst_val_c); + csr.dpc <= (others => def_rst_val_c); + csr.dscratch0 <= (others => def_rst_val_c); + + elsif rising_edge(clk_i) then + -- write access? -- + csr.we <= csr.we_nxt; + + -- defaults -- + csr.mip_clr <= (others => '0'); + + if (CPU_EXTENSION_RISCV_Zicsr = true) then + -- -------------------------------------------------------------------------------- + -- CSR access by application software + -- -------------------------------------------------------------------------------- + if (csr.we = '1') and (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- manual write access and not illegal instruction + + -- user floating-point CSRs -- + -- -------------------------------------------------------------------- + if (CPU_EXTENSION_RISCV_Zfinx = true) then -- floating point CSR class + if (csr.addr(11 downto 2) = csr_class_float_c) then + if (csr.addr(1 downto 0) = "01") then -- R/W: fflags - floating-point (FPU) exception flags + csr.fflags <= csr.wdata(4 downto 0); + elsif (csr.addr(1 downto 0) = "10") then -- R/W: frm - floating-point (FPU) rounding mode + csr.frm <= csr.wdata(2 downto 0); + elsif (csr.addr(1 downto 0) = "11") then -- R/W: fcsr - floating-point (FPU) control/status (frm + fflags) + csr.frm <= csr.wdata(7 downto 5); + csr.fflags <= csr.wdata(4 downto 0); + end if; + end if; + end if; + + -- machine trap setup -- + -- -------------------------------------------------------------------- + if (csr.addr(11 downto 3) = csr_class_setup_c) then -- trap setup CSR class + -- R/W: mstatus - machine status register -- + if (csr.addr(2 downto 0) = csr_mstatus_c(2 downto 0)) then + csr.mstatus_mie <= csr.wdata(03); + csr.mstatus_mpie <= csr.wdata(07); + if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented + csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12); + csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12); + end if; + end if; + -- R/W: mie - machine interrupt enable register -- + if (csr.addr(2 downto 0) = csr_mie_c(2 downto 0)) then + csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable + csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable + csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable + for i in 0 to 15 loop -- fast interrupt channels 0..15 + csr.mie_firqe(i) <= csr.wdata(16+i); + end loop; -- i + end if; + -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) -- + if (csr.addr(2 downto 0) = csr_mtvec_c(2 downto 0)) then + csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 + end if; + -- R/W: mcounteren - machine counter enable register -- + if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented + if (csr.addr(2 downto 0) = csr_mcounteren_c(2 downto 0)) then + csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h] + csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h] + csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h] + end if; + end if; + end if; + + -- machine trap handling -- + -- -------------------------------------------------------------------- + if (csr.addr(11 downto 4) = csr_class_trap_c) then -- machine trap handling CSR class + -- R/W: mscratch - machine scratch register -- + if (csr.addr(3 downto 0) = csr_mscratch_c(3 downto 0)) then + csr.mscratch <= csr.wdata; + end if; + -- R/W: mepc - machine exception program counter -- + if (csr.addr(3 downto 0) = csr_mepc_c(3 downto 0)) then + csr.mepc <= csr.wdata; + end if; + -- R/W: mcause - machine trap cause -- + if (csr.addr(3 downto 0) = csr_mcause_c(3 downto 0)) then + csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: async/interrupt, 0: sync/exception + csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier + end if; + -- R/W: mip - machine interrupt pending -- + if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then + csr.mip_clr <= csr.wdata(31 downto 16); + end if; + end if; + + -- physical memory protection: R/W: pmpcfg* - PMP configuration registers -- + -- -------------------------------------------------------------------- + if (PMP_NUM_REGIONS > 0) then + if (csr.addr(11 downto 4) = csr_class_pmpcfg_c) then -- pmp configuration CSR class + for i in 0 to PMP_NUM_REGIONS-1 loop + if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) then + if (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpcfg access + csr.pmpcfg(i)(0) <= csr.wdata((i mod 4)*8+0); -- R (rights.read) + csr.pmpcfg(i)(1) <= csr.wdata((i mod 4)*8+1); -- W (rights.write) + csr.pmpcfg(i)(2) <= csr.wdata((i mod 4)*8+2); -- X (rights.execute) + csr.pmpcfg(i)(3) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_L + csr.pmpcfg(i)(4) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_H - NAPOT/OFF only + csr.pmpcfg(i)(5) <= '0'; -- reserved + csr.pmpcfg(i)(6) <= '0'; -- reserved + csr.pmpcfg(i)(7) <= csr.wdata((i mod 4)*8+7); -- L (locked / rights also enforced in m-mode) + end if; + end if; + end loop; -- i (PMP regions) + end if; + end if; + + -- physical memory protection: R/W: pmpaddr* - PMP address registers -- + -- -------------------------------------------------------------------- + if (PMP_NUM_REGIONS > 0) then + if (csr.addr(11 downto 4) = csr_pmpaddr0_c(11 downto 4)) or (csr.addr(11 downto 4) = csr_pmpaddr16_c(11 downto 4)) or + (csr.addr(11 downto 4) = csr_pmpaddr32_c(11 downto 4)) or (csr.addr(11 downto 4) = csr_pmpaddr48_c(11 downto 4)) then + for i in 0 to PMP_NUM_REGIONS-1 loop + if (csr.addr(6 downto 0) = std_ulogic_vector(unsigned(csr_pmpaddr0_c(6 downto 0)) + i)) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access + csr.pmpaddr(i) <= csr.wdata; + csr.pmpaddr(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1'); + end if; + end loop; -- i (PMP regions) + end if; + end if; + + -- machine counter setup -- + -- -------------------------------------------------------------------- + if (csr.addr(11 downto 5) = csr_cnt_setup_c) then -- counter configuration CSR class + -- R/W: mcountinhibit - machine counter-inhibit register -- + if (csr.addr(4 downto 0) = csr_mcountinhibit_c(4 downto 0)) then + csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter + csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter + if (HPM_NUM_CNTS > 0) then -- any HPMs available? + csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter + end if; + end if; + -- R/W: mhpmevent - machine performance-monitors event selector -- + if (HPM_NUM_CNTS > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then + for i in 0 to HPM_NUM_CNTS-1 loop + if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then + csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0); + end if; + csr.mhpmevent(i)(hpmcnt_event_never_c) <= '0'; -- would be used for "TIME" + end loop; -- i (CSRs) + end if; + end if; + + -- debug mode CSRs -- + -- -------------------------------------------------------------------- + if (CPU_EXTENSION_RISCV_DEBUG = true) then + if (csr.addr(11 downto 2) = csr_class_debug_c) then -- debug CSR class + -- R/W: dcsr - debug mode control and status register -- + if (csr.addr(1 downto 0) = csr_dcsr_c(1 downto 0)) then + csr.dcsr_ebreakm <= csr.wdata(15); + csr.dcsr_step <= csr.wdata(2); + if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented + csr.dcsr_ebreaku <= csr.wdata(12); + csr.dcsr_prv(0) <= csr.wdata(1) or csr.wdata(0); + csr.dcsr_prv(1) <= csr.wdata(1) or csr.wdata(0); + else -- only machine mode is available + csr.dcsr_prv <= priv_mode_m_c; + end if; + end if; + -- R/W: dpc - debug mode program counter -- + if (csr.addr(1 downto 0) = csr_dpc_c(1 downto 0)) then + csr.dpc <= csr.wdata(data_width_c-1 downto 1) & '0'; + end if; + -- R/W: dscratch0 - debug mode scratch register 0 -- + if (csr.addr(1 downto 0) = csr_dscratch0_c(1 downto 0)) then + csr.dscratch0 <= csr.wdata; + end if; + end if; + end if; + + + -- -------------------------------------------------------------------------------- + -- CSR access by hardware + -- -------------------------------------------------------------------------------- + else + + -- floating-point (FPU) exception flags -- + -- -------------------------------------------------------------------- + if (CPU_EXTENSION_RISCV_Zfinx = true) and (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction + csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags") + end if; + + -- mcause, mepc, mtval: write machine trap cause, PC and trap value register -- + -- -------------------------------------------------------------------- + if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? + + if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and -- update mtval/mepc/mcause only when NOT ENTRY debug mode exception + (debug_ctrl.running = '0')) then -- and NOT IN debug mode + + -- trap cause ID code -- + csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception + csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier + + -- trap PC -- + if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source) + csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction + else -- for sync. EXCEPTIONS (sync source) + csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction + end if; + + -- trap value -- + cause_v := trap_ctrl.cause; + cause_v(5) := '0'; -- bit 5 is always zero here (= normal trapping), so we do not need to check that again + case cause_v is + when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error + csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction + when trap_brk_c => -- breakpoint + csr.mtval <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- address of breakpoint instruction + when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error + csr.mtval <= mar_i; -- faulting data access address + when trap_iil_c => -- illegal instruction + csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself + when others => -- everything else including all interrupts + csr.mtval <= (others => '0'); + end case; + + end if; + + -- DEBUG MODE (trap) enter: write dpc and dcsr -- + -- -------------------------------------------------------------------- + if (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.cause(5) = '1') and (debug_ctrl.running = '0') then -- debug mode entry exception + + -- trap cause ID code -- + csr.dcsr_cause <= trap_ctrl.cause(2 downto 0); -- why did we enter debug mode? + -- current privilege mode when debug mode was entered -- + csr.dcsr_prv <= csr.privilege; + + -- trap PC -- + if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source) + csr.dpc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction + else -- for sync. EXCEPTIONS (sync source) + csr.dpc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction + end if; + + end if; + + end if; + + -- mstatus: context switch -- + -- -------------------------------------------------------------------- + -- ENTER: trap handling starting? + if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? + + if (CPU_EXTENSION_RISCV_DEBUG = false) or -- normal trapping (debug mode NOT implemented) + ((debug_ctrl.running = '0') and (trap_ctrl.cause(5) = '0')) then -- not IN debug mode and not ENTERING debug mode + csr.mstatus_mie <= '0'; -- disable interrupts + csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state + if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode + csr.privilege <= priv_mode_m_c; -- execute trap in machine mode + csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode + end if; + end if; + + -- EXIT: return from exception + elsif (trap_ctrl.env_end = '1') then + if (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') then -- return from debug mode + if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode + csr.privilege <= csr.dcsr_prv; + end if; + else -- return from "normal trap" + csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag + csr.mstatus_mpie <= '1'; + if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode + csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode + csr.mstatus_mpp <= (others => '0'); + end if; + end if; + end if; + + end if; -- /hardware csr access + end if; + + -- -------------------------------------------------------------------------------- + -- override write access for disabled functions + -- -------------------------------------------------------------------------------- + + -- user mode disabled -- + if (CPU_EXTENSION_RISCV_U = false) then + csr.privilege <= priv_mode_m_c; + csr.mstatus_mpp <= priv_mode_m_c; + csr.mcounteren_cy <= '0'; + csr.mcounteren_tm <= '0'; + csr.mcounteren_ir <= '0'; + csr.dcsr_ebreaku <= '0'; + csr.dcsr_prv <= priv_mode_m_c; + end if; + + -- pmp disabled -- + if (PMP_NUM_REGIONS = 0) then + csr.pmpcfg <= (others => (others => '0')); + csr.pmpaddr <= (others => (others => '1')); + end if; + + -- hpms disabled -- + if (HPM_NUM_CNTS = 0) then + csr.mhpmevent <= (others => (others => '0')); + csr.mcountinhibit_hpm <= (others => '0'); + end if; + + -- cpu counters disabled -- + if (CPU_CNT_WIDTH = 0) then + csr.mcounteren_cy <= '0'; + csr.mcounteren_ir <= '0'; + csr.mcountinhibit_cy <= '0'; + csr.mcountinhibit_ir <= '0'; + end if; + + -- floating-point extension disabled -- + if (CPU_EXTENSION_RISCV_Zfinx = false) then + csr.fflags <= (others => '0'); + csr.frm <= (others => '0'); + end if; + + -- debug mode disabled -- + if (CPU_EXTENSION_RISCV_DEBUG = false) then + csr.dcsr_ebreakm <= '0'; + csr.dcsr_ebreaku <= '0'; + csr.dcsr_step <= '0'; + csr.dcsr_cause <= (others => '0'); + csr.dpc <= (others => '0'); + csr.dscratch0 <= (others => '0'); + end if; + + end if; + end process csr_write_access; + + -- decode current privilege mode -- + csr.privilege_rd <= priv_mode_m_c when (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') else csr.privilege; -- effective privilege mode ("machine" when in debug mode) + csr.priv_m_mode <= '1' when (csr.privilege_rd = priv_mode_m_c) else '0'; + csr.priv_u_mode <= '1' when (csr.privilege_rd = priv_mode_u_c) and (CPU_EXTENSION_RISCV_U = true) else '0'; + + -- PMP configuration output to bus unit -- + pmp_output: process(csr) + begin + pmp_addr_o <= (others => (others => '0')); + pmp_ctrl_o <= (others => (others => '0')); + if (PMP_NUM_REGIONS /= 0) then + for i in 0 to PMP_NUM_REGIONS-1 loop + pmp_addr_o(i) <= csr.pmpaddr(i) & "11"; + pmp_addr_o(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1'); + pmp_ctrl_o(i) <= csr.pmpcfg(i); + end loop; -- i + end if; + end process pmp_output; + + -- PMP config read dummy -- + pmp_rd_dummy: process(csr) + begin + csr.pmpcfg_rd <= (others => (others => '0')); + if (PMP_NUM_REGIONS /= 0) then + for i in 0 to PMP_NUM_REGIONS-1 loop + csr.pmpcfg_rd(i) <= csr.pmpcfg(i); + end loop; -- i + end if; + end process pmp_rd_dummy; + + + -- Control and Status Registers - Counters ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + csr_counters: process(rstn_i, clk_i) + begin + -- Counter CSRs (each counter is split into two 32-bit counters - coupled via an MSB overflow FF) + if (rstn_i = '0') then + csr.mcycle <= (others => def_rst_val_c); + csr.mcycle_ovfl <= (others => def_rst_val_c); + csr.mcycleh <= (others => def_rst_val_c); + csr.minstret <= (others => def_rst_val_c); + csr.minstret_ovfl <= (others => def_rst_val_c); + csr.minstreth <= (others => def_rst_val_c); + csr.mhpmcounter <= (others => (others => def_rst_val_c)); + csr.mhpmcounter_ovfl <= (others => (others => def_rst_val_c)); + csr.mhpmcounterh <= (others => (others => def_rst_val_c)); + elsif rising_edge(clk_i) then + + -- [m]cycle -- + if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then + csr.mcycle_ovfl(0) <= csr.mcycle_nxt(csr.mcycle_nxt'left) and (not csr.mcountinhibit_cy); + if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access + csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0); + elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update + csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle_nxt(cpu_cnt_lo_width_c-1 downto 0); + end if; + else + csr.mcycle <= (others => '-'); + csr.mcycle_ovfl(0) <= '-'; + end if; + + -- [m]cycleh -- + if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then + if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access + csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0); + else -- automatic update + csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mcycle_ovfl)); + end if; + else + csr.mcycleh <= (others => '-'); + end if; + + + -- [m]instret -- + if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then + csr.minstret_ovfl(0) <= csr.minstret_nxt(csr.minstret_nxt'left) and (not csr.mcountinhibit_ir); + if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access + csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0); + elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') then -- non-inhibited automatic update + csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret_nxt(cpu_cnt_lo_width_c-1 downto 0); + end if; + else + csr.minstret <= (others => '-'); + csr.minstret_ovfl(0) <= '-'; + end if; + + -- [m]instreth -- + if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then + if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access + csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0); + else -- automatic update + csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.minstreth(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.minstret_ovfl)); + end if; + else + csr.minstreth <= (others => '-'); + end if; + + + -- [machine] hardware performance monitors (counters) -- + for i in 0 to HPM_NUM_CNTS-1 loop + + -- [m]hpmcounter* -- + if (hpm_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then + csr.mhpmcounter_ovfl(i)(0) <= csr.mhpmcounter_nxt(i)(csr.mhpmcounter_nxt(i)'left) and (not csr.mcountinhibit_hpm(i)); + if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3_c) + i)) then -- write access + csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.wdata(hpm_cnt_lo_width_c-1 downto 0); + elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update + csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter_nxt(i)(hpm_cnt_lo_width_c-1 downto 0); + end if; + else + csr.mhpmcounter(i) <= (others => '-'); + csr.mhpmcounter_ovfl(i)(0) <= '-'; + end if; + + -- [m]hpmcounter*h -- + if (hpm_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then + if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access + csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.wdata(hpm_cnt_hi_width_c-1 downto 0); + else -- automatic update + csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mhpmcounter_ovfl(i))); + end if; + else + csr.mhpmcounterh(i) <= (others => '-'); + end if; + + end loop; -- i + + end if; + end process csr_counters; + + + -- mcycle & minstret increment LOW -- + csr.mcycle_nxt <= std_ulogic_vector(unsigned('0' & csr.mcycle) + 1); + csr.minstret_nxt <= std_ulogic_vector(unsigned('0' & csr.minstret) + 1); + + -- hpm counter increment LOW -- + hmp_cnt_lo_inc: + for i in 0 to HPM_NUM_CNTS-1 generate + csr.mhpmcounter_nxt(i) <= std_ulogic_vector(unsigned('0' & csr.mhpmcounter(i)) + 1); + end generate; + + + -- hpm counter read -- + hpm_rd_dummy: process(csr) + begin + csr.mhpmcounter_rd <= (others => (others => '0')); + csr.mhpmcounterh_rd <= (others => (others => '0')); + if (HPM_NUM_CNTS /= 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then + for i in 0 to HPM_NUM_CNTS-1 loop + if (hpm_cnt_lo_width_c > 0) then + csr.mhpmcounter_rd(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0); + end if; + if (hpm_cnt_hi_width_c > 0) then + csr.mhpmcounterh_rd(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0); + end if; + end loop; -- i + end if; + end process hpm_rd_dummy; + + + -- Hardware Performance Monitor - Counter Event Control ----------------------------------- + -- ------------------------------------------------------------------------------------------- + hpmcnt_ctrl: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + hpmcnt_trigger <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + -- enable selected triggers by ANDing actual events and according CSR configuration bits -- + -- OR everything to see if counter should increment -- + hpmcnt_trigger <= (others => '0'); -- default + if (HPM_NUM_CNTS /= 0) then + for i in 0 to HPM_NUM_CNTS-1 loop + hpmcnt_trigger(i) <= or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)); + end loop; -- i + end if; + end if; + end process hpmcnt_ctrl; + + -- counter event trigger - RISC-V-specific -- + cnt_event(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle + cnt_event(hpmcnt_event_never_c) <= '0'; -- undefined (never) + cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction + + -- counter event trigger - custom / NEORV32-specific -- + cnt_event(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction + cnt_event(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle + cnt_event(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle + cnt_event(hpmcnt_event_wait_mc_c) <= '1' when (execute_engine.state = ALU_WAIT) else '0'; -- multi-cycle alu-operation wait cycle + + cnt_event(hpmcnt_event_load_c) <= '1' when (ctrl(ctrl_bus_rd_c) = '1') else '0'; -- load operation + cnt_event(hpmcnt_event_store_c) <= '1' when (ctrl(ctrl_bus_wr_c) = '1') else '0'; -- store operation + cnt_event(hpmcnt_event_wait_ls_c) <= '1' when (execute_engine.state = LOADSTORE_2) and (execute_engine.state_prev = LOADSTORE_2) else '0'; -- load/store memory wait cycle + + cnt_event(hpmcnt_event_jump_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') else '0'; -- jump (unconditional) + cnt_event(hpmcnt_event_branch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken) + cnt_event(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional) + + cnt_event(hpmcnt_event_trap_c) <= '1' when (trap_ctrl.env_start_ack = '1') else '0'; -- entered trap + cnt_event(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation + + + -- Control and Status Registers - Read Access --------------------------------------------- + -- ------------------------------------------------------------------------------------------- + csr_read_access: process(rstn_i, clk_i) + variable csr_addr_v : std_ulogic_vector(11 downto 0); + begin + if rising_edge(clk_i) then + csr.rdata <= (others => '0'); -- default output + if (CPU_EXTENSION_RISCV_Zicsr = true) then + csr_addr_v(11 downto 10) := csr.addr(11 downto 10); + csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) registers ONLY !!! + csr_addr_v(07 downto 00) := csr.addr(07 downto 00); + case csr_addr_v is + + -- floating-point CSRs -- + -- -------------------------------------------------------------------- + when csr_fflags_c => -- fflags (r/w): floating-point (FPU) exception flags + if (CPU_EXTENSION_RISCV_Zfinx = true) then csr.rdata(4 downto 0) <= csr.fflags; else NULL; end if; + when csr_frm_c => -- frm (r/w): floating-point (FPU) rounding mode + if (CPU_EXTENSION_RISCV_Zfinx = true) then csr.rdata(2 downto 0) <= csr.frm; else NULL; end if; + when csr_fcsr_c => -- fcsr (r/w): floating-point (FPU) control/status (frm + fflags) + if (CPU_EXTENSION_RISCV_Zfinx = true) then csr.rdata(7 downto 5) <= csr.frm; csr.rdata(4 downto 0) <= csr.fflags; else NULL; end if; + + -- machine trap setup -- + -- -------------------------------------------------------------------- + when csr_mstatus_c => -- mstatus (r/w): machine status register + csr.rdata(03) <= csr.mstatus_mie; -- MIE + csr.rdata(07) <= csr.mstatus_mpie; -- MPIE + csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low + csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high + when csr_misa_c => -- misa (r/-): ISA and extensions + csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension + csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension + csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension + csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension + csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) + csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension + csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension + csr.rdata(23) <= '1'; -- X CPU extension (non-std extensions) + csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo) + csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi) + when csr_mie_c => -- mie (r/w): machine interrupt-enable register + csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable + csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable + csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable + for i in 0 to 15 loop -- fast interrupt channels 0..15 enable + csr.rdata(16+i) <= csr.mie_firqe(i); + end loop; -- i + when csr_mtvec_c => -- mtvec (r/w): machine trap-handler base address (for ALL exceptions) + csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 + when csr_mcounteren_c => -- mcounteren (r/w): machine counter enable register + if (CPU_EXTENSION_RISCV_U = false) then -- this CSR is hardwired to zero if user mode is not implemented + NULL; + else + csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h] + csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h] + csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h] + end if; + + -- machine trap handling -- + -- -------------------------------------------------------------------- + when csr_mscratch_c => -- mscratch (r/w): machine scratch register + csr.rdata <= csr.mscratch; + when csr_mepc_c => -- mepc (r/w): machine exception program counter + csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0'; + when csr_mcause_c => -- mcause (r/w): machine trap cause + csr.rdata(31) <= csr.mcause(csr.mcause'left); + csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0); + when csr_mtval_c => -- mtval (r/-): machine bad address or instruction + csr.rdata <= csr.mtval; + when csr_mip_c => -- mip (r/w): machine interrupt pending + csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c); + csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c); + csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c); + for i in 0 to 15 loop -- fast interrupt channels 0..15 pending + csr.rdata(16+i) <= trap_ctrl.irq_buf(interrupt_firq_0_c+i); + end loop; -- i + + -- physical memory protection - configuration (r/w) -- + -- -------------------------------------------------------------------- + when csr_pmpcfg0_c => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); else NULL; end if; + when csr_pmpcfg1_c => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); else NULL; end if; + when csr_pmpcfg2_c => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); else NULL; end if; + when csr_pmpcfg3_c => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); else NULL; end if; + when csr_pmpcfg4_c => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); else NULL; end if; + when csr_pmpcfg5_c => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); else NULL; end if; + when csr_pmpcfg6_c => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); else NULL; end if; + when csr_pmpcfg7_c => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); else NULL; end if; + when csr_pmpcfg8_c => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); else NULL; end if; + when csr_pmpcfg9_c => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); else NULL; end if; + when csr_pmpcfg10_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); else NULL; end if; + when csr_pmpcfg11_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); else NULL; end if; + when csr_pmpcfg12_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); else NULL; end if; + when csr_pmpcfg13_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); else NULL; end if; + when csr_pmpcfg14_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); else NULL; end if; + when csr_pmpcfg15_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); else NULL; end if; + + -- physical memory protection - addresses (r/w) -- + -- -------------------------------------------------------------------- + when csr_pmpaddr0_c => if (PMP_NUM_REGIONS > 00) then csr.rdata <= csr.pmpaddr(00); else NULL; end if; + when csr_pmpaddr1_c => if (PMP_NUM_REGIONS > 01) then csr.rdata <= csr.pmpaddr(01); else NULL; end if; + when csr_pmpaddr2_c => if (PMP_NUM_REGIONS > 02) then csr.rdata <= csr.pmpaddr(02); else NULL; end if; + when csr_pmpaddr3_c => if (PMP_NUM_REGIONS > 03) then csr.rdata <= csr.pmpaddr(03); else NULL; end if; + when csr_pmpaddr4_c => if (PMP_NUM_REGIONS > 04) then csr.rdata <= csr.pmpaddr(04); else NULL; end if; + when csr_pmpaddr5_c => if (PMP_NUM_REGIONS > 05) then csr.rdata <= csr.pmpaddr(05); else NULL; end if; + when csr_pmpaddr6_c => if (PMP_NUM_REGIONS > 06) then csr.rdata <= csr.pmpaddr(06); else NULL; end if; + when csr_pmpaddr7_c => if (PMP_NUM_REGIONS > 07) then csr.rdata <= csr.pmpaddr(07); else NULL; end if; + when csr_pmpaddr8_c => if (PMP_NUM_REGIONS > 08) then csr.rdata <= csr.pmpaddr(08); else NULL; end if; + when csr_pmpaddr9_c => if (PMP_NUM_REGIONS > 09) then csr.rdata <= csr.pmpaddr(09); else NULL; end if; + when csr_pmpaddr10_c => if (PMP_NUM_REGIONS > 10) then csr.rdata <= csr.pmpaddr(10); else NULL; end if; + when csr_pmpaddr11_c => if (PMP_NUM_REGIONS > 11) then csr.rdata <= csr.pmpaddr(11); else NULL; end if; + when csr_pmpaddr12_c => if (PMP_NUM_REGIONS > 12) then csr.rdata <= csr.pmpaddr(12); else NULL; end if; + when csr_pmpaddr13_c => if (PMP_NUM_REGIONS > 13) then csr.rdata <= csr.pmpaddr(13); else NULL; end if; + when csr_pmpaddr14_c => if (PMP_NUM_REGIONS > 14) then csr.rdata <= csr.pmpaddr(14); else NULL; end if; + when csr_pmpaddr15_c => if (PMP_NUM_REGIONS > 15) then csr.rdata <= csr.pmpaddr(15); else NULL; end if; + when csr_pmpaddr16_c => if (PMP_NUM_REGIONS > 16) then csr.rdata <= csr.pmpaddr(16); else NULL; end if; + when csr_pmpaddr17_c => if (PMP_NUM_REGIONS > 17) then csr.rdata <= csr.pmpaddr(17); else NULL; end if; + when csr_pmpaddr18_c => if (PMP_NUM_REGIONS > 18) then csr.rdata <= csr.pmpaddr(18); else NULL; end if; + when csr_pmpaddr19_c => if (PMP_NUM_REGIONS > 19) then csr.rdata <= csr.pmpaddr(19); else NULL; end if; + when csr_pmpaddr20_c => if (PMP_NUM_REGIONS > 20) then csr.rdata <= csr.pmpaddr(20); else NULL; end if; + when csr_pmpaddr21_c => if (PMP_NUM_REGIONS > 21) then csr.rdata <= csr.pmpaddr(21); else NULL; end if; + when csr_pmpaddr22_c => if (PMP_NUM_REGIONS > 22) then csr.rdata <= csr.pmpaddr(22); else NULL; end if; + when csr_pmpaddr23_c => if (PMP_NUM_REGIONS > 23) then csr.rdata <= csr.pmpaddr(23); else NULL; end if; + when csr_pmpaddr24_c => if (PMP_NUM_REGIONS > 24) then csr.rdata <= csr.pmpaddr(24); else NULL; end if; + when csr_pmpaddr25_c => if (PMP_NUM_REGIONS > 25) then csr.rdata <= csr.pmpaddr(25); else NULL; end if; + when csr_pmpaddr26_c => if (PMP_NUM_REGIONS > 26) then csr.rdata <= csr.pmpaddr(26); else NULL; end if; + when csr_pmpaddr27_c => if (PMP_NUM_REGIONS > 27) then csr.rdata <= csr.pmpaddr(27); else NULL; end if; + when csr_pmpaddr28_c => if (PMP_NUM_REGIONS > 28) then csr.rdata <= csr.pmpaddr(28); else NULL; end if; + when csr_pmpaddr29_c => if (PMP_NUM_REGIONS > 29) then csr.rdata <= csr.pmpaddr(29); else NULL; end if; + when csr_pmpaddr30_c => if (PMP_NUM_REGIONS > 30) then csr.rdata <= csr.pmpaddr(30); else NULL; end if; + when csr_pmpaddr31_c => if (PMP_NUM_REGIONS > 31) then csr.rdata <= csr.pmpaddr(31); else NULL; end if; + when csr_pmpaddr32_c => if (PMP_NUM_REGIONS > 32) then csr.rdata <= csr.pmpaddr(32); else NULL; end if; + when csr_pmpaddr33_c => if (PMP_NUM_REGIONS > 33) then csr.rdata <= csr.pmpaddr(33); else NULL; end if; + when csr_pmpaddr34_c => if (PMP_NUM_REGIONS > 34) then csr.rdata <= csr.pmpaddr(34); else NULL; end if; + when csr_pmpaddr35_c => if (PMP_NUM_REGIONS > 35) then csr.rdata <= csr.pmpaddr(35); else NULL; end if; + when csr_pmpaddr36_c => if (PMP_NUM_REGIONS > 36) then csr.rdata <= csr.pmpaddr(36); else NULL; end if; + when csr_pmpaddr37_c => if (PMP_NUM_REGIONS > 37) then csr.rdata <= csr.pmpaddr(37); else NULL; end if; + when csr_pmpaddr38_c => if (PMP_NUM_REGIONS > 38) then csr.rdata <= csr.pmpaddr(38); else NULL; end if; + when csr_pmpaddr39_c => if (PMP_NUM_REGIONS > 39) then csr.rdata <= csr.pmpaddr(39); else NULL; end if; + when csr_pmpaddr40_c => if (PMP_NUM_REGIONS > 40) then csr.rdata <= csr.pmpaddr(40); else NULL; end if; + when csr_pmpaddr41_c => if (PMP_NUM_REGIONS > 41) then csr.rdata <= csr.pmpaddr(41); else NULL; end if; + when csr_pmpaddr42_c => if (PMP_NUM_REGIONS > 42) then csr.rdata <= csr.pmpaddr(42); else NULL; end if; + when csr_pmpaddr43_c => if (PMP_NUM_REGIONS > 43) then csr.rdata <= csr.pmpaddr(43); else NULL; end if; + when csr_pmpaddr44_c => if (PMP_NUM_REGIONS > 44) then csr.rdata <= csr.pmpaddr(44); else NULL; end if; + when csr_pmpaddr45_c => if (PMP_NUM_REGIONS > 45) then csr.rdata <= csr.pmpaddr(45); else NULL; end if; + when csr_pmpaddr46_c => if (PMP_NUM_REGIONS > 46) then csr.rdata <= csr.pmpaddr(46); else NULL; end if; + when csr_pmpaddr47_c => if (PMP_NUM_REGIONS > 47) then csr.rdata <= csr.pmpaddr(47); else NULL; end if; + when csr_pmpaddr48_c => if (PMP_NUM_REGIONS > 48) then csr.rdata <= csr.pmpaddr(48); else NULL; end if; + when csr_pmpaddr49_c => if (PMP_NUM_REGIONS > 49) then csr.rdata <= csr.pmpaddr(49); else NULL; end if; + when csr_pmpaddr50_c => if (PMP_NUM_REGIONS > 50) then csr.rdata <= csr.pmpaddr(50); else NULL; end if; + when csr_pmpaddr51_c => if (PMP_NUM_REGIONS > 51) then csr.rdata <= csr.pmpaddr(51); else NULL; end if; + when csr_pmpaddr52_c => if (PMP_NUM_REGIONS > 52) then csr.rdata <= csr.pmpaddr(52); else NULL; end if; + when csr_pmpaddr53_c => if (PMP_NUM_REGIONS > 53) then csr.rdata <= csr.pmpaddr(53); else NULL; end if; + when csr_pmpaddr54_c => if (PMP_NUM_REGIONS > 54) then csr.rdata <= csr.pmpaddr(54); else NULL; end if; + when csr_pmpaddr55_c => if (PMP_NUM_REGIONS > 55) then csr.rdata <= csr.pmpaddr(55); else NULL; end if; + when csr_pmpaddr56_c => if (PMP_NUM_REGIONS > 56) then csr.rdata <= csr.pmpaddr(56); else NULL; end if; + when csr_pmpaddr57_c => if (PMP_NUM_REGIONS > 57) then csr.rdata <= csr.pmpaddr(57); else NULL; end if; + when csr_pmpaddr58_c => if (PMP_NUM_REGIONS > 58) then csr.rdata <= csr.pmpaddr(58); else NULL; end if; + when csr_pmpaddr59_c => if (PMP_NUM_REGIONS > 59) then csr.rdata <= csr.pmpaddr(59); else NULL; end if; + when csr_pmpaddr60_c => if (PMP_NUM_REGIONS > 60) then csr.rdata <= csr.pmpaddr(60); else NULL; end if; + when csr_pmpaddr61_c => if (PMP_NUM_REGIONS > 61) then csr.rdata <= csr.pmpaddr(61); else NULL; end if; + when csr_pmpaddr62_c => if (PMP_NUM_REGIONS > 62) then csr.rdata <= csr.pmpaddr(62); else NULL; end if; + when csr_pmpaddr63_c => if (PMP_NUM_REGIONS > 63) then csr.rdata <= csr.pmpaddr(63); else NULL; end if; + + -- machine counter setup -- + -- -------------------------------------------------------------------- + when csr_mcountinhibit_c => -- mcountinhibit (r/w): machine counter-inhibit register + csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter + csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter + if (HPM_NUM_CNTS > 0) then -- any HPMs available? + csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter + end if; + + -- machine performance-monitoring event selector (r/w) -- + -- -------------------------------------------------------------------- + when csr_mhpmevent3_c => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(00); else NULL; end if; + when csr_mhpmevent4_c => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(01); else NULL; end if; + when csr_mhpmevent5_c => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(02); else NULL; end if; + when csr_mhpmevent6_c => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(03); else NULL; end if; + when csr_mhpmevent7_c => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(04); else NULL; end if; + when csr_mhpmevent8_c => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(05); else NULL; end if; + when csr_mhpmevent9_c => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(06); else NULL; end if; + when csr_mhpmevent10_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(07); else NULL; end if; + when csr_mhpmevent11_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(08); else NULL; end if; + when csr_mhpmevent12_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(09); else NULL; end if; + when csr_mhpmevent13_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(10); else NULL; end if; + when csr_mhpmevent14_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(11); else NULL; end if; + when csr_mhpmevent15_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(12); else NULL; end if; + when csr_mhpmevent16_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(13); else NULL; end if; + when csr_mhpmevent17_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(14); else NULL; end if; + when csr_mhpmevent18_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(15); else NULL; end if; + when csr_mhpmevent19_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(16); else NULL; end if; + when csr_mhpmevent20_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(17); else NULL; end if; + when csr_mhpmevent21_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(18); else NULL; end if; + when csr_mhpmevent22_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(19); else NULL; end if; + when csr_mhpmevent23_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(20); else NULL; end if; + when csr_mhpmevent24_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(21); else NULL; end if; + when csr_mhpmevent25_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(22); else NULL; end if; + when csr_mhpmevent26_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(23); else NULL; end if; + when csr_mhpmevent27_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(24); else NULL; end if; + when csr_mhpmevent28_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(25); else NULL; end if; + when csr_mhpmevent29_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(26); else NULL; end if; + when csr_mhpmevent30_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(27); else NULL; end if; + when csr_mhpmevent31_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(28); else NULL; end if; + + -- counters and timers -- + -- -------------------------------------------------------------------- + when csr_cycle_c | csr_mcycle_c => -- [m]cycle (r/w): Cycle counter LOW + if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if; + when csr_cycleh_c | csr_mcycleh_c => -- [m]cycleh (r/w): Cycle counter HIGH + if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if; + + when csr_instret_c | csr_minstret_c => -- [m]instret (r/w): Instructions-retired counter LOW + if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if; + when csr_instreth_c | csr_minstreth_c => -- [m]instreth (r/w): Instructions-retired counter HIGH + if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.minstreth(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if; + + when csr_time_c => -- time (r/-): System time LOW (from MTIME unit) + if (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata <= time_i(31 downto 00); else NULL; end if; + when csr_timeh_c => -- timeh (r/-): System time HIGH (from MTIME unit) + if (CPU_EXTENSION_RISCV_Zicntr = true) then csr.rdata <= time_i(63 downto 32); else NULL; end if; + + -- hardware performance counters -- + -- -------------------------------------------------------------------- + -- low word (r/w) -- + when csr_mhpmcounter3_c => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(00); else NULL; end if; + when csr_mhpmcounter4_c => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(01); else NULL; end if; + when csr_mhpmcounter5_c => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(02); else NULL; end if; + when csr_mhpmcounter6_c => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(03); else NULL; end if; + when csr_mhpmcounter7_c => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(04); else NULL; end if; + when csr_mhpmcounter8_c => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(05); else NULL; end if; + when csr_mhpmcounter9_c => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(06); else NULL; end if; + when csr_mhpmcounter10_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(07); else NULL; end if; + when csr_mhpmcounter11_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(08); else NULL; end if; + when csr_mhpmcounter12_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(09); else NULL; end if; + when csr_mhpmcounter13_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(10); else NULL; end if; + when csr_mhpmcounter14_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(11); else NULL; end if; + when csr_mhpmcounter15_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(12); else NULL; end if; + when csr_mhpmcounter16_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(13); else NULL; end if; + when csr_mhpmcounter17_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(14); else NULL; end if; + when csr_mhpmcounter18_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(15); else NULL; end if; + when csr_mhpmcounter19_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(16); else NULL; end if; + when csr_mhpmcounter20_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(17); else NULL; end if; + when csr_mhpmcounter21_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(18); else NULL; end if; + when csr_mhpmcounter22_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(19); else NULL; end if; + when csr_mhpmcounter23_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(20); else NULL; end if; + when csr_mhpmcounter24_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(21); else NULL; end if; + when csr_mhpmcounter25_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(22); else NULL; end if; + when csr_mhpmcounter26_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(23); else NULL; end if; + when csr_mhpmcounter27_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(24); else NULL; end if; + when csr_mhpmcounter28_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(25); else NULL; end if; + when csr_mhpmcounter29_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(26); else NULL; end if; + when csr_mhpmcounter30_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(27); else NULL; end if; + when csr_mhpmcounter31_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm = true) then csr.rdata <= csr.mhpmcounter_rd(28); else NULL; end if; + -- high word (r/w) -- + when csr_mhpmcounter3h_c => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(00); else NULL; end if; + when csr_mhpmcounter4h_c => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(01); else NULL; end if; + when csr_mhpmcounter5h_c => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(02); else NULL; end if; + when csr_mhpmcounter6h_c => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(03); else NULL; end if; + when csr_mhpmcounter7h_c => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(04); else NULL; end if; + when csr_mhpmcounter8h_c => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(05); else NULL; end if; + when csr_mhpmcounter9h_c => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(06); else NULL; end if; + when csr_mhpmcounter10h_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(07); else NULL; end if; + when csr_mhpmcounter11h_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(08); else NULL; end if; + when csr_mhpmcounter12h_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(09); else NULL; end if; + when csr_mhpmcounter13h_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(10); else NULL; end if; + when csr_mhpmcounter14h_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(11); else NULL; end if; + when csr_mhpmcounter15h_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(12); else NULL; end if; + when csr_mhpmcounter16h_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(13); else NULL; end if; + when csr_mhpmcounter17h_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(14); else NULL; end if; + when csr_mhpmcounter18h_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(15); else NULL; end if; + when csr_mhpmcounter19h_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(16); else NULL; end if; + when csr_mhpmcounter20h_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(17); else NULL; end if; + when csr_mhpmcounter21h_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(18); else NULL; end if; + when csr_mhpmcounter22h_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(19); else NULL; end if; + when csr_mhpmcounter23h_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(20); else NULL; end if; + when csr_mhpmcounter24h_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(21); else NULL; end if; + when csr_mhpmcounter25h_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(22); else NULL; end if; + when csr_mhpmcounter26h_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(23); else NULL; end if; + when csr_mhpmcounter27h_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(24); else NULL; end if; + when csr_mhpmcounter28h_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(25); else NULL; end if; + when csr_mhpmcounter29h_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(26); else NULL; end if; + when csr_mhpmcounter30h_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(27); else NULL; end if; + when csr_mhpmcounter31h_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm = true) and (hpm_cnt_hi_width_c > 0) then csr.rdata <= csr.mhpmcounterh_rd(28); else NULL; end if; + + -- machine information registers -- + -- -------------------------------------------------------------------- +-- when csr_mvendorid_c => NULL; -- mvendorid (r/-): vendor ID, implemented but always zero + when csr_marchid_c => csr.rdata(4 downto 0) <= "10011"; -- marchid (r/-): arch ID - official RISC-V open-source arch ID + when csr_mimpid_c => csr.rdata <= hw_version_c; -- mimpid (r/-): implementation ID -- NEORV32 hardware version + when csr_mhartid_c => csr.rdata <= std_ulogic_vector(to_unsigned(HW_THREAD_ID, 32)); -- mhartid (r/-): hardware thread ID +-- when csr_mconfigptr_c => NULL; -- mconfigptr (r/-): machine configuration pointer register, implemented but always zero + + -- debug mode CSRs -- + -- -------------------------------------------------------------------- + when csr_dcsr_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dcsr_rd; else NULL; end if; -- dcsr (r/w): debug mode control and status + when csr_dpc_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dpc; else NULL; end if; -- dpc (r/w): debug mode program counter + when csr_dscratch0_c => if (CPU_EXTENSION_RISCV_DEBUG = true) then csr.rdata <= csr.dscratch0; else NULL; end if; -- dscratch0 (r/w): debug mode scratch register 0 + + -- undefined/unavailable -- + -- -------------------------------------------------------------------- + when others => + NULL; -- not implemented, read as zero + + end case; + end if; + end if; + end process csr_read_access; + + -- CSR read data output -- + csr_rdata_o <= csr.rdata; + + + -- Debug Control -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + debug_control: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + debug_ctrl.state <= DEBUG_OFFLINE; + debug_ctrl.ext_halt_req <= '0'; + elsif rising_edge(clk_i) then + if (CPU_EXTENSION_RISCV_DEBUG = true) then + + -- external halt request (from Debug Module) -- + debug_ctrl.ext_halt_req <= db_halt_req_i; + + -- state machine -- + case debug_ctrl.state is + + when DEBUG_OFFLINE => -- not in debug mode, waiting for entering request + if (debug_ctrl.trig_halt = '1') or -- external request (from DM) + (debug_ctrl.trig_break = '1') or -- ebreak instruction + (debug_ctrl.trig_step = '1') then -- single-stepping mode + debug_ctrl.state <= DEBUG_PENDING; + end if; + + when DEBUG_PENDING => -- waiting to start debug mode + if (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause(5) = '1') then -- processing trap entry into debug mode + debug_ctrl.state <= DEBUG_ONLINE; + end if; + + when DEBUG_ONLINE => -- we are in debug mode + if (debug_ctrl.dret = '1') then -- DRET instruction + debug_ctrl.state <= DEBUG_EXIT; + end if; + + when DEBUG_EXIT => -- leaving debug mode + if (execute_engine.state = TRAP_EXECUTE) then -- processing trap exit + debug_ctrl.state <= DEBUG_OFFLINE; + end if; + + when others => -- undefined + debug_ctrl.state <= DEBUG_OFFLINE; + + end case; + else -- debug mode NOT implemented + debug_ctrl.state <= DEBUG_OFFLINE; + debug_ctrl.ext_halt_req <= '0'; + end if; + end if; + end process debug_control; + + -- state decoding -- + debug_ctrl.pending <= '1' when (debug_ctrl.state = DEBUG_PENDING) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; + debug_ctrl.running <= '1' when ((debug_ctrl.state = DEBUG_ONLINE) or (debug_ctrl.state = DEBUG_EXIT)) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; + + -- entry debug mode triggers -- + debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- we are in debug mode: re-enter debug mode + (csr.priv_m_mode and csr.dcsr_ebreakm and (not debug_ctrl.running)) or -- enabled goto-debug-mode in machine mode on "ebreak" + (csr.priv_u_mode and csr.dcsr_ebreaku and (not debug_ctrl.running))); -- enabled goto-debug-mode in user mode on "ebreak" + debug_ctrl.trig_halt <= debug_ctrl.ext_halt_req and (not debug_ctrl.running); -- external halt request (if not halted already) + debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode) + + + -- Debug Control and Status Register (dcsr) - Read-Back ----------------------------------- + -- ------------------------------------------------------------------------------------------- + dcsr_readback_false: + if (CPU_EXTENSION_RISCV_DEBUG = false) generate + csr.dcsr_rd <= (others => '-'); + end generate; + + dcsr_readback_true: + if (CPU_EXTENSION_RISCV_DEBUG = true) generate + csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec + csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved + csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter) + csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented + csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented + csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter) + csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping + csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME ??? + csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual + csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause + csr.dcsr_rd(05) <= '0'; -- reserved + csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode + csr.dcsr_rd(03) <= '0'; -- nmip: pending non-maskable interrupt + csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode + csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered + end generate; + + +end neorv32_cpu_control_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_bitmanip.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_bitmanip.vhd new file mode 100644 index 0000000..8412c5e --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_bitmanip.vhd @@ -0,0 +1,469 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU Co-Processor: Bit-Manipulation Co-Processor Unit (RISC-V "B" Extension) >> # +-- # ********************************************************************************************* # +-- # The bit manipulation unit is implemented as co-processor that has a processing latency of 1 # +-- # cycle for logic/arithmetic operations and 3+shamt (=shift amount) cycles for shift(-related) # +-- # operations. Use the FAST_SHIFT_EN option to reduce shift-related instruction's latency to a # +-- # fixed value of 3 cycles latency (using barrel shifters). # +-- # # +-- # Supported sub-extensions (Zb*): # +-- # - Zba: Address generation instructions # +-- # - Zbb: Basic bit-manipulation instructions # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_cp_bitmanip is + generic ( + FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + shamt_i : in std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); -- shift amount + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + valid_o : out std_ulogic -- data output valid + ); +end neorv32_cpu_cp_bitmanip; + +architecture neorv32_cpu_cp_bitmanip_rtl of neorv32_cpu_cp_bitmanip is + + -- Sub-extension configuration -- + constant zbb_en_c : boolean := true; + constant zba_en_c : boolean := true; + -- --------------------------- -- + + -- commands: Zbb - logic with negate -- + constant op_andn_c : natural := 0; + constant op_orn_c : natural := 1; + constant op_xnor_c : natural := 2; + -- commands: Zbb - count leading/trailing zero bits -- + constant op_clz_c : natural := 3; + constant op_ctz_c : natural := 4; + -- commands: Zbb - count population -- + constant op_cpop_c : natural := 5; + -- commands: Zbb - integer minimum/maximum -- + constant op_max_c : natural := 6; -- signed/unsigned + constant op_min_c : natural := 7; -- signed/unsigned + -- commands: Zbb - sign- and zero-extension -- + constant op_sextb_c : natural := 8; + constant op_sexth_c : natural := 9; + constant op_zexth_c : natural := 10; + -- commands: Zbb - bitwise rotation -- + constant op_rol_c : natural := 11; + constant op_ror_c : natural := 12; -- rori + -- commands: Zbb - or-combine -- + constant op_orcb_c : natural := 13; + -- commands: Zbb - byte-reverse -- + constant op_rev8_c : natural := 14; + -- commands: Zba - shifted add -- + constant op_sh1add_c : natural := 15; + constant op_sh2add_c : natural := 16; + constant op_sh3add_c : natural := 17; + -- + constant op_width_c : natural := 18; + + -- controller -- + type ctrl_state_t is (S_IDLE, S_START_SHIFT, S_BUSY_SHIFT); + signal ctrl_state : ctrl_state_t; + signal cmd, cmd_buf : std_ulogic_vector(op_width_c-1 downto 0); + signal valid : std_ulogic; + + -- operand buffers -- + signal rs1_reg : std_ulogic_vector(data_width_c-1 downto 0); + signal rs2_reg : std_ulogic_vector(data_width_c-1 downto 0); + signal sha_reg : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); + signal less_ff : std_ulogic; + + -- serial shifter -- + type shifter_t is record + start : std_ulogic; + run : std_ulogic; + bcnt : std_ulogic_vector(index_size_f(data_width_c) downto 0); -- bit counter + cnt : std_ulogic_vector(index_size_f(data_width_c) downto 0); -- iteration counter + cnt_max : std_ulogic_vector(index_size_f(data_width_c) downto 0); + sreg : std_ulogic_vector(data_width_c-1 downto 0); + end record; + signal shifter : shifter_t; + + -- barrel shifter -- + type bs_level_t is array (index_size_f(data_width_c) downto 0) of std_ulogic_vector(data_width_c-1 downto 0); + signal bs_level : bs_level_t; + + -- operation results -- + type res_t is array (0 to op_width_c-1) of std_ulogic_vector(data_width_c-1 downto 0); + signal res_int, res_out : res_t; + + -- shifted-add unit -- + signal adder_core : std_ulogic_vector(data_width_c-1 downto 0); + +begin + + -- Sub-Extension Configuration ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + assert false report + "Implementing bit-manipulation (B) sub-extensions: " & + cond_sel_string_f(zbb_en_c, "Zbb", "") & + cond_sel_string_f(zba_en_c, "Zba", "") & + "" + severity note; + + + -- Instruction Decoding (One-Hot) --------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- a minimal decoding logic is used here -> just to distinguish between B.Zbb instructions + -- a more specific decoding and instruction check is done by the CPU control unit + + -- Zbb - Basic bit-manipulation instructions -- + cmd(op_andn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "11") else '0'; + cmd(op_orn_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "10") else '0'; + cmd(op_xnor_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "10") and (ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) = "00") else '0'; + -- + cmd(op_max_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_1_c) = '1') else '0'; + cmd(op_min_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '1') and (ctrl_i(ctrl_ir_funct3_1_c) = '0') else '0'; + cmd(op_zexth_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "00") and (ctrl_i(ctrl_ir_funct12_5_c) = '0') else '0'; + -- + cmd(op_orcb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') else '0'; + -- + cmd(op_clz_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "000") else '0'; + cmd(op_ctz_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "001") else '0'; + cmd(op_cpop_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "010") else '0'; + cmd(op_sextb_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "100") else '0'; + cmd(op_sexth_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c) = '0') and (ctrl_i(ctrl_ir_funct12_2_c downto ctrl_ir_funct12_0_c) = "101") else '0'; + cmd(op_rol_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "001") and (ctrl_i(ctrl_ir_opcode7_5_c) = '1') else '0'; + cmd(op_ror_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "101") else '0'; + cmd(op_rev8_c) <= '1' when (zbb_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "11") and (ctrl_i(ctrl_ir_funct12_7_c) = '1') else '0'; + + -- Zba - Address generation instructions -- + cmd(op_sh1add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "01") else '0'; + cmd(op_sh2add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "10") else '0'; + cmd(op_sh3add_c) <= '1' when (zba_en_c = true) and (ctrl_i(ctrl_ir_funct12_10_c downto ctrl_ir_funct12_9_c) = "01") and (ctrl_i(ctrl_ir_funct12_7_c) = '0') and (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) = "11") else '0'; + + + -- Co-Processor Controller ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + coprocessor_ctrl: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl_state <= S_IDLE; + cmd_buf <= (others => def_rst_val_c); + rs1_reg <= (others => def_rst_val_c); + rs2_reg <= (others => def_rst_val_c); + sha_reg <= (others => def_rst_val_c); + less_ff <= def_rst_val_c; + shifter.start <= '0'; + valid <= '0'; + elsif rising_edge(clk_i) then + -- defaults -- + shifter.start <= '0'; + valid <= '0'; + + -- fsm -- + case ctrl_state is + + when S_IDLE => -- wait for operation trigger + -- ------------------------------------------------------------ + if (start_i = '1') then + less_ff <= cmp_i(cmp_less_c); + cmd_buf <= cmd; + rs1_reg <= rs1_i; + rs2_reg <= rs2_i; + sha_reg <= shamt_i; + if ((cmd(op_clz_c) or cmd(op_ctz_c) or cmd(op_cpop_c) or cmd(op_ror_c) or cmd(op_rol_c)) = '1') then -- multi-cycle shift operation + if (FAST_SHIFT_EN = false) then -- default: iterative computation + shifter.start <= '1'; + ctrl_state <= S_START_SHIFT; + else -- full-parallel computation + ctrl_state <= S_BUSY_SHIFT; + end if; + else + valid <= '1'; + ctrl_state <= S_IDLE; + end if; + end if; + + when S_START_SHIFT => -- one cycle delay to start shift operation + -- ------------------------------------------------------------ + ctrl_state <= S_BUSY_SHIFT; + + when S_BUSY_SHIFT => -- wait for multi-cycle shift operation to finish + -- ------------------------------------------------------------ + if (shifter.run = '0') then + valid <= '1'; + ctrl_state <= S_IDLE; + end if; + + when others => -- undefined + -- ------------------------------------------------------------ + ctrl_state <= S_IDLE; + + end case; + end if; + end process coprocessor_ctrl; + + + -- Shifter Function Core (iterative: small but slow) -------------------------------------- + -- ------------------------------------------------------------------------------------------- + serial_shifter: + if (FAST_SHIFT_EN = false) generate + shifter_unit: process(rstn_i, clk_i) + variable new_bit_v : std_ulogic; + begin + if (rstn_i = '0') then + shifter.cnt <= (others => def_rst_val_c); + shifter.sreg <= (others => def_rst_val_c); + shifter.cnt_max <= (others => def_rst_val_c); + shifter.bcnt <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + if (shifter.start = '1') then -- trigger new shift + shifter.cnt <= (others => '0'); + -- shift operand -- + if (cmd_buf(op_clz_c) = '1') or (cmd_buf(op_rol_c) = '1') then -- count LEADING zeros / rotate LEFT + shifter.sreg <= bit_rev_f(rs1_reg); -- reverse - we can only do right shifts here + else -- ctz, cpop, ror + shifter.sreg <= rs1_reg; + end if; + -- max shift amount -- + if (cmd_buf(op_cpop_c) = '1') then -- population count + shifter.cnt_max <= (others => '0'); + shifter.cnt_max(shifter.cnt_max'left) <= '1'; + else + shifter.cnt_max <= '0' & sha_reg; + end if; + shifter.bcnt <= (others => '0'); + elsif (shifter.run = '1') then -- right shifts only + new_bit_v := ((cmd_buf(op_ror_c) or cmd_buf(op_rol_c)) and shifter.sreg(0)) or (cmd_buf(op_clz_c) or cmd_buf(op_ctz_c)); + shifter.sreg <= new_bit_v & shifter.sreg(shifter.sreg'left downto 1); -- ro[r/l]/lsr(for counting) + shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) + 1); -- iteration counter + if (shifter.sreg(0) = '1') then + shifter.bcnt <= std_ulogic_vector(unsigned(shifter.bcnt) + 1); -- bit counter + end if; + end if; + end if; + end process shifter_unit; + end generate; + + -- run control -- + serial_shifter_ctrl: + if (FAST_SHIFT_EN = false) generate + shifter_unit_ctrl: process(cmd_buf, shifter) + begin + -- keep shifting until ... -- + if (cmd_buf(op_clz_c) = '1') or (cmd_buf(op_ctz_c) = '1') then -- count leading/trailing zeros + shifter.run <= not shifter.sreg(0); + else -- population count / rotate + if (shifter.cnt = shifter.cnt_max) then + shifter.run <= '0'; + else + shifter.run <= '1'; + end if; + end if; + end process shifter_unit_ctrl; + end generate; + + + -- Shifter Function Core (parallel: fast but large) --------------------------------------- + -- ------------------------------------------------------------------------------------------- + barrel_shifter_async_sync: + if (FAST_SHIFT_EN = true) generate + shifter_unit_fast: process(rstn_i, clk_i) + variable new_bit_v : std_ulogic; + begin + if (rstn_i = '0') then + shifter.cnt <= (others => def_rst_val_c); + shifter.sreg <= (others => def_rst_val_c); + shifter.bcnt <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + -- population count -- + shifter.bcnt <= std_ulogic_vector(to_unsigned(popcount_f(rs1_reg), shifter.bcnt'length)); + -- count leading/trailing zeros -- + if cmd_buf(op_clz_c) = '1' then -- leading + shifter.cnt <= std_ulogic_vector(to_unsigned(leading_zeros_f(rs1_reg), shifter.cnt'length)); + else -- trailing + shifter.cnt <= std_ulogic_vector(to_unsigned(leading_zeros_f(bit_rev_f(rs1_reg)), shifter.cnt'length)); + end if; + -- barrel shifter -- + shifter.sreg <= bs_level(0); -- rol/ror[i] + end if; + end process shifter_unit_fast; + shifter.run <= '0'; -- we are done already! + end generate; + + -- barrel shifter array -- + barrel_shifter_async: + if (FAST_SHIFT_EN = true) generate + shifter_unit_async: process(rs1_reg, sha_reg, cmd_buf, bs_level) + begin + -- input level: convert left shifts to right shifts -- + if (cmd_buf(op_rol_c) = '1') then -- is left shift? + bs_level(index_size_f(data_width_c)) <= bit_rev_f(rs1_reg); -- reverse bit order of input operand + else + bs_level(index_size_f(data_width_c)) <= rs1_reg; + end if; + + -- shifter array -- + for i in index_size_f(data_width_c)-1 downto 0 loop + if (sha_reg(i) = '1') then + bs_level(i)(data_width_c-1 downto data_width_c-(2**i)) <= bs_level(i+1)((2**i)-1 downto 0); + bs_level(i)((data_width_c-(2**i))-1 downto 0) <= bs_level(i+1)(data_width_c-1 downto 2**i); + else + bs_level(i) <= bs_level(i+1); + end if; + end loop; + end process shifter_unit_async; + end generate; + + + -- Shifted-Add Core ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + shift_adder: process(rs1_reg, rs2_reg, ctrl_i) + variable opb_v : std_ulogic_vector(data_width_c-1 downto 0); + begin + case ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_1_c) is + when "01" => opb_v := rs1_reg(rs1_reg'left-1 downto 0) & '0'; -- << 1 + when "10" => opb_v := rs1_reg(rs1_reg'left-2 downto 0) & "00"; -- << 2 + when "11" => opb_v := rs1_reg(rs1_reg'left-3 downto 0) & "000"; -- << 3 + when others => opb_v := rs1_reg(rs1_reg'left-1 downto 0) & '0'; -- undefined + end case; + adder_core <= std_ulogic_vector(unsigned(rs2_reg) + unsigned(opb_v)); + end process shift_adder; + + + -- Operation Results ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- logic with negate -- + res_int(op_andn_c) <= rs1_reg and (not rs2_reg); -- logical and-not + res_int(op_orn_c) <= rs1_reg or (not rs2_reg); -- logical or-not + res_int(op_xnor_c) <= rs1_reg xor (not rs2_reg); -- logical xor-not + + -- count leading/trailing zeros -- + res_int(op_clz_c)(data_width_c-1 downto shifter.cnt'left+1) <= (others => '0'); + res_int(op_clz_c)(shifter.cnt'left downto 0) <= shifter.cnt; + res_int(op_ctz_c) <= (others => '0'); -- unused/redundant + + -- count set bits -- + res_int(op_cpop_c)(data_width_c-1 downto shifter.bcnt'left+1) <= (others => '0'); + res_int(op_cpop_c)(shifter.bcnt'left downto 0) <= shifter.bcnt; + + -- min/max select -- + res_int(op_min_c) <= rs1_reg when ((less_ff xor cmd_buf(op_max_c)) = '1') else rs2_reg; + res_int(op_max_c) <= (others => '0'); -- unused/redundant + + -- sign-extension -- + res_int(op_sextb_c)(data_width_c-1 downto 8) <= (others => rs1_reg(7)); + res_int(op_sextb_c)(7 downto 0) <= rs1_reg(7 downto 0); -- sign-extend byte + res_int(op_sexth_c)(data_width_c-1 downto 16) <= (others => rs1_reg(15)); + res_int(op_sexth_c)(15 downto 0) <= rs1_reg(15 downto 0); -- sign-extend half-word + res_int(op_zexth_c)(data_width_c-1 downto 16) <= (others => '0'); + res_int(op_zexth_c)(15 downto 0) <= rs1_reg(15 downto 0); -- zero-extend half-word + + -- rotate right/left -- + res_int(op_ror_c) <= shifter.sreg; + res_int(op_rol_c) <= bit_rev_f(shifter.sreg); -- reverse to compensate internal right-only shifts + + -- or-combine.byte -- + or_combine_gen: + for i in 0 to (data_width_c/8)-1 generate -- sub-byte loop + res_int(op_orcb_c)(i*8+7 downto i*8) <= (others => or_reduce_f(rs1_reg(i*8+7 downto i*8))); + end generate; -- i + + -- reversal.8 (byte swap) -- + res_int(op_rev8_c) <= bswap32_f(rs1_reg); + + -- address generation instructions -- + res_int(op_sh1add_c) <= adder_core; + res_int(op_sh2add_c) <= (others => '0'); -- unused/redundant + res_int(op_sh3add_c) <= (others => '0'); -- unused/redundant + + + -- Output Selector ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + res_out(op_andn_c) <= res_int(op_andn_c) when (cmd_buf(op_andn_c) = '1') else (others => '0'); + res_out(op_orn_c) <= res_int(op_orn_c) when (cmd_buf(op_orn_c) = '1') else (others => '0'); + res_out(op_xnor_c) <= res_int(op_xnor_c) when (cmd_buf(op_xnor_c) = '1') else (others => '0'); + res_out(op_clz_c) <= res_int(op_clz_c) when ((cmd_buf(op_clz_c) or cmd_buf(op_ctz_c)) = '1') else (others => '0'); + res_out(op_ctz_c) <= (others => '0'); -- unused/redundant + res_out(op_cpop_c) <= res_int(op_cpop_c) when (cmd_buf(op_cpop_c) = '1') else (others => '0'); + res_out(op_min_c) <= res_int(op_min_c) when ((cmd_buf(op_min_c) or cmd_buf(op_max_c)) = '1') else (others => '0'); + res_out(op_max_c) <= (others => '0'); -- unused/redundant + res_out(op_sextb_c) <= res_int(op_sextb_c) when (cmd_buf(op_sextb_c) = '1') else (others => '0'); + res_out(op_sexth_c) <= res_int(op_sexth_c) when (cmd_buf(op_sexth_c) = '1') else (others => '0'); + res_out(op_zexth_c) <= res_int(op_zexth_c) when (cmd_buf(op_zexth_c) = '1') else (others => '0'); + res_out(op_ror_c) <= res_int(op_ror_c) when (cmd_buf(op_ror_c) = '1') else (others => '0'); + res_out(op_rol_c) <= res_int(op_rol_c) when (cmd_buf(op_rol_c) = '1') else (others => '0'); + res_out(op_orcb_c) <= res_int(op_orcb_c) when (cmd_buf(op_orcb_c) = '1') else (others => '0'); + res_out(op_rev8_c) <= res_int(op_rev8_c) when (cmd_buf(op_rev8_c) = '1') else (others => '0'); + -- + res_out(op_sh1add_c) <= res_int(op_sh1add_c) when ((cmd_buf(op_sh1add_c) or cmd_buf(op_sh2add_c) or cmd_buf(op_sh3add_c)) = '1') else (others => '0'); + res_out(op_sh2add_c) <= (others => '0'); -- unused/redundant + res_out(op_sh3add_c) <= (others => '0'); -- unused/redundant + + + -- Output Gate ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + output_gate: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + res_o <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + res_o <= (others => '0'); + if (valid = '1') then + res_o <= res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or + res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here + res_out(op_min_c) or -- res_out(op_max_c) is unused here + res_out(op_sextb_c) or res_out(op_sexth_c) or res_out(op_zexth_c) or + res_out(op_ror_c) or res_out(op_rol_c) or + res_out(op_orcb_c) or res_out(op_rev8_c) or + res_out(op_sh1add_c); -- res_out(op_sh2add_c) and res_out(op_sh3add_c) are unused here + end if; + end if; + end process output_gate; + + -- valid output -- + valid_o <= valid; + + +end neorv32_cpu_cp_bitmanip_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_fpu.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_fpu.vhd new file mode 100644 index 0000000..1604207 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_fpu.vhd @@ -0,0 +1,1847 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU Co-Processor: Single-Prec. Floating Point Unit (RISC-V "Zfinx" Extension) >> # +-- # ********************************************************************************************* # +-- # The Zfinx floating-point extension uses the integer register file (x) for all FP operations. # +-- # See the official RISC-V specs (https://github.com/riscv/riscv-zfinx) for more information. # +-- # # +-- # Design Notes: # +-- # * This FPU is based on a multi-cycle architecture and is NOT suited for pipelined operations. # +-- # * The hardware design goal was SIZE (performance comes second). All shift operations are done # +-- # using an iterative approach (one bit per clock cycle, no barrel shifters!). # +-- # * Multiplication (FMUL instruction) will infer DSP blocks (if available). # +-- # * Subnormal numbers are not supported yet - they are "flushed to zero" before entering the # +-- # actual FPU core. # +-- # * Division and sqare root operations (FDIV, FSQRT) and fused multiply-accumulate operations # +-- # (F[N]MADD) are not supported yet - they will raise an illegal instruction exception. # +-- # * Rounding mode <100> ("round to nearest, ties to max magnitude") is not supported yet. # +-- # * Signaling NaNs (sNaN) will not be generated by the hardware at all. However, if inserted by # +-- # the programmer they are handled correctly. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_cp_fpu is + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags + valid_o : out std_ulogic -- data output valid + ); +end neorv32_cpu_cp_fpu; + +architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is + + -- FPU core functions -- + constant op_class_c : std_ulogic_vector(2 downto 0) := "000"; + constant op_comp_c : std_ulogic_vector(2 downto 0) := "001"; + constant op_i2f_c : std_ulogic_vector(2 downto 0) := "010"; + constant op_f2i_c : std_ulogic_vector(2 downto 0) := "011"; + constant op_sgnj_c : std_ulogic_vector(2 downto 0) := "100"; + constant op_minmax_c : std_ulogic_vector(2 downto 0) := "101"; + constant op_addsub_c : std_ulogic_vector(2 downto 0) := "110"; + constant op_mul_c : std_ulogic_vector(2 downto 0) := "111"; + + -- float-to-integer unit -- + component neorv32_cpu_cp_fpu_f2i + port ( + -- control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + start_i : in std_ulogic; -- trigger operation + rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + funct_i : in std_ulogic; -- 0=signed, 1=unsigned + -- input -- + sign_i : in std_ulogic; -- sign + exponent_i : in std_ulogic_vector(07 downto 0); -- exponent + mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa + class_i : in std_ulogic_vector(09 downto 0); -- operand class + -- output -- + result_o : out std_ulogic_vector(31 downto 0); -- integer result + flags_o : out std_ulogic_vector(04 downto 0); -- exception flags + done_o : out std_ulogic -- operation done + ); + end component; + + -- normalizer + rounding unit -- + component neorv32_cpu_cp_fpu_normalizer + port ( + -- control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + start_i : in std_ulogic; -- trigger operation + rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float) + -- input -- + sign_i : in std_ulogic; -- sign + exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent + mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa + integer_i : in std_ulogic_vector(31 downto 0); -- integer input + class_i : in std_ulogic_vector(09 downto 0); -- input number class + flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input + -- output -- + result_o : out std_ulogic_vector(31 downto 0); -- result (float or int) + flags_o : out std_ulogic_vector(04 downto 0); -- exception flags + done_o : out std_ulogic -- operation done + ); + end component; + + -- commands (one-hot) -- + type cmd_t is record + instr_class : std_ulogic; + instr_sgnj : std_ulogic; + instr_comp : std_ulogic; + instr_i2f : std_ulogic; + instr_f2i : std_ulogic; + instr_minmax : std_ulogic; + instr_addsub : std_ulogic; + instr_mul : std_ulogic; + funct : std_ulogic_vector(2 downto 0); + end record; + signal cmd : cmd_t; + signal funct_ff : std_ulogic_vector(2 downto 0); + + -- co-processor control engine -- + type ctrl_state_t is (S_IDLE, S_BUSY); + type ctrl_engine_t is record + state : ctrl_state_t; + start : std_ulogic; + valid : std_ulogic; + end record; + signal ctrl_engine : ctrl_engine_t; + + -- floating-point operands -- + type op_data_t is array (0 to 1) of std_ulogic_vector(31 downto 0); + type op_class_t is array (0 to 1) of std_ulogic_vector(09 downto 0); + type fpu_operands_t is record + rs1 : std_ulogic_vector(31 downto 0); -- operand 1 + rs1_class : std_ulogic_vector(09 downto 0); -- operand 1 number class + rs2 : std_ulogic_vector(31 downto 0); -- operand 2 + rs2_class : std_ulogic_vector(09 downto 0); -- operand 2 number class + frm : std_ulogic_vector(02 downto 0); -- rounding mode + end record; + signal op_data : op_data_t; + signal op_class : op_class_t; + signal fpu_operands : fpu_operands_t; + + -- floating-point comparator -- + signal cmp_ff : std_ulogic_vector(01 downto 0); + signal comp_equal_ff : std_ulogic; + signal comp_less_ff : std_ulogic; + + -- functional units interface -- + type fu_interface_t is record + result : std_ulogic_vector(31 downto 0); + flags : std_ulogic_vector(04 downto 0); + start : std_ulogic; + done : std_ulogic; + end record; + signal fu_classify : fu_interface_t; + signal fu_compare : fu_interface_t; + signal fu_sign_inject : fu_interface_t; + signal fu_min_max : fu_interface_t; + signal fu_conv_f2i : fu_interface_t; + signal fu_addsub : fu_interface_t; + signal fu_mul : fu_interface_t; + signal fu_core_done : std_ulogic; -- FU operation completed + + -- integer-to-float -- + type fu_i2f_interface_t is record + result : std_ulogic_vector(31 downto 0); + sign : std_ulogic; + start : std_ulogic; + done : std_ulogic; + end record; + signal fu_conv_i2f : fu_i2f_interface_t; -- float result + + -- multiplier unit -- + type multiplier_t is record + opa : unsigned(23 downto 0); -- mantissa A plus hidden one + opb : unsigned(23 downto 0); -- mantissa B plus hidden one + buf_ff : unsigned(47 downto 0); -- product buffer + sign : std_ulogic; -- resulting sign + product : std_ulogic_vector(47 downto 0); -- product + exp_sum : std_ulogic_vector(08 downto 0); -- incl 1x overflow/underflow bit + exp_res : std_ulogic_vector(09 downto 0); -- resulting exponent incl 2x overflow/underflow bit + -- + res_class : std_ulogic_vector(09 downto 0); + flags : std_ulogic_vector(04 downto 0); -- exception flags + -- + start : std_ulogic; + latency : std_ulogic_vector(02 downto 0); -- unit latency + done : std_ulogic; + end record; + signal multiplier : multiplier_t; + + -- adder/subtractor unit -- + type addsub_t is record + -- input comparison -- + exp_comp : std_ulogic_vector(01 downto 0); -- equal & less + small_exp : std_ulogic_vector(07 downto 0); + small_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one + large_exp : std_ulogic_vector(07 downto 0); + large_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one + -- smaller mantissa alginment -- + man_sreg : std_ulogic_vector(23 downto 0); -- mantissa + hidden one + man_g_ext : std_ulogic; + man_r_ext : std_ulogic; + man_s_ext : std_ulogic; + exp_cnt : std_ulogic_vector(08 downto 0); + -- adder/subtractor stage -- + man_comp : std_ulogic; + man_s : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS + man_l : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS + add_stage : std_ulogic_vector(27 downto 0); -- adder result incl. overflow + -- result -- + res_sign : std_ulogic; + res_sum : std_ulogic_vector(27 downto 0); -- mantissa sum (+1 bit) + GRS bits (for rounding) + res_class : std_ulogic_vector(09 downto 0); + flags : std_ulogic_vector(04 downto 0); -- exception flags + -- arbitration -- + start : std_ulogic; + latency : std_ulogic_vector(04 downto 0); -- unit latency + done : std_ulogic; + end record; + signal addsub : addsub_t; + + -- normalizer interface (normalization & rounding and int-to-float) -- + type normalizer_t is record + start : std_ulogic; + mode : std_ulogic; + sign : std_ulogic; + xexp : std_ulogic_vector(08 downto 0); + xmantissa : std_ulogic_vector(47 downto 0); + result : std_ulogic_vector(31 downto 0); + class : std_ulogic_vector(09 downto 0); + flags_in : std_ulogic_vector(04 downto 0); + flags_out : std_ulogic_vector(04 downto 0); + done : std_ulogic; + end record; + signal normalizer : normalizer_t; + +begin + +-- **************************************************************************************************************************** +-- Control +-- **************************************************************************************************************************** + + -- Instruction Decoding ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- one-hot re-encoding -- + cmd.instr_class <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11100") else '0'; + cmd.instr_comp <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "10100") else '0'; + cmd.instr_i2f <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11010") else '0'; + cmd.instr_f2i <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11000") else '0'; + cmd.instr_sgnj <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00100") else '0'; + cmd.instr_minmax <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00101") else '0'; + cmd.instr_addsub <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_8_c) = "0000") else '0'; + cmd.instr_mul <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00010") else '0'; + + -- binary re-encoding -- + cmd.funct <= op_mul_c when (cmd.instr_mul = '1') else + op_addsub_c when (cmd.instr_addsub = '1') else + op_minmax_c when (cmd.instr_minmax = '1') else + op_sgnj_c when (cmd.instr_sgnj = '1') else + op_f2i_c when (cmd.instr_f2i = '1') else + op_i2f_c when (cmd.instr_i2f = '1') else + op_comp_c when (cmd.instr_comp = '1') else + op_class_c;--when (cmd.instr_class = '1') else (others => '-'); + + + -- Input Operands: Check for subnormal numbers (flush to zero) ---------------------------- + -- ------------------------------------------------------------------------------------------- + -- Subnormal numbers are not supported and are "flushed to zero"! FIXME / TODO + -- rs1 -- + op_data(0)(31) <= rs1_i(31); + op_data(0)(30 downto 23) <= rs1_i(30 downto 23); + op_data(0)(22 downto 00) <= (others => '0') when (rs1_i(30 downto 23) = "00000000") else rs1_i(22 downto 0); -- flush mantissa to zero if subnormal + -- rs2 -- + op_data(1)(31) <= rs2_i(31); + op_data(1)(30 downto 23) <= rs2_i(30 downto 23); + op_data(1)(22 downto 00) <= (others => '0') when (rs2_i(30 downto 23) = "00000000") else rs2_i(22 downto 0); -- flush mantissa to zero if subnormal + + + -- Number Classifier ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + number_classifier: process(op_data) + variable op_m_all_zero_v, op_e_all_zero_v, op_e_all_one_v : std_ulogic; + variable op_is_zero_v, op_is_inf_v, op_is_denorm_v, op_is_nan_v : std_ulogic; + begin + for i in 0 to 1 loop -- for rs1 and rs2 inputs + -- check for all-zero/all-one -- + op_m_all_zero_v := not or_reduce_f(op_data(i)(22 downto 00)); + op_e_all_zero_v := not or_reduce_f(op_data(i)(30 downto 23)); + op_e_all_one_v := and_reduce_f(op_data(i)(30 downto 23)); + + -- check special cases -- + op_is_zero_v := op_e_all_zero_v and op_m_all_zero_v; -- zero + op_is_inf_v := op_e_all_one_v and op_m_all_zero_v; -- infinity + op_is_denorm_v := '0'; -- FIXME / TODO -- op_e_all_zero_v and (not op_m_all_zero_v); -- subnormal + op_is_nan_v := op_e_all_one_v and (not op_m_all_zero_v); -- NaN + + -- actual attributes -- + op_class(i)(fp_class_neg_inf_c) <= op_data(i)(31) and op_is_inf_v; -- negative infinity + op_class(i)(fp_class_neg_norm_c) <= op_data(i)(31) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- negative normal number + op_class(i)(fp_class_neg_denorm_c) <= op_data(i)(31) and op_is_denorm_v; -- negative subnormal number + op_class(i)(fp_class_neg_zero_c) <= op_data(i)(31) and op_is_zero_v; -- negative zero + op_class(i)(fp_class_pos_zero_c) <= (not op_data(i)(31)) and op_is_zero_v; -- positive zero + op_class(i)(fp_class_pos_denorm_c) <= (not op_data(i)(31)) and op_is_denorm_v; -- positive subnormal number + op_class(i)(fp_class_pos_norm_c) <= (not op_data(i)(31)) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- positive normal number + op_class(i)(fp_class_pos_inf_c) <= (not op_data(i)(31)) and op_is_inf_v; -- positive infinity + op_class(i)(fp_class_snan_c) <= op_is_nan_v and (not op_data(i)(22)); -- signaling NaN + op_class(i)(fp_class_qnan_c) <= op_is_nan_v and ( op_data(i)(22)); -- quiet NaN + end loop; -- i + end process number_classifier; + + + -- Co-Processor Control Engine ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + control_engine_fsm: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl_engine.state <= S_IDLE; + ctrl_engine.start <= '0'; + fpu_operands.frm <= (others => def_rst_val_c); + fpu_operands.rs1 <= (others => def_rst_val_c); + fpu_operands.rs1_class <= (others => def_rst_val_c); + fpu_operands.rs2 <= (others => def_rst_val_c); + fpu_operands.rs2_class <= (others => def_rst_val_c); + funct_ff <= (others => def_rst_val_c); + cmp_ff <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + -- arbiter defaults -- + ctrl_engine.valid <= '0'; + ctrl_engine.start <= '0'; + + -- state machine -- + case ctrl_engine.state is + + when S_IDLE => -- waiting for operation trigger + -- ------------------------------------------------------------ + funct_ff <= cmd.funct; -- actual operation to execute + cmp_ff <= cmp_i; -- main ALU comparator + -- rounding mode -- + -- TODO / FIXME "round to nearest, ties to max magnitude" (0b100) is not supported yet + if (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "111") then + fpu_operands.frm <= '0' & ctrl_i(ctrl_alu_frm1_c downto ctrl_alu_frm0_c); + else + fpu_operands.frm <= '0' & ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c); + end if; + -- + if (start_i = '1') then + -- operand data -- + fpu_operands.rs1 <= op_data(0); + fpu_operands.rs1_class <= op_class(0); + fpu_operands.rs2 <= op_data(1); + fpu_operands.rs2_class <= op_class(1); + -- execute! -- + ctrl_engine.start <= '1'; + ctrl_engine.state <= S_BUSY; + end if; + + when S_BUSY => -- operation in progress (multi-cycle) + -- ----------------------------------------------------------- + if (fu_core_done = '1') then -- processing done? + ctrl_engine.valid <= '1'; + ctrl_engine.state <= S_IDLE; + end if; + + when others => -- undefined + -- ------------------------------------------------------------ + ctrl_engine.state <= S_IDLE; + + end case; + end if; + end process control_engine_fsm; + + -- operation done / valid output -- + valid_o <= ctrl_engine.valid; + + + -- Functional Unit Interface (operation-start trigger) ------------------------------------ + -- ------------------------------------------------------------------------------------------- + fu_classify.start <= ctrl_engine.start and cmd.instr_class; + fu_compare.start <= ctrl_engine.start and cmd.instr_comp; + fu_sign_inject.start <= ctrl_engine.start and cmd.instr_sgnj; + fu_min_max.start <= ctrl_engine.start and cmd.instr_minmax; + fu_conv_i2f.start <= ctrl_engine.start and cmd.instr_i2f; + fu_conv_f2i.start <= ctrl_engine.start and cmd.instr_f2i; + fu_addsub.start <= ctrl_engine.start and cmd.instr_addsub; + fu_mul.start <= ctrl_engine.start and cmd.instr_mul; + + +-- **************************************************************************************************************************** +-- FPU Core - Functional Units +-- **************************************************************************************************************************** + + -- Number Classifier (FCLASS) ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + fu_classify.flags <= (others => '0'); -- does not generate flags at all + fu_classify.result(31 downto 10) <= (others => '0'); + fu_classify.result(09 downto 00) <= fpu_operands.rs1_class; + fu_classify.done <= fu_classify.start; + + + -- Floating-Point Comparator -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + float_comparator: process(rstn_i, clk_i) + variable cond_v : std_ulogic_vector(1 downto 0); + begin + if (rstn_i = '0') then + comp_equal_ff <= def_rst_val_c; + comp_less_ff <= def_rst_val_c; + fu_compare.done <= def_rst_val_c; + fu_min_max.done <= def_rst_val_c; + elsif rising_edge(clk_i) then + -- equal -- + if ((fpu_operands.rs1_class(fp_class_pos_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf == +inf + ((fpu_operands.rs1_class(fp_class_neg_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf == -inf + (((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and + ((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) or -- +/-zero == +/-zero + (cmp_ff(cmp_equal_c) = '1') then -- identical in every way (comparator result from main ALU) + comp_equal_ff <= '1'; + else + comp_equal_ff <= '0'; + end if; + + -- less than -- + if ((fpu_operands.rs1_class(fp_class_pos_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf !< +inf + ((fpu_operands.rs1_class(fp_class_neg_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf !< -inf + (((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and + ((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) then -- +/-zero !< +/-zero + comp_less_ff <= '0'; + else + cond_v := fpu_operands.rs1(31) & fpu_operands.rs2(31); + case cond_v is + when "10" => comp_less_ff <= '1'; -- rs1 negative, rs2 positive + when "01" => comp_less_ff <= '0'; -- rs1 positive, rs2 negative + when "00" => comp_less_ff <= cmp_ff(cmp_less_c); -- both positive (comparator result from main ALU) + when "11" => comp_less_ff <= not cmp_ff(cmp_less_c); -- both negative (comparator result from main ALU) + when others => comp_less_ff <= '0'; -- undefined + end case; + end if; + + -- comparator latency -- + fu_compare.done <= fu_compare.start; -- for actual comparison operation + fu_min_max.done <= fu_min_max.start; -- for min/max operations + end if; + end process float_comparator; + + + -- Comparison (FEQ/FLT/FLE) --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + float_comparison: process(fpu_operands, ctrl_i, comp_equal_ff, comp_less_ff) + variable snan_v : std_ulogic; -- at least one input is sNaN + variable qnan_v : std_ulogic; -- at least one input is qNaN + begin + -- check for NaN -- + snan_v := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_snan_c); + qnan_v := fpu_operands.rs1_class(fp_class_qnan_c) or fpu_operands.rs2_class(fp_class_qnan_c); + + -- condition evaluation -- + fu_compare.result <= (others => '0'); + case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is + when "00" => -- FLE: less than or equal + fu_compare.result(0) <= (comp_less_ff or comp_equal_ff) and (not (snan_v or qnan_v)); -- result is zero if either input is NaN + when "01" => -- FLT: less than + fu_compare.result(0) <= comp_less_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN + when "10" => -- FEQ: equal + fu_compare.result(0) <= comp_equal_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN + when others => -- undefined + fu_compare.result(0) <= '0'; + end case; + end process float_comparison; + + -- latency -- + -- -> done in "float_comparator" + + -- exceptions -- + fu_compare.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions + + + -- Min/Max Select (FMIN/FMAX) ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + min_max_select: process(fpu_operands, comp_less_ff, fu_compare, ctrl_i) + variable cond_v : std_ulogic_vector(2 downto 0); + begin + -- comparison restul - check for special cases: -0 is less than +0 + if ((fpu_operands.rs1_class(fp_class_neg_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_zero_c) = '1')) then + cond_v(0) := ctrl_i(ctrl_ir_funct3_0_c); + elsif ((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1')) then + cond_v(0) := not ctrl_i(ctrl_ir_funct3_0_c); + else -- "normal= comparison + cond_v(0) := comp_less_ff xnor ctrl_i(ctrl_ir_funct3_0_c); -- min/max select + end if; + + -- nmumber NaN check -- + cond_v(2) := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs1_class(fp_class_qnan_c); + cond_v(1) := fpu_operands.rs2_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_qnan_c); + + -- data output -- + case cond_v is + when "000" => fu_min_max.result <= fpu_operands.rs1; + when "001" => fu_min_max.result <= fpu_operands.rs2; + when "010" | "011" => fu_min_max.result <= fpu_operands.rs1; -- if one input is NaN output the non-NaN one + when "100" | "101" => fu_min_max.result <= fpu_operands.rs2; -- if one input is NaN output the non-NaN one + when others => fu_min_max.result <= fp_single_qnan_c; -- output quiet NaN if both inputs are NaN + end case; + end process min_max_select; + + -- latency -- + -- -> done in "float_comparator" + + -- exceptions -- + fu_min_max.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions + + + -- Convert: Float to [unsigned] Integer (FCVT.S.W) ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_cp_fpu_f2i_inst: neorv32_cpu_cp_fpu_f2i + port map ( + -- control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + start_i => fu_conv_f2i.start, -- trigger operation + rmode_i => fpu_operands.frm, -- rounding mode + funct_i => ctrl_i(ctrl_ir_funct12_0_c), -- 0=signed, 1=unsigned + -- input -- + sign_i => fpu_operands.rs1(31), -- sign + exponent_i => fpu_operands.rs1(30 downto 23), -- exponent + mantissa_i => fpu_operands.rs1(22 downto 00), -- mantissa + class_i => fpu_operands.rs1_class, -- operand class + -- output -- + result_o => fu_conv_f2i.result, -- integer result + flags_o => fu_conv_f2i.flags, -- exception flags + done_o => fu_conv_f2i.done -- operation done + ); + + + -- Sign-Injection (FSGNJ) ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + sign_injector: process(ctrl_i, fpu_operands) + begin + case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is + when "00" => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- FSGNJ + when "01" => fu_sign_inject.result(31) <= not fpu_operands.rs2(31); -- FSGNJN + when "10" => fu_sign_inject.result(31) <= fpu_operands.rs1(31) xor fpu_operands.rs2(31); -- FSGNJX + when others => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- undefined + end case; + fu_sign_inject.result(30 downto 0) <= fpu_operands.rs1(30 downto 0); + fu_sign_inject.flags <= (others => '0'); -- does not generate flags + end process sign_injector; + + -- latency -- + fu_sign_inject.done <= fu_sign_inject.start; + + + -- Convert: [unsigned] Integer to Float (FCVT.W.S) ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + convert_i2f: process(rstn_i, clk_i) + begin + -- this process only computes the absolute input value + -- the actual conversion is done by the normalizer + if (rstn_i = '0') then + fu_conv_i2f.result <= (others => def_rst_val_c); + fu_conv_i2f.sign <= def_rst_val_c; + elsif rising_edge(clk_i) then + if (ctrl_i(ctrl_ir_funct12_0_c) = '0') and (rs1_i(31) = '1') then -- convert signed integer + fu_conv_i2f.result <= std_ulogic_vector(0 - unsigned(rs1_i)); + fu_conv_i2f.sign <= rs1_i(31); -- original sign + else -- convert unsigned integer + fu_conv_i2f.result <= rs1_i; + fu_conv_i2f.sign <= '0'; + end if; + fu_conv_i2f.done <= fu_conv_i2f.start; -- actual conversion is done by the normalizer unit + end if; + end process convert_i2f; + + + -- Multiplier Core (FMUL) ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + multiplier_core: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + multiplier.opa <= (others => '-'); -- these might be DSP regs! + multiplier.opb <= (others => '-'); -- these might be DSP regs! + multiplier.buf_ff <= (others => '-'); -- these might be DSP regs! + multiplier.product <= (others => '-'); -- these might be DSP regs! + multiplier.sign <= def_rst_val_c; + multiplier.exp_res <= (others => def_rst_val_c); + multiplier.flags(fp_exc_of_c) <= def_rst_val_c; + multiplier.flags(fp_exc_uf_c) <= def_rst_val_c; + multiplier.flags(fp_exc_nv_c) <= def_rst_val_c; + multiplier.latency <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + -- multiplier core -- + if (multiplier.start = '1') then -- FIXME / TODO remove buffer? + multiplier.opa <= unsigned('1' & fpu_operands.rs1(22 downto 0)); -- append hidden one + multiplier.opb <= unsigned('1' & fpu_operands.rs2(22 downto 0)); -- append hidden one + end if; + multiplier.buf_ff <= multiplier.opa * multiplier.opb; + multiplier.product <= std_ulogic_vector(multiplier.buf_ff(47 downto 0)); -- let the register balancing do the magic here + multiplier.sign <= fpu_operands.rs1(31) xor fpu_operands.rs2(31); -- resulting sign + + -- exponent computation -- + multiplier.exp_res <= std_ulogic_vector(unsigned('0' & multiplier.exp_sum) - 127); + if (multiplier.exp_res(multiplier.exp_res'left) = '1') then -- underflow (exp_res is "negative") + multiplier.flags(fp_exc_of_c) <= '0'; + multiplier.flags(fp_exc_uf_c) <= '1'; + elsif (multiplier.exp_res(multiplier.exp_res'left-1) = '1') then -- overflow + multiplier.flags(fp_exc_of_c) <= '1'; + multiplier.flags(fp_exc_uf_c) <= '0'; + else + multiplier.flags(fp_exc_of_c) <= '0'; + multiplier.flags(fp_exc_uf_c) <= '0'; + end if; + + -- invalid operation -- + multiplier.flags(fp_exc_nv_c) <= + ((fpu_operands.rs1_class(fp_class_pos_zero_c) or fpu_operands.rs1_class(fp_class_neg_zero_c)) and + (fpu_operands.rs2_class(fp_class_pos_inf_c) or fpu_operands.rs2_class(fp_class_neg_inf_c))) or -- mul(+/-zero, +/-inf) + ((fpu_operands.rs1_class(fp_class_pos_inf_c) or fpu_operands.rs1_class(fp_class_neg_inf_c)) and + (fpu_operands.rs2_class(fp_class_pos_zero_c) or fpu_operands.rs2_class(fp_class_neg_zero_c))); -- mul(+/-inf, +/-zero) + + -- latency shift register -- + multiplier.latency <= multiplier.latency(multiplier.latency'left-1 downto 0) & multiplier.start; + end if; + end process multiplier_core; + + -- exponent sum -- + multiplier.exp_sum <= std_ulogic_vector(unsigned('0' & fpu_operands.rs1(30 downto 23)) + unsigned('0' & fpu_operands.rs2(30 downto 23))); + + -- latency -- + multiplier.start <= fu_mul.start; + multiplier.done <= multiplier.latency(multiplier.latency'left); + fu_mul.done <= multiplier.done; + + -- unused exception flags -- + multiplier.flags(fp_exc_dz_c) <= '0'; -- division by zero: not possible here + multiplier.flags(fp_exc_nx_c) <= '0'; -- inexcat: not possible here + + + -- result class -- + multiplier_class_core: process(rstn_i, clk_i) + variable a_pos_norm_v, a_neg_norm_v, b_pos_norm_v, b_neg_norm_v : std_ulogic; + variable a_pos_subn_v, a_neg_subn_v, b_pos_subn_v, b_neg_subn_v : std_ulogic; + variable a_pos_zero_v, a_neg_zero_v, b_pos_zero_v, b_neg_zero_v : std_ulogic; + variable a_pos_inf_v, a_neg_inf_v, b_pos_inf_v, b_neg_inf_v : std_ulogic; + variable a_snan_v, a_qnan_v, b_snan_v, b_qnan_v : std_ulogic; + begin + if (rstn_i = '0') then + multiplier.res_class(fp_class_pos_norm_c) <= def_rst_val_c; + multiplier.res_class(fp_class_neg_norm_c) <= def_rst_val_c; + multiplier.res_class(fp_class_pos_inf_c) <= def_rst_val_c; + multiplier.res_class(fp_class_neg_inf_c) <= def_rst_val_c; + multiplier.res_class(fp_class_pos_zero_c) <= def_rst_val_c; + multiplier.res_class(fp_class_neg_zero_c) <= def_rst_val_c; + elsif rising_edge(clk_i) then + -- minions -- + a_pos_norm_v := fpu_operands.rs1_class(fp_class_pos_norm_c); b_pos_norm_v := fpu_operands.rs2_class(fp_class_pos_norm_c); + a_neg_norm_v := fpu_operands.rs1_class(fp_class_neg_norm_c); b_neg_norm_v := fpu_operands.rs2_class(fp_class_neg_norm_c); + a_pos_subn_v := fpu_operands.rs1_class(fp_class_pos_denorm_c); b_pos_subn_v := fpu_operands.rs2_class(fp_class_pos_denorm_c); + a_neg_subn_v := fpu_operands.rs1_class(fp_class_neg_denorm_c); b_neg_subn_v := fpu_operands.rs2_class(fp_class_neg_denorm_c); + a_pos_zero_v := fpu_operands.rs1_class(fp_class_pos_zero_c); b_pos_zero_v := fpu_operands.rs2_class(fp_class_pos_zero_c); + a_neg_zero_v := fpu_operands.rs1_class(fp_class_neg_zero_c); b_neg_zero_v := fpu_operands.rs2_class(fp_class_neg_zero_c); + a_pos_inf_v := fpu_operands.rs1_class(fp_class_pos_inf_c); b_pos_inf_v := fpu_operands.rs2_class(fp_class_pos_inf_c); + a_neg_inf_v := fpu_operands.rs1_class(fp_class_neg_inf_c); b_neg_inf_v := fpu_operands.rs2_class(fp_class_neg_inf_c); + a_snan_v := fpu_operands.rs1_class(fp_class_snan_c); b_snan_v := fpu_operands.rs2_class(fp_class_snan_c); + a_qnan_v := fpu_operands.rs1_class(fp_class_qnan_c); b_qnan_v := fpu_operands.rs2_class(fp_class_qnan_c); + + -- +normal -- + multiplier.res_class(fp_class_pos_norm_c) <= + (a_pos_norm_v and b_pos_norm_v) or -- +norm * +norm + (a_neg_norm_v and b_neg_norm_v); -- -norm * -norm + -- -normal -- + multiplier.res_class(fp_class_neg_norm_c) <= + (a_pos_norm_v and b_neg_norm_v) or -- +norm * -norm + (a_neg_norm_v and b_pos_norm_v); -- -norm * +norm + + -- +infinity -- + multiplier.res_class(fp_class_pos_inf_c) <= + (a_pos_inf_v and b_pos_inf_v) or -- +inf * +inf + (a_neg_inf_v and b_neg_inf_v) or -- -inf * -inf + (a_pos_norm_v and b_pos_inf_v) or -- +norm * +inf + (a_pos_inf_v and b_pos_norm_v) or -- +inf * +norm + (a_neg_norm_v and b_neg_inf_v) or -- -norm * -inf + (a_neg_inf_v and b_neg_norm_v) or -- -inf * -norm + (a_neg_subn_v and b_neg_inf_v) or -- -denorm * -inf + (a_neg_inf_v and b_neg_subn_v); -- -inf * -denorm + -- -infinity -- + multiplier.res_class(fp_class_neg_inf_c) <= + (a_pos_inf_v and b_neg_inf_v) or -- +inf * -inf + (a_neg_inf_v and b_pos_inf_v) or -- -inf * +inf + (a_pos_norm_v and b_neg_inf_v) or -- +norm * -inf + (a_neg_inf_v and b_pos_norm_v) or -- -inf * +norm + (a_neg_norm_v and b_pos_inf_v) or -- -norm * +inf + (a_pos_inf_v and b_neg_norm_v) or -- +inf * -norm + (a_pos_subn_v and b_neg_inf_v) or -- +denorm * -inf + (a_neg_inf_v and b_pos_subn_v) or -- -inf * +de-norm + (a_neg_subn_v and b_pos_inf_v) or -- -denorm * +inf + (a_pos_inf_v and b_neg_subn_v); -- +inf * -de-norm + + -- +zero -- + multiplier.res_class(fp_class_pos_zero_c) <= + (a_pos_zero_v and b_pos_zero_v) or -- +zero * +zero + (a_pos_zero_v and b_pos_norm_v) or -- +zero * +norm + (a_pos_zero_v and b_pos_subn_v) or -- +zero * +denorm + (a_neg_zero_v and b_neg_zero_v) or -- -zero * -zero + (a_neg_zero_v and b_neg_norm_v) or -- -zero * -norm + (a_neg_zero_v and b_neg_subn_v) or -- -zero * -denorm + (a_pos_norm_v and b_pos_zero_v) or -- +norm * +zero + (a_pos_subn_v and b_pos_zero_v) or -- +denorm * +zero + (a_neg_norm_v and b_neg_zero_v) or -- -norm * -zero + (a_neg_subn_v and b_neg_zero_v); -- -denorm * -zero + + -- -zero -- + multiplier.res_class(fp_class_neg_zero_c) <= + (a_pos_zero_v and b_neg_zero_v) or -- +zero * -zero + (a_pos_zero_v and b_neg_norm_v) or -- +zero * -norm + (a_pos_zero_v and b_neg_subn_v) or -- +zero * -denorm + (a_neg_zero_v and b_pos_zero_v) or -- -zero * +zero + (a_neg_zero_v and b_pos_norm_v) or -- -zero * +norm + (a_neg_zero_v and b_pos_subn_v) or -- -zero * +denorm + (a_neg_norm_v and b_pos_zero_v) or -- -norm * +zero + (a_neg_subn_v and b_pos_zero_v) or -- -denorm * +zero + (a_pos_norm_v and b_neg_zero_v) or -- +norm * -zero + (a_pos_subn_v and b_neg_zero_v); -- +denorm * -zero + + -- sNaN -- + multiplier.res_class(fp_class_snan_c) <= (a_snan_v or b_snan_v); -- any input is sNaN + -- qNaN -- + multiplier.res_class(fp_class_qnan_c) <= + (a_snan_v or b_snan_v) or -- any input is sNaN + (a_qnan_v or b_qnan_v) or -- nay input is qNaN + ((a_pos_inf_v or a_neg_inf_v) and (b_pos_zero_v or b_neg_zero_v)) or -- +/-inf * +/-zero + ((a_pos_zero_v or a_neg_zero_v) and (b_pos_inf_v or b_neg_inf_v)); -- +/-zero * +/-inf + end if; + end process multiplier_class_core; + + -- subnormal result -- + multiplier.res_class(fp_class_pos_denorm_c) <= '0'; -- is evaluated by the normalizer + multiplier.res_class(fp_class_neg_denorm_c) <= '0'; -- is evaluated by the normalizer + + -- unused -- + fu_mul.result <= (others => '0'); + fu_mul.flags <= (others => '0'); + + + -- Adder/Subtractor Core (FADD, FSUB) ----------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + adder_subtractor_core: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + addsub.latency <= (others => def_rst_val_c); + addsub.exp_comp <= (others => def_rst_val_c); + addsub.man_sreg <= (others => def_rst_val_c); + addsub.exp_cnt <= (others => def_rst_val_c); + addsub.man_g_ext <= def_rst_val_c; + addsub.man_r_ext <= def_rst_val_c; + addsub.man_s_ext <= def_rst_val_c; + addsub.man_comp <= def_rst_val_c; + addsub.add_stage <= (others => def_rst_val_c); + addsub.res_sign <= def_rst_val_c; + addsub.flags(fp_exc_nv_c) <= def_rst_val_c; + elsif rising_edge(clk_i) then + -- arbitration / latency -- + if (ctrl_engine.state = S_IDLE) then -- hacky "reset" + addsub.latency <= (others => '0'); + else + addsub.latency(0) <= addsub.start; -- input comparator delay + if (addsub.latency(0) = '1') then + addsub.latency(1) <= '1'; + addsub.latency(2) <= '0'; + elsif (addsub.exp_cnt(7 downto 0) = addsub.large_exp) then -- radix point not yet aligned + addsub.latency(1) <= '0'; + addsub.latency(2) <= addsub.latency(1) and (not addsub.latency(0)); -- "shift done" + end if; + addsub.latency(3) <= addsub.latency(2); -- adder stage + addsub.latency(4) <= addsub.latency(3); -- final stage + end if; + + -- exponent check: find smaller number (radix-offset-only) -- + if (unsigned(fpu_operands.rs1(30 downto 23)) < unsigned(fpu_operands.rs2(30 downto 23))) then + addsub.exp_comp(0) <= '1'; -- rs1 < rs2 + else + addsub.exp_comp(0) <= '0'; -- rs1 >= rs2 + end if; + if (unsigned(fpu_operands.rs1(30 downto 23)) = unsigned(fpu_operands.rs2(30 downto 23))) then + addsub.exp_comp(1) <= '1'; -- rs1 == rs2 + else -- rs1 != rs2 + addsub.exp_comp(1) <= '0'; + end if; + + -- shift right small mantissa to align radix point -- + if (addsub.latency(0) = '1') then + if ((fpu_operands.rs1_class(fp_class_pos_zero_c) or fpu_operands.rs2_class(fp_class_pos_zero_c) or + fpu_operands.rs1_class(fp_class_neg_zero_c) or fpu_operands.rs2_class(fp_class_neg_zero_c)) = '0') then -- no input is zero + addsub.man_sreg <= addsub.small_man; + else + addsub.man_sreg <= (others => '0'); + end if; + addsub.exp_cnt <= '0' & addsub.small_exp; + addsub.man_g_ext <= '0'; + addsub.man_r_ext <= '0'; + addsub.man_s_ext <= '0'; + elsif (addsub.exp_cnt(7 downto 0) /= addsub.large_exp) then -- shift right until same magnitude + addsub.man_sreg <= '0' & addsub.man_sreg(addsub.man_sreg'left downto 1); + addsub.man_g_ext <= addsub.man_sreg(0); + addsub.man_r_ext <= addsub.man_g_ext; + addsub.man_s_ext <= addsub.man_s_ext or addsub.man_r_ext; -- sticky bit + addsub.exp_cnt <= std_ulogic_vector(unsigned(addsub.exp_cnt) + 1); + end if; + + -- mantissa check: find smaller number (magnitude-only) -- + if (unsigned(addsub.man_sreg) <= unsigned(addsub.large_man)) then + addsub.man_comp <= '1'; + else + addsub.man_comp <= '0'; + end if; + + -- actual addition/subtraction (incl. overflow) -- + if ((ctrl_i(ctrl_ir_funct12_7_c) xor (fpu_operands.rs1(31) xor fpu_operands.rs2(31))) = '0') then -- add + addsub.add_stage <= std_ulogic_vector(unsigned('0' & addsub.man_l) + unsigned('0' & addsub.man_s)); + else -- sub + addsub.add_stage <= std_ulogic_vector(unsigned('0' & addsub.man_l) - unsigned('0' & addsub.man_s)); + end if; + + -- result sign -- + if (ctrl_i(ctrl_ir_funct12_7_c) = '0') then -- add + if (fpu_operands.rs1(31) = fpu_operands.rs2(31)) then -- identical signs + addsub.res_sign <= fpu_operands.rs1(31); + else -- different signs + if (addsub.exp_comp(1) = '1') then -- exp are equal (also check relation of mantissas) + addsub.res_sign <= fpu_operands.rs1(31) xor (not addsub.man_comp); + else + addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0); + end if; + end if; + else -- sub + if (fpu_operands.rs1(31) = fpu_operands.rs2(31)) then -- identical signs + if (addsub.exp_comp(1) = '1') then -- exp are equal (also check relation of mantissas) + addsub.res_sign <= fpu_operands.rs1(31) xor (not addsub.man_comp); + else + addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0); + end if; + else -- different signs + addsub.res_sign <= fpu_operands.rs1(31); + end if; + end if; + + -- exception flags -- + addsub.flags(fp_exc_nv_c) <= ((fpu_operands.rs1_class(fp_class_pos_inf_c) or fpu_operands.rs1_class(fp_class_neg_inf_c)) and + (fpu_operands.rs2_class(fp_class_pos_inf_c) or fpu_operands.rs2_class(fp_class_neg_inf_c))); -- +/-inf +/- +/-inf + end if; + end process adder_subtractor_core; + + -- exceptions - unused -- + addsub.flags(fp_exc_dz_c) <= '0'; -- division by zero -> not possible + addsub.flags(fp_exc_of_c) <= '0'; -- not possible here (but may occur in normalizer) + addsub.flags(fp_exc_uf_c) <= '0'; -- not possible here (but may occur in normalizer) + addsub.flags(fp_exc_nx_c) <= '0'; -- not possible here (but may occur in normalizer) + + -- exponent check: find smaller number (magnitude-only) -- + addsub.small_exp <= fpu_operands.rs1(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs2(30 downto 23); + addsub.large_exp <= fpu_operands.rs2(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs1(30 downto 23); + addsub.small_man <= ('1' & fpu_operands.rs1(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs2(22 downto 00)); + addsub.large_man <= ('1' & fpu_operands.rs2(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs1(22 downto 00)); + + -- mantissa check: find smaller number (magnitude-only) -- + addsub.man_s <= (addsub.man_sreg & addsub.man_g_ext & addsub.man_r_ext & addsub.man_s_ext) when (addsub.man_comp = '1') else (addsub.large_man & "000"); + addsub.man_l <= (addsub.large_man & "000") when (addsub.man_comp = '1') else (addsub.man_sreg & addsub.man_g_ext & addsub.man_r_ext & addsub.man_s_ext); + + -- latency -- + addsub.start <= fu_addsub.start; + addsub.done <= addsub.latency(addsub.latency'left); + fu_addsub.done <= addsub.done; + + -- mantissa result -- + addsub.res_sum <= addsub.add_stage(27 downto 0); + + + -- result class -- + adder_subtractor_class_core: process(rstn_i, clk_i) + variable a_pos_norm_v, a_neg_norm_v, b_pos_norm_v, b_neg_norm_v : std_ulogic; + variable a_pos_subn_v, a_neg_subn_v, b_pos_subn_v, b_neg_subn_v : std_ulogic; + variable a_pos_zero_v, a_neg_zero_v, b_pos_zero_v, b_neg_zero_v : std_ulogic; + variable a_pos_inf_v, a_neg_inf_v, b_pos_inf_v, b_neg_inf_v : std_ulogic; + variable a_snan_v, a_qnan_v, b_snan_v, b_qnan_v : std_ulogic; + begin + if (rstn_i = '0') then + addsub.res_class(fp_class_pos_inf_c) <= def_rst_val_c; + addsub.res_class(fp_class_neg_inf_c) <= def_rst_val_c; + addsub.res_class(fp_class_pos_zero_c) <= def_rst_val_c; + addsub.res_class(fp_class_neg_zero_c) <= def_rst_val_c; + addsub.res_class(fp_class_qnan_c) <= def_rst_val_c; + elsif rising_edge(clk_i) then + -- minions -- + a_pos_norm_v := fpu_operands.rs1_class(fp_class_pos_norm_c); b_pos_norm_v := fpu_operands.rs2_class(fp_class_pos_norm_c); + a_neg_norm_v := fpu_operands.rs1_class(fp_class_neg_norm_c); b_neg_norm_v := fpu_operands.rs2_class(fp_class_neg_norm_c); + a_pos_subn_v := fpu_operands.rs1_class(fp_class_pos_denorm_c); b_pos_subn_v := fpu_operands.rs2_class(fp_class_pos_denorm_c); + a_neg_subn_v := fpu_operands.rs1_class(fp_class_neg_denorm_c); b_neg_subn_v := fpu_operands.rs2_class(fp_class_neg_denorm_c); + a_pos_zero_v := fpu_operands.rs1_class(fp_class_pos_zero_c); b_pos_zero_v := fpu_operands.rs2_class(fp_class_pos_zero_c); + a_neg_zero_v := fpu_operands.rs1_class(fp_class_neg_zero_c); b_neg_zero_v := fpu_operands.rs2_class(fp_class_neg_zero_c); + a_pos_inf_v := fpu_operands.rs1_class(fp_class_pos_inf_c); b_pos_inf_v := fpu_operands.rs2_class(fp_class_pos_inf_c); + a_neg_inf_v := fpu_operands.rs1_class(fp_class_neg_inf_c); b_neg_inf_v := fpu_operands.rs2_class(fp_class_neg_inf_c); + a_snan_v := fpu_operands.rs1_class(fp_class_snan_c); b_snan_v := fpu_operands.rs2_class(fp_class_snan_c); + a_qnan_v := fpu_operands.rs1_class(fp_class_qnan_c); b_qnan_v := fpu_operands.rs2_class(fp_class_qnan_c); + + if (ctrl_i(ctrl_ir_funct12_7_c) = '0') then -- addition + -- +infinity -- + addsub.res_class(fp_class_pos_inf_c) <= + (a_pos_inf_v and b_pos_inf_v) or -- +inf + +inf + (a_pos_inf_v and b_pos_zero_v) or -- +inf + +zero + (a_pos_zero_v and b_pos_inf_v) or -- +zero + +inf + (a_pos_inf_v and b_neg_zero_v) or -- +inf + -zero + (a_neg_zero_v and b_pos_inf_v) or -- -zero + +inf + -- + (a_pos_inf_v and b_pos_norm_v) or -- +inf + +norm + (a_pos_norm_v and b_pos_inf_v) or -- +norm + +inf + (a_pos_inf_v and b_pos_subn_v) or -- +inf + +denorm + (a_pos_subn_v and b_pos_inf_v) or -- +denorm + +inf + -- + (a_pos_inf_v and b_neg_norm_v) or -- +inf + -norm + (a_neg_norm_v and b_pos_inf_v) or -- -norm + +inf + (a_pos_inf_v and b_neg_subn_v) or -- +inf + -denorm + (a_neg_subn_v and b_pos_inf_v); -- -denorm + +inf + -- -infinity -- + addsub.res_class(fp_class_neg_inf_c) <= + (a_neg_inf_v and b_neg_inf_v) or -- -inf + -inf + (a_neg_inf_v and b_pos_zero_v) or -- -inf + +zero + (a_pos_zero_v and b_neg_inf_v) or -- +zero + -inf + (a_neg_inf_v and b_neg_zero_v) or -- -inf + -zero + (a_neg_zero_v and b_neg_inf_v) or -- -zero + -inf + -- + (a_neg_inf_v and b_pos_norm_v) or -- -inf + +norm + (a_pos_norm_v and b_neg_inf_v) or -- +norm + -inf + (a_neg_inf_v and b_neg_norm_v) or -- -inf + -norm + (a_neg_norm_v and b_neg_inf_v) or -- -norm + -inf + -- + (a_neg_inf_v and b_pos_subn_v) or -- -inf + +denorm + (a_pos_subn_v and b_neg_inf_v) or -- +denorm + -inf + (a_neg_inf_v and b_neg_subn_v) or -- -inf + -denorm + (a_neg_subn_v and b_neg_inf_v); -- -denorm + -inf + + -- +zero -- + addsub.res_class(fp_class_pos_zero_c) <= + (a_pos_zero_v and b_pos_zero_v) or -- +zero + +zero + (a_pos_zero_v and b_neg_zero_v) or -- +zero + -zero + (a_neg_zero_v and b_pos_zero_v); -- -zero + +zero + -- -zero -- + addsub.res_class(fp_class_neg_zero_c) <= + (a_neg_zero_v and b_neg_zero_v); -- -zero + -zero + + -- qNaN -- + addsub.res_class(fp_class_qnan_c) <= + (a_snan_v or b_snan_v) or -- any input is sNaN + (a_qnan_v or b_qnan_v) or -- any input is qNaN + (a_pos_inf_v and b_neg_inf_v) or -- +inf + -inf + (a_neg_inf_v and b_pos_inf_v); -- -inf + +inf + + else -- subtraction + -- +infinity -- + addsub.res_class(fp_class_pos_inf_c) <= + (a_pos_inf_v and b_neg_inf_v) or -- +inf - -inf + (a_pos_inf_v and b_pos_zero_v) or -- +inf - +zero + (a_pos_inf_v and b_neg_zero_v) or -- +inf - -zero + (a_pos_inf_v and b_pos_norm_v) or -- +inf - +norm + (a_pos_inf_v and b_pos_subn_v) or -- +inf - +denorm + (a_pos_inf_v and b_neg_norm_v) or -- +inf - -norm + (a_pos_inf_v and b_neg_subn_v) or -- +inf - -denorm + -- + (a_pos_zero_v and b_neg_inf_v) or -- +zero - -inf + (a_neg_zero_v and b_neg_inf_v) or -- -zero - -inf + -- + (a_pos_norm_v and b_neg_inf_v) or -- +norm - -inf + (a_pos_subn_v and b_neg_inf_v) or -- +denorm - -inf + (a_neg_norm_v and b_neg_inf_v) or -- -norm - -inf + (a_neg_subn_v and b_neg_inf_v); -- -denorm - -inf + -- -infinity -- + addsub.res_class(fp_class_neg_inf_c) <= + (a_neg_inf_v and b_pos_inf_v) or -- -inf - +inf + (a_neg_inf_v and b_pos_zero_v) or -- -inf - +zero + (a_neg_inf_v and b_neg_zero_v) or -- -inf - -zero + (a_neg_inf_v and b_pos_norm_v) or -- -inf - +norm + (a_neg_inf_v and b_pos_subn_v) or -- -inf - +denorm + (a_neg_inf_v and b_neg_norm_v) or -- -inf - -norm + (a_neg_inf_v and b_neg_subn_v) or -- -inf - -denorm + -- + (a_pos_zero_v and b_pos_inf_v) or -- +zero - +inf + (a_neg_zero_v and b_pos_inf_v) or -- -zero - +inf + -- + (a_pos_norm_v and b_pos_inf_v) or -- +norm - +inf + (a_pos_subn_v and b_pos_inf_v) or -- +denorm - +inf + (a_neg_norm_v and b_pos_inf_v) or -- -norm - +inf + (a_neg_subn_v and b_pos_inf_v); -- -denorm - +inf + + -- +zero -- + addsub.res_class(fp_class_pos_zero_c) <= + (a_pos_zero_v and b_pos_zero_v) or -- +zero - +zero + (a_pos_zero_v and b_neg_zero_v) or -- +zero - -zero + (a_neg_zero_v and b_neg_zero_v); -- -zero - -zero + -- -zero -- + addsub.res_class(fp_class_neg_zero_c) <= + (a_neg_zero_v and b_pos_zero_v); -- -zero - +zero + + -- qNaN -- + addsub.res_class(fp_class_qnan_c) <= + (a_snan_v or b_snan_v) or -- any input is sNaN + (a_qnan_v or b_qnan_v) or -- any input is qNaN + (a_pos_inf_v and b_pos_inf_v) or -- +inf - +inf + (a_neg_inf_v and b_neg_inf_v); -- -inf - -inf + end if; + + -- normal -- + addsub.res_class(fp_class_pos_norm_c) <= (a_pos_norm_v or a_neg_norm_v) and (b_pos_norm_v or b_neg_norm_v); -- +/-norm +/- +-/norm [sign is irrelevant here] + addsub.res_class(fp_class_neg_norm_c) <= (a_pos_norm_v or a_neg_norm_v) and (b_pos_norm_v or b_neg_norm_v); -- +/-norm +/- +-/norm [sign is irrelevant here] + + -- sNaN -- + addsub.res_class(fp_class_snan_c) <= (a_snan_v or b_snan_v); -- any input is sNaN + end if; + end process adder_subtractor_class_core; + + -- subnormal result -- + addsub.res_class(fp_class_pos_denorm_c) <= '0'; -- is evaluated by the normalizer + addsub.res_class(fp_class_neg_denorm_c) <= '0'; -- is evaluated by the normalizer + + -- unused -- + fu_addsub.result <= (others => '0'); + fu_addsub.flags <= (others => '0'); + + +-- **************************************************************************************************************************** +-- FPU Core - Normalize & Round +-- **************************************************************************************************************************** + + -- Normalizer Input ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + normalizer_input_select: process(funct_ff, addsub, multiplier, fu_conv_i2f) + begin + case funct_ff is + when op_addsub_c => -- addition/subtraction + normalizer.mode <= '0'; -- normalization + normalizer.sign <= addsub.res_sign; + normalizer.xexp <= addsub.exp_cnt; + normalizer.xmantissa(47 downto 23) <= addsub.res_sum(27 downto 3); + normalizer.xmantissa(22) <= addsub.res_sum(2); + normalizer.xmantissa(21) <= addsub.res_sum(1); + normalizer.xmantissa(20 downto 01) <= (others => '0'); + normalizer.xmantissa(00) <= addsub.res_sum(0); + normalizer.class <= addsub.res_class; + normalizer.flags_in <= addsub.flags; + normalizer.start <= addsub.done; + when op_mul_c => -- multiplication + normalizer.mode <= '0'; -- normalization + normalizer.sign <= multiplier.sign; + normalizer.xexp <= '0' & multiplier.exp_res(7 downto 0); + normalizer.xmantissa <= multiplier.product; + normalizer.class <= multiplier.res_class; + normalizer.flags_in <= multiplier.flags; + normalizer.start <= multiplier.done; + when others => -- op_i2f_c + normalizer.mode <= '1'; -- int_to_float + normalizer.sign <= fu_conv_i2f.sign; + normalizer.xexp <= "001111111"; -- bias = 127 + normalizer.xmantissa <= (others => '0'); -- don't care + normalizer.class <= (others => '0'); -- don't care + normalizer.flags_in <= (others => '0'); -- no flags yet + normalizer.start <= fu_conv_i2f.done; + end case; + end process normalizer_input_select; + + + -- Normalizer & Rounding Unit ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_cp_fpu_normalizer_inst: neorv32_cpu_cp_fpu_normalizer + port map ( + -- control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + start_i => normalizer.start, -- trigger operation + rmode_i => fpu_operands.frm, -- rounding mode + funct_i => normalizer.mode, -- operation mode + -- input -- + sign_i => normalizer.sign, -- sign + exponent_i => normalizer.xexp, -- extended exponent + mantissa_i => normalizer.xmantissa, -- extended mantissa + integer_i => fu_conv_i2f.result, -- integer input + class_i => normalizer.class, -- input number class + flags_i => normalizer.flags_in, -- exception flags input + -- output -- + result_o => normalizer.result, -- result (float or int) + flags_o => normalizer.flags_out, -- exception flags + done_o => normalizer.done -- operation done + ); + + +-- **************************************************************************************************************************** +-- FPU Core - Result +-- **************************************************************************************************************************** + + -- Result Output to CPU Pipeline ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + output_gate: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + res_o <= (others => def_rst_val_c); + fflags_o <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + if (ctrl_engine.valid = '1') then + case funct_ff is + when op_class_c => + res_o <= fu_classify.result; + fflags_o <= fu_classify.flags; + when op_comp_c => + res_o <= fu_compare.result; + fflags_o <= fu_compare.flags; + when op_f2i_c => + res_o <= fu_conv_f2i.result; + fflags_o <= fu_conv_f2i.flags; + when op_sgnj_c => + res_o <= fu_sign_inject.result; + fflags_o <= fu_sign_inject.flags; + when op_minmax_c => + res_o <= fu_min_max.result; + fflags_o <= fu_min_max.flags; + when others => -- op_mul_c, op_addsub_c, op_i2f_c, ... + res_o <= normalizer.result; + fflags_o <= normalizer.flags_out; + end case; + else + res_o <= (others => '0'); + fflags_o <= (others => '0'); + end if; + end if; + end process output_gate; + + -- operation done -- + fu_core_done <= fu_compare.done or fu_classify.done or fu_sign_inject.done or fu_min_max.done or normalizer.done or fu_conv_f2i.done; + + +end neorv32_cpu_cp_fpu_rtl; + +-- ########################################################################################################################################### +-- ########################################################################################################################################### + +-- ################################################################################################# +-- # << NEORV32 - Single-Precision Floating-Point Unit: Normalizer and Rounding Unit >> # +-- # ********************************************************************************************* # +-- # This unit also performs integer-to-float conversions. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_cp_fpu_normalizer is + port ( + -- control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + start_i : in std_ulogic; -- trigger operation + rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float) + -- input -- + sign_i : in std_ulogic; -- sign + exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent + mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa + integer_i : in std_ulogic_vector(31 downto 0); -- integer input + class_i : in std_ulogic_vector(09 downto 0); -- input number class + flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input + -- output -- + result_o : out std_ulogic_vector(31 downto 0); -- float result + flags_o : out std_ulogic_vector(04 downto 0); -- exception flags output + done_o : out std_ulogic -- operation done + ); +end neorv32_cpu_cp_fpu_normalizer; + +architecture neorv32_cpu_cp_fpu_normalizer_rtl of neorv32_cpu_cp_fpu_normalizer is + + -- controller -- + type ctrl_engine_state_t is (S_IDLE, S_PREPARE_I2F, S_CHECK_I2F, S_PREPARE_NORM, S_PREPARE_SHIFT, S_NORMALIZE_BUSY, S_ROUND, S_CHECK, S_FINALIZE); + type ctrl_t is record + state : ctrl_engine_state_t; -- current state + norm_r : std_ulogic; -- normalization round 0 or 1 + cnt : std_ulogic_vector(08 downto 0); -- interation counter/exponent (incl. overflow) + cnt_pre : std_ulogic_vector(08 downto 0); + cnt_of : std_ulogic; -- counter overflow + cnt_uf : std_ulogic; -- counter underflow + rounded : std_ulogic; -- output is rounded + res_sgn : std_ulogic; + res_exp : std_ulogic_vector(07 downto 0); + res_man : std_ulogic_vector(22 downto 0); + class : std_ulogic_vector(09 downto 0); + flags : std_ulogic_vector(04 downto 0); + end record; + signal ctrl : ctrl_t; + + -- normalization shift register -- + type sreg_t is record + done : std_ulogic; + dir : std_ulogic; -- shift direction: 0=right, 1=left + zero : std_ulogic; + upper : std_ulogic_vector(31 downto 0); + lower : std_ulogic_vector(22 downto 0); + ext_g : std_ulogic; -- guard bit + ext_r : std_ulogic; -- round bit + ext_s : std_ulogic; -- sticky bit + end record; + signal sreg : sreg_t; + + -- rounding unit -- + type round_t is record + en : std_ulogic; -- enable rounding + sub : std_ulogic; -- 0=decrement, 1=increment + output : std_ulogic_vector(24 downto 0); -- mantissa size + hidden one + 1 + end record; + signal round : round_t; + +begin + + -- Control Engine ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ctrl_engine: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl.state <= S_IDLE; + ctrl.norm_r <= def_rst_val_c; + ctrl.cnt <= (others => def_rst_val_c); + ctrl.cnt_pre <= (others => def_rst_val_c); + ctrl.cnt_of <= def_rst_val_c; + ctrl.cnt_uf <= def_rst_val_c; + ctrl.rounded <= def_rst_val_c; + ctrl.res_exp <= (others => def_rst_val_c); + ctrl.res_man <= (others => def_rst_val_c); + ctrl.res_sgn <= def_rst_val_c; + ctrl.class <= (others => def_rst_val_c); + ctrl.flags <= (others => def_rst_val_c); + -- + sreg.upper <= (others => def_rst_val_c); + sreg.lower <= (others => def_rst_val_c); + sreg.dir <= def_rst_val_c; + sreg.ext_g <= def_rst_val_c; + sreg.ext_r <= def_rst_val_c; + sreg.ext_s <= def_rst_val_c; + -- + done_o <= '0'; + elsif rising_edge(clk_i) then + -- defaults -- + ctrl.cnt_pre <= ctrl.cnt; + done_o <= '0'; + + -- exponent counter underflow/overflow -- + if ((ctrl.cnt_pre(8 downto 7) = "01") and (ctrl.cnt(8 downto 7) = "10")) then -- overflow + ctrl.cnt_of <= '1'; + elsif (ctrl.cnt_pre(8 downto 7) = "00") and (ctrl.cnt(8 downto 7) = "11") then -- underflow + ctrl.cnt_uf <= '1'; + end if; + + -- fsm -- + case ctrl.state is + + when S_IDLE => -- wait for operation trigger + -- ------------------------------------------------------------ + ctrl.norm_r <= '0'; -- start with first normalization + ctrl.rounded <= '0'; -- not rounded yet + ctrl.cnt_of <= '0'; + ctrl.cnt_uf <= '0'; + -- + if (start_i = '1') then + ctrl.cnt <= exponent_i; + ctrl.res_sgn <= sign_i; + ctrl.class <= class_i; + ctrl.flags <= flags_i; + if (funct_i = '0') then -- float -> float + ctrl.state <= S_PREPARE_NORM; + else -- integer -> float + ctrl.state <= S_PREPARE_I2F; + end if; + end if; + + when S_PREPARE_I2F => -- prepare integer-to-float conversion + -- ------------------------------------------------------------ + sreg.upper <= integer_i; + sreg.lower <= (others => '0'); + sreg.ext_g <= '0'; + sreg.ext_r <= '0'; + sreg.ext_s <= '0'; + sreg.dir <= '0'; -- shift right + ctrl.state <= S_CHECK_I2F; + + when S_CHECK_I2F => -- check if converting zero + -- ------------------------------------------------------------ + if (sreg.zero = '1') then -- all zero + ctrl.class(fp_class_pos_zero_c) <= '1'; + ctrl.state <= S_FINALIZE; + else + ctrl.state <= S_NORMALIZE_BUSY; + end if; + + when S_PREPARE_NORM => -- prepare "normal" normalization & rounding + -- ------------------------------------------------------------ + sreg.upper(31 downto 02) <= (others => '0'); + sreg.upper(01 downto 00) <= mantissa_i(47 downto 46); + sreg.lower <= mantissa_i(45 downto 23); + sreg.ext_g <= mantissa_i(22); + sreg.ext_r <= mantissa_i(21); + sreg.ext_s <= or_reduce_f(mantissa_i(20 downto 0)); + -- check for special cases -- + if ((ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c) or -- NaN + ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or -- zero + ctrl.class(fp_class_neg_denorm_c) or ctrl.class(fp_class_pos_denorm_c) or -- subnormal + ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or -- infinity + ctrl.flags(fp_exc_uf_c) or -- underflow + ctrl.flags(fp_exc_of_c) or -- overflow + ctrl.flags(fp_exc_nv_c)) = '1') then -- invalid + ctrl.state <= S_FINALIZE; + else + ctrl.state <= S_PREPARE_SHIFT; + end if; + + when S_PREPARE_SHIFT => -- prepare shift direction (for "normal" normalization only) + -- ------------------------------------------------------------ + if (sreg.zero = '0') then -- number < 1.0 + sreg.dir <= '0'; -- shift right + else -- number >= 1.0 + sreg.dir <= '1'; -- shift left + end if; + ctrl.state <= S_NORMALIZE_BUSY; + + when S_NORMALIZE_BUSY => -- running normalization cycle + -- ------------------------------------------------------------ + -- shift until normalized or exception -- + if (sreg.done = '1') or (ctrl.cnt_uf = '1') or (ctrl.cnt_of = '1') then + -- normalization control -- + ctrl.norm_r <= '1'; + if (ctrl.norm_r = '0') then -- first normalization cycle done + ctrl.state <= S_ROUND; + else -- second normalization cycle done + ctrl.state <= S_CHECK; + end if; + else + if (sreg.dir = '0') then -- shift right + ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) + 1); + sreg.upper <= '0' & sreg.upper(sreg.upper'left downto 1); + sreg.lower <= sreg.upper(0) & sreg.lower(sreg.lower'left downto 1); + sreg.ext_g <= sreg.lower(0); + sreg.ext_r <= sreg.ext_g; + sreg.ext_s <= sreg.ext_r or sreg.ext_s; -- sticky bit + else -- shift left + ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 1); + sreg.upper <= sreg.upper(sreg.upper'left-1 downto 0) & sreg.lower(sreg.lower'left); + sreg.lower <= sreg.lower(sreg.lower'left-1 downto 0) & sreg.ext_g; + sreg.ext_g <= sreg.ext_r; + sreg.ext_r <= sreg.ext_s; + sreg.ext_s <= sreg.ext_s; -- sticky bit + end if; + end if; + + when S_ROUND => -- rounding cycle (after first normalization) + -- ------------------------------------------------------------ + ctrl.rounded <= ctrl.rounded or round.en; + sreg.upper(31 downto 02) <= (others => '0'); + sreg.upper(01 downto 00) <= round.output(24 downto 23); + sreg.lower <= round.output(22 downto 00); + sreg.ext_g <= '0'; + sreg.ext_r <= '0'; + sreg.ext_s <= '0'; + ctrl.state <= S_PREPARE_SHIFT; + + when S_CHECK => -- check for overflow/underflow + -- ------------------------------------------------------------ + if (ctrl.cnt_uf = '1') then -- underflow + ctrl.flags(fp_exc_uf_c) <= '1'; + elsif (ctrl.cnt_of = '1') then -- overflow + ctrl.flags(fp_exc_of_c) <= '1'; + elsif (ctrl.cnt(7 downto 0) = x"00") then -- subnormal + ctrl.flags(fp_exc_uf_c) <= '1'; + elsif (ctrl.cnt(7 downto 0) = x"FF") then -- infinity + ctrl.flags(fp_exc_of_c) <= '1'; + end if; + ctrl.state <= S_FINALIZE; + + when S_FINALIZE => -- result finalization + -- ------------------------------------------------------------ + -- generate result word (the ORDER of checks is imporatant here!) -- + if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') then -- sNaN / qNaN + ctrl.res_sgn <= fp_single_qnan_c(31); + ctrl.res_exp <= fp_single_qnan_c(30 downto 23); + ctrl.res_man <= fp_single_qnan_c(22 downto 00); + elsif (ctrl.class(fp_class_neg_inf_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- infinity + (ctrl.flags(fp_exc_of_c) = '1') then -- overflow + ctrl.res_exp <= fp_single_pos_inf_c(30 downto 23); -- keep original sign + ctrl.res_man <= fp_single_pos_inf_c(22 downto 00); + elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') then -- zero + ctrl.res_sgn <= ctrl.class(fp_class_neg_zero_c); + ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23); + ctrl.res_man <= fp_single_pos_zero_c(22 downto 00); + elsif (ctrl.flags(fp_exc_uf_c) = '1') or -- underflow + (sreg.zero = '1') or (ctrl.class(fp_class_neg_denorm_c) = '1') or (ctrl.class(fp_class_pos_denorm_c) = '1') then -- denormalized (flush-to-zero) + ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23); -- keep original sign + ctrl.res_man <= fp_single_pos_zero_c(22 downto 00); + else -- result is ok + ctrl.res_exp <= ctrl.cnt(7 downto 0); + ctrl.res_man <= sreg.lower; + end if; + -- generate exception flags -- + ctrl.flags(fp_exc_nv_c) <= ctrl.flags(fp_exc_nv_c) or ctrl.class(fp_class_snan_c); -- invalid if input is SIGNALING NaN + ctrl.flags(fp_exc_nx_c) <= ctrl.flags(fp_exc_nx_c) or ctrl.rounded; -- inexcat if result is rounded + -- + done_o <= '1'; + ctrl.state <= S_IDLE; + + when others => -- undefined + -- ------------------------------------------------------------ + ctrl.state <= S_IDLE; + + end case; + end if; + end process ctrl_engine; + + -- stop shifting when normalized -- + sreg.done <= (not or_reduce_f(sreg.upper(sreg.upper'left downto 1))) and sreg.upper(0); -- input is zero, hidden one is set + + -- all-zero including hidden bit -- + sreg.zero <= not or_reduce_f(sreg.upper); + + -- result -- + result_o(31) <= ctrl.res_sgn; + result_o(30 downto 23) <= ctrl.res_exp; + result_o(22 downto 0) <= ctrl.res_man; + + -- exception flags -- + flags_o(fp_exc_nv_c) <= ctrl.flags(fp_exc_nv_c); -- invalid operation + flags_o(fp_exc_dz_c) <= ctrl.flags(fp_exc_dz_c); -- divide by zero + flags_o(fp_exc_of_c) <= ctrl.flags(fp_exc_of_c); -- overflow + flags_o(fp_exc_uf_c) <= ctrl.flags(fp_exc_uf_c); -- underflow + flags_o(fp_exc_nx_c) <= ctrl.flags(fp_exc_nx_c); -- inexact + + + -- Rounding ------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rounding_unit_ctrl: process(rmode_i, sreg) + begin + -- defaults -- + round.en <= '0'; + round.sub <= '0'; + -- rounding mode -- + case rmode_i(2 downto 0) is + when "000" => -- round to nearest, ties to even + if (sreg.ext_g = '0') then + round.en <= '0'; -- round down (do nothing) + else + if (sreg.ext_r = '0') and (sreg.ext_s = '0') then -- tie! + round.en <= sreg.lower(0); -- round up if LSB of mantissa is set + else + round.en <= '1'; -- round up + end if; + end if; + round.sub <= '0'; -- increment + when "001" => -- round towards zero + round.en <= '0'; -- no rounding -> just truncate + when "010" => -- round down (towards -infinity) + round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s; + round.sub <= '1'; -- decrement + when "011" => -- round up (towards +infinity) + round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s; + round.sub <= '0'; -- increment + when "100" => -- round to nearest, ties to max magnitude + round.en <= '0'; -- FIXME / TODO + when others => -- undefined + round.en <= '0'; + end case; + end process rounding_unit_ctrl; + + + -- incrementer/decrementer -- + rounding_unit_add: process(round, sreg) + variable tmp_v : std_ulogic_vector(24 downto 0); + begin + tmp_v := '0' & sreg.upper(0) & sreg.lower; + if (round.en = '1') then + if (round.sub = '0') then -- increment + round.output <= std_ulogic_vector(unsigned(tmp_v) + 1); + else -- decrement + round.output <= std_ulogic_vector(unsigned(tmp_v) - 1); + end if; + else -- do nothing + round.output <= tmp_v; + end if; + end process rounding_unit_add; + + +end neorv32_cpu_cp_fpu_normalizer_rtl; + +-- ########################################################################################################################################### +-- ########################################################################################################################################### + +-- ################################################################################################# +-- # << NEORV32 - Single-Precision Floating-Point Unit: Float-To-Int Converter >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_cp_fpu_f2i is + port ( + -- control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + start_i : in std_ulogic; -- trigger operation + rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + funct_i : in std_ulogic; -- 0=signed, 1=unsigned + -- input -- + sign_i : in std_ulogic; -- sign + exponent_i : in std_ulogic_vector(07 downto 0); -- exponent + mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa + class_i : in std_ulogic_vector(09 downto 0); -- operand class + -- output -- + result_o : out std_ulogic_vector(31 downto 0); -- integer result + flags_o : out std_ulogic_vector(04 downto 0); -- exception flags + done_o : out std_ulogic -- operation done + ); +end neorv32_cpu_cp_fpu_f2i; + +architecture neorv32_cpu_cp_fpu_f2i_rtl of neorv32_cpu_cp_fpu_f2i is + + -- controller -- + type ctrl_engine_state_t is (S_IDLE, S_PREPARE_F2I, S_NORMALIZE_BUSY, S_ROUND, S_FINALIZE); + type ctrl_t is record + state : ctrl_engine_state_t; -- current state + unsign : std_ulogic; + cnt : std_ulogic_vector(07 downto 0); -- interation counter/exponent + sign : std_ulogic; + class : std_ulogic_vector(09 downto 0); + rounded : std_ulogic; -- output is rounded + over : std_ulogic; -- output is overflowing + under : std_ulogic; -- output in underflowing + result_tmp : std_ulogic_vector(31 downto 0); + result : std_ulogic_vector(31 downto 0); + end record; + signal ctrl : ctrl_t; + + -- conversion shift register -- + type sreg_t is record + int : std_ulogic_vector(31 downto 0); -- including hidden-zero + mant : std_ulogic_vector(22 downto 0); + ext_g : std_ulogic; -- guard bit + ext_r : std_ulogic; -- round bit + ext_s : std_ulogic; -- sticky bit + end record; + signal sreg : sreg_t; + + -- rounding unit -- + type round_t is record + en : std_ulogic; -- enable rounding + sub : std_ulogic; -- 0=decrement, 1=increment + output : std_ulogic_vector(32 downto 0); -- result + overflow + end record; + signal round : round_t; + +begin + + -- Control Engine ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ctrl_engine: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl.state <= S_IDLE; + ctrl.cnt <= (others => def_rst_val_c); + ctrl.sign <= def_rst_val_c; + ctrl.class <= (others => def_rst_val_c); + ctrl.rounded <= def_rst_val_c; + ctrl.over <= def_rst_val_c; + ctrl.under <= def_rst_val_c; + ctrl.unsign <= def_rst_val_c; + ctrl.result <= (others => def_rst_val_c); + ctrl.result_tmp <= (others => def_rst_val_c); + sreg.int <= (others => def_rst_val_c); + sreg.mant <= (others => def_rst_val_c); + sreg.ext_s <= def_rst_val_c; + done_o <= '0'; + elsif rising_edge(clk_i) then + -- defaults -- + done_o <= '0'; + + -- fsm -- + case ctrl.state is + + when S_IDLE => -- wait for operation trigger + -- ------------------------------------------------------------ + ctrl.rounded <= '0'; -- not rounded yet + ctrl.over <= '0'; -- not overflowing yet + ctrl.under <= '0'; -- not underflowing yet + ctrl.unsign <= funct_i; + sreg.ext_s <= '0'; -- init + if (start_i = '1') then + ctrl.cnt <= exponent_i; + ctrl.sign <= sign_i; + ctrl.class <= class_i; + sreg.mant <= mantissa_i; + ctrl.state <= S_PREPARE_F2I; + end if; + + when S_PREPARE_F2I => -- prepare float-to-integer conversion + -- ------------------------------------------------------------ + if (unsigned(ctrl.cnt) < 126) then -- less than 0.5 + sreg.int <= (others => '0'); + ctrl.under <= '1'; -- this is an underflow! + ctrl.cnt <= (others => '0'); + elsif (unsigned(ctrl.cnt) = 126) then -- num < 1.0 but num >= 0.5 + sreg.int <= (others => '0'); + sreg.mant <= '1' & sreg.mant(sreg.mant'left downto 1); + ctrl.cnt <= (others => '0'); + else + sreg.int <= (others => '0'); + sreg.int(0) <= '1'; -- hidden one + ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 127); -- remove bias to get raw number of left shifts + end if; + -- check terminal cases -- + if ((ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or + ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or + ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c)) = '1') then + ctrl.state <= S_FINALIZE; + else + ctrl.state <= S_NORMALIZE_BUSY; + end if; + + when S_NORMALIZE_BUSY => -- running normalization cycle + -- ------------------------------------------------------------ + sreg.ext_s <= sreg.ext_s or or_reduce_f(sreg.mant(sreg.mant'left-2 downto 0)); -- sticky bit + if (or_reduce_f(ctrl.cnt(ctrl.cnt'left-1 downto 0)) = '0') then + if (ctrl.unsign = '0') then -- signed conversion + ctrl.over <= ctrl.over or sreg.int(sreg.int'left); -- update overrun flag again to check for numerical overflow into sign bit + end if; + ctrl.state <= S_ROUND; + else -- shift left + ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 1); + sreg.int <= sreg.int(sreg.int'left-1 downto 0) & sreg.mant(sreg.mant'left); + sreg.mant <= sreg.mant(sreg.mant'left-1 downto 0) & '0'; + ctrl.over <= ctrl.over or sreg.int(sreg.int'left); + end if; + + when S_ROUND => -- rounding cycle + -- ------------------------------------------------------------ + ctrl.rounded <= ctrl.rounded or round.en; + ctrl.over <= ctrl.over or round.output(round.output'left); -- overflow after rounding + ctrl.result_tmp <= round.output(round.output'left-1 downto 0); + ctrl.state <= S_FINALIZE; + + when S_FINALIZE => -- check for corner cases and finalize result + -- ------------------------------------------------------------ + if (ctrl.unsign = '1') then -- unsigned conversion + if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- NaN or +inf + ((ctrl.sign = '0') and (ctrl.over = '1')) then -- positive out-of-range + ctrl.result <= x"ffffffff"; + elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') or (ctrl.class(fp_class_neg_inf_c) = '1') or -- subnormal zero or -inf + (ctrl.sign = '1') or (ctrl.under = '1') then -- negative out-of-range or underflow + ctrl.result <= x"00000000"; + else + ctrl.result <= ctrl.result_tmp; + end if; + + else -- signed conversion + if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- NaN or +inf + ((ctrl.sign = '0') and (ctrl.over = '1')) then -- positive out-of-range + ctrl.result <= x"7fffffff"; + elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') or (ctrl.under = '1') then -- subnormal zero or underflow + ctrl.result <= x"00000000"; + elsif (ctrl.class(fp_class_neg_inf_c) = '1') or ((ctrl.sign = '1') and (ctrl.over = '1')) then -- -inf or negative out-of-range + ctrl.result <= x"80000000"; + else -- result is ok, make sign adaption + if (ctrl.sign = '1') then + ctrl.result <= std_ulogic_vector(0 - unsigned(ctrl.result_tmp)); -- abs() + else + ctrl.result <= ctrl.result_tmp; + end if; + end if; + end if; + done_o <= '1'; + ctrl.state <= S_IDLE; + + when others => -- undefined + -- ------------------------------------------------------------ + ctrl.state <= S_IDLE; + + end case; + end if; + end process ctrl_engine; + + -- result -- + result_o <= ctrl.result; + + -- exception flags -- + flags_o(fp_exc_nv_c) <= ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c); -- invalid operation + flags_o(fp_exc_dz_c) <= '0'; -- divide by zero - not possible here + flags_o(fp_exc_of_c) <= ctrl.over or ctrl.class(fp_class_pos_inf_c) or ctrl.class(fp_class_neg_inf_c); -- overflow + flags_o(fp_exc_uf_c) <= ctrl.under; -- underflow + flags_o(fp_exc_nx_c) <= ctrl.rounded; -- inexact if result was rounded + + + -- Rounding ------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rounding_unit_ctrl: process(rmode_i, sreg) + begin + -- defaults -- + round.en <= '0'; + round.sub <= '0'; + -- rounding mode -- + case rmode_i(2 downto 0) is + when "000" => -- round to nearest, ties to even + if (sreg.ext_g = '0') then + round.en <= '0'; -- round down (do nothing) + else + if (sreg.ext_r = '0') and (sreg.ext_s = '0') then -- tie! + round.en <= sreg.int(0); -- round up if LSB of integer is set + else + round.en <= '1'; -- round up + end if; + end if; + round.sub <= '0'; -- increment + when "001" => -- round towards zero + round.en <= '0'; -- no rounding -> just truncate + when "010" => -- round down (towards -infinity) + round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s; + round.sub <= '1'; -- decrement + when "011" => -- round up (towards +infinity) + round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s; + round.sub <= '0'; -- increment + when "100" => -- round to nearest, ties to max magnitude + round.en <= '0'; -- FIXME / TODO + when others => -- undefined + round.en <= '0'; + end case; + end process rounding_unit_ctrl; + + -- rounding: guard and round bits -- + sreg.ext_g <= sreg.mant(sreg.mant'left); + sreg.ext_r <= sreg.mant(sreg.mant'left-1); + + + -- incrementer/decrementer -- + rounding_unit_add: process(round, sreg) + variable tmp_v : std_ulogic_vector(32 downto 0); -- including overflow + begin + tmp_v := '0' & sreg.int; + if (round.en = '1') then + if (round.sub = '0') then -- increment + round.output <= std_ulogic_vector(unsigned(tmp_v) + 1); + else -- decrement + round.output <= std_ulogic_vector(unsigned(tmp_v) - 1); + end if; + else -- do nothing + round.output <= tmp_v; + end if; + end process rounding_unit_add; + + +end neorv32_cpu_cp_fpu_f2i_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_muldiv.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_muldiv.vhd new file mode 100644 index 0000000..4a3904e --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_muldiv.vhd @@ -0,0 +1,343 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU Co-Processor: Integer Multiplier/Divider Unit (RISC-V "M" Extension) >> # +-- # ********************************************************************************************* # +-- # Multiplier and Divider unit. Implements the RISC-V M CPU extension. # +-- # # +-- # Multiplier core (signed/unsigned) uses classical serial algorithm. Unit latency: 31+3 cycles # +-- # Divider core (unsigned) uses classical serial algorithm. Unit latency: 32+4 cycles # +-- # # +-- # Multiplications can be mapped to DSP blocks (faster!) when FAST_MUL_EN = true. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_cp_muldiv is + generic ( + FAST_MUL_EN : boolean; -- use DSPs for faster multiplication + DIVISION_EN : boolean -- implement divider hardware + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + valid_o : out std_ulogic -- data output valid + ); +end neorv32_cpu_cp_muldiv; + +architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is + + -- operations -- + constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul + constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh + constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu + constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu + constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div + constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu + constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem + constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu + + -- controller -- + type state_t is (IDLE, DIV_PREPROCESS, PROCESSING, FINALIZE); + signal state : state_t; + signal cnt : std_ulogic_vector(4 downto 0); + signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute + signal cp_op_ff : std_ulogic_vector(2 downto 0); -- operation that was executed + signal start_div : std_ulogic; + signal start_mul : std_ulogic; + signal operation : std_ulogic; + signal div_opy : std_ulogic_vector(data_width_c-1 downto 0); + signal rs1_is_signed : std_ulogic; + signal rs2_is_signed : std_ulogic; + signal opy_is_zero : std_ulogic; + signal div_res_corr : std_ulogic; + signal out_en : std_ulogic; + + -- divider core -- + signal remainder : std_ulogic_vector(data_width_c-1 downto 0); + signal quotient : std_ulogic_vector(data_width_c-1 downto 0); + signal div_sub : std_ulogic_vector(data_width_c downto 0); + signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0); + signal div_sign_comp : std_ulogic_vector(data_width_c-1 downto 0); + signal div_res : std_ulogic_vector(data_width_c-1 downto 0); + + -- multiplier core -- + signal mul_product : std_ulogic_vector(63 downto 0); + signal mul_do_add : std_ulogic_vector(data_width_c downto 0); + signal mul_sign_cycle : std_ulogic; + signal mul_p_sext : std_ulogic; + signal mul_op_x : signed(32 downto 0); -- for using DSPs + signal mul_op_y : signed(32 downto 0); -- for using DSPs + +begin + + -- Co-Processor Controller ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + coprocessor_ctrl: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + state <= IDLE; + div_opy <= (others => def_rst_val_c); + cnt <= (others => def_rst_val_c); + cp_op_ff <= (others => def_rst_val_c); + start_div <= '0'; + out_en <= '0'; + valid_o <= '0'; + div_res_corr <= def_rst_val_c; + opy_is_zero <= def_rst_val_c; + elsif rising_edge(clk_i) then + -- defaults -- + start_div <= '0'; + out_en <= '0'; + valid_o <= '0'; + + -- FSM -- + case state is + + when IDLE => + cp_op_ff <= cp_op; + cnt <= "11110"; + if (start_i = '1') then + if (operation = '1') and (DIVISION_EN = true) then -- division + start_div <= '1'; + state <= DIV_PREPROCESS; + else -- multiplication + if (FAST_MUL_EN = true) then + valid_o <= '1'; + state <= FINALIZE; + else + state <= PROCESSING; + end if; + end if; + end if; + + when DIV_PREPROCESS => + -- check relevant input signs -- + if (cp_op = cp_op_div_c) then -- result sign compensation for div? + div_res_corr <= rs1_i(rs1_i'left) xor rs2_i(rs2_i'left); + elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem? + div_res_corr <= rs1_i(rs1_i'left); + else + div_res_corr <= '0'; + end if; + -- divide by zero? -- + opy_is_zero <= not or_reduce_f(rs2_i); -- set if rs2 = 0 + -- abs(rs2) -- + if ((rs2_i(rs2_i'left) and rs2_is_signed) = '1') then -- signed division? + div_opy <= std_ulogic_vector(0 - unsigned(rs2_i)); -- make positive + else + div_opy <= rs2_i; + end if; + -- + state <= PROCESSING; + + when PROCESSING => + cnt <= std_ulogic_vector(unsigned(cnt) - 1); + if (cnt = "00000") then + valid_o <= '1'; + state <= FINALIZE; + end if; + + when FINALIZE => + out_en <= '1'; + state <= IDLE; + + when others => + state <= IDLE; + end case; + end if; + end process coprocessor_ctrl; + + -- co-processor command -- + cp_op <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c); + + -- operation: 0=mul, 1=div -- + operation <= '1' when (cp_op(2) = '1') else '0'; + + -- opx (rs1) signed? -- + rs1_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0'; + + -- opy (rs2) signed? -- + rs2_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0'; + + -- start MUL operation (do it fast!) -- + start_mul <= '1' when (state = IDLE) and (start_i = '1') and (operation = '0') else '0'; + + + -- Multiplier Core (signed/unsigned) ------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + -- iterative multiplication (bit-serial) -- + multiplier_core_serial: + if (FAST_MUL_EN = false) generate + multiplier_core: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + mul_product <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + if (start_mul = '1') then -- start new multiplication + mul_product(63 downto 32) <= (others => '0'); + mul_product(31 downto 00) <= rs2_i; + elsif (state = PROCESSING) or (state = FINALIZE) then -- processing step or sign-finalization step + mul_product(63 downto 31) <= mul_do_add(32 downto 0); + mul_product(30 downto 00) <= mul_product(31 downto 1); + end if; + end if; + end process multiplier_core; + end generate; + + -- parallel multiplication (using DSP blocks) -- + multiplier_core_dsp: + if (FAST_MUL_EN = true) generate + multiplier_core: process(clk_i) + variable tmp_v : signed(65 downto 0); + begin + if rising_edge(clk_i) then + if (start_mul = '1') then + mul_op_x <= signed((rs1_i(rs1_i'left) and rs1_is_signed) & rs1_i); + mul_op_y <= signed((rs2_i(rs2_i'left) and rs2_is_signed) & rs2_i); + end if; + tmp_v := mul_op_x * mul_op_y; + mul_product <= std_ulogic_vector(tmp_v(63 downto 0)); + --mul_buf_ff <= mul_op_x * mul_op_y; + --mul_product <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here + end if; + end process multiplier_core; + end generate; + + -- do another addition (bit-serial) -- + mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, rs1_is_signed, rs1_i) + begin + -- current bit of rs2_i to take care of -- + if (mul_product(0) = '1') then -- multiply with 1 + if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1 + mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((rs1_i(rs1_i'left) and rs1_is_signed) & rs1_i)); + else -- multiply with +1 + mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((rs1_i(rs1_i'left) and rs1_is_signed) & rs1_i)); + end if; + else -- multiply with 0 + mul_do_add <= mul_p_sext & mul_product(63 downto 32); + end if; + end process mul_update; + + -- sign control -- + mul_sign_cycle <= rs2_is_signed when (state = FINALIZE) else '0'; + mul_p_sext <= mul_product(mul_product'left) and rs1_is_signed; + + + -- Divider Core (unsigned) ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + divider_core_serial: + if (DIVISION_EN = true) generate + divider_core: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + quotient <= (others => def_rst_val_c); + remainder <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + if (start_div = '1') then -- start new division + if ((rs1_i(rs1_i'left) and rs1_is_signed) = '1') then -- signed division? + quotient <= std_ulogic_vector(0 - unsigned(rs1_i)); -- make positive + else + quotient <= rs1_i; + end if; + remainder <= (others => '0'); + elsif (state = PROCESSING) or (state = FINALIZE) then -- running? + quotient <= quotient(30 downto 0) & (not div_sub(32)); + if (div_sub(32) = '0') then -- still overflowing + remainder <= div_sub(31 downto 0); + else -- underflow + remainder <= remainder(30 downto 0) & quotient(31); + end if; + end if; + end if; + end process divider_core; + + -- try another subtraction -- + div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & div_opy)); + + -- result sign compensation -- + div_sign_comp_in <= quotient when (cp_op = cp_op_div_c) else remainder; + div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in)); + div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in; + end generate; + + -- no divider -- + divider_core_serial_none: + if (DIVISION_EN = false) generate + remainder <= (others => '0'); + quotient <= (others => '0'); + div_res <= (others => '0'); + end generate; + + + -- Data Output ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + operation_result: process(out_en, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1_i, remainder) + begin + if (out_en = '1') then + case cp_op_ff is + when cp_op_mul_c => + res_o <= mul_product(31 downto 00); + when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c => + res_o <= mul_product(63 downto 32); + when cp_op_div_c => + res_o <= div_res; + when cp_op_divu_c => + res_o <= quotient; + when cp_op_rem_c => + if (opy_is_zero = '0') then + res_o <= div_res; + else + res_o <= rs1_i; + end if; + when others => -- cp_op_remu_c + res_o <= remainder; + end case; + else + res_o <= (others => '0'); + end if; + end process operation_result; + + +end neorv32_cpu_cp_muldiv_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_shifter.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_shifter.vhd new file mode 100644 index 0000000..c1f0736 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_cp_shifter.vhd @@ -0,0 +1,181 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU Co-Processor: Shifter (CPU Core ISA) >> # +-- # ********************************************************************************************* # +-- # Bit-shift unit for base ISA. # +-- # FAST_SHIFT_EN = false (default): Use bit-serial shifter architecture (small but slow) # +-- # FAST_SHIFT_EN = true: Use barrel shifter architecture (large but fast) # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_cp_shifter is + generic ( + FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + shamt_i : in std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); -- shift amount + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + valid_o : out std_ulogic -- data output valid + ); +end neorv32_cpu_cp_shifter; + +architecture neorv32_cpu_cp_shifter_rtl of neorv32_cpu_cp_shifter is + + -- serial shifter -- + type shifter_t is record + busy : std_ulogic; + busy_ff : std_ulogic; + done : std_ulogic; + cnt : std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); + sreg : std_ulogic_vector(data_width_c-1 downto 0); + res : std_ulogic_vector(data_width_c-1 downto 0); + end record; + signal shifter : shifter_t; + + -- barrel shifter -- + type bs_level_t is array (index_size_f(data_width_c) downto 0) of std_ulogic_vector(data_width_c-1 downto 0); + signal bs_level : bs_level_t; + signal bs_result : std_ulogic_vector(data_width_c-1 downto 0); + +begin + + -- Iterative Shifter Core (small but slow) ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + serial_shifter_sync: + if (FAST_SHIFT_EN = false) generate + shifter_unit_sync: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + shifter.busy <= '0'; + shifter.busy_ff <= def_rst_val_c; + shifter.sreg <= (others => def_rst_val_c); + shifter.cnt <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + shifter.busy_ff <= shifter.busy; + if (start_i = '1') then + shifter.busy <= '1'; + elsif (shifter.done = '1') then + shifter.busy <= '0'; + end if; + -- + if (start_i = '1') then -- trigger new shift + shifter.sreg <= rs1_i; -- shift operand + shifter.cnt <= shamt_i; -- shift amount + elsif (or_reduce_f(shifter.cnt) = '1') then -- running shift (cnt != 0) + shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1); + if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical + shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0'; + else -- SRL: shift right logical / SRA: shift right arithmetical + shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1); + end if; + end if; + end if; + end process shifter_unit_sync; + end generate; + + -- shift control/output -- + serial_shifter_ctrl: + if (FAST_SHIFT_EN = false) generate + shifter.done <= not or_reduce_f(shifter.cnt(shifter.cnt'left downto 1)); + valid_o <= shifter.busy and shifter.done; + res_o <= shifter.sreg when (shifter.busy = '0') and (shifter.busy_ff = '1') else (others => '0'); + end generate; + + + -- Barrel Shifter Core (fast but large) --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + barrel_shifter_async: + if (FAST_SHIFT_EN = true) generate + shifter_unit_async: process(rs1_i, shamt_i, ctrl_i, bs_level) + begin + -- input level: convert left shifts to right shifts -- + if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- is left shift? + bs_level(index_size_f(data_width_c)) <= bit_rev_f(rs1_i); -- reverse bit order of input operand + else + bs_level(index_size_f(data_width_c)) <= rs1_i; + end if; + + -- shifter array -- + for i in index_size_f(data_width_c)-1 downto 0 loop + if (shamt_i(i) = '1') then + bs_level(i)(data_width_c-1 downto data_width_c-(2**i)) <= (others => (bs_level(i+1)(data_width_c-1) and ctrl_i(ctrl_alu_shift_ar_c))); + bs_level(i)((data_width_c-(2**i))-1 downto 0) <= bs_level(i+1)(data_width_c-1 downto 2**i); + else + bs_level(i) <= bs_level(i+1); + end if; + end loop; + + -- re-convert original left shifts -- + if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then + bs_result <= bit_rev_f(bs_level(0)); + else + bs_result <= bs_level(0); + end if; + end process shifter_unit_async; + end generate; + + -- output register -- + barrel_shifter_sync: + if (FAST_SHIFT_EN = true) generate + shifter_unit_sync: process(clk_i) + begin + if rising_edge(clk_i) then + res_o <= (others => '0'); + if (start_i = '1') then + res_o <= bs_result; + end if; + end if; + end process shifter_unit_sync; + end generate; + + -- shift control/output -- + barrel_shifter_ctrl: + if (FAST_SHIFT_EN = true) generate + valid_o <= start_i; + end generate; + + +end neorv32_cpu_cp_shifter_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_decompressor.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_decompressor.vhd new file mode 100644 index 0000000..3684c86 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_decompressor.vhd @@ -0,0 +1,453 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU: Compressed Instructions Decoder (RISC-V "C" Extension) >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_decompressor is + port ( + -- instruction input -- + ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input + -- instruction output -- + ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction + ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction + ); +end neorv32_cpu_decompressor; + +architecture neorv32_cpu_decompressor_rtl of neorv32_cpu_decompressor is + + -- compressed instruction layout -- + constant ci_opcode_lsb_c : natural := 0; + constant ci_opcode_msb_c : natural := 1; + constant ci_rd_3_lsb_c : natural := 2; + constant ci_rd_3_msb_c : natural := 4; + constant ci_rd_5_lsb_c : natural := 7; + constant ci_rd_5_msb_c : natural := 11; + constant ci_rs1_3_lsb_c : natural := 7; + constant ci_rs1_3_msb_c : natural := 9; + constant ci_rs1_5_lsb_c : natural := 7; + constant ci_rs1_5_msb_c : natural := 11; + constant ci_rs2_3_lsb_c : natural := 2; + constant ci_rs2_3_msb_c : natural := 4; + constant ci_rs2_5_lsb_c : natural := 2; + constant ci_rs2_5_msb_c : natural := 6; + constant ci_funct3_lsb_c : natural := 13; + constant ci_funct3_msb_c : natural := 15; + +begin + + -- Compressed Instruction Decoder --------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + decompressor: process(ci_instr16_i) + variable imm20_v : std_ulogic_vector(20 downto 0); + variable imm12_v : std_ulogic_vector(12 downto 0); + begin + -- defaults -- + ci_illegal_o <= '0'; + ci_instr32_o <= (others => '0'); + + -- helper: 22-bit sign-extended immediate for J/JAL -- + imm20_v := (others => ci_instr16_i(12)); -- sign extension + imm20_v(00):= '0'; + imm20_v(01):= ci_instr16_i(3); + imm20_v(02):= ci_instr16_i(4); + imm20_v(03):= ci_instr16_i(5); + imm20_v(04):= ci_instr16_i(11); + imm20_v(05):= ci_instr16_i(2); + imm20_v(06):= ci_instr16_i(7); + imm20_v(07):= ci_instr16_i(6); + imm20_v(08):= ci_instr16_i(9); + imm20_v(09):= ci_instr16_i(10); + imm20_v(10):= ci_instr16_i(8); + imm20_v(11):= ci_instr16_i(12); + + -- helper: 12-bit sign-extended immediate for branches -- + imm12_v := (others => ci_instr16_i(12)); -- sign extension + imm12_v(00):= '0'; + imm12_v(01):= ci_instr16_i(3); + imm12_v(02):= ci_instr16_i(4); + imm12_v(03):= ci_instr16_i(10); + imm12_v(04):= ci_instr16_i(11); + imm12_v(05):= ci_instr16_i(2); + imm12_v(06):= ci_instr16_i(5); + imm12_v(07):= ci_instr16_i(6); + imm12_v(08):= ci_instr16_i(12); + + -- actual decoder -- + case ci_instr16_i(ci_opcode_msb_c downto ci_opcode_lsb_c) is + + when "00" => -- C0: Register-Based Loads and Stores + case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is + + when "000" => -- Illegal_instruction, C.ADDI4SPN + -- ---------------------------------------------------------------------------------------------------------- + -- C.ADDI4SPN + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c); + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c; + ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => '0'); -- zero extend + ci_instr32_o(instr_imm12_lsb_c + 0) <= '0'; + ci_instr32_o(instr_imm12_lsb_c + 1) <= '0'; + ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(6); + ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(11); + ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12); + ci_instr32_o(instr_imm12_lsb_c + 6) <= ci_instr16_i(7); + ci_instr32_o(instr_imm12_lsb_c + 7) <= ci_instr16_i(8); + ci_instr32_o(instr_imm12_lsb_c + 8) <= ci_instr16_i(9); + ci_instr32_o(instr_imm12_lsb_c + 9) <= ci_instr16_i(10); + -- + ci_illegal_o <= not or_reduce_f(ci_instr16_i(12 downto 2)); -- 12:2 = "00000000000" is official illegal instruction + + when "010" | "011" => -- C.LW / C.FLW + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_load_c; + ci_instr32_o(21 downto 20) <= "00"; + ci_instr32_o(22) <= ci_instr16_i(6); + ci_instr32_o(23) <= ci_instr16_i(10); + ci_instr32_o(24) <= ci_instr16_i(11); + ci_instr32_o(25) <= ci_instr16_i(12); + ci_instr32_o(26) <= ci_instr16_i(5); + ci_instr32_o(31 downto 27) <= (others => '0'); + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_lw_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); -- x8 - x15 + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c); -- x8 - x15 + if (ci_instr16_i(ci_funct3_lsb_c) = '1') then -- C.FLW + ci_illegal_o <= '1'; + end if; + + when "110" | "111" => -- C.SW / C.FSW + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c; + ci_instr32_o(08 downto 07) <= "00"; + ci_instr32_o(09) <= ci_instr16_i(6); + ci_instr32_o(10) <= ci_instr16_i(10); + ci_instr32_o(11) <= ci_instr16_i(11); + ci_instr32_o(25) <= ci_instr16_i(12); + ci_instr32_o(26) <= ci_instr16_i(5); + ci_instr32_o(31 downto 27) <= (others => '0'); + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sw_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); -- x8 - x15 + ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "01" & ci_instr16_i(ci_rs2_3_msb_c downto ci_rs2_3_lsb_c); -- x8 - x15 + if (ci_instr16_i(ci_funct3_lsb_c) = '1') then -- C.FSW + ci_illegal_o <= '1'; + end if; + + when others => -- undefined + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o <= (others => '-'); + ci_illegal_o <= '1'; + + end case; + + when "01" => -- C1: Control Transfer Instructions, Integer Constant-Generation Instructions + + case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is + when "101" => -- C.J + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jal_c; + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00000"; -- discard return address + ci_instr32_o(19 downto 12) <= imm20_v(19 downto 12); + ci_instr32_o(20) <= imm20_v(11); + ci_instr32_o(30 downto 21) <= imm20_v(10 downto 01); + ci_instr32_o(31) <= imm20_v(20); + + when "001" => -- C.JAL + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jal_c; + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00001"; -- save return address to link register + ci_instr32_o(19 downto 12) <= imm20_v(19 downto 12); + ci_instr32_o(20) <= imm20_v(11); + ci_instr32_o(30 downto 21) <= imm20_v(10 downto 01); + ci_instr32_o(31) <= imm20_v(20); + + when "110" => -- C.BEQ + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_branch_c; + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_beq_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); + ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "00000"; -- x0 + ci_instr32_o(07) <= imm12_v(11); + ci_instr32_o(11 downto 08) <= imm12_v(04 downto 01); + ci_instr32_o(30 downto 25) <= imm12_v(10 downto 05); + ci_instr32_o(31) <= imm12_v(12); + + when "111" => -- C.BNEZ + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_branch_c; + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_bne_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); + ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "00000"; -- x0 + ci_instr32_o(07) <= imm12_v(11); + ci_instr32_o(11 downto 08) <= imm12_v(04 downto 01); + ci_instr32_o(30 downto 25) <= imm12_v(10 downto 05); + ci_instr32_o(31) <= imm12_v(12); + + when "010" => -- C.LI + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c; + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00000"; -- x0 + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend + ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2); + ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3); + ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4); + ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); + ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12); + + when "011" => -- C.LUI / C.ADDI16SP + -- ---------------------------------------------------------------------------------------------------------- + if (ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c) = "00010") then -- C.ADDI16SP + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c; + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c; + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00010"; -- stack pointer + ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend + ci_instr32_o(instr_imm12_lsb_c + 0) <= '0'; + ci_instr32_o(instr_imm12_lsb_c + 1) <= '0'; + ci_instr32_o(instr_imm12_lsb_c + 2) <= '0'; + ci_instr32_o(instr_imm12_lsb_c + 3) <= '0'; + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); + ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(2); + ci_instr32_o(instr_imm12_lsb_c + 6) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 7) <= ci_instr16_i(3); + ci_instr32_o(instr_imm12_lsb_c + 8) <= ci_instr16_i(4); + ci_instr32_o(instr_imm12_lsb_c + 9) <= ci_instr16_i(12); + + else -- C.LUI + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_lui_c; + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + ci_instr32_o(instr_imm20_msb_c downto instr_imm20_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend + ci_instr32_o(instr_imm20_lsb_c + 0) <= ci_instr16_i(2); + ci_instr32_o(instr_imm20_lsb_c + 1) <= ci_instr16_i(3); + ci_instr32_o(instr_imm20_lsb_c + 2) <= ci_instr16_i(4); + ci_instr32_o(instr_imm20_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm20_lsb_c + 4) <= ci_instr16_i(6); + ci_instr32_o(instr_imm20_lsb_c + 5) <= ci_instr16_i(12); + end if; + if (ci_instr16_i(6 downto 2) = "00000") and (ci_instr16_i(12) = '0') then -- reserved + ci_illegal_o <= '1'; + end if; + + when "000" => -- C.NOP (rd=0) / C.ADDI + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c; + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c); + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend + ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2); + ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3); + ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4); + ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); + ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12); + + when "100" => -- C.SRLI, C.SRAI, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, reserved + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); + if (ci_instr16_i(11 downto 10) = "11") then -- register-register operation + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c; + ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "01" & ci_instr16_i(ci_rs2_3_msb_c downto ci_rs2_3_lsb_c); + case ci_instr16_i(6 downto 5) is + when "00" => -- C.SUB + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c; + ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0100000"; + when "01" => -- C.XOR + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_xor_c; + ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000"; + when "10" => -- C.OR + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_or_c; + ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000"; + when others => -- C.AND + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_and_c; + ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000"; + end case; + else -- register-immediate operation + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c; + case ci_instr16_i(11 downto 10) is + when "00" => -- C.SRLI + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sr_c; + ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000"; + ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2); + ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3); + ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4); + ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); + ci_illegal_o <= ci_instr16_i(12); + when "01" => -- C.SRAI + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sr_c; + ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0100000"; + ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2); + ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3); + ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4); + ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); + ci_illegal_o <= ci_instr16_i(12); + when "10" => -- C.ANDI + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_and_c; + ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend + ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2); + ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3); + ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4); + ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); + ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12); + when others => -- register-register operation + NULL; + end case; + end if; + if (ci_instr16_i(12 downto 10) = "111") then -- reserved / undefined + ci_illegal_o <= '1'; + end if; + + when others => -- undefined + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o <= (others => '-'); + ci_illegal_o <= '1'; + + end case; + + when "10" => -- C2: Stack-Pointer-Based Loads and Stores, Control Transfer Instructions + case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is + + when "000" => -- C.SLLI + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c); + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c); + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sll_c; + ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000"; + ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2); + ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3); + ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4); + ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5); + ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); + ci_illegal_o <= ci_instr16_i(12); + + when "010" | "011" => -- C.LWSP / C.FLWSP + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_load_c; + ci_instr32_o(21 downto 20) <= "00"; + ci_instr32_o(22) <= ci_instr16_i(4); + ci_instr32_o(23) <= ci_instr16_i(5); + ci_instr32_o(24) <= ci_instr16_i(6); + ci_instr32_o(25) <= ci_instr16_i(12); + ci_instr32_o(26) <= ci_instr16_i(2); + ci_instr32_o(27) <= ci_instr16_i(3); + ci_instr32_o(31 downto 28) <= (others => '0'); + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_lw_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + if (ci_instr16_i(ci_funct3_lsb_c) = '1') then -- C.FLWSP + ci_illegal_o <= '1'; + end if; + + when "110" | "111" => -- C.SWSP / C.FSWSP + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c; + ci_instr32_o(08 downto 07) <= "00"; + ci_instr32_o(09) <= ci_instr16_i(9); + ci_instr32_o(10) <= ci_instr16_i(10); + ci_instr32_o(11) <= ci_instr16_i(11); + ci_instr32_o(25) <= ci_instr16_i(12); + ci_instr32_o(26) <= ci_instr16_i(7); + ci_instr32_o(27) <= ci_instr16_i(8); + ci_instr32_o(31 downto 28) <= (others => '0'); + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sw_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer + ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c); + if (ci_instr16_i(ci_funct3_lsb_c) = '1') then -- C.FSWSP + ci_illegal_o <= '1'; + end if; + + when "100" => -- C.JR, C.JALR, C.MV, C.EBREAK, C.ADD + -- ---------------------------------------------------------------------------------------------------------- + if (ci_instr16_i(12) = '0') then -- C.JR, C.MV + if (ci_instr16_i(6 downto 2) = "00000") then -- C.JR + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jalr_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c); + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00000"; -- discard return address + else -- C.MV + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c; + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= "000"; + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00000"; -- x0 + ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c); + end if; + else -- C.EBREAK, C.JALR, C.ADD + if (ci_instr16_i(6 downto 2) = "00000") then -- C.EBREAK, C.JALR + if (ci_instr16_i(11 downto 7) = "00000") then -- C.EBREAK + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_syscsr_c; + ci_instr32_o(instr_funct12_msb_c downto instr_funct12_lsb_c) <= "000000000001"; + else -- C.JALR + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jalr_c; + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c); + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00001"; -- save return address to link register + end if; + else -- C.ADD + ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c; + ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= "000"; + ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c); + ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c); + end if; + end if; + + when others => -- undefined + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o <= (others => '-'); + ci_illegal_o <= '1'; + + end case; + + when others => -- not a compressed instruction + -- ---------------------------------------------------------------------------------------------------------- + ci_instr32_o <= (others => '-'); + ci_illegal_o <= '0'; + + end case; + end process decompressor; + + +end neorv32_cpu_decompressor_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_regfile.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_regfile.vhd new file mode 100644 index 0000000..c205033 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_cpu_regfile.vhd @@ -0,0 +1,135 @@ +-- ################################################################################################# +-- # << NEORV32 - CPU General Purpose Data Register File >> # +-- # ********************************************************************************************* # +-- # General purpose data register file. 32 entries (= 1024 bit) for normal mode (RV32I), # +-- # 16 entries (= 512 bit) for embedded mode (RV32E) when RISC-V "E" extension is enabled. # +-- # # +-- # Register zero (r0/x0) is a "normal" physical register that has to be initialized to zero by # +-- # the early boot code. Register zero is always set to zero when written. # +-- # # +-- # The register file uses synchronous read accesses and a *single* (multiplexed) address port # +-- # for writing and reading rd/rs1 and a single read-only port for rs2. Therefore, the whole # +-- # register file can be mapped to a single true-dual-port block RAM. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_cpu_regfile is + generic ( + CPU_EXTENSION_RISCV_E : boolean -- implement embedded RF extension? + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- data input -- + mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data + alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result + -- data output -- + rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1 + rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2 + ); +end neorv32_cpu_regfile; + +architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is + + -- register file -- + type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0); + type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0); + signal reg_file : reg_file_t; + signal reg_file_emb : reg_file_emb_t; + signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data + signal rd_is_r0 : std_ulogic; -- writing to r0? + signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address + signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address + signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address + signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- read data + +begin + + -- Data Input Mux ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + input_mux: process(rd_is_r0, ctrl_i, alu_i, mem_i) + begin + if (rd_is_r0 = '1') then -- write zero if accessing x0 to "emulate" it is hardwired to zero + rf_wdata <= (others => '0'); + else + if (ctrl_i(ctrl_rf_in_mux_c) = '0') then + rf_wdata <= alu_i; + else + rf_wdata <= mem_i; + end if; + end if; + end process input_mux; + + -- check if we are writing to x0 -- + rd_is_r0 <= (not or_reduce_f(dst_addr(4 downto 0))) when (CPU_EXTENSION_RISCV_E = false) else (not or_reduce_f(dst_addr(3 downto 0))); + + + -- Register File Access ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rf_access: process(clk_i) + begin + if rising_edge(clk_i) then -- sync read and write + if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries + if (ctrl_i(ctrl_rf_wb_en_c) = '1') then + reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_wdata; + end if; + rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0)))); + rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0)))); + else -- embedded register file with 16 entries + if (ctrl_i(ctrl_rf_wb_en_c) = '1') then + reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_wdata; + end if; + rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))); + rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0)))); + end if; + end if; + end process rf_access; + + -- access addresses -- + dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c); + opa_addr <= dst_addr when (ctrl_i(ctrl_rf_wb_en_c) = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1 + opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2 + + -- data output -- + rs1_o <= rs1; + rs2_o <= rs2; + + +end neorv32_cpu_regfile_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_debug_dm.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_debug_dm.vhd new file mode 100644 index 0000000..9ebbb9f --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_debug_dm.vhd @@ -0,0 +1,728 @@ +-- ################################################################################################# +-- # << NEORV32 - RISC-V-Compatible Debug Module (DM) >> # +-- # ********************************************************************************************* # +-- # Compatible to the "Minimal RISC-V External Debug Spec. Version 0.13.2" # +-- # -> "Execution-based" debugging scheme # +-- # ********************************************************************************************* # +-- # Key features: # +-- # * register access commands only # +-- # * auto-execution commands # +-- # * for a single hart only # +-- # * 2 general purpose program buffer entries # +-- # * 1 general purpose data buffer entry # +-- # # +-- # CPU access: # +-- # * ROM for "park loop" code # +-- # * program buffer # +-- # * data buffer # +-- # * control and status register # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_debug_dm is + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + -- debug module interface (DMI) -- + dmi_rstn_i : in std_ulogic; + dmi_req_valid_i : in std_ulogic; + dmi_req_ready_o : out std_ulogic; -- DMI is allowed to make new requests when set + dmi_req_addr_i : in std_ulogic_vector(06 downto 0); + dmi_req_op_i : in std_ulogic; -- 0=read, 1=write + dmi_req_data_i : in std_ulogic_vector(31 downto 0); + dmi_resp_valid_o : out std_ulogic; -- response valid when set + dmi_resp_ready_i : in std_ulogic; -- ready to receive respond + dmi_resp_data_o : out std_ulogic_vector(31 downto 0); + dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error + -- CPU bus access -- + cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address + cpu_rden_i : in std_ulogic; -- read enable + cpu_wren_i : in std_ulogic; -- write enable + cpu_data_i : in std_ulogic_vector(31 downto 0); -- data in + cpu_data_o : out std_ulogic_vector(31 downto 0); -- data out + cpu_ack_o : out std_ulogic; -- transfer acknowledge + -- CPU control -- + cpu_ndmrstn_o : out std_ulogic; -- soc reset + cpu_halt_req_o : out std_ulogic -- request hart to halt (enter debug mode) + ); +end neorv32_debug_dm; + +architecture neorv32_debug_dm_rtl of neorv32_debug_dm is + + -- DM configuration -- + constant nscratch_c : std_ulogic_vector(03 downto 0) := "0001"; -- number of dscratch* registers in CPU = 1 + constant dataaccess_c : std_ulogic := '1'; -- 1: abstract data is memory-mapped, 0: abstract data is CSR-mapped + constant datasize_c : std_ulogic_vector(03 downto 0) := "0001"; -- number of data registers in memory/CSR space = 1 + constant dataaddr_c : std_ulogic_vector(11 downto 0) := dm_data_base_c(11 downto 0); -- signed base address of data registers in memory/CSR space + + -- available DMI registers -- + constant addr_data0_c : std_ulogic_vector(6 downto 0) := "000" & x"4"; + constant addr_dmcontrol_c : std_ulogic_vector(6 downto 0) := "001" & x"0"; + constant addr_dmstatus_c : std_ulogic_vector(6 downto 0) := "001" & x"1"; + constant addr_hartinfo_c : std_ulogic_vector(6 downto 0) := "001" & x"2"; + constant addr_abstractcs_c : std_ulogic_vector(6 downto 0) := "001" & x"6"; + constant addr_command_c : std_ulogic_vector(6 downto 0) := "001" & x"7"; + constant addr_abstractauto_c : std_ulogic_vector(6 downto 0) := "001" & x"8"; + constant addr_nextdm_c : std_ulogic_vector(6 downto 0) := "001" & x"d"; + constant addr_progbuf0_c : std_ulogic_vector(6 downto 0) := "010" & x"0"; + constant addr_progbuf1_c : std_ulogic_vector(6 downto 0) := "010" & x"1"; + constant addr_sbcs_c : std_ulogic_vector(6 downto 0) := "011" & x"8"; + constant addr_haltsum0_c : std_ulogic_vector(6 downto 0) := "100" & x"0"; + + -- RISC-V 32-bit instruction prototypes -- + constant instr_nop_c : std_ulogic_vector(31 downto 0) := x"00000013"; -- nop + constant instr_lw_c : std_ulogic_vector(31 downto 0) := x"00002003"; -- lw zero, 0(zero) + constant instr_sw_c : std_ulogic_vector(31 downto 0) := x"00002023"; -- sw zero, 0(zero) + constant instr_ebreak_c : std_ulogic_vector(31 downto 0) := x"00100073"; -- ebreak + + -- debug module controller -- + type dm_ctrl_state_t is (CMD_IDLE, CMD_EXE_CHECK, CMD_EXE_PREPARE, CMD_EXE_TRIGGER, CMD_EXE_BUSY, CMD_EXE_ERROR); + type dm_ctrl_t is record + -- fsm -- + state : dm_ctrl_state_t; + busy : std_ulogic; + ldsw_progbuf : std_ulogic_vector(31 downto 0); + pbuf_en : std_ulogic; + -- error flags -- + illegal_state : std_ulogic; + illegal_cmd : std_ulogic; + cmderr : std_ulogic_vector(02 downto 0); + -- hart status -- + hart_halted : std_ulogic; + hart_resume_req : std_ulogic; + hart_resume_ack : std_ulogic; + hart_reset : std_ulogic; + end record; + signal dm_ctrl : dm_ctrl_t; + + -- debug module DMI registers / access -- + type progbuf_t is array (0 to 1) of std_ulogic_vector(31 downto 0); + type dm_reg_t is record + dmcontrol_ndmreset : std_ulogic; + dmcontrol_dmactive : std_ulogic; + abstractauto_autoexecdata : std_ulogic; + abstractauto_autoexecprogbuf : std_ulogic_vector(01 downto 0); + progbuf : progbuf_t; + command : std_ulogic_vector(31 downto 0); + -- + halt_req : std_ulogic; + resume_req : std_ulogic; + reset_ack : std_ulogic; + wr_acc_err : std_ulogic; + rd_acc_err : std_ulogic; + clr_acc_err : std_ulogic; + autoexec_wr : std_ulogic; + autoexec_rd : std_ulogic; + end record; + signal dm_reg : dm_reg_t; + + -- cpu program buffer -- + type cpu_progbuf_t is array (0 to 4) of std_ulogic_vector(31 downto 0); + signal cpu_progbuf : cpu_progbuf_t; + + -- ********************************************************** + -- CPU Bus Interface + -- ********************************************************** + + -- Debug Core Interface + type dci_t is record + halt_ack : std_ulogic; -- CPU (re-)entered HALT state (single-shot) + resume_req : std_ulogic; -- DM wants the CPU to resume when set + resume_ack : std_ulogic; -- CPU starts resuming when set (single-shot) + execute_req : std_ulogic; -- DM wants CPU to execute program buffer when set + execute_ack : std_ulogic; -- CPU starts executing program buffer when set (single-shot) + exception_ack : std_ulogic; -- CPU has detected an exception (single-shot) + progbuf : std_ulogic_vector(255 downto 0); -- program buffer, 4 32-bit entries + data_we : std_ulogic; -- write abstract data + wdata : std_ulogic_vector(31 downto 0); -- abstract write data + rdata : std_ulogic_vector(31 downto 0); -- abstract read data + end record; + signal dci : dci_t; + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(dm_size_c); -- low address boundary bit + + -- status and control register - bits -- + constant sreg_halt_ack_c : natural := 0; -- -/w: CPU is halted in debug mode and waits in park loop + constant sreg_resume_req_c : natural := 1; -- r/-: DM requests CPU to resume + constant sreg_resume_ack_c : natural := 2; -- -/w: CPU starts resuming + constant sreg_execute_req_c : natural := 3; -- r/-: DM requests to execute program buffer + constant sreg_execute_ack_c : natural := 4; -- -/w: CPU starts to execute program buffer + constant sreg_exception_ack_c : natural := 5; -- -/w: CPU has detected an exception + + -- code ROM containing "park loop" -- + type code_rom_file_t is array (0 to 31) of std_ulogic_vector(31 downto 0); + constant code_rom_file : code_rom_file_t := ( + 00000000 => x"0180006f", + 00000001 => x"7b241073", + 00000002 => x"02000413", + 00000003 => x"98802023", + 00000004 => x"7b202473", + 00000005 => x"00100073", + 00000006 => x"7b241073", + 00000007 => x"00100413", + 00000008 => x"98802023", + 00000009 => x"98002403", + 00000010 => x"00847413", + 00000011 => x"02041263", + 00000012 => x"98002403", + 00000013 => x"00247413", + 00000014 => x"00041463", + 00000015 => x"fe9ff06f", + 00000016 => x"00400413", + 00000017 => x"98802023", + 00000018 => x"7b202473", + 00000019 => x"7b200073", + 00000020 => x"01000413", + 00000021 => x"98802023", + 00000022 => x"7b202473", + 00000023 => x"0000100f", + 00000024 => x"88000067", + others => x"00100073" -- ebreak + ); + + -- global access control -- + signal acc_en : std_ulogic; + signal rden : std_ulogic; + signal wren : std_ulogic; + signal maddr : std_ulogic_vector(01 downto 0); + + -- data buffer -- + signal data_buf : std_ulogic_vector(31 downto 0); + + -- program buffer access -- + type prog_buf_t is array (0 to 3) of std_ulogic_vector(31 downto 0); + signal prog_buf : prog_buf_t; + +begin + + -- Debug Module Command Controller -------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + dm_controller: process(clk_i) + begin + if rising_edge(clk_i) then + if (dm_reg.dmcontrol_dmactive = '0') or (dmi_rstn_i = '0') then -- DM reset / DM disabled + dm_ctrl.state <= CMD_IDLE; + dm_ctrl.ldsw_progbuf <= (others => '-'); + dci.execute_req <= '0'; + dm_ctrl.pbuf_en <= '-'; + -- + dm_ctrl.illegal_cmd <= '-'; + dm_ctrl.illegal_state <= '-'; + dm_ctrl.cmderr <= "000"; + -- + dm_ctrl.hart_reset <= '0'; + dm_ctrl.hart_halted <= '0'; + dm_ctrl.hart_resume_req <= '0'; + dm_ctrl.hart_resume_ack <= '0'; + else -- DM active + + -- defaults -- + dci.execute_req <= '0'; + dm_ctrl.illegal_cmd <= '0'; + dm_ctrl.illegal_state <= '0'; + + -- command execution fsm -- + case dm_ctrl.state is + + when CMD_IDLE => -- wait for new abstract command + -- ------------------------------------------------------------ + if (dmi_req_valid_i = '1') and (dmi_req_op_i = '1') then -- valid DM write access + if (dmi_req_addr_i = addr_command_c) then + if (dm_ctrl.cmderr = "000") then -- only execute if no error + dm_ctrl.state <= CMD_EXE_CHECK; + end if; + end if; + elsif (dm_reg.autoexec_rd = '1') or (dm_reg.autoexec_wr = '1') then -- auto execution trigger + dm_ctrl.state <= CMD_EXE_CHECK; + end if; + + when CMD_EXE_CHECK => -- check if command is valid / supported + -- ------------------------------------------------------------ + if (dm_reg.command(31 downto 24) = x"00") and -- cmdtype: register access + (dm_reg.command(23) = '0') and -- reserved + (dm_reg.command(22 downto 20) = "010") and -- aarsize: has to be 32-bit + (dm_reg.command(19) = '0') and -- aarpostincrement: not supported + ((dm_reg.command(17) = '0') or (dm_reg.command(15 downto 05) = "00010000000")) then -- regno: only GPRs are supported: 0x1000..0x101f if transfer is set + if (dm_ctrl.hart_halted = '1') then -- CPU is halted + dm_ctrl.state <= CMD_EXE_PREPARE; + else -- error! CPU is still running + dm_ctrl.illegal_state <= '1'; + dm_ctrl.state <= CMD_EXE_ERROR; + end if; + else -- invalid command + dm_ctrl.illegal_cmd <= '1'; + dm_ctrl.state <= CMD_EXE_ERROR; + end if; + + when CMD_EXE_PREPARE => -- setup program buffer + -- ------------------------------------------------------------ + if (dm_reg.command(17) = '1') then -- "transfer" + if (dm_reg.command(16) = '0') then -- "write" = 0 -> read from GPR + dm_ctrl.ldsw_progbuf <= instr_sw_c; + dm_ctrl.ldsw_progbuf(31 downto 25) <= dataaddr_c(11 downto 05); -- destination address + dm_ctrl.ldsw_progbuf(24 downto 20) <= dm_reg.command(4 downto 0); -- "regno" = source register + dm_ctrl.ldsw_progbuf(11 downto 07) <= dataaddr_c(04 downto 00); -- destination address + else -- "write" = 0 -> write to GPR + dm_ctrl.ldsw_progbuf <= instr_lw_c; + dm_ctrl.ldsw_progbuf(31 downto 20) <= dataaddr_c; -- source address + dm_ctrl.ldsw_progbuf(11 downto 07) <= dm_reg.command(4 downto 0); -- "regno" = destination register + end if; + else + dm_ctrl.ldsw_progbuf <= instr_nop_c; -- NOP - do nothing + end if; + -- + if (dm_reg.command(18) = '1') then -- "postexec" - execute program buffer + dm_ctrl.pbuf_en <= '1'; + else -- execute all program buffer entries as NOPs + dm_ctrl.pbuf_en <= '0'; + end if; + -- + dm_ctrl.state <= CMD_EXE_TRIGGER; + + when CMD_EXE_TRIGGER => -- request CPU to execute command + -- ------------------------------------------------------------ + dci.execute_req <= '1'; -- request execution + if (dci.execute_ack = '1') then -- CPU starts execution + dm_ctrl.state <= CMD_EXE_BUSY; + end if; + + when CMD_EXE_BUSY => -- wait for CPU to finish + -- ------------------------------------------------------------ + if (dci.halt_ack = '1') then -- CPU is parked (halted) again -> execution done + dm_ctrl.state <= CMD_IDLE; + end if; + + when CMD_EXE_ERROR => -- delay cycle for error to arrive abstracts.cmderr + -- ------------------------------------------------------------ + dm_ctrl.state <= CMD_IDLE; + + when others => -- undefined + -- ------------------------------------------------------------ + dm_ctrl.state <= CMD_IDLE; + + end case; + + + -- error flags -- + -- ------------------------------------------------------------ + if (dm_ctrl.cmderr = "000") then -- set new error + if (dm_ctrl.illegal_state = '1') then -- cannot execute since hart is not in expected state + dm_ctrl.cmderr <= "100"; + elsif (dci.exception_ack = '1') then -- exception during execution + dm_ctrl.cmderr <= "011"; + elsif (dm_ctrl.illegal_cmd = '1') then -- unsupported command + dm_ctrl.cmderr <= "010"; + elsif (dm_reg.rd_acc_err = '1') or (dm_reg.wr_acc_err = '1') then -- invalid read/write while command is executing + dm_ctrl.cmderr <= "001"; + end if; + elsif (dm_reg.clr_acc_err = '1') then -- acknowledge/clear error flags + dm_ctrl.cmderr <= "000"; + end if; + + + -- hart status -- + -- ------------------------------------------------------------ + + -- HALTED -- + if (dm_reg.dmcontrol_ndmreset = '1') then + dm_ctrl.hart_halted <= '0'; + elsif (dci.halt_ack = '1') then + dm_ctrl.hart_halted <= '1'; + elsif (dci.resume_ack = '1') then + dm_ctrl.hart_halted <= '0'; + end if; + + -- RESUME REQ -- + if (dm_reg.dmcontrol_ndmreset = '1') then + dm_ctrl.hart_resume_req <= '0'; + elsif (dm_reg.resume_req = '1') then + dm_ctrl.hart_resume_req <= '1'; + elsif (dci.resume_ack = '1') then + dm_ctrl.hart_resume_req <= '0'; + end if; + + -- RESUME ACK -- + if (dm_reg.dmcontrol_ndmreset = '1') then + dm_ctrl.hart_resume_ack <= '0'; + elsif (dci.resume_ack = '1') then + dm_ctrl.hart_resume_ack <= '1'; + elsif (dm_reg.resume_req = '1') then + dm_ctrl.hart_resume_ack <= '0'; + end if; + + -- hart has been RESET -- + if (dm_reg.dmcontrol_ndmreset = '1') then + dm_ctrl.hart_reset <= '1'; + elsif (dm_reg.reset_ack = '1') then + dm_ctrl.hart_reset <= '0'; + end if; + + end if; + end if; + end process dm_controller; + + -- controller busy flag -- + dm_ctrl.busy <= '0' when (dm_ctrl.state = CMD_IDLE) else '1'; + + + -- Debug Module Interface - Write Access -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + dmi_write_access: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + dm_reg.dmcontrol_ndmreset <= '0'; + dm_reg.dmcontrol_dmactive <= '0'; -- DM is in reset state after hardware reset + -- + dm_reg.abstractauto_autoexecdata <= '0'; + dm_reg.abstractauto_autoexecprogbuf <= "00"; + -- + dm_reg.command <= (others => '0'); + dm_reg.progbuf <= (others => instr_nop_c); + -- + dm_reg.halt_req <= '0'; + dm_reg.resume_req <= '0'; + dm_reg.reset_ack <= '0'; + dm_reg.wr_acc_err <= '0'; + dm_reg.clr_acc_err <= '0'; + dm_reg.autoexec_wr <= '0'; + elsif rising_edge(clk_i) then + + -- default -- + dm_reg.resume_req <= '0'; + dm_reg.reset_ack <= '0'; + dm_reg.wr_acc_err <= '0'; + dm_reg.clr_acc_err <= '0'; + dm_reg.autoexec_wr <= '0'; + + -- DMI access -- + if (dmi_req_valid_i = '1') and (dmi_req_op_i = '1') then -- valid DMI write request + + -- debug module control -- + if (dmi_req_addr_i = addr_dmcontrol_c) then + dm_reg.halt_req <= dmi_req_data_i(31); -- haltreq (-/w): write 1 to request halt; has to be cleared again by debugger + dm_reg.resume_req <= dmi_req_data_i(30); -- resumereq (-/w1): write 1 to request resume + dm_reg.reset_ack <= dmi_req_data_i(28); -- ackhavereset (-/w1) + dm_reg.dmcontrol_ndmreset <= dmi_req_data_i(01); -- ndmreset (r/w): soc reset + dm_reg.dmcontrol_dmactive <= dmi_req_data_i(00); -- dmactive (r/w): DM reset + end if; + + -- write abstract command -- + if (dmi_req_addr_i = addr_command_c) then + if (dm_ctrl.busy = '0') and (dm_ctrl.cmderr = "000") then -- idle and no errors yet + dm_reg.command <= dmi_req_data_i; + end if; + end if; + + -- write abstract command autoexec -- + if (dmi_req_addr_i = addr_abstractauto_c) then + if (dm_ctrl.busy = '0') then -- idle and no errors yet + dm_reg.abstractauto_autoexecdata <= dmi_req_data_i(00); + dm_reg.abstractauto_autoexecprogbuf(0) <= dmi_req_data_i(16); + dm_reg.abstractauto_autoexecprogbuf(1) <= dmi_req_data_i(17); + end if; + end if; + + -- auto execution trigger -- + if ((dmi_req_addr_i = addr_data0_c) and (dm_reg.abstractauto_autoexecdata = '1')) or + ((dmi_req_addr_i = addr_progbuf0_c) and (dm_reg.abstractauto_autoexecprogbuf(0) = '1')) or + ((dmi_req_addr_i = addr_progbuf1_c) and (dm_reg.abstractauto_autoexecprogbuf(1) = '1')) then + dm_reg.autoexec_wr <= '1'; + end if; + + -- acknowledge command error -- + if (dmi_req_addr_i = addr_abstractcs_c) then + if (dmi_req_data_i(10 downto 8) = "111") then + dm_reg.clr_acc_err <= '1'; + end if; + end if; + + -- write program buffer -- + if (dmi_req_addr_i(dmi_req_addr_i'left downto 1) = addr_progbuf0_c(dmi_req_addr_i'left downto 1)) then + if (dm_ctrl.busy = '0') then -- idle + if (dmi_req_addr_i(0) = addr_progbuf0_c(0)) then + dm_reg.progbuf(0) <= dmi_req_data_i; + else + dm_reg.progbuf(1) <= dmi_req_data_i; + end if; + end if; + end if; + + -- invalid access (while command is executing) -- + if (dm_ctrl.busy = '1') then -- busy + if (dmi_req_addr_i = addr_abstractcs_c) or + (dmi_req_addr_i = addr_command_c) or + (dmi_req_addr_i = addr_abstractauto_c) or + (dmi_req_addr_i = addr_data0_c) or + (dmi_req_addr_i = addr_progbuf0_c) or + (dmi_req_addr_i = addr_progbuf1_c) then + dm_reg.wr_acc_err <= '1'; + end if; + end if; + + end if; + end if; + end process dmi_write_access; + + + -- Direct Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- write to abstract data register -- + dci.data_we <= '1' when (dmi_req_valid_i = '1') and (dmi_req_op_i = '1') and (dmi_req_addr_i = addr_data0_c) and (dm_ctrl.busy = '0') else '0'; + dci.wdata <= dmi_req_data_i; + + -- CPU halt/resume request -- + cpu_halt_req_o <= dm_reg.halt_req and dm_reg.dmcontrol_dmactive; -- single shot + dci.resume_req <= dm_ctrl.hart_resume_req; -- permanent + + -- SoC reset -- + cpu_ndmrstn_o <= not (dm_reg.dmcontrol_ndmreset and dm_reg.dmcontrol_dmactive); + + -- build program buffer array for cpu access -- + cpu_progbuf(0) <= dm_ctrl.ldsw_progbuf; -- pseudo program buffer for GPR access + cpu_progbuf(1) <= instr_nop_c when (dm_ctrl.pbuf_en = '0') else dm_reg.progbuf(0); + cpu_progbuf(2) <= instr_nop_c when (dm_ctrl.pbuf_en = '0') else dm_reg.progbuf(1); + cpu_progbuf(3) <= instr_ebreak_c; -- implicit ebreak instruction + + -- DMI status -- + dmi_resp_err_o <= '0'; -- what can go wrong? + dmi_req_ready_o <= '1'; -- always ready for new read/write accesses + + + -- Debug Module Interface - Read Access --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + dmi_read_access: process(clk_i) + begin + if rising_edge(clk_i) then + dmi_resp_valid_o <= dmi_req_valid_i; -- DMI transfer ack + dmi_resp_data_o <= (others => '0'); -- default + dm_reg.rd_acc_err <= '0'; + dm_reg.autoexec_rd <= '0'; + + case dmi_req_addr_i is + + -- debug module status register -- + when addr_dmstatus_c => + dmi_resp_data_o(31 downto 23) <= (others => '0'); -- reserved (r/-) + dmi_resp_data_o(22) <= '1'; -- impebreak (r/-): there is an implicit ebreak instruction after the visible program buffer + dmi_resp_data_o(21 downto 20) <= (others => '0'); -- reserved (r/-) + dmi_resp_data_o(19) <= dm_ctrl.hart_reset; -- allhavereset (r/-): there is only one hart that can be reset + dmi_resp_data_o(18) <= dm_ctrl.hart_reset; -- anyhavereset (r/-): there is only one hart that can be reset + dmi_resp_data_o(17) <= dm_ctrl.hart_resume_ack; -- allresumeack (r/-): there is only one hart that can acknowledge resume request + dmi_resp_data_o(16) <= dm_ctrl.hart_resume_ack; -- anyresumeack (r/-): there is only one hart that can acknowledge resume request + dmi_resp_data_o(15) <= '0'; -- allnonexistent (r/-): there is only one hart that is always existent + dmi_resp_data_o(14) <= '0'; -- anynonexistent (r/-): there is only one hart that is always existent + dmi_resp_data_o(13) <= dm_reg.dmcontrol_ndmreset; -- allunavail (r/-): there is only one hart that is unavailable during reset + dmi_resp_data_o(12) <= dm_reg.dmcontrol_ndmreset; -- anyunavail (r/-): there is only one hart that is unavailable during reset + dmi_resp_data_o(11) <= not dm_ctrl.hart_halted; -- allrunning (r/-): there is only one hart that can be RUNNING or HALTED + dmi_resp_data_o(10) <= not dm_ctrl.hart_halted; -- anyrunning (r/-): there is only one hart that can be RUNNING or HALTED + dmi_resp_data_o(09) <= dm_ctrl.hart_halted; -- allhalted (r/-): there is only one hart that can be RUNNING or HALTED + dmi_resp_data_o(08) <= dm_ctrl.hart_halted; -- anyhalted (r/-): there is only one hart that can be RUNNING or HALTED + dmi_resp_data_o(07) <= '1'; -- authenticated (r/-): authentication passed since there is no authentication + dmi_resp_data_o(06) <= '0'; -- authbusy (r/-): always ready since there is no authentication + dmi_resp_data_o(05) <= '0'; -- hasresethaltreq (r/-): halt-on-reset not implemented + dmi_resp_data_o(04) <= '0'; -- confstrptrvalid (r/-): no configuration string available + dmi_resp_data_o(03 downto 00) <= "0010"; -- version (r/-): compatible to version 0.13 + + -- debug module control -- + when addr_dmcontrol_c => + dmi_resp_data_o(31) <= '0'; -- haltreq (-/w): write-only + dmi_resp_data_o(30) <= '0'; -- resumereq (-/w1): write-only + dmi_resp_data_o(29) <= '0'; -- hartreset (r/w): not supported + dmi_resp_data_o(28) <= '0'; -- ackhavereset (-/w1): write-only + dmi_resp_data_o(27) <= '0'; -- reserved (r/-) + dmi_resp_data_o(26) <= '0'; -- hasel (r/-) - there is a single currently selected hart + dmi_resp_data_o(25 downto 16) <= (others => '0'); -- hartsello (r/-) - there is only one hart + dmi_resp_data_o(15 downto 06) <= (others => '0'); -- hartselhi (r/-) - there is only one hart + dmi_resp_data_o(05 downto 04) <= (others => '0'); -- reserved (r/-) + dmi_resp_data_o(03) <= '0'; -- setresethaltreq (-/w1): halt-on-reset request - halt-on-reset not implemented + dmi_resp_data_o(02) <= '0'; -- clrresethaltreq (-/w1): halt-on-reset ack - halt-on-reset not implemented + dmi_resp_data_o(01) <= dm_reg.dmcontrol_ndmreset; -- ndmreset (r/w): soc reset + dmi_resp_data_o(00) <= dm_reg.dmcontrol_dmactive; -- dmactive (r/w): DM reset + + -- hart info -- + when addr_hartinfo_c => + dmi_resp_data_o(31 downto 24) <= (others => '0'); -- reserved (r/-) + dmi_resp_data_o(23 downto 20) <= nscratch_c; -- nscratch (r/-): number of dscratch CSRs + dmi_resp_data_o(19 downto 17) <= (others => '0'); -- reserved (r/-) + dmi_resp_data_o(16) <= dataaccess_c; -- dataaccess (r/-): 1: data registers are memory-mapped, 0: data reisters are CSR-mapped + dmi_resp_data_o(15 downto 12) <= datasize_c; -- datasize (r/-): number data registers in memory/CSR space + dmi_resp_data_o(11 downto 00) <= dataaddr_c; -- dataaddr (r/-): data registers base address (memory/CSR) + + -- abstract control and status -- + when addr_abstractcs_c => + dmi_resp_data_o(31 downto 24) <= (others => '0'); -- reserved (r/-) + dmi_resp_data_o(28 downto 24) <= "00010"; -- progbufsize (r/-): number of words in program buffer = 2 + dmi_resp_data_o(12) <= dm_ctrl.busy; -- busy (r/-): abstract command in progress (1) / idle (0) + dmi_resp_data_o(11) <= '0'; -- reserved (r/-) + dmi_resp_data_o(10 downto 08) <= dm_ctrl.cmderr; -- cmderr (r/w1c): any error during execution? + dmi_resp_data_o(07 downto 04) <= (others => '0'); -- reserved (r/-) + dmi_resp_data_o(03 downto 00) <= "0001"; -- datacount (r/-): number of implemented data registers = 1 + +-- -- abstract command (-/w) -- +-- when addr_command_c => +-- dmi_resp_data_o <= (others => '0'); -- register is write-only + + -- abstract command autoexec (r/w) -- + when addr_abstractauto_c => + dmi_resp_data_o(00) <= dm_reg.abstractauto_autoexecdata; -- autoexecdata(0): read/write access to data0 triggers execution of program buffer + dmi_resp_data_o(16) <= dm_reg.abstractauto_autoexecprogbuf(0); -- autoexecprogbuf(0): read/write access to progbuf0 triggers execution of program buffer + dmi_resp_data_o(17) <= dm_reg.abstractauto_autoexecprogbuf(1); -- autoexecprogbuf(1): read/write access to progbuf1 triggers execution of program buffer + +-- -- next debug module (r/-) -- +-- when addr_nextdm_c => +-- dmi_resp_data_o <= (others => '0'); -- this is the only DM + + -- abstract data 0 (r/w) -- + when addr_data0_c => + dmi_resp_data_o <= dci.rdata; + + -- program buffer (r/w) -- + when addr_progbuf0_c => + dmi_resp_data_o <= dm_reg.progbuf(0); -- program buffer 0 + when addr_progbuf1_c => + dmi_resp_data_o <= dm_reg.progbuf(1); -- program buffer 1 + +-- -- system bus access control and status (r/-) -- +-- when addr_sbcs_c => +-- dmi_resp_data_o <= (others => '0'); -- bus access not implemented + + -- halt summary 0 (r/-) -- + when addr_haltsum0_c => + dmi_resp_data_o(0) <= dm_ctrl.hart_halted; -- hart is halted + + -- not implemented (r/-) -- + when others => + dmi_resp_data_o <= (others => '0'); + end case; + + -- invalid read access (while command is executing) + -- ------------------------------------------------------------ + if (dmi_req_valid_i = '1') and (dmi_req_op_i = '0') then -- valid DMI read request + if (dm_ctrl.busy = '1') then -- busy + if (dmi_req_addr_i = addr_data0_c) or + (dmi_req_addr_i = addr_progbuf0_c) or + (dmi_req_addr_i = addr_progbuf1_c) then + dm_reg.rd_acc_err <= '1'; + end if; + end if; + end if; + + -- auto execution trigger -- + -- ------------------------------------------------------------ + if (dmi_req_valid_i = '1') and (dmi_req_op_i = '0') then -- valid DMI read request + if ((dmi_req_addr_i = addr_data0_c) and (dm_reg.abstractauto_autoexecdata = '1')) or + ((dmi_req_addr_i = addr_progbuf0_c) and (dm_reg.abstractauto_autoexecprogbuf(0) = '1')) or + ((dmi_req_addr_i = addr_progbuf1_c) and (dm_reg.abstractauto_autoexecprogbuf(1) = '1')) then + dm_reg.autoexec_rd <= '1'; + end if; + end if; + + end if; + end process dmi_read_access; + + + -- ************************************************************************************************************************** + -- CPU Bus Interface + -- ************************************************************************************************************************** + + -- Access Control ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (cpu_addr_i(hi_abb_c downto lo_abb_c) = dm_base_c(hi_abb_c downto lo_abb_c)) else '0'; + maddr <= cpu_addr_i(lo_abb_c-1 downto lo_abb_c-2); -- (sub-)module select address + rden <= acc_en and cpu_rden_i; + wren <= acc_en and cpu_wren_i; + + + -- Write Access --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + write_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- Data buffer -- + if (dci.data_we = '1') then -- DM write access + data_buf <= dci.wdata; + elsif (acc_en = '1') and (maddr = "10") and (wren = '1') then -- BUS write access + data_buf <= cpu_data_i; + end if; + -- Control and Status Register -- + dci.halt_ack <= '0'; -- all writable flags auto-clear + dci.resume_ack <= '0'; + dci.execute_ack <= '0'; + dci.exception_ack <= '0'; + if (acc_en = '1') and (maddr = "11") and (wren = '1') then + dci.halt_ack <= cpu_data_i(sreg_halt_ack_c); + dci.resume_ack <= cpu_data_i(sreg_resume_ack_c); + dci.execute_ack <= cpu_data_i(sreg_execute_ack_c); + dci.exception_ack <= cpu_data_i(sreg_exception_ack_c); + end if; + end if; + end process write_access; + + -- DM data buffer read access -- + dci.rdata <= data_buf; + + + -- Read Access ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + read_access: process(clk_i) + begin + if rising_edge(clk_i) then + cpu_ack_o <= rden or wren; + cpu_data_o <= (others => '0'); + if (rden = '1') then -- output gate + case maddr is -- module select + when "00" => -- code ROM + cpu_data_o <= code_rom_file(to_integer(unsigned(cpu_addr_i(6 downto 2)))); + when "01" => -- program buffer + cpu_data_o <= cpu_progbuf(to_integer(unsigned(cpu_addr_i(3 downto 2)))); + when "10" => -- data buffer + cpu_data_o <= data_buf; + when others => -- status/control register + cpu_data_o(sreg_resume_req_c) <= dci.resume_req; + cpu_data_o(sreg_execute_req_c) <= dci.execute_req; + end case; + end if; + end if; + end process read_access; + + +end neorv32_debug_dm_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_debug_dtm.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_debug_dtm.vhd new file mode 100644 index 0000000..fe86d43 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_debug_dtm.vhd @@ -0,0 +1,353 @@ +-- ################################################################################################# +-- # << NEORV32 - RISC-V Debug Transport Module (DTM) >> # +-- # ********************************************************************************************* # +-- # Provides a JTAG-compatible TAP to access the DMI register interface. # +-- # Compatible to the RISC-V debug specification. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # https://github.com/stnolting/riscv-debug-dtm (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity neorv32_debug_dtm is + generic ( + IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version + IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number + IDCODE_MANID : std_ulogic_vector(10 downto 0) -- manufacturer id + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + -- jtag connection -- + jtag_trst_i : in std_ulogic; + jtag_tck_i : in std_ulogic; + jtag_tdi_i : in std_ulogic; + jtag_tdo_o : out std_ulogic; + jtag_tms_i : in std_ulogic; + -- debug module interface (DMI) -- + dmi_rstn_o : out std_ulogic; + dmi_req_valid_o : out std_ulogic; + dmi_req_ready_i : in std_ulogic; -- DMI is allowed to make new requests when set + dmi_req_addr_o : out std_ulogic_vector(06 downto 0); + dmi_req_op_o : out std_ulogic; -- 0=read, 1=write + dmi_req_data_o : out std_ulogic_vector(31 downto 0); + dmi_resp_valid_i : in std_ulogic; -- response valid when set + dmi_resp_ready_o : out std_ulogic; -- ready to receive respond + dmi_resp_data_i : in std_ulogic_vector(31 downto 0); + dmi_resp_err_i : in std_ulogic -- 0=ok, 1=error + ); +end neorv32_debug_dtm; + +architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is + + -- DMI Configuration (fixed!) -- + constant dmi_idle_c : std_ulogic_vector(02 downto 0) := "000"; -- no idle cycles required + constant dmi_version_c : std_ulogic_vector(03 downto 0) := "0001"; -- version (0.13) + constant dmi_abits_c : std_ulogic_vector(05 downto 0) := "000111"; -- number of DMI address bits (7) + + -- tap JTAG signal synchronizer -- + type tap_sync_t is record + -- internal -- + trst_ff : std_ulogic_vector(2 downto 0); + tck_ff : std_ulogic_vector(2 downto 0); + tdi_ff : std_ulogic_vector(2 downto 0); + tms_ff : std_ulogic_vector(2 downto 0); + -- external -- + trst : std_ulogic; + tck_rising : std_ulogic; + tck_falling : std_ulogic; + tdi : std_ulogic; + tdo : std_ulogic; + tms : std_ulogic; + end record; + signal tap_sync : tap_sync_t; + + -- tap controller - fsm -- + type tap_ctrl_state_t is (LOGIC_RESET, DR_SCAN, DR_CAPTURE, DR_SHIFT, DR_EXIT1, DR_PAUSE, DR_EXIT2, DR_UPDATE, + RUN_IDLE, IR_SCAN, IR_CAPTURE, IR_SHIFT, IR_EXIT1, IR_PAUSE, IR_EXIT2, IR_UPDATE); + type tap_ctrl_t is record + state : tap_ctrl_state_t; + state_prev : tap_ctrl_state_t; + end record; + signal tap_ctrl : tap_ctrl_t; + + -- tap registers -- + type tap_reg_t is record + ireg : std_ulogic_vector(04 downto 0); + bypass : std_ulogic; + idcode : std_ulogic_vector(31 downto 0); + dtmcs, dtmcs_nxt : std_ulogic_vector(31 downto 0); + dmi, dmi_nxt : std_ulogic_vector((7+32+2)-1 downto 0); -- 7-bit address + 32-bit data + 2-bit operation + end record; + signal tap_reg : tap_reg_t; + + -- debug module interface -- + type dmi_ctrl_state_t is (DMI_IDLE, DMI_READ_WAIT, DMI_READ, DMI_READ_BUSY, + DMI_WRITE_WAIT, DMI_WRITE, DMI_WRITE_BUSY); + type dmi_ctrl_t is record + state : dmi_ctrl_state_t; + -- + dmihardreset : std_ulogic; + dmireset : std_ulogic; + -- + err : std_ulogic; -- sticky error + rdata : std_ulogic_vector(31 downto 0); + wdata : std_ulogic_vector(31 downto 0); + addr : std_ulogic_vector(06 downto 0); + end record; + signal dmi_ctrl : dmi_ctrl_t; + +begin + + -- JTAG Signal Synchronizer --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + tap_synchronizer: process(rstn_i, clk_i) + begin + if rising_edge(clk_i) then + tap_sync.trst_ff <= tap_sync.trst_ff(1 downto 0) & jtag_trst_i; + tap_sync.tck_ff <= tap_sync.tck_ff( 1 downto 0) & jtag_tck_i; + tap_sync.tdi_ff <= tap_sync.tdi_ff( 1 downto 0) & jtag_tdi_i; + tap_sync.tms_ff <= tap_sync.tms_ff( 1 downto 0) & jtag_tms_i; + if (tap_sync.tck_falling = '1') then -- update output data TDO on falling edge of TCK + jtag_tdo_o <= tap_sync.tdo; + end if; + end if; + end process tap_synchronizer; + + -- JTAG reset -- + tap_sync.trst <= '0' when (tap_sync.trst_ff(2 downto 1) = "00") else '1'; + + -- JTAG clock edge -- + tap_sync.tck_rising <= '1' when (tap_sync.tck_ff(2 downto 1) = "01") else '0'; + tap_sync.tck_falling <= '1' when (tap_sync.tck_ff(2 downto 1) = "10") else '0'; + + -- JTAG test mode select -- + tap_sync.tms <= tap_sync.tms_ff(2); + + -- JTAG serial data input -- + tap_sync.tdi <= tap_sync.tdi_ff(2); + + + -- Tap Control FSM ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + tap_control: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + tap_ctrl.state <= LOGIC_RESET; + tap_ctrl.state_prev <= LOGIC_RESET; + elsif rising_edge(clk_i) then + tap_ctrl.state_prev <= tap_ctrl.state; + if (tap_sync.trst = '0') then -- reset + tap_ctrl.state <= LOGIC_RESET; + elsif (tap_sync.tck_rising = '1') then -- clock pulse (evaluate TMS on the rising edge of TCK) + case tap_ctrl.state is -- JTAG state machine + when LOGIC_RESET => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= LOGIC_RESET; end if; + when RUN_IDLE => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if; + when DR_SCAN => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_CAPTURE; else tap_ctrl.state <= IR_SCAN; end if; + when DR_CAPTURE => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if; + when DR_SHIFT => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if; + when DR_EXIT1 => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_UPDATE; end if; + when DR_PAUSE => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_EXIT2; end if; + when DR_EXIT2 => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_UPDATE; end if; + when DR_UPDATE => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if; + when IR_SCAN => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_CAPTURE; else tap_ctrl.state <= LOGIC_RESET; end if; + when IR_CAPTURE => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if; + when IR_SHIFT => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if; + when IR_EXIT1 => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_UPDATE; end if; + when IR_PAUSE => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_EXIT2; end if; + when IR_EXIT2 => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_UPDATE; end if; + when IR_UPDATE => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if; + when others => tap_ctrl.state <= LOGIC_RESET; + end case; + end if; + end if; + end process tap_control; + + + -- Tap Register Access -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + reg_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- serial data input -- + if (tap_sync.tck_rising = '1') then -- clock pulse (evaluate TDI on rising edge of TCK) + + -- instruction register -- + if (tap_ctrl.state = LOGIC_RESET) or (tap_ctrl.state = IR_CAPTURE) then -- reset or preload phase + tap_reg.ireg <= "00001"; -- IDCODE + elsif (tap_ctrl.state = IR_SHIFT) then -- access phase + tap_reg.ireg <= tap_sync.tdi & tap_reg.ireg(tap_reg.ireg'left downto 1); + end if; + + -- data register -- + if (tap_ctrl.state = DR_CAPTURE) then -- preload phase + case tap_reg.ireg is + when "00001" => tap_reg.idcode <= IDCODE_VERSION & IDCODE_PARTID & IDCODE_MANID & '1'; -- IDCODE (LSB has to be always set!) + when "10000" => tap_reg.dtmcs <= tap_reg.dtmcs_nxt;-- dtmcs + when "10001" => tap_reg.dmi <= tap_reg.dmi_nxt; -- dmi + when others => tap_reg.bypass <= '0'; -- BYPASS + end case; + elsif (tap_ctrl.state = DR_SHIFT) then -- access phase + case tap_reg.ireg is + when "00001" => tap_reg.idcode <= tap_sync.tdi & tap_reg.idcode(tap_reg.idcode'left downto 1); -- IDCODE + when "10000" => tap_reg.dtmcs <= tap_sync.tdi & tap_reg.dtmcs(tap_reg.dtmcs'left downto 1); -- dtmcs + when "10001" => tap_reg.dmi <= tap_sync.tdi & tap_reg.dmi(tap_reg.dmi'left downto 1); -- dmi + when others => tap_reg.bypass <= tap_sync.tdi; -- BYPASS + end case; + end if; + end if; + + -- serial data output -- + if (tap_ctrl.state = IR_SHIFT) then + tap_sync.tdo <= tap_reg.ireg(0); + else + case tap_reg.ireg is + when "00001" => tap_sync.tdo <= tap_reg.idcode(0); -- IDCODE + when "10000" => tap_sync.tdo <= tap_reg.dtmcs(0); -- dtmcs + when "10001" => tap_sync.tdo <= tap_reg.dmi(0); -- dmi + when others => tap_sync.tdo <= tap_reg.bypass; -- BYPASS + end case; + end if; + end if; + end process reg_access; + + + -- Debug Module Interface ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + dmi_controller: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + dmi_ctrl.state <= DMI_IDLE; + dmi_ctrl.dmihardreset <= '1'; + dmi_ctrl.dmireset <= '1'; + dmi_ctrl.err <= '0'; + dmi_ctrl.rdata <= (others => '-'); + dmi_ctrl.wdata <= (others => '-'); + dmi_ctrl.addr <= (others => '-'); + elsif rising_edge(clk_i) then + + -- DMI status and control -- + dmi_ctrl.dmihardreset <= '0'; -- default + dmi_ctrl.dmireset <= '0'; -- default + if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10000") then + dmi_ctrl.dmireset <= tap_reg.dtmcs(16); + dmi_ctrl.dmihardreset <= tap_reg.dtmcs(17); + end if; + + -- DMI interface arbiter -- + if (dmi_ctrl.dmihardreset = '1') then -- DMI hard reset + dmi_ctrl.state <= DMI_IDLE; + dmi_ctrl.err <= '0'; + else + case dmi_ctrl.state is + + when DMI_IDLE => -- waiting for new request + if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10001") then -- update + if (tap_reg.dmi(1 downto 0) = "01") then -- read + dmi_ctrl.state <= DMI_READ_WAIT; + elsif (tap_reg.dmi(1 downto 0) = "10") then -- write + dmi_ctrl.state <= DMI_WRITE_WAIT; + end if; + dmi_ctrl.addr <= tap_reg.dmi(40 downto 34); + dmi_ctrl.wdata <= tap_reg.dmi(33 downto 02); + end if; + + + when DMI_READ_WAIT => -- wait for DMI to become ready + if (dmi_req_ready_i = '1') then + dmi_ctrl.state <= DMI_READ; + end if; + + when DMI_READ => -- start read access + dmi_ctrl.state <= DMI_READ_BUSY; + + when DMI_READ_BUSY => -- pending read access + if (dmi_resp_valid_i = '1') then + dmi_ctrl.rdata <= dmi_resp_data_i; + dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error + dmi_ctrl.state <= DMI_IDLE; + end if; + + + when DMI_WRITE_WAIT => -- wait for DMI to become ready + if (dmi_req_ready_i = '1') then + dmi_ctrl.state <= DMI_WRITE; + end if; + + when DMI_WRITE => -- start write access + dmi_ctrl.state <= DMI_WRITE_BUSY; + + when DMI_WRITE_BUSY => -- pending write access + if (dmi_resp_valid_i = '1') then + dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error + dmi_ctrl.state <= DMI_IDLE; + end if; + + + when others => -- undefined + dmi_ctrl.state <= DMI_IDLE; + + end case; + -- clear sticky error flag -- + if (dmi_ctrl.dmireset = '1') then + dmi_ctrl.err <= '0'; + end if; + end if; + end if; + end process dmi_controller; + + -- DTM Control and Status Register (dtmcs) -- + tap_reg.dtmcs_nxt(31 downto 18) <= (others => '0'); -- unused + tap_reg.dtmcs_nxt(17) <= '0'; -- dmihardreset, always reads as zero + tap_reg.dtmcs_nxt(16) <= '0'; -- dmireset, always reads as zero + tap_reg.dtmcs_nxt(15) <= '0'; -- unused + tap_reg.dtmcs_nxt(14 downto 12) <= dmi_idle_c; -- minimum number of idle cycles + tap_reg.dtmcs_nxt(11 downto 10) <= tap_reg.dmi_nxt(1 downto 0); -- dmistat + tap_reg.dtmcs_nxt(09 downto 04) <= dmi_abits_c; -- number of DMI address bits + tap_reg.dtmcs_nxt(03 downto 00) <= dmi_version_c; -- version + + -- DMI register read access -- + tap_reg.dmi_nxt(40 downto 34) <= dmi_ctrl.addr; -- address + tap_reg.dmi_nxt(33 downto 02) <= dmi_ctrl.rdata; -- read data + tap_reg.dmi_nxt(01 downto 00) <= "11" when (dmi_ctrl.state /= DMI_IDLE) else (dmi_ctrl.err & '0'); -- status + + -- direct DMI output -- + dmi_rstn_o <= '0' when (dmi_ctrl.dmihardreset = '1') else '1'; + dmi_req_valid_o <= '1' when (dmi_ctrl.state = DMI_READ) or (dmi_ctrl.state = DMI_WRITE) else '0'; + dmi_req_op_o <= '1' when (dmi_ctrl.state = DMI_WRITE) or (dmi_ctrl.state = DMI_WRITE_BUSY) else '0'; + dmi_resp_ready_o <= '1' when (dmi_ctrl.state = DMI_READ_BUSY) or (dmi_ctrl.state = DMI_WRITE_BUSY) else '0'; + dmi_req_addr_o <= dmi_ctrl.addr; + dmi_req_data_o <= dmi_ctrl.wdata; + + +end neorv32_debug_dtm_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_dmem.entity.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_dmem.entity.vhd new file mode 100644 index 0000000..ec0fd83 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_dmem.entity.vhd @@ -0,0 +1,54 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal data memory (DMEM) >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity neorv32_dmem is + generic ( + DMEM_BASE : std_ulogic_vector(31 downto 0); -- memory base address + DMEM_SIZE : natural -- processor-internal instruction memory size in bytes + ); + port ( + clk_i : in std_ulogic; -- global clock line + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable + addr_i : in std_ulogic_vector(31 downto 0); -- address + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); +end neorv32_dmem; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_fifo.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_fifo.vhd new file mode 100644 index 0000000..dd8d794 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_fifo.vhd @@ -0,0 +1,188 @@ +-- ################################################################################################# +-- # << NEORV32 - General Purpose FIFO Component >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_fifo is + generic ( + FIFO_DEPTH : natural; -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH : natural; -- size of data elements in fifo + FIFO_RSYNC : boolean; -- false = async read; true = sync read + FIFO_SAFE : boolean -- true = allow read/write only if entry available + ); + port ( + -- control -- + clk_i : in std_ulogic; -- clock, rising edge + rstn_i : in std_ulogic; -- async reset, low-active + clear_i : in std_ulogic; -- sync reset, high-active + level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level + half_o : out std_ulogic; -- FIFO is at least half full + -- write port -- + wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data + we_i : in std_ulogic; -- write enable + free_o : out std_ulogic; -- at least one entry is free when set + -- read port -- + re_i : in std_ulogic; -- read enable + rdata_o : out std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- read data + avail_o : out std_ulogic -- data available when set + ); +end neorv32_fifo; + +architecture neorv32_fifo_rtl of neorv32_fifo is + + -- FIFO -- + type fifo_data_t is array (0 to FIFO_DEPTH-1) of std_ulogic_vector(FIFO_WIDTH-1 downto 0); + type fifo_t is record + we : std_ulogic; -- write enable + re : std_ulogic; -- read enable + w_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- write pointer + r_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- read pointer + level : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill count + data : fifo_data_t; -- fifo memory + datas : std_ulogic_vector(FIFO_WIDTH-1 downto 0); + match : std_ulogic; + empty : std_ulogic; + full : std_ulogic; + free : std_ulogic; + avail : std_ulogic; + end record; + signal fifo : fifo_t; + + signal level_diff : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (FIFO_DEPTH = 0) report "NEORV32 CONFIG ERROR: FIFO depth has to be > 0." severity error; + assert not (is_power_of_two_f(FIFO_DEPTH) = false) report "NEORV32 CONFIG ERROR: FIFO depth has to be a power of two." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + fifo.re <= re_i when (FIFO_SAFE = false) else (re_i and fifo.avail); -- read only if data available + fifo.we <= we_i when (FIFO_SAFE = false) else (we_i and fifo.free); -- write only if space left + + + -- FIFO Control --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + fifo_control: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + fifo.w_pnt <= (others => '0'); + fifo.r_pnt <= (others => '0'); + elsif rising_edge(clk_i) then + -- write port -- + if (clear_i = '1') then + fifo.w_pnt <= (others => '0'); + elsif (fifo.we = '1') then + fifo.w_pnt <= std_ulogic_vector(unsigned(fifo.w_pnt) + 1); + end if; + -- read port -- + if (clear_i = '1') then + fifo.r_pnt <= (others => '0'); + elsif (fifo.re = '1') then + fifo.r_pnt <= std_ulogic_vector(unsigned(fifo.r_pnt) + 1); + end if; + end if; + end process fifo_control; + + -- status -- + fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) or (FIFO_DEPTH = 1) else '0'; + fifo.full <= '1' when (fifo.r_pnt(fifo.r_pnt'left) /= fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0'; + fifo.empty <= '1' when (fifo.r_pnt(fifo.r_pnt'left) = fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0'; + fifo.free <= not fifo.full; + fifo.avail <= not fifo.empty; + level_diff <= std_ulogic_vector(unsigned(fifo.w_pnt) - unsigned(fifo.r_pnt)); + fifo.level <= std_ulogic_vector(to_unsigned(FIFO_DEPTH, fifo.level'length)) when (fifo.full = '1') else level_diff; + + -- status output -- + level_o <= fifo.level; + free_o <= fifo.free; + avail_o <= fifo.avail; + + fifo_half_level: + if (FIFO_DEPTH > 1) generate + half_o <= level_diff(level_diff'left-1) or fifo.full; + end generate; + + fifo_half_level_simple: + if (FIFO_DEPTH = 1) generate + half_o <= fifo.full; + end generate; + + + -- FIFO Memory ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + fifo_memory_write: process(clk_i) + begin + if rising_edge(clk_i) then + if (fifo.we = '1') then + if (FIFO_DEPTH = 1) then + fifo.datas <= wdata_i; + else + fifo.data(to_integer(unsigned(fifo.w_pnt(fifo.w_pnt'left-1 downto 0)))) <= wdata_i; + end if; + end if; + end if; + end process fifo_memory_write; + + -- asynchronous read -- + fifo_read_async: + if (FIFO_RSYNC = false) generate + rdata_o <= fifo.datas when (FIFO_DEPTH = 1) else fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0)))); + end generate; + + -- synchronous read -- + fifo_read_sync: + if (FIFO_RSYNC = true) generate + fifo_memory_read: process(clk_i) + begin + if rising_edge(clk_i) then + if (FIFO_DEPTH = 1) then + rdata_o <= fifo.datas; + else + rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0)))); + end if; + end if; + end process fifo_memory_read; + end generate; + + +end neorv32_fifo_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_gpio.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_gpio.vhd new file mode 100644 index 0000000..db6dbe3 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_gpio.vhd @@ -0,0 +1,126 @@ +-- ################################################################################################# +-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> # +-- # ********************************************************************************************* # +-- # 64-bit general purpose parallel input & output port unit. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_gpio is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- parallel io -- + gpio_o : out std_ulogic_vector(63 downto 0); + gpio_i : in std_ulogic_vector(63 downto 0) + ); +end neorv32_gpio; + +architecture neorv32_gpio_rtl of neorv32_gpio is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(gpio_size_c); -- low address boundary bit + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- accessible regs -- + signal din_lo, din_hi : std_ulogic_vector(31 downto 0); -- r/- + signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= gpio_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- bus handshake -- + ack_o <= wren or rden; + + -- write access -- + if (wren = '1') then + if (addr = gpio_out_lo_addr_c) then + dout_lo <= data_i; + end if; + if (addr = gpio_out_hi_addr_c) then + dout_hi <= data_i; + end if; + end if; + + -- input buffer -- + din_lo <= gpio_i(31 downto 00); + din_hi <= gpio_i(63 downto 32); + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + case addr(3 downto 2) is + when "00" => data_o <= din_lo; + when "01" => data_o <= din_hi; + when "10" => data_o <= dout_lo; + when others => data_o <= dout_hi; + end case; + end if; + + end if; + end process rw_access; + + -- output -- + gpio_o <= dout_hi & dout_lo; + + +end neorv32_gpio_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_gptmr.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_gptmr.vhd new file mode 100644 index 0000000..5827932 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_gptmr.vhd @@ -0,0 +1,203 @@ +-- ################################################################################################# +-- # << NEORV32 - General Purpose Timer (GPTMR) >> # +-- # ********************************************************************************************* # +-- # 32-bit timer with configurable clock prescaler. The timer fires an interrupt whenever the # +-- # counter register value reaches the programmed threshold value. The timer can operate in # +-- # single-shot mode (count until it reaches THRESHOLD and stop) or in continuous mode (count # +-- # until it reaches THRESHOLD and auto-reset). # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_gptmr is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- interrupt -- + irq_o : out std_ulogic -- transmission done interrupt + ); +end neorv32_gptmr; + +architecture neorv32_gptmr_rtl of neorv32_gptmr is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(gptmr_size_c); -- low address boundary bit + + -- control register -- + constant ctrl_en_c : natural := 0; -- r/w: timer enable + constant ctrl_prsc0_c : natural := 1; -- r/w: clock prescaler select bit 0 + constant ctrl_prsc1_c : natural := 2; -- r/w: clock prescaler select bit 1 + constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler select bit 2 + constant ctrl_mode_c : natural := 4; -- r/w: mode (0=single-shot, 1=continuous) + -- + signal ctrl : std_ulogic_vector(4 downto 0); + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- clock generator -- + signal gptmr_clk_en : std_ulogic; + + -- timer core -- + type timer_t is record + count : std_ulogic_vector(31 downto 0); -- counter register + thres : std_ulogic_vector(31 downto 0); -- threshold value + match : std_ulogic; -- count == thres + cnt_we : std_ulogic; -- write access to count + end record; + signal timer : timer_t; + + -- interrupt detector -- + signal irq_detect : std_ulogic_vector(1 downto 0); + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gptmr_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= gptmr_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- bus access acknowledge -- + ack_o <= rden or wren; + + -- write access -- + timer.cnt_we <= '0'; + if (wren = '1') then + if (addr = gptmr_ctrl_addr_c) then -- control register + ctrl(ctrl_en_c) <= data_i(ctrl_en_c); + ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c); + ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c); + ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c); + ctrl(ctrl_mode_c) <= data_i(ctrl_mode_c); + end if; + if (addr = gptmr_thres_addr_c) then -- threshold register + timer.thres <= data_i; + end if; + if (addr = gptmr_count_addr_c) then -- counter register + timer.cnt_we <= '1'; + end if; + end if; + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + case addr(3 downto 2) is + when "00" => -- control register + data_o(ctrl_en_c) <= ctrl(ctrl_en_c); + data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c); + data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c); + data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c); + data_o(ctrl_mode_c) <= ctrl(ctrl_mode_c); + when "01" => -- threshold register + data_o <= timer.thres; + when others => -- counter register + data_o <= timer.count; + end case; + end if; + end if; + end process rw_access; + + -- clock generator enable -- + clkgen_en_o <= ctrl(ctrl_en_c); + + -- clock select -- + gptmr_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c)))); + + + -- Timer Core ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + timer_core: process(clk_i) + begin + if rising_edge(clk_i) then + if (timer.cnt_we = '1') then -- write access + timer.count <= data_i; + elsif (ctrl(ctrl_en_c) = '1') and (gptmr_clk_en = '1') then -- enabled and clock tick + if (timer.match = '1') then + if (ctrl(ctrl_mode_c) = '1') then -- reset counter if continuous mode + timer.count <= (others => '0'); + end if; + else + timer.count <= std_ulogic_vector(unsigned(timer.count) + 1); + end if; + end if; + end if; + end process timer_core; + + -- counter = threshold? -- + timer.match <= '1' when (timer.count = timer.thres) else '0'; + + + -- Interrupt Generator -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + irq_generator: process(clk_i) + begin + if rising_edge(clk_i) then + if (ctrl(ctrl_en_c) = '0') then + irq_detect <= "00"; + else + irq_detect <= irq_detect(0) & timer.match; + end if; + end if; + end process irq_generator; + + -- IRQ request to CPU -- + irq_o <= '1' when (irq_detect = "01") else '0'; + + +end neorv32_gptmr_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_icache.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_icache.vhd new file mode 100644 index 0000000..61b9284 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_icache.vhd @@ -0,0 +1,589 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-Internal Instruction Cache >> # +-- # ********************************************************************************************* # +-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). # +-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_icache is + generic ( + ICACHE_NUM_BLOCKS : natural; -- number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural; -- block size in bytes (min 4), has to be a power of 2 + ICACHE_NUM_SETS : natural -- associativity / number of sets (1=direct_mapped), has to be a power of 2 + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + clear_i : in std_ulogic; -- cache clear + -- host controller interface -- + host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable + host_we_i : in std_ulogic; -- write enable + host_re_i : in std_ulogic; -- read enable + host_ack_o : out std_ulogic; -- bus transfer acknowledge + host_err_o : out std_ulogic; -- bus transfer error + -- peripheral bus interface -- + bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + bus_we_o : out std_ulogic; -- write enable + bus_re_o : out std_ulogic; -- read enable + bus_ack_i : in std_ulogic; -- bus transfer acknowledge + bus_err_i : in std_ulogic -- bus transfer error + ); +end neorv32_icache; + +architecture neorv32_icache_rtl of neorv32_icache is + + -- cache layout -- + constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words + constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS); + constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset + + -- cache memory -- + component neorv32_icache_memory + generic ( + ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 + ICACHE_NUM_SETS : natural := 1 -- associativity; 0=direct-mapped, 1=2-way set-associative + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + invalidate_i : in std_ulogic; -- invalidate whole cache + -- host cache access (read-only) -- + host_addr_i : in std_ulogic_vector(31 downto 0); -- access address + host_re_i : in std_ulogic; -- read enable + host_rdata_o : out std_ulogic_vector(31 downto 0); -- read data + -- access status (1 cycle delay to access) -- + hit_o : out std_ulogic; -- hit access + -- ctrl cache access (write-only) -- + ctrl_en_i : in std_ulogic; -- control interface enable + ctrl_addr_i : in std_ulogic_vector(31 downto 0); -- access address + ctrl_we_i : in std_ulogic; -- write enable (full-word) + ctrl_wdata_i : in std_ulogic_vector(31 downto 0); -- write data + ctrl_tag_we_i : in std_ulogic; -- write tag to selected block + ctrl_valid_i : in std_ulogic; -- make selected block valid + ctrl_invalid_i : in std_ulogic -- make selected block invalid + ); + end component; + + -- cache interface -- + type cache_if_t is record + clear : std_ulogic; -- cache clear + -- + host_addr : std_ulogic_vector(31 downto 0); -- cpu access address + host_rdata : std_ulogic_vector(31 downto 0); -- cpu read data + -- + hit : std_ulogic; -- hit access + -- + ctrl_en : std_ulogic; -- control access enable + ctrl_addr : std_ulogic_vector(31 downto 0); -- control access address + ctrl_we : std_ulogic; -- control write enable + ctrl_wdata : std_ulogic_vector(31 downto 0); -- control write data + ctrl_tag_we : std_ulogic; -- control tag write enabled + ctrl_valid_we : std_ulogic; -- control valid flag set + ctrl_invalid_we : std_ulogic; -- control valid flag clear + end record; + signal cache : cache_if_t; + + -- control engine -- + type ctrl_engine_state_t is (S_IDLE, S_CACHE_CLEAR, S_CACHE_CHECK, S_CACHE_MISS, S_BUS_DOWNLOAD_REQ, S_BUS_DOWNLOAD_GET, + S_CACHE_RESYNC_0, S_CACHE_RESYNC_1, S_BUS_ERROR); + type ctrl_t is record + state : ctrl_engine_state_t; -- current state + state_nxt : ctrl_engine_state_t; -- next state + addr_reg : std_ulogic_vector(31 downto 0); -- address register for block download + addr_reg_nxt : std_ulogic_vector(31 downto 0); + -- + re_buf : std_ulogic; -- read request buffer + re_buf_nxt : std_ulogic; + -- + clear_buf : std_ulogic; -- clear request buffer + clear_buf_nxt : std_ulogic; + end record; + signal ctrl : ctrl_t; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- configuration -- + assert not (is_power_of_two_f(ICACHE_NUM_BLOCKS) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks has to be a power of 2." severity error; + assert not (is_power_of_two_f(ICACHE_BLOCK_SIZE) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size has to be a power of 2." severity error; + assert not ((is_power_of_two_f(ICACHE_NUM_SETS) = false)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity has to be a power of 2." severity error; + assert not (ICACHE_NUM_BLOCKS < 1) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks has to be >= 1." severity error; + assert not (ICACHE_BLOCK_SIZE < 4) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size has to be >= 4." severity error; + assert not ((ICACHE_NUM_SETS = 0) or (ICACHE_NUM_SETS > 2)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error; + + + -- Control Engine FSM Sync ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- registers that REQUIRE a specific reset state -- + ctrl_engine_fsm_sync_rst: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl.state <= S_CACHE_CLEAR; + ctrl.re_buf <= '0'; + ctrl.clear_buf <= '0'; + elsif rising_edge(clk_i) then + ctrl.state <= ctrl.state_nxt; + ctrl.re_buf <= ctrl.re_buf_nxt; + ctrl.clear_buf <= ctrl.clear_buf_nxt; + end if; + end process ctrl_engine_fsm_sync_rst; + + -- registers that do not require a specific reset state -- + ctrl_engine_fsm_sync: process(clk_i) + begin + if rising_edge(clk_i) then + ctrl.addr_reg <= ctrl.addr_reg_nxt; + end if; + end process ctrl_engine_fsm_sync; + + + -- Control Engine FSM Comb ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ctrl_engine_fsm_comb: process(ctrl, cache, clear_i, host_addr_i, host_re_i, bus_rdata_i, bus_ack_i, bus_err_i) + begin + -- control defaults -- + ctrl.state_nxt <= ctrl.state; + ctrl.addr_reg_nxt <= ctrl.addr_reg; + ctrl.re_buf_nxt <= ctrl.re_buf or host_re_i; + ctrl.clear_buf_nxt <= ctrl.clear_buf or clear_i; -- buffer clear request from CPU + + -- cache defaults -- + cache.clear <= '0'; + cache.host_addr <= host_addr_i; + cache.ctrl_en <= '0'; + cache.ctrl_addr <= ctrl.addr_reg; + cache.ctrl_we <= '0'; + cache.ctrl_wdata <= bus_rdata_i; + cache.ctrl_tag_we <= '0'; + cache.ctrl_valid_we <= '0'; + cache.ctrl_invalid_we <= '0'; + + -- host interface defaults -- + host_ack_o <= '0'; + host_err_o <= '0'; + host_rdata_o <= cache.host_rdata; + + -- peripheral bus interface defaults -- + bus_addr_o <= ctrl.addr_reg; + bus_wdata_o <= (others => '0'); -- cache is read-only + bus_ben_o <= (others => '0'); -- cache is read-only + bus_we_o <= '0'; -- cache is read-only + bus_re_o <= '0'; + + -- fsm -- + case ctrl.state is + + when S_IDLE => -- wait for host access request or cache control operation + -- ------------------------------------------------------------ + if (ctrl.clear_buf = '1') then -- cache control operation? + ctrl.state_nxt <= S_CACHE_CLEAR; + elsif (host_re_i = '1') or (ctrl.re_buf = '1') then -- cache access + ctrl.re_buf_nxt <= '0'; + ctrl.state_nxt <= S_CACHE_CHECK; + end if; + + when S_CACHE_CLEAR => -- invalidate all cache entries + -- ------------------------------------------------------------ + ctrl.clear_buf_nxt <= '0'; + cache.clear <= '1'; + ctrl.state_nxt <= S_IDLE; + + when S_CACHE_CHECK => -- finalize host access if cache hit + -- ------------------------------------------------------------ + if (cache.hit = '1') then -- cache HIT + host_ack_o <= '1'; + ctrl.state_nxt <= S_IDLE; + else -- cache MISS + ctrl.state_nxt <= S_CACHE_MISS; + end if; + + when S_CACHE_MISS => -- + -- ------------------------------------------------------------ + -- compute block base address -- + ctrl.addr_reg_nxt <= host_addr_i; + ctrl.addr_reg_nxt((2+cache_offset_size_c)-1 downto 2) <= (others => '0'); -- block-aligned + ctrl.addr_reg_nxt(1 downto 0) <= "00"; -- word-aligned + -- + ctrl.state_nxt <= S_BUS_DOWNLOAD_REQ; + + when S_BUS_DOWNLOAD_REQ => -- download new cache block: request new word + -- ------------------------------------------------------------ + cache.ctrl_en <= '1'; -- we are in cache control mode + bus_re_o <= '1'; -- request new read transfer + ctrl.state_nxt <= S_BUS_DOWNLOAD_GET; + + when S_BUS_DOWNLOAD_GET => -- download new cache block: wait for bus response + -- ------------------------------------------------------------ + cache.ctrl_en <= '1'; -- we are in cache control mode + -- + if (bus_err_i = '1') then -- bus error + ctrl.state_nxt <= S_BUS_ERROR; + elsif (bus_ack_i = '1') then -- ACK = write to cache and get next word + cache.ctrl_we <= '1'; -- write to cache + if (and_reduce_f(ctrl.addr_reg((2+cache_offset_size_c)-1 downto 2)) = '1') then -- block complete? + cache.ctrl_tag_we <= '1'; -- current block is valid now + cache.ctrl_valid_we <= '1'; -- write tag of current address + ctrl.state_nxt <= S_CACHE_RESYNC_0; + else -- get next word + ctrl.addr_reg_nxt <= std_ulogic_vector(unsigned(ctrl.addr_reg) + 4); + ctrl.state_nxt <= S_BUS_DOWNLOAD_REQ; + end if; + end if; + + when S_CACHE_RESYNC_0 => -- re-sync host/cache access: cache read-latency + -- ------------------------------------------------------------ + ctrl.state_nxt <= S_CACHE_RESYNC_1; + + when S_CACHE_RESYNC_1 => -- re-sync host/cache access: finalize CPU request + -- ------------------------------------------------------------ + host_ack_o <= '1'; + ctrl.state_nxt <= S_IDLE; + + when S_BUS_ERROR => -- bus error during download + -- ------------------------------------------------------------ + host_err_o <= '1'; + ctrl.state_nxt <= S_IDLE; + + when others => -- undefined + -- ------------------------------------------------------------ + ctrl.state_nxt <= S_IDLE; + + end case; + end process ctrl_engine_fsm_comb; + + + -- Cache Memory --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_icache_memory_inst: neorv32_icache_memory + generic map ( + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 + ICACHE_NUM_SETS => ICACHE_NUM_SETS -- associativity; 0=direct-mapped, 1=2-way set-associative + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + invalidate_i => cache.clear, -- invalidate whole cache + -- host cache access (read-only) -- + host_addr_i => cache.host_addr, -- access address + host_re_i => host_re_i, -- read enable + host_rdata_o => cache.host_rdata, -- read data + -- access status (1 cycle delay to access) -- + hit_o => cache.hit, -- hit access + -- ctrl cache access (write-only) -- + ctrl_en_i => cache.ctrl_en, -- control interface enable + ctrl_addr_i => cache.ctrl_addr, -- access address + ctrl_we_i => cache.ctrl_we, -- write enable (full-word) + ctrl_wdata_i => cache.ctrl_wdata, -- write data + ctrl_tag_we_i => cache.ctrl_tag_we, -- write tag to selected block + ctrl_valid_i => cache.ctrl_valid_we, -- make selected block valid + ctrl_invalid_i => cache.ctrl_invalid_we -- make selected block invalid + ); + +end neorv32_icache_rtl; + + +-- ########################################################################################################################################### +-- ########################################################################################################################################### + + +-- ################################################################################################# +-- # << NEORV32 - Cache Memory >> # +-- # ********************************************************************************************* # +-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). # +-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). # +-- # Read-only for host, write-only for control. All output signals have one cycle latency. # +-- # # +-- # Cache sets are mapped to individual memory components - no multi-dimensional memory arrays # +-- # are used as some synthesis tools have problems to map these to actual BRAM primitives. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_icache_memory is + generic ( + ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 + ICACHE_NUM_SETS : natural := 1 -- associativity; 1=direct-mapped, 2=2-way set-associative + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + invalidate_i : in std_ulogic; -- invalidate whole cache + -- host cache access (read-only) -- + host_addr_i : in std_ulogic_vector(31 downto 0); -- access address + host_re_i : in std_ulogic; -- read enable + host_rdata_o : out std_ulogic_vector(31 downto 0); -- read data + -- access status (1 cycle delay to access) -- + hit_o : out std_ulogic; -- hit access + -- ctrl cache access (write-only) -- + ctrl_en_i : in std_ulogic; -- control interface enable + ctrl_addr_i : in std_ulogic_vector(31 downto 0); -- access address + ctrl_we_i : in std_ulogic; -- write enable (full-word) + ctrl_wdata_i : in std_ulogic_vector(31 downto 0); -- write data + ctrl_tag_we_i : in std_ulogic; -- write tag to selected block + ctrl_valid_i : in std_ulogic; -- make selected block valid + ctrl_invalid_i : in std_ulogic -- make selected block invalid + ); +end neorv32_icache_memory; + +architecture neorv32_icache_memory_rtl of neorv32_icache_memory is + + -- cache layout -- + constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words + constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS); + constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset + constant cache_entries_c : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set) + + -- status flag memory -- + signal valid_flag_s0 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0); + signal valid_flag_s1 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0); + signal valid : std_ulogic_vector(1 downto 0); -- valid flag read data + + -- tag memory -- + type tag_mem_t is array (0 to ICACHE_NUM_BLOCKS-1) of std_ulogic_vector(cache_tag_size_c-1 downto 0); + signal tag_mem_s0 : tag_mem_t; + signal tag_mem_s1 : tag_mem_t; + type tag_rd_t is array (0 to 1) of std_ulogic_vector(cache_tag_size_c-1 downto 0); + signal tag : tag_rd_t; -- tag read data + + -- access status -- + signal hit : std_ulogic_vector(1 downto 0); + + -- access address decomposition -- + type acc_addr_t is record + tag : std_ulogic_vector(cache_tag_size_c-1 downto 0); + index : std_ulogic_vector(cache_index_size_c-1 downto 0); + offset : std_ulogic_vector(cache_offset_size_c-1 downto 0); + end record; + signal host_acc_addr, ctrl_acc_addr : acc_addr_t; + + -- cache data memory -- + type cache_mem_t is array (0 to cache_entries_c-1) of std_ulogic_vector(31 downto 0); + signal cache_data_memory_s0 : cache_mem_t; -- set 0 + signal cache_data_memory_s1 : cache_mem_t; -- set 1 + + -- cache data memory access -- + type cache_rdata_t is array (0 to 1) of std_ulogic_vector(31 downto 0); + signal cache_rdata : cache_rdata_t; + signal cache_index : std_ulogic_vector(cache_index_size_c-1 downto 0); + signal cache_offset : std_ulogic_vector(cache_offset_size_c-1 downto 0); + signal cache_addr : std_ulogic_vector((cache_index_size_c+cache_offset_size_c)-1 downto 0); -- index & offset + signal cache_we : std_ulogic; -- write enable (full-word) + signal set_select : std_ulogic; + + -- access history -- + type history_t is record + re_ff : std_ulogic; + last_used_set : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0); + to_be_replaced : std_ulogic; + end record; + signal history : history_t; + +begin + + -- Access Address Decomposition ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + host_acc_addr.tag <= host_addr_i(31 downto 31-(cache_tag_size_c-1)); + host_acc_addr.index <= host_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c); + host_acc_addr.offset <= host_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset + + ctrl_acc_addr.tag <= ctrl_addr_i(31 downto 31-(cache_tag_size_c-1)); + ctrl_acc_addr.index <= ctrl_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c); + ctrl_acc_addr.offset <= ctrl_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset + + + -- Cache Access History ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + access_history: process(clk_i) + begin + if rising_edge(clk_i) then + history.re_ff <= host_re_i; + if (invalidate_i = '1') then -- invalidate whole cache + history.last_used_set <= (others => '1'); + elsif (history.re_ff = '1') and (or_reduce_f(hit) = '1') and (ctrl_en_i = '0') then -- store last accessed set that caused a hit + history.last_used_set(to_integer(unsigned(cache_index))) <= not hit(0); + end if; + history.to_be_replaced <= history.last_used_set(to_integer(unsigned(cache_index))); + end if; + end process access_history; + + -- which set is going to be replaced? -> opposite of last used set = least recently used set -- + set_select <= '0' when (ICACHE_NUM_SETS = 1) else (not history.to_be_replaced); + + + -- Status flag memory --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + status_memory: process(clk_i) + begin + if rising_edge(clk_i) then + -- write access -- + if (invalidate_i = '1') then -- invalidate whole cache + valid_flag_s0 <= (others => '0'); + valid_flag_s1 <= (others => '0'); + elsif (ctrl_en_i = '1') then + if (ctrl_invalid_i = '1') then -- make current block invalid + if (set_select = '0') then + valid_flag_s0(to_integer(unsigned(cache_index))) <= '0'; + else + valid_flag_s1(to_integer(unsigned(cache_index))) <= '0'; + end if; + elsif (ctrl_valid_i = '1') then -- make current block valid + if (set_select = '0') then + valid_flag_s0(to_integer(unsigned(cache_index))) <= '1'; + else + valid_flag_s1(to_integer(unsigned(cache_index))) <= '1'; + end if; + end if; + end if; + -- read access (sync) -- + valid(0) <= valid_flag_s0(to_integer(unsigned(cache_index))); + valid(1) <= valid_flag_s1(to_integer(unsigned(cache_index))); + end if; + end process status_memory; + + + -- Tag memory ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + tag_memory: process(clk_i) + begin + if rising_edge(clk_i) then + if (ctrl_en_i = '1') and (ctrl_tag_we_i = '1') then -- write access + if (set_select = '0') then + tag_mem_s0(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag; + else + tag_mem_s1(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag; + end if; + end if; + tag(0) <= tag_mem_s0(to_integer(unsigned(cache_index))); + tag(1) <= tag_mem_s1(to_integer(unsigned(cache_index))); + end if; + end process tag_memory; + + -- comparator -- + comparator: process(host_acc_addr, tag, valid) + begin + hit <= (others => '0'); + for i in 0 to ICACHE_NUM_SETS-1 loop + if (host_acc_addr.tag = tag(i)) and (valid(i) = '1') then + hit(i) <= '1'; + end if; + end loop; -- i + end process comparator; + + -- global hit -- + hit_o <= or_reduce_f(hit); + + + -- Cache Data Memory ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + cache_mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + if (cache_we = '1') then -- write access from control (full-word) + if (set_select = '0') or (ICACHE_NUM_SETS = 1) then + cache_data_memory_s0(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i; + else + cache_data_memory_s1(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i; + end if; + end if; + -- read access from host (full-word) -- + cache_rdata(0) <= cache_data_memory_s0(to_integer(unsigned(cache_addr))); + cache_rdata(1) <= cache_data_memory_s1(to_integer(unsigned(cache_addr))); + end if; + end process cache_mem_access; + + -- data output -- + host_rdata_o <= cache_rdata(0) when (hit(0) = '1') or (ICACHE_NUM_SETS = 1) else cache_rdata(1); + + -- cache block ram access address -- + cache_addr <= cache_index & cache_offset; + + -- cache access select -- + cache_index <= host_acc_addr.index when (ctrl_en_i = '0') else ctrl_acc_addr.index; + cache_offset <= host_acc_addr.offset when (ctrl_en_i = '0') else ctrl_acc_addr.offset; + cache_we <= '0' when (ctrl_en_i = '0') else ctrl_we_i; + + +end neorv32_icache_memory_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_imem.entity.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_imem.entity.vhd new file mode 100644 index 0000000..533a317 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_imem.entity.vhd @@ -0,0 +1,58 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> # +-- # ********************************************************************************************* # +-- # This memory optionally includes the in-place executable image of the application. See the # +-- # processor's documentary to get more information. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity neorv32_imem is + generic ( + IMEM_BASE : std_ulogic_vector(31 downto 0); -- memory base address + IMEM_SIZE : natural; -- processor-internal instruction memory size in bytes + IMEM_AS_IROM : boolean -- implement IMEM as pre-initialized read-only memory? + ); + port ( + clk_i : in std_ulogic; -- global clock line + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable + addr_i : in std_ulogic_vector(31 downto 0); -- address + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); +end neorv32_imem; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_mtime.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_mtime.vhd new file mode 100644 index 0000000..e503e7f --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_mtime.vhd @@ -0,0 +1,181 @@ +-- ################################################################################################# +-- # << NEORV32 - Machine System Timer (MTIME) >> # +-- # ********************************************************************************************* # +-- # Compatible to RISC-V spec's 64-bit MACHINE system timer including "mtime[h]" & "mtimecmp[h]". # +-- # Note: The 64-bit counter and compare systems are de-coupled into two 32-bit systems. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_mtime is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- time output for CPU -- + time_o : out std_ulogic_vector(63 downto 0); -- current system time + -- interrupt -- + irq_o : out std_ulogic -- interrupt request + ); +end neorv32_mtime; + +architecture neorv32_mtime_rtl of neorv32_mtime is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(mtime_size_c); -- low address boundary bit + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- module access enable + signal rden : std_ulogic; -- read enable + + -- time write access buffer -- + signal mtime_lo_we : std_ulogic; + signal mtime_hi_we : std_ulogic; + + -- accessible regs -- + signal mtimecmp_lo : std_ulogic_vector(31 downto 0); + signal mtimecmp_hi : std_ulogic_vector(31 downto 0); + signal mtime_lo : std_ulogic_vector(31 downto 0); + signal mtime_lo_nxt : std_ulogic_vector(32 downto 0); + signal mtime_lo_ovfl : std_ulogic_vector(00 downto 0); + signal mtime_hi : std_ulogic_vector(31 downto 0); + + -- comparators -- + signal cmp_lo_ge : std_ulogic; + signal cmp_lo_ge_ff : std_ulogic; + signal cmp_hi_eq : std_ulogic; + signal cmp_hi_gt : std_ulogic; + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Write Access --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + wr_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- mtimecmp -- + if (wren = '1') then + if (addr = mtime_cmp_lo_addr_c) then + mtimecmp_lo <= data_i; + end if; + if (addr = mtime_cmp_hi_addr_c) then + mtimecmp_hi <= data_i; + end if; + end if; + + -- mtime access buffer -- +-- wdata_buf <= data_i; -- not required, CPU wdata (=data_i) is stable until transfer is acknowledged + mtime_lo_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_lo_addr_c)); + mtime_hi_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_hi_addr_c)); + + -- mtime low -- + if (mtime_lo_we = '1') then -- write access + mtime_lo <= data_i; + else -- auto increment + mtime_lo <= mtime_lo_nxt(31 downto 0); + end if; + mtime_lo_ovfl(0) <= mtime_lo_nxt(32); -- overflow (carry) + + -- mtime high -- + if (mtime_hi_we = '1') then -- write access + mtime_hi <= data_i; + else -- auto increment (if mtime.low overflows) + mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + unsigned(mtime_lo_ovfl)); + end if; + end if; + end process wr_access; + + -- mtime.time_LO increment -- + mtime_lo_nxt <= std_ulogic_vector(unsigned('0' & mtime_lo) + 1); + + + -- Read Access ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rd_access: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= rden or wren; + data_o <= (others => '0'); -- default + if (rden = '1') then + case addr(3 downto 2) is + when "00" => data_o <= mtime_lo; -- mtime LOW + when "01" => data_o <= mtime_hi; -- mtime HIGH + when "10" => data_o <= mtimecmp_lo; -- mtimecmp LOW + when others => data_o <= mtimecmp_hi; -- mtimecmp HIGH + end case; + end if; + end if; + end process rd_access; + + -- system time output for cpu -- + time_o <= mtime_hi & mtime_lo; -- NOTE: low and high words are not synchronized here! + + + -- Comparator ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + cmp_sync: process(clk_i) + begin + if rising_edge(clk_i) then + cmp_lo_ge_ff <= cmp_lo_ge; -- there is one cycle delay between low (earlier) and high (later) word + irq_o <= cmp_hi_gt or (cmp_hi_eq and cmp_lo_ge_ff); + end if; + end process cmp_sync; + + -- sub-word comparators -- + cmp_lo_ge <= '1' when (unsigned(mtime_lo) >= unsigned(mtimecmp_lo)) else '0'; -- low-word: greater than or equal + cmp_hi_eq <= '1' when (unsigned(mtime_hi) = unsigned(mtimecmp_hi)) else '0'; -- high-word: equal + cmp_hi_gt <= '1' when (unsigned(mtime_hi) > unsigned(mtimecmp_hi)) else '0'; -- high-word: greater than + + +end neorv32_mtime_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_neoled.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_neoled.vhd new file mode 100644 index 0000000..7dbd016 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_neoled.vhd @@ -0,0 +1,420 @@ +-- ################################################################################################# +-- # << NEORV32 - Smart LED (WS2811/WS2812) Interface (NEOLED) >> # +-- # ********************************************************************************************* # +-- # Hardware interface for direct control of "smart LEDs" using an asynchronous serial data # +-- # line. Compatible with the WS2811 and WS2812 LEDs. # +-- # # +-- # NeoPixel-compatible, RGB (24-bit) and RGBW (32-bit) modes supported (in "parallel") # +-- # (TM) "NeoPixel" is a trademark of Adafruit Industries. # +-- # # +-- # The interface uses a programmable carrier frequency (800 KHz for the WS2812 LEDs) # +-- # configurable via the control register's clock prescaler bits (ctrl_clksel*_c) and the period # +-- # length configuration bits (ctrl_t_tot_*_c). "high-times" for sending a ZERO or a ONE bit are # +-- # configured using the ctrl_t_0h_*_c and ctrl_t_1h_*_c bits, respectively. 32-bit transfers # +-- # (for RGBW modules) and 24-bit transfers (for RGB modules) are supported via ctrl_mode__c. # +-- # # +-- # The device features a TX buffer (FIFO) with entries with configurable interrupt. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_neoled is + generic ( + FIFO_DEPTH : natural -- TX FIFO depth (1..32k, power of two) + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- interrupt -- + irq_o : out std_ulogic; -- interrupt request + -- NEOLED output -- + neoled_o : out std_ulogic -- serial async data line + ); +end neorv32_neoled; + +architecture neorv32_neoled_rtl of neorv32_neoled is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(neoled_size_c); -- low address boundary bit + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- Control register bits -- + constant ctrl_en_c : natural := 0; -- r/w: module enable + constant ctrl_mode_c : natural := 1; -- r/w: 0 = 24-bit RGB mode, 1 = 32-bit RGBW mode + constant ctrl_strobe_c : natural := 2; -- r/w: 0 = send normal data, 1 = send LED strobe command (RESET) on data write + -- + constant ctrl_clksel0_c : natural := 3; -- r/w: prescaler select bit 0 + constant ctrl_clksel1_c : natural := 4; -- r/w: prescaler select bit 1 + constant ctrl_clksel2_c : natural := 5; -- r/w: prescaler select bit 2 + -- + constant ctrl_bufs_0_c : natural := 6; -- r/-: log2(FIFO_DEPTH) bit 0 + constant ctrl_bufs_1_c : natural := 7; -- r/-: log2(FIFO_DEPTH) bit 1 + constant ctrl_bufs_2_c : natural := 8; -- r/-: log2(FIFO_DEPTH) bit 2 + constant ctrl_bufs_3_c : natural := 9; -- r/-: log2(FIFO_DEPTH) bit 3 + -- + constant ctrl_t_tot_0_c : natural := 10; -- r/w: pulse-clock ticks per total period bit 0 + constant ctrl_t_tot_1_c : natural := 11; -- r/w: pulse-clock ticks per total period bit 1 + constant ctrl_t_tot_2_c : natural := 12; -- r/w: pulse-clock ticks per total period bit 2 + constant ctrl_t_tot_3_c : natural := 13; -- r/w: pulse-clock ticks per total period bit 3 + constant ctrl_t_tot_4_c : natural := 14; -- r/w: pulse-clock ticks per total period bit 4 + -- + constant ctrl_t_0h_0_c : natural := 15; -- r/w: pulse-clock ticks per ZERO high-time bit 0 + constant ctrl_t_0h_1_c : natural := 16; -- r/w: pulse-clock ticks per ZERO high-time bit 1 + constant ctrl_t_0h_2_c : natural := 17; -- r/w: pulse-clock ticks per ZERO high-time bit 2 + constant ctrl_t_0h_3_c : natural := 18; -- r/w: pulse-clock ticks per ZERO high-time bit 3 + constant ctrl_t_0h_4_c : natural := 19; -- r/w: pulse-clock ticks per ZERO high-time bit 4 + -- + constant ctrl_t_1h_0_c : natural := 20; -- r/w: pulse-clock ticks per ONE high-time bit 0 + constant ctrl_t_1h_1_c : natural := 21; -- r/w: pulse-clock ticks per ONE high-time bit 1 + constant ctrl_t_1h_2_c : natural := 22; -- r/w: pulse-clock ticks per ONE high-time bit 2 + constant ctrl_t_1h_3_c : natural := 23; -- r/w: pulse-clock ticks per ONE high-time bit 3 + constant ctrl_t_1h_4_c : natural := 24; -- r/w: pulse-clock ticks per ONE high-time bit 4 + -- + constant ctrl_irq_conf_c : natural := 27; -- r/w: interrupt config: 1=IRQ when buffer is empty, 0=IRQ when buffer is half-empty + constant ctrl_tx_empty_c : natural := 28; -- r/-: TX FIFO is empty + constant ctrl_tx_half_c : natural := 29; -- r/-: TX FIFO is at least half-full + constant ctrl_tx_full_c : natural := 30; -- r/-: TX FIFO is full + constant ctrl_tx_busy_c : natural := 31; -- r/-: serial TX engine busy when set + + -- control register -- + type ctrl_t is record + enable : std_ulogic; + mode : std_ulogic; + strobe : std_ulogic; + clk_prsc : std_ulogic_vector(2 downto 0); + irq_conf : std_ulogic; + -- pulse config -- + t_total : std_ulogic_vector(4 downto 0); + t0_high : std_ulogic_vector(4 downto 0); + t1_high : std_ulogic_vector(4 downto 0); + end record; + signal ctrl : ctrl_t; + + -- transmission buffer -- + type tx_buffer_t is record + we : std_ulogic; -- write enable + re : std_ulogic; -- read enable + clear : std_ulogic; -- sync reset, high-active + wdata : std_ulogic_vector(31+2 downto 0); -- write data (excluding mode) + rdata : std_ulogic_vector(31+2 downto 0); -- read data (including mode) + avail : std_ulogic; -- data available? + free : std_ulogic; -- free entry available? + half : std_ulogic; -- half full + end record; + signal tx_buffer : tx_buffer_t; + + -- interrupt generator -- + type irq_t is record + set : std_ulogic; + buf : std_ulogic_vector(1 downto 0); + end record; + signal irq : irq_t; + + -- serial transmission engine -- + type serial_state_t is (S_IDLE, S_INIT, S_GETBIT, S_PULSE, S_STROBE); + type serial_t is record + -- state control -- + state : serial_state_t; + mode : std_ulogic; + done : std_ulogic; + busy : std_ulogic; + bit_cnt : std_ulogic_vector(5 downto 0); + -- shift register -- + sreg : std_ulogic_vector(31 downto 0); + next_bit : std_ulogic; -- next bit to send + -- pulse generator -- + pulse_clk : std_ulogic; -- pulse cycle "clock" + pulse_cnt : std_ulogic_vector(4 downto 0); + t_high : std_ulogic_vector(4 downto 0); + strobe_cnt : std_ulogic_vector(6 downto 0); + tx_out : std_ulogic; + end record; + signal serial : serial_t; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not ((is_power_of_two_f(FIFO_DEPTH) = false) or (FIFO_DEPTH < 1) or (FIFO_DEPTH > 32768)) report + "NEORV32 PROCESSOR CONFIG ERROR! Invalid buffer size configuration (1..32k)!" severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = neoled_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= neoled_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- access acknowledge -- + ack_o <= wren or rden; + + -- write access: control register -- + if (wren = '1') and (addr = neoled_ctrl_addr_c) then + ctrl.enable <= data_i(ctrl_en_c); + ctrl.mode <= data_i(ctrl_mode_c); + ctrl.strobe <= data_i(ctrl_strobe_c); + ctrl.clk_prsc <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c); + ctrl.irq_conf <= data_i(ctrl_irq_conf_c); + ctrl.t_total <= data_i(ctrl_t_tot_4_c downto ctrl_t_tot_0_c); + ctrl.t0_high <= data_i(ctrl_t_0h_4_c downto ctrl_t_0h_0_c); + ctrl.t1_high <= data_i(ctrl_t_1h_4_c downto ctrl_t_1h_0_c); + end if; + + -- read access: control register -- + data_o <= (others => '0'); + if (rden = '1') then -- and (addr = neoled_ctrl_addr_c) then + data_o(ctrl_en_c) <= ctrl.enable; + data_o(ctrl_mode_c) <= ctrl.mode; + data_o(ctrl_strobe_c) <= ctrl.strobe; + data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_prsc; + data_o(ctrl_irq_conf_c) <= ctrl.irq_conf or bool_to_ulogic_f(boolean(FIFO_DEPTH = 1)); -- tie to one if FIFO_DEPTH is 1 + data_o(ctrl_bufs_3_c downto ctrl_bufs_0_c) <= std_ulogic_vector(to_unsigned(index_size_f(FIFO_DEPTH), 4)); + data_o(ctrl_t_tot_4_c downto ctrl_t_tot_0_c) <= ctrl.t_total; + data_o(ctrl_t_0h_4_c downto ctrl_t_0h_0_c) <= ctrl.t0_high; + data_o(ctrl_t_1h_4_c downto ctrl_t_1h_0_c) <= ctrl.t1_high; + -- + data_o(ctrl_tx_empty_c) <= not tx_buffer.avail; + data_o(ctrl_tx_half_c) <= tx_buffer.half; + data_o(ctrl_tx_full_c) <= not tx_buffer.free; + data_o(ctrl_tx_busy_c) <= serial.busy; + end if; + end if; + end process rw_access; + + -- enable external clock generator -- + clkgen_en_o <= ctrl.enable; + + -- FIFO write access -- + tx_buffer.we <= '1' when (wren = '1') and (addr = neoled_data_addr_c) else '0'; + tx_buffer.wdata <= ctrl.strobe & ctrl.mode & data_i; + tx_buffer.clear <= not ctrl.enable; + + + -- IRQ Generator -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + irq_select: process(ctrl, tx_buffer, serial.done) + begin + if (FIFO_DEPTH = 1) or (ctrl.irq_conf = '1') then + irq.set <= tx_buffer.free and serial.done; -- fire IRQ if FIFO is empty + else + irq.set <= not tx_buffer.half; -- fire IRQ if FIFO is less than half-full + end if; + end process irq_select; + + -- Interrupt Edge Detector -- + irq_detect: process(clk_i) + begin + if rising_edge(clk_i) then + if (ctrl.enable = '0') then + irq.buf <= "00"; + else + irq.buf <= irq.buf(0) & irq.set; + end if; + end if; + end process irq_detect; + + -- IRQ request to CPU -- + irq_o <= '1' when (irq.buf = "01") else '0'; + + + -- TX Buffer (FIFO) ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + tx_data_fifo: neorv32_fifo + generic map ( + FIFO_DEPTH => FIFO_DEPTH, -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH => 32+2, -- size of data elements in fifo + FIFO_RSYNC => true, -- sync read + FIFO_SAFE => true -- safe access + ) + port map ( + -- control -- + clk_i => clk_i, -- clock, rising edge + rstn_i => '1', -- async reset, low-active + clear_i => tx_buffer.clear, -- sync reset, high-active + level_o => open, -- fill level + half_o => tx_buffer.half, -- FIFO is at least half full + -- write port -- + wdata_i => tx_buffer.wdata, -- write data + we_i => tx_buffer.we, -- write enable + free_o => tx_buffer.free, -- at least one entry is free when set + -- read port -- + re_i => tx_buffer.re, -- read enable + rdata_o => tx_buffer.rdata, -- read data + avail_o => tx_buffer.avail -- data available when set + ); + + -- try to get new TX data -- + tx_buffer.re <= '1' when (serial.state = S_IDLE) else '0'; + + + -- Serial TX Engine ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + serial_engine: process(clk_i) + begin + if rising_edge(clk_i) then + -- clock generator -- + serial.pulse_clk <= clkgen_i(to_integer(unsigned(ctrl.clk_prsc))); + + -- defaults -- + serial.done <= '0'; + + -- FSM -- + if (ctrl.enable = '0') then -- disabled + serial.state <= S_IDLE; + else + case serial.state is + + when S_IDLE => -- waiting for new TX data + -- ------------------------------------------------------------ + serial.tx_out <= '0'; + serial.pulse_cnt <= (others => '0'); + serial.strobe_cnt <= (others => '0'); + if (tx_buffer.avail = '1') then + serial.state <= S_INIT; + end if; + + when S_INIT => -- initialize TX shift engine + -- ------------------------------------------------------------ + if (tx_buffer.rdata(33) = '0') then -- send data + if (tx_buffer.rdata(32) = '0') then -- mode = "RGB" + serial.mode <= '0'; + serial.bit_cnt <= "011000"; -- total number of bits to send: 3x8=24 + else -- mode = "RGBW" + serial.mode <= '1'; + serial.bit_cnt <= "100000"; -- total number of bits to send: 4x8=32 + end if; + serial.sreg <= tx_buffer.rdata(31 downto 00); + serial.state <= S_GETBIT; + else -- send RESET command + serial.state <= S_STROBE; + end if; + + when S_GETBIT => -- get next TX bit + -- ------------------------------------------------------------ + serial.sreg <= serial.sreg(serial.sreg'left-1 downto 0) & '0'; -- shift left by one position (MSB-first) + serial.bit_cnt <= std_ulogic_vector(unsigned(serial.bit_cnt) - 1); + serial.pulse_cnt <= (others => '0'); + if (serial.next_bit = '0') then -- send zero-bit + serial.t_high <= ctrl.t0_high; + else -- send one-bit + serial.t_high <= ctrl.t1_high; + end if; + if (serial.bit_cnt = "000000") then -- all done? + serial.tx_out <= '0'; + serial.done <= '1'; -- done sending data + serial.state <= S_IDLE; + else -- send current data MSB + serial.tx_out <= '1'; + serial.state <= S_PULSE; -- transmit single pulse + end if; + + when S_PULSE => -- send pulse with specific duty cycle + -- ------------------------------------------------------------ + -- total pulse length = ctrl.t_total + -- pulse high time = serial.t_high + if (serial.pulse_clk = '1') then + serial.pulse_cnt <= std_ulogic_vector(unsigned(serial.pulse_cnt) + 1); + -- T_high reached? -- + if (serial.pulse_cnt = serial.t_high) then + serial.tx_out <= '0'; + end if; + -- T_total reached? -- + if (serial.pulse_cnt = ctrl.t_total) then + serial.state <= S_GETBIT; -- get next bit to send + end if; + end if; + + when S_STROBE => -- strobe LED data ("RESET" command) + -- ------------------------------------------------------------ + -- wait for 127 * ctrl.t_total to _ensure_ RESET + if (serial.pulse_clk = '1') then + -- T_total reached? -- + if (serial.pulse_cnt = ctrl.t_total) then + serial.pulse_cnt <= (others => '0'); + serial.strobe_cnt <= std_ulogic_vector(unsigned(serial.strobe_cnt) + 1); + else + serial.pulse_cnt <= std_ulogic_vector(unsigned(serial.pulse_cnt) + 1); + end if; + end if; + -- number of LOW periods reached for RESET? -- + if (and_reduce_f(serial.strobe_cnt) = '1') then + serial.done <= '1'; -- done sending RESET + serial.state <= S_IDLE; + end if; + + when others => -- undefined + -- ------------------------------------------------------------ + serial.state <= S_IDLE; + + end case; + end if; + -- serial data tx_out -- + neoled_o <= serial.tx_out and ctrl.enable; + end if; + end process serial_engine; + + -- SREG's TX data: bit 23 for RGB mode (24-bit), bit 31 for RGBW mode (32-bit) -- + serial.next_bit <= serial.sreg(23) when (serial.mode = '0') else serial.sreg(31); + + -- TX engine status -- + serial.busy <= '0' when (serial.state = S_IDLE) else '1'; + + +end neorv32_neoled_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_package.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_package.vhd new file mode 100644 index 0000000..176d099 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_package.vhd @@ -0,0 +1,2426 @@ +-- ################################################################################################# +-- # << NEORV32 - Main VHDL package file >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package neorv32_package is + + -- Architecture Configuration ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- address space -- + constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address + constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address + + -- CPU core -- + constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value) + constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false + + -- "critical" number of implemented PMP regions -- + -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces + -- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length + constant pmp_num_regions_critical_c : natural := 8; -- default=8 + + -- "response time window" for processor-internal modules -- + constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2) + + -- jtag tap - identifier -- + constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version + constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number + constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id + + -- Architecture Constants (do not modify!) ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + constant data_width_c : natural := 32; -- native data path width - do not change! + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060409"; -- no touchy! + constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! + + -- Check if we're inside the Matrix ------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant is_simulation_c : boolean := false -- seems like we're on real hardware +-- pragma translate_off +-- synthesis translate_off +-- synthesis synthesis_off +-- RTL_SYNTHESIS OFF + or true -- this MIGHT be a simulation +-- RTL_SYNTHESIS ON +-- synthesis synthesis_on +-- synthesis translate_on +-- pragma translate_on + ; + + -- External Interface Types --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0); + type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type + + -- Internal Interface Types --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0); + type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0); + type cp_data_if_t is array (0 to 3) of std_ulogic_vector(data_width_c-1 downto 0); + + -- Internal Memory Types Configuration Types ---------------------------------------------- + -- ------------------------------------------------------------------------------------------- + type mem32_t is array (natural range <>) of std_ulogic_vector(31 downto 0); -- memory with 32-bit entries + type mem8_t is array (natural range <>) of std_ulogic_vector(07 downto 0); -- memory with 8-bit entries + + -- Helper Functions ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function index_size_f(input : natural) return natural; + function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural; + function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer; + function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector; + function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic; + function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string; + function bool_to_ulogic_f(cond : boolean) return std_ulogic; + function or_reduce_f(a : std_ulogic_vector) return std_ulogic; + function and_reduce_f(a : std_ulogic_vector) return std_ulogic; + function xor_reduce_f(a : std_ulogic_vector) return std_ulogic; + function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character; + function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector; + function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector; + function is_power_of_two_f(input : natural) return boolean; + function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector; + function char_to_lower_f(ch : character) return character; + function str_equal_f(str0 : string; str1 : string) return boolean; + function popcount_f(input : std_ulogic_vector) return natural; + function leading_zeros_f(input : std_ulogic_vector) return natural; + impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t; + + -- Internal (auto-generated) Configurations ----------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-'); + + -- Processor-Internal Address Space Layout ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) -- + constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address + constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address + --> internal data/instruction memory sizes are configured via top's generics + + -- !!! IMPORTANT: The base address of each component/module has to be aligned to the !!! + -- !!! total size of the module's occupied address space. The occupied address space !!! + -- !!! has to be a power of two (minimum 4 bytes). Address spaces must not overlap. !!! + + -- Internal Bootloader ROM -- + -- Actual bootloader size is determined during runtime via the length of the bootloader initialization image + constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed! + constant boot_rom_max_size_c : natural := 32*1024; -- max module's address space size in bytes, fixed! + + -- On-Chip Debugger: Debug Module -- + constant dm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800"; -- base address, fixed! + constant dm_size_c : natural := 4*32*4; -- debug ROM address space size in bytes, fixed + constant dm_code_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800"; + constant dm_pbuf_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff880"; + constant dm_data_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff900"; + constant dm_sreg_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980"; + + -- IO: Peripheral Devices ("IO") Area -- + -- Control register(s) (including the device-enable) should be located at the base address of each device + constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; + constant io_size_c : natural := 512; -- IO address space size in bytes, fixed! + + -- Custom Functions Subsystem (CFS) -- + constant cfs_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; -- base address + constant cfs_size_c : natural := 32*4; -- module's address space in bytes + constant cfs_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe00"; + constant cfs_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe04"; + constant cfs_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe08"; + constant cfs_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe0c"; + constant cfs_reg4_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe10"; + constant cfs_reg5_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe14"; + constant cfs_reg6_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe18"; + constant cfs_reg7_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe1c"; + constant cfs_reg8_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe20"; + constant cfs_reg9_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe24"; + constant cfs_reg10_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe28"; + constant cfs_reg11_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe2c"; + constant cfs_reg12_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe30"; + constant cfs_reg13_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe34"; + constant cfs_reg14_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe38"; + constant cfs_reg15_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe3c"; + constant cfs_reg16_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe40"; + constant cfs_reg17_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe44"; + constant cfs_reg18_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe48"; + constant cfs_reg19_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe4c"; + constant cfs_reg20_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe50"; + constant cfs_reg21_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe54"; + constant cfs_reg22_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe58"; + constant cfs_reg23_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe5c"; + constant cfs_reg24_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe60"; + constant cfs_reg25_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe64"; + constant cfs_reg26_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe68"; + constant cfs_reg27_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe6c"; + constant cfs_reg28_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe70"; + constant cfs_reg29_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe74"; + constant cfs_reg30_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe78"; + constant cfs_reg31_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe7c"; + + -- Pulse-Width Modulation Controller (PWM) -- + constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80"; -- base address + constant pwm_size_c : natural := 16*4; -- module's address space size in bytes + constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe80"; + constant pwm_duty0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe84"; + constant pwm_duty1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe88"; + constant pwm_duty2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe8c"; + constant pwm_duty3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe90"; + constant pwm_duty4_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe94"; + constant pwm_duty5_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe98"; + constant pwm_duty6_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffe9c"; + constant pwm_duty7_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffea0"; + constant pwm_duty8_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffea4"; + constant pwm_duty9_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffea8"; + constant pwm_duty10_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeac"; + constant pwm_duty11_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb0"; + constant pwm_duty12_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb4"; + constant pwm_duty13_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeb8"; + constant pwm_duty14_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffebc"; + + -- Stream Link Interface (SLINK) -- + constant slink_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffec0"; -- base address + constant slink_size_c : natural := 16*4; -- module's address space size in bytes + + -- reserved -- +--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address +--constant reserved_size_c : natural := 16*4; -- module's address space size in bytes + + -- reserved -- +--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40"; -- base address +--constant reserved_size_c : natural := 8*4; -- module's address space size in bytes + + -- General Purpose Timer (GPTMR) -- + constant gptmr_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60"; -- base address + constant gptmr_size_c : natural := 4*4; -- module's address space size in bytes + constant gptmr_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60"; + constant gptmr_thres_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff64"; + constant gptmr_count_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff68"; +--constant gptmr_reserve_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff6c"; + + -- reserved -- +--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff70"; -- base address +--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes + + -- reserved -- +--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff78"; -- base address +--constant reserved_size_c : natural := 1*4; -- module's address space size in bytes + + -- Bus Access Monitor (BUSKEEPER) -- + constant buskeeper_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff7c"; -- base address + constant buskeeper_size_c : natural := 1*4; -- module's address space size in bytes + + -- External Interrupt Controller (XIRQ) -- + constant xirq_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address + constant xirq_size_c : natural := 4*4; -- module's address space size in bytes + constant xirq_enable_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; + constant xirq_pending_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84"; + constant xirq_source_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88"; +--constant xirq_reserved_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c"; + + -- Machine System Timer (MTIME) -- + constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address + constant mtime_size_c : natural := 4*4; -- module's address space size in bytes + constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; + constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94"; + constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98"; + constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c"; + + -- Primary Universal Asynchronous Receiver/Transmitter (UART0) -- + constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address + constant uart0_size_c : natural := 2*4; -- module's address space size in bytes + constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; + constant uart0_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4"; + + -- Serial Peripheral Interface (SPI) -- + constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8"; -- base address + constant spi_size_c : natural := 2*4; -- module's address space size in bytes + constant spi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8"; + constant spi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffac"; + + -- Two Wire Interface (TWI) -- + constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0"; -- base address + constant twi_size_c : natural := 2*4; -- module's address space size in bytes + constant twi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0"; + constant twi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb4"; + + -- True Random Number Generator (TRNG) -- + constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address + constant trng_size_c : natural := 1*4; -- module's address space size in bytes + constant trng_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; + + -- Watch Dog Timer (WDT) -- + constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc"; -- base address + constant wdt_size_c : natural := 1*4; -- module's address space size in bytes + constant wdt_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc"; + + -- General Purpose Input/Output Controller (GPIO) -- + constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address + constant gpio_size_c : natural := 4*4; -- module's address space size in bytes + constant gpio_in_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; + constant gpio_in_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4"; + constant gpio_out_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8"; + constant gpio_out_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc"; + + -- Secondary Universal Asynchronous Receiver/Transmitter (UART1) -- + constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address + constant uart1_size_c : natural := 2*4; -- module's address space size in bytes + constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; + constant uart1_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4"; + + -- Smart LED (WS2811/WS2812) Interface (NEOLED) -- + constant neoled_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8"; -- base address + constant neoled_size_c : natural := 2*4; -- module's address space size in bytes + constant neoled_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8"; + constant neoled_data_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffdc"; + + -- System Information Memory (SYSINFO) -- + constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address + constant sysinfo_size_c : natural := 8*4; -- module's address space size in bytes + + -- Main CPU Control Bus ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- register file -- + constant ctrl_rf_in_mux_c : natural := 0; -- input source select lsb (0=MEM, 1=ALU) + constant ctrl_rf_rs1_adr0_c : natural := 1; -- source register 1 address bit 0 + constant ctrl_rf_rs1_adr1_c : natural := 2; -- source register 1 address bit 1 + constant ctrl_rf_rs1_adr2_c : natural := 3; -- source register 1 address bit 2 + constant ctrl_rf_rs1_adr3_c : natural := 4; -- source register 1 address bit 3 + constant ctrl_rf_rs1_adr4_c : natural := 5; -- source register 1 address bit 4 + constant ctrl_rf_rs2_adr0_c : natural := 6; -- source register 2 address bit 0 + constant ctrl_rf_rs2_adr1_c : natural := 7; -- source register 2 address bit 1 + constant ctrl_rf_rs2_adr2_c : natural := 8; -- source register 2 address bit 2 + constant ctrl_rf_rs2_adr3_c : natural := 9; -- source register 2 address bit 3 + constant ctrl_rf_rs2_adr4_c : natural := 10; -- source register 2 address bit 4 + constant ctrl_rf_rd_adr0_c : natural := 11; -- destination register address bit 0 + constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1 + constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2 + constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3 + constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4 + constant ctrl_rf_wb_en_c : natural := 16; -- write back enable + -- alu -- + constant ctrl_alu_op0_c : natural := 17; -- ALU operation select bit 0 + constant ctrl_alu_op1_c : natural := 18; -- ALU operation select bit 1 + constant ctrl_alu_op2_c : natural := 19; -- ALU operation select bit 2 + constant ctrl_alu_func0_c : natural := 20; -- ALU function select command bit 0 + constant ctrl_alu_func1_c : natural := 21; -- ALU function select command bit 1 + constant ctrl_alu_opa_mux_c : natural := 22; -- operand A select (0=rs1, 1=PC) + constant ctrl_alu_opb_mux_c : natural := 23; -- operand B select (0=rs2, 1=IMM) + constant ctrl_alu_unsigned_c : natural := 24; -- is unsigned ALU operation + constant ctrl_alu_shift_dir_c : natural := 25; -- shift direction (0=left, 1=right) + constant ctrl_alu_shift_ar_c : natural := 26; -- is arithmetic shift + constant ctrl_alu_frm0_c : natural := 27; -- FPU rounding mode bit 0 + constant ctrl_alu_frm1_c : natural := 28; -- FPU rounding mode bit 1 + constant ctrl_alu_frm2_c : natural := 29; -- FPU rounding mode bit 2 + -- bus interface -- + constant ctrl_bus_size_lsb_c : natural := 30; -- transfer size lsb (00=byte, 01=half-word) + constant ctrl_bus_size_msb_c : natural := 31; -- transfer size msb (10=word, 11=?) + constant ctrl_bus_rd_c : natural := 32; -- read data request + constant ctrl_bus_wr_c : natural := 33; -- write data request + constant ctrl_bus_if_c : natural := 34; -- instruction fetch request + constant ctrl_bus_mo_we_c : natural := 35; -- memory address and data output register write enable + constant ctrl_bus_mi_we_c : natural := 36; -- memory data input register write enable + constant ctrl_bus_unsigned_c : natural := 37; -- is unsigned load + constant ctrl_bus_ierr_ack_c : natural := 38; -- acknowledge instruction fetch bus exceptions + constant ctrl_bus_derr_ack_c : natural := 39; -- acknowledge data access bus exceptions + constant ctrl_bus_fence_c : natural := 40; -- executed fence operation + constant ctrl_bus_fencei_c : natural := 41; -- executed fencei operation + constant ctrl_bus_lock_c : natural := 42; -- make atomic/exclusive access lock + constant ctrl_bus_de_lock_c : natural := 43; -- remove atomic/exclusive access + constant ctrl_bus_ch_lock_c : natural := 44; -- evaluate atomic/exclusive lock (SC operation) + -- co-processors -- + constant ctrl_cp_id_lsb_c : natural := 45; -- cp select ID lsb + constant ctrl_cp_id_msb_c : natural := 46; -- cp select ID msb + -- instruction's control blocks (used by cpu co-processors) -- + constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0 + constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1 + constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2 + constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0 + constant ctrl_ir_funct12_1_c : natural := 51; -- funct12 bit 1 + constant ctrl_ir_funct12_2_c : natural := 52; -- funct12 bit 2 + constant ctrl_ir_funct12_3_c : natural := 53; -- funct12 bit 3 + constant ctrl_ir_funct12_4_c : natural := 54; -- funct12 bit 4 + constant ctrl_ir_funct12_5_c : natural := 55; -- funct12 bit 5 + constant ctrl_ir_funct12_6_c : natural := 56; -- funct12 bit 6 + constant ctrl_ir_funct12_7_c : natural := 57; -- funct12 bit 7 + constant ctrl_ir_funct12_8_c : natural := 58; -- funct12 bit 8 + constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9 + constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10 + constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11 + constant ctrl_ir_opcode7_0_c : natural := 62; -- opcode7 bit 0 + constant ctrl_ir_opcode7_1_c : natural := 63; -- opcode7 bit 1 + constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2 + constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3 + constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4 + constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5 + constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6 + -- CPU status -- + constant ctrl_priv_lvl_lsb_c : natural := 69; -- privilege level lsb + constant ctrl_priv_lvl_msb_c : natural := 70; -- privilege level msb + constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode + constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution + constant ctrl_debug_running_c : natural := 73; -- CPU is in debug mode when set + -- control bus size -- + constant ctrl_width_c : natural := 74; -- control bus size + + -- Comparator Bus ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant cmp_equal_c : natural := 0; + constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons + + -- RISC-V Opcode Layout ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0 + constant instr_opcode_msb_c : natural := 6; -- opcode bit 6 + constant instr_rd_lsb_c : natural := 7; -- destination register address bit 0 + constant instr_rd_msb_c : natural := 11; -- destination register address bit 4 + constant instr_funct3_lsb_c : natural := 12; -- funct3 bit 0 + constant instr_funct3_msb_c : natural := 14; -- funct3 bit 2 + constant instr_rs1_lsb_c : natural := 15; -- source register 1 address bit 0 + constant instr_rs1_msb_c : natural := 19; -- source register 1 address bit 4 + constant instr_rs2_lsb_c : natural := 20; -- source register 2 address bit 0 + constant instr_rs2_msb_c : natural := 24; -- source register 2 address bit 4 + constant instr_funct7_lsb_c : natural := 25; -- funct7 bit 0 + constant instr_funct7_msb_c : natural := 31; -- funct7 bit 6 + constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0 + constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11 + constant instr_imm12_lsb_c : natural := 20; -- immediate12 bit 0 + constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11 + constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0 + constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21 + constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0 + constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11 + constant instr_funct5_lsb_c : natural := 27; -- funct5 select bit 0 + constant instr_funct5_msb_c : natural := 31; -- funct5 select bit 4 + + -- RISC-V Opcodes ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- alu -- + constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate + constant opcode_auipc_c : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC + constant opcode_alui_c : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7) + constant opcode_alu_c : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7) + -- control flow -- + constant opcode_jal_c : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link + constant opcode_jalr_c : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register + constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3) + -- memory access -- + constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3) + constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3) + -- system/csr -- + constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i + constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3) + -- atomic memory access (A) -- + constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension) + -- floating point operations (Zfinx-only) (F/D/H/Q) -- + constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction + + -- RISC-V Funct3 -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- control flow -- + constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal + constant funct3_bne_c : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal + constant funct3_blt_c : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than + constant funct3_bge_c : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal + constant funct3_bltu_c : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned) + constant funct3_bgeu_c : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned) + -- memory access -- + constant funct3_lb_c : std_ulogic_vector(2 downto 0) := "000"; -- load byte + constant funct3_lh_c : std_ulogic_vector(2 downto 0) := "001"; -- load half word + constant funct3_lw_c : std_ulogic_vector(2 downto 0) := "010"; -- load word + constant funct3_lbu_c : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned) + constant funct3_lhu_c : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned) + constant funct3_sb_c : std_ulogic_vector(2 downto 0) := "000"; -- store byte + constant funct3_sh_c : std_ulogic_vector(2 downto 0) := "001"; -- store half word + constant funct3_sw_c : std_ulogic_vector(2 downto 0) := "010"; -- store word + -- alu -- + constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7 + constant funct3_sll_c : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left + constant funct3_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- set on less + constant funct3_sltu_c : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned + constant funct3_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- xor + constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7 + constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or + constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and + -- system/csr -- + constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi, ... + constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w + constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit + constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit + constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate + constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate + constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate + -- fence -- + constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP) + constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instruction stream sync + + -- RISC-V Funct12 ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- system -- + constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL + constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK + constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET + constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI + constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- DRET + + -- RISC-V Funct5 -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- atomic operations -- + constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR + constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC + + -- RISC-V Floating-Point Stuff ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + -- formats -- + constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit) + constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit) + constant float_half_c : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit) + constant float_quad_c : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit) + + -- number class flags -- + constant fp_class_neg_inf_c : natural := 0; -- negative infinity + constant fp_class_neg_norm_c : natural := 1; -- negative normal number + constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number + constant fp_class_neg_zero_c : natural := 3; -- negative zero + constant fp_class_pos_zero_c : natural := 4; -- positive zero + constant fp_class_pos_denorm_c : natural := 5; -- positive subnormal number + constant fp_class_pos_norm_c : natural := 6; -- positive normal number + constant fp_class_pos_inf_c : natural := 7; -- positive infinity + constant fp_class_snan_c : natural := 8; -- signaling NaN (sNaN) + constant fp_class_qnan_c : natural := 9; -- quiet NaN (qNaN) + + -- exception flags -- + constant fp_exc_nv_c : natural := 0; -- invalid operation + constant fp_exc_dz_c : natural := 1; -- divide by zero + constant fp_exc_of_c : natural := 2; -- overflow + constant fp_exc_uf_c : natural := 3; -- underflow + constant fp_exc_nx_c : natural := 4; -- inexact + + -- special values (single-precision) -- + constant fp_single_qnan_c : std_ulogic_vector(31 downto 0) := x"7fc00000"; -- quiet NaN + constant fp_single_snan_c : std_ulogic_vector(31 downto 0) := x"7fa00000"; -- signaling NaN + constant fp_single_pos_inf_c : std_ulogic_vector(31 downto 0) := x"7f800000"; -- positive infinity + constant fp_single_neg_inf_c : std_ulogic_vector(31 downto 0) := x"ff800000"; -- negative infinity + constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero + constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero + + -- RISC-V CSR Addresses ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- <<< standard read/write CSRs >>> -- + -- user floating-point CSRs -- + constant csr_class_float_c : std_ulogic_vector(09 downto 0) := x"00" & "00"; -- floating point + constant csr_fflags_c : std_ulogic_vector(11 downto 0) := x"001"; + constant csr_frm_c : std_ulogic_vector(11 downto 0) := x"002"; + constant csr_fcsr_c : std_ulogic_vector(11 downto 0) := x"003"; + -- machine trap setup -- + constant csr_class_setup_c : std_ulogic_vector(08 downto 0) := x"30" & '0'; -- trap setup + constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; + constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; + constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; + constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; + constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306"; + -- + constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310"; + -- machine configuration -- + constant csr_class_envcfg_c : std_ulogic_vector(06 downto 0) := x"3" & "000"; -- configuration + constant csr_menvcfg_c : std_ulogic_vector(11 downto 0) := x"30a"; + constant csr_menvcfgh_c : std_ulogic_vector(11 downto 0) := x"31a"; + -- machine counter setup -- + constant csr_cnt_setup_c : std_ulogic_vector(06 downto 0) := x"3" & "001"; -- counter setup + constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320"; + constant csr_mhpmevent3_c : std_ulogic_vector(11 downto 0) := x"323"; + constant csr_mhpmevent4_c : std_ulogic_vector(11 downto 0) := x"324"; + constant csr_mhpmevent5_c : std_ulogic_vector(11 downto 0) := x"325"; + constant csr_mhpmevent6_c : std_ulogic_vector(11 downto 0) := x"326"; + constant csr_mhpmevent7_c : std_ulogic_vector(11 downto 0) := x"327"; + constant csr_mhpmevent8_c : std_ulogic_vector(11 downto 0) := x"328"; + constant csr_mhpmevent9_c : std_ulogic_vector(11 downto 0) := x"329"; + constant csr_mhpmevent10_c : std_ulogic_vector(11 downto 0) := x"32a"; + constant csr_mhpmevent11_c : std_ulogic_vector(11 downto 0) := x"32b"; + constant csr_mhpmevent12_c : std_ulogic_vector(11 downto 0) := x"32c"; + constant csr_mhpmevent13_c : std_ulogic_vector(11 downto 0) := x"32d"; + constant csr_mhpmevent14_c : std_ulogic_vector(11 downto 0) := x"32e"; + constant csr_mhpmevent15_c : std_ulogic_vector(11 downto 0) := x"32f"; + constant csr_mhpmevent16_c : std_ulogic_vector(11 downto 0) := x"330"; + constant csr_mhpmevent17_c : std_ulogic_vector(11 downto 0) := x"331"; + constant csr_mhpmevent18_c : std_ulogic_vector(11 downto 0) := x"332"; + constant csr_mhpmevent19_c : std_ulogic_vector(11 downto 0) := x"333"; + constant csr_mhpmevent20_c : std_ulogic_vector(11 downto 0) := x"334"; + constant csr_mhpmevent21_c : std_ulogic_vector(11 downto 0) := x"335"; + constant csr_mhpmevent22_c : std_ulogic_vector(11 downto 0) := x"336"; + constant csr_mhpmevent23_c : std_ulogic_vector(11 downto 0) := x"337"; + constant csr_mhpmevent24_c : std_ulogic_vector(11 downto 0) := x"338"; + constant csr_mhpmevent25_c : std_ulogic_vector(11 downto 0) := x"339"; + constant csr_mhpmevent26_c : std_ulogic_vector(11 downto 0) := x"33a"; + constant csr_mhpmevent27_c : std_ulogic_vector(11 downto 0) := x"33b"; + constant csr_mhpmevent28_c : std_ulogic_vector(11 downto 0) := x"33c"; + constant csr_mhpmevent29_c : std_ulogic_vector(11 downto 0) := x"33d"; + constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := x"33e"; + constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := x"33f"; + -- machine trap handling -- + constant csr_class_trap_c : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling + constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; + constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; + constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; + constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; + constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; + -- physical memory protection - configuration -- + constant csr_class_pmpcfg_c : std_ulogic_vector(07 downto 0) := x"3a"; -- pmp configuration + constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0"; + constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1"; + constant csr_pmpcfg2_c : std_ulogic_vector(11 downto 0) := x"3a2"; + constant csr_pmpcfg3_c : std_ulogic_vector(11 downto 0) := x"3a3"; + constant csr_pmpcfg4_c : std_ulogic_vector(11 downto 0) := x"3a4"; + constant csr_pmpcfg5_c : std_ulogic_vector(11 downto 0) := x"3a5"; + constant csr_pmpcfg6_c : std_ulogic_vector(11 downto 0) := x"3a6"; + constant csr_pmpcfg7_c : std_ulogic_vector(11 downto 0) := x"3a7"; + constant csr_pmpcfg8_c : std_ulogic_vector(11 downto 0) := x"3a8"; + constant csr_pmpcfg9_c : std_ulogic_vector(11 downto 0) := x"3a9"; + constant csr_pmpcfg10_c : std_ulogic_vector(11 downto 0) := x"3aa"; + constant csr_pmpcfg11_c : std_ulogic_vector(11 downto 0) := x"3ab"; + constant csr_pmpcfg12_c : std_ulogic_vector(11 downto 0) := x"3ac"; + constant csr_pmpcfg13_c : std_ulogic_vector(11 downto 0) := x"3ad"; + constant csr_pmpcfg14_c : std_ulogic_vector(11 downto 0) := x"3ae"; + constant csr_pmpcfg15_c : std_ulogic_vector(11 downto 0) := x"3af"; + -- physical memory protection - address -- + constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0"; + constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1"; + constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2"; + constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3"; + constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4"; + constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := x"3b5"; + constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := x"3b6"; + constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := x"3b7"; + constant csr_pmpaddr8_c : std_ulogic_vector(11 downto 0) := x"3b8"; + constant csr_pmpaddr9_c : std_ulogic_vector(11 downto 0) := x"3b9"; + constant csr_pmpaddr10_c : std_ulogic_vector(11 downto 0) := x"3ba"; + constant csr_pmpaddr11_c : std_ulogic_vector(11 downto 0) := x"3bb"; + constant csr_pmpaddr12_c : std_ulogic_vector(11 downto 0) := x"3bc"; + constant csr_pmpaddr13_c : std_ulogic_vector(11 downto 0) := x"3bd"; + constant csr_pmpaddr14_c : std_ulogic_vector(11 downto 0) := x"3be"; + constant csr_pmpaddr15_c : std_ulogic_vector(11 downto 0) := x"3bf"; + constant csr_pmpaddr16_c : std_ulogic_vector(11 downto 0) := x"3c0"; + constant csr_pmpaddr17_c : std_ulogic_vector(11 downto 0) := x"3c1"; + constant csr_pmpaddr18_c : std_ulogic_vector(11 downto 0) := x"3c2"; + constant csr_pmpaddr19_c : std_ulogic_vector(11 downto 0) := x"3c3"; + constant csr_pmpaddr20_c : std_ulogic_vector(11 downto 0) := x"3c4"; + constant csr_pmpaddr21_c : std_ulogic_vector(11 downto 0) := x"3c5"; + constant csr_pmpaddr22_c : std_ulogic_vector(11 downto 0) := x"3c6"; + constant csr_pmpaddr23_c : std_ulogic_vector(11 downto 0) := x"3c7"; + constant csr_pmpaddr24_c : std_ulogic_vector(11 downto 0) := x"3c8"; + constant csr_pmpaddr25_c : std_ulogic_vector(11 downto 0) := x"3c9"; + constant csr_pmpaddr26_c : std_ulogic_vector(11 downto 0) := x"3ca"; + constant csr_pmpaddr27_c : std_ulogic_vector(11 downto 0) := x"3cb"; + constant csr_pmpaddr28_c : std_ulogic_vector(11 downto 0) := x"3cc"; + constant csr_pmpaddr29_c : std_ulogic_vector(11 downto 0) := x"3cd"; + constant csr_pmpaddr30_c : std_ulogic_vector(11 downto 0) := x"3ce"; + constant csr_pmpaddr31_c : std_ulogic_vector(11 downto 0) := x"3cf"; + constant csr_pmpaddr32_c : std_ulogic_vector(11 downto 0) := x"3d0"; + constant csr_pmpaddr33_c : std_ulogic_vector(11 downto 0) := x"3d1"; + constant csr_pmpaddr34_c : std_ulogic_vector(11 downto 0) := x"3d2"; + constant csr_pmpaddr35_c : std_ulogic_vector(11 downto 0) := x"3d3"; + constant csr_pmpaddr36_c : std_ulogic_vector(11 downto 0) := x"3d4"; + constant csr_pmpaddr37_c : std_ulogic_vector(11 downto 0) := x"3d5"; + constant csr_pmpaddr38_c : std_ulogic_vector(11 downto 0) := x"3d6"; + constant csr_pmpaddr39_c : std_ulogic_vector(11 downto 0) := x"3d7"; + constant csr_pmpaddr40_c : std_ulogic_vector(11 downto 0) := x"3d8"; + constant csr_pmpaddr41_c : std_ulogic_vector(11 downto 0) := x"3d9"; + constant csr_pmpaddr42_c : std_ulogic_vector(11 downto 0) := x"3da"; + constant csr_pmpaddr43_c : std_ulogic_vector(11 downto 0) := x"3db"; + constant csr_pmpaddr44_c : std_ulogic_vector(11 downto 0) := x"3dc"; + constant csr_pmpaddr45_c : std_ulogic_vector(11 downto 0) := x"3dd"; + constant csr_pmpaddr46_c : std_ulogic_vector(11 downto 0) := x"3de"; + constant csr_pmpaddr47_c : std_ulogic_vector(11 downto 0) := x"3df"; + constant csr_pmpaddr48_c : std_ulogic_vector(11 downto 0) := x"3e0"; + constant csr_pmpaddr49_c : std_ulogic_vector(11 downto 0) := x"3e1"; + constant csr_pmpaddr50_c : std_ulogic_vector(11 downto 0) := x"3e2"; + constant csr_pmpaddr51_c : std_ulogic_vector(11 downto 0) := x"3e3"; + constant csr_pmpaddr52_c : std_ulogic_vector(11 downto 0) := x"3e4"; + constant csr_pmpaddr53_c : std_ulogic_vector(11 downto 0) := x"3e5"; + constant csr_pmpaddr54_c : std_ulogic_vector(11 downto 0) := x"3e6"; + constant csr_pmpaddr55_c : std_ulogic_vector(11 downto 0) := x"3e7"; + constant csr_pmpaddr56_c : std_ulogic_vector(11 downto 0) := x"3e8"; + constant csr_pmpaddr57_c : std_ulogic_vector(11 downto 0) := x"3e9"; + constant csr_pmpaddr58_c : std_ulogic_vector(11 downto 0) := x"3ea"; + constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb"; + constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec"; + constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed"; + constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee"; + constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef"; + -- debug mode registers -- + constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers + constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0"; + constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1"; + constant csr_dscratch0_c : std_ulogic_vector(11 downto 0) := x"7b2"; + -- machine counters/timers -- + constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; + constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; + -- + constant csr_mhpmcounter3_c : std_ulogic_vector(11 downto 0) := x"b03"; + constant csr_mhpmcounter4_c : std_ulogic_vector(11 downto 0) := x"b04"; + constant csr_mhpmcounter5_c : std_ulogic_vector(11 downto 0) := x"b05"; + constant csr_mhpmcounter6_c : std_ulogic_vector(11 downto 0) := x"b06"; + constant csr_mhpmcounter7_c : std_ulogic_vector(11 downto 0) := x"b07"; + constant csr_mhpmcounter8_c : std_ulogic_vector(11 downto 0) := x"b08"; + constant csr_mhpmcounter9_c : std_ulogic_vector(11 downto 0) := x"b09"; + constant csr_mhpmcounter10_c : std_ulogic_vector(11 downto 0) := x"b0a"; + constant csr_mhpmcounter11_c : std_ulogic_vector(11 downto 0) := x"b0b"; + constant csr_mhpmcounter12_c : std_ulogic_vector(11 downto 0) := x"b0c"; + constant csr_mhpmcounter13_c : std_ulogic_vector(11 downto 0) := x"b0d"; + constant csr_mhpmcounter14_c : std_ulogic_vector(11 downto 0) := x"b0e"; + constant csr_mhpmcounter15_c : std_ulogic_vector(11 downto 0) := x"b0f"; + constant csr_mhpmcounter16_c : std_ulogic_vector(11 downto 0) := x"b10"; + constant csr_mhpmcounter17_c : std_ulogic_vector(11 downto 0) := x"b11"; + constant csr_mhpmcounter18_c : std_ulogic_vector(11 downto 0) := x"b12"; + constant csr_mhpmcounter19_c : std_ulogic_vector(11 downto 0) := x"b13"; + constant csr_mhpmcounter20_c : std_ulogic_vector(11 downto 0) := x"b14"; + constant csr_mhpmcounter21_c : std_ulogic_vector(11 downto 0) := x"b15"; + constant csr_mhpmcounter22_c : std_ulogic_vector(11 downto 0) := x"b16"; + constant csr_mhpmcounter23_c : std_ulogic_vector(11 downto 0) := x"b17"; + constant csr_mhpmcounter24_c : std_ulogic_vector(11 downto 0) := x"b18"; + constant csr_mhpmcounter25_c : std_ulogic_vector(11 downto 0) := x"b19"; + constant csr_mhpmcounter26_c : std_ulogic_vector(11 downto 0) := x"b1a"; + constant csr_mhpmcounter27_c : std_ulogic_vector(11 downto 0) := x"b1b"; + constant csr_mhpmcounter28_c : std_ulogic_vector(11 downto 0) := x"b1c"; + constant csr_mhpmcounter29_c : std_ulogic_vector(11 downto 0) := x"b1d"; + constant csr_mhpmcounter30_c : std_ulogic_vector(11 downto 0) := x"b1e"; + constant csr_mhpmcounter31_c : std_ulogic_vector(11 downto 0) := x"b1f"; + -- + constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; + constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; + -- + constant csr_mhpmcounter3h_c : std_ulogic_vector(11 downto 0) := x"b83"; + constant csr_mhpmcounter4h_c : std_ulogic_vector(11 downto 0) := x"b84"; + constant csr_mhpmcounter5h_c : std_ulogic_vector(11 downto 0) := x"b85"; + constant csr_mhpmcounter6h_c : std_ulogic_vector(11 downto 0) := x"b86"; + constant csr_mhpmcounter7h_c : std_ulogic_vector(11 downto 0) := x"b87"; + constant csr_mhpmcounter8h_c : std_ulogic_vector(11 downto 0) := x"b88"; + constant csr_mhpmcounter9h_c : std_ulogic_vector(11 downto 0) := x"b89"; + constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a"; + constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b"; + constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c"; + constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d"; + constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e"; + constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f"; + constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90"; + constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91"; + constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92"; + constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93"; + constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94"; + constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95"; + constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96"; + constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97"; + constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98"; + constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99"; + constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a"; + constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b"; + constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c"; + constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d"; + constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e"; + constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f"; + + -- <<< standard read-only CSRs >>> -- + -- user counters/timers -- + constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; + constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; + constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; + constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; + constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81"; + constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82"; + -- machine information registers -- + constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; + constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; + constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; + constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; + constant csr_mconfigptr_c : std_ulogic_vector(11 downto 0) := x"f15"; + + -- Co-Processor IDs ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant cp_sel_shifter_c : std_ulogic_vector(1 downto 0) := "00"; -- shift operations (base ISA) + constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "01"; -- multiplication/division operations ('M' extensions) + constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "10"; -- bit manipulation ('B' extensions) + constant cp_sel_fpu_c : std_ulogic_vector(1 downto 0) := "11"; -- floating-point unit ('Zfinx' extension) + + -- ALU Function Codes --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- ALU core [DO NOT CHANGE ENCODING!] -- + constant alu_op_add_c : std_ulogic_vector(2 downto 0) := "000"; -- alu_result <= A + B + constant alu_op_sub_c : std_ulogic_vector(2 downto 0) := "001"; -- alu_result <= A - B +--constant alu_op_mova_c : std_ulogic_vector(2 downto 0) := "010"; -- alu_result <= A (rs1) + constant alu_op_slt_c : std_ulogic_vector(2 downto 0) := "011"; -- alu_result <= A < B + constant alu_op_movb_c : std_ulogic_vector(2 downto 0) := "100"; -- alu_result <= B + constant alu_op_xor_c : std_ulogic_vector(2 downto 0) := "101"; -- alu_result <= A xor B + constant alu_op_or_c : std_ulogic_vector(2 downto 0) := "110"; -- alu_result <= A or B + constant alu_op_and_c : std_ulogic_vector(2 downto 0) := "111"; -- alu_result <= A and B + -- function select (actual ALU result) -- + constant alu_func_core_c : std_ulogic_vector(1 downto 0) := "00"; -- r <= alu_result + constant alu_func_nxpc_c : std_ulogic_vector(1 downto 0) := "01"; -- r <= next_PC + constant alu_func_csrr_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= CSR read + constant alu_func_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (multi-cycle) + + -- Trap ID Codes -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- MSB: 1 = async exception (IRQ), 0 = sync exception (e.g. ebreak) + -- MSB-1: 1 = entry to debug mode, 0 = normal trapping + -- RISC-V compliant sync. exceptions -- + constant trap_ima_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00000"; -- 0.0: instruction misaligned + constant trap_iba_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00001"; -- 0.1: instruction access fault + constant trap_iil_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00010"; -- 0.2: illegal instruction + constant trap_brk_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00011"; -- 0.3: breakpoint + constant trap_lma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00100"; -- 0.4: load address misaligned + constant trap_lbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00101"; -- 0.5: load access fault + constant trap_sma_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00110"; -- 0.6: store address misaligned + constant trap_sbe_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "00111"; -- 0.7: store access fault + constant trap_uenv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01000"; -- 0.8: environment call from u-mode + constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode + -- RISC-V compliant interrupts (async. exceptions) -- + constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt + constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt + constant trap_mei_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "01011"; -- 1.11: machine external interrupt + -- NEORV32-specific (custom) interrupts (async. exceptions) -- + constant trap_firq0_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10000"; -- 1.16: fast interrupt 0 + constant trap_firq1_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10001"; -- 1.17: fast interrupt 1 + constant trap_firq2_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10010"; -- 1.18: fast interrupt 2 + constant trap_firq3_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10011"; -- 1.19: fast interrupt 3 + constant trap_firq4_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10100"; -- 1.20: fast interrupt 4 + constant trap_firq5_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10101"; -- 1.21: fast interrupt 5 + constant trap_firq6_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10110"; -- 1.22: fast interrupt 6 + constant trap_firq7_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "10111"; -- 1.23: fast interrupt 7 + constant trap_firq8_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11000"; -- 1.24: fast interrupt 8 + constant trap_firq9_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11001"; -- 1.25: fast interrupt 9 + constant trap_firq10_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11010"; -- 1.26: fast interrupt 10 + constant trap_firq11_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11011"; -- 1.27: fast interrupt 11 + constant trap_firq12_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11100"; -- 1.28: fast interrupt 12 + constant trap_firq13_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11101"; -- 1.29: fast interrupt 13 + constant trap_firq14_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11110"; -- 1.30: fast interrupt 14 + constant trap_firq15_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "11111"; -- 1.31: fast interrupt 15 + -- entering debug mode - cause -- + constant trap_db_break_c : std_ulogic_vector(6 downto 0) := "0" & "1" & "00010"; -- break instruction (sync / EXCEPTION) + constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- external halt request (async / IRQ) + constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- single-stepping (async / IRQ) + + -- CPU Control Exception System ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- exception source bits -- + constant exception_iaccess_c : natural := 0; -- instruction access fault + constant exception_iillegal_c : natural := 1; -- illegal instruction + constant exception_ialign_c : natural := 2; -- instruction address misaligned + constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode + constant exception_u_envcall_c : natural := 4; -- ENV call from u-mode + constant exception_break_c : natural := 5; -- breakpoint + constant exception_salign_c : natural := 6; -- store address misaligned + constant exception_lalign_c : natural := 7; -- load address misaligned + constant exception_saccess_c : natural := 8; -- store access fault + constant exception_laccess_c : natural := 9; -- load access fault + -- for debug mode only -- + constant exception_db_break_c : natural := 10; -- enter debug mode via ebreak instruction ("sync EXCEPTION") + -- + constant exception_width_c : natural := 11; -- length of this list in bits + -- interrupt source bits -- + constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt + constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt + constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt + constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0 + constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1 + constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2 + constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3 + constant interrupt_firq_4_c : natural := 7; -- fast interrupt channel 4 + constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5 + constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6 + constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7 + constant interrupt_firq_8_c : natural := 11; -- fast interrupt channel 8 + constant interrupt_firq_9_c : natural := 12; -- fast interrupt channel 9 + constant interrupt_firq_10_c : natural := 13; -- fast interrupt channel 10 + constant interrupt_firq_11_c : natural := 14; -- fast interrupt channel 11 + constant interrupt_firq_12_c : natural := 15; -- fast interrupt channel 12 + constant interrupt_firq_13_c : natural := 16; -- fast interrupt channel 13 + constant interrupt_firq_14_c : natural := 17; -- fast interrupt channel 14 + constant interrupt_firq_15_c : natural := 18; -- fast interrupt channel 15 + -- for debug mode only -- + constant interrupt_db_halt_c : natural := 19; -- enter debug mode via external halt request ("async IRQ") + constant interrupt_db_step_c : natural := 20; -- enter debug mode via single-stepping ("async IRQ") + -- + constant interrupt_width_c : natural := 21; -- length of this list in bits + + -- CPU Privilege Modes -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode + constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode + + -- HPM Event System ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + constant hpmcnt_event_cy_c : natural := 0; -- Active cycle + constant hpmcnt_event_never_c : natural := 1; -- Unused / never (actually, this would be used for TIME) + constant hpmcnt_event_ir_c : natural := 2; -- Retired instruction + constant hpmcnt_event_cir_c : natural := 3; -- Retired compressed instruction + constant hpmcnt_event_wait_if_c : natural := 4; -- Instruction fetch memory wait cycle + constant hpmcnt_event_wait_ii_c : natural := 5; -- Instruction issue wait cycle + constant hpmcnt_event_wait_mc_c : natural := 6; -- Multi-cycle ALU-operation wait cycle + constant hpmcnt_event_load_c : natural := 7; -- Load operation + constant hpmcnt_event_store_c : natural := 8; -- Store operation + constant hpmcnt_event_wait_ls_c : natural := 9; -- Load/store memory wait cycle + constant hpmcnt_event_jump_c : natural := 10; -- Unconditional jump + constant hpmcnt_event_branch_c : natural := 11; -- Conditional branch (taken or not taken) + constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch + constant hpmcnt_event_trap_c : natural := 13; -- Entered trap + constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception + -- + constant hpmcnt_event_size_c : natural := 15; -- length of this list + + -- Clock Generator ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + constant clk_div2_c : natural := 0; + constant clk_div4_c : natural := 1; + constant clk_div8_c : natural := 2; + constant clk_div64_c : natural := 3; + constant clk_div128_c : natural := 4; + constant clk_div1024_c : natural := 5; + constant clk_div2048_c : natural := 6; + constant clk_div4096_c : natural := 7; + + -- Component: NEORV32 Processor Top Entity ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + component neorv32_top + generic ( + -- General -- + CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + -- Internal Instruction memory (IMEM) -- + MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + -- Internal Data memory (DMEM) -- + MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes + -- Internal Cache memory (iCACHE) -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External memory interface (WISHBONE) -- + MEM_EXT_EN : boolean := false; -- implement external memory bus interface? + MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled) + MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian + MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false + -- Stream link interface (SLINK) -- + SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) + SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) + SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic + IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits + IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- JTAG on-chip debugger interface -- + jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional) + jtag_tck_i : in std_ulogic := 'U'; -- serial clock + jtag_tdi_i : in std_ulogic := 'U'; -- serial data input + jtag_tdo_o : out std_ulogic; -- serial data output + jtag_tms_i : in std_ulogic := 'U'; -- mode select + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag + wb_adr_o : out std_ulogic_vector(31 downto 0); -- address + wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data + wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data + wb_we_o : out std_ulogic; -- read/write + wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable + wb_stb_o : out std_ulogic; -- strobe + wb_cyc_o : out std_ulogic; -- valid cycle + wb_lock_o : out std_ulogic; -- exclusive access request + wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge + wb_err_i : in std_ulogic := 'L'; -- transfer error + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o : out std_ulogic; -- indicates an executed FENCE operation + fencei_o : out std_ulogic; -- indicates an executed FENCEI operation + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o : out sdata_8x32_t; -- output data + slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data + slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input + slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output + gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data + uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o : out std_ulogic; -- UART1 send data + uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data + uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_ulogic; -- SPI serial clock + spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in + spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic := 'U'; -- twi serial data line + twi_scl_io : inout std_logic := 'U'; -- twi serial clock line + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels + -- Custom Functions Subsystem IO -- + cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit + cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o : out std_ulogic; -- async serial data line + -- System time -- + mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels + -- CPU Interrupts -- + mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt + mext_irq_i : in std_ulogic := 'L' -- machine external interrupt + ); + end component; + + -- Component: CPU Top Entity -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu + generic ( + -- General -- + HW_THREAD_ID : natural; -- hardware thread id (32-bit) + CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address + CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? + -- Extension Options -- + FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64) + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + sleep_o : out std_ulogic; -- cpu is in sleep mode when set + debug_o : out std_ulogic; -- cpu is in debug mode when set + -- instruction bus interface -- + i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + i_bus_we_o : out std_ulogic; -- write enable + i_bus_re_o : out std_ulogic; -- read enable + i_bus_lock_o : out std_ulogic; -- exclusive access request + i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + i_bus_err_i : in std_ulogic; -- bus transfer error + i_bus_fence_o : out std_ulogic; -- executed FENCEI operation + i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level + -- data bus interface -- + d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + d_bus_we_o : out std_ulogic; -- write enable + d_bus_re_o : out std_ulogic; -- read enable + d_bus_lock_o : out std_ulogic; -- exclusive access request + d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + d_bus_err_i : in std_ulogic; -- bus transfer error + d_bus_fence_o : out std_ulogic; -- executed FENCE operation + d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level + -- system time input from MTIME -- + time_i : in std_ulogic_vector(63 downto 0); -- current system time + -- interrupts (risc-v compliant) -- + msw_irq_i : in std_ulogic; -- machine software interrupt + mext_irq_i : in std_ulogic; -- machine external interrupt + mtime_irq_i : in std_ulogic; -- machine timer interrupt + -- fast interrupts (custom) -- + firq_i : in std_ulogic_vector(15 downto 0); + -- debug mode (halt) request -- + db_halt_req_i : in std_ulogic + ); + end component; + + -- Component: CPU Control ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_control + generic ( + -- General -- + HW_THREAD_ID : natural; -- hardware thread id (32-bit) + CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address + CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? + -- Extension Options -- + CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64) + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- status input -- + alu_idone_i : in std_ulogic; -- ALU iterative operation done + bus_i_wait_i : in std_ulogic; -- wait for bus + bus_d_wait_i : in std_ulogic; -- wait for bus + excl_state_i : in std_ulogic; -- atomic/exclusive access lock status + -- data input -- + instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction + cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status + alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + -- data output -- + imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate + fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch + curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction) + next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to next instruction) + csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data + -- FPU interface -- + fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags + -- debug mode (halt) request -- + db_halt_req_i : in std_ulogic; + -- interrupts (risc-v compliant) -- + msw_irq_i : in std_ulogic; -- machine software interrupt + mext_irq_i : in std_ulogic; -- machine external interrupt + mtime_irq_i : in std_ulogic; -- machine timer interrupt + -- fast interrupts (custom) -- + firq_i : in std_ulogic_vector(15 downto 0); + -- system time input from MTIME -- + time_i : in std_ulogic_vector(63 downto 0); -- current system time + -- physical memory protection -- + pmp_addr_o : out pmp_addr_if_t; -- addresses + pmp_ctrl_o : out pmp_ctrl_if_t; -- configs + -- bus access exceptions -- + mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register + ma_instr_i : in std_ulogic; -- misaligned instruction address + ma_load_i : in std_ulogic; -- misaligned load data address + ma_store_i : in std_ulogic; -- misaligned store data address + be_instr_i : in std_ulogic; -- bus error on instruction access + be_load_i : in std_ulogic; -- bus error on load data access + be_store_i : in std_ulogic -- bus error on store data access + ); + end component; + + -- Component: CPU Register File ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_regfile + generic ( + CPU_EXTENSION_RISCV_E : boolean -- implement embedded RF extension? + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- data input -- + mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data + alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result + -- data output -- + rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1 + rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2 + ); + end component; + + -- Component: CPU ALU --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_alu + generic ( + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + -- Extension Options -- + FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- data input -- + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC + pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- next PC + imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate + csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data + -- data output -- + cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result + add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result + fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags + -- status -- + idone_o : out std_ulogic -- iterative processing units done? + ); + end component; + + -- Component: CPU Co-Processor SHIFTER ---------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_cp_shifter + generic ( + FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + shamt_i : in std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); -- shift amount + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + valid_o : out std_ulogic -- data output valid + ); + end component; + + -- Component: CPU Co-Processor MULDIV ('M' extension) ------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_cp_muldiv + generic ( + FAST_MUL_EN : boolean; -- use DSPs for faster multiplication + DIVISION_EN : boolean -- implement divider hardware + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + valid_o : out std_ulogic -- data output valid + ); + end component; + + -- Component: CPU Co-Processor Bit-Manipulation Unit ('B' extension) ---------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_cp_bitmanip is + generic ( + FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + shamt_i : in std_ulogic_vector(index_size_f(data_width_c)-1 downto 0); -- shift amount + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + valid_o : out std_ulogic -- data output valid + ); + end component; + + -- Component: CPU Co-Processor 32-bit FPU ('Zfinx' extension) ----------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_cp_fpu + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + start_i : in std_ulogic; -- trigger operation + -- data input -- + cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status + rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 + rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 + -- result and status -- + res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result + fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags + valid_o : out std_ulogic -- data output valid + ); + end component; + + -- Component: CPU Bus Interface ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_bus + generic ( + CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension? + CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension? + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic := '0'; -- global reset, low-active, async + ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus + -- cpu instruction fetch interface -- + fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch + instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction + i_wait_o : out std_ulogic; -- wait for fetch to complete + -- + ma_instr_o : out std_ulogic; -- misaligned instruction address + be_instr_o : out std_ulogic; -- bus error on instruction access + -- cpu data access interface -- + addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address + wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data + rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data + mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register + d_wait_o : out std_ulogic; -- wait for access to complete + -- + excl_state_o : out std_ulogic; -- atomic/exclusive access status + ma_load_o : out std_ulogic; -- misaligned load data address + ma_store_o : out std_ulogic; -- misaligned store data address + be_load_o : out std_ulogic; -- bus error on load data access + be_store_o : out std_ulogic; -- bus error on store data access + -- physical memory protection -- + pmp_addr_i : in pmp_addr_if_t; -- addresses + pmp_ctrl_i : in pmp_ctrl_if_t; -- configs + -- instruction bus -- + i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + i_bus_we_o : out std_ulogic; -- write enable + i_bus_re_o : out std_ulogic; -- read enable + i_bus_lock_o : out std_ulogic; -- exclusive access request + i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + i_bus_err_i : in std_ulogic; -- bus transfer error + i_bus_fence_o : out std_ulogic; -- fence operation + -- data bus -- + d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + d_bus_we_o : out std_ulogic; -- write enable + d_bus_re_o : out std_ulogic; -- read enable + d_bus_lock_o : out std_ulogic; -- exclusive access request + d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + d_bus_err_i : in std_ulogic; -- bus transfer error + d_bus_fence_o : out std_ulogic -- fence operation + ); + end component; + + -- Component: Bus Keeper ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + component neorv32_bus_keeper is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset, low-active, async + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error + -- bus monitoring -- + bus_addr_i : in std_ulogic_vector(31 downto 0); -- address + bus_rden_i : in std_ulogic; -- read enable + bus_wren_i : in std_ulogic; -- write enable + bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system + bus_err_i : in std_ulogic; -- transfer error from bus system + bus_tmo_i : in std_ulogic; -- transfer timeout (external interface) + bus_ext_i : in std_ulogic -- external bus access + ); + end component; + + -- Component: CPU Instruction Cache ------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_icache + generic ( + ICACHE_NUM_BLOCKS : natural; -- number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural; -- block size in bytes (min 4), has to be a power of 2 + ICACHE_NUM_SETS : natural -- associativity / number of sets (1=direct_mapped), has to be a power of 2 + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + clear_i : in std_ulogic; -- cache clear + -- host controller interface -- + host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable + host_we_i : in std_ulogic; -- write enable + host_re_i : in std_ulogic; -- read enable + host_ack_o : out std_ulogic; -- bus transfer acknowledge + host_err_o : out std_ulogic; -- bus transfer error + -- peripheral bus interface -- + bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + bus_we_o : out std_ulogic; -- write enable + bus_re_o : out std_ulogic; -- read enable + bus_ack_i : in std_ulogic; -- bus transfer acknowledge + bus_err_i : in std_ulogic -- bus transfer error + ); + end component; + + -- Component: CPU Bus Switch -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_busswitch + generic ( + PORT_CA_READ_ONLY : boolean; -- set if controller port A is read-only + PORT_CB_READ_ONLY : boolean -- set if controller port B is read-only + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- controller interface a -- + ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable + ca_bus_we_i : in std_ulogic; -- write enable + ca_bus_re_i : in std_ulogic; -- read enable + ca_bus_lock_i : in std_ulogic; -- exclusive access request + ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge + ca_bus_err_o : out std_ulogic; -- bus transfer error + -- controller interface b -- + cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable + cb_bus_we_i : in std_ulogic; -- write enable + cb_bus_re_i : in std_ulogic; -- read enable + cb_bus_lock_i : in std_ulogic; -- exclusive access request + cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge + cb_bus_err_o : out std_ulogic; -- bus transfer error + -- peripheral bus -- + p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B + p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable + p_bus_we_o : out std_ulogic; -- write enable + p_bus_re_o : out std_ulogic; -- read enable + p_bus_lock_o : out std_ulogic; -- exclusive access request + p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge + p_bus_err_i : in std_ulogic -- bus transfer error + ); + end component; + + -- Component: CPU Compressed Instructions Decompressor ------------------------------------ + -- ------------------------------------------------------------------------------------------- + component neorv32_cpu_decompressor + port ( + -- instruction input -- + ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input + -- instruction output -- + ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction + ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction + ); + end component; + + -- Component: Processor-internal instruction memory (IMEM) -------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_imem + generic ( + IMEM_BASE : std_ulogic_vector(31 downto 0); -- memory base address + IMEM_SIZE : natural; -- processor-internal instruction memory size in bytes + IMEM_AS_IROM : boolean -- implement IMEM as pre-initialized read-only memory? + ); + port ( + clk_i : in std_ulogic; -- global clock line + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable + addr_i : in std_ulogic_vector(31 downto 0); -- address + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); + end component; + + -- Component: Processor-internal data memory (DMEM) --------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_dmem + generic ( + DMEM_BASE : std_ulogic_vector(31 downto 0); -- memory base address + DMEM_SIZE : natural -- processor-internal instruction memory size in bytes + ); + port ( + clk_i : in std_ulogic; -- global clock line + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable + addr_i : in std_ulogic_vector(31 downto 0); -- address + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); + end component; + + -- Component: Processor-internal bootloader ROM (BOOTROM) --------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_boot_rom + generic ( + BOOTROM_BASE : std_ulogic_vector(31 downto 0) -- boot ROM base address + ); + port ( + clk_i : in std_ulogic; -- global clock line + rden_i : in std_ulogic; -- read enable + addr_i : in std_ulogic_vector(31 downto 0); -- address + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); + end component; + + -- Component: Machine System Timer (mtime) ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + component neorv32_mtime + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- time output for CPU -- + time_o : out std_ulogic_vector(63 downto 0); -- current system time + -- interrupt -- + irq_o : out std_ulogic -- interrupt request + ); + end component; + + -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------ + -- ------------------------------------------------------------------------------------------- + component neorv32_gpio + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- parallel io -- + gpio_o : out std_ulogic_vector(63 downto 0); + gpio_i : in std_ulogic_vector(63 downto 0) + ); + end component; + + -- Component: Watchdog Timer (WDT) -------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_wdt + generic ( + DEBUG_EN : boolean -- CPU debug mode implemented? + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + addr_i : in std_ulogic_vector(31 downto 0); -- address + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- CPU in debug mode? -- + cpu_debug_i : in std_ulogic; + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- timeout event -- + irq_o : out std_ulogic; -- timeout IRQ + rstn_o : out std_ulogic -- timeout reset, low_active, use it as async! + ); + end component; + + -- Component: Universal Asynchronous Receiver and Transmitter (UART) ---------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_uart + generic ( + UART_PRIMARY : boolean; -- true = primary UART (UART0), false = secondary UART (UART1) + UART_RX_FIFO : natural; -- RX fifo depth, has to be a power of two, min 1 + UART_TX_FIFO : natural -- TX fifo depth, has to be a power of two, min 1 + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- com lines -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- hardware flow control -- + uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional + uart_cts_i : in std_ulogic; -- UART.TX allowed to transmit, low-active, optional + -- interrupts -- + irq_rxd_o : out std_ulogic; -- uart data received interrupt + irq_txd_o : out std_ulogic -- uart transmission done interrupt + ); + end component; + + -- Component: Serial Peripheral Interface (SPI) ------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_spi + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- com lines -- + spi_sck_o : out std_ulogic; -- SPI serial clock + spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in + spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out + spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS + -- interrupt -- + irq_o : out std_ulogic -- transmission done interrupt + ); + end component; + + -- Component: Two-Wire Interface (TWI) ---------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_twi + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- com lines -- + twi_sda_io : inout std_logic; -- serial data line + twi_scl_io : inout std_logic; -- serial clock line + -- interrupt -- + irq_o : out std_ulogic -- transfer done IRQ + ); + end component; + + -- Component: Pulse-Width Modulation Controller (PWM) ------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_pwm + generic ( + NUM_CHANNELS : natural -- number of PWM channels (0..60) + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- pwm output channels -- + pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0) + ); + end component; + + -- Component: True Random Number Generator (TRNG) ----------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_trng + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); + end component; + + -- Component: Wishbone Bus Gateway (WISHBONE) --------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_wishbone + generic ( + -- Internal instruction memory -- + MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes + -- Internal data memory -- + MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes + -- Interface Configuration -- + BUS_TIMEOUT : natural; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception + PIPE_MODE : boolean; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian + ASYNC_RX : boolean -- use register buffer for RX data when false + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + -- host access -- + src_i : in std_ulogic; -- access type (0: data, 1:instruction) + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + lock_i : in std_ulogic; -- exclusive access request + ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error + tmo_o : out std_ulogic; -- transfer timeout + priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level + ext_o : out std_ulogic; -- active external access + -- wishbone interface -- + wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag + wb_adr_o : out std_ulogic_vector(31 downto 0); -- address + wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data + wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data + wb_we_o : out std_ulogic; -- read/write + wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable + wb_stb_o : out std_ulogic; -- strobe + wb_cyc_o : out std_ulogic; -- valid cycle + wb_lock_o : out std_ulogic; -- exclusive access request + wb_ack_i : in std_ulogic; -- transfer acknowledge + wb_err_i : in std_ulogic -- transfer error + ); + end component; + + -- Component: Custom Functions Subsystem (CFS) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_cfs + generic ( + CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic + CFS_IN_SIZE : positive; -- size of CFS input conduit in bits + CFS_OUT_SIZE : positive -- size of CFS output conduit in bits + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active, use as async + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- word write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs + -- interrupt -- + irq_o : out std_ulogic; -- interrupt request + -- custom io (conduit) -- + cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE-1 downto 0); -- custom inputs + cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0) -- custom outputs + ); + end component; + + -- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) -------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_neoled + generic ( + FIFO_DEPTH : natural -- TX FIFO depth (1..32k, power of two) + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- interrupt -- + irq_o : out std_ulogic; -- interrupt request + -- NEOLED output -- + neoled_o : out std_ulogic -- serial async data line + ); + end component; + + -- Component: Stream Link Interface (SLINK) ----------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_slink + generic ( + SLINK_NUM_TX : natural; -- number of TX links (0..8) + SLINK_NUM_RX : natural; -- number of TX links (0..8) + SLINK_TX_FIFO : natural; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural -- RX fifo depth, has to be a power of two + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- interrupt -- + irq_tx_o : out std_ulogic; -- transmission done + irq_rx_o : out std_ulogic; -- data received + -- TX stream interfaces -- + slink_tx_dat_o : out sdata_8x32_t; -- output data + slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_ulogic_vector(7 downto 0); -- ready to send + -- RX stream interfaces -- + slink_rx_dat_i : in sdata_8x32_t; -- input data + slink_rx_val_i : in std_ulogic_vector(7 downto 0); -- valid input + slink_rx_rdy_o : out std_ulogic_vector(7 downto 0) -- ready to receive + ); + end component; + + -- Component: External Interrupt Controller (XIRQ) ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_xirq + generic ( + XIRQ_NUM_CH : natural; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0); -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- external interrupt lines -- + xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + -- CPU interrupt -- + cpu_irq_o : out std_ulogic + ); + end component; + + -- Component: General Purpose Timer (GPTMR) ----------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_gptmr + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- interrupt -- + irq_o : out std_ulogic -- transmission done interrupt + ); + end component; + + -- Component: System Configuration Information Memory (SYSINFO) --------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_sysinfo + generic ( + -- General -- + CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? + -- Extension Options -- + FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN : boolean; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2 + -- External memory interface -- + MEM_EXT_EN : boolean; -- implement external memory bus interface? + MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian + -- On-Chip Debugger -- + ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? + -- Processor peripherals -- + IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural; -- number of PWM channels to implement + IO_WDT_EN : boolean; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)? + IO_SLINK_EN : boolean; -- implement stream link interface? + IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement + IO_GPTMR_EN : boolean -- implement general purpose timer (GPTMR)? + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); + end component; + + -- Component: General Purpose FIFO -------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_fifo + generic ( + FIFO_DEPTH : natural; -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH : natural; -- size of data elements in fifo + FIFO_RSYNC : boolean; -- false = async read; true = sync read + FIFO_SAFE : boolean -- true = allow read/write only if entry available + ); + port ( + -- control -- + clk_i : in std_ulogic; -- clock, rising edge + rstn_i : in std_ulogic; -- async reset, low-active + clear_i : in std_ulogic; -- sync reset, high-active + level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level + half_o : out std_ulogic; -- FIFO is at least half full + -- write port -- + wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data + we_i : in std_ulogic; -- write enable + free_o : out std_ulogic; -- at least one entry is free when set + -- read port -- + re_i : in std_ulogic; -- read enable + rdata_o : out std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- read data + avail_o : out std_ulogic -- data available when set + ); + end component; + + -- Component: On-Chip Debugger - Debug Module (DM) ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_debug_dm + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + -- debug module interface (DMI) -- + dmi_rstn_i : in std_ulogic; + dmi_req_valid_i : in std_ulogic; + dmi_req_ready_o : out std_ulogic; -- DMI is allowed to make new requests when set + dmi_req_addr_i : in std_ulogic_vector(06 downto 0); + dmi_req_op_i : in std_ulogic; -- 0=read, 1=write + dmi_req_data_i : in std_ulogic_vector(31 downto 0); + dmi_resp_valid_o : out std_ulogic; -- response valid when set + dmi_resp_ready_i : in std_ulogic; -- ready to receive respond + dmi_resp_data_o : out std_ulogic_vector(31 downto 0); + dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error + -- CPU bus access -- + cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address + cpu_rden_i : in std_ulogic; -- read enable + cpu_wren_i : in std_ulogic; -- write enable + cpu_data_i : in std_ulogic_vector(31 downto 0); -- data in + cpu_data_o : out std_ulogic_vector(31 downto 0); -- data out + cpu_ack_o : out std_ulogic; -- transfer acknowledge + -- CPU control -- + cpu_ndmrstn_o : out std_ulogic; -- soc reset + cpu_halt_req_o : out std_ulogic -- request hart to halt (enter debug mode) + ); + end component; + + -- Component: On-Chip Debugger - Debug Transport Module (DTM) ----------------------------- + -- ------------------------------------------------------------------------------------------- + component neorv32_debug_dtm + generic ( + IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version + IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number + IDCODE_MANID : std_ulogic_vector(10 downto 0) -- manufacturer id + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + -- jtag connection -- + jtag_trst_i : in std_ulogic; + jtag_tck_i : in std_ulogic; + jtag_tdi_i : in std_ulogic; + jtag_tdo_o : out std_ulogic; + jtag_tms_i : in std_ulogic; + -- debug module interface (DMI) -- + dmi_rstn_o : out std_ulogic; + dmi_req_valid_o : out std_ulogic; + dmi_req_ready_i : in std_ulogic; -- DMI is allowed to make new requests when set + dmi_req_addr_o : out std_ulogic_vector(06 downto 0); + dmi_req_op_o : out std_ulogic; -- 0=read, 1=write + dmi_req_data_o : out std_ulogic_vector(31 downto 0); + dmi_resp_valid_i : in std_ulogic; -- response valid when set + dmi_resp_ready_o : out std_ulogic; -- ready to receive respond + dmi_resp_data_i : in std_ulogic_vector(31 downto 0); + dmi_resp_err_i : in std_ulogic -- 0=ok, 1=error + ); + end component; + +end neorv32_package; + +package body neorv32_package is + + -- Function: Minimal required number of bits to represent numbers ----------------- + -- ------------------------------------------------------------------------------------------- + function index_size_f(input : natural) return natural is + begin + for i in 0 to natural'high loop + if (2**i >= input) then + return i; + end if; + end loop; -- i + return 0; + end function index_size_f; + + -- Function: Conditional select natural --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is + begin + if (cond = true) then + return val_t; + else + return val_f; + end if; + end function cond_sel_natural_f; + + -- Function: Conditional select integer --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer is + begin + if (cond = true) then + return val_t; + else + return val_f; + end if; + end function cond_sel_int_f; + + -- Function: Conditional select std_ulogic_vector ----------------------------------------- + -- ------------------------------------------------------------------------------------------- + function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is + begin + if (cond = true) then + return val_t; + else + return val_f; + end if; + end function cond_sel_stdulogicvector_f; + + -- Function: Conditional select std_ulogic ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic is + begin + if (cond = true) then + return val_t; + else + return val_f; + end if; + end function cond_sel_stdulogic_f; + + -- Function: Conditional select string ---------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is + begin + if (cond = true) then + return val_t; + else + return val_f; + end if; + end function cond_sel_string_f; + + -- Function: Convert bool to std_ulogic --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function bool_to_ulogic_f(cond : boolean) return std_ulogic is + begin + if (cond = true) then + return '1'; + else + return '0'; + end if; + end function bool_to_ulogic_f; + + -- Function: OR-reduce all bits ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function or_reduce_f(a : std_ulogic_vector) return std_ulogic is + variable tmp_v : std_ulogic; + begin + tmp_v := '0'; + for i in a'range loop + tmp_v := tmp_v or a(i); + end loop; -- i + return tmp_v; + end function or_reduce_f; + + -- Function: AND-reduce all bits ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function and_reduce_f(a : std_ulogic_vector) return std_ulogic is + variable tmp_v : std_ulogic; + begin + tmp_v := '1'; + for i in a'range loop + tmp_v := tmp_v and a(i); + end loop; -- i + return tmp_v; + end function and_reduce_f; + + -- Function: XOR-reduce all bits ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function xor_reduce_f(a : std_ulogic_vector) return std_ulogic is + variable tmp_v : std_ulogic; + begin + tmp_v := '0'; + for i in a'range loop + tmp_v := tmp_v xor a(i); + end loop; -- i + return tmp_v; + end function xor_reduce_f; + + -- Function: Convert std_ulogic_vector to hex char ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is + variable output_v : character; + begin + case input is + when x"0" => output_v := '0'; + when x"1" => output_v := '1'; + when x"2" => output_v := '2'; + when x"3" => output_v := '3'; + when x"4" => output_v := '4'; + when x"5" => output_v := '5'; + when x"6" => output_v := '6'; + when x"7" => output_v := '7'; + when x"8" => output_v := '8'; + when x"9" => output_v := '9'; + when x"a" => output_v := 'a'; + when x"b" => output_v := 'b'; + when x"c" => output_v := 'c'; + when x"d" => output_v := 'd'; + when x"e" => output_v := 'e'; + when x"f" => output_v := 'f'; + when others => output_v := '?'; + end case; + return output_v; + end function to_hexchar_f; + + -- Function: Convert hex char to std_ulogic_vector ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is + variable hex_value_v : std_ulogic_vector(3 downto 0); + begin + case input is + when '0' => hex_value_v := x"0"; + when '1' => hex_value_v := x"1"; + when '2' => hex_value_v := x"2"; + when '3' => hex_value_v := x"3"; + when '4' => hex_value_v := x"4"; + when '5' => hex_value_v := x"5"; + when '6' => hex_value_v := x"6"; + when '7' => hex_value_v := x"7"; + when '8' => hex_value_v := x"8"; + when '9' => hex_value_v := x"9"; + when 'a' | 'A' => hex_value_v := x"a"; + when 'b' | 'B' => hex_value_v := x"b"; + when 'c' | 'C' => hex_value_v := x"c"; + when 'd' | 'D' => hex_value_v := x"d"; + when 'e' | 'E' => hex_value_v := x"e"; + when 'f' | 'F' => hex_value_v := x"f"; + when others => hex_value_v := (others => 'X'); + end case; + return hex_value_v; + end function hexchar_to_stdulogicvector_f; + + -- Function: Bit reversal ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is + variable output_v : std_ulogic_vector(input'range); + begin + for i in 0 to input'length-1 loop + output_v(input'length-i-1) := input(i); + end loop; -- i + return output_v; + end function bit_rev_f; + + -- Function: Test if input number is a power of two --------------------------------------- + -- ------------------------------------------------------------------------------------------- + function is_power_of_two_f(input : natural) return boolean is + begin + if (input = 1) then -- 2^0 + return true; + elsif ((input / 2) /= 0) and ((input mod 2) = 0) then + return true; + else + return false; + end if; + end function is_power_of_two_f; + + -- Function: Swap all bytes of a 32-bit word (endianness conversion) ---------------------- + -- ------------------------------------------------------------------------------------------- + function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is + variable output_v : std_ulogic_vector(input'range); + begin + output_v(07 downto 00) := input(31 downto 24); + output_v(15 downto 08) := input(23 downto 16); + output_v(23 downto 16) := input(15 downto 08); + output_v(31 downto 24) := input(07 downto 00); + return output_v; + end function bswap32_f; + + -- Function: Convert char to lowercase ---------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function char_to_lower_f(ch : character) return character is + variable res: character; + begin + case ch is + when 'A' => res := 'a'; + when 'B' => res := 'b'; + when 'C' => res := 'c'; + when 'D' => res := 'd'; + when 'E' => res := 'e'; + when 'F' => res := 'f'; + when 'G' => res := 'g'; + when 'H' => res := 'h'; + when 'I' => res := 'i'; + when 'J' => res := 'j'; + when 'K' => res := 'k'; + when 'L' => res := 'l'; + when 'M' => res := 'm'; + when 'N' => res := 'n'; + when 'O' => res := 'o'; + when 'P' => res := 'p'; + when 'Q' => res := 'q'; + when 'R' => res := 'r'; + when 'S' => res := 's'; + when 'T' => res := 't'; + when 'U' => res := 'u'; + when 'V' => res := 'v'; + when 'W' => res := 'w'; + when 'X' => res := 'x'; + when 'Y' => res := 'y'; + when 'Z' => res := 'z'; + when others => res := ch; + end case; + return res; + end function char_to_lower_f; + + -- Function: Compare strings (convert to lower case, check lengths) ----------------------- + -- ------------------------------------------------------------------------------------------- + function str_equal_f(str0 : string; str1 : string) return boolean is + variable tmp0_v : string(str0'range); + variable tmp1_v : string(str1'range); + begin + if (str0'length /= str1'length) then -- equal length? + return false; + else + -- convert to lower case -- + for i in str0'range loop + tmp0_v(i) := char_to_lower_f(str0(i)); + end loop; + for i in str1'range loop + tmp1_v(i) := char_to_lower_f(str1(i)); + end loop; + -- compare lowercase strings -- + if (tmp0_v = tmp1_v) then + return true; + else + return false; + end if; + end if; + end function str_equal_f; + + -- Function: Population count (number of set bits) ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + function popcount_f(input : std_ulogic_vector) return natural is + variable cnt_v : natural range 0 to input'length; + begin + cnt_v := 0; + for i in input'length-1 downto 0 loop + if (input(i) = '1') then + cnt_v := cnt_v + 1; + end if; + end loop; -- i + return cnt_v; + end function popcount_f; + + -- Function: Count leading zeros ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + function leading_zeros_f(input : std_ulogic_vector) return natural is + variable cnt_v : natural range 0 to input'length; + begin + cnt_v := 0; + for i in input'length-1 downto 0 loop + if (input(i) = '0') then + cnt_v := cnt_v + 1; + else + exit; + end if; + end loop; -- i + return cnt_v; + end function leading_zeros_f; + + -- Function: Initialize mem32_t array from another mem32_t array -------------------------- + -- ------------------------------------------------------------------------------------------- + -- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed + impure function mem32_init_f(init : mem32_t; depth : natural) return mem32_t is + variable mem_v : mem32_t(0 to depth-1); + begin + mem_v := (others => (others => '0')); -- make sure remaining memory entries are set to zero + if (init'length > depth) then + return mem_v; + end if; + for idx_v in 0 to init'length-1 loop -- init only in range of source data array + mem_v(idx_v) := init(idx_v); + end loop; -- idx_v + return mem_v; + end function mem32_init_f; + + +end neorv32_package; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_pwm.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_pwm.vhd new file mode 100644 index 0000000..f9813ab --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_pwm.vhd @@ -0,0 +1,200 @@ +-- ################################################################################################# +-- # << NEORV32 - Pulse Width Modulation Controller (PWM) >> # +-- # ********************************************************************************************* # +-- # Simple PWM controller with 8 bit resolution for the duty cycle and programmable base # +-- # frequency. The controller supports up to 60 PWM channels. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_pwm is + generic ( + NUM_CHANNELS : natural -- number of PWM channels (0..60) + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- pwm output channels -- + pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0) + ); +end neorv32_pwm; + +architecture neorv32_pwm_rtl of neorv32_pwm is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(pwm_size_c); -- low address boundary bit + + -- Control register bits -- + constant ctrl_enable_c : natural := 0; -- r/w: PWM enable + constant ctrl_prsc0_bit_c : natural := 1; -- r/w: prescaler select bit 0 + constant ctrl_prsc1_bit_c : natural := 2; -- r/w: prescaler select bit 1 + constant ctrl_prsc2_bit_c : natural := 3; -- r/w: prescaler select bit 2 + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- write enable + signal rden : std_ulogic; -- read enable + + -- accessible regs -- + type pwm_ch_t is array (0 to NUM_CHANNELS-1) of std_ulogic_vector(7 downto 0); + signal pwm_ch : pwm_ch_t; -- duty cycle (r/w) + signal enable : std_ulogic; -- enable unit (r/w) + signal prsc : std_ulogic_vector(2 downto 0); -- clock prescaler (r/w) + + type pwm_ch_rd_t is array (0 to 60-1) of std_ulogic_vector(7 downto 0); + signal pwm_ch_rd : pwm_ch_rd_t; -- duty cycle read-back + + -- prescaler clock generator -- + signal prsc_tick : std_ulogic; + + -- pwm core counter -- + signal pwm_cnt : std_ulogic_vector(7 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (NUM_CHANNELS > 60) report "NEORV32 PROCESSOR CONFIG ERROR! invalid number of channels! Has to be 0..60.!" severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = pwm_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= pwm_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + rden <= acc_en and rden_i; + wren <= acc_en and wren_i; + + + -- Write access --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + wr_access: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= rden or wren; + + -- write access -- + if (wren = '1') then + -- control register -- + if (addr = pwm_ctrl_addr_c) then + enable <= data_i(ctrl_enable_c); + prsc <= data_i(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c); + end if; + -- duty cycle registers -- + for i in 0 to NUM_CHANNELS-1 loop -- channel loop + if (addr(5 downto 2) = std_ulogic_vector(to_unsigned((i/4)+1, 4))) then -- 4 channels per register; add ctrl reg offset + pwm_ch(i) <= data_i((i mod 4)*8+7 downto (i mod 4)*8+0); + end if; + end loop; + end if; + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + case addr(5 downto 2) is + when x"0" => data_o(ctrl_enable_c) <= enable; data_o(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c) <= prsc; + when x"1" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(3) & pwm_ch_rd(2) & pwm_ch_rd(1) & pwm_ch_rd(0); else NULL; end if; + when x"2" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(7) & pwm_ch_rd(6) & pwm_ch_rd(5) & pwm_ch_rd(4); else NULL; end if; + when x"3" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(11) & pwm_ch_rd(10) & pwm_ch_rd(9) & pwm_ch_rd(8); else NULL; end if; + when x"4" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(15) & pwm_ch_rd(14) & pwm_ch_rd(13) & pwm_ch_rd(12); else NULL; end if; + when x"5" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(19) & pwm_ch_rd(18) & pwm_ch_rd(17) & pwm_ch_rd(16); else NULL; end if; + when x"6" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(23) & pwm_ch_rd(22) & pwm_ch_rd(21) & pwm_ch_rd(20); else NULL; end if; + when x"7" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(27) & pwm_ch_rd(26) & pwm_ch_rd(25) & pwm_ch_rd(24); else NULL; end if; + when x"8" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(31) & pwm_ch_rd(30) & pwm_ch_rd(29) & pwm_ch_rd(28); else NULL; end if; + when x"9" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(35) & pwm_ch_rd(34) & pwm_ch_rd(33) & pwm_ch_rd(32); else NULL; end if; + when x"a" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(39) & pwm_ch_rd(38) & pwm_ch_rd(37) & pwm_ch_rd(36); else NULL; end if; + when x"b" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(43) & pwm_ch_rd(42) & pwm_ch_rd(41) & pwm_ch_rd(40); else NULL; end if; + when x"c" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(47) & pwm_ch_rd(46) & pwm_ch_rd(45) & pwm_ch_rd(44); else NULL; end if; + when x"d" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(51) & pwm_ch_rd(50) & pwm_ch_rd(49) & pwm_ch_rd(48); else NULL; end if; + when x"e" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(55) & pwm_ch_rd(54) & pwm_ch_rd(53) & pwm_ch_rd(52); else NULL; end if; + when x"f" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(59) & pwm_ch_rd(58) & pwm_ch_rd(57) & pwm_ch_rd(56); else NULL; end if; + when others => NULL; + end case; + end if; + end if; + end process wr_access; + + -- duty cycle read-back -- + pwm_dc_rd_gen: process(pwm_ch) + begin + pwm_ch_rd <= (others => (others => '0')); + for i in 0 to NUM_CHANNELS-1 loop + pwm_ch_rd(i) <= pwm_ch(i); + end loop; + end process pwm_dc_rd_gen; + + -- PWM clock select -- + clkgen_en_o <= enable; -- enable clock generator + prsc_tick <= clkgen_i(to_integer(unsigned(prsc))); + + + -- PWM Core ------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + pwm_core: process(clk_i) + begin + if rising_edge(clk_i) then + -- pwm base counter -- + if (enable = '0') then + pwm_cnt <= (others => '0'); + elsif (prsc_tick = '1') then + pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1); + end if; + + -- channels -- + for i in 0 to NUM_CHANNELS-1 loop + if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then + pwm_o(i) <= '0'; + else + pwm_o(i) <= '1'; + end if; + end loop; + end if; + end process pwm_core; + + +end neorv32_pwm_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_slink.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_slink.vhd new file mode 100644 index 0000000..af25984 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_slink.vhd @@ -0,0 +1,439 @@ +-- ################################################################################################# +-- # << NEORV32 - Stream Link Interface (SLINK) >> # +-- # ********************************************************************************************* # +-- # Up to 8 input (RX) and up to 8 output (TX) stream links are supported. Each link provides an # +-- # internal FIFO for buffering. Each stream direction provides a global interrupt to indicate # +-- # that a RX link has received new data or that a TX link has finished sending data # +-- # (if FIFO_DEPTH = 1) OR if RX/TX link FIFO has become half full (if FIFO_DEPTH > 1). # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_slink is + generic ( + SLINK_NUM_TX : natural; -- number of TX links (0..8) + SLINK_NUM_RX : natural; -- number of TX links (0..8) + SLINK_TX_FIFO : natural; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural -- RX fifo depth, has to be a power of two + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- interrupt -- + irq_tx_o : out std_ulogic; -- transmission done + irq_rx_o : out std_ulogic; -- data received + -- TX stream interfaces -- + slink_tx_dat_o : out sdata_8x32_t; -- output data + slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_ulogic_vector(7 downto 0); -- ready to send + -- RX stream interfaces -- + slink_rx_dat_i : in sdata_8x32_t; -- input data + slink_rx_val_i : in std_ulogic_vector(7 downto 0); -- valid input + slink_rx_rdy_o : out std_ulogic_vector(7 downto 0) -- ready to receive + ); +end neorv32_slink; + +architecture neorv32_slink_rtl of neorv32_slink is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(slink_size_c); -- low address boundary bit + + -- control register bits -- + constant ctrl_rx_num_lsb_c : natural := 0; -- r/-: number of implemented RX links + constant ctrl_rx_num_msb_c : natural := 3; + -- + constant ctrl_tx_num_lsb_c : natural := 4; -- r/-: number of implemented TX links + constant ctrl_tx_num_msb_c : natural := 7; + -- + constant ctrl_rx_size_lsb_c : natural := 8; -- r/-: log2(RX FIFO size) + constant ctrl_rx_size_msb_c : natural := 11; + -- + constant ctrl_tx_size_lsb_c : natural := 12; -- r/-: log2(TX FIFO size) + constant ctrl_tx_size_msb_c : natural := 15; + -- + constant ctrl_en_c : natural := 31; -- r/w: global enable + + -- interrupt configuration register bits -- + constant irq_rx_en_lsb_c : natural := 0; -- r/w: enable RX interrupt for link 0..7 + constant irq_rx_en_msb_c : natural := 7; + -- + constant irq_rx_mode_lsb_c : natural := 8; -- r/w: RX IRQ mode: 0=FIFO at least half-full; 1=FIFO not empty + constant irq_rx_mode_msb_c : natural := 15; + -- + constant irq_tx_en_lsb_c : natural := 16; -- r/w: enable TX interrupt for link 0..7 + constant irq_tx_en_msb_c : natural := 23; + -- + constant irq_tx_mode_lsb_c : natural := 24; -- r/w: TX IRQ mode: 0=FIFO less than half-full; 1=FIFO not full + constant irq_tx_mode_msb_c : natural := 31; + + -- status register bits -- + constant status_rx_avail_lsb_c : natural := 0; -- r/-: set if RX link 0..7 FIFO is NOT empty + constant status_rx_avail_msb_c : natural := 7; + -- + constant status_tx_free_lsb_c : natural := 8; -- r/-: set if TX link 0..7 FIFO is NOT full + constant status_tx_free_msb_c : natural := 15; + -- + constant status_rx_half_lsb_c : natural := 16; -- r/-: set if RX link 0..7 FIFO fill-level is >= half-full + constant status_rx_half_msb_c : natural := 23; + -- + constant status_tx_half_lsb_c : natural := 24; -- r/-: set if TX link 0..7 FIFO fill-level is > half-full + constant status_tx_half_msb_c : natural := 31; + + -- bus access control -- + signal ack_read : std_ulogic; + signal ack_write : std_ulogic; + signal acc_en : std_ulogic; + signal addr : std_ulogic_vector(31 downto 0); + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- control register -- + signal enable : std_ulogic; -- global enable + + -- IRQ configuration register -- + signal irq_rx_en : std_ulogic_vector(7 downto 0); + signal irq_rx_mode : std_ulogic_vector(7 downto 0); + signal irq_tx_en : std_ulogic_vector(7 downto 0); + signal irq_tx_mode : std_ulogic_vector(7 downto 0); + + -- stream link fifo interface -- + type fifo_data_t is array (0 to 7) of std_ulogic_vector(31 downto 0); + signal rx_fifo_rdata : fifo_data_t; + signal fifo_clear : std_ulogic; + signal link_sel : std_ulogic_vector(7 downto 0); + signal tx_fifo_we : std_ulogic_vector(7 downto 0); + signal rx_fifo_re : std_ulogic_vector(7 downto 0); + signal rx_fifo_avail : std_ulogic_vector(7 downto 0); + signal tx_fifo_free : std_ulogic_vector(7 downto 0); + signal rx_fifo_half : std_ulogic_vector(7 downto 0); + signal tx_fifo_half : std_ulogic_vector(7 downto 0); + + -- interrupt generator -- + type detect_t is array (0 to 7) of std_ulogic_vector(1 downto 0); + type irq_t is record + detect : detect_t; -- rising-edge detector + trigger : std_ulogic_vector(7 downto 0); + set : std_ulogic_vector(7 downto 0); + end record; + signal rx_irq, tx_irq : irq_t; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (is_power_of_two_f(SLINK_TX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK has to be a power of two." severity error; + assert not (SLINK_TX_FIFO > 2**15) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK has to be 1..32768." severity error; + -- + assert not (is_power_of_two_f(SLINK_RX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK has to be a power of two." severity error; + assert not (SLINK_RX_FIFO > 2**15) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK has to be 1..32768." severity error; + -- + assert not (SLINK_NUM_RX > 8) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK has to be 0..8." severity error; + assert not (SLINK_NUM_TX > 8) report "NEORV32 PROCESSOR CONFIG ERROR: SLINK has to be 0..8." severity error; + -- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing " & integer'image(SLINK_NUM_RX) & " RX and " & + integer'image(SLINK_NUM_TX) & " TX stream links." severity note; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = slink_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= slink_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- write access -- + ack_write <= '0'; + if (wren = '1') then + if (addr(5) = '0') then -- control/status/irq + if (addr(4 downto 3) = "00") then -- control register + enable <= data_i(ctrl_en_c); + end if; + if (addr(4 downto 3) = "01") then -- IRQ configuration register + for i in 0 to SLINK_NUM_RX-1 loop + irq_rx_en(i) <= data_i(i + irq_rx_en_lsb_c); + irq_rx_mode(i) <= data_i(i + irq_rx_mode_lsb_c); + end loop; + for i in 0 to SLINK_NUM_TX-1 loop + irq_tx_en(i) <= data_i(i + irq_tx_en_lsb_c); + irq_tx_mode(i) <= data_i(i + irq_tx_mode_lsb_c); + end loop; + end if; + ack_write <= '1'; + else -- TX links + ack_write <= or_reduce_f(link_sel and tx_fifo_free); + end if; + end if; + + -- read access -- + data_o <= (others => '0'); + ack_read <= '0'; + if (rden = '1') then + if (addr(5) = '0') then -- control/status registers + ack_read <= '1'; + case addr(4 downto 3) is + when "00" => -- control register + data_o(ctrl_rx_num_msb_c downto ctrl_rx_num_lsb_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_RX, 4)); + data_o(ctrl_tx_num_msb_c downto ctrl_tx_num_lsb_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_TX, 4)); + data_o(ctrl_rx_size_msb_c downto ctrl_rx_size_lsb_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_RX_FIFO), 4)); + data_o(ctrl_tx_size_msb_c downto ctrl_tx_size_lsb_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_TX_FIFO), 4)); + data_o(ctrl_en_c) <= enable; + when "01" => -- IRQ configuration register + for i in 0 to SLINK_NUM_RX-1 loop + data_o(irq_rx_en_lsb_c + i) <= irq_rx_en(i); + data_o(irq_rx_mode_lsb_c + i) <= irq_rx_mode(i) or bool_to_ulogic_f(boolean(SLINK_RX_FIFO = 1)); -- tie to one if SLINK_RX_FIFO is 1 + end loop; + for i in 0 to SLINK_NUM_TX-1 loop + data_o(irq_tx_en_lsb_c + i) <= irq_tx_en(i); + data_o(irq_tx_mode_lsb_c + i) <= irq_tx_mode(i) or bool_to_ulogic_f(boolean(SLINK_TX_FIFO = 1)); -- tie to one if SLINK_TX_FIFO is 1 + end loop; + when "10" | "11" => -- fifo status register + data_o(status_rx_avail_msb_c downto status_rx_avail_lsb_c) <= rx_fifo_avail; + data_o(status_tx_free_msb_c downto status_tx_free_lsb_c) <= tx_fifo_free; + data_o(status_rx_half_msb_c downto status_rx_half_lsb_c) <= rx_fifo_half; + data_o(status_tx_half_msb_c downto status_tx_half_lsb_c) <= tx_fifo_half; + when others => + data_o <= (others => '0'); + end case; + else -- RX links + data_o <= rx_fifo_rdata(to_integer(unsigned(addr(4 downto 2)))); + ack_read <= or_reduce_f(link_sel and rx_fifo_avail); + end if; + end if; + end if; + end process rw_access; + + -- bus access acknowledge -- + ack_o <= ack_write or ack_read; + + -- link fifo reset (sync) -- + fifo_clear <= not enable; + + + -- Interrupt Generator -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- interrupt trigger type / condition -- + irq_type: process(irq_rx_mode, rx_fifo_avail, rx_fifo_half, irq_tx_mode, tx_fifo_free, tx_fifo_half, tx_fifo_we) + begin + -- RX interrupt -- + rx_irq.trigger <= (others => '0'); + for i in 0 to SLINK_NUM_RX-1 loop + if (SLINK_RX_FIFO = 1) or (irq_rx_mode(i) = '0') then + rx_irq.trigger(i) <= rx_fifo_avail(i); -- fire if any RX_FIFO is not empty (= data available) + else + rx_irq.trigger(i) <= rx_fifo_half(i); + end if; + end loop; + -- TX interrupt -- + tx_irq.trigger <= (others => '0'); + for i in 0 to SLINK_NUM_TX-1 loop + if (SLINK_TX_FIFO = 1) or (irq_tx_mode(i) = '0') then + tx_irq.trigger(i) <= tx_fifo_free(i) and tx_fifo_we(i); -- fire if any TX_FIFO is not full (= free buffer space available) + else + tx_irq.trigger(i) <= not tx_fifo_half(i); + end if; + end loop; + end process irq_type; + + -- edge detector - sync -- + irq_edge_detect_sync: process(clk_i) + begin + if rising_edge(clk_i) then + -- RX -- + for i in 0 to SLINK_NUM_RX-1 loop + if (enable = '1') and (irq_rx_en(i) = '1') then + rx_irq.detect(i) <= rx_irq.detect(i)(0) & rx_irq.trigger(i); + else + rx_irq.detect(i) <= "00"; + end if; + end loop; + -- TX -- + for i in 0 to SLINK_NUM_TX-1 loop + if (enable = '1') and (irq_tx_en(i) = '1') then + tx_irq.detect(i) <= tx_irq.detect(i)(0) & tx_irq.trigger(i); + else + tx_irq.detect(i) <= "00"; + end if; + end loop; + end if; + end process irq_edge_detect_sync; + + -- edge detector - sync -- + irq_edge_detect_comb: process(rx_irq, irq_rx_en, tx_irq, irq_tx_en) + begin + -- RX -- + rx_irq.set <= (others => '0'); + for i in 0 to SLINK_NUM_RX-1 loop + if (rx_irq.detect(i) = "01") then -- rising-edge + rx_irq.set(i) <= '1'; + end if; + end loop; + -- TX -- + tx_irq.set <= (others => '0'); + for i in 0 to SLINK_NUM_TX-1 loop + if (tx_irq.detect(i) = "01") then -- rising-edge + tx_irq.set(i) <= '1'; + end if; + end loop; + end process irq_edge_detect_comb; + + -- interrupt arbiter -- + irq_generator: process(clk_i) + begin + if rising_edge(clk_i) then + irq_rx_o <= or_reduce_f(rx_irq.set); + irq_tx_o <= or_reduce_f(tx_irq.set); + end if; + end process irq_generator; + + + -- Link Select ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + link_select: process(addr) + begin + case addr(5 downto 2) is -- MSB = data fifo access at all? + when "1000" => link_sel <= "00000001"; + when "1001" => link_sel <= "00000010"; + when "1010" => link_sel <= "00000100"; + when "1011" => link_sel <= "00001000"; + when "1100" => link_sel <= "00010000"; + when "1101" => link_sel <= "00100000"; + when "1110" => link_sel <= "01000000"; + when "1111" => link_sel <= "10000000"; + when others => link_sel <= "00000000"; + end case; + end process link_select; + + fifo_access_gen: + for i in 0 to 7 generate + tx_fifo_we(i) <= link_sel(i) and wren; + rx_fifo_re(i) <= link_sel(i) and rden; + end generate; + + + -- TX Link FIFOs -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + transmit_fifo_gen: + for i in 0 to SLINK_NUM_TX-1 generate + transmit_fifo_inst: neorv32_fifo + generic map ( + FIFO_DEPTH => SLINK_TX_FIFO, -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH => 32, -- size of data elements in fifo + FIFO_RSYNC => false, -- async read + FIFO_SAFE => true -- safe access + ) + port map ( + -- control -- + clk_i => clk_i, -- clock, rising edge + rstn_i => '1', -- async reset, low-active + clear_i => fifo_clear, -- sync reset, high-active + level_o => open, -- fill level + half_o => tx_fifo_half(i), -- FIFO is at least half full + -- write port -- + wdata_i => data_i, -- write data + we_i => tx_fifo_we(i), -- write enable + free_o => tx_fifo_free(i), -- at least one entry is free when set + -- read port -- + re_i => slink_tx_rdy_i(i), -- read enable + rdata_o => slink_tx_dat_o(i), -- read data + avail_o => slink_tx_val_o(i) -- data available when set + ); + end generate; + + -- terminate unimplemented links -- + transmit_fifo_gen_terminate: + for i in SLINK_NUM_TX to 7 generate + tx_fifo_free(i) <= '0'; + slink_tx_dat_o(i) <= (others => '0'); + slink_tx_val_o(i) <= '0'; + tx_fifo_half(i) <= '0'; + end generate; + + + -- RX Link FIFOs -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + receive_fifo_gen: + for i in 0 to SLINK_NUM_RX-1 generate + receive_fifo_inst: neorv32_fifo + generic map ( + FIFO_DEPTH => SLINK_RX_FIFO, -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH => 32, -- size of data elements in fifo + FIFO_RSYNC => false, -- async read + FIFO_SAFE => true -- safe access + ) + port map ( + -- control -- + clk_i => clk_i, -- clock, rising edge + rstn_i => '1', -- async reset, low-active + clear_i => fifo_clear, -- sync reset, high-active + level_o => open, -- fill level + half_o => rx_fifo_half(i), -- FIFO is at least half full + -- write port -- + wdata_i => slink_rx_dat_i(i), -- write data + we_i => slink_rx_val_i(i), -- write enable + free_o => slink_rx_rdy_o(i), -- at least one entry is free when set + -- read port -- + re_i => rx_fifo_re(i), -- read enable + rdata_o => rx_fifo_rdata(i), -- read data + avail_o => rx_fifo_avail(i) -- data available when set + ); + end generate; + + -- terminate unimplemented links -- + receive_fifo_gen_terminate: + for i in SLINK_NUM_RX to 7 generate + rx_fifo_avail(i) <= '0'; + slink_rx_rdy_o(i) <= '0'; + rx_fifo_rdata(i) <= (others => '0'); + rx_fifo_half(i) <= '0'; + end generate; + + +end neorv32_slink_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_spi.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_spi.vhd new file mode 100644 index 0000000..1f9e4e1 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_spi.vhd @@ -0,0 +1,287 @@ +-- ################################################################################################# +-- # << NEORV32 - Serial Peripheral Interface Controller (SPI) >> # +-- # ********************************************************************************************* # +-- # Frame format: 8/16/24/32-bit receive/transmit data, always MSB first, 2 clock modes, # +-- # 8 pre-scaled clocks (derived from system clock), 8 dedicated chip-select lines (low-active). # +-- # Interrupt: "transfer done" # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_spi is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- com lines -- + spi_sck_o : out std_ulogic; -- SPI serial clock + spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in + spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out + spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS + -- interrupt -- + irq_o : out std_ulogic -- transmission done interrupt + ); +end neorv32_spi; + +architecture neorv32_spi_rtl of neorv32_spi is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(spi_size_c); -- low address boundary bit + + -- control register -- + constant ctrl_cs0_c : natural := 0; -- r/w: spi CS 0 + constant ctrl_cs1_c : natural := 1; -- r/w: spi CS 1 + constant ctrl_cs2_c : natural := 2; -- r/w: spi CS 2 + constant ctrl_cs3_c : natural := 3; -- r/w: spi CS 3 + constant ctrl_cs4_c : natural := 4; -- r/w: spi CS 4 + constant ctrl_cs5_c : natural := 5; -- r/w: spi CS 5 + constant ctrl_cs6_c : natural := 6; -- r/w: spi CS 6 + constant ctrl_cs7_c : natural := 7; -- r/w: spi CS 7 + -- + constant ctrl_en_c : natural := 8; -- r/w: spi enable + constant ctrl_cpha_c : natural := 9; -- r/w: spi clock phase + constant ctrl_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0 + constant ctrl_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1 + constant ctrl_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2 + constant ctrl_size0_c : natural := 13; -- r/w: data size lsb (00: 8-bit, 01: 16-bit) + constant ctrl_size1_c : natural := 14; -- r/w: data size msb (10: 24-bit, 11: 32-bit) + constant ctrl_cpol_c : natural := 15; -- r/w: spi clock polarity + -- + constant ctrl_busy_c : natural := 31; -- r/-: spi transceiver is busy + -- + signal ctrl : std_ulogic_vector(15 downto 0); + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- clock generator -- + signal spi_clk_en : std_ulogic; + + -- spi transceiver -- + type rtx_engine_t is record + state : std_ulogic_vector(02 downto 0); + busy : std_ulogic; + start : std_ulogic; + sreg : std_ulogic_vector(31 downto 0); + bitcnt : std_ulogic_vector(05 downto 0); + bytecnt : std_ulogic_vector(02 downto 0); + sdi_sync : std_ulogic_vector(01 downto 0); + end record; + signal rtx_engine : rtx_engine_t; + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = spi_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= spi_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- bus access acknowledge -- + ack_o <= rden or wren; + + -- write access -- + if (wren = '1') then + if (addr = spi_ctrl_addr_c) then -- control register + ctrl(ctrl_cs0_c) <= data_i(ctrl_cs0_c); + ctrl(ctrl_cs1_c) <= data_i(ctrl_cs1_c); + ctrl(ctrl_cs2_c) <= data_i(ctrl_cs2_c); + ctrl(ctrl_cs3_c) <= data_i(ctrl_cs3_c); + ctrl(ctrl_cs4_c) <= data_i(ctrl_cs4_c); + ctrl(ctrl_cs5_c) <= data_i(ctrl_cs5_c); + ctrl(ctrl_cs6_c) <= data_i(ctrl_cs6_c); + ctrl(ctrl_cs7_c) <= data_i(ctrl_cs7_c); + -- + ctrl(ctrl_en_c) <= data_i(ctrl_en_c); + ctrl(ctrl_cpha_c) <= data_i(ctrl_cpha_c); + ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c); + ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c); + ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c); + ctrl(ctrl_size0_c) <= data_i(ctrl_size0_c); + ctrl(ctrl_size1_c) <= data_i(ctrl_size1_c); + ctrl(ctrl_cpol_c) <= data_i(ctrl_cpol_c); + end if; + end if; + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + if (addr = spi_ctrl_addr_c) then -- control register + data_o(ctrl_cs0_c) <= ctrl(ctrl_cs0_c); + data_o(ctrl_cs1_c) <= ctrl(ctrl_cs1_c); + data_o(ctrl_cs2_c) <= ctrl(ctrl_cs2_c); + data_o(ctrl_cs3_c) <= ctrl(ctrl_cs3_c); + data_o(ctrl_cs4_c) <= ctrl(ctrl_cs4_c); + data_o(ctrl_cs5_c) <= ctrl(ctrl_cs5_c); + data_o(ctrl_cs6_c) <= ctrl(ctrl_cs6_c); + data_o(ctrl_cs7_c) <= ctrl(ctrl_cs7_c); + -- + data_o(ctrl_en_c) <= ctrl(ctrl_en_c); + data_o(ctrl_cpha_c) <= ctrl(ctrl_cpha_c); + data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c); + data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c); + data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c); + data_o(ctrl_size0_c) <= ctrl(ctrl_size0_c); + data_o(ctrl_size1_c) <= ctrl(ctrl_size1_c); + data_o(ctrl_cpol_c) <= ctrl(ctrl_cpol_c); + -- + data_o(ctrl_busy_c) <= rtx_engine.busy; + else -- data register (spi_rtx_addr_c) + data_o <= rtx_engine.sreg; + end if; + end if; + end if; + end process rw_access; + + -- direct chip-select (CS), output is low-active -- + spi_csn_o(7 downto 0) <= not ctrl(ctrl_cs7_c downto ctrl_cs0_c); + + -- trigger new SPI transmission -- + rtx_engine.start <= '1' when (wren = '1') and (addr = spi_rtx_addr_c) else '0'; + + + -- Clock Selection ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + clkgen_en_o <= ctrl(ctrl_en_c); -- clock generator enable + spi_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c)))); -- clock select + + + -- Transmission Data Size ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + data_size: process(ctrl) + begin + case ctrl(ctrl_size1_c downto ctrl_size0_c) is + when "00" => rtx_engine.bytecnt <= "001"; -- 1-byte mode + when "01" => rtx_engine.bytecnt <= "010"; -- 2-byte mode + when "10" => rtx_engine.bytecnt <= "011"; -- 3-byte mode + when others => rtx_engine.bytecnt <= "100"; -- 4-byte mode + end case; + end process data_size; + + + -- SPI Transceiver ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + spi_rtx_unit: process(clk_i) + begin + if rising_edge(clk_i) then + -- input (sdi) synchronizer -- + rtx_engine.sdi_sync <= rtx_engine.sdi_sync(0) & spi_sdi_i; + + -- output (sdo) buffer -- + case ctrl(ctrl_size1_c downto ctrl_size0_c) is + when "00" => spi_sdo_o <= rtx_engine.sreg(07); -- 8-bit mode + when "01" => spi_sdo_o <= rtx_engine.sreg(15); -- 16-bit mode + when "10" => spi_sdo_o <= rtx_engine.sreg(23); -- 24-bit mode + when others => spi_sdo_o <= rtx_engine.sreg(31); -- 32-bit mode + end case; + + -- defaults -- + spi_sck_o <= ctrl(ctrl_cpol_c); + irq_o <= '0'; + + -- serial engine -- + rtx_engine.state(2) <= ctrl(ctrl_en_c); + case rtx_engine.state is + + when "100" => -- enabled but idle, waiting for new transmission trigger + -- ------------------------------------------------------------ + rtx_engine.bitcnt <= (others => '0'); + if (rtx_engine.start = '1') then -- trigger new transmission + rtx_engine.sreg <= data_i; + rtx_engine.state(1 downto 0) <= "01"; + end if; + + when "101" => -- start with next new clock pulse + -- ------------------------------------------------------------ + if (spi_clk_en = '1') then + rtx_engine.state(1 downto 0) <= "10"; + end if; + + when "110" => -- first half of bit transmission + -- ------------------------------------------------------------ + spi_sck_o <= ctrl(ctrl_cpha_c) xor ctrl(ctrl_cpol_c); + if (spi_clk_en = '1') then + rtx_engine.bitcnt <= std_ulogic_vector(unsigned(rtx_engine.bitcnt) + 1); + rtx_engine.state(1 downto 0) <= "11"; + end if; + + when "111" => -- second half of bit transmission + -- ------------------------------------------------------------ + spi_sck_o <= ctrl(ctrl_cpha_c) xnor ctrl(ctrl_cpol_c); + if (spi_clk_en = '1') then + rtx_engine.sreg <= rtx_engine.sreg(30 downto 0) & rtx_engine.sdi_sync(rtx_engine.sdi_sync'left); + if (rtx_engine.bitcnt(5 downto 3) = rtx_engine.bytecnt) then -- all bits transferred? + irq_o <= '1'; -- interrupt! + rtx_engine.state(1 downto 0) <= "00"; -- transmission done + else + rtx_engine.state(1 downto 0) <= "10"; + end if; + end if; + + when others => -- "0--": SPI deactivated + -- ------------------------------------------------------------ + rtx_engine.state(1 downto 0) <= "00"; + + end case; + end if; + end process spi_rtx_unit; + + -- busy flag -- + rtx_engine.busy <= '0' when (rtx_engine.state(1 downto 0) = "00") else '1'; + + +end neorv32_spi_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_sysinfo.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_sysinfo.vhd new file mode 100644 index 0000000..a849a9c --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_sysinfo.vhd @@ -0,0 +1,227 @@ +-- ################################################################################################# +-- # << NEORV32 - System/Processor Configuration Information Memory (SYSINFO) >> # +-- # ********************************************************************************************* # +-- # This unit provides information regarding the NEORV32 processor system configuration - # +-- # mostly derived from the top's configuration generics. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_sysinfo is + generic ( + -- General -- + CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode? + -- Extension Options -- + FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64) + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS : natural; -- number of regions (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN : boolean; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2 + -- External memory interface -- + MEM_EXT_EN : boolean; -- implement external memory bus interface? + MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian + -- On-Chip Debugger -- + ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? + -- Processor peripherals -- + IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural; -- number of PWM channels to implement + IO_WDT_EN : boolean; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)? + IO_SLINK_EN : boolean; -- implement stream link interface? + IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement + IO_GPTMR_EN : boolean -- implement general purpose timer (GPTMR)? + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); +end neorv32_sysinfo; + +architecture neorv32_sysinfo_rtl of neorv32_sysinfo is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + signal info_addr : std_ulogic_vector(02 downto 0); + + -- system information ROM -- + type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0); + signal sysinfo_mem : info_mem_t; + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0'; + rden <= acc_en and rden_i; -- valid read access + addr <= sysinfo_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + info_addr <= addr(index_size_f(sysinfo_size_c)-1 downto 2); + + + -- Construct Info ROM --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- SYSINFO(0): Processor (primary) clock frequency -- + sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); + + -- SYSINFO(1): CPU configuration -- + sysinfo_mem(1)(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr + sysinfo_mem(1)(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei + sysinfo_mem(1)(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul + -- + sysinfo_mem(1)(04 downto 03) <= (others => '0'); -- reserved + -- + sysinfo_mem(1)(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx ("F-alternative") + sysinfo_mem(1)(06) <= bool_to_ulogic_f(boolean(CPU_CNT_WIDTH /= 64)); -- reduced-size CPU counters (Zxscnt) + sysinfo_mem(1)(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- base CPU counter + sysinfo_mem(1)(08) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP (physical memory protection) + sysinfo_mem(1)(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- HPM (hardware performance monitors) + sysinfo_mem(1)(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- RISC-V debug mode + -- + sysinfo_mem(1)(29 downto 11) <= (others => '0'); -- reserved + -- misc -- + sysinfo_mem(1)(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extension only) + sysinfo_mem(1)(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (like barrel shifters) + + -- SYSINFO(2): Implemented processor devices/features -- + -- Memory -- + sysinfo_mem(2)(00) <= bool_to_ulogic_f(INT_BOOTLOADER_EN); -- processor-internal bootloader implemented? + sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_EN); -- external memory bus interface implemented? + sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_EN) and bool_to_ulogic_f(boolean(MEM_INT_IMEM_SIZE > 0)); -- processor-internal instruction memory implemented? + sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_DMEM_EN) and bool_to_ulogic_f(boolean(MEM_INT_DMEM_SIZE > 0)); -- processor-internal data memory implemented? + sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_EXT_BIG_ENDIAN); -- is external memory bus interface using BIG-endian byte-order? + sysinfo_mem(2)(05) <= bool_to_ulogic_f(ICACHE_EN); -- processor-internal instruction cache implemented? + -- + sysinfo_mem(2)(12 downto 06) <= (others => '0'); -- reserved + -- Misc -- + sysinfo_mem(2)(13) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation? + sysinfo_mem(2)(14) <= bool_to_ulogic_f(ON_CHIP_DEBUGGER_EN); -- on-chip debugger implemented? + sysinfo_mem(2)(15) <= bool_to_ulogic_f(dedicated_reset_c); -- dedicated hardware reset of all core registers? + -- IO -- + sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN); -- general purpose input/output port unit (GPIO) implemented? + sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented? + sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART0_EN); -- primary universal asynchronous receiver/transmitter (UART0) implemented? + sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented? + sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented? + sysinfo_mem(2)(21) <= bool_to_ulogic_f(boolean(IO_PWM_NUM_CH > 0)); -- pulse-width modulation unit (PWM) implemented? + sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented? + sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented? + sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented? + sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_SLINK_EN); -- stream links (SLINK) implemented? + sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented? + sysinfo_mem(2)(27) <= bool_to_ulogic_f(IO_NEOLED_EN); -- NeoPixel-compatible smart LED interface (NEOLED) implemented? + sysinfo_mem(2)(28) <= bool_to_ulogic_f(boolean(IO_XIRQ_NUM_CH > 0)); -- external interrupt controller (XIRQ) implemented? + sysinfo_mem(2)(29) <= bool_to_ulogic_f(IO_GPTMR_EN); -- general purpose timer (GPTMR) implemented? + -- + sysinfo_mem(2)(31 downto 30) <= (others => '0'); -- reserved + + -- SYSINFO(3): Cache configuration -- + sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes) + sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(number_of_block) + sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(associativity) + sysinfo_mem(3)(15 downto 12) <= "0001" when (ICACHE_ASSOCIATIVITY > 1) and (ICACHE_EN = true) else (others => '0'); -- i-cache: replacement strategy (LRU only (yet)) + -- + sysinfo_mem(3)(19 downto 16) <= (others => '0'); -- reserved - d-cache: log2(block_size) + sysinfo_mem(3)(23 downto 20) <= (others => '0'); -- reserved - d-cache: log2(num_blocks) + sysinfo_mem(3)(27 downto 24) <= (others => '0'); -- reserved - d-cache: log2(associativity) + sysinfo_mem(3)(31 downto 28) <= (others => '0'); -- reserved - d-cache: replacement strategy + + -- SYSINFO(4): Base address of instruction memory space -- + sysinfo_mem(4) <= ispace_base_c; -- defined in neorv32_package.vhd file + + -- SYSINFO(5): Base address of data memory space -- + sysinfo_mem(5) <= dspace_base_c; -- defined in neorv32_package.vhd file + + -- SYSINFO(6): Size of IMEM in bytes -- + sysinfo_mem(6) <= std_ulogic_vector(to_unsigned(MEM_INT_IMEM_SIZE, 32)) when (MEM_INT_IMEM_EN = true) else (others => '0'); + + -- SYSINFO(7): Size of DMEM in bytes -- + sysinfo_mem(7) <= std_ulogic_vector(to_unsigned(MEM_INT_DMEM_SIZE, 32)) when (MEM_INT_DMEM_EN = true) else (others => '0'); + + + -- Read Access ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + read_access: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= rden; + data_o <= (others => '0'); + if (rden = '1') then + data_o <= sysinfo_mem(to_integer(unsigned(info_addr))); + end if; + end if; + end process read_access; + + +end neorv32_sysinfo_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_top.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_top.vhd new file mode 100644 index 0000000..868cec2 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_top.vhd @@ -0,0 +1,1563 @@ +-- ################################################################################################# +-- # << The NEORV32 RISC-V Processor - Top Entity >> # +-- # ********************************************************************************************* # +-- # Check out the processor's online documentation for more information: # +-- # HQ: https://github.com/stnolting/neorv32 # +-- # Data Sheet: https://stnolting.github.io/neorv32 # +-- # User Guide: https://stnolting.github.io/neorv32/ug # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_top is + generic ( + -- General -- + CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? + + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2 + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory (IMEM) -- + MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory (DMEM) -- + MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes + + -- Internal Cache memory (iCACHE) -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- External memory interface (WISHBONE) -- + MEM_EXT_EN : boolean := false; -- implement external memory bus interface? + MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled) + MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian + MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false + + -- Stream link interface (SLINK) -- + SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) + SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) + SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two + + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + + -- Processor peripherals -- + IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic + IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits + IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional) + jtag_tck_i : in std_ulogic := 'U'; -- serial clock + jtag_tdi_i : in std_ulogic := 'U'; -- serial data input + jtag_tdo_o : out std_ulogic; -- serial data output + jtag_tms_i : in std_ulogic := 'U'; -- mode select + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag + wb_adr_o : out std_ulogic_vector(31 downto 0); -- address + wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data + wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data + wb_we_o : out std_ulogic; -- read/write + wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable + wb_stb_o : out std_ulogic; -- strobe + wb_cyc_o : out std_ulogic; -- valid cycle + wb_lock_o : out std_ulogic; -- exclusive access request + wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge + wb_err_i : in std_ulogic := 'L'; -- transfer error + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o : out std_ulogic; -- indicates an executed FENCE operation + fencei_o : out std_ulogic; -- indicates an executed FENCEI operation + + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o : out sdata_8x32_t; -- output data + slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send + + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data + slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input + slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output + gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data + uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o : out std_ulogic; -- UART1 send data + uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data + uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_ulogic; -- SPI serial clock + spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in + spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic := 'U'; -- twi serial data line + twi_scl_io : inout std_logic := 'U'; -- twi serial clock line + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels + + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit + cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o : out std_ulogic; -- async serial data line + + -- System time -- + mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) + + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels + + -- CPU interrupts -- + mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt + mext_irq_i : in std_ulogic := 'L' -- machine external interrupt + ); +end neorv32_top; + +architecture neorv32_top_rtl of neorv32_top is + + -- CPU boot configuration -- + constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(INT_BOOTLOADER_EN, boot_rom_base_c, ispace_base_c); + + -- alignment check for internal memories -- + constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0'); + constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0'); + + -- helpers -- + constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all? + + -- reset generator -- + signal rstn_gen : std_ulogic_vector(7 downto 0) := (others => '0'); -- initialize (=reset) via (for FPGAs only) + signal ext_rstn : std_ulogic; + signal sys_rstn : std_ulogic; + signal wdt_rstn : std_ulogic; + + -- clock generator -- + signal clk_div : std_ulogic_vector(11 downto 0); + signal clk_div_ff : std_ulogic_vector(11 downto 0); + signal clk_gen : std_ulogic_vector(07 downto 0); + signal clk_gen_en : std_ulogic_vector(08 downto 0); + -- + signal wdt_cg_en : std_ulogic; + signal uart0_cg_en : std_ulogic; + signal uart1_cg_en : std_ulogic; + signal spi_cg_en : std_ulogic; + signal twi_cg_en : std_ulogic; + signal pwm_cg_en : std_ulogic; + signal cfs_cg_en : std_ulogic; + signal neoled_cg_en : std_ulogic; + signal gptmr_cg_en : std_ulogic; + + -- bus interface -- + type bus_interface_t is record + addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address + rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data + wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data + ben : std_ulogic_vector(03 downto 0); -- byte enable + we : std_ulogic; -- write enable + re : std_ulogic; -- read enable + ack : std_ulogic; -- bus transfer acknowledge + err : std_ulogic; -- bus transfer error + fence : std_ulogic; -- fence(i) instruction executed + priv : std_ulogic_vector(1 downto 0); -- current privilege level + src : std_ulogic; -- access source (1=instruction fetch, 0=data access) + lock : std_ulogic; -- exclusive access request + end record; + signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t; + + -- bus access error (from BUSKEEPER) -- + signal bus_error : std_ulogic; + + -- debug core interface (DCI) -- + signal dci_ndmrstn : std_ulogic; + signal dci_halt_req : std_ulogic; + + -- debug module interface (DMI) -- + type dmi_t is record + rstn : std_ulogic; + req_valid : std_ulogic; + req_ready : std_ulogic; -- DMI is allowed to make new requests when set + req_addr : std_ulogic_vector(06 downto 0); + req_op : std_ulogic; -- 0=read, 1=write + req_data : std_ulogic_vector(31 downto 0); + resp_valid : std_ulogic; -- response valid when set + resp_ready : std_ulogic; -- ready to receive respond + resp_data : std_ulogic_vector(31 downto 0); + resp_err : std_ulogic; -- 0=ok, 1=error + end record; + signal dmi : dmi_t; + + -- io space access -- + signal io_acc : std_ulogic; + signal io_rden : std_ulogic; + signal io_wren : std_ulogic; + + -- module response bus - entry type -- + type resp_bus_entry_t is record + rdata : std_ulogic_vector(data_width_c-1 downto 0); + ack : std_ulogic; + err : std_ulogic; + end record; + constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0'); + + -- module response bus - device ID -- + type resp_bus_id_t is (RESP_BUSKEEPER, RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI, + RESP_TWI, RESP_PWM, RESP_WDT, RESP_TRNG, RESP_CFS, RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ, RESP_GPTMR); + + -- module response bus -- + type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t; + signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c); + + -- IRQs -- + signal fast_irq : std_ulogic_vector(15 downto 0); + signal mtime_irq : std_ulogic; + signal wdt_irq : std_ulogic; + signal uart0_rxd_irq : std_ulogic; + signal uart0_txd_irq : std_ulogic; + signal uart1_rxd_irq : std_ulogic; + signal uart1_txd_irq : std_ulogic; + signal spi_irq : std_ulogic; + signal twi_irq : std_ulogic; + signal cfs_irq : std_ulogic; + signal neoled_irq : std_ulogic; + signal slink_tx_irq : std_ulogic; + signal slink_rx_irq : std_ulogic; + signal xirq_irq : std_ulogic; + signal gptmr_irq : std_ulogic; + + -- misc -- + signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME + signal ext_timeout : std_ulogic; + signal ext_access : std_ulogic; + signal debug_mode : std_ulogic; + +begin + + -- Processor IO/Peripherals Configuration ------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report + "NEORV32 PROCESSOR IO Configuration: " & + cond_sel_string_f(IO_GPIO_EN, "GPIO ", "") & + cond_sel_string_f(IO_MTIME_EN, "MTIME ", "") & + cond_sel_string_f(IO_UART0_EN, "UART0 ", "") & + cond_sel_string_f(IO_UART1_EN, "UART1 ", "") & + cond_sel_string_f(IO_SPI_EN, "SPI ", "") & + cond_sel_string_f(IO_TWI_EN, "TWI ", "") & + cond_sel_string_f(boolean(IO_PWM_NUM_CH > 0), "PWM ", "") & + cond_sel_string_f(IO_WDT_EN, "WDT ", "") & + cond_sel_string_f(IO_TRNG_EN, "TRNG ", "") & + cond_sel_string_f(IO_CFS_EN, "CFS ", "") & + cond_sel_string_f(io_slink_en_c, "SLINK ", "") & + cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") & + cond_sel_string_f(boolean(XIRQ_NUM_CH > 0), "XIRQ ", "") & + cond_sel_string_f(IO_GPTMR_EN, "GPTMR ", "") & + "" + severity note; + + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- boot configuration -- + assert not (INT_BOOTLOADER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note; + assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-internal IMEM)." severity note; + assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Direct boot from memory (processor-external (I)MEM)." severity note; + -- + assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal IMEM." severity error; + assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (INT_BOOTLOADER_EN = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal IMEM and bootloader." severity error; + + -- memory system - size -- + assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning; + assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning; + + -- memory system - alignment -- + assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error; + assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error; + assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error; + assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error; + + -- memory system - layout warning -- + assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning; + assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning; + + -- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only -- + assert not ((ICACHE_EN = true) and (MEM_EXT_EN = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note; + + -- on-chip debugger -- + assert not (ON_CHIP_DEBUGGER_EN = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing on-chip debugger (OCD)." severity note; + + + -- Reset Generator ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + reset_generator: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + rstn_gen <= (others => '0'); + sys_rstn <= '0'; + elsif rising_edge(clk_i) then + -- keep internal reset active for at least clock cycles -- + rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1'; + -- system reset: can also be triggered by watchdog and debug module -- + sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn; + end if; + end process reset_generator; + + -- beautified external reset signal -- + ext_rstn <= rstn_gen(rstn_gen'left); + + + -- Clock Generator ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + clock_generator: process(sys_rstn, clk_i) + begin + if (sys_rstn = '0') then + clk_gen_en <= (others => '-'); + clk_div <= (others => '0'); + clk_div_ff <= (others => '-'); + clk_gen <= (others => '-'); + elsif rising_edge(clk_i) then + -- fresh clocks anyone? -- + clk_gen_en(0) <= wdt_cg_en; + clk_gen_en(1) <= uart0_cg_en; + clk_gen_en(2) <= uart1_cg_en; + clk_gen_en(3) <= spi_cg_en; + clk_gen_en(4) <= twi_cg_en; + clk_gen_en(5) <= pwm_cg_en; + clk_gen_en(6) <= cfs_cg_en; + clk_gen_en(7) <= neoled_cg_en; + clk_gen_en(8) <= gptmr_cg_en; + -- actual clock generator -- + if (or_reduce_f(clk_gen_en) = '1') then + clk_div <= std_ulogic_vector(unsigned(clk_div) + 1); + end if; + -- clock enables: rising edge detectors -- + clk_div_ff <= clk_div; + clk_gen(clk_div2_c) <= clk_div(0) and (not clk_div_ff(0)); -- CLK/2 + clk_gen(clk_div4_c) <= clk_div(1) and (not clk_div_ff(1)); -- CLK/4 + clk_gen(clk_div8_c) <= clk_div(2) and (not clk_div_ff(2)); -- CLK/8 + clk_gen(clk_div64_c) <= clk_div(5) and (not clk_div_ff(5)); -- CLK/64 + clk_gen(clk_div128_c) <= clk_div(6) and (not clk_div_ff(6)); -- CLK/128 + clk_gen(clk_div1024_c) <= clk_div(9) and (not clk_div_ff(9)); -- CLK/1024 + clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048 + clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096 + end if; + end process clock_generator; + + + -- CPU Core ------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_inst: neorv32_cpu + generic map ( + -- General -- + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id + CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address + CPU_DEBUG_ADDR => dm_base_c, -- cpu debug mode start address + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode? + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64) + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => sys_rstn, -- global reset, low-active, async + sleep_o => open, -- cpu is in sleep mode when set + debug_o => debug_mode, -- cpu is in debug mode when set + -- instruction bus interface -- + i_bus_addr_o => cpu_i.addr, -- bus access address + i_bus_rdata_i => cpu_i.rdata, -- bus read data + i_bus_wdata_o => cpu_i.wdata, -- bus write data + i_bus_ben_o => cpu_i.ben, -- byte enable + i_bus_we_o => cpu_i.we, -- write enable + i_bus_re_o => cpu_i.re, -- read enable + i_bus_lock_o => cpu_i.lock, -- exclusive access request + i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge + i_bus_err_i => cpu_i.err, -- bus transfer error + i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation + i_bus_priv_o => cpu_i.priv, -- privilege level + -- data bus interface -- + d_bus_addr_o => cpu_d.addr, -- bus access address + d_bus_rdata_i => cpu_d.rdata, -- bus read data + d_bus_wdata_o => cpu_d.wdata, -- bus write data + d_bus_ben_o => cpu_d.ben, -- byte enable + d_bus_we_o => cpu_d.we, -- write enable + d_bus_re_o => cpu_d.re, -- read enable + d_bus_lock_o => cpu_d.lock, -- exclusive access request + d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge + d_bus_err_i => cpu_d.err, -- bus transfer error + d_bus_fence_o => cpu_d.fence, -- executed FENCE operation + d_bus_priv_o => cpu_d.priv, -- privilege level + -- system time input from MTIME -- + time_i => mtime_time, -- current system time + -- non-maskable interrupt -- + msw_irq_i => msw_irq_i, -- machine software interrupt + mext_irq_i => mext_irq_i, -- machine external interrupt request + mtime_irq_i => mtime_irq, -- machine timer interrupt + -- fast interrupts (custom) -- + firq_i => fast_irq, -- fast interrupt trigger + -- debug mode (halt) request -- + db_halt_req_i => dci_halt_req + ); + + -- misc -- + cpu_i.src <= '1'; -- initialized but unused + cpu_d.src <= '0'; -- initialized but unused + + -- advanced memory control -- + fence_o <= cpu_d.fence; -- indicates an executed FENCE operation + fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation + + -- fast interrupt requests (FIRQs) -- + -- these signals are single-shot -- + fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog + fast_irq(01) <= cfs_irq; -- custom functions subsystem + fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX + fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX + fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX + fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX + fast_irq(06) <= spi_irq; -- SPI + fast_irq(07) <= twi_irq; -- TWI + fast_irq(08) <= xirq_irq; -- external interrupt controller + fast_irq(09) <= neoled_irq; -- NEOLED buffer free + fast_irq(10) <= slink_rx_irq; -- SLINK RX + fast_irq(11) <= slink_tx_irq; -- SLINK TX + fast_irq(12) <= gptmr_irq; -- general purpose timer + -- + fast_irq(13) <= '0'; -- reserved + fast_irq(14) <= '0'; -- reserved + fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved + + + -- CPU Instruction Cache ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_icache_inst_true: + if (ICACHE_EN = true) generate + neorv32_icache_inst: neorv32_icache + generic map ( + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 + ICACHE_NUM_SETS => ICACHE_ASSOCIATIVITY -- associativity / number of sets (1=direct_mapped), has to be a power of 2 + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => sys_rstn, -- global reset, low-active, async + clear_i => cpu_i.fence, -- cache clear + -- host controller interface -- + host_addr_i => cpu_i.addr, -- bus access address + host_rdata_o => cpu_i.rdata, -- bus read data + host_wdata_i => cpu_i.wdata, -- bus write data + host_ben_i => cpu_i.ben, -- byte enable + host_we_i => cpu_i.we, -- write enable + host_re_i => cpu_i.re, -- read enable + host_ack_o => cpu_i.ack, -- bus transfer acknowledge + host_err_o => cpu_i.err, -- bus transfer error + -- peripheral bus interface -- + bus_addr_o => i_cache.addr, -- bus access address + bus_rdata_i => i_cache.rdata, -- bus read data + bus_wdata_o => i_cache.wdata, -- bus write data + bus_ben_o => i_cache.ben, -- byte enable + bus_we_o => i_cache.we, -- write enable + bus_re_o => i_cache.re, -- read enable + bus_ack_i => i_cache.ack, -- bus transfer acknowledge + bus_err_i => i_cache.err -- bus transfer error + ); + end generate; + + -- TODO: do not use LOCKED instruction fetch -- + i_cache.lock <= '0'; + + neorv32_icache_inst_false: + if (ICACHE_EN = false) generate + i_cache.addr <= cpu_i.addr; + cpu_i.rdata <= i_cache.rdata; + i_cache.wdata <= cpu_i.wdata; + i_cache.ben <= cpu_i.ben; + i_cache.we <= cpu_i.we; + i_cache.re <= cpu_i.re; + cpu_i.ack <= i_cache.ack; + cpu_i.err <= i_cache.err; + end generate; + + + -- CPU Bus Switch ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_busswitch_inst: neorv32_busswitch + generic map ( + PORT_CA_READ_ONLY => false, -- set if controller port A is read-only + PORT_CB_READ_ONLY => true -- set if controller port B is read-only + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => sys_rstn, -- global reset, low-active, async + -- controller interface a -- + ca_bus_addr_i => cpu_d.addr, -- bus access address + ca_bus_rdata_o => cpu_d.rdata, -- bus read data + ca_bus_wdata_i => cpu_d.wdata, -- bus write data + ca_bus_ben_i => cpu_d.ben, -- byte enable + ca_bus_we_i => cpu_d.we, -- write enable + ca_bus_re_i => cpu_d.re, -- read enable + ca_bus_lock_i => cpu_d.lock, -- exclusive access request + ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge + ca_bus_err_o => cpu_d.err, -- bus transfer error + -- controller interface b -- + cb_bus_addr_i => i_cache.addr, -- bus access address + cb_bus_rdata_o => i_cache.rdata, -- bus read data + cb_bus_wdata_i => i_cache.wdata, -- bus write data + cb_bus_ben_i => i_cache.ben, -- byte enable + cb_bus_we_i => i_cache.we, -- write enable + cb_bus_re_i => i_cache.re, -- read enable + cb_bus_lock_i => i_cache.lock, -- exclusive access request + cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge + cb_bus_err_o => i_cache.err, -- bus transfer error + -- peripheral bus -- + p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions) + p_bus_addr_o => p_bus.addr, -- bus access address + p_bus_rdata_i => p_bus.rdata, -- bus read data + p_bus_wdata_o => p_bus.wdata, -- bus write data + p_bus_ben_o => p_bus.ben, -- byte enable + p_bus_we_o => p_bus.we, -- write enable + p_bus_re_o => p_bus.re, -- read enable + p_bus_lock_o => p_bus.lock, -- exclusive access request + p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge + p_bus_err_i => bus_error -- bus transfer error + ); + + -- current CPU privilege level -- + p_bus.priv <= cpu_i.priv; -- note: cpu_i.priv == cpu_d.priv + + -- fence operation (unused) -- + p_bus.fence <= cpu_d.fence or cpu_i.fence; + + -- bus response -- + bus_response: process(resp_bus) + variable rdata_v : std_ulogic_vector(data_width_c-1 downto 0); + variable ack_v : std_ulogic; + variable err_v : std_ulogic; + begin + rdata_v := (others => '0'); + ack_v := '0'; + err_v := '0'; + for i in resp_bus'range loop + rdata_v := rdata_v or resp_bus(i).rdata; -- read data + ack_v := ack_v or resp_bus(i).ack; -- acknowledge + err_v := err_v or resp_bus(i).err; -- error + end loop; -- i + p_bus.rdata <= rdata_v; -- processor bus: CPU transfer data input + p_bus.ack <= ack_v; -- processor bus: CPU transfer ACK input + p_bus.err <= err_v; -- processor bus: CPU transfer data bus error input + end process; + + + -- Bus Keeper (BUSKEEPER) ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_bus_keeper_inst: neorv32_bus_keeper + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => sys_rstn, -- global reset line, low-active, use as async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- byte write enable + data_o => resp_bus(RESP_BUSKEEPER).rdata, -- data out + ack_o => resp_bus(RESP_BUSKEEPER).ack, -- transfer acknowledge + err_o => bus_error, -- transfer error + -- bus monitoring -- + bus_addr_i => p_bus.addr, -- address + bus_rden_i => p_bus.re, -- read enable + bus_wren_i => p_bus.we, -- write enable + bus_ack_i => p_bus.ack, -- transfer acknowledge from bus system + bus_err_i => p_bus.err, -- transfer error from bus system + bus_tmo_i => ext_timeout, -- transfer timeout (external interface) + bus_ext_i => ext_access -- external bus access + ); + + -- unused, BUSKEEPER **directly** issues error to the CPU -- + resp_bus(RESP_BUSKEEPER).err <= '0'; + + + -- Processor-Internal Instruction Memory (IMEM) ------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_int_imem_inst_true: + if (MEM_INT_IMEM_EN = true) and (MEM_INT_IMEM_SIZE > 0) generate + neorv32_int_imem_inst: neorv32_imem + generic map ( + IMEM_BASE => imem_base_c, -- memory base address + IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes + IMEM_AS_IROM => not INT_BOOTLOADER_EN -- implement IMEM as pre-initialized read-only memory? + ) + port map ( + clk_i => clk_i, -- global clock line + rden_i => p_bus.re, -- read enable + wren_i => p_bus.we, -- write enable + ben_i => p_bus.ben, -- byte write enable + addr_i => p_bus.addr, -- address + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_IMEM).rdata, -- data out + ack_o => resp_bus(RESP_IMEM).ack -- transfer acknowledge + ); + resp_bus(RESP_IMEM).err <= '0'; -- no access error possible + end generate; + + neorv32_int_imem_inst_false: + if (MEM_INT_IMEM_EN = false) or (MEM_INT_IMEM_SIZE = 0) generate + resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c; + end generate; + + + -- Processor-Internal Data Memory (DMEM) -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_int_dmem_inst_true: + if (MEM_INT_DMEM_EN = true) and (MEM_INT_DMEM_SIZE > 0) generate + neorv32_int_dmem_inst: neorv32_dmem + generic map ( + DMEM_BASE => dmem_base_c, -- memory base address + DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes + ) + port map ( + clk_i => clk_i, -- global clock line + rden_i => p_bus.re, -- read enable + wren_i => p_bus.we, -- write enable + ben_i => p_bus.ben, -- byte write enable + addr_i => p_bus.addr, -- address + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_DMEM).rdata, -- data out + ack_o => resp_bus(RESP_DMEM).ack -- transfer acknowledge + ); + resp_bus(RESP_DMEM).err <= '0'; -- no access error possible + end generate; + + neorv32_int_dmem_inst_false: + if (MEM_INT_DMEM_EN = false) or (MEM_INT_DMEM_SIZE = 0) generate + resp_bus(RESP_DMEM) <= resp_bus_entry_terminate_c; + end generate; + + + -- Processor-Internal Bootloader ROM (BOOTROM) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_boot_rom_inst_true: + if (INT_BOOTLOADER_EN = true) generate + neorv32_boot_rom_inst: neorv32_boot_rom + generic map ( + BOOTROM_BASE => boot_rom_base_c -- boot ROM base address + ) + port map ( + clk_i => clk_i, -- global clock line + rden_i => p_bus.re, -- read enable + addr_i => p_bus.addr, -- address + data_o => resp_bus(RESP_BOOTROM).rdata, -- data out + ack_o => resp_bus(RESP_BOOTROM).ack -- transfer acknowledge + ); + resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible + end generate; + + neorv32_boot_rom_inst_false: + if (INT_BOOTLOADER_EN = false) generate + resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c; + end generate; + + + -- External Wishbone Gateway (WISHBONE) --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_wishbone_inst_true: + if (MEM_EXT_EN = true) generate + neorv32_wishbone_inst: neorv32_wishbone + generic map ( + -- Internal instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Interface Configuration -- + BUS_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception + PIPE_MODE => MEM_EXT_PIPE_MODE, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian + ASYNC_RX => MEM_EXT_ASYNC_RX -- use register buffer for RX data when false + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock line + rstn_i => sys_rstn, -- global reset line, low-active + -- host access -- + src_i => p_bus.src, -- access type (0: data, 1:instruction) + addr_i => p_bus.addr, -- address + rden_i => p_bus.re, -- read enable + wren_i => p_bus.we, -- write enable + ben_i => p_bus.ben, -- byte write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_WISHBONE).rdata, -- data out + lock_i => p_bus.lock, -- exclusive access request + ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge + err_o => resp_bus(RESP_WISHBONE).err, -- transfer error + tmo_o => ext_timeout, -- transfer timeout + priv_i => p_bus.priv, -- current CPU privilege level + ext_o => ext_access, -- active external access + -- wishbone interface -- + wb_tag_o => wb_tag_o, -- request tag + wb_adr_o => wb_adr_o, -- address + wb_dat_i => wb_dat_i, -- read data + wb_dat_o => wb_dat_o, -- write data + wb_we_o => wb_we_o, -- read/write + wb_sel_o => wb_sel_o, -- byte enable + wb_stb_o => wb_stb_o, -- strobe + wb_cyc_o => wb_cyc_o, -- valid cycle + wb_lock_o => wb_lock_o, -- exclusive access request + wb_ack_i => wb_ack_i, -- transfer acknowledge + wb_err_i => wb_err_i -- transfer error + ); + end generate; + + neorv32_wishbone_inst_false: + if (MEM_EXT_EN = false) generate + resp_bus(RESP_WISHBONE) <= resp_bus_entry_terminate_c; + ext_timeout <= '0'; + ext_access <= '0'; + -- + wb_adr_o <= (others => '0'); + wb_dat_o <= (others => '0'); + wb_we_o <= '0'; + wb_sel_o <= (others => '0'); + wb_stb_o <= '0'; + wb_cyc_o <= '0'; + wb_lock_o <= '0'; + wb_tag_o <= (others => '0'); + end generate; + + + -- IO Access? ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; + io_rden <= io_acc and p_bus.re and (not p_bus.src); -- PMA: no_execute for IO region + -- the default NEORV32 peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity) + io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben) and (not p_bus.src); -- PMA: write32 only, no_execute for IO region + + + -- Custom Functions Subsystem (CFS) ------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cfs_inst_true: + if (IO_CFS_EN = true) generate + neorv32_cfs_inst: neorv32_cfs + generic map ( + CFS_CONFIG => IO_CFS_CONFIG, -- custom CFS configuration generic + CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits + CFS_OUT_SIZE => IO_CFS_OUT_SIZE -- size of CFS output conduit in bits + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => sys_rstn, -- global reset line, low-active, use as async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- byte write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_CFS).rdata, -- data out + ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge + err_o => resp_bus(RESP_CFS).err, -- access error + -- clock generator -- + clkgen_en_o => cfs_cg_en, -- enable clock generator + clkgen_i => clk_gen, -- "clock" inputs + -- interrupt -- + irq_o => cfs_irq, -- interrupt request + -- custom io (conduit) -- + cfs_in_i => cfs_in_i, -- custom inputs + cfs_out_o => cfs_out_o -- custom outputs + ); + end generate; + + neorv32_cfs_inst_false: + if (IO_CFS_EN = false) generate + resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c; + cfs_cg_en <= '0'; + cfs_irq <= '0'; + cfs_out_o <= (others => '0'); + end generate; + + + -- General Purpose Input/Output Port (GPIO) ----------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_gpio_inst_true: + if (IO_GPIO_EN = true) generate + neorv32_gpio_inst: neorv32_gpio + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_GPIO).rdata, -- data out + ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge + -- parallel io -- + gpio_o => gpio_o, + gpio_i => gpio_i + ); + resp_bus(RESP_GPIO).err <= '0'; -- no access error possible + end generate; + + neorv32_gpio_inst_false: + if (IO_GPIO_EN = false) generate + resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c; + gpio_o <= (others => '0'); + end generate; + + + -- Watch Dog Timer (WDT) ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_wdt_inst_true: + if (IO_WDT_EN = true) generate + neorv32_wdt_inst: neorv32_wdt + generic map( + DEBUG_EN => ON_CHIP_DEBUGGER_EN -- CPU debug mode implemented? + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => ext_rstn, -- global reset line, low-active + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + addr_i => p_bus.addr, -- address + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_WDT).rdata, -- data out + ack_o => resp_bus(RESP_WDT).ack, -- transfer acknowledge + -- CPU in debug mode? -- + cpu_debug_i => debug_mode, + -- clock generator -- + clkgen_en_o => wdt_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- timeout event -- + irq_o => wdt_irq, -- timeout IRQ + rstn_o => wdt_rstn -- timeout reset, low_active, use it as async! + ); + resp_bus(RESP_WDT).err <= '0'; -- no access error possible + end generate; + + neorv32_wdt_inst_false: + if (IO_WDT_EN = false) generate + resp_bus(RESP_WDT) <= resp_bus_entry_terminate_c; + wdt_irq <= '0'; + wdt_rstn <= '1'; + wdt_cg_en <= '0'; + end generate; + + + -- Machine System Timer (MTIME) ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_mtime_inst_true: + if (IO_MTIME_EN = true) generate + neorv32_mtime_inst: neorv32_mtime + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_MTIME).rdata, -- data out + ack_o => resp_bus(RESP_MTIME).ack, -- transfer acknowledge + -- time output for CPU -- + time_o => mtime_time, -- current system time + -- interrupt -- + irq_o => mtime_irq -- interrupt request + ); + resp_bus(RESP_MTIME).err <= '0'; -- no access error possible + end generate; + + neorv32_mtime_inst_false: + if (IO_MTIME_EN = false) generate + resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c; + mtime_time <= mtime_i; -- use external machine timer time signal + mtime_irq <= mtime_irq_i; -- use external machine timer interrupt + end generate; + + + -- system time output LO -- + mtime_sync: process(clk_i) + begin + if rising_edge(clk_i) then + -- buffer low word one clock cycle to compensate for MTIME's 1-cycle delay + -- when overflowing from low-word to high-word -> only relevant for processor-external devices + -- processor-internal devices (= the CPU) do not care about this delay offset as 64-bit MTIME.TIME + -- cannot be accessed within a single cycle + if (IO_MTIME_EN = true) then + mtime_o(31 downto 0) <= mtime_time(31 downto 0); + else + mtime_o(31 downto 0) <= (others => '0'); + end if; + end if; + end process mtime_sync; + + -- system time output HI -- + mtime_o(63 downto 32) <= mtime_time(63 downto 32) when (IO_MTIME_EN = true) else (others => '0'); + + + -- Primary Universal Asynchronous Receiver/Transmitter (UART0) ---------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_uart0_inst_true: + if (IO_UART0_EN = true) generate + neorv32_uart0_inst: neorv32_uart + generic map ( + UART_PRIMARY => true, -- true = primary UART (UART0), false = secondary UART (UART1) + UART_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + UART_TX_FIFO => IO_UART0_TX_FIFO -- TX fifo depth, has to be a power of two, min 1 + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_UART0).rdata, -- data out + ack_o => resp_bus(RESP_UART0).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => uart0_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines -- + uart_txd_o => uart0_txd_o, + uart_rxd_i => uart0_rxd_i, + -- hardware flow control -- + uart_rts_o => uart0_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => uart0_cts_i, -- UART.TX allowed to transmit, low-active, optional + -- interrupts -- + irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt + irq_txd_o => uart0_txd_irq -- uart transmission done interrupt + ); + resp_bus(RESP_UART0).err <= '0'; -- no access error possible + end generate; + + neorv32_uart0_inst_false: + if (IO_UART0_EN = false) generate + resp_bus(RESP_UART0) <= resp_bus_entry_terminate_c; + uart0_txd_o <= '0'; + uart0_rts_o <= '0'; + uart0_cg_en <= '0'; + uart0_rxd_irq <= '0'; + uart0_txd_irq <= '0'; + end generate; + + + -- Secondary Universal Asynchronous Receiver/Transmitter (UART1) -------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_uart1_inst_true: + if (IO_UART1_EN = true) generate + neorv32_uart1_inst: neorv32_uart + generic map ( + UART_PRIMARY => false, -- true = primary UART (UART0), false = secondary UART (UART1) + UART_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + UART_TX_FIFO => IO_UART1_TX_FIFO -- TX fifo depth, has to be a power of two, min 1 + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_UART1).rdata, -- data out + ack_o => resp_bus(RESP_UART1).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => uart1_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines -- + uart_txd_o => uart1_txd_o, + uart_rxd_i => uart1_rxd_i, + -- hardware flow control -- + uart_rts_o => uart1_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => uart1_cts_i, -- UART.TX allowed to transmit, low-active, optional + -- interrupts -- + irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt + irq_txd_o => uart1_txd_irq -- uart transmission done interrupt + ); + resp_bus(RESP_UART1).err <= '0'; -- no access error possible + end generate; + + neorv32_uart1_inst_false: + if (IO_UART1_EN = false) generate + resp_bus(RESP_UART1) <= resp_bus_entry_terminate_c; + uart1_txd_o <= '0'; + uart1_rts_o <= '0'; + uart1_cg_en <= '0'; + uart1_rxd_irq <= '0'; + uart1_txd_irq <= '0'; + end generate; + + + -- Serial Peripheral Interface (SPI) ------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_spi_inst_true: + if (IO_SPI_EN = true) generate + neorv32_spi_inst: neorv32_spi + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_SPI).rdata, -- data out + ack_o => resp_bus(RESP_SPI).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => spi_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines -- + spi_sck_o => spi_sck_o, -- SPI serial clock + spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in + spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out + spi_csn_o => spi_csn_o, -- SPI CS + -- interrupt -- + irq_o => spi_irq -- transmission done interrupt + ); + resp_bus(RESP_SPI).err <= '0'; -- no access error possible + end generate; + + neorv32_spi_inst_false: + if (IO_SPI_EN = false) generate + resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c; + spi_sck_o <= '0'; + spi_sdo_o <= '0'; + spi_csn_o <= (others => '1'); -- CSn lines are low-active + spi_cg_en <= '0'; + spi_irq <= '0'; + end generate; + + + -- Two-Wire Interface (TWI) --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_twi_inst_true: + if (IO_TWI_EN = true) generate + neorv32_twi_inst: neorv32_twi + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_TWI).rdata, -- data out + ack_o => resp_bus(RESP_TWI).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => twi_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines -- + twi_sda_io => twi_sda_io, -- serial data line + twi_scl_io => twi_scl_io, -- serial clock line + -- interrupt -- + irq_o => twi_irq -- transfer done IRQ + ); + resp_bus(RESP_TWI).err <= '0'; -- no access error possible + end generate; + + neorv32_twi_inst_false: + if (IO_TWI_EN = false) generate + resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c; + twi_sda_io <= 'Z'; + twi_scl_io <= 'Z'; + twi_cg_en <= '0'; + twi_irq <= '0'; + end generate; + + + -- Pulse-Width Modulation Controller (PWM) ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_pwm_inst_true: + if (IO_PWM_NUM_CH > 0) generate + neorv32_pwm_inst: neorv32_pwm + generic map ( + NUM_CHANNELS => IO_PWM_NUM_CH -- number of PWM channels (0..60) + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_PWM).rdata, -- data out + ack_o => resp_bus(RESP_PWM).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => pwm_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- pwm output channels -- + pwm_o => pwm_o + ); + resp_bus(RESP_PWM).err <= '0'; -- no access error possible + end generate; + + neorv32_pwm_inst_false: + if (IO_PWM_NUM_CH = 0) generate + resp_bus(RESP_PWM) <= resp_bus_entry_terminate_c; + pwm_cg_en <= '0'; + pwm_o <= (others => '0'); + end generate; + + + -- True Random Number Generator (TRNG) ---------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_trng_inst_true: + if (IO_TRNG_EN = true) generate + neorv32_trng_inst: neorv32_trng + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_TRNG).rdata, -- data out + ack_o => resp_bus(RESP_TRNG).ack -- transfer acknowledge + ); + resp_bus(RESP_TRNG).err <= '0'; -- no access error possible + end generate; + + neorv32_trng_inst_false: + if (IO_TRNG_EN = false) generate + resp_bus(RESP_TRNG) <= resp_bus_entry_terminate_c; + end generate; + + + -- Smart LED (WS2811/WS2812) Interface (NEOLED) ------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_neoled_inst_true: + if (IO_NEOLED_EN = true) generate + neorv32_neoled_inst: neorv32_neoled + generic map ( + FIFO_DEPTH => IO_NEOLED_TX_FIFO -- TX FIFO depth (1..32k, power of two) + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_NEOLED).rdata, -- data out + ack_o => resp_bus(RESP_NEOLED).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => neoled_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- interrupt -- + irq_o => neoled_irq, -- interrupt request + -- NEOLED output -- + neoled_o => neoled_o -- serial async data line + ); + resp_bus(RESP_NEOLED).err <= '0'; -- no access error possible + end generate; + + neorv32_neoled_inst_false: + if (IO_NEOLED_EN = false) generate + resp_bus(RESP_NEOLED) <= resp_bus_entry_terminate_c; + neoled_cg_en <= '0'; + neoled_irq <= '0'; + neoled_o <= '0'; + end generate; + + + -- Stream Link Interface (SLINK) ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_slink_inst_true: + if (io_slink_en_c = true) generate + neorv32_slink_inst: neorv32_slink + generic map ( + SLINK_NUM_TX => SLINK_NUM_TX, -- number of TX links (0..8) + SLINK_NUM_RX => SLINK_NUM_RX, -- number of TX links (0..8) + SLINK_TX_FIFO => SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO => SLINK_RX_FIFO -- RX fifo depth, has to be a power of two + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_SLINK).rdata, -- data out + ack_o => resp_bus(RESP_SLINK).ack, -- transfer acknowledge + -- interrupt -- + irq_tx_o => slink_tx_irq, -- transmission done + irq_rx_o => slink_rx_irq, -- data received + -- TX stream interfaces -- + slink_tx_dat_o => slink_tx_dat_o, -- output data + slink_tx_val_o => slink_tx_val_o, -- valid output + slink_tx_rdy_i => slink_tx_rdy_i, -- ready to send + -- RX stream interfaces -- + slink_rx_dat_i => slink_rx_dat_i, -- input data + slink_rx_val_i => slink_rx_val_i, -- valid input + slink_rx_rdy_o => slink_rx_rdy_o -- ready to receive + ); + resp_bus(RESP_SLINK).err <= '0'; -- no access error possible + end generate; + + neorv32_slink_inst_false: + if (io_slink_en_c = false) generate + resp_bus(RESP_SLINK) <= resp_bus_entry_terminate_c; + slink_tx_irq <= '0'; + slink_rx_irq <= '0'; + slink_tx_dat_o <= (others => (others => '0')); + slink_tx_val_o <= (others => '0'); + slink_rx_rdy_o <= (others => '0'); + end generate; + + + -- External Interrupt Controller (XIRQ) --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_xirq_inst_true: + if (XIRQ_NUM_CH > 0) generate + neorv32_slink_inst: neorv32_xirq + generic map ( + XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE, -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_XIRQ).rdata, -- data out + ack_o => resp_bus(RESP_XIRQ).ack, -- transfer acknowledge + -- external interrupt lines -- + xirq_i => xirq_i, + -- CPU interrupt -- + cpu_irq_o => xirq_irq + ); + resp_bus(RESP_XIRQ).err <= '0'; -- no access error possible + end generate; + + neorv32_xirq_inst_false: + if (XIRQ_NUM_CH = 0) generate + resp_bus(RESP_XIRQ) <= resp_bus_entry_terminate_c; + xirq_irq <= '0'; + end generate; + + + -- General Purpose Timer (GPTMR) ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_gptmr_inst_true: + if (IO_GPTMR_EN = true) generate + neorv32_gptmr_inst: neorv32_gptmr + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_GPTMR).rdata, -- data out + ack_o => resp_bus(RESP_GPTMR).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => gptmr_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- interrupt -- + irq_o => gptmr_irq -- transmission done interrupt + ); + resp_bus(RESP_GPTMR).err <= '0'; -- no access error possible + end generate; + + neorv32_gptmr_inst_false: + if (IO_GPTMR_EN = false) generate + resp_bus(RESP_GPTMR) <= resp_bus_entry_terminate_c; + gptmr_cg_en <= '0'; + gptmr_irq <= '0'; + end generate; + + + -- System Configuration Information Memory (SYSINFO) -------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_sysinfo_inst: neorv32_sysinfo + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader? + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_DEBUG => ON_CHIP_DEBUGGER_EN, -- implement CPU debug mode? + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + -- internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2 + -- External memory interface -- + MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface? + MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian + -- On-Chip Debugger -- + ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD? + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? + IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? + IO_SLINK_EN => io_slink_en_c, -- implement stream link interface? + IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement + IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)? + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + data_o => resp_bus(RESP_SYSINFO).rdata, -- data out + ack_o => resp_bus(RESP_SYSINFO).ack -- transfer acknowledge + ); + + resp_bus(RESP_SYSINFO).err <= '0'; -- no access error possible + + + -- ************************************************************************************************************************** + -- On-Chip Debugger Complex + -- ************************************************************************************************************************** + + + -- On-Chip Debugger - Debug Module (DM) --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_neorv32_debug_dm_true: + if (ON_CHIP_DEBUGGER_EN = true) generate + neorv32_debug_dm_inst: neorv32_debug_dm + port map ( + -- global control -- + clk_i => clk_i, -- global clock line + rstn_i => ext_rstn, -- external reset, low-active + -- debug module interface (DMI) -- + dmi_rstn_i => dmi.rstn, + dmi_req_valid_i => dmi.req_valid, + dmi_req_ready_o => dmi.req_ready, + dmi_req_addr_i => dmi.req_addr, + dmi_req_op_i => dmi.req_op, + dmi_req_data_i => dmi.req_data, + dmi_resp_valid_o => dmi.resp_valid, -- response valid when set + dmi_resp_ready_i => dmi.resp_ready, -- ready to receive respond + dmi_resp_data_o => dmi.resp_data, + dmi_resp_err_o => dmi.resp_err, -- 0=ok, 1=error + -- CPU bus access -- + cpu_addr_i => p_bus.addr, -- address + cpu_rden_i => p_bus.re, -- read enable + cpu_wren_i => p_bus.we, -- write enable + cpu_data_i => p_bus.wdata, -- data in + cpu_data_o => resp_bus(RESP_OCD).rdata, -- data out + cpu_ack_o => resp_bus(RESP_OCD).ack, -- transfer acknowledge + -- CPU control -- + cpu_ndmrstn_o => dci_ndmrstn, -- soc reset + cpu_halt_req_o => dci_halt_req -- request hart to halt (enter debug mode) + ); + resp_bus(RESP_OCD).err <= '0'; -- no access error possible + end generate; + + neorv32_debug_dm_false: + if (ON_CHIP_DEBUGGER_EN = false) generate + dmi.req_ready <= '0'; + dmi.resp_valid <= '0'; + dmi.resp_data <= (others => '0'); + dmi.resp_err <= '0'; + -- + resp_bus(RESP_OCD) <= resp_bus_entry_terminate_c; + dci_ndmrstn <= '1'; + dci_halt_req <= '0'; + end generate; + + + -- On-Chip Debugger - Debug Transport Module (DTM) ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_neorv32_debug_dtm_true: + if (ON_CHIP_DEBUGGER_EN = true) generate + neorv32_debug_dtm_inst: neorv32_debug_dtm + generic map ( + IDCODE_VERSION => jtag_tap_idcode_version_c, -- version + IDCODE_PARTID => jtag_tap_idcode_partid_c, -- part number + IDCODE_MANID => jtag_tap_idcode_manid_c -- manufacturer id + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock line + rstn_i => ext_rstn, -- external reset, low-active + -- jtag connection -- + jtag_trst_i => jtag_trst_i, + jtag_tck_i => jtag_tck_i, + jtag_tdi_i => jtag_tdi_i, + jtag_tdo_o => jtag_tdo_o, + jtag_tms_i => jtag_tms_i, + -- debug module interface (DMI) -- + dmi_rstn_o => dmi.rstn, + dmi_req_valid_o => dmi.req_valid, + dmi_req_ready_i => dmi.req_ready, -- DMI is allowed to make new requests when set + dmi_req_addr_o => dmi.req_addr, + dmi_req_op_o => dmi.req_op, -- 0=read, 1=write + dmi_req_data_o => dmi.req_data, + dmi_resp_valid_i => dmi.resp_valid, -- response valid when set + dmi_resp_ready_o => dmi.resp_ready, -- ready to receive respond + dmi_resp_data_i => dmi.resp_data, + dmi_resp_err_i => dmi.resp_err -- 0=ok, 1=error + ); + end generate; + + neorv32_debug_dtm_false: + if (ON_CHIP_DEBUGGER_EN = false) generate + jtag_tdo_o <= jtag_tdi_i; -- feed-through + -- + dmi.rstn <= '0'; + dmi.req_valid <= '0'; + dmi.req_addr <= (others => '0'); + dmi.req_op <= '0'; + dmi.req_data <= (others => '0'); + dmi.resp_ready <= '0'; + end generate; + + +end neorv32_top_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_trng.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_trng.vhd new file mode 100644 index 0000000..0eaeb41 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_trng.vhd @@ -0,0 +1,550 @@ +-- ################################################################################################# +-- # << NEORV32 - True Random Number Generator (TRNG) >> # +-- # ********************************************************************************************* # +-- # This processor module instantiates the "neoTRNG" true random number generator. # +-- # See the neoTRNG's documentation for more information: https://github.com/stnolting/neoTRNG # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_trng is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic -- transfer acknowledge + ); +end neorv32_trng; + +architecture neorv32_trng_rtl of neorv32_trng is + + -- neoTRNG Configuration ------------------------------------------------------------------------------------------- + constant num_cells_c : natural := 3; -- total number of ring-oscillator cells + constant num_inv_start_c : natural := 3; -- number of inverters in first cell (short path), has to be odd + constant num_inv_inc_c : natural := 2; -- number of additional inverters in next cell (short path), has to be even + constant num_inv_delay_c : natural := 2; -- additional inverters to form cell's long path, has to be even + -- ----------------------------------------------------------------------------------------------------------------- + + -- control register bits -- + constant ctrl_data_lsb_c : natural := 0; -- r/-: Random data byte LSB + constant ctrl_data_msb_c : natural := 7; -- r/-: Random data byte MSB + constant ctrl_en_c : natural := 30; -- r/w: TRNG enable + constant ctrl_valid_c : natural := 31; -- r/-: Output data valid + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(trng_size_c); -- low address boundary bit + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal wren : std_ulogic; -- full word write enable + signal rden : std_ulogic; -- read enable + + -- Component: neoTRNG true random number generator -- + component neoTRNG + generic ( + NUM_CELLS : natural; -- total number of ring-oscillator cells + NUM_INV_START : natural; -- number of inverters in first cell (short path), has to be odd + NUM_INV_INC : natural; -- number of additional inverters in next cell (short path), has to be even + NUM_INV_DELAY : natural -- additional inverters to form cell's long path, has to be even + ); + port ( + clk_i : in std_ulogic; -- global clock line + enable_i : in std_ulogic; -- unit enable (high-active), reset unit when low + data_o : out std_ulogic_vector(7 downto 0); -- random data byte output + valid_o : out std_ulogic -- data_o is valid when set + ); + end component; + + -- TRNG interface -- + signal trng_data : std_ulogic_vector(7 downto 0); + signal trng_valid : std_ulogic; + + -- arbiter -- + signal enable : std_ulogic; + signal valid : std_ulogic; + signal rnd_reg : std_ulogic_vector(7 downto 0); + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0'; + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- host bus acknowledge -- + ack_o <= wren or rden; + + -- write access -- + if (wren = '1') then + enable <= data_i(ctrl_en_c); + end if; + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + data_o(ctrl_data_msb_c downto ctrl_data_lsb_c) <= rnd_reg; + data_o(ctrl_en_c) <= enable; + data_o(ctrl_valid_c) <= valid; + end if; + + -- sample -- + if (trng_valid = '1') then + rnd_reg <= trng_data; + end if; + + -- data valid? -- + if (enable = '0') then -- disabled + valid <= '0'; + else + if (trng_valid = '1') then + valid <= '1'; + elsif (rden = '1') then + valid <= '0'; + end if; + end if; + end if; + end process rw_access; + + + -- neoTRNG -------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neoTRNG_inst: neoTRNG + generic map ( + NUM_CELLS => num_cells_c, + NUM_INV_START => num_inv_start_c, + NUM_INV_INC => num_inv_inc_c, + NUM_INV_DELAY => num_inv_delay_c + ) + port map ( + clk_i => clk_i, + enable_i => enable, + data_o => trng_data, + valid_o => trng_valid + ); + + +end neorv32_trng_rtl; + + +-- ############################################################################################################################ +-- ############################################################################################################################ + + +-- ################################################################################################# +-- # << neoTRNG - A Tiny and Platform-Independent True Random Number Generator for any FPGA >> # +-- # ********************************************************************************************* # +-- # This generator is based on entropy cells, which implement simple ring-oscillators. Each ring- # +-- # oscillator features a short and a long delay path that is dynamically selected defining the # +-- # primary oscillation frequency. The cells are cascaded so that the random data output of a # +-- # cell controls the delay path of the next cell (which has the next-larger inverter chain). # +-- # # +-- # The random data outputs of all cells are XOR-ed and de-biased using a von Neumann randomness # +-- # extractor (converting edges into bits). The resulting bit is sampled in chunks of 8 bits to # +-- # provide the final random data output. No further internal post-processing is applied. Hence, # +-- # the TRNG produces simple de-biased *RAW* data. # +-- # # +-- # The entropy cell architecture uses individually-controlled latches and inverters to create # +-- # the inverter chain in a platform-agnostic style that can be implemented for any FPGA without # +-- # requiring primitive instantiation or technology-specific attributes. # +-- # # +-- # See the neoTRNG's documentation for more information: https://github.com/stnolting/neoTRNG # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # neoTRNG - https://github.com/stnolting/neoTRNG (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity neoTRNG is + generic ( + NUM_CELLS : natural; -- total number of ring-oscillator cells + NUM_INV_START : natural; -- number of inverters in first cell (short path), has to be odd + NUM_INV_INC : natural; -- number of additional inverters in next cell (short path), has to be even + NUM_INV_DELAY : natural -- additional inverters to form cell's long path, has to be even + ); + port ( + clk_i : in std_ulogic; -- global clock line + enable_i : in std_ulogic; -- unit enable (high-active), reset unit when low + data_o : out std_ulogic_vector(7 downto 0); -- random data byte output + valid_o : out std_ulogic -- data_o is valid when set + ); +end neoTRNG; + +architecture neoTRNG_rtl of neoTRNG is + + -- Component: neoTRNG entropy cell -- + component neoTRNG_cell + generic ( + NUM_INV_S : natural; -- number of inverters in short path + NUM_INV_L : natural -- number of inverters in long path + ); + port ( + clk_i : in std_ulogic; -- system clock + select_i : in std_ulogic; -- delay select + enable_i : in std_ulogic; -- enable chain input + enable_o : out std_ulogic; -- enable chain output + data_o : out std_ulogic -- sync random bit + ); + end component; + + -- ring-oscillator array interconnect -- + type cell_array_t is record + en_in : std_ulogic_vector(NUM_CELLS-1 downto 0); + en_out : std_ulogic_vector(NUM_CELLS-1 downto 0); + rnd : std_ulogic_vector(NUM_CELLS-1 downto 0); + sel : std_ulogic_vector(NUM_CELLS-1 downto 0); + end record; + signal cell_array : cell_array_t; + + -- global cell-XOR -- + signal rnd_bit : std_ulogic; + + -- von-Neumann de-biasing -- + type debiasing_t is record + sreg : std_ulogic_vector(1 downto 0); + state : std_ulogic; -- process de-biasing every second cycle + valid : std_ulogic; -- de-biased data + data : std_ulogic; -- de-biased data valid + end record; + signal deb : debiasing_t; + + -- control unit -- + type ctrl_t is record + enable : std_ulogic; + run : std_ulogic; + cnt : std_ulogic_vector(2 downto 0); -- bit counter + sreg : std_ulogic_vector(7 downto 0); -- data shift register + end record; + signal ctrl : ctrl_t; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (NUM_CELLS < 2) report "neoTRNG config ERROR: Total number of ring-oscillator cells has to be >= 2." severity error; + assert not ((NUM_INV_START mod 2) = 0) report "neoTRNG config ERROR: Number of inverters in first cell has to be odd." severity error; + assert not ((NUM_INV_INC mod 2) /= 0) report "neoTRNG config ERROR: Inverter increment for each next cell has to be even." severity error; + assert not ((NUM_INV_DELAY mod 2) /= 0) report "neoTRNG config ERROR: Inverter increment to form long path has to be even." severity error; + + + -- Entropy Source ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neoTRNG_cell_inst: + for i in 0 to NUM_CELLS-1 generate + neoTRNG_cell_inst_i: neoTRNG_cell + generic map ( + NUM_INV_S => NUM_INV_START + (i*NUM_INV_INC), -- number of inverters in short chain + NUM_INV_L => NUM_INV_START + (i*NUM_INV_INC) + NUM_INV_DELAY -- number of inverters in long chain + ) + port map ( + clk_i => clk_i, + select_i => cell_array.sel(i), + enable_i => cell_array.en_in(i), + enable_o => cell_array.en_out(i), + data_o => cell_array.rnd(i) -- SYNC data output + ); + end generate; + + -- path select chain -- + cell_array.sel(0) <= cell_array.rnd(NUM_CELLS-1); -- use output of last cell to select path of first cell + cell_array.sel(NUM_CELLS-1 downto 1) <= cell_array.rnd(NUM_CELLS-2 downto 0); -- i+1 <= i + + -- enable chain -- + cell_array.en_in(0) <= ctrl.enable; -- start of chain + cell_array.en_in(NUM_CELLS-1 downto 1) <=cell_array.en_out(NUM_CELLS-2 downto 0); -- i+1 <= i + + + -- XOR All Cell's Outputs ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + cell_xor: process(cell_array.rnd) + variable tmp_v : std_ulogic; + begin + tmp_v := '0'; + for i in 0 to NUM_CELLS-1 loop + tmp_v := tmp_v xor cell_array.rnd(i); + end loop; -- i + rnd_bit <= tmp_v; + end process cell_xor; + + + -- John von Neumann Randomness Extractor -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + debiasing_sync: process(clk_i) + begin + if rising_edge(clk_i) then + deb.sreg <= deb.sreg(0) & rnd_bit; + -- start operation when last cell is enabled and process in every second cycle -- + deb.state <= (not deb.state) and cell_array.en_out(NUM_CELLS-1); + end if; + end process debiasing_sync; + + -- edge detector -- + debiasing_comb: process(deb) + variable tmp_v : std_ulogic_vector(2 downto 0); + begin + tmp_v := deb.state & deb.sreg(1 downto 0); -- check groups of two non-overlapping bits from the input stream + case tmp_v is + when "101" => deb.valid <= '1'; deb.data <= '0'; -- rising edge = '0' + when "110" => deb.valid <= '1'; deb.data <= '1'; -- falling edge = '1' + when others => deb.valid <= '0'; deb.data <= '-'; -- no valid data + end case; + end process debiasing_comb; + + + -- Control Unit --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + control_unit: process(clk_i) + begin + if rising_edge(clk_i) then + -- make sure enable is sync -- + ctrl.enable <= enable_i; + + -- sample chunks of 8 bit -- + if (ctrl.enable = '0') then + ctrl.cnt <= (others => '0'); + ctrl.run <= '0'; + elsif (deb.valid = '1') then -- valid random sample? + ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) + 1); + ctrl.run <= '1'; + end if; + + -- sample shift register -- + if (deb.valid = '1') then + ctrl.sreg <= ctrl.sreg(ctrl.sreg'left-1 downto 0) & deb.data; + end if; + + end if; + end process control_unit; + + -- random byte output -- + data_o <= ctrl.sreg; + + -- data valid? -- + valid_o <= '1' when (ctrl.cnt = "000") and (ctrl.run = '1') else '0'; + + +end neoTRNG_rtl; + + +-- ############################################################################################################################ +-- ############################################################################################################################ + + +-- ################################################################################################# +-- # << neoTRNG - A Tiny and Platform-Independent True Random Number Generator for any FPGA >> # +-- # ********************************************************************************************* # +-- # neoTRNG Entropy Cell # +-- # # +-- # The cell consists of two ring-oscillators build from inverter chains. The short chain uses # +-- # NUM_INV_S inverters and oscillates at a "high" frequency and the long chain uses NUM_INV_L # +-- # inverters and oscillates at a "low" frequency. The select_i input selects which chain is # +-- # actually used. # +-- # # +-- # Each inverter chain is constructed as an "asynchronous" shift register. The single inverters # +-- # are connected via latches that are used to enable/disable the TRNG. Also, these latches are # +-- # used as additional delay element. By using unique enable signals for each latch, the # +-- # synthesis tool cannot "optimize" (=remove) any of the inverters out of the design making the # +-- # design platform-agnostic. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # neoTRNG - https://github.com/stnolting/neoTRNG (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; + +entity neoTRNG_cell is + generic ( + NUM_INV_S : natural; -- number of inverters in short path + NUM_INV_L : natural -- number of inverters in long path + ); + port ( + clk_i : in std_ulogic; -- system clock + select_i : in std_ulogic; -- delay select + enable_i : in std_ulogic; -- enable chain input + enable_o : out std_ulogic; -- enable chain output + data_o : out std_ulogic -- sync random bit + ); +end neoTRNG_cell; + +architecture neoTRNG_cell_rtl of neoTRNG_cell is + + signal inv_chain_s : std_ulogic_vector(NUM_INV_S-1 downto 0); -- short oscillator chain + signal inv_chain_l : std_ulogic_vector(NUM_INV_L-1 downto 0); -- long oscillator chain + signal feedback : std_ulogic; -- cell feedback/output + signal enable_sreg_s : std_ulogic_vector(NUM_INV_S-1 downto 0); -- enable shift register for short chain + signal enable_sreg_l : std_ulogic_vector(NUM_INV_L-1 downto 0); -- enable shift register for long chain + signal sync_ff : std_ulogic_vector(1 downto 0); -- output signal synchronizer + +begin + + -- Ring Oscillators ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Each cell provides a short inverter chain (high frequency) and a long oscillator chain (low frequency). + -- The select_i signals defines which chain is enabled. + -- NOTE: All signals that control a inverter-latch element have to be registered to ensure a single element + -- is mapped to a single LUT (or LUT + FF(latch-mode)). + + -- short oscillator chain -- + ring_osc_short: process(enable_i, enable_sreg_s, feedback, inv_chain_s) + begin + for i in 0 to NUM_INV_S-1 loop -- inverters in short chain + if (enable_i = '0') then -- start with a defined state (latch reset) + inv_chain_s(i) <= '0'; + elsif (enable_sreg_s(i) = '1') then + if (i = NUM_INV_S-1) then -- left-most inverter? + inv_chain_s(i) <= not feedback; + else + inv_chain_s(i) <= not inv_chain_s(i+1); + end if; + end if; + end loop; -- i + end process ring_osc_short; + + -- long oscillator chain -- + ring_osc_long: process(enable_i, enable_sreg_l, feedback, inv_chain_l) + begin + for i in 0 to NUM_INV_L-1 loop -- inverters in long chain + if (enable_i = '0') then -- start with a defined state (latch reset) + inv_chain_l(i) <= '0'; + elsif (enable_sreg_l(i) = '1') then + if (i = NUM_INV_L-1) then -- left-most inverter? + inv_chain_l(i) <= not feedback; + else + inv_chain_l(i) <= not inv_chain_l(i+1); + end if; + end if; + end loop; -- i + end process ring_osc_long; + + -- length select -- + feedback <= inv_chain_l(0) when (select_i = '0') else inv_chain_s(0); + + + -- Control -------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Using individual enable signals for each inverter from a shift register to prevent the synthesis tool + -- from removing all but one inverter (since they implement "logical identical functions" (='toggle')). + -- This makes the TRNG platform independent (since we do not need to use primitives to ensure a correct architecture). + ctrl_unit: process(clk_i) + begin + if rising_edge(clk_i) then + -- enable sreg -- + enable_sreg_s <= enable_sreg_s(enable_sreg_s'left-1 downto 0) & enable_i; + enable_sreg_l <= enable_sreg_l(enable_sreg_l'left-1 downto 0) & enable_sreg_s(enable_sreg_s'left); + -- data output sync - no metastability beyond this point -- + sync_ff <= sync_ff(0) & feedback; + end if; + end process ctrl_unit; + + -- output for "enable chain" -- + enable_o <= enable_sreg_l(enable_sreg_l'left); + + -- random data output -- + data_o <= sync_ff(1); + + +end neoTRNG_cell_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_twi.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_twi.vhd new file mode 100644 index 0000000..aee310f --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_twi.vhd @@ -0,0 +1,290 @@ +-- ################################################################################################# +-- # << NEORV32 - Two-Wire Interface Controller (TWI) >> # +-- # ********************************************************************************************* # +-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. # +-- # Supports ACKs by the controller. No multi-controller support and no peripheral mode support # +-- # yet. Interrupt: "operation done" # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_twi is + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- com lines -- + twi_sda_io : inout std_logic; -- serial data line + twi_scl_io : inout std_logic; -- serial clock line + -- interrupt -- + irq_o : out std_ulogic -- transfer done IRQ + ); +end neorv32_twi; + +architecture neorv32_twi_rtl of neorv32_twi is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(twi_size_c); -- low address boundary bit + + -- control register -- + constant ctrl_en_c : natural := 0; -- r/w: TWI enable + constant ctrl_start_c : natural := 1; -- -/w: Generate START condition + constant ctrl_stop_c : natural := 2; -- -/w: Generate STOP condition + constant ctrl_prsc0_c : natural := 3; -- r/w: CLK prsc bit 0 + constant ctrl_prsc1_c : natural := 4; -- r/w: CLK prsc bit 1 + constant ctrl_prsc2_c : natural := 5; -- r/w: CLK prsc bit 2 + constant ctrl_mack_c : natural := 6; -- r/w: generate ACK by controller for transmission + -- + constant ctrl_ack_c : natural := 30; -- r/-: Set if ACK received + constant ctrl_busy_c : natural := 31; -- r/-: Set if TWI unit is busy + -- + signal ctrl : std_ulogic_vector(6 downto 0); -- unit's control register + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- twi clocking -- + signal twi_clk : std_ulogic; + signal twi_phase_gen : std_ulogic_vector(3 downto 0); + signal twi_clk_phase : std_ulogic_vector(3 downto 0); + + -- twi clock stretching -- + signal twi_clk_halt : std_ulogic; + + -- twi transceiver core -- + signal arbiter : std_ulogic_vector(2 downto 0); + signal bitcnt : std_ulogic_vector(3 downto 0); + signal rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg + + -- tri-state I/O -- + signal twi_sda_in_ff : std_ulogic_vector(1 downto 0); -- SDA input sync + signal twi_scl_in_ff : std_ulogic_vector(1 downto 0); -- SCL input sync + signal twi_sda_in : std_ulogic; + signal twi_scl_in : std_ulogic; + signal twi_sda_out : std_ulogic; + signal twi_scl_out : std_ulogic; + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = twi_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= twi_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= rden or wren; + -- write access -- + if (wren = '1') then + if (addr = twi_ctrl_addr_c) then + ctrl <= data_i(ctrl'left downto 0); + end if; + end if; + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + if (addr = twi_ctrl_addr_c) then + data_o(ctrl_en_c) <= ctrl(ctrl_en_c); + data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c); + data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c); + data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c); + data_o(ctrl_mack_c) <= ctrl(ctrl_mack_c); + -- + data_o(ctrl_ack_c) <= not rtx_sreg(0); + data_o(ctrl_busy_c) <= arbiter(1) or arbiter(0); + else -- twi_rtx_addr_c => + data_o(7 downto 0) <= rtx_sreg(8 downto 1); + end if; + end if; + end if; + end process rw_access; + + + -- Clock Generation ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- clock generator enable -- + clkgen_en_o <= ctrl(ctrl_en_c); + + -- twi clock select -- + twi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c)))); + + -- generate four non-overlapping clock ticks at twi_clk/4 -- + clock_phase_gen: process(clk_i) + begin + if rising_edge(clk_i) then + if (arbiter(2) = '0') or (arbiter(1 downto 0) = "00") then -- offline or idle + twi_phase_gen <= "0001"; -- make sure to start with a new phase, bit 0,1,2,3 stepping + elsif (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected + twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- rotate left + end if; + end if; + end process clock_phase_gen; + + -- TWI bus signals are set/sampled using 4 clock phases -- + twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk; -- first step + twi_clk_phase(1) <= twi_phase_gen(1) and twi_clk; + twi_clk_phase(2) <= twi_phase_gen(2) and twi_clk; + twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk; -- last step + + + -- TWI Transceiver ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + twi_rtx_unit: process(clk_i) + begin + if rising_edge(clk_i) then + -- input synchronizer & sampler -- + twi_sda_in_ff <= twi_sda_in_ff(0) & twi_sda_in; + twi_scl_in_ff <= twi_scl_in_ff(0) & twi_scl_in; + + -- defaults -- + irq_o <= '0'; + + -- serial engine -- + arbiter(2) <= ctrl(ctrl_en_c); -- still activated? + case arbiter is + + when "100" => -- IDLE: waiting for requests, bus might be still claimed by this controller if no STOP condition was generated + bitcnt <= (others => '0'); + if (wren = '1') then + if (addr = twi_ctrl_addr_c) then + if (data_i(ctrl_start_c) = '1') then -- issue START condition + arbiter(1 downto 0) <= "01"; + elsif (data_i(ctrl_stop_c) = '1') then -- issue STOP condition + arbiter(1 downto 0) <= "10"; + end if; + elsif (addr = twi_rtx_addr_c) then -- start a data transmission + -- one bit extra for ack, issued by controller if ctrl_mack_c is set, + -- sampled from peripheral if ctrl_mack_c is cleared + rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_mack_c)); + arbiter(1 downto 0) <= "11"; + end if; + end if; + + when "101" => -- START: generate START condition + if (twi_clk_phase(0) = '1') then + twi_sda_out <= '1'; + elsif (twi_clk_phase(1) = '1') then + twi_sda_out <= '0'; + end if; + -- + if (twi_clk_phase(0) = '1') then + twi_scl_out <= '1'; + elsif (twi_clk_phase(3) = '1') then + twi_scl_out <= '0'; + irq_o <= '1'; -- Interrupt! + arbiter(1 downto 0) <= "00"; -- go back to IDLE + end if; + + when "110" => -- STOP: generate STOP condition + if (twi_clk_phase(0) = '1') then + twi_sda_out <= '0'; + elsif (twi_clk_phase(3) = '1') then + twi_sda_out <= '1'; + irq_o <= '1'; -- Interrupt! + arbiter(1 downto 0) <= "00"; -- go back to IDLE + end if; + -- + if (twi_clk_phase(0) = '1') then + twi_scl_out <= '0'; + elsif (twi_clk_phase(1) = '1') then + twi_scl_out <= '1'; + end if; + + when "111" => -- TRANSMISSION: transmission in progress + if (twi_clk_phase(0) = '1') then + bitcnt <= std_ulogic_vector(unsigned(bitcnt) + 1); + twi_scl_out <= '0'; + twi_sda_out <= rtx_sreg(8); -- MSB first + elsif (twi_clk_phase(1) = '1') then -- first half + second half of valid data strobe + twi_scl_out <= '1'; + elsif (twi_clk_phase(3) = '1') then + rtx_sreg <= rtx_sreg(7 downto 0) & twi_sda_in_ff(twi_sda_in_ff'left); -- sample and shift left + twi_scl_out <= '0'; + end if; + -- + if (bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay + irq_o <= '1'; -- Interrupt! + arbiter(1 downto 0) <= "00"; -- go back to IDLE + end if; + + when others => -- "0--" OFFLINE: TWI deactivated + twi_sda_out <= '1'; + twi_scl_out <= '1'; + arbiter(1 downto 0) <= "00"; -- stay here, go to idle when activated + + end case; + end if; + end process twi_rtx_unit; + + + -- Clock Stretching Detector -------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- controller wants to pull SCL high, but SCL is pulled low by peripheral -- + twi_clk_halt <= '1' when (twi_scl_out = '1') and (twi_scl_in_ff(twi_scl_in_ff'left) = '0') else '0'; + + + -- Tri-State Driver ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- SDA and SCL need to be of type std_logic to be correctly resolved in simulation + twi_sda_io <= '0' when (twi_sda_out = '0') else 'Z'; + twi_scl_io <= '0' when (twi_scl_out = '0') else 'Z'; + + -- read-back -- + twi_sda_in <= std_ulogic(twi_sda_io); + twi_scl_in <= std_ulogic(twi_scl_io); + + +end neorv32_twi_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_uart.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_uart.vhd new file mode 100644 index 0000000..87daf86 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_uart.vhd @@ -0,0 +1,648 @@ +-- ################################################################################################# +-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART0/1) >> # +-- # ********************************************************************************************* # +-- # Frame configuration: 1 start bit, 8 bit data, parity bit (none/even/odd), 1 stop bit, # +-- # programmable BAUD rate via clock pre-scaler and 12-bit BAUD value configuration register, # +-- # optional configurable RX and TX FIFOs. # +-- # # +-- # Interrupts: Configurable RX and TX interrupt (both triggered by specific FIFO fill-levels) # +-- # # +-- # Support for RTS("RTR")/CTS hardware flow control: # +-- # * uart_rts_o = 0: RX is ready to receive a new char, enabled via CTRL.ctrl_rts_en_c # +-- # * uart_cts_i = 0: TX is allowed to send a new char, enabled via CTRL.ctrl_cts_en_c # +-- # # +-- # UART0 / UART1: # +-- # This module is used for implementing UART0 and UART1. The UART_PRIMARY generic configures the # +-- # interface register addresses and simulation outputs for UART0 (UART_PRIMARY = true) or UART1 # +-- # (UART_PRIMARY = false). # +-- # # +-- # SIMULATION MODE: # +-- # When the simulation mode is enabled (setting the ctrl.ctrl_sim_en_c bit) any write # +-- # access to the TX register will not trigger any UART activity. Instead, the written data is # +-- # output to the simulation environment. The lowest 8 bits of the written data are printed as # +-- # ASCII char to the simulator console. # +-- # This char is also stored to the file "neorv32.uartX.sim_mode.text.out" (where X = 0 for UART0 # +-- # and X = 1 for UART1). The full 32-bit write data is also stored as 8-digit hexadecimal value # +-- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1). # +-- # No interrupts are triggered when in SIMULATION MODE. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; +use std.textio.all; + +entity neorv32_uart is + generic ( + UART_PRIMARY : boolean; -- true = primary UART (UART0), false = secondary UART (UART1) + UART_RX_FIFO : natural; -- RX fifo depth, has to be a power of two, min 1 + UART_TX_FIFO : natural -- TX fifo depth, has to be a power of two, min 1 + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- com lines -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- hardware flow control -- + uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional + uart_cts_i : in std_ulogic; -- UART.TX allowed to transmit, low-active, optional + -- interrupts -- + irq_rxd_o : out std_ulogic; -- uart data received interrupt + irq_txd_o : out std_ulogic -- uart transmission done interrupt + ); +end neorv32_uart; + +architecture neorv32_uart_rtl of neorv32_uart is + + -- interface configuration for UART0 / UART1 -- + constant uart_id_base_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_base_c, uart1_base_c); + constant uart_id_size_c : natural := cond_sel_natural_f( UART_PRIMARY, uart0_size_c, uart1_size_c); + constant uart_id_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_ctrl_addr_c, uart1_ctrl_addr_c); + constant uart_id_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := cond_sel_stdulogicvector_f(UART_PRIMARY, uart0_rtx_addr_c, uart1_rtx_addr_c); + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(uart_id_size_c); -- low address boundary bit + + -- simulation output configuration -- + constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled + constant sim_text_output_en_c : boolean := true; -- output lowest byte as char to text file when enabled + constant sim_data_output_en_c : boolean := true; -- dump 32-bit TX word to file when enabled + constant sim_uart_text_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out"); + constant sim_uart_data_file_c : string := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out"); + + -- control register -- + signal ctrl : std_ulogic_vector(31 downto 0); + + -- control register bits -- + constant ctrl_baud00_c : natural := 0; -- r/w: baud config bit 0 + constant ctrl_baud01_c : natural := 1; -- r/w: baud config bit 1 + constant ctrl_baud02_c : natural := 2; -- r/w: baud config bit 2 + constant ctrl_baud03_c : natural := 3; -- r/w: baud config bit 3 + constant ctrl_baud04_c : natural := 4; -- r/w: baud config bit 4 + constant ctrl_baud05_c : natural := 5; -- r/w: baud config bit 5 + constant ctrl_baud06_c : natural := 6; -- r/w: baud config bit 6 + constant ctrl_baud07_c : natural := 7; -- r/w: baud config bit 7 + constant ctrl_baud08_c : natural := 8; -- r/w: baud config bit 8 + constant ctrl_baud09_c : natural := 9; -- r/w: baud config bit 9 + constant ctrl_baud10_c : natural := 10; -- r/w: baud config bit 10 + constant ctrl_baud11_c : natural := 11; -- r/w: baud config bit 11 + constant ctrl_sim_en_c : natural := 12; -- r/w: UART <> enable + constant ctrl_rx_empty_c : natural := 13; -- r/-: RX FIFO is empty + constant ctrl_rx_half_c : natural := 14; -- r/-: RX FIFO is at least half-full + constant ctrl_rx_full_c : natural := 15; -- r/-: RX FIFO is full + constant ctrl_tx_empty_c : natural := 16; -- r/-: TX FIFO is empty + constant ctrl_tx_half_c : natural := 17; -- r/-: TX FIFO is at least half-full + constant ctrl_tx_full_c : natural := 18; -- r/-: TX FIFO is full + -- ... + constant ctrl_rts_en_c : natural := 20; -- r/w: enable hardware flow control: assert rts_o if ready to receive + constant ctrl_cts_en_c : natural := 21; -- r/w: enable hardware flow control: send only if cts_i is asserted + constant ctrl_pmode0_c : natural := 22; -- r/w: Parity config (0=even; 1=odd) + constant ctrl_pmode1_c : natural := 23; -- r/w: Enable parity bit + constant ctrl_prsc0_c : natural := 24; -- r/w: baud prsc bit 0 + constant ctrl_prsc1_c : natural := 25; -- r/w: baud prsc bit 1 + constant ctrl_prsc2_c : natural := 26; -- r/w: baud prsc bit 2 + constant ctrl_cts_c : natural := 27; -- r/-: current state of CTS input + constant ctrl_en_c : natural := 28; -- r/w: UART enable + constant ctrl_rx_irq_c : natural := 29; -- r/w: RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty + constant ctrl_tx_irq_c : natural := 30; -- r/w: TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full + constant ctrl_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy + + -- data register flags -- + constant data_lsb_c : natural := 0; -- r/-: received char LSB + constant data_msb_c : natural := 7; -- r/-: received char MSB + -- ... + constant data_rx_perr_c : natural := 28; -- r/-: RX parity error + constant data_rx_ferr_c : natural := 29; -- r/-: RX frame error + constant data_rx_overr_c : natural := 30; -- r/-: RX data overrun + constant data_rx_avail_c : natural := 31; -- r/-: RX data available + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- clock generator -- + signal uart_clk : std_ulogic; + + -- numbers of bits in transmission frame -- + signal num_bits : std_ulogic_vector(3 downto 0); + + -- hardware flow-control IO buffer -- + signal uart_cts_ff : std_ulogic_vector(1 downto 0); + signal uart_rts : std_ulogic; + + -- UART transmitter -- + type tx_state_t is (S_TX_IDLE, S_TX_GET, S_TX_CHECK, S_TX_TRANSMIT, S_TX_SIM); + type tx_engine_t is record + state : tx_state_t; + busy : std_ulogic; + done : std_ulogic; + bitcnt : std_ulogic_vector(03 downto 0); + sreg : std_ulogic_vector(10 downto 0); + baud_cnt : std_ulogic_vector(11 downto 0); + cts : std_ulogic; -- allow new transmission when 1 + end record; + signal tx_engine : tx_engine_t; + + -- UART receiver -- + type rx_state_t is (S_RX_IDLE, S_RX_RECEIVE); + type rx_engine_t is record + state : rx_state_t; + done : std_ulogic; + sync : std_ulogic_vector(04 downto 0); + bitcnt : std_ulogic_vector(03 downto 0); + sreg : std_ulogic_vector(09 downto 0); + baud_cnt : std_ulogic_vector(11 downto 0); + overr : std_ulogic; + rtr : std_ulogic; -- ready to receive when 1 + end record; + signal rx_engine : rx_engine_t; + + -- TX FIFO -- + type tx_buffer_t is record + we : std_ulogic; -- write enable + re : std_ulogic; -- read enable + clear : std_ulogic; -- sync reset, high-active + wdata : std_ulogic_vector(31 downto 0); -- write data + rdata : std_ulogic_vector(31 downto 0); -- read data + avail : std_ulogic; -- data available? + free : std_ulogic; -- free entry available? + half : std_ulogic; -- half full + end record; + signal tx_buffer : tx_buffer_t; + + -- RX FIFO -- + type rx_buffer_t is record + we : std_ulogic; -- write enable + re : std_ulogic; -- read enable + clear : std_ulogic; -- sync reset, high-active + wdata : std_ulogic_vector(9 downto 0); -- write data + rdata : std_ulogic_vector(9 downto 0); -- read data + avail : std_ulogic; -- data available? + free : std_ulogic; -- free entry available? + half : std_ulogic; -- half full + end record; + signal rx_buffer : rx_buffer_t; + + -- interrupt generator -- + type irq_t is record + set : std_ulogic; + buf : std_ulogic_vector(1 downto 0); + end record; + signal rx_irq, tx_irq : irq_t; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (is_power_of_two_f(UART_RX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: UART" & + cond_sel_string_f(UART_PRIMARY, "0", "1") & " has to be a power of two." severity error; + assert not (is_power_of_two_f(UART_TX_FIFO) = false) report "NEORV32 PROCESSOR CONFIG ERROR: UART" & + cond_sel_string_f(UART_PRIMARY, "0", "1") & " has to be a power of two." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = uart_id_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= uart_id_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- bus access acknowledge -- + ack_o <= wren or rden; + + -- write access -- + if (wren = '1') then + if (addr = uart_id_ctrl_addr_c) then + ctrl <= (others => '0'); + ctrl(ctrl_baud11_c downto ctrl_baud00_c) <= data_i(ctrl_baud11_c downto ctrl_baud00_c); + ctrl(ctrl_sim_en_c) <= data_i(ctrl_sim_en_c); + ctrl(ctrl_pmode1_c downto ctrl_pmode0_c) <= data_i(ctrl_pmode1_c downto ctrl_pmode0_c); + ctrl(ctrl_prsc2_c downto ctrl_prsc0_c) <= data_i(ctrl_prsc2_c downto ctrl_prsc0_c); + ctrl(ctrl_rts_en_c) <= data_i(ctrl_rts_en_c); + ctrl(ctrl_cts_en_c) <= data_i(ctrl_cts_en_c); + ctrl(ctrl_rx_irq_c) <= data_i(ctrl_rx_irq_c); + ctrl(ctrl_tx_irq_c) <= data_i(ctrl_tx_irq_c); + ctrl(ctrl_en_c) <= data_i(ctrl_en_c); + end if; + end if; + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + if (addr = uart_id_ctrl_addr_c) then + data_o(ctrl_baud11_c downto ctrl_baud00_c) <= ctrl(ctrl_baud11_c downto ctrl_baud00_c); + data_o(ctrl_sim_en_c) <= ctrl(ctrl_sim_en_c); + data_o(ctrl_pmode1_c downto ctrl_pmode0_c) <= ctrl(ctrl_pmode1_c downto ctrl_pmode0_c); + data_o(ctrl_prsc2_c downto ctrl_prsc0_c) <= ctrl(ctrl_prsc2_c downto ctrl_prsc0_c); + data_o(ctrl_rts_en_c) <= ctrl(ctrl_rts_en_c); + data_o(ctrl_cts_en_c) <= ctrl(ctrl_cts_en_c); + data_o(ctrl_rx_empty_c) <= not rx_buffer.avail; + data_o(ctrl_rx_half_c) <= rx_buffer.half; + data_o(ctrl_rx_full_c) <= not rx_buffer.free; + data_o(ctrl_tx_empty_c) <= not tx_buffer.avail; + data_o(ctrl_tx_half_c) <= tx_buffer.half; + data_o(ctrl_tx_full_c) <= not tx_buffer.free; + data_o(ctrl_en_c) <= ctrl(ctrl_en_c); + data_o(ctrl_rx_irq_c) <= ctrl(ctrl_rx_irq_c) and bool_to_ulogic_f(boolean(UART_RX_FIFO > 1)); -- tie to zero if UART_RX_FIFO = 1 + data_o(ctrl_tx_irq_c) <= ctrl(ctrl_tx_irq_c) and bool_to_ulogic_f(boolean(UART_TX_FIFO > 1)); -- tie to zero if UART_TX_FIFO = 1 + data_o(ctrl_tx_busy_c) <= tx_engine.busy; + data_o(ctrl_cts_c) <= uart_cts_ff(1); + else -- uart_id_rtx_addr_c + data_o(data_msb_c downto data_lsb_c) <= rx_buffer.rdata(7 downto 0); + data_o(data_rx_perr_c) <= rx_buffer.rdata(8); + data_o(data_rx_ferr_c) <= rx_buffer.rdata(9); + data_o(data_rx_overr_c) <= rx_engine.overr; + data_o(data_rx_avail_c) <= rx_buffer.avail; -- data available (valid?) + end if; + end if; + end if; + end process rw_access; + + -- number of bits to be sampled -- + -- if parity flag is ENABLED: 11 bit -> "1011" (1 start bit + 8 data bits + 1 parity bit + 1 stop bit) + -- if parity flag is DISABLED: 10 bit -> "1010" (1 start bit + 8 data bits + 1 stop bit) + num_bits <= "1011" when (ctrl(ctrl_pmode1_c) = '1') else "1010"; + + + -- Clock Selection ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + -- clock enable -- + clkgen_en_o <= ctrl(ctrl_en_c); + + -- uart clock select -- + uart_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c)))); + + + -- TX FIFO -------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + tx_engine_fifo_inst: neorv32_fifo + generic map ( + FIFO_DEPTH => UART_TX_FIFO, -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH => 32, -- size of data elements in fifo (32-bit only for simulation) + FIFO_RSYNC => false, -- async read + FIFO_SAFE => true -- safe access + ) + port map ( + -- control -- + clk_i => clk_i, -- clock, rising edge + rstn_i => '1', -- async reset, low-active + clear_i => tx_buffer.clear, -- sync reset, high-active + level_o => open, + half_o => tx_buffer.half, -- FIFO at least half-full + -- write port -- + wdata_i => tx_buffer.wdata, -- write data + we_i => tx_buffer.we, -- write enable + free_o => tx_buffer.free, -- at least one entry is free when set + -- read port -- + re_i => tx_buffer.re, -- read enable + rdata_o => tx_buffer.rdata, -- read data + avail_o => tx_buffer.avail -- data available when set + ); + + -- control -- + tx_buffer.clear <= not ctrl(ctrl_en_c); + + -- write access -- + tx_buffer.we <= '1' when (wren = '1') and (addr = uart_id_rtx_addr_c) else '0'; + tx_buffer.wdata <= data_i; + + + -- UART Transmitter Engine ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + uart_tx_engine: process(clk_i) + begin + if rising_edge(clk_i) then + -- defaults -- + uart_txd_o <= '1'; -- keep TX line idle (=high) if waiting for permission to start sending (->CTS) + tx_buffer.re <= '0'; + tx_engine.done <= '0'; + + -- FSM -- + if (ctrl(ctrl_en_c) = '0') then -- disabled + tx_engine.state <= S_TX_IDLE; + else + case tx_engine.state is + + when S_TX_IDLE => -- wait for new data to send + -- ------------------------------------------------------------ + if (tx_buffer.avail = '1') then -- new data available + if (ctrl(ctrl_sim_en_c) = '0') then -- normal mode + tx_engine.state <= S_TX_GET; + else -- simulation mode + tx_engine.state <= S_TX_SIM; + end if; + tx_buffer.re <= '1'; + end if; + + when S_TX_GET => -- get new data from buffer and prepare transmission + -- ------------------------------------------------------------ + tx_engine.baud_cnt <= ctrl(ctrl_baud11_c downto ctrl_baud00_c); + tx_engine.bitcnt <= num_bits; + if (ctrl(ctrl_pmode1_c) = '1') then -- add parity flag + -- stop bit & parity bit & data (8-bit) & start bit + tx_engine.sreg <= '1' & (xor_reduce_f(tx_buffer.rdata(7 downto 0)) xor ctrl(ctrl_pmode0_c)) & tx_buffer.rdata(7 downto 0) & '0'; + else + -- (dummy fill-bit &) stop bit & data (8-bit) & start bit + tx_engine.sreg <= '1' & '1' & tx_buffer.rdata(7 downto 0) & '0'; + end if; + tx_engine.state <= S_TX_CHECK; + + when S_TX_CHECK => -- check if allowed to send + -- ------------------------------------------------------------ + if (tx_engine.cts = '1') then -- clear to send + tx_engine.state <= S_TX_TRANSMIT; + end if; + + when S_TX_TRANSMIT => -- transmit data + -- ------------------------------------------------------------ + if (uart_clk = '1') then + if (or_reduce_f(tx_engine.baud_cnt) = '0') then -- bit done? + tx_engine.baud_cnt <= ctrl(ctrl_baud11_c downto ctrl_baud00_c); + tx_engine.bitcnt <= std_ulogic_vector(unsigned(tx_engine.bitcnt) - 1); + tx_engine.sreg <= '1' & tx_engine.sreg(tx_engine.sreg'left downto 1); + else + tx_engine.baud_cnt <= std_ulogic_vector(unsigned(tx_engine.baud_cnt) - 1); + end if; + end if; + uart_txd_o <= tx_engine.sreg(0); + if (or_reduce_f(tx_engine.bitcnt) = '0') then -- all bits send? + tx_engine.done <= '1'; -- sending done + tx_engine.state <= S_TX_IDLE; + end if; + + when S_TX_SIM => -- simulation mode output + -- ------------------------------------------------------------ + tx_engine.state <= S_TX_IDLE; + + when others => -- undefined + -- ------------------------------------------------------------ + tx_engine.state <= S_TX_IDLE; + + end case; + end if; + end if; + end process uart_tx_engine; + + -- transmitter busy -- + tx_engine.busy <= '0' when (tx_engine.state = S_TX_IDLE) else '1'; + + + -- UART Receiver Engine ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + uart_rx_engine: process(clk_i) + begin + if rising_edge(clk_i) then + -- input synchronizer -- + rx_engine.sync <= uart_rxd_i & rx_engine.sync(rx_engine.sync'left downto 1); + + -- default -- + rx_engine.done <= '0'; + + -- FSM -- + if (ctrl(ctrl_en_c) = '0') then -- disabled + rx_engine.overr <= '0'; + rx_engine.state <= S_RX_IDLE; + else + case rx_engine.state is + + when S_RX_IDLE => -- idle; prepare receive + -- ------------------------------------------------------------ + rx_engine.baud_cnt <= '0' & ctrl(ctrl_baud11_c downto ctrl_baud01_c); -- half baud delay at the beginning to sample in the middle of each bit + rx_engine.bitcnt <= num_bits; + if (rx_engine.sync(3 downto 0) = "0011") then -- start bit? (falling edge) + rx_engine.state <= S_RX_RECEIVE; + end if; + + when S_RX_RECEIVE => -- receive data + -- ------------------------------------------------------------ + if (uart_clk = '1') then + if (or_reduce_f(rx_engine.baud_cnt) = '0') then -- bit done + rx_engine.baud_cnt <= ctrl(ctrl_baud11_c downto ctrl_baud00_c); + rx_engine.bitcnt <= std_ulogic_vector(unsigned(rx_engine.bitcnt) - 1); + rx_engine.sreg <= rx_engine.sync(2) & rx_engine.sreg(rx_engine.sreg'left downto 1); + else + rx_engine.baud_cnt <= std_ulogic_vector(unsigned(rx_engine.baud_cnt) - 1); + end if; + end if; + if (or_reduce_f(rx_engine.bitcnt) = '0') then -- all bits received? + rx_engine.done <= '1'; -- receiving done + rx_engine.state <= S_RX_IDLE; + end if; + + when others => -- undefined + -- ------------------------------------------------------------ + rx_engine.state <= S_RX_IDLE; + + end case; + + -- overrun flag -- + if (rden = '1') and (addr = uart_id_rtx_addr_c) then -- clear when reading data register + rx_engine.overr <= '0'; + elsif (rx_buffer.we = '1') and (rx_buffer.free = '0') then -- write to full FIFO + rx_engine.overr <= '1'; + end if; + end if; + end if; + end process uart_rx_engine; + + -- RX engine ready for a new char? -- + rx_engine.rtr <= '1' when (rx_engine.state = S_RX_IDLE) and (ctrl(ctrl_en_c) = '1') else '0'; + + + -- RX FIFO -------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rx_engine_fifo_inst: neorv32_fifo + generic map ( + FIFO_DEPTH => UART_RX_FIFO, -- number of fifo entries; has to be a power of two; min 1 + FIFO_WIDTH => 10, -- size of data elements in fifo + FIFO_RSYNC => false, -- async read + FIFO_SAFE => true -- safe access + ) + port map ( + -- control -- + clk_i => clk_i, -- clock, rising edge + rstn_i => '1', -- async reset, low-active + clear_i => rx_buffer.clear, -- sync reset, high-active + level_o => open, + half_o => rx_buffer.half, -- FIFO at least half-full + -- write port -- + wdata_i => rx_buffer.wdata, -- write data + we_i => rx_buffer.we, -- write enable + free_o => rx_buffer.free, -- at least one entry is free when set + -- read port -- + re_i => rx_buffer.re, -- read enable + rdata_o => rx_buffer.rdata, -- read data + avail_o => rx_buffer.avail -- data available when set + ); + + -- control -- + rx_buffer.clear <= not ctrl(ctrl_en_c); + + -- read/write access -- + rx_buffer.wdata(7 downto 0) <= rx_engine.sreg(7 downto 0) when (ctrl(ctrl_pmode1_c) = '1') else rx_engine.sreg(8 downto 1); -- RX data + rx_buffer.wdata(8) <= ctrl(ctrl_pmode1_c) and (xor_reduce_f(rx_engine.sreg(8 downto 0)) xor ctrl(ctrl_pmode0_c)); -- parity error flag + rx_buffer.wdata(9) <= not rx_engine.sreg(9); -- frame error flag: check stop bit (error if not set) + rx_buffer.we <= '1' when (rx_engine.bitcnt = "0000") and (rx_engine.state = S_RX_RECEIVE) else '0'; -- RX complete + rx_buffer.re <= '1' when (rden = '1') and (addr = uart_id_rtx_addr_c) else '0'; + + + -- Hardware Flow Control ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + tx_engine.cts <= (not uart_cts_ff(1)) when (ctrl(ctrl_cts_en_c) = '1') else '1'; -- input is low-active, internal signal is high-active + uart_rts <= (not rx_engine.rtr) when (ctrl(ctrl_rts_en_c) = '1') else '0'; -- output is low-active + + -- flow-control input/output synchronizer -- + flow_control_buffer: process(clk_i) + begin + if rising_edge(clk_i) then -- should be mapped to IOBs + uart_cts_ff <= uart_cts_ff(0) & uart_cts_i; + uart_rts_o <= uart_rts; + end if; + end process flow_control_buffer; + + + -- Interrupt Generator -------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + irq_type: process(ctrl, tx_buffer, rx_buffer, tx_engine.done) + begin + -- TX interrupt -- + if (UART_TX_FIFO = 1) or (ctrl(ctrl_tx_irq_c) = '0') then + tx_irq.set <= tx_buffer.free and tx_engine.done; -- fire IRQ if FIFO is not full + else + tx_irq.set <= (not tx_buffer.half) and tx_engine.done; -- fire IRQ if FIFO is less than half-full + end if; + -- RX interrupt -- + if (UART_RX_FIFO = 1) or (ctrl(ctrl_rx_irq_c) = '0') then + rx_irq.set <= rx_buffer.avail; -- fire IRQ if FIFO is not empty + else + rx_irq.set <= rx_buffer.half; -- fire IRQ if FIFO is at least half-full + end if; + end process irq_type; + + -- interrupt edge detector -- + irq_detect: process(clk_i) + begin + if rising_edge(clk_i) then + if (ctrl(ctrl_en_c) = '0') then + tx_irq.buf <= "00"; + rx_irq.buf <= "00"; + else + tx_irq.buf <= tx_irq.buf(0) & tx_irq.set; + rx_irq.buf <= rx_irq.buf(0) & rx_irq.set; + end if; + end if; + end process irq_detect; + + -- IRQ requests to CPU -- + irq_txd_o <= '1' when (tx_irq.buf = "01") else '0'; + irq_rxd_o <= '1' when (rx_irq.buf = "01") else '0'; + + + -- SIMULATION Transmitter ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- +-- pragma translate_off +-- synthesis translate_off +-- RTL_SYNTHESIS OFF + sim_output: process(clk_i) -- for SIMULATION ONLY! + file file_uart_text_out : text open write_mode is sim_uart_text_file_c; + file file_uart_data_out : text open write_mode is sim_uart_data_file_c; + variable char_v : integer; + variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable + variable line_text_v : line; + variable line_data_v : line; + begin + if rising_edge(clk_i) then + if (tx_engine.state = S_TX_SIM) then -- UART simulation mode + + -- print lowest byte as ASCII char -- + char_v := to_integer(unsigned(tx_buffer.rdata(7 downto 0))); + if (char_v >= 128) then -- out of range? + char_v := 0; + end if; + + if (char_v /= 10) and (char_v /= 13) then -- skip line breaks - they are issued via "writeline" + if (sim_screen_output_en_c = true) then + write(line_screen_v, character'val(char_v)); + end if; + if (sim_text_output_en_c = true) then + write(line_text_v, character'val(char_v)); + end if; + end if; + + if (char_v = 10) then -- line break: write to screen and text file + if (sim_screen_output_en_c = true) then + writeline(output, line_screen_v); + end if; + if (sim_text_output_en_c = true) then + writeline(file_uart_text_out, line_text_v); + end if; + end if; + + -- dump raw data as 8 hex chars to file -- + if (sim_data_output_en_c = true) then + for x in 7 downto 0 loop + write(line_data_v, to_hexchar_f(tx_buffer.rdata(3+x*4 downto 0+x*4))); -- write in hex form + end loop; -- x + writeline(file_uart_data_out, line_data_v); + end if; + + end if; + end if; + end process sim_output; +-- RTL_SYNTHESIS ON +-- synthesis translate_on +-- pragma translate_on + +end neorv32_uart_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_wdt.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_wdt.vhd new file mode 100644 index 0000000..3d0e79a --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_wdt.vhd @@ -0,0 +1,244 @@ +-- ################################################################################################# +-- # << NEORV32 - Watch Dog Timer (WDT) >> # +-- # ********************************************************************************************* # +-- # Watchdog counter to trigger an action if the CPU gets stuck. # +-- # The internal counter is 20-bit wide. If this counter overflows one of two possible actions is # +-- # triggered: Generate an IRQ or force a hardware reset of the system. # +-- # A WDT action can also be triggered manually at any time by setting the FORCE bit. # +-- # # +-- # Access to the control register can be permanently locked by setting the lock bit. This bit # +-- # can only be cleared by a hardware reset (external or caused by the watchdog itself). # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_wdt is + generic ( + DEBUG_EN : boolean -- CPU debug mode implemented? + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- CPU in debug mode? -- + cpu_debug_i : in std_ulogic; + -- clock generator -- + clkgen_en_o : out std_ulogic; -- enable clock generator + clkgen_i : in std_ulogic_vector(07 downto 0); + -- timeout event -- + irq_o : out std_ulogic; -- timeout IRQ + rstn_o : out std_ulogic -- timeout reset, low_active, use as async + ); +end neorv32_wdt; + +architecture neorv32_wdt_rtl of neorv32_wdt is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(wdt_size_c); -- low address boundary bit + + -- Control register bits -- + constant ctrl_enable_c : natural := 0; -- r/w: WDT enable + constant ctrl_clksel0_c : natural := 1; -- r/w: prescaler select bit 0 + constant ctrl_clksel1_c : natural := 2; -- r/w: prescaler select bit 1 + constant ctrl_clksel2_c : natural := 3; -- r/w: prescaler select bit 2 + constant ctrl_mode_c : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset + constant ctrl_rcause_c : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow + constant ctrl_reset_c : natural := 6; -- -/w: reset WDT if set + constant ctrl_force_c : natural := 7; -- -/w: force WDT action + constant ctrl_lock_c : natural := 8; -- r/w: lock access to control register when set + constant ctrl_dben_c : natural := 9; -- r/w: allow WDT to continue operation even when in debug mode + constant ctrl_half_c : natural := 10; -- r/-: set if at least half of the max. timeout counter value has been reached + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal wren : std_ulogic; + signal rden : std_ulogic; + + -- control register -- + type ctrl_t is record + enable : std_ulogic; -- 1=WDT enabled + clk_sel : std_ulogic_vector(2 downto 0); + mode : std_ulogic; -- 0=trigger IRQ on overflow; 1=trigger hard reset on overflow + rcause : std_ulogic; -- cause of last system reset: '0' = external, '1' = watchdog + reset : std_ulogic; -- reset WDT + enforce : std_ulogic; -- force action + lock : std_ulogic; -- lock control register + dben : std_ulogic; -- allow operation also in debug mode + end record; + signal ctrl : ctrl_t; + + -- prescaler clock generator -- + signal prsc_tick : std_ulogic; + + -- WDT core -- + signal wdt_cnt : std_ulogic_vector(20 downto 0); + signal hw_rst : std_ulogic; + signal rst_gen : std_ulogic_vector(03 downto 0); + signal cnt_en : std_ulogic; + + -- internal reset (sync, low-active) -- + signal rstn_sync : std_ulogic; + +begin + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0'; + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Write Access --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + write_access: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl.reset <= '1'; -- reset counter on start-up + ctrl.enforce <= '0'; + ctrl.enable <= '0'; -- disable WDT + ctrl.mode <= '0'; + ctrl.clk_sel <= (others => '0'); + ctrl.lock <= '0'; + ctrl.dben <= '0'; + elsif rising_edge(clk_i) then + if (rstn_sync = '0') then -- internal reset + ctrl.reset <= '1'; -- reset counter on start-up + ctrl.enforce <= '0'; + ctrl.enable <= '0'; -- disable WDT + ctrl.mode <= '0'; + ctrl.clk_sel <= (others => '0'); + ctrl.lock <= '0'; + ctrl.dben <= '0'; + else + -- auto-clear WDT reset and WDT force flags -- + ctrl.reset <= '0'; + ctrl.enforce <= '0'; + -- actual write access -- + if (wren = '1') then + ctrl.reset <= data_i(ctrl_reset_c); + ctrl.enforce <= data_i(ctrl_force_c); + if (ctrl.lock = '0') then -- update configuration only if not locked + ctrl.enable <= data_i(ctrl_enable_c); + ctrl.mode <= data_i(ctrl_mode_c); + ctrl.clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c); + ctrl.lock <= data_i(ctrl_lock_c); + ctrl.dben <= data_i(ctrl_dben_c) and bool_to_ulogic_f(DEBUG_EN); + end if; + end if; + end if; + end if; + end process write_access; + + -- clock generator -- + clkgen_en_o <= ctrl.enable; -- enable clock generator + prsc_tick <= clkgen_i(to_integer(unsigned(ctrl.clk_sel))); -- clock enable tick + + + -- Watchdog Counter ----------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + wdt_counter: process(clk_i) + begin + if rising_edge(clk_i) then + if (ctrl.reset = '1') then -- watchdog reset + wdt_cnt <= (others => '0'); + elsif (cnt_en = '1') then + wdt_cnt <= std_ulogic_vector(unsigned('0' & wdt_cnt(wdt_cnt'left-1 downto 0)) + 1); + end if; + end if; + end process wdt_counter; + + -- WDT counter enable -- + cnt_en <= ctrl.enable and prsc_tick and ((not cpu_debug_i) or ctrl.dben); + + -- action trigger -- + irq_o <= ctrl.enable and (wdt_cnt(wdt_cnt'left) or ctrl.enforce) and (not ctrl.mode); -- mode 0: IRQ + hw_rst <= ctrl.enable and (wdt_cnt(wdt_cnt'left) or ctrl.enforce) and ( ctrl.mode); -- mode 1: RESET + + + -- Reset Generator & Action Cause Indicator ----------------------------------------------- + -- ------------------------------------------------------------------------------------------- + reset_generator: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl.rcause <= '0'; + rst_gen <= (others => '1'); -- do NOT fire on reset! + rstn_sync <= '1'; + elsif rising_edge(clk_i) then + ctrl.rcause <= ctrl.rcause or hw_rst; -- sticky-set on WDT timeout/force + if (hw_rst = '1') then + rst_gen <= (others => '0'); + else + rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1'; + end if; + rstn_sync <= rst_gen(rst_gen'left); + end if; + end process reset_generator; + + -- system reset -- + rstn_o <= rst_gen(rst_gen'left); + + + -- Read Access ---------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + read_access: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= rden or wren; + if (rden = '1') then + data_o(ctrl_enable_c) <= ctrl.enable; + data_o(ctrl_mode_c) <= ctrl.mode; + data_o(ctrl_rcause_c) <= ctrl.rcause; + data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_sel; + data_o(ctrl_lock_c) <= ctrl.lock; + data_o(ctrl_dben_c) <= ctrl.dben; + data_o(ctrl_half_c) <= wdt_cnt(wdt_cnt'left-1); + else + data_o <= (others => '0'); + end if; + end if; + end process read_access; + + +end neorv32_wdt_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_wishbone.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_wishbone.vhd new file mode 100644 index 0000000..cb9913d --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_wishbone.vhd @@ -0,0 +1,274 @@ +-- ################################################################################################# +-- # << NEORV32 - External Bus Interface (WISHBONE) >> # +-- # ********************************************************************************************* # +-- # All bus accesses from the CPU, which do not target the internal IO region / the internal # +-- # bootloader / the internal instruction or data memories (if implemented), are delegated via # +-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response # +-- # latency of up to BUS_TIMEOUT - 1 cycles. # +-- # # +-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address # +-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_wishbone is + generic ( + -- Internal instruction memory -- + MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes + -- Internal data memory -- + MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes + -- Interface Configuration -- + BUS_TIMEOUT : natural; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception + PIPE_MODE : boolean; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian + ASYNC_RX : boolean -- use register buffer for RX data when false + ); + port ( + -- global control -- + clk_i : in std_ulogic; -- global clock line + rstn_i : in std_ulogic; -- global reset line, low-active + -- host access -- + src_i : in std_ulogic; -- access type (0: data, 1:instruction) + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + lock_i : in std_ulogic; -- exclusive access request + ack_o : out std_ulogic; -- transfer acknowledge + err_o : out std_ulogic; -- transfer error + tmo_o : out std_ulogic; -- transfer timeout + priv_i : in std_ulogic_vector(01 downto 0); -- current CPU privilege level + ext_o : out std_ulogic; -- active external access + -- wishbone interface -- + wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag + wb_adr_o : out std_ulogic_vector(31 downto 0); -- address + wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data + wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data + wb_we_o : out std_ulogic; -- read/write + wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable + wb_stb_o : out std_ulogic; -- strobe + wb_cyc_o : out std_ulogic; -- valid cycle + wb_lock_o : out std_ulogic; -- exclusive access request + wb_ack_i : in std_ulogic; -- transfer acknowledge + wb_err_i : in std_ulogic -- transfer error + ); +end neorv32_wishbone; + +architecture neorv32_wishbone_rtl of neorv32_wishbone is + + -- timeout enable -- + constant timeout_en_c : boolean := boolean(BUS_TIMEOUT /= 0); -- timeout enabled if BUS_TIMEOUT > 0 + + -- access control -- + signal int_imem_acc : std_ulogic; + signal int_dmem_acc : std_ulogic; + signal int_boot_acc : std_ulogic; + signal xbus_access : std_ulogic; + + -- bus arbiter + type ctrl_state_t is (IDLE, BUSY); + type ctrl_t is record + state : ctrl_state_t; + state_ff : ctrl_state_t; + we : std_ulogic; + adr : std_ulogic_vector(31 downto 0); + wdat : std_ulogic_vector(31 downto 0); + rdat : std_ulogic_vector(31 downto 0); + sel : std_ulogic_vector(03 downto 0); + ack : std_ulogic; + err : std_ulogic; + tmo : std_ulogic; + timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT) downto 0); + src : std_ulogic; + lock : std_ulogic; + priv : std_ulogic_vector(01 downto 0); + end record; + signal ctrl : ctrl_t; + signal stb_int : std_ulogic; + signal cyc_int : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + + -- async RX mode -- + signal ack_gated : std_ulogic; + signal rdata_gated : std_ulogic_vector(31 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- protocol -- + assert not (PIPE_MODE = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing STANDARD Wishbone protocol." severity note; + assert not (PIPE_MODE = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing PIEPLINED Wishbone protocol." severity note; + + -- bus timeout -- + assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing auto-timeout (" & integer'image(BUS_TIMEOUT) & " cycles)." severity note; + assert not (BUS_TIMEOUT = 0) report "NEORV32 PROCESSOR CONFIG WARNING: External Bus Interface - Implementing NO auto-timeout (can cause permanent CPU stall!)." severity warning; + + -- endianness -- + assert not (BIG_ENDIAN = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing LITTLE-endian byte order." severity note; + assert not (BIG_ENDIAN = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing BIG-endian byte." severity note; + + -- async RX -- + assert not (ASYNC_RX = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing registered RX path." severity note; + assert not (ASYNC_RX = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing ASYNC RX path." severity note; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- access to processor-internal IMEM or DMEM? -- + int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_EN = true) else '0'; + int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_EN = true) else '0'; + -- access to processor-internal BOOTROM or IO devices? -- + int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky! + -- actual external bus access? -- + xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc); + + + -- Bus Arbiter ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + bus_arbiter: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + ctrl.state <= IDLE; + ctrl.state_ff <= IDLE; + ctrl.we <= def_rst_val_c; + ctrl.adr <= (others => def_rst_val_c); + ctrl.wdat <= (others => def_rst_val_c); + ctrl.rdat <= (others => def_rst_val_c); + ctrl.sel <= (others => def_rst_val_c); + ctrl.timeout <= (others => def_rst_val_c); + ctrl.ack <= def_rst_val_c; + ctrl.err <= def_rst_val_c; + ctrl.tmo <= def_rst_val_c; + ctrl.src <= def_rst_val_c; + ctrl.lock <= def_rst_val_c; + ctrl.priv <= (others => def_rst_val_c); + elsif rising_edge(clk_i) then + -- defaults -- + ctrl.state_ff <= ctrl.state; + ctrl.rdat <= (others => '0'); -- required for internal output gating + ctrl.ack <= '0'; + ctrl.err <= '0'; + ctrl.tmo <= '0'; + ctrl.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)+1)); + + -- state machine -- + case ctrl.state is + + when IDLE => -- waiting for host request + -- ------------------------------------------------------------ + -- buffer all outgoing signals -- + ctrl.we <= wren_i; + ctrl.adr <= addr_i; + if (BIG_ENDIAN = true) then -- big-endian + ctrl.wdat <= bswap32_f(data_i); + ctrl.sel <= bit_rev_f(ben_i); + else -- little-endian + ctrl.wdat <= data_i; + ctrl.sel <= ben_i; + end if; + ctrl.src <= src_i; + ctrl.lock <= lock_i; + ctrl.priv <= priv_i; + -- valid new or buffered read/write request -- + if ((xbus_access and (wren_i or rden_i)) = '1') then + ctrl.state <= BUSY; + end if; + + when BUSY => -- transfer in progress + -- ------------------------------------------------------------ + ctrl.rdat <= wb_dat_i; + if (wb_err_i = '1') then -- abnormal bus termination + ctrl.err <= '1'; + ctrl.state <= IDLE; + elsif (timeout_en_c = true) and (or_reduce_f(ctrl.timeout) = '0') then -- enabled timeout + ctrl.tmo <= '1'; + ctrl.state <= IDLE; + elsif (wb_ack_i = '1') then -- normal bus termination + ctrl.ack <= '1'; + ctrl.state <= IDLE; + end if; + -- timeout counter -- + if (timeout_en_c = true) then + ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter + end if; + + when others => -- undefined + -- ------------------------------------------------------------ + ctrl.state <= IDLE; + + end case; + end if; + end process bus_arbiter; + + -- host access -- + ack_gated <= wb_ack_i when (ctrl.state = BUSY) else '0'; -- CPU ack gate for "async" RX + rdata_gated <= wb_dat_i when (ctrl.state = BUSY) else (others => '0'); -- CPU read data gate for "async" RX + rdata <= ctrl.rdat when (ASYNC_RX = false) else rdata_gated; + + ext_o <= '1' when (ctrl.state = BUSY) else '0'; -- active external access + + data_o <= rdata when (BIG_ENDIAN = false) else bswap32_f(rdata); -- endianness conversion + ack_o <= ctrl.ack when (ASYNC_RX = false) else ack_gated; + err_o <= ctrl.err; + tmo_o <= ctrl.tmo; + + -- wishbone interface -- + wb_tag_o(0) <= '0' when (ctrl.priv = priv_mode_u_c) else '1'; -- unprivileged access when in user mode + wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure + wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access + + wb_lock_o <= ctrl.lock; -- 1 = exclusive access request + + wb_adr_o <= ctrl.adr; + wb_dat_o <= ctrl.wdat; + wb_we_o <= ctrl.we; + wb_sel_o <= ctrl.sel; + wb_stb_o <= stb_int when (PIPE_MODE = true) else cyc_int; + wb_cyc_o <= cyc_int; + + stb_int <= '1' when (ctrl.state = BUSY) and (ctrl.state_ff /= BUSY) else '0'; + cyc_int <= '1' when (ctrl.state = BUSY) else '0'; + + +end neorv32_wishbone_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/core/neorv32_xirq.vhd b/Libs/RiscV/NEORV32/rtl/core/neorv32_xirq.vhd new file mode 100644 index 0000000..9192ba1 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/core/neorv32_xirq.vhd @@ -0,0 +1,229 @@ +-- ################################################################################################# +-- # << NEORV32 - External Interrupt Controller (XIRQ) >> # +-- # ********************************************************************************************* # +-- # Simple interrupt controller for platform (processor-external) interrupts. Up to 32 channels # +-- # are supported that get (optionally) prioritized into a single CPU interrupt. # +-- # # +-- # The actual trigger configuration has to be done BEFORE synthesis using the XIRQ_TRIGGER_TYPE # +-- # and XIRQ_TRIGGER_POLARITY generics. These allow to configure channel-independent low-level, # +-- # high-level, falling-edge and rising-edge triggers. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_xirq is + generic ( + XIRQ_NUM_CH : natural; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0); -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + ); + port ( + -- host access -- + clk_i : in std_ulogic; -- global clock line + addr_i : in std_ulogic_vector(31 downto 0); -- address + rden_i : in std_ulogic; -- read enable + wren_i : in std_ulogic; -- write enable + data_i : in std_ulogic_vector(31 downto 0); -- data in + data_o : out std_ulogic_vector(31 downto 0); -- data out + ack_o : out std_ulogic; -- transfer acknowledge + -- external interrupt lines -- + xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + -- CPU interrupt -- + cpu_irq_o : out std_ulogic + ); +end neorv32_xirq; + +architecture neorv32_xirq_rtl of neorv32_xirq is + + -- IO space: module base address -- + constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(xirq_size_c); -- low address boundary bit + + -- access control -- + signal acc_en : std_ulogic; -- module access enable + signal addr : std_ulogic_vector(31 downto 0); -- access address + signal wren : std_ulogic; -- word write enable + signal rden : std_ulogic; -- read enable + + -- control registers -- + signal irq_enable : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: interrupt enable + signal clr_pending : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); -- r/w: clear pending IRQs + signal irq_src : std_ulogic_vector(4 downto 0); -- r/w: source IRQ, ACK on any write + + -- interrupt trigger -- + signal irq_sync : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + signal irq_sync2 : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + signal irq_trig : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + + -- interrupt buffer -- + signal irq_buf : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + signal irq_fire : std_ulogic; + + -- interrupt source -- + signal irq_src_nxt : std_ulogic_vector(4 downto 0); + + -- arbiter -- + signal irq_run : std_ulogic; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not ((XIRQ_NUM_CH < 0) or (XIRQ_NUM_CH > 32)) report "NEORV32 PROCESSOR CONFIG ERROR: Number of XIRQ inputs has to be 0..32." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = xirq_base_c(hi_abb_c downto lo_abb_c)) else '0'; + addr <= xirq_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned + wren <= acc_en and wren_i; + rden <= acc_en and rden_i; + + + -- Read/Write Access ---------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + rw_access: process(clk_i) + begin + if rising_edge(clk_i) then + -- bus handshake -- + ack_o <= rden or wren; + + -- write access -- + clr_pending <= (others => '1'); + if (wren = '1') then + -- channel-enable -- + if (addr = xirq_enable_addr_c) then + irq_enable <= data_i(XIRQ_NUM_CH-1 downto 0); + end if; + -- clear pending IRQs -- + if (addr = xirq_pending_addr_c) then + clr_pending <= data_i(XIRQ_NUM_CH-1 downto 0); -- set zero to clear pending IRQ + end if; + end if; + + -- read access -- + data_o <= (others => '0'); + if (rden = '1') then + case addr is + when xirq_enable_addr_c => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_enable; -- channel-enable + when xirq_pending_addr_c => data_o(XIRQ_NUM_CH-1 downto 0) <= irq_buf; -- pending IRQs + when xirq_source_addr_c => data_o(4 downto 0) <= irq_src; -- source IRQ + when others => NULL; + end case; + end if; + end if; + end process rw_access; + + + -- IRQ Trigger -------------------------------------------------------------- + -- ----------------------------------------------------------------------------- + irq_trigger: process(clk_i) + begin + if rising_edge(clk_i) then + irq_sync <= xirq_i; + irq_sync2 <= irq_sync; + end if; + end process irq_trigger; + + irq_trigger_comb: process(irq_sync, irq_sync2) + variable sel_v : std_ulogic_vector(1 downto 0); + begin + for i in 0 to XIRQ_NUM_CH-1 loop + sel_v := XIRQ_TRIGGER_TYPE(i) & XIRQ_TRIGGER_POLARITY(i); + case sel_v is + when "00" => irq_trig(i) <= not irq_sync(i); -- low-level + when "01" => irq_trig(i) <= irq_sync(i); -- high-level + when "10" => irq_trig(i) <= (not irq_sync(i)) and irq_sync2(i); -- falling-edge + when "11" => irq_trig(i) <= irq_sync(i) and (not irq_sync2(i)); -- rising-edge + when others => irq_trig(i) <= '0'; + end case; + end loop; + end process irq_trigger_comb; + + + -- IRQ Buffer --------------------------------------------------------------- + -- ----------------------------------------------------------------------------- + irq_buffer: process(clk_i) + begin + if rising_edge(clk_i) then + irq_buf <= (irq_buf or (irq_trig and irq_enable)) and clr_pending; + end if; + end process irq_buffer; + + -- anyone firing? -- + irq_fire <= or_reduce_f(irq_buf); + + + -- IRQ Priority Encoder ----------------------------------------------------- + -- ----------------------------------------------------------------------------- + irq_priority: process(irq_buf) + begin + irq_src_nxt <= (others => '0'); + if (XIRQ_NUM_CH > 1) then + for i in 0 to XIRQ_NUM_CH-1 loop + if (irq_buf(i) = '1') then + irq_src_nxt(index_size_f(XIRQ_NUM_CH)-1 downto 0) <= std_ulogic_vector(to_unsigned(i, index_size_f(XIRQ_NUM_CH))); + exit; + end if; + end loop; + end if; + end process irq_priority; + + + -- IRQ Arbiter -------------------------------------------------------------- + -- ----------------------------------------------------------------------------- + irq_arbiter: process(clk_i) + begin + if rising_edge(clk_i) then + cpu_irq_o <= '0'; + if (irq_run = '0') then -- no active IRQ + if (irq_fire = '1') then + cpu_irq_o <= '1'; + irq_run <= '1'; + irq_src <= irq_src_nxt; + end if; + else -- active IRQ, wait for CPU to acknowledge + if (wren = '1') and (addr = xirq_source_addr_c) then -- write _any_ value to acknowledge + irq_run <= '0'; + end if; + end if; + end if; + end process irq_arbiter; + + +end neorv32_xirq_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/processor_templates/README.md b/Libs/RiscV/NEORV32/rtl/processor_templates/README.md new file mode 100644 index 0000000..291164a --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/processor_templates/README.md @@ -0,0 +1,35 @@ +# SoC/Processor Templates + +This folder provides exemplary templates that wrap the processor top entity and provide a simplified +set of configuration generics and IOs. These setups are intended to allow beginner an easy start by +hiding much of the processor's configuration complexity. Furthermore, these setups are used by many +of the provided [example setups](https://github.com/stnolting/neorv32/tree/master/setups). + +Alternatively, you can directly instantiate the processor's top entity +[`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) +to have full access to _all_ features. + +### [`neorv32_ProcessorTop_Minimal.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd) + +This setup used the ["Direct Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration). +Application software is installed directly into the processor-internal instruction memory (IMEM) during +synthesis. This memory is implemented as ROM and these is no bootloader available. Hence, the executable +remains unchangeable is executed right after reset. + +The setup only provides 3 PWM channels as IO. + +### [`neorv32_ProcessorTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd) + +This setup used the ["Indirect Boot Configuration"](https://stnolting.github.io/neorv32/#_boot_configuration). +The NEORV32 bootloader is enabled in this setup allowing to upload new application software at any time +via a UART connection. + +The setup provides 8 GPIO outputs and the UART communication lines as IO. + +### [`neorv32_ProcessorTop_UP5KDemo.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd) + +This is a more complex template that implements a small microcontroller-like NEORV32. +It was originally designed for _UPDuino V3_ board, which features a Lattice iCE40up5k FPGA, but has +also been ported to other boards that provide the same FPGA. + +This setup provides a rich set of IOs including GPIO, SPI, TWI and PWM. diff --git a/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd b/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd new file mode 100644 index 0000000..143ae8b --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd @@ -0,0 +1,246 @@ +-- ################################################################################################# +-- # << NEORV32 - Minimal setup without a bootloader >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; + +entity neorv32_ProcessorTop_Minimal is + generic ( + CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 34; -- total width of CPU cycle and instret counters (0..64) + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 8*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 64*1024; -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- Processor peripherals -- + IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? + IO_PWM_NUM_CH : natural := 3; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := false -- implement watch dog timer (WDT)? + ); + port ( + clk_i : in std_logic; + rstn_i : in std_logic; + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0) + ); +end entity; + +architecture neorv32_ProcessorTop_Minimal_rtl of neorv32_ProcessorTop_Minimal is + +begin + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity neorv32.neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (32-bit) + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger? + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (1..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- External memory interface -- + MEM_EXT_EN => false, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) + + -- Processor peripherals -- + IO_GPIO_EN => false, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => false, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => false, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => false, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => false, -- implement true random number generator (TRNG)? + IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NEOLED_EN => false -- implement NeoPixel-compatible smart LED interface (NEOLED)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => '0', -- low-active TAP reset (optional) + jtag_tck_i => '0', -- serial clock + jtag_tdi_i => '0', -- serial data input + jtag_tdo_o => open, -- serial data output + jtag_tms_i => '0', -- mode select + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => open, -- request tag + wb_adr_o => open, -- address + wb_dat_i => (others => '0'), -- read data + wb_dat_o => open, -- write data + wb_we_o => open, -- read/write + wb_sel_o => open, -- byte enable + wb_stb_o => open, -- strobe + wb_cyc_o => open, -- valid cycle + wb_lock_o => open, -- exclusive access request + wb_ack_i => '0', -- transfer acknowledge + wb_err_i => '0', -- transfer error + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => open, -- parallel output + gpio_i => (others => '0'), -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => open, -- UART0 send data + uart0_rxd_i => '0', -- UART0 receive data + uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => open, -- UART1 send data + uart1_rxd_i => '0', -- UART1 receive data + uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => open, -- SPI serial clock + spi_sdo_o => open, -- controller data out, peripheral data in + spi_sdi_i => '0', -- controller data in, peripheral data out + spi_csn_o => open, -- SPI CS + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => open, -- twi serial data line + twi_scl_io => open, -- twi serial clock line + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => pwm_o, -- pwm channels + + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom CFS inputs conduit + cfs_out_o => open, -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + + -- Interrupts -- + mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => '0', -- machine software interrupt + mext_irq_i => '0' -- machine external interrupt + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd new file mode 100644 index 0000000..b0a0aac --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd @@ -0,0 +1,267 @@ +-- ################################################################################################# +-- # << NEORV32 - Minimal setup with the bootloader enabled >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; + +entity neorv32_ProcessorTop_MinimalBoot is + generic ( + CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := true; -- implement atomic extension? + CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := true; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 34; -- total width of CPU cycle and instret counters (0..64) + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 64*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 64*1024; -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- Processor peripherals -- + IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_PWM_NUM_CH : natural := 3; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := true -- implement watch dog timer (WDT)? + ); + port ( + clk_i : in std_logic; + rstn_i : in std_logic; + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_ulogic_vector(3 downto 0); + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart_txd_o : out std_ulogic; -- UART0 send data + uart_rxd_i : in std_ulogic := '0'; -- UART0 receive data + uart_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0) + ); +end entity; + +architecture neorv32_ProcessorTop_MinimalBoot_rtl of neorv32_ProcessorTop_MinimalBoot is + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(63 downto 0); + +begin + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- GPIO -- + gpio_o <= con_gpio_o(3 downto 0); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity neorv32.neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => INT_BOOTLOADER_EN,-- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (32-bit) + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger? + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (1..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- External memory interface -- + MEM_EXT_EN => false, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) + + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => false, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => false, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => false, -- implement true random number generator (TRNG)? + IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NEOLED_EN => false -- implement NeoPixel-compatible smart LED interface (NEOLED)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => '0', -- low-active TAP reset (optional) + jtag_tck_i => '0', -- serial clock + jtag_tdi_i => '0', -- serial data input + jtag_tdo_o => open, -- serial data output + jtag_tms_i => '0', -- mode select + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => open, -- request tag + wb_adr_o => open, -- address + wb_dat_i => (others => '0'), -- read data + wb_dat_o => open, -- write data + wb_we_o => open, -- read/write + wb_sel_o => open, -- byte enable + wb_stb_o => open, -- strobe + wb_cyc_o => open, -- valid cycle + wb_lock_o => open, -- exclusive access request + wb_ack_i => '0', -- transfer acknowledge + wb_err_i => '0', -- transfer error + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + gpio_i => (others => '0'), -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart_txd_o, -- UART0 send data + uart0_rxd_i => uart_rxd_i, -- UART0 receive data + uart0_rts_o => uart_rts_o, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => uart_cts_i, -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => open, -- UART1 send data + uart1_rxd_i => '0', -- UART1 receive data + uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => open, -- SPI serial clock + spi_sdo_o => open, -- controller data out, peripheral data in + spi_sdi_i => '0', -- controller data in, peripheral data out + spi_csn_o => open, -- SPI CS + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => open, -- twi serial data line + twi_scl_io => open, -- twi serial clock line + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => pwm_o, -- pwm channels + + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom CFS inputs conduit + cfs_out_o => open, -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + + -- Interrupts -- + mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => '0', -- machine software interrupt + mext_irq_i => '0' -- machine external interrupt + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd b/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd new file mode 100644 index 0000000..f09428b --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd @@ -0,0 +1,307 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for boards with UP5K devices >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; + +entity neorv32_ProcessorTop_UP5KDemo is + generic ( + CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger? + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := true; -- implement atomic extension? + CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := true; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 34; -- total width of CPU cycle and instret counters (0..64) + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 64*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 64*1024; -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- Processor peripherals -- + IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 3; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := true -- implement watch dog timer (WDT)? + ); + port ( + clk_i : in std_logic; + rstn_i : in std_logic; + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_i : in std_ulogic_vector(3 downto 0); + gpio_o : out std_ulogic_vector(3 downto 0); + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart_txd_o : out std_ulogic; -- UART0 send data + uart_rxd_i : in std_ulogic := '0'; -- UART0 receive data + uart_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- SPI to on-board flash -- + flash_sck_o : out std_ulogic; + flash_sdo_o : out std_ulogic; + flash_sdi_i : in std_ulogic; + flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0) + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_ulogic; + spi_sdo_o : out std_ulogic; + spi_sdi_i : in std_ulogic; + spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1) + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic; + twi_scl_io : inout std_logic; + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0) + ); +end entity; + +architecture neorv32_ProcessorTop_UP5KDemo_rtl of neorv32_ProcessorTop_UP5KDemo is + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(63 downto 0); + signal con_gpio_i : std_ulogic_vector(63 downto 0); + signal con_spi_sck : std_ulogic; + signal con_spi_sdi : std_ulogic; + signal con_spi_sdo : std_ulogic; + signal con_spi_csn : std_ulogic_vector(07 downto 0); + +begin + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- SPI: on-board flash -- + flash_sck_o <= con_spi_sck; + flash_sdo_o <= con_spi_sdo; + flash_csn_o <= con_spi_csn(0); + + -- SPI: user port -- + spi_sck_o <= con_spi_sck; + spi_sdo_o <= con_spi_sdo; + spi_csn_o <= con_spi_csn(1); + + con_spi_sdi <= flash_sdi_i when (con_spi_csn(0) = '0') else spi_sdi_i; + + -- GPIO -- + gpio_o <= con_gpio_o(3 downto 0); + con_gpio_i(03 downto 0) <= gpio_i; + con_gpio_i(63 downto 4) <= (others => '0'); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity neorv32.neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (32-bit) + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement on-chip debugger? + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (1..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- External memory interface -- + MEM_EXT_EN => false, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) + + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => false, -- implement true random number generator (TRNG)? + IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NEOLED_EN => false -- implement NeoPixel-compatible smart LED interface (NEOLED)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => '0', -- low-active TAP reset (optional) + jtag_tck_i => '0', -- serial clock + jtag_tdi_i => '0', -- serial data input + jtag_tdo_o => open, -- serial data output + jtag_tms_i => '0', -- mode select + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => open, -- request tag + wb_adr_o => open, -- address + wb_dat_i => (others => '0'), -- read data + wb_dat_o => open, -- write data + wb_we_o => open, -- read/write + wb_sel_o => open, -- byte enable + wb_stb_o => open, -- strobe + wb_cyc_o => open, -- valid cycle + wb_lock_o => open, -- exclusive access request + wb_ack_i => '0', -- transfer acknowledge + wb_err_i => '0', -- transfer error + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + gpio_i => con_gpio_i, -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart_txd_o, -- UART0 send data + uart0_rxd_i => uart_rxd_i, -- UART0 receive data + uart0_rts_o => uart_rts_o, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => uart_cts_i, -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => open, -- UART1 send data + uart1_rxd_i => '0', -- UART1 receive data + uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => con_spi_sck, -- SPI serial clock + spi_sdo_o => con_spi_sdo, -- controller data out, peripheral data in + spi_sdi_i => con_spi_sdi, -- controller data in, peripheral data out + spi_csn_o => con_spi_csn, -- SPI CS + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda_io, -- twi serial data line + twi_scl_io => twi_scl_io, -- twi serial clock line + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => pwm_o, -- pwm channels + + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom CFS inputs conduit + cfs_out_o => open, -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + + -- Interrupts -- + mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => '0', -- machine software interrupt + mext_irq_i => '0' -- machine external interrupt + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd b/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd new file mode 100644 index 0000000..4e56831 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd @@ -0,0 +1,486 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor Top Entity with Resolved Port Signals (std_logic/std_logic_vector) >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_ProcessorTop_stdlogic is + generic ( + -- General -- + CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External memory interface -- + MEM_EXT_EN : boolean := false; -- implement external memory bus interface? + MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled) + MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian + MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false + -- Stream link interface -- + SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) + SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) + SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic + IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits + IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? + ); + port ( + -- Global control -- + clk_i : in std_logic := '0'; -- global clock, rising edge + rstn_i : in std_logic := '0'; -- global reset, low-active, async + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i : in std_logic := '0'; -- low-active TAP reset (optional) + jtag_tck_i : in std_logic := '0'; -- serial clock + jtag_tdi_i : in std_logic := '0'; -- serial data input + jtag_tdo_o : out std_logic; -- serial data output + jtag_tms_i : in std_logic := '0'; -- mode select + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o : out std_logic_vector(02 downto 0); -- tag + wb_adr_o : out std_logic_vector(31 downto 0); -- address + wb_dat_i : in std_logic_vector(31 downto 0) := (others => '0'); -- read data + wb_dat_o : out std_logic_vector(31 downto 0); -- write data + wb_we_o : out std_logic; -- read/write + wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable + wb_stb_o : out std_logic; -- strobe + wb_cyc_o : out std_logic; -- valid cycle + wb_lock_o : out std_logic; -- exclusive access request + wb_ack_i : in std_logic := '0'; -- transfer acknowledge + wb_err_i : in std_logic := '0'; -- transfer error + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o : out std_logic; -- indicates an executed FENCE operation + fencei_o : out std_logic; -- indicates an executed FENCEI operation + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o : out sdata_8x32r_t; -- output data + slink_tx_val_o : out std_logic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_logic_vector(7 downto 0) := (others => '0'); -- ready to send + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i : in sdata_8x32r_t := (others => (others => '0')); -- input data + slink_rx_val_i : in std_logic_vector(7 downto 0) := (others => '0'); -- valid input + slink_rx_rdy_o : out std_logic_vector(7 downto 0); -- ready to receive + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_logic_vector(63 downto 0); -- parallel output + gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o : out std_logic; -- UART0 send data + uart0_rxd_i : in std_logic := '0'; -- UART0 receive data + uart0_rts_o : out std_logic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i : in std_logic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o : out std_logic; -- UART1 send data + uart1_rxd_i : in std_logic := '0'; -- UART1 receive data + uart1_rts_o : out std_logic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i : in std_logic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_logic; -- SPI serial clock + spi_sdo_o : out std_logic; -- controller data out, peripheral data in + spi_sdi_i : in std_logic := '0'; -- controller data in, peripheral data out + spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic; -- twi serial data line + twi_scl_io : inout std_logic; -- twi serial clock line + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_logic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs + cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o : out std_logic; -- async serial data line + -- System time -- + mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o : out std_logic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i : in std_logic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels + -- CPU Interrupts -- + mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i : in std_logic := '0'; -- machine software interrupt + mext_irq_i : in std_logic := '0' -- machine external interrupt + ); +end entity; + +architecture neorv32_ProcessorTop_stdlogic_rtl of neorv32_ProcessorTop_stdlogic is + + -- type conversion -- + constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG); + constant XIRQ_TRIGGER_TYPE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_TYPE); + constant XIRQ_TRIGGER_POLARITY_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_POLARITY); + -- + signal clk_i_int : std_ulogic; + signal rstn_i_int : std_ulogic; + -- + signal jtag_trst_i_int :std_ulogic; + signal jtag_tck_i_int :std_ulogic; + signal jtag_tdi_i_int :std_ulogic; + signal jtag_tdo_o_int :std_ulogic; + signal jtag_tms_i_int :std_ulogic; + -- + signal wb_tag_o_int : std_ulogic_vector(02 downto 0); + signal wb_adr_o_int : std_ulogic_vector(31 downto 0); + signal wb_dat_i_int : std_ulogic_vector(31 downto 0); + signal wb_dat_o_int : std_ulogic_vector(31 downto 0); + signal wb_we_o_int : std_ulogic; + signal wb_sel_o_int : std_ulogic_vector(03 downto 0); + signal wb_stb_o_int : std_ulogic; + signal wb_cyc_o_int : std_ulogic; + signal wb_lock_o_int : std_ulogic; + signal wb_ack_i_int : std_ulogic; + signal wb_err_i_int : std_ulogic; + -- + signal fence_o_int : std_ulogic; + signal fencei_o_int : std_ulogic; + -- + signal slink_tx_dat_o_int : sdata_8x32_t; + signal slink_tx_val_o_int : std_logic_vector(7 downto 0); + signal slink_tx_rdy_i_int : std_logic_vector(7 downto 0); + signal slink_rx_dat_i_int : sdata_8x32_t; + signal slink_rx_val_i_int : std_logic_vector(7 downto 0); + signal slink_rx_rdy_o_int : std_logic_vector(7 downto 0); + -- + signal gpio_o_int : std_ulogic_vector(63 downto 0); + signal gpio_i_int : std_ulogic_vector(63 downto 0); + -- + signal uart0_txd_o_int : std_ulogic; + signal uart0_rxd_i_int : std_ulogic; + signal uart0_rts_o_int : std_ulogic; + signal uart0_cts_i_int : std_ulogic; + -- + signal uart1_txd_o_int : std_ulogic; + signal uart1_rxd_i_int : std_ulogic; + signal uart1_rts_o_int : std_ulogic; + signal uart1_cts_i_int : std_ulogic; + -- + signal spi_sck_o_int : std_ulogic; + signal spi_sdo_o_int : std_ulogic; + signal spi_sdi_i_int : std_ulogic; + signal spi_csn_o_int : std_ulogic_vector(07 downto 0); + -- + signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); + -- + signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); + signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); + -- + signal neoled_o_int : std_ulogic; + -- + signal mtime_i_int : std_ulogic_vector(63 downto 0); + signal mtime_o_int : std_ulogic_vector(63 downto 0); + -- + signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + -- + signal mtime_irq_i_int : std_ulogic; + signal msw_irq_i_int : std_ulogic; + signal mext_irq_i_int : std_ulogic; + +begin + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (hartid) (32-bit) + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External memory interface -- + MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after a pending bus access auto-terminates (0 = disabled) + MEM_EXT_PIPE_MODE => MEM_EXT_PIPE_MODE, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian + MEM_EXT_ASYNC_RX => MEM_EXT_ASYNC_RX, -- use register buffer for RX data when false + -- Stream link interface -- + SLINK_NUM_TX => SLINK_NUM_TX, -- number of TX links (0..8) + SLINK_NUM_RX => SLINK_NUM_RX, -- number of TX links (0..8) + SLINK_TX_FIFO => SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO => SLINK_RX_FIFO, -- RX fifo depth, has to be a power of two + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE_INT, -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO => IO_UART0_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO => IO_UART1_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? + IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic + IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits + IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)? + ) + port map ( + -- Global control -- + clk_i => clk_i_int, -- global clock, rising edge + rstn_i => rstn_i_int, -- global reset, low-active, async + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => jtag_trst_i_int, -- low-active TAP reset (optional) + jtag_tck_i => jtag_tck_i_int, -- serial clock + jtag_tdi_i => jtag_tdi_i_int, -- serial data input + jtag_tdo_o => jtag_tdo_o_int, -- serial data output + jtag_tms_i => jtag_tms_i_int, -- mode select + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => wb_tag_o_int, -- tag + wb_adr_o => wb_adr_o_int, -- address + wb_dat_i => wb_dat_i_int, -- read data + wb_dat_o => wb_dat_o_int, -- write data + wb_we_o => wb_we_o_int, -- read/write + wb_sel_o => wb_sel_o_int, -- byte enable + wb_stb_o => wb_stb_o_int, -- strobe + wb_cyc_o => wb_cyc_o_int, -- valid cycle + wb_lock_o => wb_lock_o_int, -- exclusive access request + wb_ack_i => wb_ack_i_int, -- transfer acknowledge + wb_err_i => wb_err_i_int, -- transfer error + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => fence_o_int, -- indicates an executed FENCE operation + fencei_o => fencei_o_int, -- indicates an executed FENCEI operation + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o => slink_tx_dat_o_int, -- output data + slink_tx_val_o => slink_tx_val_o_int, -- valid output + slink_tx_rdy_i => slink_tx_rdy_i_int, -- ready to send + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i => slink_rx_dat_i_int, -- input data + slink_rx_val_i => slink_rx_val_i_int, -- valid input + slink_rx_rdy_o => slink_rx_rdy_o_int, -- ready to receive + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => gpio_o_int, -- parallel output + gpio_i => gpio_i_int, -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd_o_int, -- UART0 send data + uart0_rxd_i => uart0_rxd_i_int, -- UART0 receive data + uart0_rts_o => uart0_rts_o_int, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => uart0_cts_i_int, -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => uart1_txd_o_int, -- UART1 send data + uart1_rxd_i => uart1_rxd_i_int, -- UART1 receive data + uart1_rts_o => uart1_rts_o_int, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => uart1_cts_i_int, -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => spi_sck_o_int, -- SPI serial clock + spi_sdo_o => spi_sdo_o_int, -- controller data out, peripheral data in + spi_sdi_i => spi_sdi_i_int, -- controller data in, peripheral data out + spi_csn_o => spi_csn_o_int, -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda_io, -- twi serial data line + twi_scl_io => twi_scl_io, -- twi serial clock line + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => pwm_o_int, -- pwm channels + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i => cfs_in_i_int, -- custom inputs + cfs_out_o => cfs_out_o_int, -- custom outputs + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => neoled_o_int, -- async serial data line + -- System time -- + mtime_i => mtime_i_int, -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => mtime_o_int, -- current system time from int. MTIME (if IO_MTIME_EN = true) + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i => xirq_i_int, -- IRQ channels + -- CPU Interrupts -- + mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => msw_irq_i_int, -- machine software interrupt + mext_irq_i => mext_irq_i_int -- machine external interrupt + ); + + -- type conversion -- + clk_i_int <= std_ulogic(clk_i); + rstn_i_int <= std_ulogic(rstn_i); + + jtag_trst_i_int <= std_ulogic(jtag_trst_i); + jtag_tck_i_int <= std_ulogic(jtag_tck_i); + jtag_tdi_i_int <= std_ulogic(jtag_tdi_i); + jtag_tdo_o <= std_logic(jtag_tdo_o_int); + jtag_tms_i_int <= std_ulogic(jtag_tms_i); + + wb_tag_o <= std_logic_vector(wb_tag_o_int); + wb_adr_o <= std_logic_vector(wb_adr_o_int); + wb_dat_i_int <= std_ulogic_vector(wb_dat_i); + wb_dat_o <= std_logic_vector(wb_dat_o_int); + wb_we_o <= std_logic(wb_we_o_int); + wb_sel_o <= std_logic_vector(wb_sel_o_int); + wb_stb_o <= std_logic(wb_stb_o_int); + wb_cyc_o <= std_logic(wb_cyc_o_int); + wb_lock_o <= std_logic(wb_lock_o_int); + wb_ack_i_int <= std_ulogic(wb_ack_i); + wb_err_i_int <= std_ulogic(wb_err_i); + + fence_o <= std_logic(fence_o_int); + fencei_o <= std_logic(fencei_o_int); + + slink_tx_val_o <= std_logic_vector(slink_tx_val_o_int); + slink_tx_rdy_i_int <= std_ulogic_vector(slink_tx_rdy_i); + slink_rx_val_i_int <= std_ulogic_vector(slink_rx_val_i); + slink_rx_rdy_o <= std_logic_vector(slink_rx_rdy_o_int); + + slink_conv: + for i in 0 to 7 generate + slink_tx_dat_o(i) <= std_logic_vector(slink_tx_dat_o_int(i)); + slink_rx_dat_i_int(i) <= std_ulogic_vector(slink_rx_dat_i(i)); + end generate; + + gpio_o <= std_logic_vector(gpio_o_int); + gpio_i_int <= std_ulogic_vector(gpio_i); + + uart0_txd_o <= std_logic(uart0_txd_o_int); + uart0_rxd_i_int <= std_ulogic(uart0_rxd_i); + uart0_rts_o <= std_logic(uart0_rts_o_int); + uart0_cts_i_int <= std_ulogic(uart0_cts_i); + uart1_txd_o <= std_logic(uart1_txd_o_int); + uart1_rxd_i_int <= std_ulogic(uart1_rxd_i); + uart1_rts_o <= std_logic(uart1_rts_o_int); + uart1_cts_i_int <= std_ulogic(uart1_cts_i); + + spi_sck_o <= std_logic(spi_sck_o_int); + spi_sdo_o <= std_logic(spi_sdo_o_int); + spi_sdi_i_int <= std_ulogic(spi_sdi_i); + spi_csn_o <= std_logic_vector(spi_csn_o_int); + + pwm_o <= std_logic_vector(pwm_o_int); + + cfs_in_i_int <= std_ulogic_vector(cfs_in_i); + cfs_out_o <= std_logic_vector(cfs_out_o_int); + + neoled_o <= std_logic(neoled_o_int); + + mtime_i_int <= std_ulogic_vector(mtime_i); + mtime_o <= std_logic_vector(mtime_o_int); + + xirq_i_int <= std_ulogic_vector(xirq_i); + + msw_irq_i_int <= std_ulogic(msw_irq_i); + mext_irq_i_int <= std_ulogic(mext_irq_i); + + +end architecture; diff --git a/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd b/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd new file mode 100644 index 0000000..bcab595 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd @@ -0,0 +1,423 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor Top Entity with AvalonMM Compatible Master Interface >> # +-- # ********************************************************************************************* # +-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" # +-- # are trademarks of Intel # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_top_avalonmm is + generic ( + -- General -- + CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? + + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2 + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory (IMEM) -- + MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory (DMEM) -- + MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes + + -- Internal Cache memory (iCACHE) -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- Stream link interface (SLINK) -- + SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) + SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) + SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two + + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + + -- Processor peripherals -- + IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic + IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits + IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional) + jtag_tck_i : in std_ulogic := 'U'; -- serial clock + jtag_tdi_i : in std_ulogic := 'U'; -- serial data input + jtag_tdo_o : out std_ulogic; -- serial data output + jtag_tms_i : in std_ulogic := 'U'; -- mode select + + -- AvalonMM interface + read_o : out std_logic; + write_o : out std_logic; + waitrequest_i : in std_logic := '0'; + byteenable_o : out std_logic_vector(3 downto 0); + address_o : out std_logic_vector(31 downto 0); + writedata_o : out std_logic_vector(31 downto 0); + readdata_i : in std_logic_vector(31 downto 0) := (others => '0'); + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o : out std_ulogic; -- indicates an executed FENCE operation + fencei_o : out std_ulogic; -- indicates an executed FENCEI operation + + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o : out sdata_8x32_t; -- output data + slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send + + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data + slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input + slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output + gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data + uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o : out std_ulogic; -- UART1 send data + uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data + uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_ulogic; -- SPI serial clock + spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in + spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic := 'U'; -- twi serial data line + twi_scl_io : inout std_logic := 'U'; -- twi serial clock line + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels + + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit + cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o : out std_ulogic; -- async serial data line + + -- System time -- + mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) + + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels + + -- CPU interrupts -- + mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt + mext_irq_i : in std_ulogic := 'L' -- machine external interrupt + ); +end neorv32_top_avalonmm; + +architecture neorv32_top_avalonmm_rtl of neorv32_top_avalonmm is + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag + signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address + signal wb_dat_i : std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data + signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data + signal wb_we_o : std_ulogic; -- read/write + signal wb_sel_o : std_ulogic_vector(03 downto 0); -- byte enable + signal wb_stb_o : std_ulogic; -- strobe + signal wb_cyc_o : std_ulogic; -- valid cycle + signal wb_lock_o : std_ulogic; -- exclusive access request + signal wb_ack_i : std_ulogic := 'L'; -- transfer acknowledge + signal wb_err_i : std_ulogic := 'L'; -- transfer error + +begin + + neorv32_top_map : neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + HW_THREAD_ID => HW_THREAD_ID, + INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, + CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, + CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, + CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, + + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, + FAST_SHIFT_EN => FAST_SHIFT_EN, + CPU_CNT_WIDTH => CPU_CNT_WIDTH, + CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, + HPM_CNT_WIDTH => HPM_CNT_WIDTH, + + -- Internal Instruction memory (IMEM) -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, + + -- Internal Data memory (DMEM) -- + MEM_INT_DMEM_EN => MEM_INT_IMEM_EN, + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, + + -- Internal Cache memory (iCACHE) -- + ICACHE_EN => ICACHE_EN, + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, + + -- External memory interface (WISHBONE) -- + MEM_EXT_EN => true, + MEM_EXT_TIMEOUT => 0, + MEM_EXT_PIPE_MODE => false, + MEM_EXT_BIG_ENDIAN => false, + MEM_EXT_ASYNC_RX => false, + + -- Stream link interface (SLINK) -- + SLINK_NUM_TX => SLINK_NUM_TX, + SLINK_NUM_RX => SLINK_NUM_RX, + SLINK_TX_FIFO => SLINK_TX_FIFO, + SLINK_RX_FIFO => SLINK_RX_FIFO, + + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH => XIRQ_NUM_CH, + XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE, + XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY, + + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, + IO_MTIME_EN => IO_MTIME_EN, + IO_UART0_EN => IO_UART0_EN, + IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, + IO_UART0_TX_FIFO => IO_UART0_TX_FIFO, + IO_UART1_EN => IO_UART1_EN, + IO_UART1_RX_FIFO => IO_UART1_RX_FIFO, + IO_UART1_TX_FIFO => IO_UART1_TX_FIFO, + IO_SPI_EN => IO_SPI_EN, + IO_TWI_EN => IO_TWI_EN, + IO_PWM_NUM_CH => IO_PWM_NUM_CH, + IO_WDT_EN => IO_WDT_EN, + IO_TRNG_EN => IO_TRNG_EN, + IO_CFS_EN => IO_CFS_EN, + IO_CFS_CONFIG => IO_CFS_CONFIG, + IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, + IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, + IO_NEOLED_EN => IO_NEOLED_EN, + IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, + IO_GPTMR_EN => IO_GPTMR_EN + ) + port map ( + -- Global control -- + clk_i => clk_i, + rstn_i => rstn_i, + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => jtag_trst_i, + jtag_tck_i => jtag_tck_i, + jtag_tdi_i => jtag_tdi_i, + jtag_tdo_o => jtag_tdo_o, + jtag_tms_i => jtag_tms_i, + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => wb_tag_o, + wb_adr_o => wb_adr_o, + wb_dat_i => wb_dat_i, + wb_dat_o => wb_dat_o, + wb_we_o => wb_we_o, + wb_sel_o => wb_sel_o, + wb_stb_o => wb_stb_o, + wb_cyc_o => wb_cyc_o, + wb_lock_o => wb_lock_o, + wb_ack_i => wb_ack_i, + wb_err_i => wb_err_i, + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => fence_o, + fencei_o => fencei_o, + + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o => slink_tx_dat_o, + slink_tx_val_o => slink_tx_val_o, + slink_tx_rdy_i => slink_tx_rdy_i, + + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i => slink_rx_dat_i, + slink_rx_val_i => slink_rx_val_i, + slink_rx_rdy_o => slink_rx_rdy_o, + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => gpio_o, + gpio_i => gpio_i, + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd_o, + uart0_rxd_i => uart0_rxd_i, + uart0_rts_o => uart0_rts_o, + uart0_cts_i => uart0_cts_i, + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => uart1_txd_o, + uart1_rxd_i => uart1_rxd_i, + uart1_rts_o => uart1_rts_o, + uart1_cts_i => uart1_cts_i, + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => spi_sck_o, + spi_sdo_o => spi_sdo_o, + spi_sdi_i => spi_sdi_i, + spi_csn_o => spi_csn_o, + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda_io, + twi_scl_io => twi_scl_io, + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => pwm_o, + + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i => cfs_in_i, + cfs_out_o => cfs_out_o, + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => neoled_o, + + -- System time -- + mtime_i => mtime_i, + mtime_o => mtime_o, + + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i => xirq_i, + + -- CPU interrupts -- + mtime_irq_i => mtime_irq_i, + msw_irq_i => msw_irq_i, + mext_irq_i => mext_irq_i + ); + + -- Wishbone to AvalonMM bridge + read_o <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0'; + write_o <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0'; + address_o <= std_logic_vector(wb_adr_o); + writedata_o <= std_logic_vector(wb_dat_o); + byteenable_o <= std_logic_vector(wb_sel_o); + + wb_dat_i <= std_ulogic_vector(readdata_i); + wb_ack_i <= not(waitrequest_i); + wb_err_i <= '0'; + +end neorv32_top_avalonmm_rtl; diff --git a/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd b/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd new file mode 100644 index 0000000..382f97c --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd @@ -0,0 +1,532 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor Top Entity with AXI4-Lite Compatible Master Interface >> # +-- # ********************************************************************************************* # +-- # (c) "AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc. # +-- # Note: External MTIME is not supported. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_SystemTop_axi4lite is + generic ( + -- ------------------------------------------------------------ + -- Configuration Generics -- + -- ------------------------------------------------------------ + -- General -- + CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic + IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits + IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN : boolean := false -- implement general purpose timer (GPTMR)? + ); + port ( + -- ------------------------------------------------------------ + -- AXI4-Lite-Compatible Master Interface -- + -- ------------------------------------------------------------ + -- Clock and Reset -- + m_axi_aclk : in std_logic; + m_axi_aresetn : in std_logic; + -- Write Address Channel -- + m_axi_awaddr : out std_logic_vector(31 downto 0); + m_axi_awprot : out std_logic_vector(2 downto 0); + m_axi_awvalid : out std_logic; + m_axi_awready : in std_logic; + -- Write Data Channel -- + m_axi_wdata : out std_logic_vector(31 downto 0); + m_axi_wstrb : out std_logic_vector(3 downto 0); + m_axi_wvalid : out std_logic; + m_axi_wready : in std_logic; + -- Read Address Channel -- + m_axi_araddr : out std_logic_vector(31 downto 0); + m_axi_arprot : out std_logic_vector(2 downto 0); + m_axi_arvalid : out std_logic; + m_axi_arready : in std_logic; + -- Read Data Channel -- + m_axi_rdata : in std_logic_vector(31 downto 0); + m_axi_rresp : in std_logic_vector(1 downto 0); + m_axi_rvalid : in std_logic; + m_axi_rready : out std_logic; + -- Write Response Channel -- + m_axi_bresp : in std_logic_vector(1 downto 0); + m_axi_bvalid : in std_logic; + m_axi_bready : out std_logic; + -- ------------------------------------------------------------ + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + -- ------------------------------------------------------------ + jtag_trst_i : in std_logic := '0'; -- low-active TAP reset (optional) + jtag_tck_i : in std_logic := '0'; -- serial clock + jtag_tdi_i : in std_logic := '0'; -- serial data input + jtag_tdo_o : out std_logic; -- serial data output + jtag_tms_i : in std_logic := '0'; -- mode select + -- ------------------------------------------------------------ + -- Processor IO -- + -- ------------------------------------------------------------ + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_logic_vector(63 downto 0); -- parallel output + gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o : out std_logic; -- UART0 send data + uart0_rxd_i : in std_logic := '0'; -- UART0 receive data + uart0_rts_o : out std_logic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i : in std_logic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o : out std_logic; -- UART1 send data + uart1_rxd_i : in std_logic := '0'; -- UART1 receive data + uart1_rts_o : out std_logic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i : in std_logic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_logic; -- SPI serial clock + spi_sdo_o : out std_logic; -- controller data out, peripheral data in + spi_sdi_i : in std_logic := '0'; -- controller data in, peripheral data out + spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic; -- twi serial data line + twi_scl_io : inout std_logic; -- twi serial clock line + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_logic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs + cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o : out std_logic; -- async serial data line + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i : in std_logic_vector(XIRQ_NUM_CH-1 downto 0) := (others => '0'); -- IRQ channels + -- CPU Interrupts -- + msw_irq_i : in std_logic := '0'; -- machine software interrupt + mext_irq_i : in std_logic := '0' -- machine external interrupt + ); +end entity; + +architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is + + -- type conversion -- + constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG); + constant XIRQ_TRIGGER_TYPE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_TYPE); + constant XIRQ_TRIGGER_POLARITY_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_POLARITY); + -- + signal clk_i_int : std_ulogic; + signal rstn_i_int : std_ulogic; + -- + signal jtag_trst_i_int :std_ulogic; + signal jtag_tck_i_int :std_ulogic; + signal jtag_tdi_i_int :std_ulogic; + signal jtag_tdo_o_int :std_ulogic; + signal jtag_tms_i_int :std_ulogic; + -- + signal gpio_o_int : std_ulogic_vector(63 downto 0); + signal gpio_i_int : std_ulogic_vector(63 downto 0); + -- + signal uart0_txd_o_int : std_ulogic; + signal uart0_rxd_i_int : std_ulogic; + signal uart0_rts_o_int : std_ulogic; + signal uart0_cts_i_int : std_ulogic; + -- + signal uart1_txd_o_int : std_ulogic; + signal uart1_rxd_i_int : std_ulogic; + signal uart1_rts_o_int : std_ulogic; + signal uart1_cts_i_int : std_ulogic; + -- + signal spi_sck_o_int : std_ulogic; + signal spi_sdo_o_int : std_ulogic; + signal spi_sdi_i_int : std_ulogic; + signal spi_csn_o_int : std_ulogic_vector(07 downto 0); + -- + signal pwm_o_int : std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); + -- + signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); + signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); + -- + signal neoled_o_int : std_ulogic; + -- + signal xirq_i_int : std_ulogic_vector(XIRQ_NUM_CH-1 downto 0); + -- + signal msw_irq_i_int : std_ulogic; + signal mext_irq_i_int : std_ulogic; + + -- internal wishbone bus -- + type wb_bus_t is record + adr : std_ulogic_vector(31 downto 0); -- address + di : std_ulogic_vector(31 downto 0); -- processor input data + do : std_ulogic_vector(31 downto 0); -- processor output data + we : std_ulogic; -- write enable + sel : std_ulogic_vector(03 downto 0); -- byte enable + stb : std_ulogic; -- strobe + cyc : std_ulogic; -- valid cycle + ack : std_ulogic; -- transfer acknowledge + err : std_ulogic; -- transfer error + tag : std_ulogic_vector(02 downto 0); -- tag + lock : std_ulogic; -- exclusive access request + end record; + signal wb_core : wb_bus_t; + + -- AXI bridge control -- + type ctrl_t is record + radr_received : std_ulogic; + wadr_received : std_ulogic; + wdat_received : std_ulogic; + end record; + signal ctrl : ctrl_t; + + signal ack_read, ack_write : std_ulogic; -- normal transfer termination + signal err_read, err_write : std_ulogic; -- error transfer termination + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 PROCESSOR CONFIG WARNING: AXI4-Lite provides NO support for atomic memory operations. LR/SC access via AXI will raise a bus exception." severity warning; + + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (hartid) + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64) + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External memory interface -- + MEM_EXT_EN => true, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) + MEM_EXT_PIPE_MODE => false, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian + MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE_INT, -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO => IO_UART0_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO => IO_UART1_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? + IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic + IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits + IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN => IO_GPTMR_EN -- implement general purpose timer (GPTMR)? + ) + port map ( + -- Global control -- + clk_i => clk_i_int, -- global clock, rising edge + rstn_i => rstn_i_int, -- global reset, low-active, async + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => jtag_trst_i_int, -- low-active TAP reset (optional) + jtag_tck_i => jtag_tck_i_int, -- serial clock + jtag_tdi_i => jtag_tdi_i_int, -- serial data input + jtag_tdo_o => jtag_tdo_o_int, -- serial data output + jtag_tms_i => jtag_tms_i_int, -- mode select + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => wb_core.tag, -- tag + wb_adr_o => wb_core.adr, -- address + wb_dat_i => wb_core.di, -- read data + wb_dat_o => wb_core.do, -- write data + wb_we_o => wb_core.we, -- read/write + wb_sel_o => wb_core.sel, -- byte enable + wb_stb_o => wb_core.stb, -- strobe + wb_cyc_o => wb_core.cyc, -- valid cycle + wb_lock_o => wb_core.lock, -- exclusive access request + wb_ack_i => wb_core.ack, -- transfer acknowledge + wb_err_i => wb_core.err, -- transfer error + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => gpio_o_int, -- parallel output + gpio_i => gpio_i_int, -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd_o_int, -- UART0 send data + uart0_rxd_i => uart0_rxd_i_int, -- UART0 receive data + uart0_rts_o => uart0_rts_o_int, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => uart0_cts_i_int, -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => uart1_txd_o_int, -- UART1 send data + uart1_rxd_i => uart1_rxd_i_int, -- UART1 receive data + uart1_rts_o => uart1_rts_o_int, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => uart1_cts_i_int, -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => spi_sck_o_int, -- SPI serial clock + spi_sdo_o => spi_sdo_o_int, -- controller data out, peripheral data in + spi_sdi_i => spi_sdi_i_int, -- controller data in, peripheral data out + spi_csn_o => spi_csn_o_int, -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda_io, -- twi serial data line + twi_scl_io => twi_scl_io, -- twi serial clock line + -- PWM available if IO_PWM_NUM_CH > 0) -- + pwm_o => pwm_o_int, -- pwm channels + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i => cfs_in_i_int, -- custom inputs + cfs_out_o => cfs_out_o_int, -- custom outputs + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => neoled_o_int, -- async serial data line + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i => xirq_i_int, -- IRQ channels + -- CPU Interrupts -- + mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => msw_irq_i_int, -- machine software interrupt + mext_irq_i => mext_irq_i_int -- machine external interrupt + ); + + -- type conversion -- + gpio_o <= std_logic_vector(gpio_o_int); + gpio_i_int <= std_ulogic_vector(gpio_i); + + jtag_trst_i_int <= std_ulogic(jtag_trst_i); + jtag_tck_i_int <= std_ulogic(jtag_tck_i); + jtag_tdi_i_int <= std_ulogic(jtag_tdi_i); + jtag_tdo_o <= std_logic(jtag_tdo_o_int); + jtag_tms_i_int <= std_ulogic(jtag_tms_i); + + uart0_txd_o <= std_logic(uart0_txd_o_int); + uart0_rxd_i_int <= std_ulogic(uart0_rxd_i); + uart0_rts_o <= std_logic(uart0_rts_o_int); + uart0_cts_i_int <= std_ulogic(uart0_cts_i); + uart1_txd_o <= std_logic(uart1_txd_o_int); + uart1_rxd_i_int <= std_ulogic(uart1_rxd_i); + uart1_rts_o <= std_logic(uart1_rts_o_int); + uart1_cts_i_int <= std_ulogic(uart1_cts_i); + + spi_sck_o <= std_logic(spi_sck_o_int); + spi_sdo_o <= std_logic(spi_sdo_o_int); + spi_sdi_i_int <= std_ulogic(spi_sdi_i); + spi_csn_o <= std_logic_vector(spi_csn_o_int); + + pwm_o <= std_logic_vector(pwm_o_int); + + cfs_in_i_int <= std_ulogic_vector(cfs_in_i); + cfs_out_o <= std_logic_vector(cfs_out_o_int); + + neoled_o <= std_logic(neoled_o_int); + + xirq_i_int <= std_ulogic_vector(xirq_i); + + msw_irq_i_int <= std_ulogic(msw_irq_i); + mext_irq_i_int <= std_ulogic(mext_irq_i); + + + -- Wishbone to AXI4-Lite Bridge ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- access arbiter -- + axi_access_arbiter: process(rstn_i_int, clk_i_int) + begin + if (rstn_i_int = '0') then + ctrl.radr_received <= '0'; + ctrl.wadr_received <= '0'; + ctrl.wdat_received <= '0'; + elsif rising_edge(clk_i_int) then + if (wb_core.cyc = '0') then -- idle + ctrl.radr_received <= '0'; + ctrl.wadr_received <= '0'; + ctrl.wdat_received <= '0'; + else -- busy + -- "read address received" flag -- + if (wb_core.we = '0') then -- pending READ + if (m_axi_arready = '1') then -- read address received by interconnect? + ctrl.radr_received <= '1'; + end if; + end if; + -- "write address received" flag -- + if (wb_core.we = '1') then -- pending WRITE + if (m_axi_awready = '1') then -- write address received by interconnect? + ctrl.wadr_received <= '1'; + end if; + end if; + -- "write data received" flag -- + if (wb_core.we = '1') then -- pending WRITE + if (m_axi_wready = '1') then -- write data received by interconnect? + ctrl.wdat_received <= '1'; + end if; + end if; + end if; + end if; + end process axi_access_arbiter; + + + -- AXI4-Lite Global Signals -- + clk_i_int <= std_ulogic(m_axi_aclk); + rstn_i_int <= std_ulogic(m_axi_aresetn); + + + -- AXI4-Lite Read Address Channel -- + m_axi_araddr <= std_logic_vector(wb_core.adr); + m_axi_arvalid <= std_logic((wb_core.cyc and (not wb_core.we)) and (not ctrl.radr_received)); +--m_axi_arprot <= "000"; -- recommended by Xilinx + m_axi_arprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access + m_axi_arprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access + m_axi_arprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access + + -- AXI4-Lite Read Data Channel -- + m_axi_rready <= std_logic(wb_core.cyc and (not wb_core.we)); + wb_core.di <= std_ulogic_vector(m_axi_rdata); + ack_read <= std_ulogic(m_axi_rvalid); + err_read <= '0' when (m_axi_rresp = "00") else '1'; -- read response = ok? check this signal only when m_axi_rvalid = '1' + + + -- AXI4-Lite Write Address Channel -- + m_axi_awaddr <= std_logic_vector(wb_core.adr); + m_axi_awvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wadr_received)); +--m_axi_awprot <= "000"; -- recommended by Xilinx + m_axi_awprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access + m_axi_awprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access + m_axi_awprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access + + -- AXI4-Lite Write Data Channel -- + m_axi_wdata <= std_logic_vector(wb_core.do); + m_axi_wvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wdat_received)); + m_axi_wstrb <= std_logic_vector(wb_core.sel); -- byte-enable + + -- AXI4-Lite Write Response Channel -- + m_axi_bready <= std_logic(wb_core.cyc and wb_core.we); + ack_write <= std_ulogic(m_axi_bvalid); + err_write <= '0' when (m_axi_bresp = "00") else '1'; -- write response = ok? check this signal only when m_axi_bvalid = '1' + + + -- Wishbone transfer termination -- + wb_core.ack <= ack_read or ack_write; + wb_core.err <= (ack_read and err_read) or (ack_write and err_write) or wb_core.lock; + + +end architecture; diff --git a/Libs/RiscV/NEORV32/rtl/test_setups/README.md b/Libs/RiscV/NEORV32/rtl/test_setups/README.md new file mode 100644 index 0000000..d3ee026 --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/test_setups/README.md @@ -0,0 +1,52 @@ +# Test Setups + +This folder contains very simple test setups that are intended for project beginners +to setup a minimal NEORV32 SoC. These setups are used in the :books: +[NEORV32 User Guide](https://stnolting.github.io/neorv32/ug/). +Note that these setups provides a minimalistic configuration to keep +things at a simple level at first. Additional CPU ISA extensions, performance options and +optional peripheral modules can be enabled by specifying the according :book: +[configuration generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics). + + +### Setup's Top Entity + +#### Clocking and Reset + +All test setups require an external clock (via `clk_i` signal) and an external +low-active reset (via `rstn_i` signal). + +#### Configuration Generics + +Each setup provides three elementary generics that can/should be adapted to fit +your FPGA/board. + +* The clock speed in Hz **has to be specified** via the `CLOCK_SPEED` generic to fit your clock source. +* The processor-internal instruction memory (IMEM) size _can be modified_ via the `MEM_INT_IMEM_SIZE` generic. +* The processor-internal data memory (DMEM) size _can be modified_ via the `MEM_INT_DMEM_SIZE` generic. +Note that this might require adaption of the NEORV32 linker script. + + +### [`neorv32_test_setup_approm.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_approm.vhd) + +This setup configures a `rv32imc_Zicsr` CPU with 16kB IMEM (as pre-initialized ROM), +8kB DMEM and includes the GPIO module to drive 8 external signals (`gpio_o`) +and the MTIME module for generating timer interrupts. +The setup uses the ["indirect boot"](https://stnolting.github.io/neorv32/#_indirect_boot) +configuration, so software applications are "installed" directly into the +processor-internal IMEM during synthesis. + +:books: See User Guide section [_Installing an Executable Directly Into Memory_](https://stnolting.github.io/neorv32/ug/#_installing_an_executable_directly_into_memory). + + +### [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) + +This setup configures a `rv32imc_Zicsr` CPU with 16kB IMEM (as RAM), 8kB DMEM +and includes the GPIO module to drive 8 external signals (`gpio_o`), the MTIME +module for generating timer interrupts and UART0 to interface with the bootloader +(via `uart0_txd_o` and `uart0_rxd_i`) via a serial terminal. +The setup uses the ["direct boot"](https://stnolting.github.io/neorv32/#_direct_boot) +configuration, so software applications can be uploaded and run at any timer via a serial terminal. + +:books: See User Guide section +[_Uploading and Starting of a Binary Executable Image via UART_](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart). diff --git a/Libs/RiscV/NEORV32/rtl/test_setups/neorv32_test_setup_approm.vhd b/Libs/RiscV/NEORV32/rtl/test_setups/neorv32_test_setup_approm.vhd new file mode 100644 index 0000000..6f48bef --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/test_setups/neorv32_test_setup_approm.vhd @@ -0,0 +1,98 @@ +-- ################################################################################################# +-- # << NEORV32 - Test Setup using the internal IMEM as ROM to run pre-installed executables >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_test_setup_approm is + generic ( + -- adapt these for your setup -- + CLOCK_FREQUENCY : natural := 100000000; -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_ulogic_vector(7 downto 0) -- parallel output + ); +end entity; + +architecture neorv32_test_setup_approm_rtl of neorv32_test_setup_approm is + + signal con_gpio_o : std_ulogic_vector(63 downto 0); + +begin + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => true, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true -- implement machine system timer (MTIME)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o -- parallel output + ); + + -- GPIO output -- + gpio_o <= con_gpio_o(7 downto 0); + + +end architecture; diff --git a/Libs/RiscV/NEORV32/rtl/test_setups/neorv32_test_setup_bootloader.vhd b/Libs/RiscV/NEORV32/rtl/test_setups/neorv32_test_setup_bootloader.vhd new file mode 100644 index 0000000..1c420af --- /dev/null +++ b/Libs/RiscV/NEORV32/rtl/test_setups/neorv32_test_setup_bootloader.vhd @@ -0,0 +1,105 @@ +-- ################################################################################################# +-- # << NEORV32 - Test Setup using the UART-Bootloader to upload and run executables >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_test_setup_bootloader is + generic ( + -- adapt these for your setup -- + CLOCK_FREQUENCY : natural := 100000000; -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output + -- UART0 -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic -- UART0 receive data + ); +end entity; + +architecture neorv32_test_setup_bootloader_rtl of neorv32_test_setup_bootloader is + + signal con_gpio_o : std_ulogic_vector(63 downto 0); + +begin + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => true, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd_o, -- UART0 send data + uart0_rxd_i => uart0_rxd_i -- UART0 receive data + ); + + -- GPIO output -- + gpio_o <= con_gpio_o(7 downto 0); + + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/README.md b/Libs/RiscV/NEORV32/setups/README.md new file mode 100644 index 0000000..d0cc30b --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/README.md @@ -0,0 +1,65 @@ +# Exemplary FPGA Board Setups + +* [Setups using Commercial Toolchains](#Setups-using-Commercial-Toolchains) +* [Setups using Open-Source Toolchains](#Setups-using-Open-Source-Toolchains) +* [Adding Your Project Setup](#Adding-Your-Project-Setup) +* [Setup-Specific NEORV32 Software Framework Modification](#Setup-Specific-NEORV32-Software-Framework-Modification) + +This folder provides exemplary NEORV32 SoC setups and projects for different FPGA platforms/boards. +You can directly use one of the provided setups or use them as starting point to build your own setup. +Project maintainers may make pull requests against this repository to [add or link their setups](#Adding-Your-Project-Setup). + + +## Setups using Commercial Toolchains + +| Setup | Toolchain | Board :books: | FPGA | Author(s) | +|:------|:----------|:--------------|:------|:----------| +| :file_folder: [`de0-nano-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/quartus/de0-nano-test-setup) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [stnolting](https://github.com/stnolting) | +| :file_folder: [`de0-nano-test-setup-qsys`](quartus/de0-nano-test-setup-qsys) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [torerams](https://github.com/torerams) | +| :file_folder: [`de0-nano-test-setup-avalonmm`](quartus/de0-nano-test-setup-avalonmm-wrapper) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [torerams](https://github.com/torerams) | +| :file_folder: [`terasic-cyclone-V-gx-starter-kit-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup) | Intel Quartus Prime | [Terasic Cyclone-V GX Starter Kit](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830) | Intel Cyclone V `5CGXFC5C6F27C7N` | zs6mue | +| :file_folder: [`UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/setups/radiant/UPduino_v3) | Lattice Radiant | [tinyVision.ai Inc. UPduino `v3.0`](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [stnolting](https://github.com/stnolting) | +| :file_folder: [`arty-a7-35-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/arty-a7-test-setup) | Xilinx Vivado | [Digilent Arty A7-35](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) | Xilinx Artix-7 `XC7A35TICSG324-1L` | [stnolting](https://github.com/stnolting) | +| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | +| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys 4 DDR](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start) | Xilinx Artix-7 `XC7A100TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) | +| :earth_africa: [custom CRC32 processor module for the nexys-a7 boards (**tutorial**)](https://github.com/motius/neorv32/tree/add-custom-crc32-module) | Xilinx Vivado | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [motius](https://github.com/motius) ([ikstvn](https://github.com/ikstvn), [turbinenreiter](https://github.com/turbinenreiter)) | +| :earth_africa: [neorv32-examples](https://github.com/emb4fun/neorv32-examples) | Intel Quartus Prime | Different Terasic boards | Different Intel FPGAs | [emb4fun](https://github.com/emb4fun) | + + +## Setups using Open-Source Toolchains + +| Setup | Toolchain | Board :books: | FPGA | Author(s) | +|:------|:----------|:--------------|:------|:----------| +| :file_folder: [`UPduino v3`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [UPduino v3.0](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [tmeissner](https://github.com/tmeissner) | +| :file_folder: [`FOMU`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [FOMU](https://tomu.im/fomu.html) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) | +| :file_folder: [`iCESugar`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [iCESugar](https://github.com/wuxx/icesugar/blob/master/README_en.md) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) | +| :file_folder: [`AlhambraII`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [AlhambraII](https://alhambrabits.com/alhambra/) | Lattice iCE40HX4K | [zipotron](https://github.com/zipotron) | +| :file_folder: [`Orange Crab`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [Orange Crab](https://github.com/gregdavill/OrangeCrab) | Lattice ECP5-25F | [umarcor](https://github.com/umarcor), [jeremyherbert](https://github.com/jeremyherbert) | +| :file_folder: [`ULX3S`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/) | Lattice ECP5 `LFE5U-85F-6BG381C` | [zipotron](https://github.com/zipotron) | +| :earth_africa: [`ULX3S-SDRAM`](https://github.com/zipotron/neorv32-complex-setups) | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/) | Lattice ECP5 `LFE5U-85F-6BG381C` | [zipotron](https://github.com/zipotron) | + +:information_source: All setups using open-source toolchains are located in the +[`osflow`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) folder. +See the README there for more information how to run a specific setup / configuration. + + +## Adding Your Project Setup + +Please respect the following guidelines if you'd like to add (or link) your setup to the list. + +* check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md) +* add a link if the board you are using provides online documentation (and/or can be purchased somewhere) +* use the :file_folder: emoji (`:file_folder:`) if the setup is located *in this* folder; use the :earth_africa: +emoji (`:earth_africa:`) if it is a link to your local project +* please add a `README` to give some brief information about the setup and a `.gitignore` to keep things clean; +take a look at [`UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/setups/radiant/UPduino_v3) to get some ideas what a project setup might look like + + +## Setup-Specific NEORV32 Software Framework Modification + +In order to use the features provided by the setups, minor *optional* changes can be made to the default NEORV32 setup. + +* To change the default data memory size take a look at the :books: User Guide section +[_General Software Framework Setup_](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) +* To modify the SPI flash base address for storing/booting software application see :books: User Guide section +[_Customizing the Internal Bootloader_](https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader) diff --git a/Libs/RiscV/NEORV32/setups/osflow/.gitignore b/Libs/RiscV/NEORV32/setups/osflow/.gitignore new file mode 100644 index 0000000..ff73747 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/.gitignore @@ -0,0 +1,8 @@ +*.asc +*.bit +*.cfg +*.dfu +*.history +*.json +*.svf +*-report.txt diff --git a/Libs/RiscV/NEORV32/setups/osflow/Makefile b/Libs/RiscV/NEORV32/setups/osflow/Makefile new file mode 100644 index 0000000..6890a09 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/Makefile @@ -0,0 +1,134 @@ +TEMPLATES := ../../rtl/processor_templates +MV := mv + +.DEFAULT_GOAL := help + +TASK := clean $(BITSTREAM) + +FOMU_REV ?= pvt +OrangeCrab_REV ?= r02-25F +UPduino_REV ?= v3 + +#ifndef BOARD +#$(error BOARD needs to be set to 'Fomu', 'iCESugar', 'UPDuino', 'iCEBreaker' or 'OrangeCrab' !) +#endif + +run: + $(eval TASK ?= clean $(BITSTREAM)) + $(MAKE) -f common.mk \ + BOARD_SRC=./board_tops/neorv32_$(BOARD)_BoardTop_$(DESIGN).vhd \ + TOP=neorv32_$(BOARD)_BoardTop_$(DESIGN) \ + ID=$(DESIGN) \ + $(TASK) + IMPL="$${BITSTREAM%%.*}"; for item in ".bit" ".svf"; do \ + if [ -f "./$$IMPL$$item" ]; then \ + $(MV) "./$$IMPL$$item" ./; \ + fi \ + done + +# Boards + +Fomu: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(FOMU_REV)_$(DESIGN).bit) +ifeq ($(DESIGN),Minimal) + $(eval IMEM_SRC := ../../rtl/core/mem/neorv32_imem.default.vhd) +else + $(eval IMEM_SRC := devices/ice40/neorv32_imem.ice40up_spram.vhd) +endif + $(eval NEORV32_MEM_SRC ?= ${IMEM_SRC} devices/ice40/neorv32_dmem.ice40up_spram.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run + +iCESugar: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) + $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run + +UPduino: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(UPduino_REV)_$(DESIGN).bit) + $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run + +OrangeCrab: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(OrangeCrab_REV)_$(DESIGN).bit) + $(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run + +AlhambraII: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) + $(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run + +ULX3S: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) + $(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run + +iCEBreaker: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) + $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run + +# Designs + +Minimal: + $(eval DESIGN ?= $@) + $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd) + $(MAKE) \ + DESIGN="$(DESIGN)" \ + DESIGN_SRC="$(DESIGN_SRC)" \ + $(BOARD) + +MinimalBoot: + $(eval DESIGN ?= $@) + $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_MinimalBoot.vhd) + $(MAKE) \ + DESIGN="$(DESIGN)" \ + DESIGN_SRC="$(DESIGN_SRC)" \ + $(BOARD) + +UP5KDemo: + $(eval DESIGN ?= $@) + $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_UP5KDemo.vhd) + $(MAKE) \ + DESIGN="$(DESIGN)" \ + DESIGN_SRC="$(DESIGN_SRC)" \ + $(BOARD) + +MixedLanguage: + $(eval DESIGN ?= $@) + $(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd) + $(eval NEORV32_VERILOG_SRC ?= devices/ice40/sb_ice40_components.v board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v) + $(MAKE) \ + DESIGN="$(DESIGN)" \ + DESIGN_SRC="$(DESIGN_SRC)" \ + NEORV32_VERILOG_SRC="$(NEORV32_VERILOG_SRC)" \ + $(BOARD) + +# Help + +help: + @echo "Open-Source Synthesis, P&R, Routing and Bitstream Generation" + @echo "Usage: make BOARD= " + @echo "Example: make BOARD=Fomu Minimal" + diff --git a/Libs/RiscV/NEORV32/setups/osflow/PnR_Bit.mk b/Libs/RiscV/NEORV32/setups/osflow/PnR_Bit.mk new file mode 100644 index 0000000..cdfbd4f --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/PnR_Bit.mk @@ -0,0 +1,14 @@ +${IMPL}.${PNR2BIT_EXT}: $(IMPL).json $(CONSTRAINTS) + $(NEXTPNR) \ + $(PNRFLAGS) \ + --$(CONSTRAINTS_FORMAT) $(CONSTRAINTS) \ + --json $(IMPL).json \ + --${NEXTPNR_OUT} $@ 2>&1 | tee nextpnr-report.txt + +${IMPL}.bit: ${IMPL}.${PNR2BIT_EXT} + $(PACKTOOL) $< $@ + +ifeq ($(DEVICE_SERIES),ecp5) +${IMPL}.svf: ${IMPL}.${PNR2BIT_EXT} + $(PACKTOOL) $(PACKARGS) --svf $@ $< +endif diff --git a/Libs/RiscV/NEORV32/setups/osflow/README.md b/Libs/RiscV/NEORV32/setups/osflow/README.md new file mode 100644 index 0000000..4b61357 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/README.md @@ -0,0 +1,145 @@ +# Exemplary FPAG Board Setups - Using Open Source Toolchains + +* [Folder Structure](#Folder-Structure) +* [Prerequisites](#Prerequisites) +* [How To Run](#How-To-Run) +* [Porting to a new FPGA or Board](#Porting-to-a-new-FPGA-or-Board) + +This folder provides the infrastructure for generating bitstream for various FPGAs using +open-source toolchains. Synthesis is based on [ghdl-yosys](https://github.com/ghdl/ghdl-yosys-plugin). + +:information_source: Note that the provided setups just implement very basic SoC configurations. +These setups are intended as minimal example (how to synthesize the processor) for a given FPGA + board +that can be used as starting point to build more complex user-defined SoCs. + +## Folder Structure + +* `.`: Main makefile (main entry point) and partial-makefiles for synthesis, place & route and bitstream generation +* `boards`: board-specific _partial makefiles_ (used by main makefile "`Makefile`") for generating bitstreams +* `board_top`: board-specific top entities (board wrappers; may include FPGA-specific modules) +* `constraints`: physical constraints (mainly pin mappings) +* `devices`: FPGA-specific primitives and optimized processor modules (like memories) + + +## Prerequisites + +:construction: TODO :construction: + +* local installation of the tools +* using containers + + +## How To Run + +:construction: TODO :construction: + +The `Makefile` in this folder is the main entry point. To run the whole process of synthesis, place & route and bitstream +generation run: + +**Prototype:** +``` +make BOARD= +``` + +**Example:** +``` +make BOARD=Fomu Minimal +``` + +`` specifies the actual FPGA board and implicitly sets the FPGA type. The currently supported FPGA board +targets are listed in the `boards/` folder where each partial-makefile corresponds to a supported platform. + +`` is used to define the actual SoC top. Available SoCs are located in +[`rtl/processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates). + + +## Porting to a new FPGA or Board + +This sections illustrates how to add a new basic setup for a specific FPGA and board. This tutorial used the iCEBreaker +"MinimalBoot" setup as reference. + +#### 1. Setup a board- and FPGA-specific top entity + +1. Write a new top design unit that instantiates one of the provided processor templates from +[`rtl/processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates). +This new top unit can be a Verilog or VHDL file. +2. _Optional:_ You can also include FPGA-specific primitives like PLLs or block RAMs (but keep it simple). These components +need to be added to a FPGA-specific library in [`setups/osflow/devices`](https://github.com/stnolting/neorv32/tree/master/setups/osflow/devices). +3. Try to keep the external IO at a minimum even if the targeted FPGA boards provides cool features. Besides of clock and reset +you need to add at least one kind of IO interface like a UART, GPIO or PWM. +4. Give your new top entity file a specific name that includes the board's name and the instantiated processor template. +The name scheme is `neorv32_[board-name]_BoardTop_[template-name].[v/vhd]`. +5. Put this file in `setups/osflow/board_tops`. +6. Take a look at the iCEBreaker MinimalBoot top entity as a reference: +[`setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd) + +#### 2. Pin mapping + +1. Add a new constraints file to define the mapping between the your top unit's IO and the FPGA's physical pins. +You can add _all_ of the FPGA's physical pins even though just a subset is used by the new setup. +2. Name the new constraints file according to the board `[board-name].pcf`. +3. Put this file in `setups/osflow/constraints`. +4. Take a look at the iCEBreaker pin mapping as a reference: +[`setups/osflow/constraints/iCEBreaker.pcf`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/constraints/iCEBreaker.pcf) + +#### 3. Adding a board-specific makefile + +1. Add a board-specific makefile to the `setups/osflow/boards` folder. Name the new constraints file according to the board `[board-name].mk`. +2. The makefile contains (at least) one target to build the final bitstream: +```makefile +.PHONY: all + +all: bit + echo "! Built $(IMPL) for $(BOARD)" +``` +3. Take a look at the iCEBreaker pin mapping as a reference: +[` setups/osflow/boards/iCEBreaker.mk`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/boards/iCEBreaker.mk) + +#### 4. Adding a new target to `index.mk` + +1. Add a new conditional section to the boards management makefile `setups/osflow/boards/index.mk`. +2. This board-specific section sets variables that are required to run synthesis, mapping, place & route and bitstream generation: + * `CONSTRAINTS` defines the physical pin mapping file + * `PNRFLAGS` defines the FPGA-specific flags for mapping and place & route + * `IMPL` defines the setup's implementation name +```makefile +ifeq ($(BOARD),iCEBreaker) +$(info Setting constraints and implementation args for BOARD iCEBreaker) + +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf +PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail +IMPL ?= neorv32_$(BOARD)_$(ID) + +endif +``` + +#### 5. Adding a new target to the main makefile + +1. As final step add the new setup to the main osflow makefile `setups/osflow/Makefile`. +2. Use the board's name to create a new makefile target. + * The new target should set the final bitstream's name using the `BITSTREAM` variable. + * Alternative _memory_ HDL sources like FPGA-optimized module can be set using the `NEORV32_MEM_SRC` variable. +```makefile +iCEBreaker: + $(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit) + $(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd) + $(MAKE) \ + BITSTREAM="$(BITSTREAM)" \ + NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \ + run +``` + +#### 6. _Optional:_ Add the new setup to the automatic "Implementation" github workflow + +If you like you can add the new setup to the automatic build environment of the project. The project's "Implementation" +workflow will generate bitstreams for all configured osflow setups on every repository push. This is used to check for +regressions and also to provide up-to-date bitstreams that can be used right away. + +1. Add the new setup to the job matrix file `.github/generate-job-matrix.py`. +```python +{ + 'board': 'iCEBreaker', + 'design': 'MinimalBoot', + 'bitstream': 'neorv32_iCEBreaker_MinimalBoot.bit' +}, +``` diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd new file mode 100644 index 0000000..621ab8e --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd @@ -0,0 +1,128 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup including the bootloader, for the AlhambraII (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_AlhambraII_BoardTop_MinimalBoot is + port ( + -- external clock (12 MHz) + AlhambraII_CLK : in std_logic; + -- LED outputs + AlhambraII_LED0 : out std_logic; + AlhambraII_LED1 : out std_logic; + AlhambraII_LED2 : out std_logic; + AlhambraII_LED3 : out std_logic; + AlhambraII_LED4 : out std_logic; + AlhambraII_LED5 : out std_logic; + AlhambraII_LED6 : out std_logic; + AlhambraII_LED7 : out std_logic; + -- UART0 + AlhambraII_RX : in std_logic; + AlhambraII_TX : out std_logic + ); +end entity; + +architecture neorv32_AlhambraII_BoardTop_MinimalBoot_rtl of neorv32_AlhambraII_BoardTop_MinimalBoot is + + -- configuration -- + constant f_clock_c : natural := 12000000; -- clock frequency in Hz + + -- reset generator -- + signal rst_cnt : std_logic_vector(8 downto 0) := (others => '0'); -- initialized by bitstream + signal sys_rstn : std_logic; + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(3 downto 0); + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- Reset Generator ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + reset_generator: process(AlhambraII_CLK) + begin + if rising_edge(AlhambraII_CLK) then + if (rst_cnt(rst_cnt'left) = '0') then + rst_cnt <= std_logic_vector(unsigned(rst_cnt) + 1); + end if; + end if; + end process reset_generator; + + sys_rstn <= rst_cnt(rst_cnt'left); + + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE => 4*1024, -- size of processor-internal instruction memory in bytes + MEM_INT_DMEM_SIZE => 2*1024 -- size of processor-internal data memory in bytes + ) + port map ( + -- Global control -- + clk_i => std_ulogic(AlhambraII_CLK), + rstn_i => std_ulogic(sys_rstn), + + -- GPIO -- + gpio_o => con_gpio_o, + + -- primary UART -- + uart_txd_o => AlhambraII_TX, -- UART0 send data + uart_rxd_i => AlhambraII_RX, -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + AlhambraII_LED0 <= con_gpio_o(0); + AlhambraII_LED1 <= con_gpio_o(1); + AlhambraII_LED2 <= con_gpio_o(2); + AlhambraII_LED3 <= con_gpio_o(3); + AlhambraII_LED4 <= '0'; -- unused + AlhambraII_LED5 <= con_pwm(0); + AlhambraII_LED6 <= con_pwm(1); + AlhambraII_LED7 <= con_pwm(2); + + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd new file mode 100644 index 0000000..d2c7b78 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd @@ -0,0 +1,149 @@ +-- ################################################################################################# +-- # << NEORV32 - Example minimal setup for the Fomu (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_Fomu_BoardTop_Minimal is + port ( + -- 48MHz Clock input + clki : in std_logic; + -- LED outputs + rgb : out std_logic_vector(2 downto 0); + -- USB Pins (which should be statically driven if not being used) + usb_dp : out std_logic; + usb_dn : out std_logic; + usb_dp_pu : out std_logic + ); +end entity; + +architecture neorv32_Fomu_BoardTop_Minimal_rtl of neorv32_Fomu_BoardTop_Minimal is + + -- configuration -- + constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- Assign USB pins to "0" so as to disconnect Fomu from + -- the host system. Otherwise it would try to talk to + -- us over USB, which wouldn't work since we have no stack. + usb_dp <= '0'; + usb_dn <= '0'; + usb_dp_pu <= '0'; + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 48 -o 21: + -- F_PLLIN: 48.000 MHz (given) + -- F_PLLOUT: 22.000 MHz (requested) + -- F_PLLOUT: 22.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 16.000 MHz + -- F_VCO: 704.000 MHz + -- DIVR: 2 (4'b0010) + -- DIVF: 43 (7'b0101011) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"2", + DIVF => 7x"2B", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => clki, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_Minimal + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB1PWM => con_pwm(1), -- I - red - pwm channel 1 || BOOT blink + RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 + RGB2 => rgb(2), -- O - blue + RGB1 => rgb(1), -- O - red + RGB0 => rgb(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd new file mode 100644 index 0000000..ae50b9e --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd @@ -0,0 +1,174 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_Fomu_BoardTop_MinimalBoot is + port ( + -- 48MHz Clock input + clki : in std_logic; + -- LED outputs + rgb : out std_logic_vector(2 downto 0); + -- USB Pins (which should be statically driven if not being used) + usb_dp : out std_logic; + usb_dn : out std_logic; + usb_dp_pu : out std_logic + ); +end entity; + +architecture neorv32_Fomu_BoardTop_MinimalBoot_rtl of neorv32_Fomu_BoardTop_MinimalBoot is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(3 downto 0); + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- Assign USB pins to "0" so as to disconnect Fomu from + -- the host system. Otherwise it would try to talk to + -- us over USB, which wouldn't work since we have no stack. + usb_dp <= '0'; + usb_dn <= '0'; + usb_dp_pu <= '0'; + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : SB_HFOSC + generic map ( + CLKHF_DIV => "0b10" -- 12 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 18: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 18.000 MHz (requested) + -- F_PLLOUT: 18.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 576.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 47 (7'b0101111) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"2F", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => hf_osc_clk, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- GPIO -- + gpio_o => con_gpio_o, + + -- primary UART -- + uart_txd_o => open, -- UART0 send data + uart_rxd_i => '0', -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink + RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 + RGB2 => rgb(2), -- O - blue + RGB1 => rgb(1), -- O - red + RGB0 => rgb(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd new file mode 100644 index 0000000..de05fdb --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd @@ -0,0 +1,139 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_Fomu_BoardTop_MixedLanguage is + port ( + -- 48MHz Clock input + clki : in std_logic; + -- LED outputs + rgb : out std_logic_vector(2 downto 0); + -- USB Pins (which should be statically driven if not being used) + usb_dp : out std_logic; + usb_dn : out std_logic; + usb_dp_pu : out std_logic + ); +end entity; + +architecture neorv32_Fomu_BoardTop_MixedLanguage_rtl of neorv32_Fomu_BoardTop_MixedLanguage is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + component neorv32_Fomu_MixedLanguage_ClkGen + port ( + clk_o : out std_logic; + rstn_o : out std_logic + ); + end component; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(3 downto 0); + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- Assign USB pins to "0" so as to disconnect Fomu from + -- the host system. Otherwise it would try to talk to + -- us over USB, which wouldn't work since we have no stack. + usb_dp <= '0'; + usb_dn <= '0'; + usb_dp_pu <= '0'; + + -- On-Chip HF Oscillator and System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + Clk_inst : neorv32_Fomu_MixedLanguage_ClkGen + port map ( + clk_o => pll_clk, + rstn_o => pll_rstn + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- GPIO -- + gpio_o => con_gpio_o, + + -- primary UART -- + uart_txd_o => open, -- UART0 send data + uart_rxd_i => '0', -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink + RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 + RGB2 => rgb(2), -- O - blue + RGB1 => rgb(1), -- O - red + RGB0 => rgb(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd new file mode 100644 index 0000000..e1a8f5a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd @@ -0,0 +1,185 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for the Fomu (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_Fomu_BoardTop_UP5KDemo is + port ( + -- 48MHz Clock input + clki : in std_logic; + -- LED outputs + rgb : out std_logic_vector(2 downto 0); + -- USB Pins (which should be statically driven if not being used) + usb_dp : out std_logic; + usb_dn : out std_logic; + usb_dp_pu : out std_logic + ); +end entity; + +architecture neorv32_Fomu_BoardTop_UP5KDemo_rtl of neorv32_Fomu_BoardTop_UP5KDemo is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_pwm : std_ulogic_vector(2 downto 0); + signal con_gpio_o : std_ulogic_vector(3 downto 0); + +begin + + -- Assign USB pins to "0" so as to disconnect Fomu from + -- the host system. Otherwise it would try to talk to + -- us over USB, which wouldn't work since we have no stack. + usb_dp <= '0'; + usb_dn <= '0'; + usb_dp_pu <= '0'; + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : SB_HFOSC + generic map ( + CLKHF_DIV => "0b10" -- 12 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 18: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 18.000 MHz (requested) + -- F_PLLOUT: 18.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 576.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 47 (7'b0101111) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"2F", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => hf_osc_clk, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + -- primary UART -- + uart_txd_o => open, + uart_rxd_i => '0', + uart_rts_o => open, + uart_cts_i => '0', + -- SPI to on-board flash -- + flash_sck_o => open, + flash_sdo_o => open, + flash_sdi_i => '0', + flash_csn_o => open, + -- SPI to IO pins -- + spi_sck_o => open, + spi_sdo_o => open, + spi_sdi_i => '0', + spi_csn_o => open, + -- TWI -- + twi_sda_io => open, + twi_scl_io => open, + -- GPIO -- + gpio_i => (others=>'0'), + gpio_o => con_gpio_o, + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink + RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 + RGB2 => rgb(2), -- O - blue + RGB1 => rgb(1), -- O - red + RGB0 => rgb(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd new file mode 100644 index 0000000..801f129 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd @@ -0,0 +1,130 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup including the bootloader, for the OrangeCrab (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ECP5; +use ECP5.components.all; -- for device primitives and macros + +entity neorv32_OrangeCrab_BoardTop_MinimalBoot is + port ( + -- Clock and Reset inputs + OrangeCrab_CLK : in std_logic; + OrangeCrab_RST_N : in std_logic; + -- LED outputs + OrangeCrab_LED_RGB_R : out std_logic; + OrangeCrab_LED_RGB_G : out std_logic; + OrangeCrab_LED_RGB_B : out std_logic; + -- UART0 + OrangeCrab_GPIO_0 : in std_logic; + OrangeCrab_GPIO_1 : out std_logic; + OrangeCrab_GPIO_9 : out std_logic; + -- USB Pins (which should be statically driven if not being used) + OrangeCrab_USB_D_P : out std_logic; + OrangeCrab_USB_D_N : out std_logic; + OrangeCrab_USB_DP_PU : out std_logic + ); +end entity; + +architecture neorv32_OrangeCrab_BoardTop_MinimalBoot_rtl of neorv32_OrangeCrab_BoardTop_MinimalBoot is + + -- configuration -- + constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz + + -- Globals + signal pll_clk: std_logic; + + -- internal IO connection -- + signal con_pwm : std_logic_vector(2 downto 0); + signal con_gpio_o : std_ulogic_vector(3 downto 0); + +begin + + -- Assign USB pins to "0" so as to disconnect OrangeCrab from + -- the host system. Otherwise it would try to talk to + -- us over USB, which wouldn't work since we have no stack. + OrangeCrab_USB_D_P <= '0'; + OrangeCrab_USB_D_N <= '0'; + OrangeCrab_USB_DP_PU <= '0'; + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + PLL_inst: EHXPLLL + generic map ( + CLKI_DIV => 2, -- from `ecppll -i 48 -o 24` + CLKFB_DIV => 1, + CLKOP_DIV => 25 + ) + port map ( + CLKI => OrangeCrab_CLK, + CLKFB => pll_clk, + ENCLKOP => '1', + CLKOP => pll_clk, + LOCK => OrangeCrab_GPIO_9 + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE => 16*1024, + MEM_INT_DMEM_SIZE => 8*1024 + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(OrangeCrab_RST_N), + + -- GPIO -- + gpio_o => con_gpio_o, + + -- primary UART -- + uart_txd_o => OrangeCrab_GPIO_1, -- UART0 send data + uart_rxd_i => OrangeCrab_GPIO_0, -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + OrangeCrab_LED_RGB_R <= con_pwm(0) or not con_gpio_o(0); + OrangeCrab_LED_RGB_G <= con_pwm(1); + OrangeCrab_LED_RGB_B <= con_pwm(2); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd new file mode 100644 index 0000000..63aaa25 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd @@ -0,0 +1,110 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup including the bootloader, for the ULX3S (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ECP5; +use ECP5.components.all; -- for device primitives and macros + +entity neorv32_ULX3S_BoardTop_MinimalBoot is + port ( + -- Clock and Reset inputs + ULX3S_CLK : in std_logic; + ULX3S_RST_N : in std_logic; + -- LED outputs + ULX3S_LED0 : out std_logic; + ULX3S_LED1 : out std_logic; + ULX3S_LED2 : out std_logic; + ULX3S_LED3 : out std_logic; + ULX3S_LED4 : out std_logic; + ULX3S_LED5 : out std_logic; + ULX3S_LED6 : out std_logic; + ULX3S_LED7 : out std_logic; + -- UART0 + ULX3S_RX : in std_logic; + ULX3S_TX : out std_logic + ); +end entity; + +architecture neorv32_ULX3S_BoardTop_MinimalBoot_rtl of neorv32_ULX3S_BoardTop_MinimalBoot is + + -- configuration -- + constant f_clock_c : natural := 25000000; -- clock frequency in Hz + + -- internal IO connection -- + signal con_pwm : std_logic_vector(2 downto 0); + signal con_gpio_o : std_ulogic_vector(3 downto 0); + +begin + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE => 16*1024, + MEM_INT_DMEM_SIZE => 8*1024 + ) + port map ( + -- Global control -- + clk_i => std_ulogic(ULX3S_CLK), + rstn_i => std_ulogic(ULX3S_RST_N), + + -- GPIO -- + gpio_o => con_gpio_o, + + -- primary UART -- + uart_txd_o => ULX3S_TX, -- UART0 send data + uart_rxd_i => ULX3S_RX, -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ULX3S_LED0 <= con_gpio_o(0); + ULX3S_LED1 <= con_gpio_o(1); + ULX3S_LED2 <= con_gpio_o(2); + ULX3S_LED3 <= con_gpio_o(3); + ULX3S_LED4 <= '0'; -- unused + ULX3S_LED5 <= con_pwm(0); + ULX3S_LED6 <= con_pwm(1); + ULX3S_LED7 <= con_pwm(2); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd new file mode 100644 index 0000000..315273d --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd @@ -0,0 +1,163 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_UPduino_BoardTop_MinimalBoot is + port ( + -- UART (uart0) -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- GPIO -- + gpio_o : out std_ulogic_vector(3 downto 0); + -- PWM (to on-board RGB power LED) -- + pwm_o : out std_logic_vector(2 downto 0) + ); +end entity; + +architecture neorv32_UPduino_BoardTop_MinimalBoot_rtl of neorv32_UPduino_BoardTop_MinimalBoot is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : SB_HFOSC + generic map ( + CLKHF_DIV => "0b10" -- 12 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 18: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 18.000 MHz (requested) + -- F_PLLOUT: 18.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 576.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 47 (7'b0101111) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"2F", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => hf_osc_clk, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- GPIO -- + gpio_o => gpio_o, + + -- primary UART -- + uart_txd_o => uart_txd_o, -- UART0 send data + uart_rxd_i => uart_rxd_i, -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 + RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 + RGB2 => pwm_o(2), -- O - red + RGB1 => pwm_o(1), -- O - blue + RGB0 => pwm_o(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd new file mode 100644 index 0000000..46c1a73 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd @@ -0,0 +1,204 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_UPduino_BoardTop_UP5KDemo is + port ( + -- UART (uart0) -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- SPI to on-board flash -- + flash_sck_o : out std_ulogic; + flash_sdo_o : out std_ulogic; + flash_sdi_i : in std_ulogic; + flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0) + -- SPI to IO pins -- + spi_sck_o : out std_ulogic; + spi_sdo_o : out std_ulogic; + spi_sdi_i : in std_ulogic; + spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1) + -- TWI -- + twi_sda_io : inout std_logic; + twi_scl_io : inout std_logic; + -- GPIO -- + gpio_i : in std_ulogic_vector(3 downto 0); + gpio_o : out std_ulogic_vector(3 downto 0); + -- PWM (to on-board RGB power LED) -- + pwm_o : out std_ulogic_vector(2 downto 0) + ); +end entity; + +architecture neorv32_UPduino_BoardTop_UP5KDemo_rtl of neorv32_UPduino_BoardTop_UP5KDemo is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_pwm : std_ulogic_vector(2 downto 0); + signal con_spi_sdi : std_ulogic; + signal con_spi_csn : std_ulogic; + +begin + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : SB_HFOSC + generic map ( + CLKHF_DIV => "0b10" -- 12 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 18: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 18.000 MHz (requested) + -- F_PLLOUT: 18.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 576.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 47 (7'b0101111) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"2F", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => hf_osc_clk, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- primary UART -- + uart_txd_o => uart_txd_o, + uart_rxd_i => uart_rxd_i, + uart_rts_o => open, + uart_cts_i => '0', + + -- SPI to on-board flash -- + flash_sck_o => flash_sck_o, + flash_sdo_o => flash_sdo_o, + flash_sdi_i => flash_sdi_i, + flash_csn_o => flash_csn_o, + + -- SPI to IO pins -- + spi_sck_o => spi_sck_o, + spi_sdo_o => spi_sdo_o, + spi_sdi_i => con_spi_sdi, + spi_csn_o => con_spi_csn, + + -- TWI -- + twi_sda_io => twi_sda_io, + twi_scl_io => twi_scl_io, + + -- GPIO -- + gpio_i => gpio_i, + gpio_o => gpio_o, + + -- PWM (to on-board RGB power LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- SPI sdi read-back -- + spi_csn_o <= con_spi_csn; + con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i; + + -- RGB -- + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000001", + RGB1_CURRENT => "0b000001", + RGB2_CURRENT => "0b000001" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 + RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2 + RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 + RGB2 => pwm_o(2), -- O - red + RGB1 => pwm_o(1), -- O - blue + RGB0 => pwm_o(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd new file mode 100644 index 0000000..003e1af --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd @@ -0,0 +1,163 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_iCEBreaker_BoardTop_MinimalBoot is + port ( + -- UART (uart0) -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- GPIO -- + gpio_o : out std_ulogic_vector(3 downto 0); + -- PWM (to on-board RGB power LED) -- + pwm_o : out std_logic_vector(2 downto 0) + ); +end entity; + +architecture neorv32_iCEBreaker_BoardTop_MinimalBoot_rtl of neorv32_iCEBreaker_BoardTop_MinimalBoot is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : SB_HFOSC + generic map ( + CLKHF_DIV => "0b10" -- 12 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 18: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 18.000 MHz (requested) + -- F_PLLOUT: 18.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 576.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 47 (7'b0101111) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"2F", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => hf_osc_clk, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- GPIO -- + gpio_o => gpio_o, + + -- primary UART -- + uart_txd_o => uart_txd_o, -- UART0 send data + uart_rxd_i => uart_rxd_i, -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 + RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 + RGB2 => pwm_o(2), -- O - red + RGB1 => pwm_o(1), -- O - blue + RGB0 => pwm_o(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_UP5KDemo.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_UP5KDemo.vhd new file mode 100644 index 0000000..880524f --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_UP5KDemo.vhd @@ -0,0 +1,205 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_iCEBreaker_BoardTop_UP5KDemo is + port ( + user_reset_btn : in std_ulogic; + -- UART (uart0) -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- SPI to on-board flash -- + flash_sck_o : out std_ulogic; + flash_sdo_o : out std_ulogic; + flash_sdi_i : in std_ulogic; + flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0) + -- SPI to IO pins -- + spi_sck_o : out std_ulogic; + spi_sdo_o : out std_ulogic; + spi_sdi_i : in std_ulogic; + spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1) + -- TWI -- + twi_sda_io : inout std_logic; + twi_scl_io : inout std_logic; + -- GPIO -- + gpio_i : in std_ulogic_vector(3 downto 0); + gpio_o : out std_ulogic_vector(3 downto 0); + -- PWM (to on-board RGB power LED) -- + pwm_o : out std_ulogic_vector(2 downto 0) + ); +end entity; + +architecture neorv32_iCEBreaker_BoardTop_UP5KDemo_rtl of neorv32_iCEBreaker_BoardTop_UP5KDemo is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_pwm : std_ulogic_vector(2 downto 0); + signal con_spi_sdi : std_ulogic; + signal con_spi_csn : std_ulogic; + +begin + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : SB_HFOSC + generic map ( + CLKHF_DIV => "0b10" -- 12 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 18: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 18.000 MHz (requested) + -- F_PLLOUT: 18.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 576.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 47 (7'b0101111) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"2F", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => hf_osc_clk, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => user_reset_btn, + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- primary UART -- + uart_txd_o => uart_txd_o, + uart_rxd_i => uart_rxd_i, + uart_rts_o => open, + uart_cts_i => '0', + + -- SPI to on-board flash -- + flash_sck_o => flash_sck_o, + flash_sdo_o => flash_sdo_o, + flash_sdi_i => flash_sdi_i, + flash_csn_o => flash_csn_o, + + -- SPI to IO pins -- + spi_sck_o => spi_sck_o, + spi_sdo_o => spi_sdo_o, + spi_sdi_i => con_spi_sdi, + spi_csn_o => con_spi_csn, + + -- TWI -- + twi_sda_io => twi_sda_io, + twi_scl_io => twi_scl_io, + + -- GPIO -- + gpio_i => gpio_i, + gpio_o => gpio_o, + + -- PWM (to on-board RGB power LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- SPI sdi read-back -- + spi_csn_o <= con_spi_csn; + con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i; + + -- RGB -- + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000001", + RGB1_CURRENT => "0b000001", + RGB2_CURRENT => "0b000001" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB0PWM => con_pwm(1), -- I - green - pwm channel 1 + RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2 + RGB2PWM => con_pwm(0), -- I - red - pwm channel 0 + RGB2 => pwm_o(2), -- O - red + RGB1 => pwm_o(1), -- O - blue + RGB0 => pwm_o(0) -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd new file mode 100644 index 0000000..4fe0cb3 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd @@ -0,0 +1,172 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup with an external clock, for the iCESugar (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_iCESugar_BoardTop_Minimal is + port ( + -- 48MHz Clock input + iCESugarv15_CLK : in std_logic; + -- UART0 + iCESugarv15_RX : in std_logic; + iCESugarv15_TX : out std_logic; + -- LED outputs + iCESugarv15_LED_R : out std_logic; + iCESugarv15_LED_G : out std_logic; + iCESugarv15_LED_B : out std_logic; + -- USB Pins (which should be statically driven if not being used) + iCESugarv15_USB_DP : out std_logic; + iCESugarv15_USB_DN : out std_logic; + iCESugarv15_USB_DP_PU : out std_logic + ); +end entity; + +architecture neorv32_iCESugar_BoardTop_Minimal_rtl of neorv32_iCESugar_BoardTop_Minimal is + + -- configuration -- + constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(3 downto 0); + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- Assign USB pins to "0" so as to disconnect iCESugar from + -- the host system. Otherwise it would try to talk to + -- us over USB, which wouldn't work since we have no stack. + iCESugarv15_USB_DP <= '0'; + iCESugarv15_USB_DN <= '0'; + iCESugarv15_USB_DP_PU <= '0'; + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 22: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 22.000 MHz (requested) + -- F_PLLOUT: 22.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 708.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 58 (7'b0111010) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_PAD + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"3A", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + PACKAGEPIN => iCESugarv15_CLK, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz + CPU_EXTENSION_RISCV_A => false, + CPU_EXTENSION_RISCV_C => false, + CPU_EXTENSION_RISCV_E => false, + CPU_EXTENSION_RISCV_M => false, + CPU_EXTENSION_RISCV_U => false, + CPU_EXTENSION_RISCV_Zfinx => false, + CPU_EXTENSION_RISCV_Zicsr => true, + CPU_EXTENSION_RISCV_Zifencei => false + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- GPIO -- + gpio_o => con_gpio_o, + + -- primary UART -- + uart_txd_o => iCESugarv15_TX, -- UART0 send data + uart_rxd_i => iCESugarv15_RX, -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink + RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 + RGB2 => iCESugarv15_LED_B, -- O - blue + RGB1 => iCESugarv15_LED_R, -- O - red + RGB0 => iCESugarv15_LED_G -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd new file mode 100644 index 0000000..b0ac673 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd @@ -0,0 +1,177 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup including the bootloader, for the iCESugar (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iCE40; +use iCE40.components.all; -- for device primitives and macros + +entity neorv32_iCESugar_BoardTop_MinimalBoot is + port ( + -- LED outputs + iCESugarv15_LED_R : out std_logic; + iCESugarv15_LED_G : out std_logic; + iCESugarv15_LED_B : out std_logic; + -- UART0 + iCESugarv15_RX : in std_logic; + iCESugarv15_TX : out std_logic; + -- USB Pins (which should be statically driven if not being used) + iCESugarv15_USB_DP : out std_logic; + iCESugarv15_USB_DN : out std_logic; + iCESugarv15_USB_DP_PU : out std_logic + ); +end entity; + +architecture neorv32_iCESugar_BoardTop_MinimalBoot_rtl of neorv32_iCESugar_BoardTop_MinimalBoot is + + -- configuration -- + constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- Globals + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(3 downto 0); + signal con_pwm : std_logic_vector(2 downto 0); + +begin + + -- Assign USB pins to "0" so as to disconnect iCESugar from + -- the host system. Otherwise it would try to talk to + -- us over USB, which wouldn't work since we have no stack. + iCESugarv15_USB_DP <= '0'; + iCESugarv15_USB_DN <= '0'; + iCESugarv15_USB_DP_PU <= '0'; + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : SB_HFOSC + generic map ( + CLKHF_DIV => "0b10" -- 12 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- Settings generated by icepll -i 12 -o 18: + -- F_PLLIN: 12.000 MHz (given) + -- F_PLLOUT: 18.000 MHz (requested) + -- F_PLLOUT: 18.000 MHz (achieved) + -- FEEDBACK: SIMPLE + -- F_PFD: 12.000 MHz + -- F_VCO: 576.000 MHz + -- DIVR: 0 (4'b0000) + -- DIVF: 47 (7'b0101111) + -- DIVQ: 5 (3'b101) + -- FILTER_RANGE: 1 (3'b001) + Pll_inst : SB_PLL40_CORE + generic map ( + FEEDBACK_PATH => "SIMPLE", + DIVR => x"0", + DIVF => 7x"2F", + DIVQ => 3x"5", + FILTER_RANGE => 3x"1" + ) + port map ( + REFERENCECLK => hf_osc_clk, + PLLOUTCORE => open, + PLLOUTGLOBAL => pll_clk, + EXTFEEDBACK => '0', + DYNAMICDELAY => x"00", + LOCK => pll_rstn, + BYPASS => '0', + RESETB => '1', + LATCHINPUTVALUE => '0', + SDO => open, + SDI => '0', + SCLK => '0' + ); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot + generic map ( + CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz + ) + port map ( + -- Global control -- + clk_i => std_ulogic(pll_clk), + rstn_i => std_ulogic(pll_rstn), + + -- GPIO -- + gpio_o => con_gpio_o, + + -- primary UART -- + uart_txd_o => iCESugarv15_TX, -- UART0 send data + uart_rxd_i => iCESugarv15_RX, -- UART0 receive data + uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- PWM (to on-board RGB LED) -- + pwm_o => con_pwm + ); + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + RGB_inst: SB_RGBA_DRV + generic map ( + CURRENT_MODE => "0b1", + RGB0_CURRENT => "0b000011", + RGB1_CURRENT => "0b000011", + RGB2_CURRENT => "0b000011" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2 + RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink + RGB0PWM => con_pwm(0), -- I - green - pwm channel 0 + RGB2 => iCESugarv15_LED_B, -- O - blue + RGB1 => iCESugarv15_LED_R, -- O - red + RGB0 => iCESugarv15_LED_G -- O - green + ); + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/AlhambraII.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/AlhambraII.mk new file mode 100644 index 0000000..8c9f85a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/AlhambraII.mk @@ -0,0 +1,4 @@ +.PHONY: all + +all: bit + echo "! Built $(IMPL) for $(BOARD)" diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/Fomu.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/Fomu.mk new file mode 100644 index 0000000..b103198 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/Fomu.mk @@ -0,0 +1,16 @@ +.PHONY: all + +# Default target: run all required targets to build the DFU image. +all: $(IMPL).dfu + echo "! Built $(IMPL) for $(BOARD) $(FOMU_REV)" + +# Use dfu-suffix to generate the DFU image from the FPGA bitstream. +${IMPL}.dfu: $(IMPL).bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 70b1 -a $@ + +# Use df-util to load the DFU image onto the Fomu. +load: $(IMPL).dfu + dfu-util -D $< + +.PHONY: load diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/OrangeCrab.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/OrangeCrab.mk new file mode 100644 index 0000000..8c9f85a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/OrangeCrab.mk @@ -0,0 +1,4 @@ +.PHONY: all + +all: bit + echo "! Built $(IMPL) for $(BOARD)" diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/ULX3S.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/ULX3S.mk new file mode 100644 index 0000000..8c9f85a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/ULX3S.mk @@ -0,0 +1,4 @@ +.PHONY: all + +all: bit + echo "! Built $(IMPL) for $(BOARD)" diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/UPduino.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/UPduino.mk new file mode 100644 index 0000000..8c9f85a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/UPduino.mk @@ -0,0 +1,4 @@ +.PHONY: all + +all: bit + echo "! Built $(IMPL) for $(BOARD)" diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/iCEBreaker.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/iCEBreaker.mk new file mode 100644 index 0000000..8c9f85a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/iCEBreaker.mk @@ -0,0 +1,4 @@ +.PHONY: all + +all: bit + echo "! Built $(IMPL) for $(BOARD)" diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/iCESugar.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/iCESugar.mk new file mode 100644 index 0000000..8c9f85a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/iCESugar.mk @@ -0,0 +1,4 @@ +.PHONY: all + +all: bit + echo "! Built $(IMPL) for $(BOARD)" diff --git a/Libs/RiscV/NEORV32/setups/osflow/boards/index.mk b/Libs/RiscV/NEORV32/setups/osflow/boards/index.mk new file mode 100644 index 0000000..a57645c --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/boards/index.mk @@ -0,0 +1,107 @@ +PCF_PATH ?= constraints + + +ifeq ($(BOARD),Fomu) + +$(info Setting constraints and implementation args for BOARD Fomu) + +# Different Fomu hardware revisions are wired differently and thus +# require different configurations for yosys and nextpnr. +# Configuration is performed by setting the environment variable FOMU_REV accordingly. + +FOMU_REV ?= pvt + +ifeq ($(FOMU_REV),evt1) +YOSYSFLAGS ?= -D EVT=1 -D EVT1=1 -D HAVE_PMOD=1 +PNRFLAGS ?= --up5k --package sg48 +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-evt2.pcf +else ifeq ($(FOMU_REV),evt2) +YOSYSFLAGS ?= -D EVT=1 -D EVT2=1 -D HAVE_PMOD=1 +PNRFLAGS ?= --up5k --package sg48 +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf +else ifeq ($(FOMU_REV),evt3) +YOSYSFLAGS ?= -D EVT=1 -D EVT3=1 -D HAVE_PMOD=1 +PNRFLAGS ?= --up5k --package sg48 +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf +else ifeq ($(FOMU_REV),hacker) +YOSYSFLAGS ?= -D HACKER=1 +PNRFLAGS ?= --up5k --package uwg30 +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf +else ifeq ($(FOMU_REV),pvt) +YOSYSFLAGS ?= -D PVT=1 +PNRFLAGS ?= --up5k --package uwg30 +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf +else +$(error Unrecognized FOMU_REV value. must be "evt1", "evt2", "evt3", "pvt", or "hacker") +endif + +IMPL := neorv32_Fomu_$(FOMU_REV)_$(ID) + +endif + + +ifeq ($(BOARD),iCESugar) +$(info Setting constraints and implementation args for BOARD iCESugar) + +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf +PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail +IMPL ?= neorv32_$(BOARD)_$(ID) + +endif + + +ifeq ($(BOARD),UPduino) +$(info Setting constraints and implementation args for BOARD UPduino) + +UPduino_REV ?= v3 + +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)_v3.pcf +PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail +IMPL ?= neorv32_$(BOARD)_$(UPduino_REV)_$(ID) + +endif + +ifeq ($(BOARD),iCEBreaker) +$(info Setting constraints and implementation args for BOARD iCEBreaker) + +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf +PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail +IMPL ?= neorv32_$(BOARD)_$(ID) + +endif + + + +ifeq ($(BOARD),OrangeCrab) +$(info Setting constraints and implementation args for BOARD OrangeCrab) + +DEVICE_SERIES = ecp5 + +OrangeCrab_REV ?= r02-25F + +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).lpf +PNRFLAGS ?= --25k --package CSFBGA285 --ignore-loops --timing-allow-fail +IMPL ?= neorv32_$(BOARD)_$(OrangeCrab_REV)_$(ID) + +endif + +ifeq ($(BOARD),AlhambraII) +$(info Setting constraints and implementation args for BOARD AlhambraII) + +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf +PNRFLAGS ?= --hx8k --package tq144:4k --ignore-loops --timing-allow-fail +IMPL ?= neorv32_$(BOARD)_$(ID) + +endif + + +ifeq ($(BOARD),ULX3S) +$(info Setting constraints and implementation args for BOARD ULX3S) + +DEVICE_SERIES = ecp5 + +CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).lpf +PNRFLAGS ?= --85k --freq 25 --package CABGA381 --ignore-loops --timing-allow-fail +IMPL ?= neorv32_$(BOARD)_$(ID) + +endif diff --git a/Libs/RiscV/NEORV32/setups/osflow/common.mk b/Libs/RiscV/NEORV32/setups/osflow/common.mk new file mode 100644 index 0000000..7bf264e --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/common.mk @@ -0,0 +1,39 @@ +ID ?= impl_1 + +include boards/index.mk + +ifndef TOP +$(error TOP needs to be specified!) +endif + +include filesets.mk + +ifndef DESIGN_SRC +ifndef BOARD_SRC +$(error Neither DESIGN_SRC nor BOARD_SRC were set!) +endif +endif + +include tools.mk + +ifdef GHDL_PLUGIN_MODULE +YOSYSFLAGS += -m $(GHDL_PLUGIN_MODULE) +endif + +include synthesis.mk +include PnR_Bit.mk + +.PHONY: syn impl bit svf clean + +syn: ${IMPL}.json +impl: ${IMPL}.${PNR2BIT_EXT} +bit: ${IMPL}.bit + +ifeq ($(DEVICE_SERIES),ecp5) +svf: ${IMPL}.svf +endif + +clean: + rm -rf *.{${PNR2BIT_EXT},bit,cf,dfu,history,json,o,svf} *-report.txt + +include boards/$(BOARD).mk diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/AlhambraII.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/AlhambraII.pcf new file mode 100644 index 0000000..8fae040 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/AlhambraII.pcf @@ -0,0 +1,24 @@ +# ----------------------------------------------------------------------------- +#- Alhambra II constraint file (.pcf) +#- By Carlos Dominguez +#- May - 2021 +#- GPL license +#- Repo: https://github.com/zipotron/neorv32 +# ----------------------------------------------------------------------------- + +# UART port (on-board FTDI) +set_io AlhambraII_TX 61 # output (ser-tx) +set_io AlhambraII_RX 62 # input (ser-rx) + +#> External clock (12 MHz) +set_io AlhambraII_CLK 49 + +#> On-Board LEDs +set_io AlhambraII_LED0 45 +set_io AlhambraII_LED1 44 +set_io AlhambraII_LED2 43 +set_io AlhambraII_LED3 42 +set_io AlhambraII_LED4 41 +set_io AlhambraII_LED5 39 +set_io AlhambraII_LED6 38 +set_io AlhambraII_LED7 37 diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt2.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt2.pcf new file mode 100644 index 0000000..f41d27c --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt2.pcf @@ -0,0 +1,34 @@ +# Configuration for the Fomu 'evt2' board +set_io clki 44 +set_io clki_alt 20 +set_io rgb[0] 39 +set_io rgb[1] 40 +set_io rgb[2] 41 +set_io pmod[0] 25 +set_io pmod[1] 26 +set_io pmod[2] 27 +set_io pmod[3] 28 +set_io user[0] 48 +set_io user[1] 47 +set_io user[2] 46 +set_io user[3] 45 +set_io user[4] 42 +set_io user[5] 38 +set_io spi_mosi 14 +set_io spi_miso 17 +set_io spi_clk 15 +set_io spi_cs 16 +set_io spi_io2 18 +set_io spi_io3 19 +set_io uart_tx 21 +set_io uart_rx 13 +set_io usb_dn 37 +set_io usb_dp 34 +set_io usb_dp_pu 35 +set_io usb_dn_pu 36 +set_io dbg[0] 20 +set_io dbg[1] 12 +set_io dbg[2] 11 +set_io dbg[3] 23 +set_io dbg[4] 10 +set_io dbg[5] 9 diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt3.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt3.pcf new file mode 100644 index 0000000..8d6057b --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt3.pcf @@ -0,0 +1,34 @@ +# Configuration for the Fomu 'evt3' board +set_io rgb[0] 39 +set_io rgb[1] 40 +set_io rgb[2] 41 +set_io pmod[0] 28 +set_io pmod[1] 27 +set_io pmod[2] 26 +set_io pmod[3] 23 +set_io clki_alt 20 +set_io clki 44 +set_io user[0] 48 +set_io user[1] 47 +set_io user[2] 46 +set_io user[3] 45 +set_io user[4] 42 +set_io user[5] 38 +set_io spi_mosi 14 +set_io spi_miso 17 +set_io spi_clk 15 +set_io spi_io2 18 +set_io spi_io3 19 +set_io spi_cs 16 +set_io uart_tx 21 +set_io uart_rx 13 +set_io usb_dn 37 +set_io usb_dp 34 +set_io usb_dp_pu 35 +set_io usb_dn_pu 36 +set_io dbg[0] 20 +set_io dbg[1] 12 +set_io dbg[2] 11 +set_io dbg[3] 25 +set_io dbg[4] 10 +set_io dbg[5] 9 diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-hacker.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-hacker.pcf new file mode 100644 index 0000000..3b17e6e --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-hacker.pcf @@ -0,0 +1,16 @@ +# Configuration for the Fomu 'hacker' board +set_io clki F5 # Clock input from 48MHz Oscillator +set_io rgb[0] A5 # Blue LED +set_io rgb[1] B5 # Green LED +set_io rgb[2] C5 # Red LED +set_io user[0] F4 # User touch pad 1 +set_io user[1] E5 # User touch pad 2 +set_io user[2] E4 # User touch pad 3 +set_io user[3] F2 # User touch pad 4 +set_io spi_mosi F1 # SPI Master Out, Slave In Pin +set_io spi_miso E1 # SPI Master In, Slave Out Pin +set_io spi_clk D1 # SPI Master Clock Output Pin +set_io spi_cs C1 # SPI Chip Select +set_io usb_dn A2 # USB D- pad +set_io usb_dp A4 # USB D+ pad +set_io usb_dp_pu D5 # USB D+ pull up (indicates device connected) diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-pvt.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-pvt.pcf new file mode 100644 index 0000000..d600953 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-pvt.pcf @@ -0,0 +1,18 @@ +# Configuration for the Fomu 'pvt' board +set_io clki F4 # Clock input from 48MHz Oscillator +set_io rgb[0] A5 # Blue LED +set_io rgb[1] B5 # Green LED +set_io rgb[2] C5 # Red LED +set_io user[0] E4 # User touch pad 1 +set_io user[1] D5 # User touch pad 2 +set_io user[2] E5 # User touch pad 3 +set_io user[3] F5 # User touch pad 4 +set_io spi_mosi F1 # SPI Master Out, Slave In Pin +set_io spi_miso E1 # SPI Master In, Slave Out Pin +set_io spi_clk D1 # SPI Master Clock Output Pin +set_io spi_cs C1 # SPI Chip Select +set_io spi_io2 F2 +set_io spi_io3 B1 +set_io usb_dn A2 # USB D- pad +set_io usb_dp A1 # USB D+ pad +set_io usb_dp_pu A4 # USB D+ pull up (indicates device connected) diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/OrangeCrab.lpf b/Libs/RiscV/NEORV32/setups/osflow/constraints/OrangeCrab.lpf new file mode 100644 index 0000000..4c559cc --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/OrangeCrab.lpf @@ -0,0 +1,278 @@ +#| OrangeCrab-r02-25F + + +LOCATE COMP "OrangeCrab_CLK" SITE "A9"; +IOBUF PORT "OrangeCrab_CLK" IO_TYPE=LVCMOS33; +FREQUENCY PORT "OrangeCrab_CLK" 48.0 MHz; + +LOCATE COMP "OrangeCrab_RST_N" SITE "V17"; +IOBUF PORT "OrangeCrab_RST_N" IO_TYPE=LVCMOS33; + +LOCATE COMP "OrangeCrab_LED_RGB_R" SITE "K4"; +IOBUF PORT "OrangeCrab_LED_RGB_R" IO_TYPE=LVCMOS33; +LOCATE COMP "OrangeCrab_LED_RGB_G" SITE "M3"; +IOBUF PORT "OrangeCrab_LED_RGB_G" IO_TYPE=LVCMOS33; +LOCATE COMP "OrangeCrab_LED_RGB_B" SITE "J3"; +IOBUF PORT "OrangeCrab_LED_RGB_B" IO_TYPE=LVCMOS33; + +LOCATE COMP "OrangeCrab_USR_BTN" SITE "J17"; +IOBUF PORT "OrangeCrab_USR_BTN" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_USB_D_P" SITE "N1"; +IOBUF PORT "OrangeCrab_USB_D_P" IO_TYPE=LVCMOS33; +LOCATE COMP "OrangeCrab_USB_D_N" SITE "M2"; +IOBUF PORT "OrangeCrab_USB_D_N" IO_TYPE=LVCMOS33; +LOCATE COMP "OrangeCrab_USB_DP_PU" SITE "N2"; +IOBUF PORT "OrangeCrab_USB_DP_PU" IO_TYPE=LVCMOS33; + +LOCATE COMP "OrangeCrab_GPIO_0" SITE "N17"; +IOBUF PORT "OrangeCrab_GPIO_0" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_0" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_1" SITE "M18"; +IOBUF PORT "OrangeCrab_GPIO_1" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_1" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_5" SITE "B10"; +IOBUF PORT "OrangeCrab_GPIO_5" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_5" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_6" SITE "B9"; +IOBUF PORT "OrangeCrab_GPIO_6" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_6" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_9" SITE "C8"; +IOBUF PORT "OrangeCrab_GPIO_9" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_9" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_10" SITE "B8"; +IOBUF PORT "OrangeCrab_GPIO_10" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_10" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_11" SITE "A8"; +IOBUF PORT "OrangeCrab_GPIO_11" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_11" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_12" SITE "H2"; +IOBUF PORT "OrangeCrab_GPIO_12" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_12" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_13" SITE "J2"; +IOBUF PORT "OrangeCrab_GPIO_13" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_13" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_A0" SITE "L4"; +IOBUF PORT "OrangeCrab_GPIO_A0" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_A0" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_A1" SITE "N3"; +IOBUF PORT "OrangeCrab_GPIO_A1" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_A1" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_A2" SITE "N4"; +IOBUF PORT "OrangeCrab_GPIO_A2" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_A2" PULLMODE=DOWN; +LOCATE COMP "OrangeCrab_GPIO_A3" SITE "H4"; +IOBUF PORT "OrangeCrab_GPIO_A3" IO_TYPE=LVCMOS33; +IOBUF PORT "OrangeCrab_GPIO_A3" PULLMODE=DOWN; + +LOCATE COMP "OrangeCrab_DDRAM_A[0]" SITE "C4"; +IOBUF PORT "OrangeCrab_DDRAM_A[0]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[1]" SITE "D2"; +IOBUF PORT "OrangeCrab_DDRAM_A[1]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[2]" SITE "D3"; +IOBUF PORT "OrangeCrab_DDRAM_A[2]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[3]" SITE "A3"; +IOBUF PORT "OrangeCrab_DDRAM_A[3]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[3]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[4]" SITE "A4"; +IOBUF PORT "OrangeCrab_DDRAM_A[4]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[4]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[5]" SITE "D4"; +IOBUF PORT "OrangeCrab_DDRAM_A[5]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[5]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[6]" SITE "C3"; +IOBUF PORT "OrangeCrab_DDRAM_A[6]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[6]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[7]" SITE "B2"; +IOBUF PORT "OrangeCrab_DDRAM_A[7]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[7]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[8]" SITE "B1"; +IOBUF PORT "OrangeCrab_DDRAM_A[8]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[8]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[9]" SITE "D1"; +IOBUF PORT "OrangeCrab_DDRAM_A[9]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[9]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[10]" SITE "A7"; +IOBUF PORT "OrangeCrab_DDRAM_A[10]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[10]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[11]" SITE "C2"; +IOBUF PORT "OrangeCrab_DDRAM_A[11]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[11]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[12]" SITE "B6"; +IOBUF PORT "OrangeCrab_DDRAM_A[12]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[12]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[13]" SITE "C1"; +IOBUF PORT "OrangeCrab_DDRAM_A[13]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[13]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[14]" SITE "A2"; +IOBUF PORT "OrangeCrab_DDRAM_A[14]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[14]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_A[15]" SITE "C7"; +IOBUF PORT "OrangeCrab_DDRAM_A[15]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_A[15]" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_BA[0]" SITE "D6"; +IOBUF PORT "OrangeCrab_DDRAM_BA[0]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_BA[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_BA[1]" SITE "B7"; +IOBUF PORT "OrangeCrab_DDRAM_BA[1]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_BA[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_BA[2]" SITE "A6"; +IOBUF PORT "OrangeCrab_DDRAM_BA[2]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_BA[2]" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_RAS_N" SITE "C12"; +IOBUF PORT "OrangeCrab_DDRAM_RAS_N" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_RAS_N" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_CAS_N" SITE "D13"; +IOBUF PORT "OrangeCrab_DDRAM_CAS_N" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_CAS_N" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_WE_N" SITE "B12"; +IOBUF PORT "OrangeCrab_DDRAM_WE_N" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_WE_N" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_CS_N" SITE "A12"; +IOBUF PORT "OrangeCrab_DDRAM_CS_N" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_CS_N" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_DM[0]" SITE "D16"; +IOBUF PORT "OrangeCrab_DDRAM_DM[0]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DM[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "OrangeCrab_DDRAM_DM[1]" SITE "G16"; +IOBUF PORT "OrangeCrab_DDRAM_DM[1]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DM[1]" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_DQ[0]" SITE "C17"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[1]" SITE "D15"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[2]" SITE "B17"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[3]" SITE "C16"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[4]" SITE "A15"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[5]" SITE "B13"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[6]" SITE "A17"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[7]" SITE "A13"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[8]" SITE "F17"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[9]" SITE "F16"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[10]" SITE "G15"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[11]" SITE "F15"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[12]" SITE "J16"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[13]" SITE "C18"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[14]" SITE "H16"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" TERMINATION=OFF; +LOCATE COMP "OrangeCrab_DDRAM_DQ[15]" SITE "F18"; +IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" IO_TYPE=SSTL135_I; +IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" TERMINATION=OFF; + +LOCATE COMP "OrangeCrab_DDRAM_DQS_P[0]" SITE "B15"; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" IO_TYPE=SSTL135D_I; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" TERMINATION=OFF; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" DIFFRESISTOR=100; +LOCATE COMP "OrangeCrab_DDRAM_DQS_P[1]" SITE "G18"; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" IO_TYPE=SSTL135D_I; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" TERMINATION=OFF; +IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" DIFFRESISTOR=100; + +LOCATE COMP "OrangeCrab_DDRAM_CLK_P" SITE "J18"; +IOBUF PORT "OrangeCrab_DDRAM_CLK_P" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_CLK_P" IO_TYPE=SSTL135D_I; + +LOCATE COMP "OrangeCrab_DDRAM_CKE" SITE "D18"; +IOBUF PORT "OrangeCrab_DDRAM_CKE" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_CKE" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_ODT" SITE "C13"; +IOBUF PORT "OrangeCrab_DDRAM_ODT" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_ODT" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_RESET_N" SITE "L18"; +IOBUF PORT "OrangeCrab_DDRAM_RESET_N" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_RESET_N" IO_TYPE=SSTL135_I; + +LOCATE COMP "OrangeCrab_DDRAM_VCCIO[0]" SITE "K16"; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[0]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "OrangeCrab_DDRAM_VCCIO[1]" SITE "D17"; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[1]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "OrangeCrab_DDRAM_VCCIO[2]" SITE "K15"; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[2]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[2]" IO_TYPE=SSTL135_II; +LOCATE COMP "OrangeCrab_DDRAM_VCCIO[3]" SITE "K17"; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[3]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[3]" IO_TYPE=SSTL135_II; +LOCATE COMP "OrangeCrab_DDRAM_VCCIO[4]" SITE "B18"; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[4]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[4]" IO_TYPE=SSTL135_II; +LOCATE COMP "OrangeCrab_DDRAM_VCCIO[5]" SITE "C6"; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[5]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_VCCIO[5]" IO_TYPE=SSTL135_II; + +LOCATE COMP "OrangeCrab_DDRAM_GND[0]" SITE "L15"; +IOBUF PORT "OrangeCrab_DDRAM_GND[0]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_GND[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "OrangeCrab_DDRAM_GND[1]" SITE "L16"; +IOBUF PORT "OrangeCrab_DDRAM_GND[1]" SLEWRATE=FAST; +IOBUF PORT "OrangeCrab_DDRAM_GND[1]" IO_TYPE=SSTL135_II; + +LOCATE COMP "OrangeCrab_SPIFLASH_CS_N" SITE "U17"; +IOBUF PORT "OrangeCrab_SPIFLASH_CS_N" IO_TYPE=LVCMOS33; + +LOCATE COMP "OrangeCrab_SPIFLASH_DQ[0]" SITE "U18"; +IOBUF PORT "OrangeCrab_SPIFLASH_DQ[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "OrangeCrab_SPIFLASH_DQ[1]" SITE "T18"; +IOBUF PORT "OrangeCrab_SPIFLASH_DQ[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "OrangeCrab_SPIFLASH_DQ[2]" SITE "R18"; +IOBUF PORT "OrangeCrab_SPIFLASH_DQ[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "OrangeCrab_SPIFLASH_DQ[3]" SITE "N18"; +IOBUF PORT "OrangeCrab_SPIFLASH_DQ[3]" IO_TYPE=LVCMOS33; diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/ULX3S.lpf b/Libs/RiscV/NEORV32/setups/osflow/constraints/ULX3S.lpf new file mode 100644 index 0000000..df65329 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/ULX3S.lpf @@ -0,0 +1,598 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v2.x.x and v3.0.x + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "ULX3S_CLK" SITE "G2"; +IOBUF PORT "ULX3S_CLK" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "ULX3S_CLK" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +# write to FLASH possible any time from JTAG: +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE; +# write to FLASH possible from user bitstream: +# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ULX3S_TX" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ULX3S_RX" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ULX3S_TX" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_RX" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "ULX3S_LED7" SITE "H3"; +LOCATE COMP "ULX3S_LED6" SITE "E1"; +LOCATE COMP "ULX3S_LED5" SITE "E2"; +LOCATE COMP "ULX3S_LED4" SITE "D1"; +LOCATE COMP "ULX3S_LED3" SITE "D2"; +LOCATE COMP "ULX3S_LED2" SITE "C1"; +LOCATE COMP "ULX3S_LED1" SITE "C2"; +LOCATE COMP "ULX3S_LED0" SITE "B2"; +IOBUF PORT "ULX3S_LED0" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_LED1" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_LED2" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_LED3" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_LED4" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_LED5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_LED6" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ULX3S_LED7" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "ULX3S_RST_N" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +IOBUF PORT "ULX3S_RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +# wifi_gpio2,4,12,13,14,15 are shared with SD card. +# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[]. +# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free, +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_d1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_d2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_d3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping without 3.3V efuse +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +# input lines shared with GP,GN14-17 +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# output impedance: 75 ohm +# Stereo 16 ohm earphones, analog audio, +# SPDIF digital audio and composite video. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# wifi_gpio2,4,12,13,14,15 are shared with SD card. +# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[]. +# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free, +# other pins are shared with GP/GN, and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +# wifi lines shared with SD card +LOCATE COMP "wifi_gpio2" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2 +LOCATE COMP "wifi_gpio4" SITE "H1"; # sd_d1_irq WiFi GPIO4 +LOCATE COMP "wifi_gpio12" SITE "K1"; # sd_d2 WiFi_GPIO12 +LOCATE COMP "wifi_gpio13" SITE "K2"; # sd_d3_csn WiFi_GPIO13 +LOCATE COMP "wifi_gpio14" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "wifi_gpio15" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +# wifi lines shared with JTAG +# LOCATE COMP "wifi_gpio21" SITE "U5"; # JTAG TMS +# LOCATE COMP "wifi_gpio18" SITE "T5"; # JTAG TCK +# LOCATE COMP "wifi_gpio23" SITE "R5"; # JTAG TDI +# LOCATE COMP "wifi_gpio19" SITE "V4"; # JTAG TDO +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio5" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "ULX3S_USB_D_P" SITE "E16"; # single ended or differential input only +LOCATE COMP "ULX3S_USB_D_N" SITE "F16"; +IOBUF PORT "ULX3S_USB_D_P" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16; +IOBUF PORT "ULX3S_USB_D_N" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "ULX3S_USB_DP_PU" SITE "B12"; # pull up/down control +LOCATE COMP "ULX3S_USB_DN_PU" SITE "C12"; +IOBUF PORT "ULX3S_USB_DP_PU" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "ULX3S_USB_DN_PU" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +LOCATE COMP "gpdi_util" SITE "A19"; # add 10k parallel to C +LOCATE COMP "gpdi_hpd" SITE "B20"; # add 549ohm parallel to C +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_util" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_hpd" IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +# FEMALE ANGLED (90 deg PMOD) on TOP or +# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable +LOCATE COMP "gp[0]" SITE "B11"; # PCLK +LOCATE COMP "gn[0]" SITE "C11"; # PCLK +LOCATE COMP "gp[1]" SITE "A10"; # PCLK +LOCATE COMP "gn[1]" SITE "A11"; # PCLK +LOCATE COMP "gp[2]" SITE "A9"; # GR_PCLK +LOCATE COMP "gn[2]" SITE "B10"; # GR_PCLK +LOCATE COMP "gp[3]" SITE "B9"; +LOCATE COMP "gn[3]" SITE "C10"; +LOCATE COMP "gp[4]" SITE "A7"; +LOCATE COMP "gn[4]" SITE "A8"; +LOCATE COMP "gp[5]" SITE "C8"; +LOCATE COMP "gn[5]" SITE "B8"; +LOCATE COMP "gp[6]" SITE "C6"; +LOCATE COMP "gn[6]" SITE "C7"; +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; +LOCATE COMP "gn[7]" SITE "B6"; +LOCATE COMP "gp[8]" SITE "A4"; # DIFF +LOCATE COMP "gn[8]" SITE "A5"; # DIFF +LOCATE COMP "gp[9]" SITE "A2"; # DIFF +LOCATE COMP "gn[9]" SITE "B1"; # DIFF +LOCATE COMP "gp[10]" SITE "C4"; # DIFF +LOCATE COMP "gn[10]" SITE "B4"; # DIFF +LOCATE COMP "gp[11]" SITE "F4"; # DIFF wifi_gpio26 +LOCATE COMP "gn[11]" SITE "E3"; # DIFF wifi_gpio25 +LOCATE COMP "gp[12]" SITE "G3"; # DIFF wifi_gpio33 PCLK +LOCATE COMP "gn[12]" SITE "F3"; # DIFF wifi_gpio32 PCLK +LOCATE COMP "gp[13]" SITE "H4"; # DIFF wifi_gpio35 +LOCATE COMP "gn[13]" SITE "G5"; # DIFF wifi_gpio34 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "gn[12]" 50 MHZ; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # DIFF ADC AIN1 +LOCATE COMP "gn[14]" SITE "U17"; # DIFF ADC AIN0 +LOCATE COMP "gp[15]" SITE "N17"; # DIFF ADC AIN3 +LOCATE COMP "gn[15]" SITE "P16"; # DIFF ADC AIN2 +LOCATE COMP "gp[16]" SITE "N16"; # DIFF ADC AIN5 +LOCATE COMP "gn[16]" SITE "M17"; # DIFF ADC AIN4 +LOCATE COMP "gp[17]" SITE "L16"; # DIFF ADC AIN7 GR_PCLK +LOCATE COMP "gn[17]" SITE "L17"; # DIFF ADC AIN6 +LOCATE COMP "gp[18]" SITE "H18"; # DIFF +LOCATE COMP "gn[18]" SITE "H17"; # DIFF +LOCATE COMP "gp[19]" SITE "F17"; # DIFF +LOCATE COMP "gn[19]" SITE "G18"; # DIFF +LOCATE COMP "gp[20]" SITE "D18"; # DIFF +LOCATE COMP "gn[20]" SITE "E17"; # DIFF +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # DIFF +LOCATE COMP "gn[21]" SITE "D17"; # DIFF +LOCATE COMP "gp[22]" SITE "B15"; +LOCATE COMP "gn[22]" SITE "C15"; +LOCATE COMP "gp[23]" SITE "B17"; +LOCATE COMP "gn[23]" SITE "C17"; +LOCATE COMP "gp[24]" SITE "C16"; +LOCATE COMP "gn[24]" SITE "D16"; +LOCATE COMP "gp[25]" SITE "D14"; +LOCATE COMP "gn[25]" SITE "E14"; +LOCATE COMP "gp[26]" SITE "B13"; +LOCATE COMP "gn[26]" SITE "C13"; +LOCATE COMP "gp[27]" SITE "D13"; +LOCATE COMP "gn[27]" SITE "E13"; +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## GPIO repeated as individual signals (non-vector) +# Allows mixed input, output, bidirectional, clock, differential +# If any of individual gp is used, then don't use gp[] vector. +# Same for gn and gn[]. +# FEMALE ANGLED (90 deg PMOD) on TOP or +# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable +LOCATE COMP "gp0" SITE "B11"; # PCLK +LOCATE COMP "gn0" SITE "C11"; # PCLK +LOCATE COMP "gp1" SITE "A10"; # PCLK +LOCATE COMP "gn1" SITE "A11"; # PCLK +LOCATE COMP "gp2" SITE "A9"; # GR_PCLK +LOCATE COMP "gn2" SITE "B10"; # GR_PCLK +LOCATE COMP "gp3" SITE "B9"; +LOCATE COMP "gn3" SITE "C10"; +LOCATE COMP "gp4" SITE "A7"; +LOCATE COMP "gn4" SITE "A8"; +LOCATE COMP "gp5" SITE "C8"; +LOCATE COMP "gn5" SITE "B8"; +LOCATE COMP "gp6" SITE "C6"; +LOCATE COMP "gn6" SITE "C7"; +IOBUF PORT "gp0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp7" SITE "A6"; +LOCATE COMP "gn7" SITE "B6"; +LOCATE COMP "gp8" SITE "A4"; # DIFF +LOCATE COMP "gn8" SITE "A5"; # DIFF +LOCATE COMP "gp9" SITE "A2"; # DIFF +LOCATE COMP "gn9" SITE "B1"; # DIFF +LOCATE COMP "gp10" SITE "C4"; # DIFF +LOCATE COMP "gn10" SITE "B4"; # DIFF +LOCATE COMP "gp11" SITE "F4"; # DIFF wifi_gpio26 +LOCATE COMP "gn11" SITE "E3"; # DIFF wifi_gpio25 +LOCATE COMP "gp12" SITE "G3"; # DIFF wifi_gpio33 PCLK +LOCATE COMP "gn12" SITE "F3"; # DIFF wifi_gpio32 PCLK +LOCATE COMP "gp13" SITE "H4"; # DIFF wifi_gpio35 +LOCATE COMP "gn13" SITE "G5"; # DIFF wifi_gpio34 +# wifi sharing PCB v2.0.6-v3.0.8 +# prior to v2.0.6 see schematics +IOBUF PORT "gp7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +FREQUENCY PORT "gn12" 50 MHZ; +IOBUF PORT "gp13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp14" SITE "U18"; # DIFF ADC AIN1 +LOCATE COMP "gn14" SITE "U17"; # DIFF ADC AIN0 +LOCATE COMP "gp15" SITE "N17"; # DIFF ADC AIN3 +LOCATE COMP "gn15" SITE "P16"; # DIFF ADC AIN2 +LOCATE COMP "gp16" SITE "N16"; # DIFF ADC AIN5 +LOCATE COMP "gn16" SITE "M17"; # DIFF ADC AIN4 +LOCATE COMP "gp17" SITE "L16"; # DIFF ADC AIN7 GR_PCLK +LOCATE COMP "gn17" SITE "L17"; # DIFF ADC AIN6 +LOCATE COMP "gp18" SITE "H18"; # DIFF +LOCATE COMP "gn18" SITE "H17"; # DIFF +LOCATE COMP "gp19" SITE "F17"; # DIFF +LOCATE COMP "gn19" SITE "G18"; # DIFF +LOCATE COMP "gp20" SITE "D18"; # DIFF +LOCATE COMP "gn20" SITE "E17"; # DIFF +IOBUF PORT "gp14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp21" SITE "C18"; # DIFF +LOCATE COMP "gn21" SITE "D17"; # DIFF +LOCATE COMP "gp22" SITE "B15"; +LOCATE COMP "gn22" SITE "C15"; +LOCATE COMP "gp23" SITE "B17"; +LOCATE COMP "gn23" SITE "C17"; +LOCATE COMP "gp24" SITE "C16"; +LOCATE COMP "gn24" SITE "D16"; +LOCATE COMP "gp25" SITE "D14"; +LOCATE COMP "gn25" SITE "E14"; +LOCATE COMP "gp26" SITE "B13"; +LOCATE COMP "gn26" SITE "C13"; +LOCATE COMP "gp27" SITE "D13"; +LOCATE COMP "gn27" SITE "E13"; +IOBUF PORT "gp21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/UPduino_v3.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/UPduino_v3.pcf new file mode 100644 index 0000000..ba815e9 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/UPduino_v3.pcf @@ -0,0 +1,36 @@ +## UART (uart0) +set_io uart_txd_o 38 +set_io uart_rxd_i 28 + +## SPI - on-board flash +set_io flash_sdo_o 14 +set_io flash_sck_o 15 +set_io flash_csn_o 16 +set_io flash_sdi_i 17 + +## SPI - user port +set_io spi_sdo_o 34 +set_io spi_sck_o 43 +set_io spi_csn_o 36 +set_io spi_sdi_i 42 + +## TWI +set_io twi_sda_io 31 +set_io twi_scl_io 37 + +## GPIO - input +set_io gpio_i[0] 44 +set_io gpio_i[1] 4 +set_io gpio_i[2] 3 +set_io gpio_i[3] 48 + +## GPIO - output +set_io gpio_o[0] 45 +set_io gpio_o[1] 47 +set_io gpio_o[2] 46 +set_io gpio_o[3] 2 + +## RGB power LED +set_io pwm_o[0] 39 +set_io pwm_o[1] 40 +set_io pwm_o[2] 41 diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/iCEBreaker.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/iCEBreaker.pcf new file mode 100644 index 0000000..88ee9f1 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/iCEBreaker.pcf @@ -0,0 +1,39 @@ +## UART (uart0) +set_io uart_txd_o 9 +set_io uart_rxd_i 6 + +## SPI - on-board flash +set_io flash_sdo_o 14 +set_io flash_sck_o 15 +set_io flash_csn_o 16 +set_io flash_sdi_i 17 + +## SPI - user port +set_io spi_sdo_o 43 +set_io spi_sck_o 38 +set_io spi_csn_o 34 +set_io spi_sdi_i 31 + +## TWI +set_io twi_sda_io 2 +set_io twi_scl_io 4 + +## GPIO - input +set_io gpio_i[0] 18 +set_io gpio_i[1] 19 +set_io gpio_i[2] 20 +set_io gpio_i[3] 28 + +## GPIO - output +set_io gpio_o[0] 25 +set_io gpio_o[1] 26 +set_io gpio_o[2] 27 +set_io gpio_o[3] 23 + +## RGB power LED +set_io pwm_o[0] 39 +set_io pwm_o[1] 40 +set_io pwm_o[2] 41 + +#User Reset Btn +set_io user_reset_btn 10 diff --git a/Libs/RiscV/NEORV32/setups/osflow/constraints/iCESugar.pcf b/Libs/RiscV/NEORV32/setups/osflow/constraints/iCESugar.pcf new file mode 100644 index 0000000..ad56458 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/constraints/iCESugar.pcf @@ -0,0 +1,69 @@ +#| iCESugar-v1.5 + + +#> Clock (12 MHz) +set_io --warn-no-port iCESugarv15_CLK 35 + + +#> Tri-colour LED +set_io --warn-no-port iCESugarv15_LED_G 41 +set_io --warn-no-port iCESugarv15_LED_R 40 +set_io --warn-no-port iCESugarv15_LED_B 39 + + +#> UART +set_io --warn-no-port iCESugarv15_RX 4 +set_io --warn-no-port iCESugarv15_TX 6 + + +#> USB +set_io --warn-no-port iCESugarv15_USB_DN 9 +set_io --warn-no-port iCESugarv15_USB_DP 10 +set_io --warn-no-port iCESugarv15_USB_DP_PU 11 + + +#> PMOD 1 +set_io --warn-no-port iCESugarv15_PMOD1A_0 10 +set_io --warn-no-port iCESugarv15_PMOD1A_1 6 +set_io --warn-no-port iCESugarv15_PMOD1A_2 3 +set_io --warn-no-port iCESugarv15_PMOD1A_3 48 +set_io --warn-no-port iCESugarv15_PMOD1B_0 47 +set_io --warn-no-port iCESugarv15_PMOD1B_1 2 +set_io --warn-no-port iCESugarv15_PMOD1B_2 4 +set_io --warn-no-port iCESugarv15_PMOD1B_3 9 + + +#> PMOD 2 +set_io --warn-no-port iCESugarv15_PMOD2A_0 46 +set_io --warn-no-port iCESugarv15_PMOD2A_1 44 +set_io --warn-no-port iCESugarv15_PMOD2A_2 42 +set_io --warn-no-port iCESugarv15_PMOD2A_3 37 +set_io --warn-no-port iCESugarv15_PMOD2B_0 36 +set_io --warn-no-port iCESugarv15_PMOD2B_1 38 +set_io --warn-no-port iCESugarv15_PMOD2B_2 43 +set_io --warn-no-port iCESugarv15_PMOD2B_3 45 + + +#> PMOD 3 +set_io --warn-no-port iCESugarv15_PMOD3A_0 34 +set_io --warn-no-port iCESugarv15_PMOD3A_1 31 +set_io --warn-no-port iCESugarv15_PMOD3A_2 27 +set_io --warn-no-port iCESugarv15_PMOD3A_3 25 +set_io --warn-no-port iCESugarv15_PMOD3B_0 23 +set_io --warn-no-port iCESugarv15_PMOD3B_1 26 +set_io --warn-no-port iCESugarv15_PMOD3B_2 28 +set_io --warn-no-port iCESugarv15_PMOD3B_3 32 + + +#> PMOD 4 | Switches +set_io --warn-no-port iCESugarv15_PMOD4_0 21 +set_io --warn-no-port iCESugarv15_PMOD4_1 20 +set_io --warn-no-port iCESugarv15_PMOD4_2 19 +set_io --warn-no-port iCESugarv15_PMOD4_3 18 + + +#> SPI +set_io --warn-no-port iCESugarv15_SPI_SS 16 +set_io --warn-no-port iCESugarv15_SPI_SCK 15 +set_io --warn-no-port iCESugarv15_SPI_MOSI 17 +set_io --warn-no-port iCESugarv15_SPI_MISO 14 diff --git a/Libs/RiscV/NEORV32/setups/osflow/devices/ecp5/ecp5_components.vhd b/Libs/RiscV/NEORV32/setups/osflow/devices/ecp5/ecp5_components.vhd new file mode 100644 index 0000000..9385a3d --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/devices/ecp5/ecp5_components.vhd @@ -0,0 +1,75 @@ +library ieee ; +use ieee.std_logic_1164.all; + +package components is + + -- Yosys wrapper components + + component EHXPLLL + generic + ( + CLKI_DIV : integer := 1; + CLKFB_DIV : integer := 1; + CLKOP_DIV : integer := 8; + CLKOS_DIV : integer := 8; + CLKOS2_DIV : integer := 8; + CLKOS3_DIV : integer := 8; + CLKOP_ENABLE : string := "ENABLED"; + CLKOS_ENABLE : string := "DISABLED"; + CLKOS2_ENABLE : string := "DISABLED"; + CLKOS3_ENABLE : string := "DISABLED"; + CLKOP_CPHASE : integer := 0; + CLKOS_CPHASE : integer := 0; + CLKOS2_CPHASE : integer := 0; + CLKOS3_CPHASE : integer := 0; + CLKOP_FPHASE : integer := 0; + CLKOS_FPHASE : integer := 0; + CLKOS2_FPHASE : integer := 0; + CLKOS3_FPHASE : integer := 0; + FEEDBK_PATH : string := "CLKOP"; + CLKOP_TRIM_POL : string := "RISING"; + CLKOP_TRIM_DELAY : integer := 0; + CLKOS_TRIM_POL : string := "RISING"; + CLKOS_TRIM_DELAY : integer := 0; + OUTDIVIDER_MUXA : string := "DIVA"; + OUTDIVIDER_MUXB : string := "DIVB"; + OUTDIVIDER_MUXC : string := "DIVC"; + OUTDIVIDER_MUXD : string := "DIVD"; + PLL_LOCK_MODE : integer := 0; + PLL_LOCK_DELAY : integer := 200; + STDBY_ENABLE : string := "DISABLED"; + REFIN_RESET : string := "DISABLED"; + SYNC_ENABLE : string := "DISABLED"; + INT_LOCK_STICKY : string := "ENABLED"; + DPHASE_SOURCE : string := "DISABLED"; + PLLRST_ENA : string := "DISABLED"; + INTFB_WAKE : string := "DISABLED" + ); + port + ( + CLKI : IN std_logic := 'X'; + CLKFB : IN std_logic := 'X'; + RST : IN std_logic := 'X'; + STDBY : IN std_logic := 'X'; + PLLWAKESYNC : IN std_logic := 'X'; + PHASESEL1 : IN std_logic := 'X'; + PHASESEL0 : IN std_logic := 'X'; + PHASEDIR : IN std_logic := 'X'; + PHASESTEP : IN std_logic := 'X'; + PHASELOADREG : IN std_logic := 'X'; + ENCLKOP : IN std_logic := 'X'; + ENCLKOS : IN std_logic := 'X'; + ENCLKOS2 : IN std_logic := 'X'; + ENCLKOS3 : IN std_logic := 'X'; + CLKOP : OUT std_logic := 'X'; + CLKOS : OUT std_logic := 'X'; + CLKOS2 : OUT std_logic := 'X'; + CLKOS3 : OUT std_logic := 'X'; + LOCK : OUT std_logic := 'X'; + INTLOCK : OUT std_logic := 'X'; + REFCLK : OUT std_logic := 'X'; + CLKINTFB : OUT std_logic := 'X' + ); + end component; + +end package; diff --git a/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd b/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd new file mode 100644 index 0000000..3cd4a5d --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_dmem.ice40up_spram.vhd @@ -0,0 +1,145 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> # +-- # ********************************************************************************************* # +-- # Memory has a physical size of 64kb (2 x SPRAMs). # +-- # Logical size DMEM_SIZE must be less or equal. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +library iCE40; +use iCE40.components.all; + +architecture neorv32_dmem_rtl of neorv32_dmem is + + -- advanced configuration -------------------------------------------------------------------------------- + constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power) + -- ------------------------------------------------------------------------------------------------------- + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal mem_cs : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + + -- SPRAM signals -- + signal spram_clk : std_logic; + signal spram_addr : std_logic_vector(13 downto 0); + signal spram_di_lo : std_logic_vector(15 downto 0); + signal spram_di_hi : std_logic_vector(15 downto 0); + signal spram_do_lo : std_logic_vector(15 downto 0); + signal spram_do_hi : std_logic_vector(15 downto 0); + signal spram_be_lo : std_logic_vector(03 downto 0); + signal spram_be_hi : std_logic_vector(03 downto 0); + signal spram_we : std_logic; + signal spram_pwr_n : std_logic; + signal spram_cs : std_logic; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based DMEM." severity note; + assert not (DMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: DMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + mem_cs <= acc_en and (rden_i or wren_i); + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_spram_lo_inst : SB_SPRAM256KA + port map ( + ADDRESS => spram_addr, -- I + DATAIN => spram_di_lo, -- I + MASKWREN => spram_be_lo, -- I + WREN => spram_we, -- I + CHIPSELECT => spram_cs, -- I + CLOCK => spram_clk, -- I + STANDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + POWEROFF => '1', -- I + DATAOUT => spram_do_lo -- O + ); + + imem_spram_hi_inst : SB_SPRAM256KA + port map ( + ADDRESS => spram_addr, -- I + DATAIN => spram_di_hi, -- I + MASKWREN => spram_be_hi, -- I + WREN => spram_we, -- I + CHIPSELECT => spram_cs, -- I + CLOCK => spram_clk, -- I + STANDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + POWEROFF => '1', -- I + DATAOUT => spram_do_hi -- O + ); + + -- access logic and signal type conversion -- + spram_clk <= std_logic(clk_i); + spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2)); + spram_di_lo <= std_logic_vector(data_i(15 downto 00)); + spram_di_hi <= std_logic_vector(data_i(31 downto 16)); + spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable + spram_cs <= std_logic(mem_cs); + spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable + spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable + spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected + rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo); + + buffer_ff: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= mem_cs; + rden <= acc_en and rden_i; + end if; + end process buffer_ff; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_dmem_rtl; diff --git a/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd b/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd new file mode 100644 index 0000000..9272291 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd @@ -0,0 +1,146 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> # +-- # ********************************************************************************************* # +-- # Memory has a physical size of 64kb (2 x SPRAMs). # +-- # Logical size IMEM_SIZE must be less or equal. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +library iCE40; +use iCE40.components.all; + +architecture neorv32_imem_rtl of neorv32_imem is + + -- advanced configuration -------------------------------------------------------------------------------- + constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power) + -- ------------------------------------------------------------------------------------------------------- + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal mem_cs : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + + -- SPRAM signals -- + signal spram_clk : std_logic; + signal spram_addr : std_logic_vector(13 downto 0); + signal spram_di_lo : std_logic_vector(15 downto 0); + signal spram_di_hi : std_logic_vector(15 downto 0); + signal spram_do_lo : std_logic_vector(15 downto 0); + signal spram_do_hi : std_logic_vector(15 downto 0); + signal spram_be_lo : std_logic_vector(03 downto 0); + signal spram_be_hi : std_logic_vector(03 downto 0); + signal spram_we : std_logic; + signal spram_pwr_n : std_logic; + signal spram_cs : std_logic; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note; + assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure; + assert not (IMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: IMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + mem_cs <= acc_en and (rden_i or wren_i); + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_spram_lo_inst : SB_SPRAM256KA + port map ( + ADDRESS => spram_addr, -- I + DATAIN => spram_di_lo, -- I + MASKWREN => spram_be_lo, -- I + WREN => spram_we, -- I + CHIPSELECT => spram_cs, -- I + CLOCK => spram_clk, -- I + STANDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + POWEROFF => '1', -- I + DATAOUT => spram_do_lo -- O + ); + + imem_spram_hi_inst : SB_SPRAM256KA + port map ( + ADDRESS => spram_addr, -- I + DATAIN => spram_di_hi, -- I + MASKWREN => spram_be_hi, -- I + WREN => spram_we, -- I + CHIPSELECT => spram_cs, -- I + CLOCK => spram_clk, -- I + STANDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + POWEROFF => '1', -- I + DATAOUT => spram_do_hi -- O + ); + + -- access logic and signal type conversion -- + spram_clk <= std_logic(clk_i); + spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2)); + spram_di_lo <= std_logic_vector(data_i(15 downto 00)); + spram_di_hi <= std_logic_vector(data_i(31 downto 16)); + spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable + spram_cs <= std_logic(mem_cs); + spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable + spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable + spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected + rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo); + + buffer_ff: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= mem_cs; + rden <= acc_en and rden_i; + end if; + end process buffer_ff; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_imem_rtl; diff --git a/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/sb_ice40_components.vhd b/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/sb_ice40_components.vhd new file mode 100644 index 0000000..9db1924 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/devices/ice40/sb_ice40_components.vhd @@ -0,0 +1,126 @@ +library ieee ; +use ieee.std_logic_1164.all; + +package components is + + -- Yosys / IceCube wrapper components + + component SB_GB + port( + GLOBAL_BUFFER_OUTPUT : out std_logic; + USER_SIGNAL_TO_GLOBAL_BUFFER : in std_logic + ); + end component; + + component SB_HFOSC + generic ( + CLKHF_DIV : string + ); + port ( + CLKHFPU : in std_logic; + CLKHFEN : in std_logic; + CLKHF : out std_logic + ); + end component; + + component SB_PLL40_CORE is + generic ( + FEEDBACK_PATH : string := "SIMPLE"; + DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED"; + DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED"; + SHIFTREG_DIV_MODE : std_logic := '0'; + FDA_FEEDBACK : std_logic_vector(3 downto 0) := x"0"; + FDA_RELATIVE : std_logic_vector(3 downto 0) := x"0"; + PLLOUT_SELECT : string := "GENCLK"; + DIVR : std_logic_vector(3 downto 0) := x"0"; + DIVF : std_logic_vector(6 downto 0) := "0000000"; + DIVQ : std_logic_vector(2 downto 0) := "000"; + FILTER_RANGE : std_logic_vector(2 downto 0) := "000"; + ENABLE_ICEGATE : bit := '0'; + TEST_MODE : bit := '0'; + EXTERNAL_DIVIDE_FACTOR : integer := 1 + ); + port ( + REFERENCECLK : in std_logic; + PLLOUTCORE : out std_logic; + PLLOUTGLOBAL : out std_logic; + EXTFEEDBACK : in std_logic; + DYNAMICDELAY : in std_logic_vector(7 downto 0); + LOCK : out std_logic; + BYPASS : in std_logic; + RESETB : in std_logic; + LATCHINPUTVALUE : in std_logic; + SDO : out std_logic; + SDI : in std_logic; + SCLK : in std_logic + ); + end component; + + component SB_PLL40_PAD + generic ( + FEEDBACK_PATH : string := "SIMPLE"; + DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED"; + DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED"; + SHIFTREG_DIV_MODE : bit_vector(1 downto 0) := "00"; + FDA_FEEDBACK : bit_vector(3 downto 0) := "0000"; + FDA_RELATIVE : bit_vector(3 downto 0) := "0000"; + PLLOUT_SELECT : string := "GENCLK"; + DIVR : bit_vector(3 downto 0) := x"0"; + DIVF : bit_vector(6 downto 0) := "0000000"; + DIVQ : bit_vector(2 downto 0) := "000"; + FILTER_RANGE : bit_vector(2 downto 0) := "000"; + ENABLE_ICEGATE : bit := '0'; + TEST_MODE : bit := '0'; + EXTERNAL_DIVIDE_FACTOR : integer := 1 + ); + port ( + PACKAGEPIN : in std_logic; + PLLOUTCORE : out std_logic; + PLLOUTGLOBAL : out std_logic; + EXTFEEDBACK : in std_logic; + DYNAMICDELAY : in std_logic_vector(7 downto 0); + LOCK : out std_logic; + BYPASS : in std_logic; + RESETB : in std_logic; + LATCHINPUTVALUE : in std_logic; + SDO : out std_logic; + SDI : in std_logic; + SCLK : in std_logic + ); + end component; + + component SB_RGBA_DRV + generic ( + CURRENT_MODE : string := "0b0"; + RGB0_CURRENT : string := "0b000000"; + RGB1_CURRENT : string := "0b000000"; + RGB2_CURRENT : string := "0b000000" + ); + port ( + RGB0PWM : in std_logic; + RGB1PWM : in std_logic; + RGB2PWM : in std_logic; + CURREN : in std_logic; + RGBLEDEN : in std_logic; + RGB0 : out std_logic; + RGB1 : out std_logic; + RGB2 : out std_logic + ); + end component; + + component SB_SPRAM256KA + port ( + ADDRESS : in std_logic_vector(13 downto 0); + DATAIN : in std_logic_vector(15 downto 0); + MASKWREN : in std_logic_vector(3 downto 0); + WREN : in std_logic; + CHIPSELECT : in std_logic; + CLOCK : in std_logic; + STANDBY : in std_logic; + SLEEP : in std_logic; + POWEROFF : in std_logic; + DATAOUT : out std_logic_vector(15 downto 0) + ); + end component; + +end package; diff --git a/Libs/RiscV/NEORV32/setups/osflow/filesets.mk b/Libs/RiscV/NEORV32/setups/osflow/filesets.mk new file mode 100644 index 0000000..db44aac --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/filesets.mk @@ -0,0 +1,66 @@ +RTL_CORE_SRC := ../../rtl/core + +NEORV32_PKG := $(RTL_CORE_SRC)/neorv32_package.vhd + +NEORV32_APP_SRC := \ + $(RTL_CORE_SRC)/neorv32_application_image.vhd \ + +NEORV32_MEM_ENTITIES := \ + $(RTL_CORE_SRC)/neorv32_dmem.entity.vhd \ + $(RTL_CORE_SRC)/neorv32_imem.entity.vhd + +NEORV32_CORE_SRC := \ + $(RTL_CORE_SRC)/neorv32_bootloader_image.vhd \ + $(RTL_CORE_SRC)/neorv32_boot_rom.vhd \ + $(RTL_CORE_SRC)/neorv32_bus_keeper.vhd \ + $(RTL_CORE_SRC)/neorv32_busswitch.vhd \ + $(RTL_CORE_SRC)/neorv32_cfs.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_alu.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_bus.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_control.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_cp_bitmanip.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_cp_fpu.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_cp_muldiv.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_cp_shifter.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_decompressor.vhd \ + $(RTL_CORE_SRC)/neorv32_cpu_regfile.vhd \ + $(RTL_CORE_SRC)/neorv32_debug_dm.vhd \ + $(RTL_CORE_SRC)/neorv32_debug_dtm.vhd \ + $(RTL_CORE_SRC)/neorv32_fifo.vhd \ + $(RTL_CORE_SRC)/neorv32_gpio.vhd \ + $(RTL_CORE_SRC)/neorv32_gptmr.vhd \ + $(RTL_CORE_SRC)/neorv32_icache.vhd \ + $(RTL_CORE_SRC)/neorv32_mtime.vhd \ + $(RTL_CORE_SRC)/neorv32_neoled.vhd \ + $(RTL_CORE_SRC)/neorv32_pwm.vhd \ + $(RTL_CORE_SRC)/neorv32_slink.vhd \ + $(RTL_CORE_SRC)/neorv32_spi.vhd \ + $(RTL_CORE_SRC)/neorv32_sysinfo.vhd \ + $(RTL_CORE_SRC)/neorv32_top.vhd \ + $(RTL_CORE_SRC)/neorv32_trng.vhd \ + $(RTL_CORE_SRC)/neorv32_twi.vhd \ + $(RTL_CORE_SRC)/neorv32_uart.vhd \ + $(RTL_CORE_SRC)/neorv32_wdt.vhd \ + $(RTL_CORE_SRC)/neorv32_wishbone.vhd \ + $(RTL_CORE_SRC)/neorv32_xirq.vhd + +# Before including this partial makefile, NEORV32_MEM_SRC needs to be set +# (containing two VHDL sources: one for IMEM and one for DMEM) + +NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} ${NEORV32_MEM_SRC} ${NEORV32_MEM_SRC_EXTRA} ${NEORV32_CORE_SRC} ${NEORV32_CORE_SRC_EXTRA} +NEORV32_VERILOG_ALL := ${NEORV32_VERILOG_SRC} ${NEORV32_VERILOG_SRC_EXTRA} + +ICE40_SRC := \ + devices/ice40/sb_ice40_components.vhd + +ECP5_SRC := \ + devices/ecp5/ecp5_components.vhd + +ifeq ($(DEVICE_SERIES),ecp5) +DEVICE_SRC := ${ECP5_SRC} +else +DEVICE_SRC := ${ICE40_SRC} +endif + +# Optionally NEORV32_VERILOG_SRC can be set to a list of Verilog sources diff --git a/Libs/RiscV/NEORV32/setups/osflow/synthesis.mk b/Libs/RiscV/NEORV32/setups/osflow/synthesis.mk new file mode 100644 index 0000000..7adc9c0 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/synthesis.mk @@ -0,0 +1,16 @@ +${DEVICE_LIB}-obj08.cf: ${DEVICE_SRC} + ghdl -a $(GHDL_FLAGS) --work=${DEVICE_LIB} ${DEVICE_SRC} + +neorv32-obj08.cf: ${DEVICE_LIB}-obj08.cf ${NEORV32_SRC} + ghdl -a $(GHDL_FLAGS) --work=neorv32 ${NEORV32_SRC} + +work-obj08.cf: neorv32-obj08.cf ${DESIGN_SRC} ${BOARD_SRC} + ghdl -a $(GHDL_FLAGS) --work=work ${DESIGN_SRC} ${BOARD_SRC} + +${IMPL}.json: work-obj08.cf $(NEORV32_VERILOG_ALL) + $(YOSYS) $(YOSYSFLAGS) \ + -p \ + "$(GHDLSYNTH) $(GHDL_FLAGS) --no-formal $(TOP); \ + synth_${YOSYSSYNTH} \ + -top $(TOP) $(YOSYSPIPE) \ + -json $@" $(NEORV32_VERILOG_ALL) 2>&1 | tee yosys-report.txt diff --git a/Libs/RiscV/NEORV32/setups/osflow/tools.mk b/Libs/RiscV/NEORV32/setups/osflow/tools.mk new file mode 100644 index 0000000..32c6cc1 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/osflow/tools.mk @@ -0,0 +1,28 @@ +GHDL_FLAGS += --std=08 +GHDL ?= ghdl +GHDLSYNTH ?= ghdl +YOSYS ?= yosys +ICEPACK ?= icepack +ECPPACK ?= ecppack +OPENOCD ?= openocd +COPY ?= cp -a + +DEVICE_SERIES ?= ice40 +DEVICE_LIB ?= $(DEVICE_SERIES) +YOSYSSYNTH ?= $(DEVICE_SERIES) +NEXTPNR ?= nextpnr-$(DEVICE_SERIES) + +ifeq ($(DEVICE_SERIES),ice40) +YOSYSPIPE ?= -dsp +CONSTRAINTS_FORMAT ?= pcf +NEXTPNR_OUT ?= asc +PNR2BIT_EXT ?= asc +PACKTOOL ?= $(ICEPACK) +PACKARGS ?= +else +CONSTRAINTS_FORMAT ?= lpf +NEXTPNR_OUT ?= textcfg +PNR2BIT_EXT ?= cfg +PACKTOOL ?= $(ECPPACK) +PACKARGS ?= --compress +endif diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore new file mode 100644 index 0000000..0acbb70 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore @@ -0,0 +1,5 @@ +db +incremental_db +output_files +greybox_tmp +*.qws diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/README.md b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/README.md new file mode 100644 index 0000000..036819b --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/README.md @@ -0,0 +1,60 @@ +# NEORV32 Test Setup using the NEORV32 with AvalonMM Master Interface wrapper + +This setup provides a very simple "demo setup" that uses the NEORV32 with a AvalonMM +Interface wrapper. This makes if possible to connect you own modules using a simple +version of the AvalonMM Master interface. + +Note that the AvalonMM Master is a very simple version providing only basic features: + +* Single read and write access +* Flow control (variable wait-states) +* 8/16/32 bit data access +* Aligned and unaligned access supported + +The AvalonMM Master does **not** support: +* Burst access +* Pipeline transfer +* Pending reads + +The design is based on the de0-nano-test-setup, but added a AvalonMM Master wrapper. +The wrapper file can be found here [`AvalonMM wrapper`](../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd). + +As a test an "external" DMEM is conneced to the NEORV32 over the AvalonMM Master Interface. + +It uses the simplified and simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). + +* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) +* FPGA: Intel Cyclone-IV `EP4CE22F17C6N` +* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition) + + +### NEORV32 Configuration + +For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used +with a few exceptions: + +* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader +* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +* Clock: 50MHz from on-board oscillator +* Reset: via on-board button "KEY0" +* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") +* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header + * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4") + * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6") + +### FPGA Utilization + +``` +Total logic elements 3,439 / 22,320 ( 15 % ) +Total registers 1674 +Total pins 12 / 154 ( 8 % ) +Total virtual pins 0 +Total memory bits 197,632 / 608,256 ( 32 % ) +Embedded Multiplier 9-bit elements 0 / 132 ( 0 % ) +Total PLLs 0 / 4 ( 0 % ) +``` + + +## How To Run + +Open the Quartus project file, compile and upload to FPGA. \ No newline at end of file diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qpf b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qpf new file mode 100644 index 0000000..bbef58c --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition +# Date created = 20:23:30 September 13, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "20:23:30 September 13, 2021" + +# Revisions + +PROJECT_REVISION = "de0-nano-test-setup" diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qsf b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qsf new file mode 100644 index 0000000..9300818 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/de0-nano-test-setup.qsf @@ -0,0 +1,108 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition +# Date created = 20:23:30 September 13, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de0-nano-test-setup_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_avalonmm +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_application_image.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bootloader_image.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_boot_rom.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_busswitch.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bus_keeper.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cfs.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_alu.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_bus.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_control.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_bitmanip.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_fpu.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_muldiv.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_shifter.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_decompressor.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_regfile.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dm.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dtm.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_fifo.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_gpio.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_icache.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_mtime.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_neoled.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_package.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_pwm.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_slink.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_spi.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_sysinfo.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_top.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_trng.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_twi.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_uart.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wdt.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wishbone.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_xirq.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32 +set_global_assignment -name VHDL_FILE neorv32_test_setup_avalonmm.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_R8 -to clk_i +set_location_assignment PIN_L3 -to gpio_o[7] +set_location_assignment PIN_B1 -to gpio_o[6] +set_location_assignment PIN_F3 -to gpio_o[5] +set_location_assignment PIN_D1 -to gpio_o[4] +set_location_assignment PIN_A11 -to gpio_o[3] +set_location_assignment PIN_B13 -to gpio_o[2] +set_location_assignment PIN_A13 -to gpio_o[1] +set_location_assignment PIN_A15 -to gpio_o[0] +set_location_assignment PIN_J15 -to rstn_i +set_location_assignment PIN_C3 -to uart0_txd_o +set_location_assignment PIN_A3 -to uart0_rxd_i +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip new file mode 100644 index 0000000..03189d4 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dmem_ram.vhd"] diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd new file mode 100644 index 0000000..83ca80b --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/dmem_ram.vhd @@ -0,0 +1,163 @@ +-- megafunction wizard: %RAM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: dmem_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.1 Build 646 04/11/2019 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 2019 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details, at +--https://fpgasoftware.intel.com/eula. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY dmem_ram IS + PORT + ( + address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END dmem_ram; + + +ARCHITECTURE SYN OF dmem_ram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + byte_size => 8, + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone IV E", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2048, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => 11, + width_a => 32, + width_byteena_a => 4 + ) + PORT MAP ( + address_a => address, + byteena_a => byteena, + clock0 => clock, + data_a => data, + wren_a => wren, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrData NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegData NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +-- Retrieval info: PRIVATE: WidthData NUMERIC "32" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" +-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +-- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +-- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd new file mode 100644 index 0000000..daa5b76 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/neorv32_test_setup_avalonmm.vhd @@ -0,0 +1,332 @@ +-- ################################################################################################# +-- # << NEORV32 - Test Setup using the AvalonMM Interface >> # +-- # ********************************************************************************************* # +-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" # +-- # are trademarks of Intel # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.ALL; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_test_setup_avalonmm is + generic ( + -- adapt these for your setup -- + CLOCK_FREQUENCY : natural := 50000000; -- clock frequency of clk_i in Hz + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output + -- UART0 -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic -- UART0 receive data + ); +end entity; + +architecture neorv32_test_setup_avalonmm_rtl of neorv32_test_setup_avalonmm is + + component neorv32_top_avalonmm is + generic ( + -- General -- + CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? + CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? + + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2 + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) + PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory (IMEM) -- + MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory (DMEM) -- + MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes + + -- Internal Cache memory (iCACHE) -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- Stream link interface (SLINK) -- + SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) + SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) + SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two + + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + + -- Processor peripherals -- + IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)? + IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic + IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits + IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional) + jtag_tck_i : in std_ulogic := 'U'; -- serial clock + jtag_tdi_i : in std_ulogic := 'U'; -- serial data input + jtag_tdo_o : out std_ulogic; -- serial data output + jtag_tms_i : in std_ulogic := 'U'; -- mode select + + -- AvalonMM interface + read_o : out std_logic; + write_o : out std_logic; + waitrequest_i : in std_logic := '0'; + byteenable_o : out std_logic_vector(3 downto 0); + address_o : out std_logic_vector(31 downto 0); + writedata_o : out std_logic_vector(31 downto 0); + readdata_i : in std_logic_vector(31 downto 0) := (others => '0'); + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o : out std_ulogic; -- indicates an executed FENCE operation + fencei_o : out std_ulogic; -- indicates an executed FENCEI operation + + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o : out sdata_8x32_t; -- output data + slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send + + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data + slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input + slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output + gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data + uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o : out std_ulogic; -- UART1 send data + uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data + uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_ulogic; -- SPI serial clock + spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in + spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic := 'U'; -- twi serial data line + twi_scl_io : inout std_logic := 'U'; -- twi serial clock line + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels + + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit + cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o : out std_ulogic; -- async serial data line + + -- System time -- + mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true) + + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels + + -- CPU interrupts -- + mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt + mext_irq_i : in std_ulogic := 'L' -- machine external interrupt + ); + end component neorv32_top_avalonmm; + + -- Intel/Altera RAM module created by MegaWizard + COMPONENT dmem_ram IS + PORT + ( + address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT dmem_ram; + +signal con_gpio_o : std_ulogic_vector(63 downto 0); + +signal read_o : std_logic; +signal write_o : std_logic; +signal waitrequest_i : std_logic; +signal byteenable_o : std_logic_vector(3 downto 0); +signal address_o : std_logic_vector(31 downto 0); +signal writedata_o : std_logic_vector(31 downto 0); +signal readdata_i : std_logic_vector(31 downto 0); + +signal read_wait_cnt : std_logic_vector(1 downto 0); + + +begin + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top_avalonmm + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => false, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => 0, -- size of processor-internal data memory in bytes + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd_o, -- UART0 send data + uart0_rxd_i => uart0_rxd_i, -- UART0 receive data + -- AvalonMM Interface + read_o => read_o, + write_o => write_o, + waitrequest_i => waitrequest_i, + byteenable_o => byteenable_o, + address_o => address_o, + writedata_o => writedata_o, + readdata_i => readdata_i + ); + + -- Simple example hooking up RAM module to AvalonMM Interface + -- and using this RAM as DMEM + my_dmem_ram : dmem_ram + port map( + address => address_o(12 downto 2), + byteena => byteenable_o, + clock => clk_i, + data => writedata_o, + wren => write_o, + q => readdata_i); + + + -- Very simple AvalonMM control signals + -- Write has 0 wait-states + -- Read has 2 wait-states + waitrequest_i <= '1' when (read_o = '1' and read_wait_cnt /= "10") else '0'; + process(clk_i, rstn_i) + begin + if rstn_i = '0' then + read_wait_cnt <= "00"; + elsif rising_edge(clk_i) then + if read_o = '0' then + read_wait_cnt <= "00"; + else + read_wait_cnt <= read_wait_cnt + '1'; + end if; + end if; + end process; + + -- GPIO output -- + gpio_o <= con_gpio_o(7 downto 0); + + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/.gitignore b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/.gitignore new file mode 100644 index 0000000..818036c --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/.gitignore @@ -0,0 +1,8 @@ +/.qsys_edit +/db +/neorv32_test_qsys +/*.sopcinfo +/*.rpt +/output_files +/incremental_db +/*.qws diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/README.md b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/README.md new file mode 100644 index 0000000..012a17a --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/README.md @@ -0,0 +1,51 @@ +# NEORV32 Test Setup using the NEORV32 as a Nios II drop-in replacement + +This setup provides a very simple "demo setup" that uses the NEORV32 Qsys/Platform Designer component +so that the NEORV32 can be used as a drop-in replacement of the Nios II soft CPU from Intel. +The demo is running on the Terasic DE0-Nano FPGA Board. + +The design is based on the de0-nano-test-setup, but the NEORV32 cpu is added as a QSys/Platform Designer +component. As an example the DMEM is "external" and uses an Platform Designer SRAM block. + +![NEORV32 in Platform Designer](figures/neorv32_platform_designer.png) + +For details about the design and use of the NEORV32 as a Qsys/Platform Designer component please +look at the Qsys component files and documentation here [`NEORV32 Qsys Component`](../neorv32_qsys_component) + +It uses the simplified simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). + +* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) +* FPGA: Intel Cyclone-IV `EP4CE22F17C6N` +* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition) + + +### NEORV32 Configuration + +For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used +with a few exceptions: + +* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader +* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +* Clock: 50MHz from on-board oscillator +* Reset: via on-board button "KEY0" +* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") +* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header + * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4") + * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6") + +### FPGA Utilization + +``` +Total logic elements 4,064 / 22,320 ( 18 % ) +Total registers 1932 +Total pins 12 / 154 ( 8 % ) +Total virtual pins 0 +Total memory bits 230,400 / 608,256 ( 38 % ) +Embedded Multiplier 9-bit elements 0 / 132 ( 0 % ) +Total PLLs 0 / 4 ( 0 % ) +``` + + +## How To Run + +Open the Quartus project file, compile and upload to FPGA. \ No newline at end of file diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/User_Components.ipx b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/User_Components.ipx new file mode 100644 index 0000000..a0e1337 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/User_Components.ipx @@ -0,0 +1,3 @@ + + + diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qpf b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qpf new file mode 100644 index 0000000..2381531 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition +# Date created = 21:29:54 June 08, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "21:29:54 June 08, 2021" + +# Revisions + +PROJECT_REVISION = "de0-nano-test-setup" diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qsf b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qsf new file mode 100644 index 0000000..708a065 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.qsf @@ -0,0 +1,76 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition +# Date created = 21:29:54 June 08, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de0-nano-test-setup_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name TOP_LEVEL_ENTITY neorv32_ProcessorTop_Test +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id neorv32_ProcessorTop_Test +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id neorv32_ProcessorTop_Test +set_global_assignment -name PARTITION_COLOR 16764057 -section_id neorv32_ProcessorTop_Test +set_location_assignment PIN_R8 -to clk_i +set_location_assignment PIN_J15 -to rstn_i +set_location_assignment PIN_C3 -to uart0_txd_o +set_location_assignment PIN_A3 -to uart0_rxd_i +set_location_assignment PIN_L3 -to gpio_o[7] +set_location_assignment PIN_B1 -to gpio_o[6] +set_location_assignment PIN_F3 -to gpio_o[5] +set_location_assignment PIN_D1 -to gpio_o[4] +set_location_assignment PIN_A11 -to gpio_o[3] +set_location_assignment PIN_B13 -to gpio_o[2] +set_location_assignment PIN_A13 -to gpio_o[1] +set_location_assignment PIN_A15 -to gpio_o[0] +set_global_assignment -name QSYS_FILE neorv32_test_qsys.qsys +set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip +set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32 +set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32 +set_global_assignment -name VHDL_FILE neorv32_ProcessorTop_Test.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id neorv32_ProcessorTop_Test \ No newline at end of file diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.sdc b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.sdc new file mode 100644 index 0000000..f67f960 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/de0-nano-test-setup.sdc @@ -0,0 +1,12 @@ +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] +create_clock -name {clk_i} -period 20.0 -waveform { 0.0 10.0 } [get_ports {clk_i}] diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/figures/neorv32_platform_designer.png b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/figures/neorv32_platform_designer.png new file mode 100644 index 0000000..26dbe4e Binary files /dev/null and b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/figures/neorv32_platform_designer.png differ diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd new file mode 100644 index 0000000..b1841d6 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_ProcessorTop_Test.vhd @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library work; + +entity neorv32_ProcessorTop_Test is port ( + clk_i : in std_logic; + rstn_i : in std_logic; + gpio_o : out std_logic_vector(7 downto 0); + uart0_txd_o : out std_logic; + uart0_rxd_i : in std_logic); +end neorv32_ProcessorTop_Test; + +---------------------------------------------------------------------------------------------------- +architecture rtl of neorv32_ProcessorTop_Test is +---------------------------------------------------------------------------------------------------- + +component neorv32_test_qsys is +port ( + clk_clk : in std_logic; + perf_uart0_uart0_txd_o : out std_logic; + perf_uart0_uart0_rxd_i : in std_logic; + perf_gpio_gpio_o : out std_logic_vector(31 downto 0); + perf_gpio_gpio_i : in std_logic_vector(31 downto 0); + reset_reset_n : in std_logic); +end component; + +signal perf_gpio_gpio_o : std_logic_vector(31 downto 0); + +begin + + gpio_o <= perf_gpio_gpio_o(7 downto 0); + + my_riscv_core : neorv32_test_qsys + port map ( + clk_clk => clk_i, + perf_gpio_gpio_o => perf_gpio_gpio_o, + perf_gpio_gpio_i => (others => '0'), + perf_uart0_uart0_txd_o => uart0_txd_o, + perf_uart0_uart0_rxd_i => uart0_rxd_i, + reset_reset_n => rstn_i); + +end rtl; diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_test_qsys.qsys b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_test_qsys.qsys new file mode 100644 index 0000000..7a0dac1 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/neorv32_test_qsys.qsys @@ -0,0 +1,232 @@ + + + + + + + + + + + + + + + + + de0-nano-test-setup.qpf + + + + + + + + + + + + + + $${FILENAME}_access_test_mem + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_ext_dmem + + + + + + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/.gitignore b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/.gitignore new file mode 100644 index 0000000..8a6f547 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/.gitignore @@ -0,0 +1,7 @@ +db +incremental_db +output_files +*.qpf +*.qsf +*.qws +*.vhd diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/README.md b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/README.md new file mode 100644 index 0000000..39ffe2c --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/README.md @@ -0,0 +1,62 @@ +# NEORV32 Test Setup for the Terasic DE0-Nano FPGA Board + +This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic DE0-Nano board. +It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor +top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). + +* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) +* FPGA: Intel Cyclone-IV `EP4CE22F17C6N` +* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition) + + +### NEORV32 Configuration + +:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for +configuration and entity details and `create_project.tcl` for the according FPGA pin mapping. + +* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide) +* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM +* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` +* Tested with version [`1.5.7.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +* Clock: 50MHz from on-board oscillator +* Reset: via on-board button "KEY0" +* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") +* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header + * `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4") + * `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6") + +:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity +is configured for a 100MHz input clock. Since the on-board oscillator of the DE0-nano board generates a 50MHz clock, the test setup has to be modified. +This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file +(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual +top entity. + +### FPGA Utilization + +``` +Total logic elements 4,009 / 22,320 ( 18 % ) +Total registers 1860 +Total pins 12 / 154 ( 8 % ) +Total virtual pins 0 +Total memory bits 230,400 / 608,256 ( 38 % ) +Embedded Multiplier 9-bit elements 0 / 132 ( 0 % ) +Total PLLs 0 / 4 ( 0 % ) +``` + + +## How To Run + +The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project. +If not already available, this script will create a `work` folder in this directory. + +1. start Quartus (in GUI mode) +2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console +3. use the console to naviagte to **this** folder: `cd .../neorv32/boards/de0-nano-test-setup` +4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder +5. if a "select family" prompt appears select the "Cyclone IV E" family and click OK +6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream +7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA +8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: +19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline) +9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) +and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources. diff --git a/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/create_project.tcl b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/create_project.tcl new file mode 100644 index 0000000..2f2be7e --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/create_project.tcl @@ -0,0 +1,94 @@ +# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file +# and modify the default clock frequency: set to 50MHz +set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd " +exec sh -c $shell_script + +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. + +# Quartus Prime: Generate Tcl File for Project +# File: de0_nano_test.tcl +# Generated on: Sat Apr 10 16:57:48 2021 + +# Load Quartus Prime Tcl Project package +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "de0-nano-test-setup"]} { + puts "Project de0-nano-test-setup is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists de0-nano-test-setup]} { + project_open -revision de0-nano-test-setup de0-nano-test-setup + } else { + project_new -revision de0-nano-test-setup de0-nano-test-setup + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY "Cyclone IV E" + set_global_assignment -name DEVICE EP4CE22F17C6 + set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader + set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 + set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021" + set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" + set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 + set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + + # core VHDL files + set core_src_dir [glob ./../../../rtl/core/*.vhd] + foreach core_src_file $core_src_dir { + set_global_assignment -name VHDL_FILE $core_src_file -library neorv32 + } + set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32 + set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32 + + # top entity: use local modified copy of the original test setup + set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd" + + set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + set_location_assignment PIN_R8 -to clk_i + set_location_assignment PIN_L3 -to gpio_o[7] + set_location_assignment PIN_B1 -to gpio_o[6] + set_location_assignment PIN_F3 -to gpio_o[5] + set_location_assignment PIN_D1 -to gpio_o[4] + set_location_assignment PIN_A11 -to gpio_o[3] + set_location_assignment PIN_B13 -to gpio_o[2] + set_location_assignment PIN_A13 -to gpio_o[1] + set_location_assignment PIN_A15 -to gpio_o[0] + set_location_assignment PIN_J15 -to rstn_i + set_location_assignment PIN_C3 -to uart0_txd_o + set_location_assignment PIN_A3 -to uart0_rxd_i + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments +} diff --git a/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/README.md b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/README.md new file mode 100644 index 0000000..187d985 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/README.md @@ -0,0 +1,73 @@ +# NEORV32 Platform Designer Component + +This folder contains a Qsys/Platform Designer wrapper for the NEORV32 together with +an Wishbone to AvalonMM bridge. This makes the NEORV32 a drop-in replacement for the +Altera/Intel Nios II soft CPU. + +This is just a quick template showing a possible solution, and not a feature complete +solution. All parameters in the Generic section could be added to the GUI. + +Only some peripherals (UART0, UART1 and GPIO) are connected, but other peripheral +could easily be connected. + +## Solution overview + +The solution is made up of 3 files. One VHDL file for the component implementation +(neorv32_qsys.vhd), one file for the Qsys component (neorv32_qsys_hw.tcl) and one file +listing files to include (neorv32_qsys.qip) to simplify the Quartus setup (.qsf) file. +The figure below shows how the component is implemented. + +![NEORV32 Qsys Component Solution](figures/overview.png) + +## GUI Settings + +The Qsys component is created so that some parameters can be set in the Platform Design +GUI. More settings could be added as needed. + +![NEORV32 GUI Settings](figures/gui_settings.png) + +## Implementation notes + +The Platform Designer has a bug (feature?) that makes boolean parameters from the Platform +Designer GUI being port mapped to the VHDL component generic as 0/1 instead of true/false. +This is a known bug/feature. + +A workaround for this is made by making the generic (boolean) parameters in the VHDL +as "integer", and then use a "integer2bool" function to make the parameter boolean +again to fit the NEORV32 top. + +## How to use + +To use the Qsys component in your Platform Designer design, you will just need to +make a "User_Components.ipx" file in your Qsys folder, and reference this (rtl/system_integration/neorv32_qsys_component) folder. + +Example "User_Components.ipx" content: +``` + + + +``` + +You will also need to add 3 lines in your Quartus project file (QSF-file) in order to +get the correct source files. + +Example QSF-file info: +``` +...... +set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip +set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd +...... +``` + +Having seperate links for the bootloader and application images makes it easy to include images +from your own project folders. + +# NEORV32 Platform Designer Component - Example Design + +The branch contains an example design using the Qsys/Platform designer component +and running on the DE0 Nano board. + +The example design can be found here [setups/quartus/de0-nano-test-setup-qsys`](../de0-nano-test-setup-qsys) + +The example design will run the software examples. diff --git a/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/figures/gui_settings.png b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/figures/gui_settings.png new file mode 100644 index 0000000..f607085 Binary files /dev/null and b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/figures/gui_settings.png differ diff --git a/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/figures/overview.png b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/figures/overview.png new file mode 100644 index 0000000..985ac9e Binary files /dev/null and b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/figures/overview.png differ diff --git a/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.qip b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.qip new file mode 100644 index 0000000..59271eb --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.qip @@ -0,0 +1,33 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_boot_rom.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_busswitch.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_bus_keeper.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cfs.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_alu.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_bus.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_control.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_fpu.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_muldiv.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_decompressor.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_regfile.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dm.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dtm.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_gpio.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_icache.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_mtime.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_nco.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_neoled.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_pwm.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_spi.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_sysinfo.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_top.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_trng.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_twi.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_uart.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wdt.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wishbone.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_fifo.vhd"] -library neorv32 +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_shifter.vhd"] -library neorv32 + diff --git a/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd new file mode 100644 index 0000000..c04da0d --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys.vhd @@ -0,0 +1,279 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor Top Qsys component with AvalonMM Compatible Master Interface >> # +-- # ********************************************************************************************* # +-- # (c) "NIOS-2", "Qsys", "Platform Designer" and "AvalonMM" are trademarks of Intel. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_qsys is + generic ( + GUI_CLOCK_FREQUENCY : integer := 100000000; + GUI_EMABLE_INTERNAL_IMEM : integer := 1; + GUI_IMEM_SIZE : integer := 16; + GUI_EMABLE_INTERNAL_DMEM : integer := 1; + GUI_DMEM_SIZE : integer := 8; + GUI_ENABLE_BOOTLOADER : integer := 0; + GUI_ENABLE_AVALONMM : integer := 1; + GUI_ENABLE_UART0 : integer := 1; + GUI_ENABLE_UART1 : integer := 0; + GUI_ENABLE_GPIO : integer := 0 + ); + port ( + -- Global control -- + clk_i : in std_logic := '0'; -- global clock, rising edge + rstn_i : in std_logic := '0'; -- global reset, low-active, async + -- GPIO -- + gpio_o : out std_logic_vector(63 downto 0); -- parallel output + gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel output + -- UART0 -- + uart0_txd_o : out std_logic; -- UART0 send data + uart0_rxd_i : in std_logic := '0'; -- UART0 receive data + + -- UART1 -- + uart1_txd_o : out std_logic; -- UART0 send data + uart1_rxd_i : in std_logic := '0'; -- UART0 receive data + + -- AvalonMM interface + read : out std_logic; + write : out std_logic; + waitrequest : in std_logic := '0'; + byteenable : out std_logic_vector(3 downto 0); + address : out std_logic_vector(31 downto 0); + writedata : out std_logic_vector(31 downto 0); + readdata : in std_logic_vector(31 downto 0) := (others => '0') + + ); +end entity; + +architecture neorv32_qsys_rtl of neorv32_qsys is + +signal gpio_i_ulogic : std_ulogic_vector(63 downto 0); +signal gpio_o_ulogic : std_ulogic_vector(63 downto 0); + +-- Wishbone bus interface (available if MEM_EXT_EN = true) -- +signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag +signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address +signal wb_dat_i : std_ulogic_vector(31 downto 0); -- read data +signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data +signal wb_we_o : std_ulogic; -- read/write +signal wb_sel_o : std_ulogic_vector(03 downto 0); -- byte enable +signal wb_stb_o : std_ulogic; -- strobe +signal wb_cyc_o : std_ulogic; -- valid cycle +signal wb_lock_o : std_ulogic; -- exclusive access request +signal wb_ack_i : std_ulogic; -- transfer acknowledge +signal wb_err_i : std_ulogic; -- transfer error + +signal reset : std_logic; + +function integer2bool(integer_value : integer := 0) return boolean is +begin + if integer_value = 0 then + return false; + else + return true; + end if; +end function; + +begin + + -- The Core Of The Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => GUI_CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => integer2bool(GUI_ENABLE_BOOTLOADER), -- implement processor-internal bootloader? + HW_THREAD_ID => 0, -- hardware thread id (hartid) + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => false, -- implement atomic extension? + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension? + CPU_EXTENSION_RISCV_U => true, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension? + -- Extension Options -- + FAST_MUL_EN => false, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => false, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64) + CPU_IPB_ENTRIES => 2, -- entries is instruction prefetch buffer, has to be a power of 2 + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => 0, -- number of regions (0..64) + PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => 4, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_IMEM), -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => GUI_IMEM_SIZE*1024, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_DMEM), -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => GUI_DMEM_SIZE*1024, -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN => false, -- implement instruction cache + ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External memory interface -- + MEM_EXT_EN => integer2bool(GUI_ENABLE_AVALONMM), -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) + MEM_EXT_PIPE_MODE => false, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian + MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false + -- Stream link interface (SLINK) -- + SLINK_NUM_TX => 0, -- number of TX links (0..8) + SLINK_NUM_RX => 0, -- number of TX links (0..8) + SLINK_TX_FIFO => 1, -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO => 1, -- RX fifo depth, has to be a power of two + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH => 0, -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE => (x"FFFFFFFF"), -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY => (x"FFFFFFFF"), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN => integer2bool(GUI_ENABLE_GPIO), -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => integer2bool(GUI_ENABLE_UART0), -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => integer2bool(GUI_ENABLE_UART1), -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => false, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => false, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => true, -- implement watch dog timer (WDT)? + IO_TRNG_EN => false, -- implement true random number generator (TRNG)? + IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NEOLED_EN => false, -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO => 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => '0', -- low-active TAP reset (optional) + jtag_tck_i => '0', -- serial clock + jtag_tdi_i => '0', -- serial data input + jtag_tdo_o => open, -- serial data output + jtag_tms_i => '0', -- mode select + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => wb_tag_o, -- tag + wb_adr_o => wb_adr_o, -- address + wb_dat_i => wb_dat_i, -- read data + wb_dat_o => wb_dat_o, -- write data + wb_we_o => wb_we_o, -- read/write + wb_sel_o => wb_sel_o, -- byte enable + wb_stb_o => wb_stb_o, -- strobe + wb_cyc_o => wb_cyc_o, -- valid cycle + wb_lock_o => wb_lock_o, -- exclusive access request + wb_ack_i => wb_ack_i, -- transfer acknowledge + wb_err_i => wb_err_i, -- transfer error + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o => open, -- output data + slink_tx_val_o => open, -- valid output + slink_tx_rdy_i => (others => 'L'), -- ready to send + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i => (others => (others => 'U')), -- input data + slink_rx_val_i => (others => 'L'), -- valid input + slink_rx_rdy_o => open, -- ready to receive + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => gpio_o_ulogic, -- parallel output + gpio_i => gpio_i_ulogic, -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd_o, -- UART0 send data + uart0_rxd_i => uart0_rxd_i, -- UART0 receive data + uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => uart1_txd_o, -- UART1 send data + uart1_rxd_i => uart1_rxd_i, -- UART1 receive data + uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => open, -- SPI serial clock + spi_sdo_o => open, -- controller data out, peripheral data in + spi_sdi_i => '0', -- controller data in, peripheral data out + spi_csn_o => open, -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => open, -- twi serial data line + twi_scl_io => open, -- twi serial clock line + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => open, -- pwm channels + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom inputs + cfs_out_o => open, -- custom outputs + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i => (others => '0'), -- IRQ channels + -- Interrupts -- + mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => '0', -- machine software interrupt + mext_irq_i => '0' -- machine external interrupt + ); + + -- Convert between std_logic / std_ulogic + gpio_o <= std_logic_vector(gpio_o_ulogic); + gpio_i_ulogic <= std_ulogic_vector(gpio_i); + + reset <= not(rstn_i); + + -- Wishbone to AvalonMM brdige + read <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0'; + write <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0'; + address <= std_logic_vector(wb_adr_o); + writedata <= std_logic_vector(wb_dat_o); + byteenable <= std_logic_vector(wb_sel_o); + + wb_dat_i <= std_ulogic_vector(readdata); + wb_ack_i <= not(waitrequest); + wb_err_i <= '0'; + +end architecture; diff --git a/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys_hw.tcl b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys_hw.tcl new file mode 100644 index 0000000..55f7b0f --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/neorv32_qsys_component/neorv32_qsys_hw.tcl @@ -0,0 +1,258 @@ + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + +# +# module neorv32_qsys +# +set_module_property DESCRIPTION "NEORV32 RISC-V CPU" +set_module_property NAME neorv32_qsys +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP "NEORV32" +set_module_property AUTHOR "Stephan Nolting" +set_module_property DISPLAY_NAME "NEORV32 CPU" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE false +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false +set_module_property ELABORATION_CALLBACK elaborate + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL neorv32_qsys +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file neorv32_qsys.vhd VHDL PATH neorv32_qsys.vhd TOP_LEVEL_FILE + +# +# parameters +# +#add_parameter src_id INTEGER 1 "" +#set_parameter_property src_id DEFAULT_VALUE 1 +#set_parameter_property src_id DISPLAY_NAME src_id +#set_parameter_property src_id WIDTH "" +#set_parameter_property src_id TYPE INTEGER +#set_parameter_property src_id UNITS None +#set_parameter_property src_id ALLOWED_RANGES 1:15 +#set_parameter_property src_id DESCRIPTION "Input source ID" +#set_parameter_property src_id HDL_PARAMETER true + +add_parameter GUI_CLOCK_FREQUENCY INTEGER 100000000 +set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_NAME "CPU Clock Frequency" +set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_UNITS "Hz" +set_parameter_property GUI_CLOCK_FREQUENCY DESCRIPTION "CPU clock frequency" +set_parameter_property GUI_CLOCK_FREQUENCY ALLOWED_RANGES 1000000:250000000 +set_parameter_property GUI_CLOCK_FREQUENCY GROUP "Core" +set_parameter_property GUI_CLOCK_FREQUENCY HDL_PARAMETER true + +add_parameter GUI_EMABLE_INTERNAL_IMEM BOOLEAN true +set_parameter_property GUI_EMABLE_INTERNAL_IMEM DISPLAY_NAME "Enable Internal IMEM" +set_parameter_property GUI_EMABLE_INTERNAL_IMEM DESCRIPTION "Use interal IMEM" +set_parameter_property GUI_EMABLE_INTERNAL_IMEM GROUP "Core" +set_parameter_property GUI_EMABLE_INTERNAL_IMEM HDL_PARAMETER true + +add_parameter GUI_IMEM_SIZE INTEGER 16 +set_parameter_property GUI_IMEM_SIZE DISPLAY_NAME "Internal IMEM Memory Size" +set_parameter_property GUI_IMEM_SIZE DISPLAY_UNITS "KBytes" +set_parameter_property GUI_IMEM_SIZE DESCRIPTION "Size of IMEM instruction memory" +set_parameter_property GUI_IMEM_SIZE ALLOWED_RANGES {4 8 16 32 64} +set_parameter_property GUI_IMEM_SIZE GROUP "Core" +set_parameter_property GUI_IMEM_SIZE HDL_PARAMETER true + +add_parameter GUI_EMABLE_INTERNAL_DMEM BOOLEAN true +set_parameter_property GUI_EMABLE_INTERNAL_DMEM DISPLAY_NAME "Enable Internal DMEM" +set_parameter_property GUI_EMABLE_INTERNAL_DMEM DESCRIPTION "Use interal DMEM" +set_parameter_property GUI_EMABLE_INTERNAL_DMEM GROUP "Core" +set_parameter_property GUI_EMABLE_INTERNAL_DMEM HDL_PARAMETER true + +add_parameter GUI_DMEM_SIZE INTEGER 8 +set_parameter_property GUI_DMEM_SIZE DISPLAY_NAME "Internal DMEM Memory Size" +set_parameter_property GUI_DMEM_SIZE DISPLAY_UNITS "KBytes" +set_parameter_property GUI_DMEM_SIZE DESCRIPTION "Size of DMEM data memory" +set_parameter_property GUI_DMEM_SIZE ALLOWED_RANGES {2 4 8 16 32 64} +set_parameter_property GUI_DMEM_SIZE GROUP "Core" +set_parameter_property GUI_DMEM_SIZE HDL_PARAMETER true + + +add_parameter GUI_ENABLE_BOOTLOADER BOOLEAN false +set_parameter_property GUI_ENABLE_BOOTLOADER DISPLAY_NAME "Enable Bootloader" +set_parameter_property GUI_ENABLE_BOOTLOADER DESCRIPTION "Add bootloader and start bootloader" +set_parameter_property GUI_ENABLE_BOOTLOADER GROUP "Bootloader" +set_parameter_property GUI_ENABLE_BOOTLOADER HDL_PARAMETER true + + +add_parameter GUI_ENABLE_AVALONMM BOOLEAN true +set_parameter_property GUI_ENABLE_AVALONMM DISPLAY_NAME "Enable AvalonMM Interface" +set_parameter_property GUI_ENABLE_AVALONMM DESCRIPTION "Add AvalonMM Interface for external modules" +set_parameter_property GUI_ENABLE_AVALONMM GROUP "Peripheral" +set_parameter_property GUI_ENABLE_AVALONMM HDL_PARAMETER true + +add_parameter GUI_ENABLE_UART0 BOOLEAN true +set_parameter_property GUI_ENABLE_UART0 DISPLAY_NAME "Enable UART0" +set_parameter_property GUI_ENABLE_UART0 DESCRIPTION "Add UART0 to core" +set_parameter_property GUI_ENABLE_UART0 GROUP "Peripheral" +set_parameter_property GUI_ENABLE_UART0 HDL_PARAMETER true + +add_parameter GUI_ENABLE_UART1 BOOLEAN false +set_parameter_property GUI_ENABLE_UART1 DISPLAY_NAME "Enable UART1" +set_parameter_property GUI_ENABLE_UART1 DESCRIPTION "Add UART1 to core" +set_parameter_property GUI_ENABLE_UART1 GROUP "Peripheral" +set_parameter_property GUI_ENABLE_UART1 HDL_PARAMETER true + +add_parameter GUI_ENABLE_GPIO BOOLEAN false +set_parameter_property GUI_ENABLE_GPIO DISPLAY_NAME "Enable GPIO" +set_parameter_property GUI_ENABLE_GPIO DESCRIPTION "Add GPIO to core" +set_parameter_property GUI_ENABLE_GPIO GROUP "Peripheral" +set_parameter_property GUI_ENABLE_GPIO HDL_PARAMETER true + + + +# +# display items +# + + +# +# connection point clk +# +add_interface clk clock end +set_interface_property clk clockRate 0 +set_interface_property clk ENABLED true +set_interface_property clk EXPORT_OF "" +set_interface_property clk PORT_NAME_MAP "" +set_interface_property clk CMSIS_SVD_VARIABLES "" +set_interface_property clk SVD_ADDRESS_GROUP "" + +add_interface_port clk clk_i clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clk +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rstn_i reset_n Input 1 + +# +# connection point perf_gpio +# +add_interface perf_gpio conduit end +set_interface_property perf_gpio associatedClock none +set_interface_property perf_gpio associatedReset none +set_interface_property perf_gpio ENABLED true +set_interface_property perf_gpio EXPORT_OF "" +set_interface_property perf_gpio PORT_NAME_MAP "" +set_interface_property perf_gpio CMSIS_SVD_VARIABLES "" +set_interface_property perf_gpio SVD_ADDRESS_GROUP "" + +add_interface_port perf_gpio gpio_o gpio_o Output 64 +add_interface_port perf_gpio gpio_i gpio_i Input 64 + +# +# connection point perf_uart0 +# +add_interface perf_uart0 conduit end +set_interface_property perf_uart0 associatedClock none +set_interface_property perf_uart0 associatedReset none +set_interface_property perf_uart0 ENABLED true +set_interface_property perf_uart0 EXPORT_OF "" +set_interface_property perf_uart0 PORT_NAME_MAP "" +set_interface_property perf_uart0 CMSIS_SVD_VARIABLES "" +set_interface_property perf_uart0 SVD_ADDRESS_GROUP "" + +add_interface_port perf_uart0 uart0_txd_o uart0_txd_o Output 1 +add_interface_port perf_uart0 uart0_rxd_i uart0_rxd_i Input 1 + +# +# connection point perf_uart1 +# +add_interface perf_uart1 conduit end +set_interface_property perf_uart1 associatedClock none +set_interface_property perf_uart1 associatedReset none +set_interface_property perf_uart1 ENABLED true +set_interface_property perf_uart1 EXPORT_OF "" +set_interface_property perf_uart1 PORT_NAME_MAP "" +set_interface_property perf_uart1 CMSIS_SVD_VARIABLES "" +set_interface_property perf_uart1 SVD_ADDRESS_GROUP "" + +add_interface_port perf_uart1 uart1_txd_o uart1_txd_o Output 1 +add_interface_port perf_uart1 uart1_rxd_i uart1_rxd_i Input 1 + +# +# connection point master +# +add_interface master avalon start +set_interface_property master addressUnits SYMBOLS +set_interface_property master associatedClock clk +set_interface_property master associatedReset reset +set_interface_property master bitsPerSymbol 8 +set_interface_property master burstOnBurstBoundariesOnly false +set_interface_property master burstcountUnits WORDS +set_interface_property master doStreamReads false +set_interface_property master doStreamWrites false +set_interface_property master holdTime 0 +set_interface_property master linewrapBursts false +set_interface_property master maximumPendingReadTransactions 0 +set_interface_property master maximumPendingWriteTransactions 0 +set_interface_property master readLatency 0 +set_interface_property master readWaitTime 0 +set_interface_property master setupTime 0 +set_interface_property master timingUnits Cycles +set_interface_property master writeWaitTime 0 +set_interface_property master ENABLED true +set_interface_property master EXPORT_OF "" +set_interface_property master PORT_NAME_MAP "" +set_interface_property master CMSIS_SVD_VARIABLES "" +set_interface_property master SVD_ADDRESS_GROUP "" + +add_interface_port master address address Output 32 +add_interface_port master read read Output 1 +add_interface_port master write write Output 1 +add_interface_port master byteenable byteenable Output 4 +add_interface_port master writedata writedata Output 32 +add_interface_port master readdata readdata Input 32 +add_interface_port master waitrequest waitrequest Input 1 + +# Callback to enable/disable interface signals +proc elaborate {} { + + if { [get_parameter_value GUI_ENABLE_GPIO] == "false" } { + set_interface_property perf_gpio ENABLED false + } else { + set_interface_property perf_gpio ENABLED true + } + + if { [get_parameter_value GUI_ENABLE_UART0] == "false" } { + set_interface_property perf_uart0 ENABLED false + } else { + set_interface_property perf_uart0 ENABLED true + } + + if { [get_parameter_value GUI_ENABLE_UART1] == "false" } { + set_interface_property perf_uart1 ENABLED false + } else { + set_interface_property perf_uart1 ENABLED true + } + + if { [get_parameter_value GUI_ENABLE_AVALONMM] == "false" } { + set_interface_property master ENABLED false + } else { + set_interface_property master ENABLED true + } + +} + diff --git a/Libs/RiscV/NEORV32/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/README.md b/Libs/RiscV/NEORV32/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/README.md new file mode 100644 index 0000000..088f4ea --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/README.md @@ -0,0 +1,65 @@ +# NEORV32 Test Setup for the Terasic Cyclone-V GX Starter Kit FPGA Board + +This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic Cyclone-V GX Starter Kit board. +It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor +top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs). + +* FPGA Board: :books: [Terasic Cyclone-V GX Starter Kit FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830) +* FPGA: Intel Cyclone-V GX `5CGXFC5C6F27C7N` +* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition) + + +### NEORV32 Configuration + +:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for +configuration and entity details and `create_project.tcl` for the according FPGA pin mapping. + +* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide) +* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM +* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` +* Tested with version [`1.5.9.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +* Clock: 50MHz from on-board oscillator +* Reset: via on-board button "KEY0" +* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0") +* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board provided USB to UART converter + +:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity +is configured for a 100MHz input clock. Since the on-board clock generator of the Cyclone-V GX Starter Kit board needs I2C to be programmed, the fixed 50MHz clock on bank 5B, pin R20 is used for this test setup, and the test setup has to be modified accordingly. +This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file +(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual +top entity. + +### FPGA Utilization + +``` +Logic utilization (in ALMs) 1,442 / 29,080 ( 5 % ) +Total registers 1771 +Total pins 12 / 364 ( 3 % ) +Total virtual pins 0 +Total block memory bits 231,424 / 4,567,040 ( 5 % ) +Total DSP Blocks 0 / 150 ( 0 % ) +Total HSSI RX PCSs 0 / 6 ( 0 % ) +Total HSSI PMA RX Deserializers 0 / 6 ( 0 % ) +Total HSSI TX PCSs 0 / 6 ( 0 % ) +Total HSSI PMA TX Serializers 0 / 6 ( 0 % ) +Total PLLs 0 / 12 ( 0 % ) +Total DLLs 0 / 4 ( 0 % ) +``` + + +## How To Run + +The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project. +If not already available, this script will create a `work` folder in this directory. + +1. start Quartus (in GUI mode) +2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console +3. use the console to navigate to **this** folder: `cd .../setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup` +4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder. Do NOT run the Quartus-supplied tcl setup script, as that will change all assignment names. +5. if a "select family" prompt appears, go to the "Board" tab, select the "Cyclone V GX Starter Kit" board and click OK +6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream +7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA +8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: +19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline) +9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) +and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources. diff --git a/Libs/RiscV/NEORV32/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/create_project.tcl b/Libs/RiscV/NEORV32/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/create_project.tcl new file mode 100644 index 0000000..436e4be --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup/create_project.tcl @@ -0,0 +1,108 @@ +# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file +# and modify the default clock frequency: set to 50MHz +set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd " +exec sh -c $shell_script + +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. + +# Quartus Prime: Generate Tcl File for Project +# File: terasic-cyclone-V-gx=starter-kit_test.tcl +# Generated on: Sat Apr 10 16:57:48 2021 + +# Load Quartus Prime Tcl Project package +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "terasic-cyclone-V-gx-starter-kit-test-setup"]} { + puts "Project terasic-cyclone-V-gx-starter-kit-test-setup is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists de0-nano-test-setup]} { + project_open -revision terasic-cyclone-V-gx-starter-kit-setup terasic-cyclone-V-gx-starter-kit-test-setup + } else { + project_new -revision terasic-cyclone-V-gx-starter-kit-test-setup terasic-cyclone-V-gx-starter-kit-test-setup + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY "Cyclone V" + set_global_assignment -name DEVICE 5CGXFC5C6F27C7 + set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader + set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 + set_global_assignment -name PROJECT_CREATION_TIME_DATE "TUE JUN 4 20:41:15 2013" + set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" + set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + set_global_assignment -name BOARD "Cyclone V GX Starter Kit" + set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 + set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + + # core VHDL files + set core_src_dir [glob ./../../../rtl/core/*.vhd] + foreach core_src_file $core_src_dir { + set_global_assignment -name VHDL_FILE $core_src_file -library neorv32 + } + + # top entity: use local modified copy of the original test setup + set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd" + + set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i + set_instance_assignment -name IO_STANDARD "1.2 V" -to rstn_i + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[0] + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[1] + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[2] + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[3] + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[4] + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[5] + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[6] + set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[7] + set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_rxd_i + set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_txd_o + + set_location_assignment PIN_R20 -to clk_i + set_location_assignment PIN_P11 -to rstn_i + set_location_assignment PIN_L7 -to gpio_o[0] + set_location_assignment PIN_K6 -to gpio_o[1] + set_location_assignment PIN_D8 -to gpio_o[2] + set_location_assignment PIN_E9 -to gpio_o[3] + set_location_assignment PIN_A5 -to gpio_o[4] + set_location_assignment PIN_B6 -to gpio_o[5] + set_location_assignment PIN_H8 -to gpio_o[6] + set_location_assignment PIN_H9 -to gpio_o[7] + set_location_assignment PIN_M9 -to uart0_rxd_i + set_location_assignment PIN_L9 -to uart0_txd_o + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments +} diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/.gitignore b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/.gitignore new file mode 100644 index 0000000..970d11e --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/.gitignore @@ -0,0 +1,20 @@ +/* + +!.gitignore +!README.md + +!system_pll/ +system_pll/* +!system_pll/system_pll.ipx +!system_pll/rtl/ +system_pll/rtl/* +!system_pll/rtl/system_pll.v + +!source/ +source/* +!source/impl_1.xcf + +!*.vhd +!*.rdf +!*.pdc +!*.bin diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/README.md b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/README.md new file mode 100644 index 0000000..6b88cdc --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/README.md @@ -0,0 +1,103 @@ +# NEORV32 Example Setup for the tinyVision.ai Inc. "UPduino v3.0" FPGA Board + + +This example setup turns the UPduino v3.0 board, which features a Lattice iCE40 UltraPlus FPGA, into a medium-scale NEORV32 *microcontroller*. +The processor setup provides 64kB of data and instruction memory, an RTOS-capable CPU (privileged architecture) +and a set of standard peripherals like UART, TWI and SPI. + + +* FPGA Board: :books: [tinyVision.ai Inc. UPduino v3 FPGA Board (GitHub)](https://github.com/tinyvision-ai-inc/UPduino-v3.0/), +:credit_card: buy on [Tindie](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) +* FPGA: Lattice iCE40 UltraPlus 5k `iCE40UP5K-SG48I` +* Toolchain: Lattice Radiant (tested with Radiant version 3.0.0), using *Lattice Synthesis Engine (LSE)* +* Top entity: [`neorv32_upduino_v3_top.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_upduino_v3_top.vhd) (instantiates NEORV32 top entity) + + +### Processor Configuration + +- [x] CPU: `rv32imacu_Zicsr_Zicntr` (reduced CPU `[m]instret` & `[m]cycle` counter width!) +- [x] Memory: 64 kB instruction memory (internal IMEM), 64 kB data memory (internal DMEM), 4 kB bootloader ROM +- [x] Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`, `TRNG` +- [x] Clock: 24 MHz from on-chip HF oscillator (via PLL) +- [x] Reset: via PLL "locked" signal; external "reset" via FPGA re-reconfiguration pin (`creset_n`) +- [x] Tested with processor version [`1.6.1.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +- [x] On-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader) + +:information_source: This setup uses optimized platform-specific memory modules for the internal data and instruction memories (DMEM & IMEM). Each memory uses two +UltraPlus SPRAM primitives (total memory size per memory = 2 x 32kB = 64kB). VHDL source file for platform-specific IMEM: +[`neorv32_imem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_imem.ice40up_spram.vhd); +VHDL source file for platform-specific DMEM: [`neorv32_dmem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_dmem.ice40up_spram.vhd). +These platform-specific memories are used *instead* of the default platform-agnostic modules from the core's `rtl/core/mem` folder. + + +### Interface Signals + +:information_source: See [`neorv32_upduino_v3.pdc`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_upduino_v3.pdc) +for the FPGA pin mapping. + +| Top Entity Signal | FPGA Pin | Package Pin | Board Header Pin | +|:------------------------------|:----------:|:------------:|:-----------------| +| `flash_csn_o` (spi_cs[0]) | IOB_35B | 16 | J3-1 | +| `flash_sck_o` | IOB_34A | 15 | J3-2 | +| `flash_sdo_o` | IOB_32A | 14 | J3-3 | +| `flash_sdi_i` | IOB_33B | 17 | J3-4 | +| `gpio_i(0)` | IOB_3B_G6 | 44 | J3-9 | +| `gpio_i(1)` | IOB_8A | 4 | J3-10 | +| `gpio_i(2)` | IOB_9B | 3 | J3-11 | +| `gpio_i(3)` | IOB_4A | 48 | J3-12 | +| `gpio_o(0)` (status LED) | IOB_5B | 45 | J3-13 | +| `gpio_o(1)` | IOB_2A | 47 | J3-14 | +| `gpio_o(2)` | IOB_0A | 46 | J3-15 | +| `gpio_o(3)` | IOB_6A | 2 | J3-16 | +| - | - | - | - | +| **reconfigure FPGA** ("_reset_") | CRESET | 8 | J2-3 | +| `pwm_o(0)` | `gpio_i(0)` (red)| RGB2 | 41 | J2-5 | +| `pwm_o(1)` (green) | RGB0 | 39 | J2-6 | +| `pwm_o(2)` (blue) | RGB1 | 40 | J2-7 | +| `twi_sda_io` | IOT_42B | 31 | J2-9 | +| `twi_scl_io` | IOT_45A_G1 | 37 | J2-10 | +| `spi_sdo_o` | IOT_44B | 34 | J2-11 | +| `spi_sck_o` | IOT_49A | 43 | J2-12 | +| `spi_csn_o` (spi_cs[1]) | IOT_48B | 36 | J2-13 | +| `spi_sdi_i` | IOT_51A | 42 | J2-14 | +| `uart_txd_o` (UART0) | IOT_50B | 38 | J2-15 | +| `uart_rxd_i` (UART0) | IOT_41A | 28 | J2-16 | + +:information_source: The TWI signals (`twi_sda_io` and `twi_scl_io`) and the reset input (`rstn_i`) require an external pull-up resistor. +GPIO output 0 (`gpio_o(0)`, also connected to the RGB drive) is used as output for a high-active **status LED** driven by the bootloader. + + +### FPGA Utilization + +``` +Number of slice registers: 1754 out of 5280 (33%) +Number of I/O registers: 11 out of 117 (9%) +Number of LUT4s: 4882 out of 5280 (92%) +Number of DSPs: 0 out of 8 (0%) +Number of I2Cs: 0 out of 2 (0%) +Number of High Speed OSCs: 1 out of 1 (100%) +Number of Low Speed OSCs: 0 out of 1 (0%) +Number of RGB PWM: 0 out of 1 (0%) +Number of RGB Drivers: 1 out of 1 (100%) +Number of SCL FILTERs: 0 out of 2 (0%) +Number of SRAMs: 4 out of 4 (100%) +Number of WARMBOOTs: 0 out of 1 (0%) +Number of SPIs: 0 out of 2 (0%) +Number of EBRs: 15 out of 30 (50%) +Number of PLLs: 1 out of 1 (100%) +``` + +### FPGA Setup + +1. start Lattice Radiant (in GUI mode) +2. click on "open project" and select `neorv32_upduino_v3.rdf` from this folder +3. click the :arrow_forward: button to synthesize, map, place and route the design and to generate a programming file +4. when done open the programmer (for example via "Tools" -> "Programmer"); you will need a programmer configuration, which will be created in the next steps; alternatively, +you can use the pre-build configuration `source/impl_1.xcf` +5. in the programmer double click on the field under "Operation" (_fast configuration_ should be the default) and select "External SPI Memory" as "Target Memory" +6. select "SPI Serial Flash" under "SPI Flash Options / Family" +7. select "WinBond" under "SPI Flash Options / Vendor" +8. select "W25Q32" under "SPI Flash Options / Device" +9. close the dialog by clicking "ok" +10. click on "Program Device" + diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd new file mode 100644 index 0000000..4ff9d74 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd @@ -0,0 +1,145 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> # +-- # ********************************************************************************************* # +-- # Memory has a physical size of 64kb (2 x SPRAMs). # +-- # Logical size DMEM_SIZE must be less or equal. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +library iCE40UP; +use iCE40UP.components.all; -- for device primitives + +architecture neorv32_dmem_rtl of neorv32_dmem is + + -- advanced configuration -------------------------------------------------------------------------------- + constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power) + -- ------------------------------------------------------------------------------------------------------- + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal mem_cs : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + + -- SPRAM signals -- + signal spram_clk : std_logic; + signal spram_addr : std_logic_vector(13 downto 0); + signal spram_di_lo : std_logic_vector(15 downto 0); + signal spram_di_hi : std_logic_vector(15 downto 0); + signal spram_do_lo : std_logic_vector(15 downto 0); + signal spram_do_hi : std_logic_vector(15 downto 0); + signal spram_be_lo : std_logic_vector(03 downto 0); + signal spram_be_hi : std_logic_vector(03 downto 0); + signal spram_we : std_logic; + signal spram_pwr_n : std_logic; + signal spram_cs : std_logic; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based DMEM." severity note; + assert not (DMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: DMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + mem_cs <= acc_en and (rden_i or wren_i); + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + dmem_spram_lo_inst : SP256K + port map ( + AD => spram_addr, -- I + DI => spram_di_lo, -- I + MASKWE => spram_be_lo, -- I + WE => spram_we, -- I + CS => spram_cs, -- I + CK => spram_clk, -- I + STDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + PWROFF_N => '1', -- I + DO => spram_do_lo -- O + ); + + dmem_spram_hi_inst : SP256K + port map ( + AD => spram_addr, -- I + DI => spram_di_hi, -- I + MASKWE => spram_be_hi, -- I + WE => spram_we, -- I + CS => spram_cs, -- I + CK => spram_clk, -- I + STDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + PWROFF_N => '1', -- I + DO => spram_do_hi -- O + ); + + -- access logic and signal type conversion -- + spram_clk <= std_logic(clk_i); + spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2)); + spram_di_lo <= std_logic_vector(data_i(15 downto 00)); + spram_di_hi <= std_logic_vector(data_i(31 downto 16)); + spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable + spram_cs <= std_logic(mem_cs); + spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable + spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable + spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected + rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo); + + buffer_ff: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= mem_cs; + rden <= acc_en and rden_i; + end if; + end process buffer_ff; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_dmem_rtl; diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_imem.ice40up_spram.vhd b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_imem.ice40up_spram.vhd new file mode 100644 index 0000000..d065504 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_imem.ice40up_spram.vhd @@ -0,0 +1,146 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> # +-- # ********************************************************************************************* # +-- # Memory has a physical size of 64kb (2 x SPRAMs). # +-- # Logical size IMEM_SIZE must be less or equal. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +library iCE40UP; +use iCE40UP.components.all; -- for device primitives + +architecture neorv32_imem_rtl of neorv32_imem is + + -- advanced configuration -------------------------------------------------------------------------------- + constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power) + -- ------------------------------------------------------------------------------------------------------- + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal mem_cs : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + + -- SPRAM signals -- + signal spram_clk : std_logic; + signal spram_addr : std_logic_vector(13 downto 0); + signal spram_di_lo : std_logic_vector(15 downto 0); + signal spram_di_hi : std_logic_vector(15 downto 0); + signal spram_do_lo : std_logic_vector(15 downto 0); + signal spram_do_hi : std_logic_vector(15 downto 0); + signal spram_be_lo : std_logic_vector(03 downto 0); + signal spram_be_hi : std_logic_vector(03 downto 0); + signal spram_we : std_logic; + signal spram_pwr_n : std_logic; + signal spram_cs : std_logic; + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note; + assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure; + assert not (IMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: IMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + mem_cs <= acc_en and (rden_i or wren_i); + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_spram_lo_inst : SP256K + port map ( + AD => spram_addr, -- I + DI => spram_di_lo, -- I + MASKWE => spram_be_lo, -- I + WE => spram_we, -- I + CS => spram_cs, -- I + CK => spram_clk, -- I + STDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + PWROFF_N => '1', -- I + DO => spram_do_lo -- O + ); + + imem_spram_hi_inst : SP256K + port map ( + AD => spram_addr, -- I + DI => spram_di_hi, -- I + MASKWE => spram_be_hi, -- I + WE => spram_we, -- I + CS => spram_cs, -- I + CK => spram_clk, -- I + STDBY => '0', -- I + SLEEP => spram_pwr_n, -- I + PWROFF_N => '1', -- I + DO => spram_do_hi -- O + ); + + -- access logic and signal type conversion -- + spram_clk <= std_logic(clk_i); + spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2)); + spram_di_lo <= std_logic_vector(data_i(15 downto 00)); + spram_di_hi <= std_logic_vector(data_i(31 downto 16)); + spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable + spram_cs <= std_logic(mem_cs); + spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable + spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable + spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected + rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo); + + buffer_ff: process(clk_i) + begin + if rising_edge(clk_i) then + ack_o <= mem_cs; + rden <= acc_en and rden_i; + end if; + end process buffer_ff; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_imem_rtl; diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3.pdc b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3.pdc new file mode 100644 index 0000000..d5141a5 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3.pdc @@ -0,0 +1,41 @@ +# Radiant pin mapping for the "tinyvision.ai Inc. UPduino v3" FPGA board + +## Clock (on-chip hf oscillator) +#create_clock -period 41.666666 -name hf_osc_clk [get_nets hf_osc_clk] + +## UART (uart0) +ldc_set_location -site {38} [get_ports uart_txd_o] +ldc_set_location -site {28} [get_ports uart_rxd_i] + +## SPI - on-board flash +ldc_set_location -site {14} [get_ports flash_sdo_o] +ldc_set_location -site {15} [get_ports flash_sck_o] +ldc_set_location -site {16} [get_ports flash_csn_o] +ldc_set_location -site {17} [get_ports flash_sdi_i] + +## SPI - user port +ldc_set_location -site {34} [get_ports spi_sdo_o] +ldc_set_location -site {43} [get_ports spi_sck_o] +ldc_set_location -site {36} [get_ports spi_csn_o] +ldc_set_location -site {42} [get_ports spi_sdi_i] + +## TWI +ldc_set_location -site {31} [get_ports twi_sda_io] +ldc_set_location -site {37} [get_ports twi_scl_io] + +## GPIO - input +ldc_set_location -site {44} [get_ports {gpio_i[0]}] +ldc_set_location -site {4} [get_ports {gpio_i[1]}] +ldc_set_location -site {3} [get_ports {gpio_i[2]}] +ldc_set_location -site {48} [get_ports {gpio_i[3]}] + +## GPIO - output +ldc_set_location -site {45} [get_ports {gpio_o[0]}] +ldc_set_location -site {47} [get_ports {gpio_o[1]}] +ldc_set_location -site {46} [get_ports {gpio_o[2]}] +ldc_set_location -site {2} [get_ports {gpio_o[3]}] + +## RGB power LED +ldc_set_location -site {39} [get_ports {pwm_o[0]}] +ldc_set_location -site {40} [get_ports {pwm_o[1]}] +ldc_set_location -site {41} [get_ports {pwm_o[2]}] diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3.rdf b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3.rdf new file mode 100644 index 0000000..86e0025 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3.rdf @@ -0,0 +1,137 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd new file mode 100644 index 0000000..b0c05df --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/neorv32_upduino_v3_top.vhd @@ -0,0 +1,248 @@ +-- ################################################################################################# +-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +library work; +use work.all; + +library iCE40UP; +use iCE40UP.components.all; -- for device primitives + +entity neorv32_upduino_v3_top is + port ( + -- UART (uart0) -- + uart_txd_o : out std_ulogic; + uart_rxd_i : in std_ulogic; + -- SPI to on-board flash -- + flash_sck_o : out std_ulogic; + flash_sdo_o : out std_ulogic; + flash_sdi_i : in std_ulogic; + flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0) + -- SPI to IO pins -- + spi_sck_o : out std_ulogic; + spi_sdo_o : out std_ulogic; + spi_sdi_i : in std_ulogic; + spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1) + -- TWI -- + twi_sda_io : inout std_logic; + twi_scl_io : inout std_logic; + -- GPIO -- + gpio_i : in std_ulogic_vector(3 downto 0); + gpio_o : out std_ulogic_vector(3 downto 0); + -- PWM (to on-board RGB power LED) -- + pwm_o : out std_ulogic_vector(2 downto 0) + ); +end neorv32_upduino_v3_top; + +architecture neorv32_upduino_v3_top_rtl of neorv32_upduino_v3_top is + + -- configuration -- + constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz + + -- On-chip oscillator -- + signal hf_osc_clk : std_logic; + + -- PLL (macro generated by radiant) -- + component system_pll + port ( + ref_clk_i : in std_logic; + rst_n_i : in std_logic; + lock_o : out std_logic; + outcore_o : out std_logic; + outglobal_o : out std_logic + ); + end component; + + signal pll_rstn : std_logic; + signal pll_clk : std_logic; + + -- CPU -- + signal cpu_clk : std_ulogic; + signal cpu_rstn : std_ulogic; + + -- internal IO connection -- + signal con_pwm : std_ulogic_vector(02 downto 0); + signal con_spi_sck : std_ulogic; + signal con_spi_sdi : std_ulogic; + signal con_spi_sdo : std_ulogic; + signal con_spi_csn : std_ulogic_vector(07 downto 0); + signal con_gpio_i : std_ulogic_vector(63 downto 0); + signal con_gpio_o : std_ulogic_vector(63 downto 0); + + -- Misc -- + signal pwm_drive : std_logic_vector(2 downto 0); + signal pwm_driven : std_ulogic_vector(2 downto 0); + +begin + + -- On-Chip HF Oscillator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + HSOSC_inst : HSOSC + generic map ( + CLKHF_DIV => "0b01" -- 24 MHz + ) + port map ( + CLKHFPU => '1', + CLKHFEN => '1', + CLKHF => hf_osc_clk + ); + + + -- System PLL ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + system_pll_inst: system_pll + port map ( + ref_clk_i => hf_osc_clk, + rst_n_i => '1', + lock_o => pll_rstn, + outcore_o => open, + outglobal_o => pll_clk + ); + + cpu_clk <= std_ulogic(pll_clk); + cpu_rstn <= std_ulogic(pll_rstn); + + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz + HW_THREAD_ID => 0, -- hardware thread id (32-bit) + INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => true, -- implement atomic extension? + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => true, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.? + + -- Extension Options -- + CPU_CNT_WIDTH => 34, -- total width of CPU cycle and instret counters (0..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => 64*1024, -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN => true, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => 64*1024, -- size of processor-internal data memory in bytes + + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_SPI_EN => true, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => true, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => 3, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => true, -- implement watch dog timer (WDT)? + IO_TRNG_EN => true -- implement true random number generator (TRNG)? + ) + port map ( + -- Global control -- + clk_i => cpu_clk, -- global clock, rising edge + rstn_i => cpu_rstn, -- global reset, low-active, async + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + gpio_i => con_gpio_i, -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart_txd_o, -- UART0 send data + uart0_rxd_i => uart_rxd_i, -- UART0 receive data + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => con_spi_sck, + spi_sdo_o => con_spi_sdo, + spi_sdi_i => con_spi_sdi, + spi_csn_o => con_spi_csn, + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda_io, -- twi serial data line + twi_scl_io => twi_scl_io, -- twi serial clock line + + -- PWM (available if IO_PWM_EN = true) -- + pwm_o => con_pwm -- pwm channels + ); + + -- GPIO -- + con_gpio_i <= x"000000000000000" & gpio_i(3 downto 0); + gpio_o(3 downto 0) <= con_gpio_o(3 downto 0); + + -- SPI -- + flash_sck_o <= con_spi_sck; + flash_sdo_o <= con_spi_sdo; + flash_csn_o <= con_spi_csn(0); + spi_sck_o <= con_spi_sck; + spi_sdo_o <= con_spi_sdo; + spi_csn_o <= con_spi_csn(1); + con_spi_sdi <= flash_sdi_i when (con_spi_csn(0) = '0') else spi_sdi_i; + + -- RGB -- + pwm_drive(0) <= std_logic(con_pwm(0) or con_gpio_o(0)); -- bit 0: red - pwm channel 0 OR gpio_o(0) [status LED] + pwm_drive(1) <= std_logic(con_pwm(1)); -- bit 1: green - pwm channel 1 + pwm_drive(2) <= std_logic(con_pwm(2)); -- bit 2: blue - pwm channel 2 + + RGB_inst: RGB + generic map ( + CURRENT_MODE => "1", + RGB0_CURRENT => "0b000001", + RGB1_CURRENT => "0b000001", + RGB2_CURRENT => "0b000001" + ) + port map ( + CURREN => '1', -- I + RGBLEDEN => '1', -- I + RGB0PWM => pwm_drive(1), -- I - green + RGB1PWM => pwm_drive(2), -- I - blue + RGB2PWM => pwm_drive(0), -- I - red + RGB2 => pwm_driven(2), -- O - red + RGB1 => pwm_driven(1), -- O - blue + RGB0 => pwm_driven(0) -- O - green + ); + + pwm_o <= std_ulogic_vector(pwm_driven); + + +end neorv32_upduino_v3_top_rtl; diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/source/impl_1.xcf b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/source/impl_1.xcf new file mode 100644 index 0000000..bd737ab --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/source/impl_1.xcf @@ -0,0 +1,108 @@ + + + + + + SPI + + + 1 + Lattice + iCE40 UltraPlus + iCE40UP5K + All + + 8 + 11111111 + 1 + 0 + + ../../impl_1/neorv32_upduino_v3_impl_1.bin + 11/04/21 21:44:40 + External SPI Flash Memory (SPI FLASH) + Erase,Program,Verify + + + + + 1 + Lattice + iCE40 UltraPlus + iCE40UP5K + 0x11200639 + All + iCE40UP5K + + 8 + 11111111 + 1 + 0 + + Compressed Random Access Memory (CRAM) + Bypass + + + + + + 1 + WinBond + SPI Serial Flash + W25Q32 + 0x15 + 8-pin SOIC + Erase,Program,Verify + ../../impl_1/neorv32_upduino_v3_impl_1.bin + 0x00000000 + 0x003F0000 + 32 + 104156 + 1 + + + + + + 1 + + N:/Projects/neorv32/boards/UPduino_v3/impl_1/neorv32_upduino_v3_impl_1.bin + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + 1 + + + USB2 + FTUSB-1 + UPduino v3.0 Location 0002 Serial + + diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/rtl/system_pll.v b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/rtl/system_pll.v new file mode 100644 index 0000000..bb22353 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/rtl/system_pll.v @@ -0,0 +1,222 @@ + +/******************************************************************************* + Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit) + 2.1.0.27.2 + Soft IP Version: 1.0.1 + Wed May 12 22:58:47 2021 +*******************************************************************************/ +/******************************************************************************* + Wrapper Module generated per user settings. +*******************************************************************************/ +module system_pll (ref_clk_i, + rst_n_i, + lock_o, + outcore_o, + outglobal_o) ; + input ref_clk_i ; + input rst_n_i ; + output lock_o ; + output outcore_o ; + output outglobal_o ; + system_pll_ipgen_lscc_pll #(.DIVR("0"), + .FILTER_RANGE("2"), + .FREQUENCY_PIN_REFERENCECLK("24.000000"), + .FEEDBACK_PATH("PHASE_AND_DELAY"), + .EXTERNAL_DIVIDE_FACTOR("NONE"), + .DIVF("0"), + .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), + .FDA_FEEDBACK("0"), + .SHIFTREG_DIV_MODE("0"), + .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"), + .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"), + .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), + .FDA_RELATIVE("0"), + .DIVQ("3"), + .ENABLE_ICEGATE_PORTA("0"), + .ENABLE_ICEGATE_PORTB("0")) lscc_pll_inst (.ref_clk_i(ref_clk_i), + .rst_n_i(rst_n_i), + .feedback_i(1'b0), + .dynamic_delay_i({4'b0000, + 4'b0000}), + .bypass_i(1'b0), + .latch_i(1'b0), + .lock_o(lock_o), + .outcore_o(outcore_o), + .outglobal_o(outglobal_o), + .outcoreb_o(), + .outglobalb_o(), + .sclk_i(), + .sdi_i(), + .sdo_o()) ; +endmodule + + + +// ============================================================================= +// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// ----------------------------------------------------------------------------- +// Copyright (c) 2017 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ----------------------------------------------------------------------------- +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// ----------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// ----------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : +// File : lscc_pll.v +// Title : +// Dependencies : 1. PLL_B primitive +// Description : iCE40UP Phase-Locked Loop. +// ============================================================================= +// REVISION HISTORY +// Version : 1.0.0. +// Author(s) : +// Mod. Date : 04.20.2017 +// Changes Made : Initial release. +// ============================================================================= +module system_pll_ipgen_lscc_pll #(parameter DIVR = "1", + parameter DIVF = "1", + parameter DIVQ = "1", + parameter FEEDBACK_PATH = "SIMPLE", + parameter FILTER_RANGE = "0", + parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED", + parameter FDA_FEEDBACK = "0", + parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED", + parameter FDA_RELATIVE = "0", + parameter SHIFTREG_DIV_MODE = "0", + parameter PLLOUT_SELECT_PORTA = "SHIFTREG_0deg", + parameter PLLOUT_SELECT_PORTB = "SHIFTREG_0deg", + parameter EXTERNAL_DIVIDE_FACTOR = "NONE", + parameter ENABLE_ICEGATE_PORTA = "0", + parameter ENABLE_ICEGATE_PORTB = "0", + parameter FREQUENCY_PIN_REFERENCECLK = "10.0") ( + // ----------------------------------------------------------------------------- + // Module Parameters + // ----------------------------------------------------------------------------- + // ----------------------------------------------------------------------------- + // Input/Output Ports + // ----------------------------------------------------------------------------- + input ref_clk_i, + input rst_n_i, + input feedback_i, + input [7:0] dynamic_delay_i, + input bypass_i, + input latch_i, + output wire lock_o, + output wire outcore_o, + output wire outglobal_o, + output wire outcoreb_o, + output wire outglobalb_o, + input sclk_i, + input sdi_i, + output wire sdo_o) ; + // ----------------------------------------------------------------------------- + // Wire Declarations + // ----------------------------------------------------------------------------- + wire [7:0] dynamic_delay_w ; + wire feedback_w ; + wire intfbout_w ; + // ----------------------------------------------------------------------------- + // Generate Assign Statements + // ----------------------------------------------------------------------------- + generate + if ((EXTERNAL_DIVIDE_FACTOR != "NONE")) + begin : genblk1 + assign feedback_w = feedback_i ; + end + else + begin : genblk1 + assign feedback_w = intfbout_w ; + end + endgenerate + generate + if ((DELAY_ADJUSTMENT_MODE_FEEDBACK == "FIXED")) + begin : genblk2 + assign dynamic_delay_w[3:0] = 4'b0 ; + end + else + begin : genblk2 + assign dynamic_delay_w[3:0] = dynamic_delay_i[3:0] ; + end + if ((DELAY_ADJUSTMENT_MODE_RELATIVE == "FIXED")) + begin : genblk3 + assign dynamic_delay_w[7:4] = 4'b0 ; + end + else + begin : genblk3 + assign dynamic_delay_w[7:4] = dynamic_delay_i[7:4] ; + end + endgenerate + // ----------------------------------------------------------------------------- + // PLL Primitive Instantiation + // ----------------------------------------------------------------------------- + PLL_B #(.DIVR(DIVR), + .DIVF(DIVF), + .DIVQ(DIVQ), + .FEEDBACK_PATH(FEEDBACK_PATH), + .FILTER_RANGE(FILTER_RANGE), + .DELAY_ADJUSTMENT_MODE_FEEDBACK(DELAY_ADJUSTMENT_MODE_FEEDBACK), + .FDA_FEEDBACK(FDA_FEEDBACK), + .DELAY_ADJUSTMENT_MODE_RELATIVE(DELAY_ADJUSTMENT_MODE_RELATIVE), + .FDA_RELATIVE(FDA_RELATIVE), + .SHIFTREG_DIV_MODE(SHIFTREG_DIV_MODE), + .PLLOUT_SELECT_PORTA(PLLOUT_SELECT_PORTA), + .PLLOUT_SELECT_PORTB(PLLOUT_SELECT_PORTB), + .EXTERNAL_DIVIDE_FACTOR(EXTERNAL_DIVIDE_FACTOR), + .ENABLE_ICEGATE_PORTA(ENABLE_ICEGATE_PORTA), + .ENABLE_ICEGATE_PORTB(ENABLE_ICEGATE_PORTB), + .FREQUENCY_PIN_REFERENCECLK(FREQUENCY_PIN_REFERENCECLK)) u_PLL_B (.REFERENCECLK(ref_clk_i), + .RESET_N(rst_n_i), + .FEEDBACK(feedback_w), + .DYNAMICDELAY7(dynamic_delay_w[7]), + .DYNAMICDELAY6(dynamic_delay_w[6]), + .DYNAMICDELAY5(dynamic_delay_w[5]), + .DYNAMICDELAY4(dynamic_delay_w[4]), + .DYNAMICDELAY3(dynamic_delay_w[3]), + .DYNAMICDELAY2(dynamic_delay_w[2]), + .DYNAMICDELAY1(dynamic_delay_w[1]), + .DYNAMICDELAY0(dynamic_delay_w[0]), + .INTFBOUT(intfbout_w), + .BYPASS(bypass_i), + .LATCH(latch_i), + .OUTCORE(outcore_o), + .OUTGLOBAL(outglobal_o), + .OUTCOREB(outcoreb_o), + .OUTGLOBALB(outglobalb_o), + .LOCK(lock_o), + .SCLK(sclk_i), + .SDI(sdi_i), + .SDO(sdo_o)) ; +endmodule + + diff --git a/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/system_pll.ipx b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/system_pll.ipx new file mode 100644 index 0000000..f0331a3 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/system_pll/system_pll.ipx @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/Libs/RiscV/NEORV32/setups/vivado/README.md b/Libs/RiscV/NEORV32/setups/vivado/README.md new file mode 100644 index 0000000..6d4eae2 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/README.md @@ -0,0 +1,32 @@ +# NEORV32 Xilinx Vivado Example Setups + +## How To Run + +The `create_project.tcl` TCL script in the board subdirectories can be used for creating a complete Vivado project and for running the implementation. +If not already available, this script will create a `work` folder in those subdirectories. + +Note that you may need to install support for your particular development board through "XHub Stores" menu item within Vivado prior to sourcing the `create_project.tcl` script. + +### Batch mode + +Execute `vivado -mode batch -nojournal -nolog -source create_project.tcl` from the board subdir. +The project will be created and implementation will be run until generation of `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`. + +### GUI + +1. start Vivado (in GUI mode) +2. click on "TCL Console" at the bottom +3. use the console to naviagte to the boards folder. For example: `cd .../neorv32/setups/vivado/arty-a7-test-setup` +4. execute `source create_project.tcl` - this will create the actual Vivado project in `work` +5. when the Vivado project has openend, Implementation will run and a bitstream will be generated. +6. maybe a prompt will notify about it. + +### Programming the Bitstream + +1. open the "Hardware Manager" (maybe a prompt will ask for that) +2. click on "Open target/Auto Connect" +3. click on "Program device" and select `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`; click "Program" +4. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration: +19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline) +5. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) +and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources. diff --git a/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/.gitignore b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/.gitignore new file mode 100644 index 0000000..97d1942 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/.gitignore @@ -0,0 +1,3 @@ +/vivado* +/.Xil +/work/* diff --git a/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/README.md b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/README.md new file mode 100644 index 0000000..f241c32 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/README.md @@ -0,0 +1,29 @@ +# NEORV32 Test Setup for the Digilent Arty A7-35 FPGA Board + +This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Arty A7-35 board. +It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor +top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs). + +* FPGA Board: :books: [Digilent Arty A7-35 FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual) +* FPGA: Xilinx Artix-7 `XC7A35TICSG324-1L` +* Toolchain: Xilinx Vivado (tested with Vivado 2019.2) + + +## NEORV32 Configuration + +:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for +configuration and entity details and [`arty_a7_35_test_setup.xdc`](https://github.com/stnolting/neorv32/blob/master/boards/arty-a7-35-test-setup/arty_a7_35_test_setup.xdc) +for the according FPGA pin mapping. + +* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors) +* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM +* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` +* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +* Clock: 100MHz from on-board oscillator +* Reset: Via dedicated on-board "RESET" button +* GPIO output port `gpio_o` + * bits 0..3 are connected to the green on-board LEDs (LD4 - LD7); LD4 is the bootloader status LED + * bits 4..7 are (not actually used) connected to PMOD `JA` connector pins 1-4 +* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip + + diff --git a/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc new file mode 100644 index 0000000..23a9757 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/arty_a7_test_setup.xdc @@ -0,0 +1,26 @@ +## This file is a general .xdc for the Arty A7-35 Rev. D + +## For default neorv32_test_setup.vhd top entity + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }]; + +## LEDs +set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L24N_T3_35 Sch=led[4] +set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_25_35 Sch=led[5] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] + +## Pmod Header JA (unused GPIO outputs) +set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_0_15 Sch=ja[1] +set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L4P_T0_15 Sch=ja[2] +set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L4N_T0_15 Sch=ja[3] +set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L6P_T0_15 Sch=ja[4] + +## USB-UART Interface +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in + +## Misc. +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { rstn_i }]; #IO_L16P_T2_35 Sch=ck_rst diff --git a/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/create_project.tcl b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/create_project.tcl new file mode 100644 index 0000000..8b8cbb0 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/create_project.tcl @@ -0,0 +1,57 @@ +set board "arty-a7-35" + +# Create and clear output directory +set outputdir work +file mkdir $outputdir + +set files [glob -nocomplain "$outputdir/*"] +if {[llength $files] != 0} { + puts "deleting contents of $outputdir" + file delete -force {*}[glob -directory $outputdir *]; # clear folder contents +} else { + puts "$outputdir is empty" +} + +switch $board { + "arty-a7-35" { + set a7part "xc7a35ticsg324-1L" + set a7prj ${board}-test-setup + } +} + +# Create project +create_project -part $a7part $a7prj $outputdir + +set_property board_part digilentinc.com:${board}:part0:1.0 [current_project] +set_property target_language VHDL [current_project] + +# Define filesets + +## Core: NEORV32 +add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd +set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]] +set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]] + +## Design: processor subsystem template, and (optionally) BoardTop and/or other additional sources +set fileset_design ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd + +## Constraints +set fileset_constraints [glob ./*.xdc] + +## Simulation-only sources +set fileset_sim [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd] + +# Add source files + +## Design +add_files $fileset_design + +## Constraints +add_files -fileset constrs_1 $fileset_constraints + +## Simulation-only +add_files -fileset sim_1 $fileset_sim + +# Run synthesis, implementation and bitstream generation +launch_runs impl_1 -to_step write_bitstream -jobs 4 +wait_on_run impl_1 diff --git a/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/.gitignore b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/.gitignore new file mode 100644 index 0000000..97d1942 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/.gitignore @@ -0,0 +1,3 @@ +/vivado* +/.Xil +/work/* diff --git a/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/README.md b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/README.md new file mode 100644 index 0000000..b41dc10 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/README.md @@ -0,0 +1,29 @@ +# NEORV32 Test Setup for the Digilent Nexys A7 and Nexys 4 DDR FPGA Boards + +This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Nexys A7 and Nexys 4 DDR boards. +It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor +top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs). + +* FPGA Boards: + * :books: [Digilent Nexys A7 FPGA Boards](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual) + * :books: [Digilent Nexys 4 DDR FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual) +* FPGAs: + * Xilinx Artix-7 `XC7A50TCSG324-1` + * Xilinx Artix-7 `XC7A100TCSG324-1` +* Toolchain: Xilinx Vivado (tested with Vivado 2020.2) + + +## NEORV32 Configuration + +:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for +configuration and entity details and [`nexys_a7_test_setup.xdc`](https://github.com/AWenzel83/neorv32/blob/nexys_a7_example/boards/nexys-a7-test-setup/nexys_a7_test_setup.xdc) +for the according FPGA pin mapping. + +* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors) +* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM +* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT` +* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +* Clock: 100MHz from on-board oscillator +* Reset: Via dedicated on-board "RESET" button +* GPIO output port `gpio_o` bits 0..7 are connected to the green on-board LEDs (LD0 - LD7); LD0 is the bootloader status LED +* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip diff --git a/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/create_project.tcl b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/create_project.tcl new file mode 100644 index 0000000..6b4f615 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/create_project.tcl @@ -0,0 +1,45 @@ +set board "A7-50" + +# create and clear output directory +set outputdir work +file mkdir $outputdir + +set files [glob -nocomplain "$outputdir/*"] +if {[llength $files] != 0} { + puts "deleting contents of $outputdir" + file delete -force {*}[glob -directory $outputdir *]; # clear folder contents +} else { + puts "$outputdir is empty" +} + +switch $board { + "A7-50" { + set a7part "xc7a50tcsg324-1" + set a7prj "nexys-a7-50-test-setup" + } + "A7-100" { + set a7part "xc7a100tcsg324-1" + set a7prj "nexys-a7-100-test-setup" + } +} + +# create project +create_project -part $a7part $a7prj $outputdir + +# add source files: core sources +add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd +set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]] +set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]] + +# add source file: top entity +add_files [glob ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd] + +# add source files: simulation-only +add_files -fileset sim_1 [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd] + +# add source files: constraints +add_files -fileset constrs_1 [glob ./*.xdc] + +# run synthesis, implementation and bitstream generation +launch_runs impl_1 -to_step write_bitstream -jobs 4 +wait_on_run impl_1 diff --git a/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/nexys_a7_test_setup.xdc b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/nexys_a7_test_setup.xdc new file mode 100644 index 0000000..c171bc4 --- /dev/null +++ b/Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/nexys_a7_test_setup.xdc @@ -0,0 +1,23 @@ +## This file is a general .xdc for the Nexys A7 and Nexys 4 DDR +## For default neorv32_test_setup.vhd top entity + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }]; + +## LEDs +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] + +## USB-UART Interface +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in + +## Misc. +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rstn_i }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_rst diff --git a/Libs/RiscV/NEORV32/sw/README.md b/Libs/RiscV/NEORV32/sw/README.md new file mode 100644 index 0000000..aebeab4 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/README.md @@ -0,0 +1,55 @@ +# NEORV32 Software Framework + +This folder provides the core of the NEORV32 software framework. +This is a short description of the main folders. + + +## [bootloader](bootloader) + +Source(s) of the default NEORV32 bootloader. +A pre-built image is already installed into the rtl design via the `rtl/core/neorv32_bootloader_image.vhd` file. + + +## [common](common) + +NEORV32-specific common files for all bootloader and application programs: +linker script for executable generation and processor start-up code. + + +## [example](example) + +Several example programs for testing and for getting started. + + +## [image_gen](image_gen) + +This folder contains a simple program that is used to create NEORV32 executables (for upload via bootloader) and VHDL +memory initialization files (for memory-persistent applications and for the bootloader). +This program is automatically compiled using the native GCC when invoking one of the application compilation makefiles. + + +## [isa-test](isa-test) + +NEORV32 RISC-V Architecture Test Framework. +See [sim/README](../sim/README.md). + + +## [lib](lib) + +Core libraries (sources and header files) and helper functions for using the processor peripherals and the CPU itself. + + +## [ocd-firmware](ocd-firmware) + +Firmware (debugger "park loop") for the on-chip debugger. This folder is just for documenting the source code. +Modifying the sources is not recommended as this could break the on-chip debugger. + + +## [openocd](openocd) + +Configuration file for openOCD to connect to the NEORV32 on-chip debugger via JTAG. + + +## [svd](svd) + +Contains a CMSIS-SVD compatible system view description file including _all_ peripherals. diff --git a/Libs/RiscV/NEORV32/sw/bootloader/makefile b/Libs/RiscV/NEORV32/sw/bootloader/makefile new file mode 100644 index 0000000..b34ab61 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/bootloader/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/common/common.mk b/Libs/RiscV/NEORV32/sw/common/common.mk new file mode 100644 index 0000000..074a92f --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/common/common.mk @@ -0,0 +1,368 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# ----------------------------------------------------------------------------- +# USER CONFIGURATION +# ----------------------------------------------------------------------------- +# User's application sources (*.c, *.cpp, *.s, *.S); add additional files here +APP_SRC ?= $(wildcard ./*.c) $(wildcard ./*.s) $(wildcard ./*.cpp) $(wildcard ./*.S) + +# User's application include folders (don't forget the '-I' before each entry) +APP_INC ?= -I . +# User's application include folders - for assembly files only (don't forget the '-I' before each entry) +ASM_INC ?= -I . + +# Optimization +EFFORT ?= -Os + +# Compiler toolchain +RISCV_PREFIX ?= riscv32-unknown-elf- + +# CPU architecture and ABI +MARCH ?= rv32i +MABI ?= ilp32 + +# User flags for additional configuration (will be added to compiler flags) +USER_FLAGS ?= + +# Relative or absolute path to the NEORV32 home folder +NEORV32_HOME ?= ../../.. +NEORV32_LOCAL_RTL ?= $(NEORV32_HOME)/rtl + +# ----------------------------------------------------------------------------- +# NEORV32 framework +# ----------------------------------------------------------------------------- +# Path to NEORV32 linker script and startup file +NEORV32_COM_PATH = $(NEORV32_HOME)/sw/common +# Path to main NEORV32 library include files +NEORV32_INC_PATH = $(NEORV32_HOME)/sw/lib/include +# Path to main NEORV32 library source files +NEORV32_SRC_PATH = $(NEORV32_HOME)/sw/lib/source +# Path to NEORV32 executable generator +NEORV32_EXG_PATH = $(NEORV32_HOME)/sw/image_gen +# Path to NEORV32 core rtl folder +NEORV32_RTL_PATH = $(NEORV32_LOCAL_RTL)/core +# Path to NEORV32 sim folder +NEORV32_SIM_PATH = $(NEORV32_HOME)/sim +# Marker file to check for NEORV32 home folder +NEORV32_HOME_MARKER = $(NEORV32_INC_PATH)/neorv32.h + +# Core libraries (peripheral and CPU drivers) +CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) +# Application start-up code +CORE_SRC += $(NEORV32_COM_PATH)/crt0.S + +# Linker script +LD_SCRIPT = $(NEORV32_COM_PATH)/neorv32.ld + +# Main output files +APP_EXE = neorv32_exe.bin +APP_HEX = neorv32_exe.hex +APP_ASM = main.asm +APP_IMG = neorv32_application_image.vhd +BOOT_IMG = neorv32_bootloader_image.vhd + + +# ----------------------------------------------------------------------------- +# Sources and objects +# ----------------------------------------------------------------------------- +# Define all sources +SRC = $(APP_SRC) +SRC += $(CORE_SRC) + +# Define all object files +OBJ = $(SRC:%=%.o) + + +# ----------------------------------------------------------------------------- +# Tools and flags +# ----------------------------------------------------------------------------- +# Compiler tools +CC = $(RISCV_PREFIX)gcc +OBJDUMP = $(RISCV_PREFIX)objdump +OBJCOPY = $(RISCV_PREFIX)objcopy +SIZE = $(RISCV_PREFIX)size + +# Host native compiler +CC_X86 = g++ -Wall -O -g + +# NEORV32 executable image generator +IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen + +# Compiler & linker flags +CC_OPTS = -march=$(MARCH) -mabi=$(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv +CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc +# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) +CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 +CC_OPTS += $(USER_FLAGS) + + +# ----------------------------------------------------------------------------- +# Application output definitions +# ----------------------------------------------------------------------------- +.PHONY: check info help elf_info clean clean_all bootloader +.DEFAULT_GOAL := help + +# 'compile' is still here for compatibility +exe: $(APP_ASM) $(APP_EXE) +hex: $(APP_ASM) $(APP_HEX) +compile: $(APP_ASM) $(APP_EXE) +image: $(APP_ASM) $(APP_IMG) +install: image install-$(APP_IMG) +all: $(APP_ASM) $(APP_EXE) $(APP_IMG) $(APP_HEX) install + +# Check if making bootloader +# Use different base address and length for instruction memory/"rom" (BOOTROM instead of IMEM) +# Also define "make_bootloader" symbol for crt0.S +target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader +target bl_image: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader + + +# ----------------------------------------------------------------------------- +# Image generator targets +# ----------------------------------------------------------------------------- +# install/compile tools +$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.c + @echo Compiling $(IMAGE_GEN) + @$(CC_X86) $< -o $(IMAGE_GEN) + + +# ----------------------------------------------------------------------------- +# General targets: Assemble, compile, link, dump +# ----------------------------------------------------------------------------- +# Compile app *.s sources (assembly) +%.s.o: %.s + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ + +# Compile app *.S sources (assembly + C pre-processor) +%.S.o: %.S + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ + +# Compile app *.c sources +%.c.o: %.c + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ + +# Compile app *.cpp sources +%.cpp.o: %.cpp + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ + +# Link object files and show memory utilization +main.elf: $(OBJ) + @$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm + @echo "Memory utilization:" + @$(SIZE) main.elf + +# Assembly listing file (for debugging) +$(APP_ASM): main.elf + @$(OBJDUMP) -d -S -z $< > $@ + +# Generate final executable from .text + .rodata + .data (in THIS order!) +main.bin: main.elf $(APP_ASM) + @$(OBJCOPY) -I elf32-little $< -j .text -O binary text.bin + @$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.bin + @$(OBJCOPY) -I elf32-little $< -j .data -O binary data.bin + @cat text.bin rodata.bin data.bin > $@ + @rm -f text.bin rodata.bin data.bin + + +# ----------------------------------------------------------------------------- +# Application targets: Generate binary executable, install (as VHDL file) +# ----------------------------------------------------------------------------- +# Generate NEORV32 executable image for upload via bootloader +$(APP_EXE): main.bin $(IMAGE_GEN) + @set -e + @$(IMAGE_GEN) -app_bin $< $@ $(shell basename $(CURDIR)) + @echo "Executable ($(APP_EXE)) size in bytes:" + @wc -c < $(APP_EXE) + +# Generate NEORV32 executable VHDL boot image +$(APP_IMG): main.bin $(IMAGE_GEN) + @set -e + @$(IMAGE_GEN) -app_img $< $@ $(shell basename $(CURDIR)) + +install-$(APP_IMG): $(APP_IMG) + @set -e + @echo "Installing application image to $(NEORV32_RTL_PATH)/$(APP_IMG)" + @cp $(APP_IMG) $(NEORV32_RTL_PATH)/. + +# Generate NEORV32 executable image in plain hex format +$(APP_HEX): main.bin $(IMAGE_GEN) + @set -e + @$(IMAGE_GEN) -app_hex $< $@ $(shell basename $(CURDIR)) + + +# ----------------------------------------------------------------------------- +# Bootloader targets +# ----------------------------------------------------------------------------- +# Create and install bootloader VHDL init image +$(BOOT_IMG): main.bin $(IMAGE_GEN) + @set -e + @$(IMAGE_GEN) -bld_img $< $(BOOT_IMG) $(shell basename $(CURDIR)) + +install-$(BOOT_IMG): $(BOOT_IMG) + @set -e + @echo "Installing bootloader image to $(NEORV32_RTL_PATH)/$(BOOT_IMG)" + @cp $(BOOT_IMG) $(NEORV32_RTL_PATH)/. + +# Just an alias +bl_image: $(BOOT_IMG) +bootloader: bl_image install-$(BOOT_IMG) + + +# ----------------------------------------------------------------------------- +# Check toolchain +# ----------------------------------------------------------------------------- +check: $(IMAGE_GEN) + @echo "---------------- Check: NEORV32_HOME folder ----------------" +ifneq ($(shell [ -e $(NEORV32_HOME_MARKER) ] && echo 1 || echo 0 ), 1) +$(error NEORV32_HOME folder not found!) +endif + @echo "NEORV32_HOME: $(NEORV32_HOME)" + @echo "---------------- Check: $(CC) ----------------" + @$(CC) -v + @echo "---------------- Check: $(OBJDUMP) ----------------" + @$(OBJDUMP) -V + @echo "---------------- Check: $(OBJCOPY) ----------------" + @$(OBJCOPY) -V + @echo "---------------- Check: $(SIZE) ----------------" + @$(SIZE) -V + @echo "---------------- Check: NEORV32 image_gen ----------------" + @$(IMAGE_GEN) -help + @echo "---------------- Check: Native GCC ----------------" + @$(CC_X86) -v + @echo + @echo "Toolchain check OK" + + +# ----------------------------------------------------------------------------- +# Show configuration +# ----------------------------------------------------------------------------- +info: + @echo "---------------- Info: Project ----------------" + @echo "Project folder: $(shell basename $(CURDIR))" + @echo "Source files: $(APP_SRC)" + @echo "Include folder(s): $(APP_INC)" + @echo "ASM include folder(s): $(ASM_INC)" + @echo "---------------- Info: NEORV32 ----------------" + @echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" + @echo "IMAGE_GEN: $(IMAGE_GEN)" + @echo "Core source files:" + @echo "$(CORE_SRC)" + @echo "Core include folder:" + @echo "$(NEORV32_INC_PATH)" + @echo "---------------- Info: Objects ----------------" + @echo "Project object files:" + @echo "$(OBJ)" + @echo "---------------- Info: RISC-V CPU ----------------" + @echo "MARCH: $(MARCH)" + @echo "MABI: $(MABI)" + @echo "---------------- Info: Toolchain ----------------" + @echo "Toolchain: $(RISCV_TOLLCHAIN)" + @echo "CC: $(CC)" + @echo "OBJDUMP: $(OBJDUMP)" + @echo "OBJCOPY: $(OBJCOPY)" + @echo "SIZE: $(SIZE)" + @echo "---------------- Info: Compiler Configuration ----------------" + @$(CC) -v + @echo "---------------- Info: Compiler Libraries ----------------" + @echo "LIBGCC:" + @$(CC) -print-libgcc-file-name + @echo "SEARCH-DIRS:" + @$(CC) -print-search-dirs + @echo "---------------- Info: Flags ----------------" + @echo "USER_FLAGS: $(USER_FLAGS)" + @echo "CC_OPTS: $(CC_OPTS)" + @echo "---------------- Info: Host Native GCC Flags ----------------" + @echo "CC_X86: $(CC_X86)" + + +# ----------------------------------------------------------------------------- +# In-console simulation using default/simple testbench and GHDL +# ----------------------------------------------------------------------------- +sim: $(APP_IMG) install + @echo "Simulating $(APP_IMG)..." + @sh $(NEORV32_SIM_PATH)/simple/ghdl.sh + +# ----------------------------------------------------------------------------- +# Show final ELF details (just for debugging) +# ----------------------------------------------------------------------------- +elf_info: main.elf + @$(OBJDUMP) -x main.elf + + +# ----------------------------------------------------------------------------- +# Help +# ----------------------------------------------------------------------------- +help: + @echo "<<< NEORV32 SW Application Makefile >>>" + @echo "Make sure to add the bin folder of RISC-V GCC to your PATH variable." + @echo "" + @echo "== Targets ==" + @echo " help - show this text" + @echo " check - check toolchain" + @echo " info - show makefile/toolchain configuration" + @echo " exe - compile and generate executable for upload via bootloader" + @echo " hex - compile and generate executable raw file" + @echo " image - compile and generate VHDL IMEM boot image (for application) in local folder" + @echo " install - compile, generate and install VHDL IMEM boot image (for application)" + @echo " sim - in-console simulation using default/simple testbench and GHDL" + @echo " all - exe + hex + install" + @echo " elf_info - show ELF layout info" + @echo " clean - clean up project" + @echo " clean_all - clean up project, core libraries and image generator" + @echo " bl_image - compile and generate VHDL BOOTROM boot image (for bootloader only!) in local folder" + @echo " bootloader - compile, generate and install VHDL BOOTROM boot image (for bootloader only!)" + @echo "" + @echo "== Variables ==" + @echo " USER_FLAGS - Custom toolchain flags [append only], default \"$(USER_FLAGS)\"" + @echo " EFFORT - Optimization level, default \"$(EFFORT)\"" + @echo " MARCH - Machine architecture, default \"$(MARCH)\"" + @echo " MABI - Machine binary interface, default \"$(MABI)\"" + @echo " APP_INC - C include folder(s) [append only], default \"$(APP_INC)\"" + @echo " ASM_INC - ASM include folder(s) [append only], default \"$(ASM_INC)\"" + @echo " RISCV_PREFIX - Toolchain prefix, default \"$(RISCV_PREFIX)\"" + @echo " NEORV32_HOME - NEORV32 home folder, default \"$(NEORV32_HOME)\"" + @echo "" + + +# ----------------------------------------------------------------------------- +# Clean up +# ----------------------------------------------------------------------------- +clean: + @rm -f *.elf *.o *.bin *.out *.asm *.vhd *.hex + +clean_all: clean + @rm -f $(OBJ) $(IMAGE_GEN) diff --git a/Libs/RiscV/NEORV32/sw/common/crt0.S b/Libs/RiscV/NEORV32/sw/common/crt0.S new file mode 100644 index 0000000..1c65664 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/common/crt0.S @@ -0,0 +1,261 @@ +/* ################################################################################################# */ +/* # << NEORV32 - crt0.S - Start-Up Code >> # */ +/* # ********************************************************************************************* # */ +/* # BSD 3-Clause License # */ +/* # # */ +/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */ +/* # # */ +/* # Redistribution and use in source and binary forms, with or without modification, are # */ +/* # permitted provided that the following conditions are met: # */ +/* # # */ +/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */ +/* # conditions and the following disclaimer. # */ +/* # # */ +/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */ +/* # conditions and the following disclaimer in the documentation and/or other materials # */ +/* # provided with the distribution. # */ +/* # # */ +/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */ +/* # endorse or promote products derived from this software without specific prior written # */ +/* # permission. # */ +/* # # */ +/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */ +/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */ +/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */ +/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */ +/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */ +/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */ +/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */ +/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */ +/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */ +/* # ********************************************************************************************* # */ +/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */ +/* ################################################################################################# */ + +.file "crt0.S" +.section .text.boot +.balign 4 +.global _start + + +_start: +.cfi_startproc +.cfi_undefined ra + + +// ************************************************************************************************ +// This is the very first instruction that is executed after hardware reset. It ensures that x0 is +// written at least once - the CPU HW will ensure it is always set to zero on any write access. +// ************************************************************************************************ + lui zero, 0 // "dummy" instruction that uses no reg-file input operands at all + + +// ************************************************************************************************ +// Setup pointers using linker script symbols +// ************************************************************************************************ +__crt0_pointer_init: + .option push + .option norelax + + la sp, __crt0_stack_begin // stack pointer + la gp, __global_pointer$ // global pointer + + .option pop + + +// ************************************************************************************************ +// Setup CPU core CSRs (some of them DO NOT have a dedicated +// reset and need to be explicitly initialized) +// ************************************************************************************************ +__crt0_cpu_csr_init: + + la x10, __crt0_dummy_trap_handler // configure early trap handler + csrw mtvec, x10 + csrw mepc, x10 // just to init mepc + + csrw mstatus, zero // disable global IRQ + + csrw mie, zero // absolutely no interrupts sources, thanks + + csrw mcounteren, zero // no access from less-privileged modes to counter CSRs + + li x11, ~5 // stop all counters except for [m]cycle[h] and [m]instret[h] + csrw 0x320, x11 // = mcountinhibit (literal address for lagacy toolchain compatibility) + + csrw mcycle, zero // reset cycle counters + csrw mcycleh, zero + csrw minstret, zero // reset instruction counters + csrw minstreth, zero + + +// ************************************************************************************************ +// Initialize integer register file (lower half) +// ************************************************************************************************ +__crt0_reg_file_clear: +//addi x0, x0, 0 // hardwired to zero + addi x1, x0, 0 +//addi x2, x0, 0 // stack pointer sp +//addi x3, x0, 0 // global pointer gp + addi x4, x0, 0 + addi x5, x0, 0 + addi x6, x0, 0 + addi x7, x0, 0 +//addi x8, x0, 0 // implicitly initialized within crt0 +//addi x9, x0, 0 // implicitly initialized within crt0 +//addi x10, x0, 0 // implicitly initialized within crt0 +//addi x11, x0, 0 // implicitly initialized within crt0 +//addi x12, x0, 0 // implicitly initialized within crt0 +//addi x13, x0, 0 // implicitly initialized within crt0 + addi x14, x0, 0 + addi x15, x0, 0 + + +// ************************************************************************************************ +// Initialize integer register file (upper half, if no E extension) +// ************************************************************************************************ +#ifndef __riscv_32e +// do not do this if compiling bootloader (to save some program space) +#ifndef make_bootloader + addi x16, x0, 0 + addi x17, x0, 0 + addi x18, x0, 0 + addi x19, x0, 0 + addi x20, x0, 0 + addi x21, x0, 0 + addi x22, x0, 0 + addi x23, x0, 0 + addi x24, x0, 0 + addi x25, x0, 0 + addi x26, x0, 0 + addi x27, x0, 0 + addi x28, x0, 0 + addi x29, x0, 0 + addi x30, x0, 0 + addi x31, x0, 0 +#endif +#endif + + +// ************************************************************************************************ +// Reset/deactivate IO/peripheral devices +// Devices, that are not implemented, will cause a store bus access fault +// which is captured (but actually ignored) by the dummy trap handler. +// ************************************************************************************************ +__crt0_reset_io: + la x8, __ctr0_io_space_begin // start of processor-internal IO region + la x9, __ctr0_io_space_end // end of processor-internal IO region + +__crt0_reset_io_loop: + sw zero, 0(x8) + addi x8, x8, 4 + bne x8, x9, __crt0_reset_io_loop + + +// ************************************************************************************************ +// Clear .bss section (byte-wise) using linker script symbols +// ************************************************************************************************ +__crt0_clear_bss: + la x11, __crt0_bss_start + la x12, __crt0_bss_end + +__crt0_clear_bss_loop: + bge x11, x12, __crt0_clear_bss_loop_end + sb zero, 0(x11) + addi x11, x11, 1 + j __crt0_clear_bss_loop + +__crt0_clear_bss_loop_end: + + +// ************************************************************************************************ +// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols +// ************************************************************************************************ +__crt0_copy_data: + la x11, __crt0_copy_data_src_begin // start of data area (copy source) + la x12, __crt0_copy_data_dst_begin // start of data area (copy destination) + la x13, __crt0_copy_data_dst_end // last address of destination data area + +__crt0_copy_data_loop: + bge x12, x13, __crt0_copy_data_loop_end + lb x14, 0(x11) + sb x14, 0(x12) + addi x11, x11, 1 + addi x12, x12, 1 + j __crt0_copy_data_loop + +__crt0_copy_data_loop_end: + + +// ************************************************************************************************ +// Setup arguments and call main function +// ************************************************************************************************ +__crt0_main_entry: + addi x10, zero, 0 // a0 = argc = 0 + addi x11, zero, 0 // a1 = argv = 0 + jal ra, main // call actual app's main function, this "should" not return + + +// ************************************************************************************************ +// call "after main" handler (if there is any) if main really returns +// ************************************************************************************************ +__crt0_main_aftermath: + csrw mscratch, a0 // copy main's return code in mscratch for debugger + +#ifndef make_bootloader // after_main handler not supported for bootloader + .weak __neorv32_crt0_after_main + la ra, __neorv32_crt0_after_main + beqz ra, __crt0_main_aftermath_end // check if an aftermath handler has been specified + jalr ra // execute handler, main's return code in a0 +#endif + + +// ************************************************************************************************ +// go to endless sleep mode +// ************************************************************************************************ +__crt0_main_aftermath_end: + csrci mstatus, 8 // mstatus: disable global IRQs (mstatus.mie) +__crt0_main_aftermath_end_loop: + wfi // try to go to sleep mode + j __crt0_main_aftermath_end_loop // endless loop + + +// ************************************************************************************************ +// dummy trap handler (for exceptions & IRQs during very early boot stage) +// does nothing but tries to move on to next instruction +// ************************************************************************************************ +.balign 4 +__crt0_dummy_trap_handler: + + addi sp, sp, -8 + sw x8, 0(sp) + sw x9, 4(sp) + + csrr x8, mcause + blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt + + csrr x8, mepc + +__crt0_dummy_trap_handler_exc_c_check: // is compressed instruction? + lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception + andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions) + + addi x8, x8, +2 // only this for compressed instructions + csrw mepc, x8 // set return address when compressed instruction + + addi x8, zero, 3 + bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction + +__crt0_dummy_trap_handler_exc_uncrompressed: // is uncompressed instruction! + csrr x8, mepc + addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions + csrw mepc, x8 + +__crt0_dummy_trap_handler_irq: + lw x8, 0(sp) + lw x9, 4(sp) + addi sp, sp, +8 + + mret + +.cfi_endproc +.end diff --git a/Libs/RiscV/NEORV32/sw/common/neorv32.ld b/Libs/RiscV/NEORV32/sw/common/neorv32.ld new file mode 100644 index 0000000..ed20dcd --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/common/neorv32.ld @@ -0,0 +1,309 @@ +/* ################################################################################################# */ +/* # << NEORV32 - RISC-V GCC Linker Script >> # */ +/* # ********************************************************************************************* # */ +/* # BSD 3-Clause License # */ +/* # # */ +/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */ +/* # # */ +/* # Redistribution and use in source and binary forms, with or without modification, are # */ +/* # permitted provided that the following conditions are met: # */ +/* # # */ +/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */ +/* # conditions and the following disclaimer. # */ +/* # # */ +/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */ +/* # conditions and the following disclaimer in the documentation and/or other materials # */ +/* # provided with the distribution. # */ +/* # # */ +/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */ +/* # endorse or promote products derived from this software without specific prior written # */ +/* # permission. # */ +/* # # */ +/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */ +/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */ +/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */ +/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */ +/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */ +/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */ +/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */ +/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */ +/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */ +/* # ********************************************************************************************* # */ +/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */ +/* ################################################################################################# */ + +/* Default linker script, for normal executables */ +/* Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copying and distribution of this script, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. */ + +/* modified for the NEORV32 processor by Stephan Nolting */ + + +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(_start) +SEARCH_DIR("/opt/riscv/riscv32-unknown-elf/lib"); SEARCH_DIR("=/opt/riscv/riscv64-unknown-linux-gnu/lib"); SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib"); + +/* ************************************************************************** */ +/* NEORV32 memory section configuration. */ +/* ************************************************************************** */ +/* "ram" : data memory (int/ext DMEM) - make sure this is sync with the HW! */ +/* "rom" : instruction memory (int/ext IMEM or bootloader ROM) */ +/* "iodev" : peripheral/IO devices */ +/* ************************************************************************** */ +MEMORY +{ +/* section base addresses and sizes have to be a multiple of 4 bytes */ +/* ram section: first value of LENGTH => data memory used by bootloader (fixed!); second value of LENGTH => *physical* size of data memory */ +/* adapt the right-most value to match the *total physical data memory size* of your setup */ + + ram (rwx) : ORIGIN = 0x80000000, LENGTH = DEFINED(make_bootloader) ? 512 : 8*1024 + +/* rom and iodev sections should NOT be modified by the user at all! */ +/* rom section: first value of ORIGIN/LENGTH => bootloader ROM; second value of ORIGIN/LENGTH => maximum *logical* size of instruction memory */ + + rom (rx) : ORIGIN = DEFINED(make_bootloader) ? 0xFFFF0000 : 0x00000000, LENGTH = DEFINED(make_bootloader) ? 32K : 2048M + iodev (rw) : ORIGIN = 0xFFFFFE00, LENGTH = 512 + +} +/* ************************************************************************* */ + +SECTIONS +{ + /* start section on WORD boundary */ + . = ALIGN(4); + + + /* Actual instructions */ + .text : + { + PROVIDE(__text_start = .); + PROVIDE(__textstart = .); + + PROVIDE_HIDDEN (__rela_iplt_start = .); + *(.rela.iplt) + PROVIDE_HIDDEN (__rela_iplt_end = .); + + *(.rela.plt) + + KEEP(*(.text.boot)); /* keep start-up code at the beginning of rom */ + + KEEP (*(SORT_NONE(.init))) + + *(.text.unlikely .text.*_unlikely .text.unlikely.*) + *(.text.exit .text.exit.*) + *(.text.startup .text.startup.*) + *(.text.hot .text.hot.*) + *(SORT(.text.sorted.*)) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf.em. */ + *(.gnu.warning) + + KEEP (*(SORT_NONE(.fini))) + + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* finish section on WORD boundary */ + . = ALIGN(4); + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > rom + + + /* read-only data, appended to .text */ + .rodata : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + + /* finish section on WORD boundary */ + . = ALIGN(4); + } > rom + + + /* initialized read/write data, accessed in RAM, placed in ROM, copied during boot */ + .data : + { + __DATA_BEGIN__ = .; + __SDATA_BEGIN__ = .; + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + *(.data1) + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + + *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) + *(.dynamic) + + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + + PROVIDE_HIDDEN (__tdata_start = .); + *(.tdata .tdata.* .gnu.linkonce.td.*) + + + /* finish section on WORD boundary */ + . = ALIGN(4); + + _edata = .; PROVIDE (edata = .); + . = .; + + } > ram AT > rom + + + /* zero/non-initialized read/write data placed in RAM */ + .bss (NOLOAD): + { + __bss_start = .; + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + *(.scommon) + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. + FIXME: Why do we need it? When there is no .bss section, we do not + pad the .data section. */ + . = ALIGN(. != 0 ? 32 / 8 : 1); + + . = ALIGN(32 / 8); + __BSS_END__ = .; + __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); + _end = .; PROVIDE (end = .); + } > ram + + + /* Yet unused */ + .jcr : { KEEP (*(.jcr)) } + .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } .interp : { *(.interp) } + .note.gnu.build-id : { *(.note.gnu.build-id) } + .hash : { *(.hash) } + .gnu.hash : { *(.gnu.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rela.init : { *(.rela.init) } + .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } + .rela.fini : { *(.rela.fini) } + .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) } + .rela.data.rel.ro : { *(.rela.data.rel.ro .rela.data.rel.ro.* .rela.gnu.linkonce.d.rel.ro.*) } + .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) } + .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) } + .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } + .rela.ctors : { *(.rela.ctors) } + .rela.dtors : { *(.rela.dtors) } + .rela.got : { *(.rela.got) } + .rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) } + .rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) } + .rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) } + .rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) } + .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) } + + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + .debug_addr 0 : { *(.debug_addr) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } + + + /* Provide symbols for neorv32 crt0 start-up code */ + PROVIDE(__ctr0_imem_begin = ORIGIN(rom)); + PROVIDE(__ctr0_dmem_begin = ORIGIN(ram)); + PROVIDE(__crt0_stack_begin = (ORIGIN(ram) + LENGTH(ram)) - 4); + PROVIDE(__crt0_bss_start = __bss_start); + PROVIDE(__crt0_bss_end = __BSS_END__); + PROVIDE(__crt0_copy_data_src_begin = __etext + SIZEOF(.rodata)); + PROVIDE(__crt0_copy_data_dst_begin = __DATA_BEGIN__); + PROVIDE(__crt0_copy_data_dst_end = __DATA_BEGIN__ + SIZEOF(.data)); + PROVIDE(__ctr0_io_space_begin = ORIGIN(iodev)); + PROVIDE(__ctr0_io_space_end = ORIGIN(iodev) + LENGTH(iodev)); +} diff --git a/Libs/RiscV/NEORV32/sw/example/bitmanip_test/README.md b/Libs/RiscV/NEORV32/sw/example/bitmanip_test/README.md new file mode 100644 index 0000000..7e9dae0 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/bitmanip_test/README.md @@ -0,0 +1,13 @@ +# NEORV32 Bit-Manipulation `B` Extension + +:warning: The RISC-V bit-manipulation extension is frozen but not yet officially ratified. + +:warning: The NEORV32 bit manipulation extensions `B` only supports the `Zbb` and `Zba` sub-extension +(basic bit-manipulation operation) yet. + +The provided test program `main.c` verifies all currently implemented instruction by checking the results against a pure-software emulation model. +The emulation functions as well as the available **intrinsics** for the sub-extension are located in `neorv32_b_extension_intrinsics.h`. + +:information_source: More information regarding the RISC-V bit manipulation extension can be found in the officail GitHub repo: +[github.com/riscv/riscv-bitmanip](https://github.com/riscv/riscv-bitmanip). +The specification of the bit-manipulation spec supported by the NEORV32 can be found in `docs/references/bitmanip-draft.pdf`. diff --git a/Libs/RiscV/NEORV32/sw/example/bitmanip_test/makefile b/Libs/RiscV/NEORV32/sw/example/bitmanip_test/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/bitmanip_test/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/bitmanip_test/neorv32_b_extension_intrinsics.h b/Libs/RiscV/NEORV32/sw/example/bitmanip_test/neorv32_b_extension_intrinsics.h new file mode 100644 index 0000000..2ae53eb --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/bitmanip_test/neorv32_b_extension_intrinsics.h @@ -0,0 +1,903 @@ +// ################################################################################################# +// # << NEORV32 - Intrinsics + Emulation Functions for the CPU B extension >> # +// # ********************************************************************************************* # +// # The intrinsics provided by this library allow to use the hardware bit manipulation unit of # +// # the RISC-V B CPU extension without the need for support by the compiler. # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file bitmanip_test/neorv32_b_extension_intrinsics.h + * @author Stephan Nolting + * @brief "Intrinsic" library for the NEORV32 bit manipulation B extension. + * Also provides emulation functions for all intrinsics (functionality re-built in pure software). + * + * @warning This library is just a temporary fall-back until the B extension is supported by the upstream RISC-V GCC port. + **************************************************************************/ + +#ifndef neorv32_b_extension_intrinsics_h +#define neorv32_b_extension_intrinsics_h + + +// ################################################################################################ +// "Intrinsics" +// ################################################################################################ + + +// ================================================================================================ +// Zbb - Base instructions +// ================================================================================================ + +/**********************************************************************//** + * Intrinsic: Bit manipulation CLZ (count leading zeros) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Number of leading zeros in source operand. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_clz(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // clz a0, a0 + CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00000, a0, 0b001, a0, 0b0010011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation CTZ (count trailing zeros) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Number of trailing zeros in source operand. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_ctz(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // ctz a0, a0 + CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00001, a0, 0b001, a0, 0b0010011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation CPOP (count set bits) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Number of set bits in source operand. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_cpop(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // cpop a0, a0 + CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00010, a0, 0b001, a0, 0b0010011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation SEXT.B (sign-extend byte) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Sign extended byte (operand(7:0)). + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sextb(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // sext.b a0, a0 + CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00100, a0, 0b001, a0, 0b0010011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation SEXT.H (sign-extend half-word) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Sign-extended half-word (operand(15:0)). + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sexth(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // sext.h a0, a0 + CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00101, a0, 0b001, a0, 0b0010011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ZEXT.H (zero-extend half-word) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Zero-extended half-word (operand(15:0)). + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_zexth(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // sext.h a0, a0 + CUSTOM_INSTR_R1_TYPE(0b0000100, 0b00000, a0, 0b100, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MIN (select signed minimum) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Signed minimum. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_min(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // min a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b100, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MINU (select unsigned minimum) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Unsigned minimum. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_minu(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // minu a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b101, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MAX (select signed maximum) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Signed maximum. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_max(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // max a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b110, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MAXU (select unsigned maximum) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Unsigned maximum. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_maxu(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // maxu a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b111, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ANDN (logical and-negate) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 1 AND NOT operand 2. + **************************************************************************/ +inline inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_andn(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // andn a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b111, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ORN (logical or-negate) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 1 OR NOT operand 2. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_orn(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // orn a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b110, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation XNOR (logical xor-negate) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 1 XOR NOT operand 2. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_xnor(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // xnor a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b100, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ROL (rotate-left) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 1 rotated left by operand_2(4:0) positions. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rol(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // rol a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0110000, a1, a0, 0b001, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ROR (rotate-right) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 1 rotated right by operand_2(4:0) positions. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_ror(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // ror a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0110000, a1, a0, 0b101, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation RORI (rotate-right) by 20 positions. [B.Zbb] + * @warning Fixed shift amount (20) for now. + * + * @param[in] rs1 Source operand 1 (a0). + * @return Operand 1 rotated right by 20 positions. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rori20(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // rori a0, a0, 20 + CUSTOM_INSTR_R1_TYPE(0b0110000, 0b10100, a0, 0b101, a0, 0b0010011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ORC.B (or-combine byte) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return OR-combined bytes of operand 1. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_orcb(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // gorci a0, a0, 7 (pseudo-instruction: orc.b a0, a0) + CUSTOM_INSTR_R1_TYPE(0b0010100, 0b00111, a0, 0b101, a0, 0b0010011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation REV8 (byte-swap) [B.Zbb] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Byte swap of operand 1 + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_rev8(uint32_t rs1) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // grevi a0, a0, -8 (pseudo-instruction: rev8 a0, a0) + CUSTOM_INSTR_R1_TYPE(0b0110100, 0b11000, a0, 0b101, a0, 0b0010011); + + return result; +} + + +// ================================================================================================ +// Zbb - Base instructions +// ================================================================================================ + +/**********************************************************************//** + * Intrinsic: Address generation instructions SH1ADD (add with logical-1-shift) [B.Zba] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 2 + (Operand 1 << 1) + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh1add(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // sh1add a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b0110011); + + return result; +} + + +/**********************************************************************//** + * Intrinsic: Address generation instructions SH2ADD (add with logical-2-shift) [B.Zba] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 2 + (Operand 1 << 2) + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh2add(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // sh2add a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b100, a0, 0b0110011); + + return result; +} + +/**********************************************************************//** + * Intrinsic: Address generation instructions SH1ADD (add with logical-3-shift) [B.Zba] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a0). + * @return Operand 2 + (Operand 1 << 3) + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_sh3add(uint32_t rs1, uint32_t rs2) { + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + register uint32_t tmp_b __asm__ ("a1") = rs2; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // sh3add a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b110, a0, 0b0110011); + + return result; +} + + + +// ################################################################################################ +// Emulation functions +// ################################################################################################ + + +// ================================================================================================ +// Zbb - Base instructions +// ================================================================================================ + + +/**********************************************************************//** + * Intrinsic: Bit manipulation CLZ (count leading zeros) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Number of leading zeros in source operand. + **************************************************************************/ +uint32_t riscv_emulate_clz(uint32_t rs1) { + + uint32_t sreg = rs1; + uint32_t cnt = 0; + + while(1) { + if (sreg & 0x80000000UL) { + break; + } + else { + sreg <<= 1; + cnt++; + } + } + + return cnt; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation CTZ (count trailing zeros) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Number of trailing zeros in source operand. + **************************************************************************/ +uint32_t riscv_emulate_ctz(uint32_t rs1) { + + uint32_t sreg = rs1; + uint32_t cnt = 0; + + while(1) { + if (sreg & 1) { + break; + } + else { + sreg >>= 1; + cnt++; + } + } + + return cnt; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation CPOP (population count) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Number of set bits in source operand. + **************************************************************************/ +uint32_t riscv_emulate_cpop(uint32_t rs1) { + + uint32_t sreg = rs1; + uint32_t cnt = 0; + int i; + + for (i=0; i<32; i++) { + if (sreg & 1) { + cnt++; + } + sreg >>= 1; + } + + return cnt; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation SEXT.B (sign-extend byte) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Sign-extended byte (operand(7:0)). + **************************************************************************/ +uint32_t riscv_emulate_sextb(uint32_t rs1) { + + uint32_t tmp = rs1 & 0xff; + + if (tmp & 0x80) { + tmp |= 0xFFFFFF00UL; + } + + return tmp; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation SEXT.H (sign-extend half-word) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Sign-extended half-word (operand(15:0)). + **************************************************************************/ +uint32_t riscv_emulate_sexth(uint32_t rs1) { + + uint32_t tmp = rs1 & 0xffff; + + if (tmp & 0x8000) { + tmp |= 0xFFFF0000UL; + } + + return tmp; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ZEXT.H (zero-extend half-word) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Zero-extended half-word (operand(15:0)). + **************************************************************************/ +uint32_t riscv_emulate_zexth(uint32_t rs1) { + + return rs1 & 0x0000FFFFUL; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MIN (select signed minimum) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Signed minimum. + **************************************************************************/ +uint32_t riscv_emulate_min(uint32_t rs1, uint32_t rs2) { + + int32_t s_opa = (int32_t)rs1; + int32_t s_opb = (int32_t)rs2; + + if (s_opa < s_opb) { + return rs1; + } + else { + return rs2; + } +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MINU (select unsigned minimum) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Unsigned minimum. + **************************************************************************/ +uint32_t riscv_emulate_minu(uint32_t rs1, uint32_t rs2) { + + if (rs1 < rs2) { + return rs1; + } + else { + return rs2; + } +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MAX (select signed maximum) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Signed maximum. + **************************************************************************/ +uint32_t riscv_emulate_max(uint32_t rs1, uint32_t rs2) { + + int32_t s_opa = (int32_t)rs1; + int32_t s_opb = (int32_t)rs2; + + if (s_opa < s_opb) { + return rs2; + } + else { + return rs1; + } +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation MAXU (select unsigned maximum) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Unsigned maximum. + **************************************************************************/ +uint32_t riscv_emulate_maxu(uint32_t rs1, uint32_t rs2) { + + if (rs1 < rs2) { + return rs2; + } + else { + return rs1; + } +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ANDN (logical and-negate) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 1 AND NOT operand 2. + **************************************************************************/ +uint32_t riscv_emulate_andn(uint32_t rs1, uint32_t rs2) { + + return rs1 & (~rs2); +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ORN (logical or-negate) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 1 OR NOT operand 2. + **************************************************************************/ +uint32_t riscv_emulate_orn(uint32_t rs1, uint32_t rs2) { + + return rs1 | (~rs2); +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation XNOR (logical xor-negate) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 1 XOR NOT operand 2. + **************************************************************************/ +uint32_t riscv_emulate_xnor(uint32_t rs1, uint32_t rs2) { + + return rs1 ^ (~rs2); +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ROL (rotate-left) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 1 rotated left by operand_2(4:0) positions. + **************************************************************************/ +uint32_t riscv_emulate_rol(uint32_t rs1, uint32_t rs2) { + + uint32_t shamt = rs2 & 0x1f; + + uint32_t tmp_a = rs1 << shamt; + uint32_t tmp_b = rs1 >> (32-shamt); + + return tmp_a | tmp_b; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ROR (rotate-right) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 1 rotated right by operand_2(4:0) positions. + **************************************************************************/ +uint32_t riscv_emulate_ror(uint32_t rs1, uint32_t rs2) { + + uint32_t shamt = rs2 & 0x1f; + + uint32_t tmp_a = rs1 >> shamt; + uint32_t tmp_b = rs1 << (32-shamt); + + return tmp_a | tmp_b; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation REV8 (byte swap) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return Operand 1 byte swapped. + **************************************************************************/ +uint32_t riscv_emulate_rev8(uint32_t rs1) { + + uint32_t tmp_a = (rs1 & 0x000000ffUL) << 24; + uint32_t tmp_b = (rs1 & 0x0000ff00UL) << 8; + uint32_t tmp_c = (rs1 & 0x00ff0000UL) >> 8; + uint32_t tmp_d = (rs1 & 0xff000000UL) >> 24; + + return tmp_a | tmp_b | tmp_c | tmp_d; +} + + +/**********************************************************************//** + * Intrinsic: Bit manipulation ORCB (or-combine bytes) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @return OR-combined bytes of operand 1. + **************************************************************************/ +uint32_t riscv_emulate_orcb(uint32_t rs1) { + + uint32_t tmp = 0; + + if (rs1 & 0x000000ffUL) { + tmp |= 0x000000ffUL; + } + if (rs1 & 0x0000ff00UL) { + tmp |= 0x0000ff00UL; + } + if (rs1 & 0x00ff0000UL) { + tmp |= 0x00ff0000UL; + } + if (rs1 & 0xff000000UL) { + tmp |= 0xff000000UL; + } + + return tmp; +} + + +// ================================================================================================ +// Zba - Address generation instructions +// ================================================================================================ + + +/**********************************************************************//** + * Intrinsic: Address generation instructions SH1ADD (add with logical-1-shift) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 2 + (Operand 1 << 1) + **************************************************************************/ +uint32_t riscv_emulate_sh1add(uint32_t rs1, uint32_t rs2) { + + return rs2 + (rs1 << 1); +} + + +/**********************************************************************//** + * Intrinsic: Address generation instructions SH2ADD (add with logical-2-shift) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 2 + (Operand 1 << 2) + **************************************************************************/ +uint32_t riscv_emulate_sh2add(uint32_t rs1, uint32_t rs2) { + + return rs2 + (rs1 << 2); +} + + +/**********************************************************************//** + * Intrinsic: Address generation instructions SH3ADD (add with logical-3-shift) [emulation] + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 1 (a0). + * @return Operand 2 + (Operand 1 << 3) + **************************************************************************/ +uint32_t riscv_emulate_sh3add(uint32_t rs1, uint32_t rs2) { + + return rs2 + (rs1 << 3); +} + + +#endif // neorv32_b_extension_intrinsics_h diff --git a/Libs/RiscV/NEORV32/sw/example/blink_led/blink_led_in_asm.S b/Libs/RiscV/NEORV32/sw/example/blink_led/blink_led_in_asm.S new file mode 100644 index 0000000..072e7a1 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/blink_led/blink_led_in_asm.S @@ -0,0 +1,37 @@ +.file "blink_led_in_asm.S" +.section .text +.balign 4 +.global blink_led_asm + +blink_led_asm: + + /* base address of GPIO controller's output port is passed as argument (in a0)*/ + sw zero, 0(a0) /* clear output port */ + + li t1, 0 /* initialize counter */ + + +blink_loop: + andi t1, t1, 255 /* apply 8-bit mask */ + sw t1, 0(a0) /* output current counter value */ + addi t1, t1, 1 /* increment counter */ + + jal ra, blink_delay /* call delay function */ + + j blink_loop + + +blink_delay: + li t2, 0xfffff /* delay time */ + +blink_delay_loop: + beq t2, zero, blink_delay_end + addi t2, t2, -1 + nop + nop + j blink_delay_loop + +blink_delay_end: + ret + +.end diff --git a/Libs/RiscV/NEORV32/sw/example/blink_led/makefile b/Libs/RiscV/NEORV32/sw/example/blink_led/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/blink_led/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/bus_explorer/makefile b/Libs/RiscV/NEORV32/sw/example/bus_explorer/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/bus_explorer/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/coremark/LICENSE.md b/Libs/RiscV/NEORV32/sw/example/coremark/LICENSE.md new file mode 100644 index 0000000..14e53e9 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/coremark/LICENSE.md @@ -0,0 +1,100 @@ +# COREMARK® ACCEPTABLE USE AGREEMENT + +This ACCEPTABLE USE AGREEMENT (this “Agreementâ€) is offered by Embedded Microprocessor Benchmark Consortium, a California nonprofit corporation (“Licensorâ€), to users of its CoreMark® software (“Licenseeâ€) exclusively on the following terms. + +Licensor offers benchmarking software (“Softwareâ€) pursuant to an open source license, but carefully controls use of its benchmarks and their associated goodwill. Licensor has registered its trademark in one of the benchmarks available through the Software, COREMARK, Ser. No. 85/487,290; Reg. No. 4,179,307 (the “Trademarkâ€), and promotes the use of a standard metric as a benchmark for assessing the performance of embedded systems. Solely on the terms described herein, Licensee may use and display the Trademark in connection with the generation of data regarding measurement and analysis of computer and embedded system benchmarking via the Software (the “Licensed Useâ€). + +## Article 1 – License Grant. +1.1. License. Subject to the terms and conditions of this Agreement, Licensor hereby grants to Licensee, and Licensee hereby accepts from Licensor, a personal, non-exclusive, royalty-free, revocable right and license to use and display the Trademark during the term of this Agreement (the “Termâ€), solely and exclusively in connection with the Licensed Use. During the Term, Licensee (i) shall not modify or otherwise create derivative works of the Trademark, and (ii) may use the Trademark only to the extent permitted under this License. Neither Licensee nor any affiliate or agent thereof shall otherwise use the Trademark without the prior express written consent of Licensor, which may be withheld in its sole and absolute discretion. All rights not expressly granted to Licensee hereunder shall remain the exclusive property of Licensor. + +1.2. Modifications to the Software. Licensee shall not use the Trademark in connection with any use of a modified, derivative, or otherwise altered copy of the Software. + +1.3. Licensor’s Use. Nothing in this Agreement shall preclude Licensor or any of its successors or assigns from using or permitting other entities to use the Trademark, whether or not such entity directly or indirectly competes or conflicts with Licensee’s Licensed Use in any manner. + +1.4. Term and Termination. This Agreement is perpetual unless terminated by either of the parties. Licensee may terminate this Agreement for convenience, without cause or liability, for any reason or for no reason whatsoever, upon ten (10) business days written notice. Licensor may terminate this Agreement effective immediately upon notice of breach. Upon termination, Licensee shall immediately remove all implementations of the Trademark from the Licensed Use, and delete all digitals files and records of all materials related to the Trademark. + +## Article 2 – Ownership. +2.1. Ownership. Licensee acknowledges and agrees that Licensor is the owner of all right, title, and interest in and to the Trademark, and all such right, title, and interest shall remain with Licensor. Licensee shall not contest, dispute, challenge, oppose, or seek to cancel Licensor’s right, title, and interest in and to the Trademark. Licensee shall not prosecute any application for registration of the Trademark. Licensee shall display appropriate notices regarding ownership of the Trademark in connection with the Licensed Use. + +2.2. Goodwill. Licensee acknowledges that Licensee shall not acquire any right, title, or interest in the Trademark by virtue of this Agreement other than the license granted hereunder, and disclaims any such right, title, interest, or ownership. All goodwill and reputation generated by Licensee’s use of the Trademark shall inure to the exclusive benefit of Licensor. Licensee shall not by any act or omission use the Trademark in any manner that disparages or reflects adversely on Licensor or its Licensed Use or reputation. Licensee shall not take any action that would interfere with or prejudice Licensor’s ownership or registration of the Trademark, the validity of the Trademark or the validity of the license granted by this Agreement. If Licensor determines and notifies Licensee that any act taken in connection with the Licensed Use (i) is inaccurate, unlawful or offensive to good taste; (ii) fails to provide for proper trademark notices, or (iii) otherwise violates Licensee’s obligations under this Agreement, the license granted under this Agreement shall terminate. + +## Article 3 – Indemnification. +3.1. Indemnification Generally. Licensee agrees to indemnify, defend, and hold harmless (collectively “indemnify†or “indemnificationâ€) Licensor, including Licensor’s members, managers, officers, and employees (collectively “Related Personsâ€), from and against, and pay or reimburse Licensor and such Related Persons for, any and all third-party actions, claims, demands, proceedings, investigations, inquiries (collectively, “Claimsâ€), and any and all liabilities, obligations, fines, deficiencies, costs, expenses, royalties, losses, and damages (including reasonable outside counsel fees and expenses) associated with such Claims, to the extent that such Claim arises out of (i) Licensee’s material breach of this Agreement, or (ii) any allegation(s) that Licensee’s actions infringe or violate any third-party intellectual property right, including without limitation, any U.S. copyright, patent, or trademark, or are otherwise found to be tortious or criminal (whether or not such indemnified person is a named party in a legal proceeding). + +3.2. Notice and Defense of Claims. Licensor shall promptly notify Licensee of any Claim for which indemnification is sought, following actual knowledge of such Claim, provided however that the failure to give such notice shall not relieve Licensee of its obligations hereunder except to the extent that Licensee is materially prejudiced by such failure. In the event that any third-party Claim is brought, Licensee shall have the right and option to undertake and control the defense of such action with counsel of its choice, provided however that (i) Licensor at its own expense may participate and appear on an equal footing with Licensee in the defense of any such Claim, (ii) Licensor may undertake and control such defense in the event of the material failure of Licensee to undertake and control the same; and (iii) the defense of any Claim relating to the intellectual property rights of Licensor or its licensors and any related counterclaims shall be solely controlled by Licensor with counsel of its choice. Licensee shall not consent to judgment or concede or settle or compromise any Claim without the prior written approval of Licensor (whose approval shall not be unreasonably withheld), unless such concession or settlement or compromise includes a full and unconditional release of Licensor and any applicable Related Persons from all liabilities in respect of such Claim. + +## Article 4 – Miscellaneous. +4.1. Relationship of the Parties. This Agreement does not create a partnership, franchise, joint venture, agency, fiduciary, or employment relationship between the parties. + +4.2. No Third-Party Beneficiaries. Except for the rights of Related Persons under Article 3 (Indemnification), there are no third-party beneficiaries to this Agreement. + +4.3. Assignment. Licensee’s rights hereunder are non-assignable, and may not be sublicensed. + +4.4. Equitable Relief. Licensee acknowledges that the remedies available at law for any breach of this Agreement will, by their nature, be inadequate. Accordingly, Licensor may obtain injunctive relief or other equitable relief to restrain a breach or threatened breach of this Agreement or to specifically enforce this Agreement, without proving that any monetary damages have been sustained, and without the requirement of posting of a bond prior to obtaining such equitable relief. + +4.5. Governing Law. This Agreement will be interpreted, construed, and enforced in all respects in accordance with the laws of the State of California, without reference to its conflict of law principles. + +4.6. Attorneys’ Fees. If any legal action, arbitration or other proceeding is brought for the enforcement of this Agreement, or because of an alleged dispute, breach, default, or misrepresentation in connection with any of the provisions of this Agreement, the successful or prevailing party shall be entitled to recover its reasonable attorneys’ fees and other reasonable costs incurred in that action or proceeding, in addition to any other relief to which it may be entitled. + +4.7. Amendment; Waiver. This Agreement may not be amended, nor may any rights under it be waived, except in writing by Licensor. + +4.8. Severability. If any provision of this Agreement is held by a court of competent jurisdiction to be contrary to law, the provision shall be modified by the court and interpreted so as best to accomplish the objectives of the original provision to the fullest extent +permitted by law, and the remaining provisions of this Agreement shall remain in effect. + +4.9. Entire Agreement. This Agreement constitutes the entire agreement between the parties and supersedes all prior and contemporaneous agreements, proposals or representations, written or oral, concerning its subject matter. + + +# Apache License + +Version 2.0, January 2004 + +http://www.apache.org/licenses/ + +## TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. Definitions. + +"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. + +"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. + +"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. + +"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License. + +"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files. + +"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types. + +"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below). + +"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. + +"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. 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Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form. + +3. Grant of Patent License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. + +4. Redistribution. You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions: + + You must give any other recipients of the Work or Derivative Works a copy of this License; and + You must cause any modified files to carry prominent notices stating that You changed the files; and + You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and + If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License. + + You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License. + +5. Submission of Contributions. Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions. + +6. Trademarks. This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file. + +7. Disclaimer of Warranty. Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License. + +8. Limitation of Liability. In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS diff --git a/Libs/RiscV/NEORV32/sw/example/coremark/README.md b/Libs/RiscV/NEORV32/sw/example/coremark/README.md new file mode 100644 index 0000000..d37b09a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/coremark/README.md @@ -0,0 +1,78 @@ + +# Introduction + +CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features. For more information about EEMBC's comprehensive embedded benchmark suites, please see www.eembc.org. + +For a more compute-intensive version of CoreMark that uses larger datasets and execution loops taken from common applications, please check out EEMBC's [CoreMark-PRO](https://www.github.com/eembc/coremark-pro) benchmark, also on GitHub. + +This project folder is a port of CoreMark (from the official [GitHub repository](https://github.com/eembc/coremark)) for the NEORV32 processor. + +# Building + +To build the executable (`neorv32_exe.bin`) of the benchmark, type: + +`> make USER_FLAGS+=-DRUN_COREMARK clean_all exe` + +Make sure to define `RUN_COREMARK` *when invoking* `make` (via `USER_FLAGS+=-DRUN_COREMARK`). + +To build the executable for a certain CPU configuration and a certain optimization level of the benchmark, type (`rv32imc` and `O3` in this example): + +`> make USER_FLAGS+=-DRUN_COREMARK MARCH=rv32imc EFFORT=-O3 clean_all exe` + + +# Running + +Upload the generated executable `neorv32_exe.bin` via the bootloader ('u' command) and execute it ('e' command): + +``` +<< NEORV32 Bootloader >> + +BLDV: Nov 7 2020 +HWV: 0x01040700 +CLK: 0x05F5E100 Hz +USER: 0x10000DE0 +MISA: 0x40901104 +PROC: 0x007F0015 +IMEM: 0x00008000 bytes @ 0x00000000 +DMEM: 0x00008000 bytes @ 0x80000000 + +Autoboot in 8s. Press key to abort. +Aborted. + +Available CMDs: + h: Help + r: Restart + u: Upload + s: Store to flash + l: Load from flash + e: Execute +CMD:> u +Awaiting neorv32_exe.bin... OK +CMD:> e +Booting... + +NEORV32: Processor running at 100000000 Hz +NEORV32: Executing coremark (2000 iterations). This may take some time... + +2K performance run parameters for coremark. +CoreMark Size : 666 +Total ticks : 3036959876 +Total time (secs): 30 +Iterations/Sec : 66 +Iterations : 2000 +Compiler version : GCC10.1.0 +Compiler flags : -> default, see makefile +Memory location : STACK +seedcrc : 0xe9f5 +[0]crclist : 0xe714 +[0]crcmatrix : 0x1fd7 +[0]crcstate : 0x8e3a +[0]crcfinal : 0x4983 +Correct operation validated. See README.md for run and reporting rules. + +NEORV32: All reported numbers only show the integer results. + +NEORV32: Executed instructions 0x00000000_24b8576e +NEORV32: CoreMark core clock cycles 0x00000000_b5045484 +NEORV32: Average CPI (integer part only): 4 cycles/instruction +``` diff --git a/Libs/RiscV/NEORV32/sw/example/coremark/core_portme.h b/Libs/RiscV/NEORV32/sw/example/coremark/core_portme.h new file mode 100644 index 0000000..df3320a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/coremark/core_portme.h @@ -0,0 +1,232 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +/* Modified for the NEORV32 Processor - by Stephan Nolting */ + +/* Topic : Description + This file contains configuration constants required to execute on + different platforms +*/ +#ifndef CORE_PORTME_H +#define CORE_PORTME_H + +#include +#include + +/************************/ +/* NEORV32-specific */ +/************************/ +#define BAUD_RATE (19200) +#define ITERATIONS (2000) +#define FLAGS_STR "-> default, see makefile" // compiler optimization + +/************************/ +/* Data types and settings */ +/************************/ +/* Configuration : HAS_FLOAT + Define to 1 if the platform supports floating point. +*/ +#ifndef HAS_FLOAT +#define HAS_FLOAT 0 +#endif +/* Configuration : HAS_TIME_H + Define to 1 if platform has the time.h header file, + and implementation of functions thereof. +*/ +#ifndef HAS_TIME_H +#define HAS_TIME_H 0 +#endif +/* Configuration : USE_CLOCK + Define to 1 if platform has the time.h header file, + and implementation of functions thereof. +*/ +#ifndef USE_CLOCK +#define USE_CLOCK 0 +#endif +/* Configuration : HAS_STDIO + Define to 1 if the platform has stdio.h. +*/ +#ifndef HAS_STDIO +#define HAS_STDIO 0 +#endif +/* Configuration : HAS_PRINTF + Define to 1 if the platform has stdio.h and implements the printf + function. +*/ +#ifndef HAS_PRINTF +#define HAS_PRINTF 0 +#endif + +/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION + Initialize these strings per platform +*/ +#ifndef COMPILER_VERSION +#ifdef __GNUC__ +#define COMPILER_VERSION "GCC"__VERSION__ +#else +#define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" +#endif +#endif +#ifndef COMPILER_FLAGS +#define COMPILER_FLAGS \ + FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ +#endif +#ifndef MEM_LOCATION +#define MEM_LOCATION "STATIC" +#endif + +/* Data Types : + To avoid compiler issues, define the data types that need ot be used for + 8b, 16b and 32b in . + + *Imprtant* : + ee_ptr_int needs to be the data type used to hold pointers, otherwise + coremark may fail!!! +*/ +typedef int16_t ee_s16; +typedef uint16_t ee_u16; +typedef int32_t ee_s32; +typedef double ee_f32; +typedef unsigned char ee_u8; +typedef uint32_t ee_u32; +typedef uint64_t ee_u64; +typedef ee_u32 ee_ptr_int; +typedef size_t ee_size_t; +#define NULL ((void *)0) +/* align_mem : + This macro is used to align an offset to point to a 32b value. It is + used in the Matrix algorithm to initialize the input memory blocks. +*/ +#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3)) + +/* Configuration : CORE_TICKS + Define type of return from the timing functions. + */ +#define CORETIMETYPE ee_u64 +typedef ee_u64 CORE_TICKS; + +/* Configuration : SEED_METHOD + Defines method to get seed values that cannot be computed at compile + time. + + Valid values : + SEED_ARG - from command line. + SEED_FUNC - from a system function. + SEED_VOLATILE - from volatile variables. +*/ +#ifndef SEED_METHOD +#define SEED_METHOD SEED_VOLATILE +#endif + +/* Configuration : MEM_METHOD + Defines method to get a block of memry. + + Valid values : + MEM_MALLOC - for platforms that implement malloc and have malloc.h. + MEM_STATIC - to use a static memory array. + MEM_STACK - to allocate the data block on the stack (NYI). +*/ +#ifndef MEM_METHOD +#define MEM_METHOD MEM_STATIC +#endif + +/* Configuration : MULTITHREAD + Define for parallel execution + + Valid values : + 1 - only one context (default). + N>1 - will execute N copies in parallel. + + Note : + If this flag is defined to more then 1, an implementation for launching + parallel contexts must be defined. + + Two sample implementations are provided. Use or + to enable them. + + It is valid to have a different implementation of + and in , to fit a particular architecture. +*/ +#ifndef MULTITHREAD +#define MULTITHREAD 1 +#define USE_PTHREAD 0 +#define USE_FORK 0 +#define USE_SOCKET 0 +#endif + +/* Configuration : MAIN_HAS_NOARGC + Needed if platform does not support getting arguments to main. + + Valid values : + 0 - argc/argv to main is supported + 1 - argc/argv to main is not supported + + Note : + This flag only matters if MULTITHREAD has been defined to a value + greater then 1. +*/ +#ifndef MAIN_HAS_NOARGC +#define MAIN_HAS_NOARGC 0 +#endif + +/* Configuration : MAIN_HAS_NORETURN + Needed if platform does not support returning a value from main. + + Valid values : + 0 - main returns an int, and return value will be 0. + 1 - platform does not support returning a value from main +*/ +#ifndef MAIN_HAS_NORETURN +#define MAIN_HAS_NORETURN 0 +#endif + +/* Variable : default_num_contexts + Not used for this simple port, must cintain the value 1. +*/ +extern ee_u32 default_num_contexts; + +typedef struct CORE_PORTABLE_S +{ + ee_u8 portable_id; +} core_portable; + +/* target specific init/fini */ +#ifndef RUN_COREMARK +void +__attribute__((__noreturn__)) +portable_init(core_portable *p, int *argc, char *argv[]); +#else +void +portable_init(core_portable *p, int *argc, char *argv[]); +#endif +void portable_fini(core_portable *p); + +#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) \ + && !defined(VALIDATION_RUN) +#if (TOTAL_DATA_SIZE == 1200) +#define PROFILE_RUN 1 +#elif (TOTAL_DATA_SIZE == 2000) +#define PERFORMANCE_RUN 1 +#else +#define VALIDATION_RUN 1 +#endif +#endif + +int ee_printf(const char *fmt, ...); + +#endif /* CORE_PORTME_H */ diff --git a/Libs/RiscV/NEORV32/sw/example/coremark/coremark.h b/Libs/RiscV/NEORV32/sw/example/coremark/coremark.h new file mode 100644 index 0000000..9c5e406 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/coremark/coremark.h @@ -0,0 +1,183 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +/* Topic: Description + This file contains declarations of the various benchmark functions. +*/ + +/* Configuration: TOTAL_DATA_SIZE + Define total size for data algorithms will operate on +*/ +#ifndef TOTAL_DATA_SIZE +#define TOTAL_DATA_SIZE 2 * 1000 +#endif + +#define SEED_ARG 0 +#define SEED_FUNC 1 +#define SEED_VOLATILE 2 + +#define MEM_STATIC 0 +#define MEM_MALLOC 1 +#define MEM_STACK 2 + +#include "core_portme.h" + +#if HAS_STDIO +#include +#endif +#if HAS_PRINTF +#define ee_printf printf +#endif + +/* Actual benchmark execution in iterate */ +void *iterate(void *pres); + +/* Typedef: secs_ret + For machines that have floating point support, get number of seconds as + a double. Otherwise an unsigned int. +*/ +#if HAS_FLOAT +typedef double secs_ret; +#else +typedef ee_u32 secs_ret; +#endif + +#if MAIN_HAS_NORETURN +#define MAIN_RETURN_VAL +#define MAIN_RETURN_TYPE void +#else +#define MAIN_RETURN_VAL 0 +#define MAIN_RETURN_TYPE int +#endif + +void start_time(void); +void stop_time(void); +CORE_TICKS get_time(void); +secs_ret time_in_secs(CORE_TICKS ticks); + +/* Misc useful functions */ +ee_u16 crcu8(ee_u8 data, ee_u16 crc); +ee_u16 crc16(ee_s16 newval, ee_u16 crc); +ee_u16 crcu16(ee_u16 newval, ee_u16 crc); +ee_u16 crcu32(ee_u32 newval, ee_u16 crc); +ee_u8 check_data_types(void); +void * portable_malloc(ee_size_t size); +void portable_free(void *p); +ee_s32 parseval(char *valstring); + +/* Algorithm IDS */ +#define ID_LIST (1 << 0) +#define ID_MATRIX (1 << 1) +#define ID_STATE (1 << 2) +#define ALL_ALGORITHMS_MASK (ID_LIST | ID_MATRIX | ID_STATE) +#define NUM_ALGORITHMS 3 + +/* list data structures */ +typedef struct list_data_s +{ + ee_s16 data16; + ee_s16 idx; +} list_data; + +typedef struct list_head_s +{ + struct list_head_s *next; + struct list_data_s *info; +} list_head; + +/*matrix benchmark related stuff */ +#define MATDAT_INT 1 +#if MATDAT_INT +typedef ee_s16 MATDAT; +typedef ee_s32 MATRES; +#else +typedef ee_f16 MATDAT; +typedef ee_f32 MATRES; +#endif + +typedef struct MAT_PARAMS_S +{ + int N; + MATDAT *A; + MATDAT *B; + MATRES *C; +} mat_params; + +/* state machine related stuff */ +/* List of all the possible states for the FSM */ +typedef enum CORE_STATE +{ + CORE_START = 0, + CORE_INVALID, + CORE_S1, + CORE_S2, + CORE_INT, + CORE_FLOAT, + CORE_EXPONENT, + CORE_SCIENTIFIC, + NUM_CORE_STATES +} core_state_e; + +/* Helper structure to hold results */ +typedef struct RESULTS_S +{ + /* inputs */ + ee_s16 seed1; /* Initializing seed */ + ee_s16 seed2; /* Initializing seed */ + ee_s16 seed3; /* Initializing seed */ + void * memblock[4]; /* Pointer to safe memory location */ + ee_u32 size; /* Size of the data */ + ee_u32 iterations; /* Number of iterations to execute */ + ee_u32 execs; /* Bitmask of operations to execute */ + struct list_head_s *list; + mat_params mat; + /* outputs */ + ee_u16 crc; + ee_u16 crclist; + ee_u16 crcmatrix; + ee_u16 crcstate; + ee_s16 err; + /* ultithread specific */ + core_portable port; +} core_results; + +/* Multicore execution handling */ +#if (MULTITHREAD > 1) +ee_u8 core_start_parallel(core_results *res); +ee_u8 core_stop_parallel(core_results *res); +#endif + +/* list benchmark functions */ +list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed); +ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx); + +/* state benchmark functions */ +void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p); +ee_u16 core_bench_state(ee_u32 blksize, + ee_u8 *memblock, + ee_s16 seed1, + ee_s16 seed2, + ee_s16 step, + ee_u16 crc); + +/* matrix benchmark functions */ +ee_u32 core_init_matrix(ee_u32 blksize, + void * memblk, + ee_s32 seed, + mat_params *p); +ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc); diff --git a/Libs/RiscV/NEORV32/sw/example/coremark/makefile b/Libs/RiscV/NEORV32/sw/example/coremark/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/coremark/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/FreeRTOSConfig.h b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/FreeRTOSConfig.h new file mode 100644 index 0000000..8de5d6e --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/FreeRTOSConfig.h @@ -0,0 +1,152 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +//#include "clock_config.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html */ +#define configMTIME_BASE_ADDRESS ( 0xFFFFFF90UL ) +#define configMTIMECMP_BASE_ADDRESS ( 0xFFFFFF98UL ) + +#define configISR_STACK_SIZE_WORDS ( 128 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ 100000000 +#define configTICK_RATE_HZ ( ( TickType_t ) 100 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */ +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configTASK_NOTIFICATION_ARRAY_ENTRIES 4 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Task priorities. Allow these to be overridden. */ +#ifndef uartPRIMARY_PRIORITY + #define uartPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#endif + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); } + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/README.md b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/README.md new file mode 100644 index 0000000..b35ace8 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/README.md @@ -0,0 +1,71 @@ + # FreeRTOS Demo for the NEORV32 Processor + +This example shows how to run [FreeRTOS](https://www.freertos.org/) on the NEORV32 processor. It features the default +"blinky_demo" and the more sophisticated "full_demo" demo applications. See the comments in `main.c` and the according +source files for more information. + +The chip-specific extensions folder (`chip_specific_extensions/neorv32`) should be in `$(FREERTOS_HOME)/Source/portable/GCC/RISC-V/chip_specific_extensions`, +but is placed in this source directory for simplicity. + + +## Hardware Requirements + +* DMEM/IMEM requriements depend on the actual application (for example: 8kB DMEM and 16kB IMEM for *blinky_demo*) +* MTIME (machine timer) + UART + GPIO +* `Zicsr` CPU extension + + +## Instructions + +Download FreeRTOS from the [official GitHub repository](https://github.com/FreeRTOS/FreeRTOS) or from the its official homepage. + + $ git clone https://github.com/FreeRTOS/FreeRTOS.git + +Open the makefile from this example folder and configure the `FREERTOS_HOME` variable to point to your FreeRTOS home folder. + + FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOSv10.4.1 + +Compile the NEORV32 executable. Do not forget the `RUN_FREERTOS_DEMO` switch. + + $ make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all exe + +Note: The *.c sources and the FreeRTOS-specific part of the makefile have (include) guards that test if `RUN_FREERTOS_DEMO` is defined. +This has no pratical usage for the user - it is just a work-around for the NEORV32 CI environment. + +Upload the executable (`neorv32_exe.bin`) to the processor via the bootloader and execute it. + +``` +Awaiting neorv32_exe.bin... OK +CMD:> e +Booting... + +FreeRTOS V10.4.1 +Blink +Blink +Blink +``` + +## FreeRTOS Plus + +To automatically add source and include files from FreeRTOS plus extensions add one (or more) of the following arguments when invoking `make`: + +* FreeRTOS-Plus-CLI: `USER_FLAGS+=-FREERTOS_PLUS_CLI` +* FreeRTOS-Plus-TCP: `USER_FLAGS+=-FREERTOS_PLUS_TCP` + +Example: + + $ make USER_FLAGS+=-DRUN_FREERTOS_DEMO USER_FLAGS+=-FREERTOS_PLUS_TCP clean_all exe + + +## Notes + +The onfiguration of the FreeRTOS home folder (via `FREERTOS_HOME`) is corrupted if the compiler shows the following error: + +``` +main.c:36:10: fatal error: FreeRTOS.h: No such file or directory + 36 | #include + | ^~~~~~~~~~~~ +compilation terminated. +make: *** [makefile:203: main.c.o] Error 1 +``` + diff --git a/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/chip_specific_extensions/neorv32/freertos_risc_v_chip_specific_extensions.h b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/chip_specific_extensions/neorv32/freertos_risc_v_chip_specific_extensions.h new file mode 100644 index 0000000..c10f848 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/chip_specific_extensions/neorv32/freertos_risc_v_chip_specific_extensions.h @@ -0,0 +1,72 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * The FreeRTOS kernel's RISC-V port is split between the the code that is + * common across all currently supported RISC-V chips (implementations of the + * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: + * + * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that + * is common to all currently supported RISC-V chips. There is only one + * portASM.S file because the same file is built for all RISC-V target chips. + * + * + Header files called freertos_risc_v_chip_specific_extensions.h contain the + * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V + * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files + * as there are multiple RISC-V chip implementations. + * + * !!!NOTE!!! + * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h + * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the + * compiler's!) include path. For example, if the chip in use includes a core + * local interrupter (CLINT) and does not include any chip specific register + * extensions then add the path below to the assembler's include path: + * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions + * + */ + +/* + * NEORV32 chip specific extensions + */ + + +#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__ +#define __FREERTOS_RISC_V_EXTENSIONS_H__ + +#define portasmHAS_SIFIVE_CLINT 0 +#define portasmHAS_MTIME 1 +#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */ + +.macro portasmSAVE_ADDITIONAL_REGISTERS + /* No additional registers to save, so this macro does nothing. */ + .endm + +.macro portasmRESTORE_ADDITIONAL_REGISTERS + /* No additional registers to restore, so this macro does nothing. */ + .endm + +#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/full_demo/RegTest.s b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/full_demo/RegTest.s new file mode 100644 index 0000000..e274604 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/full_demo/RegTest.s @@ -0,0 +1,266 @@ +/* + * FreeRTOS Kernel V10.3.0 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + .extern ulRegTest1LoopCounter + .extern ulRegTest2LoopCounter + + .global vRegTest1Implementation + .global vRegTest2Implementation + +/*-----------------------------------------------------------*/ + +/* + * The register check tasks are described in the comments at the top of + * main_full.c. + */ + +.align( 4 ) +vRegTest1Implementation: + + /* Fill the core registers with known values. */ + li x5, 0x5 + li x6, 0x6 + li x7, 0x7 + li x8, 0x8 + li x9, 0x9 + li x10, 0xa + li x11, 0xb + li x12, 0xc + li x13, 0xd + li x14, 0xe + li x15, 0xf + li x16, 0x10 + li x17, 0x11 + li x18, 0x12 + li x19, 0x13 + li x20, 0x14 + li x21, 0x15 + li x22, 0x16 + li x23, 0x17 + li x24, 0x18 + li x25, 0x19 + li x26, 0x1a + li x27, 0x1b + li x28, 0x1c + li x29, 0x1d + li x30, 0x1e + +reg1_loop: + + /* Check each register still contains the expected known value. + vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation + uses x5 as the temporary. */ + li x31, 0x5 + bne x31, x5, reg1_error_loop + li x31, 0x6 + bne x31, x6, reg1_error_loop + li x31, 0x7 + bne x31, x7, reg1_error_loop + li x31, 0x8 + bne x31, x8, reg1_error_loop + li x31, 0x9 + bne x31, x9, reg1_error_loop + li x31, 0xa + bne x31, x10, reg1_error_loop + li x31, 0xb + bne x31, x11, reg1_error_loop + li x31, 0xc + bne x31, x12, reg1_error_loop + li x31, 0xd + bne x31, x13, reg1_error_loop + li x31, 0xe + bne x31, x14, reg1_error_loop + li x31, 0xf + bne x31, x15, reg1_error_loop + li x31, 0x10 + bne x31, x16, reg1_error_loop + li x31, 0x11 + bne x31, x17, reg1_error_loop + li x31, 0x12 + bne x31, x18, reg1_error_loop + li x31, 0x13 + bne x31, x19, reg1_error_loop + li x31, 0x14 + bne x31, x20, reg1_error_loop + li x31, 0x15 + bne x31, x21, reg1_error_loop + li x31, 0x16 + bne x31, x22, reg1_error_loop + li x31, 0x17 + bne x31, x23, reg1_error_loop + li x31, 0x18 + bne x31, x24, reg1_error_loop + li x31, 0x19 + bne x31, x25, reg1_error_loop + li x31, 0x1a + bne x31, x26, reg1_error_loop + li x31, 0x1b + bne x31, x27, reg1_error_loop + li x31, 0x1c + bne x31, x28, reg1_error_loop + li x31, 0x1d + bne x31, x29, reg1_error_loop + li x31, 0x1e + bne x31, x30, reg1_error_loop + + /* Everything passed, increment the loop counter. */ + lw x31, ulRegTest1LoopCounterConst + lw x30, 0(x31) + addi x30, x30, 1 + sw x30, 0(x31) + + /* Restore clobbered register reading for next loop. */ + li x30, 0x1e + + /* Yield to increase code coverage. */ + ecall + + /* Start again. */ + jal reg1_loop + +reg1_error_loop: + /* Jump here if a register contains an uxpected value. This stops the loop + counter being incremented so the check task knows an error was found. */ + ebreak + jal reg1_error_loop + +.align( 4 ) +ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter + +/*-----------------------------------------------------------*/ + +.align( 4 ) +vRegTest2Implementation: + + /* Fill the core registers with known values. */ + li x6, 0x61 + li x7, 0x71 + li x8, 0x81 + li x9, 0x91 + li x10, 0xa1 + li x11, 0xb1 + li x12, 0xc1 + li x13, 0xd1 + li x14, 0xe1 + li x15, 0xf1 + li x16, 0x20 + li x17, 0x21 + li x18, 0x22 + li x19, 0x23 + li x20, 0x24 + li x21, 0x25 + li x22, 0x26 + li x23, 0x27 + li x24, 0x28 + li x25, 0x29 + li x26, 0x2a + li x27, 0x2b + li x28, 0x2c + li x29, 0x2d + li x30, 0x2e + li x31, 0x2f + +Reg2_loop: + + /* Check each register still contains the expected known value. + vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation + uses x31 as the temporary. */ + li x5, 0x61 + bne x5, x6, reg2_error_loop + li x5, 0x71 + bne x5, x7, reg2_error_loop + li x5, 0x81 + bne x5, x8, reg2_error_loop + li x5, 0x91 + bne x5, x9, reg2_error_loop + li x5, 0xa1 + bne x5, x10, reg2_error_loop + li x5, 0xb1 + bne x5, x11, reg2_error_loop + li x5, 0xc1 + bne x5, x12, reg2_error_loop + li x5, 0xd1 + bne x5, x13, reg2_error_loop + li x5, 0xe1 + bne x5, x14, reg2_error_loop + li x5, 0xf1 + bne x5, x15, reg2_error_loop + li x5, 0x20 + bne x5, x16, reg2_error_loop + li x5, 0x21 + bne x5, x17, reg2_error_loop + li x5, 0x22 + bne x5, x18, reg2_error_loop + li x5, 0x23 + bne x5, x19, reg2_error_loop + li x5, 0x24 + bne x5, x20, reg2_error_loop + li x5, 0x25 + bne x5, x21, reg2_error_loop + li x5, 0x26 + bne x5, x22, reg2_error_loop + li x5, 0x27 + bne x5, x23, reg2_error_loop + li x5, 0x28 + bne x5, x24, reg2_error_loop + li x5, 0x29 + bne x5, x25, reg2_error_loop + li x5, 0x2a + bne x5, x26, reg2_error_loop + li x5, 0x2b + bne x5, x27, reg2_error_loop + li x5, 0x2c + bne x5, x28, reg2_error_loop + li x5, 0x2d + bne x5, x29, reg2_error_loop + li x5, 0x2e + bne x5, x30, reg2_error_loop + li x5, 0x2f + bne x5, x31, reg2_error_loop + + /* Everything passed, increment the loop counter. */ + lw x5, ulRegTest2LoopCounterConst + lw x6, 0(x5) + addi x6, x6, 1 + sw x6, 0(x5) + + /* Restore clobbered register reading for next loop. */ + li x6, 0x61 + + /* Start again. */ + jal Reg2_loop + +reg2_error_loop: + /* Jump here if a register contains an uxpected value. This stops the loop + counter being incremented so the check task knows an error was found. */ + ebreak + jal reg2_error_loop + +.align( 4 ) +ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter + + diff --git a/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/makefile b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/makefile new file mode 100644 index 0000000..cdc8c1a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_freeRTOS/makefile @@ -0,0 +1,144 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + + +# ***************************************************************************** +# USER CONFIGURATION +# ***************************************************************************** +# User's application sources (*.c, *.cpp, *.s, *.S); add additional files here +APP_SRC ?= $(wildcard ./*.c) $(wildcard ./*.s) $(wildcard ./*.cpp) $(wildcard ./*.S) + +# User's application include folders (don't forget the '-I' before each entry) +APP_INC ?= -I . +# User's application include folders - for assembly files only (don't forget the '-I' before each entry) +ASM_INC ?= -I . + +# Optimization +EFFORT ?= -Os + +# Compiler toolchain +RISCV_PREFIX ?= riscv32-unknown-elf- + +# CPU architecture and ABI +MARCH ?= rv32i +MABI ?= ilp32 + +# User flags for additional configuration (will be added to compiler flags) +USER_FLAGS ?= + +# Relative or absolute path to the NEORV32 home folder +NEORV32_HOME ?= ../../.. +# ***************************************************************************** + + + +# ----------------------------------------------------------------------------- +# FreeRTOS +# ----------------------------------------------------------------------------- +ifneq (,$(findstring RUN_FREERTOS_DEMO,$(USER_FLAGS))) +# FreeRTOS home folder (adapt this!) +FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOSv10.4.1 + +# FreeRTOS RISC-V specific +APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V/*.c) +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S + +APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V + +# FreeRTOS core +APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/*.c) +APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/portable/MemMang/heap_4.c) + +APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Source/include + +# FreeRTOS sources for the full_demo +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/blocktim.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/dynamic.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/GenQTest.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/recmutex.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TaskNotify.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TaskNotifyArray.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TimerDemo.c + +APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Demo/Common/include + +# NEORV32 specific +ASM_INC += -DportasmHANDLE_INTERRUPT=SystemIrqHandler + +APP_INC += -I chip_specific_extensions/neorv32 + +ASM_INC += -I chip_specific_extensions/neorv32 + +# Demo application +APP_SRC += blinky_demo/main_blinky.c +APP_SRC += full_demo/main_full.c +APP_SRC += full_demo/RegTest.s +endif + +# ----------------- +# FreeRTOS-Plus-CLI +# ----------------- +ifneq (,$(findstring FREERTOS_PLUS_CLI,$(USER_FLAGS))) +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.c + +APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI +endif + +# ----------------- +# FreeRTOS-Plus-TCP +# ----------------- +ifneq (,$(findstring FREERTOS_PLUS_TCP,$(USER_FLAGS))) +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c +APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c + +APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include +APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC +endif + + + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_gptmr/makefile b/Libs/RiscV/NEORV32/sw/example/demo_gptmr/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_gptmr/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_neopixel/makefile b/Libs/RiscV/NEORV32/sw/example/demo_neopixel/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_neopixel/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_pwm/makefile b/Libs/RiscV/NEORV32/sw/example/demo_pwm/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_pwm/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_slink/makefile b/Libs/RiscV/NEORV32/sw/example/demo_slink/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_slink/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_spi/makefile b/Libs/RiscV/NEORV32/sw/example/demo_spi/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_spi/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_trng/makefile b/Libs/RiscV/NEORV32/sw/example/demo_trng/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_trng/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_twi/makefile b/Libs/RiscV/NEORV32/sw/example/demo_twi/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_twi/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_wdt/makefile b/Libs/RiscV/NEORV32/sw/example/demo_wdt/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_wdt/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/demo_xirq/makefile b/Libs/RiscV/NEORV32/sw/example/demo_xirq/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/demo_xirq/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/dhrystone/LICENSE b/Libs/RiscV/NEORV32/sw/example/dhrystone/LICENSE new file mode 100644 index 0000000..ab666a9 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/dhrystone/LICENSE @@ -0,0 +1,9 @@ +Original LICENSE from https://github.com/sifive/benchmark-dhrystone + +Dhrystone +------------------------------------------------------------------------------ +There is no explicit license defined. They were originally +written in ADA by Reinhold P. Weicker and translated to C by Rick Richardson . + +The source obtained from the following site: +https://fossies.org/linux/privat/old/dhrystone-2.1.tar.gz diff --git a/Libs/RiscV/NEORV32/sw/example/dhrystone/README.md b/Libs/RiscV/NEORV32/sw/example/dhrystone/README.md new file mode 100644 index 0000000..81c4ec1 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/dhrystone/README.md @@ -0,0 +1,98 @@ +# Dhrystone Benchmark + +:copyright: Original sources from [https://github.com/sifive/benchmark-dhrystone](https://github.com/sifive/benchmark-dhrystone) (also, see `LICENSE`). +The source code has been modified for the NEORV32 processor. + +To compile the NEORV32 executable: +``` +neorv32/sw/example/dhrystone$ sh dhrystone.sh +``` + +The default number of iterations is 2000000. You can modify this by changing `USER_FLAGS+=-DDHRY_ITERS=2000000` in `dhrystone.sh`. +The default optimization level (EFFORT) is `O3`. + +:warning: Dhrystone will require an IMEM size of 16kB and a DMEM size of 16kB. The MTIME machine timer is used for timing evaluation. + +:construction: Porting Dhrystone is still work-in-progress. Performance results might be incorrect and not optimized. +All results only show the integer parts. + +### Exemplary Output + +Output generated for processor HW version [v1.5.9.1](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) +using performance-optimized configuration options. + +``` +NEORV32: Processor running at 100000000 Hz +NEORV32: Executing Dhrystone (2000000 iterations). This may take some time... + + +Dhrystone Benchmark, Version 2.1 (Language: C) + +Program compiled without 'register' attribute + +Execution starts, 2000000 runs through Dhrystone +Execution ends + +Final values of the variables used in the benchmark: + +Int_Glob: 5 + should be: 5 +Bool_Glob: 1 + should be: 1 +Ch_1_Glob: A + should be: A +Ch_2_Glob: B + should be: B +Arr_1_Glob[8]: 7 + should be: 7 +Arr_2_Glob[8][7]: 2000010 + should be: Number_Of_Runs + 10 +Ptr_Glob-> + Ptr_Comp: -2147467428 + should be: (implementation-dependent) + Discr: 0 + should be: 0 + Enum_Comp: 2 + should be: 2 + Int_Comp: 17 + should be: 17 + Str_Comp: DHRYSTONE PROGRAM, SOME STRING + should be: DHRYSTONE PROGRAM, SOME STRING +Next_Ptr_Glob-> + Ptr_Comp: -2147467428 + should be: (implementation-dependent), same as above + Discr: 0 + should be: 0 + Enum_Comp: 1 + should be: 1 + Int_Comp: 18 + should be: 18 + Str_Comp: DHRYSTONE PROGRAM, SOME STRING + should be: DHRYSTONE PROGRAM, SOME STRING +Int_1_Loc: 5 + should be: 5 +Int_2_Loc: 13 + should be: 13 +Int_3_Loc: 7 + should be: 7 +Enum_Loc: 1 + should be: 1 +Str_1_Loc: DHRYSTONE PROGRAM, 1'ST STRING + should be: DHRYSTONE PROGRAM, 1'ST STRING +Str_2_Loc: DHRYSTONE PROGRAM, 2'ND STRING + should be: DHRYSTONE PROGRAM, 2'ND STRING + +Microseconds for one run through Dhrystone: 13 +Dhrystones per Second: 76923 + +NEORV32: << DETAILED RESULTS (integer parts only) >> +NEORV32: Total cycles: 2662000187 +NEORV32: Cycles per second: 100000000 +NEORV32: Total runs: 2000000 + +NEORV32: DMIPS/s: 76923 +NEORV32: DMIPS/MHz: 769 + +NEORV32: VAX DMIPS/s: 43 +NEORV32: VAX DMIPS/MHz: 43/100 +``` diff --git a/Libs/RiscV/NEORV32/sw/example/dhrystone/dhry.h b/Libs/RiscV/NEORV32/sw/example/dhrystone/dhry.h new file mode 100644 index 0000000..f296c1b --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/dhrystone/dhry.h @@ -0,0 +1,451 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens AG, E STE 35 + * Postfach 3240 + * 8520 Erlangen + * Germany (West) + * Phone: [xxx-49]-9131-7-20330 + * (8-17 Central European Time) + * Usenet: ..!mcvax!unido!estevax!weicker + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * In addition, Berkeley UNIX system calls "times ()" or "time ()" + * are used for execution time measurement. For measurements + * on other systems, these calls have to be changed. + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 389-8963 (9-17 EST) + * Usenet: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software used. + * Hardware information includes: Machine type, CPU, type and size + * of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). + * Software information includes: Compiler (and runtime library) + * manufacturer and version, compilation switches, OS version. + * The Operating System version may give an indication about the + * compiler; Dhrystone itself performs no OS calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + *************************************************************************** + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used most. + * There should be, as far as possible, only one C version of + * Dhrystone such that results can be compared without + * restrictions. In the past, the C versions distributed + * by Rick Richardson (Version 1.1) and by Reinhold Weicker + * had small (though not significant) differences. + * + * 2) As far as it is possible without changes to the Dhrystone + * statistics, optimizing compilers should be prevented from + * removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold Weicker. + * As a concession to older compilers, names have been made + * unique within the first 8 characters. + * Inside the measurement loop, this version follows the + * version previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing compilers + * should be prevented from moving code out of the measurement + * loop, or from removing code altogether. Since the statements + * that are executed within the measurement loop have NOT been + * changed, the numbers defining the "Dhrystone distribution" + * (distribution of statements, operand types and locality) + * still hold. Except for sophisticated optimizing compilers, + * execution times for this version should be the same as + * for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic benchmarks. + * Users of the benchmark are advised to check code listings + * whether code is generated for all statements of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it corrects + * some minor deficiencies that were found by users of version 2.0. + * The only change within the measurement loop is that a + * non-executed "else" part was added to the "if" statement in + * Func_3, and a non-executed "else" part removed from Proc_3. + * + *************************************************************************** + * + * Defines: The following "Defines" are possible: + * -DREG=register (default: Not defined) + * As an approximation to what an average C programmer + * might do, the "register" storage class is applied + * (if enabled by -DREG=register) + * - for local variables, if they are used (dynamically) + * five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" declarations + * do not necessarily lead to faster execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * -DTIMES (default) + * -DTIME + * The "times" function of UNIX (returning process times) + * or the "time" function (returning wallclock time) + * is used for measurement. + * For single user machines, "time ()" is adequate. For + * multi-user machines where you cannot get single-user + * access, use the "times ()" function. If you have + * neither, use a stopwatch in the dead of night. + * "printf"s are provided marking the points "Start Timer" + * and "Stop Timer". DO NOT use the UNIX "time(1)" + * command, as this will measure the total time to + * run this program, which will (erroneously) include + * the time to allocate storage (malloc) and to perform + * the initialization. + * -DHZ=nnn + * In Berkeley UNIX, the function "times" returns process + * time in 1/HZ seconds, with HZ = 60 for most systems. + * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY + * A VALUE. + * + *************************************************************************** + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system used. + * + ************************************************************************** + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values aX * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a record + * component), only the final data type on the access path is counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is syntactically + * and semantically correct. All variables have a value assigned to them + * before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code or + * data. + * + *************************************************************************** + */ + +#ifndef dhrystone_h +#define dhrystone_h + +/* Compiler and system dependent definitions: */ + +#ifndef TIME +#undef TIMES +#define TIMES +#endif + /* Use times(2) time function unless */ + /* explicitly defined otherwise */ + +//#ifdef MSC_CLOCK +//#undef HZ +//#undef TIMES +//#include +//#define HZ CLK_TCK +//#endif +// /* Use Microsoft C hi-res clock */ + +#define HZ SYSINFO_CLK + +#ifdef TIMES +#include +#include + /* for "times" */ +#endif + +#define Mic_secs_Per_Second 1000000 + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +#include + /* for strcpy, strcmp */ + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + + +// function prototypes +Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val); +Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref); +Boolean Func_3 (Enum_Par_Val); +void Proc_1 (Ptr_Val_Par); +void Proc_2 (Int_Par_Ref); +void Proc_3 (Ptr_Ref_Par); +void Proc_4 (void); +void Proc_5 (void); +void Proc_6 (Enum_Val_Par, Enum_Ref_Par); +void Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref); +void Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val); +int strcmp(const char *p1, const char *p2); + +#endif // dhrystone_h diff --git a/Libs/RiscV/NEORV32/sw/example/dhrystone/dhrystone.sh b/Libs/RiscV/NEORV32/sw/example/dhrystone/dhrystone.sh new file mode 100644 index 0000000..89f0c79 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/dhrystone/dhrystone.sh @@ -0,0 +1 @@ +make USER_FLAGS+=-DRUN_DHRYSTONE USER_FLAGS+=-DDHRY_ITERS=2000000 USER_FLAGS+=-DNOENUM MARCH=rv32imc EFFORT=-O3 clean_all exe diff --git a/Libs/RiscV/NEORV32/sw/example/dhrystone/makefile b/Libs/RiscV/NEORV32/sw/example/dhrystone/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/dhrystone/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/floating_point_test/README.md b/Libs/RiscV/NEORV32/sw/example/floating_point_test/README.md new file mode 100644 index 0000000..80c4bb1 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/floating_point_test/README.md @@ -0,0 +1,52 @@ +# NEORV32 `Zfinx` Floating-Point Extension + +The NEORV32 floating-point unit (FPU) implements the `Zfinx` RISC-V extension. The extensions can be enabled via the `CPU_EXTENSION_RISCV_Zfinx` top configuration generic. + +The RISC-V `Zfinx` single-precision floating-point extensions uses the integer register file `x` instead of the dedicated floating-point `f` register file (which is +defined by the RISC-V `F` single-precision floating-point extension). Hence, the standard data transfer instructions from the `F` extension are **not** available in `Zfinx`: + +* floating-point load/store operations (`FLW`, `FSW`) and their compressed versions +* integer register file `x` <-> floating point register file `f` move operations (`FMV.W.X`, `FMV.X.W`) + +:information_source: More information regarding the RISC-V `Zfinx` single-precision floating-point extension can be found in the official GitHub repo: +[`github.com/riscv/riscv-zfinx`](https://github.com/riscv/riscv-zfinx). + +:warning: The RISC-V `Zfinx` extension is not officially ratified yet, but it is assumed to remain unchanged. Hence, it is not supported by the upstream RISC-V GCC port. +Make sure you **do not** use the `f` ISA attribute when compiling applications that use floating-point arithmetic (`MARCH=rv32i*f*` is **NOT ALLOWED!**). + + +### :warning: FPU Limitations + +* The FPU **does not support subnormal numbers** yet. Subnormal FPU inputs and subnormal FPU results are always *flushed to zero*. The *classify* instruction `FCLASS` will never set the "subnormal" mask bits. +* Rounding mode `ob100` "round to nearest, ties to max magnitude" is not supported yet (this and all invalid rounding mode configurations behave as "round towards zero" (truncation)). + + +## Intrinsic Library + +The NEORV32 `Zfinx` floating-point extension can still be used using the provided **intrinsic library**. This library uses "custom" inline assmbly instructions +wrapped within normal C-language functions. Each original instruction of the extension can be utilized using an according intrinsic function. + +For example, the floating-point addition instruction `FADD.S` can be invoked using the according intrinsic function: + +```c +float riscv_intrinsic_fadds(float rs1, float rs2) +``` + +The pure-software emulation instruction, which uses the standard built-in functions to execute all floating-point operations, is available via wrapper function. The +emulation function for the `FADD.S` instruction is: + +```c +float riscv_emulate_fadds(float rs1, float rs2) +``` + +The emulation functions as well as the available intrinsics for the `Zfinx` extension are located in `neorv32_zfinx_extension_intrinsics.h`. + +The provided test program `main.c` verifies all currently implemented `Zfinx` instructions by checking the functionality against the pure software-based emulation model +(GCC soft-float library). + + +## Resources + +* Great page with online calculators for floating-point arithmetic: [http://www.ecs.umass.edu/ece/koren/arith/simulator/](http://www.ecs.umass.edu/ece/koren/arith/simulator/) +* A handy tool for visualizing floating-point numbers in their binary representation: [https://www.h-schmidt.net/FloatConverter/IEEE754.html](https://www.h-schmidt.net/FloatConverter/IEEE754.html) +* This helped me to understand what results the different FPU operation generate when having "special" inputs like NaN: [https://techdocs.altium.com/display/FPGA/IEEE+754+Standard+-+Overview](https://techdocs.altium.com/display/FPGA/IEEE+754+Standard+-+Overview) diff --git a/Libs/RiscV/NEORV32/sw/example/floating_point_test/makefile b/Libs/RiscV/NEORV32/sw/example/floating_point_test/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/floating_point_test/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/floating_point_test/neorv32_zfinx_extension_intrinsics.h b/Libs/RiscV/NEORV32/sw/example/floating_point_test/neorv32_zfinx_extension_intrinsics.h new file mode 100644 index 0000000..5b4b578 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/floating_point_test/neorv32_zfinx_extension_intrinsics.h @@ -0,0 +1,1370 @@ +// ################################################################################################# +// # << NEORV32 - Intrinsics + Emulation Functions for the RISC-V "Zfinx" CPU extension >> # +// # ********************************************************************************************* # +// # The intrinsics provided by this library allow to use the hardware floating-point unit of the # +// # RISC-V Zfinx CPU extension without the need for Zfinx support by the compiler / toolchain. # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file floating_point_test/neorv32_zfinx_extension_intrinsics.h + * @author Stephan Nolting + * + * @brief "Intrinsic" library for the NEORV32 single-precision floating-point in x registers (Zfinx) extension + * @brief Also provides emulation functions for all intrinsics (functionality re-built in pure software). The functionality of the emulation + * @brief functions is based on the RISC-V floating-point spec. + * + * @note All operations from this library use the default GCC "round to nearest, ties to even" rounding mode. + * + * @warning This library is just a temporary fall-back until the Zfinx extensions are supported by the upstream RISC-V GCC port. + **************************************************************************/ + +#ifndef neorv32_zfinx_extension_intrinsics_h +#define neorv32_zfinx_extension_intrinsics_h + +#define __USE_GNU + +#include +//#pragma STDC FENV_ACCESS ON + +#define _GNU_SOURCE + +#include +#include + + +/**********************************************************************//** + * Sanity check + **************************************************************************/ +#if defined __riscv_f || (__riscv_flen == 32) + #error Application programs using the Zfinx intrinsic library have to be compiled WITHOUT the MARCH ISA attribute! +#endif + + +/**********************************************************************//** + * Custom data type to access floating-point values as native floats and in binary representation + **************************************************************************/ +typedef union +{ + uint32_t binary_value; /**< Access as native float */ + float float_value; /**< Access in binary representation */ +} float_conv_t; + + +// ################################################################################################ +// Helper functions +// ################################################################################################ + +/**********************************************************************//** + * Flush to zero if denormal number. + * + * @warning Subnormal numbers are not supported yet! Flush them to zero. + * + * @param[in] tmp Source operand. + * @return Result. + **************************************************************************/ +float subnormal_flush(float tmp) { + + float res = tmp; + + if (fpclassify(tmp) == FP_SUBNORMAL) { + if (signbit(tmp) != 0) { + res = -0.0f; + } + else { + res = +0.0f; + } + } + + return res; +} + + +// ################################################################################################ +// Exception access +// ################################################################################################ + +/**********************************************************************//** + * Get exception flags from fflags CSR (floating-point hardware). + * + * @return Floating point exception status word. + **************************************************************************/ +uint32_t get_hw_exceptions(void) { + + uint32_t res = neorv32_cpu_csr_read(CSR_FFLAGS); + + neorv32_cpu_csr_write(CSR_FFLAGS, 0); // clear status word + + return res; +} + + +/**********************************************************************//** + * Get exception flags from C runtime (floating-point emulation). + * + * @warning WORK-IN-PROGRESS! + * + * @return Floating point exception status word. + **************************************************************************/ +uint32_t get_sw_exceptions(void) { + + const uint32_t FP_EXC_NV_C = 1 << 0; // invalid operation + const uint32_t FP_EXC_DZ_C = 1 << 1; // divide by zero + const uint32_t FP_EXC_OF_C = 1 << 2; // overflow + const uint32_t FP_EXC_UF_C = 1 << 3; // underflow + const uint32_t FP_EXC_NX_C = 1 << 4; // inexact + + int fpeRaised = fetestexcept(FE_ALL_EXCEPT); + + uint32_t res = 0; + + if (fpeRaised & FE_INVALID) { res |= FP_EXC_NV_C; } + if (fpeRaised & FE_DIVBYZERO) { res |= FP_EXC_DZ_C; } + if (fpeRaised & FE_OVERFLOW) { res |= FP_EXC_OF_C; } + if (fpeRaised & FE_UNDERFLOW) { res |= FP_EXC_UF_C; } + if (fpeRaised & FE_INEXACT) { res |= FP_EXC_NX_C; } + + feclearexcept(FE_ALL_EXCEPT); + + return res; +} + + +// ################################################################################################ +// "Intrinsics" +// ################################################################################################ + +/**********************************************************************//** + * Single-precision floating-point addition + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fadds(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fadd.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0000000, a1, a0, 0b000, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point subtraction + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fsubs(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fsub.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0000100, a1, a0, 0b000, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point multiplication + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fmuls(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fmul.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0001000, a1, a0, 0b000, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point minimum + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fmins(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fmin.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b000, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point maximum + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fmaxs(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fmax.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b001, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point convert float to unsigned integer + * + * @param[in] rs1 Source operand 1 (a0). + * @return Result. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_wus(float rs1) { + + float_conv_t opa; + opa.float_value = rs1; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // fcvt.wu.s a0, a0 + CUSTOM_INSTR_R2_TYPE(0b1100000, x1, a0, 0b000, a0, 0b1010011); + + return result; +} + + +/**********************************************************************//** + * Single-precision floating-point convert float to signed integer + * + * @param[in] rs1 Source operand 1 (a0). + * @return Result. + **************************************************************************/ +inline int32_t __attribute__ ((always_inline)) riscv_intrinsic_fcvt_ws(float rs1) { + + float_conv_t opa; + opa.float_value = rs1; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // fcvt.w.s a0, a0 + CUSTOM_INSTR_R2_TYPE(0b1100000, x0, a0, 0b000, a0, 0b1010011); + + return (int32_t)result; +} + + +/**********************************************************************//** + * Single-precision floating-point convert unsigned integer to float + * + * @param[in] rs1 Source operand 1 (a0). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fcvt_swu(uint32_t rs1) { + + float_conv_t res; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // fcvt.s.wu a0, a0 + CUSTOM_INSTR_R2_TYPE(0b1101000, x1, a0, 0b000, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point convert signed integer to float + * + * @param[in] rs1 Source operand 1 (a0). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fcvt_sw(int32_t rs1) { + + float_conv_t res; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = (uint32_t)rs1; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // fcvt.s.w a0, a0 + CUSTOM_INSTR_R2_TYPE(0b1101000, x0, a0, 0b000, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point equal comparison + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_feqs(float rs1, float rs2) { + + float_conv_t opa, opb; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // feq.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b010, a0, 0b1010011); + + return result; +} + + +/**********************************************************************//** + * Single-precision floating-point less-than comparison + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_flts(float rs1, float rs2) { + + float_conv_t opa, opb; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // flt.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b001, a0, 0b1010011); + + return result; +} + + +/**********************************************************************//** + * Single-precision floating-point less-than-or-equal comparison + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fles(float rs1, float rs2) { + + float_conv_t opa, opb; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fle.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b000, a0, 0b1010011); + + return result; +} + + +/**********************************************************************//** + * Single-precision floating-point sign-injection + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjs(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fsgnj.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b000, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point sign-injection NOT + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjns(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fsgnjn.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b001, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point sign-injection XOR + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fsgnjxs(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fsgnjx.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b1010011); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point number classification + * + * @param[in] rs1 Source operand 1 (a0). + * @return Result. + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) riscv_intrinsic_fclasss(float rs1) { + + float_conv_t opa; + opa.float_value = rs1; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("" : [output] "=r" (result) : [input_i] "r" (tmp_a)); + + // fclass.s a0, a0 + CUSTOM_INSTR_R2_TYPE(0b1110000, x0, a0, 0b001, a0, 0b1010011); + + return result; +} + + +// ################################################################################################ +// !!! UNSUPPORTED instructions !!! +// ################################################################################################ + +/**********************************************************************//** + * Single-precision floating-point division + * + * @warning This instruction is not supported and should raise an illegal instruction exception when executed. + * + * @param[in] rs1 Source operand 1 (a0). + * @param[in] rs2 Source operand 2 (a1). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fdivs(float rs1, float rs2) { + + float_conv_t opa, opb, res; + opa.float_value = rs1; + opb.float_value = rs2; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + + // fdiv.s a0, a0, x1 + CUSTOM_INSTR_R2_TYPE(0b0001100, a1, a0, 0b000, a0, 0b1010011); + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) ); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point square root + * + * @warning This instruction is not supported and should raise an illegal instruction exception when executed. + * + * @param[in] rs1 Source operand 1 (a0). + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fsqrts(float rs1) { + + float_conv_t opa, res; + opa.float_value = rs1; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a)); + + // fsqrt.s a0, a0, a1 + CUSTOM_INSTR_R2_TYPE(0b0101100, a1, a0, 0b000, a0, 0b1010011); + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) ); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point fused multiply-add + * + * @warning This instruction is not supported and should raise an illegal instruction exception when executed. + * + * @param[in] rs1 Source operand 1 (a0) + * @param[in] rs2 Source operand 2 (a1) + * @param[in] rs3 Source operand 3 (a2) + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fmadds(float rs1, float rs2, float rs3) { + + float_conv_t opa, opb, opc, res; + opa.float_value = rs1; + opb.float_value = rs2; + opc.float_value = rs3; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + register uint32_t tmp_c __asm__ ("a2") = opc.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c)); + + // fmadd.s a0, a0, a1, a2 + CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1000011); + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) ); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point fused multiply-sub + * + * @warning This instruction is not supported and should raise an illegal instruction exception when executed. + * + * @param[in] rs1 Source operand 1 (a0) + * @param[in] rs2 Source operand 2 (a1) + * @param[in] rs3 Source operand 3 (a2) + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fmsubs(float rs1, float rs2, float rs3) { + + float_conv_t opa, opb, opc, res; + opa.float_value = rs1; + opb.float_value = rs2; + opc.float_value = rs3; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + register uint32_t tmp_c __asm__ ("a2") = opc.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c)); + + // fmsub.s a0, a0, a1, a2 + CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1000111); + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) ); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point fused negated multiply-sub + * + * @warning This instruction is not supported and should raise an illegal instruction exception when executed. + * + * @param[in] rs1 Source operand 1 (a0) + * @param[in] rs2 Source operand 2 (a1) + * @param[in] rs3 Source operand 3 (a2) + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fnmsubs(float rs1, float rs2, float rs3) { + + float_conv_t opa, opb, opc, res; + opa.float_value = rs1; + opb.float_value = rs2; + opc.float_value = rs3; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + register uint32_t tmp_c __asm__ ("a2") = opc.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c)); + + // fnmsub.s a0, a0, a1, a2 + CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1001011); + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) ); + + res.binary_value = result; + return res.float_value; +} + + +/**********************************************************************//** + * Single-precision floating-point fused negated multiply-add + * + * @warning This instruction is not supported and should raise an illegal instruction exception when executed. + * + * @param[in] rs1 Source operand 1 (a0) + * @param[in] rs2 Source operand 2 (a1) + * @param[in] rs3 Source operand 3 (a2) + * @return Result. + **************************************************************************/ +inline float __attribute__ ((always_inline)) riscv_intrinsic_fnmadds(float rs1, float rs2, float rs3) { + + float_conv_t opa, opb, opc, res; + opa.float_value = rs1; + opb.float_value = rs2; + opc.float_value = rs3; + + register uint32_t result __asm__ ("a0"); + register uint32_t tmp_a __asm__ ("a0") = opa.binary_value; + register uint32_t tmp_b __asm__ ("a1") = opb.binary_value; + register uint32_t tmp_c __asm__ ("a2") = opc.binary_value; + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b)); + asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c)); + + // fnmadd.s a0, a0, a1, a2 + CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1001111); + + // dummy instruction to prevent GCC "constprop" optimization + asm volatile ("add %[res], %[input], x0" : [res] "=r" (result) : [input] "r" (result) ); + + res.binary_value = result; + return res.float_value; +} + + +// ################################################################################################ +// Emulation functions +// ################################################################################################ + +/**********************************************************************//** + * Single-precision floating-point addition + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fadds(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + float res = opa + opb; + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point subtraction + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fsubs(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + float res = opa - opb; + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point multiplication + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fmuls(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + float res = opa * opb; + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point minimum + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fmins(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + union { + uint32_t binary_value; /**< Access as native float */ + float float_value; /**< Access in binary representation */ + } tmp_a, tmp_b; + + if ((fpclassify(opa) == FP_NAN) && (fpclassify(opb) == FP_NAN)) { + return nanf(""); + } + + if (fpclassify(opa) == FP_NAN) { + return opb; + } + + if (fpclassify(opb) == FP_NAN) { + return opa; + } + + // RISC-V spec: -0 < +0 + tmp_a.float_value = opa; + tmp_b.float_value = opb; + if (((tmp_a.binary_value == 0x80000000) && (tmp_b.binary_value == 0x00000000)) || + ((tmp_a.binary_value == 0x00000000) && (tmp_b.binary_value == 0x80000000))) { + return -0.0f; + } + + return fmin(opa, opb); +} + + +/**********************************************************************//** + * Single-precision floating-point maximum + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fmaxs(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + union { + uint32_t binary_value; /**< Access as native float */ + float float_value; /**< Access in binary representation */ + } tmp_a, tmp_b; + + + if ((fpclassify(opa) == FP_NAN) && (fpclassify(opb) == FP_NAN)) { + return nanf(""); + } + + if (fpclassify(opa) == FP_NAN) { + return opb; + } + + if (fpclassify(opb) == FP_NAN) { + return opa; + } + + // RISC-V spec: -0 < +0 + tmp_a.float_value = opa; + tmp_b.float_value = opb; + if (((tmp_a.binary_value == 0x80000000) && (tmp_b.binary_value == 0x00000000)) || + ((tmp_a.binary_value == 0x00000000) && (tmp_b.binary_value == 0x80000000))) { + return +0.0f; + } + + return fmax(opa, opb); +} + + +/**********************************************************************//** + * Single-precision floating-point float to unsigned integer + * + * @param[in] rs1 Source operand 1. + * @return Result. + **************************************************************************/ +uint32_t __attribute__ ((noinline)) riscv_emulate_fcvt_wus(float rs1) { + + float opa = subnormal_flush(rs1); + + return (uint32_t)roundf(opa); +} + + +/**********************************************************************//** + * Single-precision floating-point float to signed integer + * + * @param[in] rs1 Source operand 1. + * @return Result. + **************************************************************************/ +int32_t __attribute__ ((noinline)) riscv_emulate_fcvt_ws(float rs1) { + + float opa = subnormal_flush(rs1); + + return (int32_t)roundf(opa); +} + + +/**********************************************************************//** + * Single-precision floating-point unsigned integer to float + * + * @param[in] rs1 Source operand 1. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fcvt_swu(uint32_t rs1) { + + return (float)rs1; +} + + +/**********************************************************************//** + * Single-precision floating-point signed integer to float + * + * @param[in] rs1 Source operand 1. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fcvt_sw(int32_t rs1) { + + return (float)rs1; +} + + +/**********************************************************************//** + * Single-precision floating-point equal comparison + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +uint32_t __attribute__ ((noinline)) riscv_emulate_feqs(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + if ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) { + return 0; + } + + if isless(opa, opb) { + return 0; + } + else if isgreater(opa, opb) { + return 0; + } + else { + return 1; + } +} + + +/**********************************************************************//** + * Single-precision floating-point less-than comparison + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +uint32_t __attribute__ ((noinline)) riscv_emulate_flts(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + if ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) { + return 0; + } + + if isless(opa, opb) { + return 1; + } + else { + return 0; + } +} + + +/**********************************************************************//** + * Single-precision floating-point less-than-or-equal comparison + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +uint32_t __attribute__ ((noinline)) riscv_emulate_fles(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + if ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) { + return 0; + } + + if islessequal(opa, opb) { + return 1; + } + else { + return 0; + } +} + + +/**********************************************************************//** + * Single-precision floating-point sign-injection + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fsgnjs(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + int sign_1 = (int)signbit(opa); + int sign_2 = (int)signbit(opb); + float res = 0; + + if (sign_2 != 0) { // opb is negative + if (sign_1 == 0) { + res = -opa; + } + else { + res = opa; + } + } + else { // opb is positive + if (sign_1 == 0) { + res = opa; + } + else { + res = -opa; + } + } + + return res; +} + + +/**********************************************************************//** + * Single-precision floating-point sign-injection NOT + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fsgnjns(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + int sign_1 = (int)signbit(opa); + int sign_2 = (int)signbit(opb); + float res = 0; + + if (sign_2 != 0) { // opb is negative + if (sign_1 == 0) { + res = opa; + } + else { + res = -opa; + } + } + else { // opb is positive + if (sign_1 == 0) { + res = -opa; + } + else { + res = opa; + } + } + + return res; +} + + +/**********************************************************************//** + * Single-precision floating-point sign-injection XOR + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fsgnjxs(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + int sign_1 = (int)signbit(opa); + int sign_2 = (int)signbit(opb); + float res = 0; + + if (((sign_1 == 0) && (sign_2 != 0)) || ((sign_1 != 0) && (sign_2 == 0))) { + if (sign_1 == 0) { + res = -opa; + } + else { + res = opa; + } + } + else { + if (sign_1 == 0) { + res = opa; + } + else { + res = -opa; + } + } + + return res; +} + + +/**********************************************************************//** + * Single-precision floating-point number classification + * + * @param[in] rs1 Source operand 1. + * @return Result. + **************************************************************************/ +uint32_t __attribute__ ((noinline)) riscv_emulate_fclasss(float rs1) { + + float opa = subnormal_flush(rs1); + + union { + uint32_t binary_value; /**< Access as native float */ + float float_value; /**< Access in binary representation */ + } aux; + + // RISC-V classify result layout + const uint32_t CLASS_NEG_INF = 1 << 0; // negative infinity + const uint32_t CLASS_NEG_NORM = 1 << 1; // negative normal number + const uint32_t CLASS_NEG_DENORM = 1 << 2; // negative subnormal number + const uint32_t CLASS_NEG_ZERO = 1 << 3; // negative zero + const uint32_t CLASS_POS_ZERO = 1 << 4; // positive zero + const uint32_t CLASS_POS_DENORM = 1 << 5; // positive subnormal number + const uint32_t CLASS_POS_NORM = 1 << 6; // positive normal number + const uint32_t CLASS_POS_INF = 1 << 7; // positive infinity + const uint32_t CLASS_SNAN = 1 << 8; // signaling NaN (sNaN) + const uint32_t CLASS_QNAN = 1 << 9; // quiet NaN (qNaN) + + int tmp = fpclassify(opa); + int sgn = (int)signbit(opa); + + uint32_t res = 0; + + // infinity + if (tmp == FP_INFINITE) { + if (sgn) { res |= CLASS_NEG_INF; } + else { res |= CLASS_POS_INF; } + } + + // zero + if (tmp == FP_ZERO) { + if (sgn) { res |= CLASS_NEG_ZERO; } + else { res |= CLASS_POS_ZERO; } + } + + // normal + if (tmp == FP_NORMAL) { + if (sgn) { res |= CLASS_NEG_NORM; } + else { res |= CLASS_POS_NORM; } + } + + // subnormal + if (tmp == FP_SUBNORMAL) { + if (sgn) { res |= CLASS_NEG_DENORM; } + else { res |= CLASS_POS_DENORM; } + } + + // NaN + if (tmp == FP_NAN) { + aux.float_value = opa; + if ((aux.binary_value >> 22) & 0b1) { // bit 22 (mantissa's MSB) is set -> canonical (quiet) NAN + res |= CLASS_QNAN; + } + else { + res |= CLASS_SNAN; + } + } + + return res; +} + + +/**********************************************************************//** + * Single-precision floating-point division + * + * @param[in] rs1 Source operand 1. + * @param[in] rs2 Source operand 2. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fdivs(float rs1, float rs2) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + + float res = opa / opb; + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point square root + * + * @param[in] rs1 Source operand 1. + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fsqrts(float rs1) { + + float opa = subnormal_flush(rs1); + + float res = sqrtf(opa); + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point fused multiply-add + * + * @note "noinline" attributed to make sure arguments/return values are in a0 and a1. + * + * @warning This instruction is not supported! + * + * @param[in] rs1 Source operand 1 + * @param[in] rs2 Source operand 2 + * @param[in] rs3 Source operand 3 + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fmadds(float rs1, float rs2, float rs3) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + float opc = subnormal_flush(rs3); + + float res = (opa * opb) + opc; + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point fused multiply-sub + * + * @param[in] rs1 Source operand 1 + * @param[in] rs2 Source operand 2 + * @param[in] rs3 Source operand 3 + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fmsubs(float rs1, float rs2, float rs3) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + float opc = subnormal_flush(rs3); + + float res = (opa * opb) - opc; + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point fused negated multiply-sub + * + * @param[in] rs1 Source operand 1 + * @param[in] rs2 Source operand 2 + * @param[in] rs3 Source operand 3 + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fnmsubs(float rs1, float rs2, float rs3) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + float opc = subnormal_flush(rs3); + + float res = -(opa * opb) + opc; + return subnormal_flush(res); +} + + +/**********************************************************************//** + * Single-precision floating-point fused negated multiply-add + * + * @param[in] rs1 Source operand 1 + * @param[in] rs2 Source operand 2 + * @param[in] rs3 Source operand 3 + * @return Result. + **************************************************************************/ +float __attribute__ ((noinline)) riscv_emulate_fnmadds(float rs1, float rs2, float rs3) { + + float opa = subnormal_flush(rs1); + float opb = subnormal_flush(rs2); + float opc = subnormal_flush(rs3); + + float res = -(opa * opb) - opc; + return subnormal_flush(res); +} + + +#endif // neorv32_zfinx_extension_intrinsics_h + \ No newline at end of file diff --git a/Libs/RiscV/NEORV32/sw/example/game_of_life/makefile b/Libs/RiscV/NEORV32/sw/example/game_of_life/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/game_of_life/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/hello_world/makefile b/Libs/RiscV/NEORV32/sw/example/hello_world/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/hello_world/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/example/makefile b/Libs/RiscV/NEORV32/sw/example/makefile new file mode 100644 index 0000000..572b8c2 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/makefile @@ -0,0 +1,71 @@ +################################################################################################# +# << NEORV32 - All-Projects Makefile >> # +# ********************************************************************************************* # +# Make sure to add the riscv GCC compiler's bin folder to your PATH variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2020, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + + +#------------------------------------------------------------------------------- +# Make defaults and targets +#------------------------------------------------------------------------------- +.SUFFIXES: +.DEFAULT_GOAL := help + +TOPTARGETS := exe clean_all check info all + +SUBDIRS := $(wildcard */.) +# ignore dummy folders (starting with '~') +DUMMYDIRS := $(wildcard ~*/.) +SUBDIRS := $(filter-out $(DUMMYDIRS), $(SUBDIRS)) + +$(TOPTARGETS): $(SUBDIRS) +$(SUBDIRS): + @set -e + @$(MAKE) -C $@ $(MAKECMDGOALS) + +.PHONY: $(TOPTARGETS) $(SUBDIRS) + + +#------------------------------------------------------------------------------- +# Help +#------------------------------------------------------------------------------- +help: + @echo "Build / clean up all projects" + @echo "Targets:" + @echo " help - show this text" + @echo " check - check toolchain" + @echo " info - show makefile configuration" + @echo " exe - create executables from all projects" + @echo " all - create executables and boot images from all projects" + @echo " clean_all - clean up everything" + diff --git a/Libs/RiscV/NEORV32/sw/example/processor_check/makefile b/Libs/RiscV/NEORV32/sw/example/processor_check/makefile new file mode 100644 index 0000000..cd8a97a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/example/processor_check/makefile @@ -0,0 +1,40 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + +# Modify this variable to fit your NEORV32 setup (neorv32 home folder) +NEORV32_HOME ?= ../../.. + +include $(NEORV32_HOME)/sw/common/common.mk diff --git a/Libs/RiscV/NEORV32/sw/image_gen/uart_upload.sh b/Libs/RiscV/NEORV32/sw/image_gen/uart_upload.sh new file mode 100644 index 0000000..0d6ab76 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/image_gen/uart_upload.sh @@ -0,0 +1,58 @@ +#!/bin/sh + +set -e + +# Simple script to upload executable to bootloader + +if [ $# -ne 2 ] +then + echo "Upload image via serial port (UART) to the NEORV32 bootloader." + echo "Reset processor before starting the upload." + echo "Usage: [sudo] sh uart_upload.sh " + echo "Example: sh uart_upload.sh /dev/ttyS6 neorv32_exe.bin" + exit +fi + +# configure serial port +stty -F "$1" 19200 -hup raw -echo -echoe -echok -echoctl -echoke -crtscts cs8 -cstopb noflsh clocal cread + +# trigger fast upload mode and get response +exec 3<$1 # redirect serial output to fd 3 + cat <&3 > uart_upload.response.dat & # redirect serial output to file + PID=$! # save pid to kill cat + printf "u" > $1 # send upload command to serial port + sleep 0.5s # wait for bootloader response + kill $PID # kill cat process + +exec 3<&- # free fd 3 + +# check response +if ! grep -Fq "Awaiting neorv32_exe.bin" uart_upload.response.dat; +then + echo "Bootloader response error." + echo "Reset processor before starting the upload." + rm -f uart_upload.response.dat + exit +fi + +# send executable and get repsonse +echo -n "Uploading... " +exec 3<$1 # redirect serial output to fd 3 + cat <&3 > uart_upload.response.dat & # redirect serial output to file + PID=$! # save pid to kill cat + cat "$2" > "$1" # send executable to serial port + sleep 3s # wait for bootloader response + kill $PID # kill cat process + +exec 3<&- # free fd 3 + +# check response +if ! grep -Fq "OK" uart_upload.response.dat; +then + echo "Upload error." + rm -f uart_upload.response.dat + exit +fi + +rm -f uart_upload.response.dat +echo "Done." diff --git a/Libs/RiscV/NEORV32/sw/isa-test/common.mk b/Libs/RiscV/NEORV32/sw/isa-test/common.mk new file mode 100644 index 0000000..e272cce --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/common.mk @@ -0,0 +1,74 @@ +ifndef NEORV32_ROOT + $(error NEORV32_ROOT is undefined) +endif + +NEORV32_LOCAL_RTL ?= $(NEORV32_ROOT)/sim/work + +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +NEORV32_MARCH ?= rv32i +NEORV32_MABI ?= ilp32 + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=$(NEORV32_MARCH) -mabi=$(NEORV32_MABI) + +NEORV32_LINK ?= link.imem_rom.ld + +COMPILE_TARGET ?= \ + $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + $$(RISCV_TARGET_FLAGS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/$(NEORV32_LINK) \ + $$(<) -o $$@ + +NEORV32_CPU_EXTENSION_RISCV_C ?= false +NEORV32_CPU_EXTENSION_RISCV_E ?= false +NEORV32_CPU_EXTENSION_RISCV_M ?= false +NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= false +NEORV32_MEM_INT_IMEM_SIZE ?= '2097152' + +NEORV32_SOFTWARE_EXAMPLE ?= $(NEORV32_ROOT)/sw/example/blink_led + +ifeq ($(NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI), true) +RUN_TARGET ?= \ + echo "copying/using SIM-only IMEM (pre-initialized RAM!)"; \ + rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \ + cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.iram.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; +else +RUN_TARGET ?= \ + echo "copying/using SIM-only IMEM (pre-initialized ROM!)"; \ + rm -f $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; \ + cp -f $(NEORV32_ROOT)/sim/simple/neorv32_imem.simple.vhd $(NEORV32_LOCAL_RTL)/core/mem/neorv32_imem.default.vhd; +endif + +RUN_TARGET += \ + cd $(work_dir_isa); \ + echo ">"; \ + rm -f $(NEORV32_ROOT)/sim/*.out; \ + make -C $(NEORV32_SOFTWARE_EXAMPLE) main.elf; \ + cp -f $< $(NEORV32_SOFTWARE_EXAMPLE)/main.elf; \ + make -C $(NEORV32_SOFTWARE_EXAMPLE) main.bin install; \ + touch $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out; \ + GHDL_DEVNULL=true $(shell which time) -v $(NEORV32_ROOT)/sim/simple/ghdl.run.sh \ + --stop-time=$(SIM_TIME) \ + -gCPU_EXTENSION_RISCV_A=false \ + -gCPU_EXTENSION_RISCV_C=$(NEORV32_CPU_EXTENSION_RISCV_C) \ + -gCPU_EXTENSION_RISCV_E=$(NEORV32_CPU_EXTENSION_RISCV_E) \ + -gCPU_EXTENSION_RISCV_M=$(NEORV32_CPU_EXTENSION_RISCV_M) \ + -gCPU_EXTENSION_RISCV_U=false \ + -gCPU_EXTENSION_RISCV_Zicsr=true \ + -gCPU_EXTENSION_RISCV_Zifencei=true \ + -gEXT_IMEM_C=false \ + -gMEM_INT_IMEM_SIZE=$(NEORV32_MEM_INT_IMEM_SIZE); \ + cp $(NEORV32_ROOT)/sim/simple/neorv32.uart0.sim_mode.data.out $(*).signature.output; \ + echo "<"; diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/README.md b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/README.md new file mode 100644 index 0000000..d263a24 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/README.md @@ -0,0 +1,28 @@ +# NEORV32 Port for running the RISC-V Architecture Tests + + +The following tasks are executed by the device makefiles: + +* replace the original processor's IMEM rtl file by a simulation-optimized IMEM (ROM!) +* `sed` command is used to modify the default testbench (`neorv32/sim/neorv32_tb.simple.vhd`): + * enable/disable the required `CPU_EXTENSION_RISCV_xxx` VHDL configuration generics in the testbench (`neorv32/sim/neorv32_tb.simple.vhd`) + * set the processor memory configuration +* compile test code and install application image to processor's `rtl/core` folder + * compilation uses the `link.imem_rom.ld` linker script as default; code (the test code) is executed from simulation-optimized IMEM (which is read-only); data including signature is stored to DMEM + * certain areas in the DMEM are initialized using port code in `model_test.h` (`RVTEST` = 0xbabecafe and `SIGNATURE` = 0xdeadbeef); can be disabled using `RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT` +* the processor is simulated using the default testbench +* the results are dumped via the SIM_MODE feature of UART0 + * the according code can be found in the `RVMODEL_HALT` macro in `model_test.h` + * data output (the "signature") is zero-padded to be always a multiple of 16 bytes + + +**Notes** + +:warning: The `Zifencei` test requires the r/w/e capabilities of the original IMEM rtl file. +Hence, the original file is restored for this test. Also, this test uses `link.imem_ram.ld` as linker script since the +IMEM is used as RAM to allow self-modifying code. + +:information_source: The `RVMODEL_BOOT` macro in `model_test.h` provides a simple "dummy trap handler" that just advances +to the next instruction. This trap handler is required for some `C` tests as the NEORV32 will raise an illegal instruction +exception for **all** unimplemented instructions. The trap handler can be overriden (by changing `mtval` CSR) if a test +uses the defualt trap handler of the test framework. diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/C/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/C/Makefile.include new file mode 100644 index 0000000..36d296e --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/C/Makefile.include @@ -0,0 +1,6 @@ +NEORV32_MARCH ?= rv32ec +NEORV32_MABI ?= ilp32e +NEORV32_CPU_EXTENSION_RISCV_C ?= true +NEORV32_CPU_EXTENSION_RISCV_E ?= true + +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/E/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/E/Makefile.include new file mode 100644 index 0000000..e797e8c --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/E/Makefile.include @@ -0,0 +1,5 @@ +NEORV32_MARCH ?= rv32e +NEORV32_MABI ?= ilp32e +NEORV32_CPU_EXTENSION_RISCV_E ?= true + +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/M/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/M/Makefile.include new file mode 100644 index 0000000..e3623b3 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32e_unratified/M/Makefile.include @@ -0,0 +1,6 @@ +NEORV32_MARCH ?= rv32em +NEORV32_MABI ?= ilp32e +NEORV32_CPU_EXTENSION_RISCV_E ?= true +NEORV32_CPU_EXTENSION_RISCV_M ?= true + +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/C/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/C/Makefile.include new file mode 100644 index 0000000..d699665 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/C/Makefile.include @@ -0,0 +1,4 @@ +NEORV32_MARCH ?= rv32ic +NEORV32_CPU_EXTENSION_RISCV_C ?= true + +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/I/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/I/Makefile.include new file mode 100644 index 0000000..9e41632 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/I/Makefile.include @@ -0,0 +1 @@ +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/M/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/M/Makefile.include new file mode 100644 index 0000000..523d7b3 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/M/Makefile.include @@ -0,0 +1,4 @@ +NEORV32_MARCH ?= rv32im +NEORV32_CPU_EXTENSION_RISCV_M ?= true + +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/Zifencei/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/Zifencei/Makefile.include new file mode 100644 index 0000000..bbc15b3 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/Zifencei/Makefile.include @@ -0,0 +1,6 @@ +NEORV32_MARCH ?= rv32im +NEORV32_LINK ?= link.imem_ram.ld +NEORV32_MEM_INT_IMEM_SIZE ?= '16384' +NEORV32_CPU_EXTENSION_RISCV_ZIFENCEI ?= true + +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/privilege/Makefile.include b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/privilege/Makefile.include new file mode 100644 index 0000000..c6cd2e5 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/device/rv32i_m/privilege/Makefile.include @@ -0,0 +1,3 @@ +NEORV32_CPU_EXTENSION_RISCV_C ?= true + +include $(NEORV32_ROOT)/sw/isa-test/common.mk diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_ram.ld b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_ram.ld new file mode 100644 index 0000000..bc8be81 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_ram.ld @@ -0,0 +1,22 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(rvtest_entry_point) + +SECTIONS +{ + . = 0x00000000; + .text : + { + *(.text.init) + . = ALIGN(0x1000); + *(.text) + . = ALIGN(0x1000); + *(.tohost) + *(.data) + *(.data.string) + *(.bss) + . = ALIGN(0x1000); + + _end = .; + } +} + diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_rom.ld b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_rom.ld new file mode 100644 index 0000000..0e41dd7 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/link.imem_rom.ld @@ -0,0 +1,26 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(rvtest_entry_point) + +SECTIONS +{ + . = 0x00000000; + .text : + { + *(.text.init) + . = ALIGN(0x1000); + *(.text) + . = ALIGN(0x1000); + _end = .; + } + + . = 0x80000000; + .data : + { + . = ALIGN(0x1000); + *(.tohost) + *(.data) + *(.data.string) + *(.bss) + } +} + diff --git a/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/model_test.h b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/model_test.h new file mode 100644 index 0000000..72a9255 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/isa-test/port-neorv32/model_test.h @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: BSD-3-Clause + +// Modified by Stephan Nolting for the NEORV32 Processor + +#ifndef _COMPLIANCE_MODEL_H +#define _COMPLIANCE_MODEL_H + +#define RVMODEL_DATA_SECTION \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +//RV_COMPLIANCE_HALT +// neorv32: this will dump the results via the UART0_SIM_MODE data file output +// neorv32: due to the modifications on "end_signature" (not 4-aligned) we need to make sure we output a 4-aligned number of data here +// neorv32: -> for zero-padding of the rest of the SIGNATURE section +#define RVMODEL_HALT \ + signature_dump: \ + la a0, begin_signature; \ + la a1, end_signature; \ + li a2, 0xFFFFFFA4; \ + signature_dump_loop: \ + beq a0, a1, signature_dump_padding; \ + lw t0, 0(a0); \ + sw t0, 0(a2); \ + addi a0, a0, 4; \ + j signature_dump_loop; \ +nop; \ +nop; \ + signature_dump_padding: \ + andi a0, a1, 0x0000000C; \ + beq a0, zero, signature_dump_end; \ + li t0, 16; \ + sub a0, t0, a0; \ + signature_dump_padding_loop: \ + beq a0, zero, signature_dump_end; \ + sw zero, 0(a2); \ + addi a0, a0, -4; \ + j signature_dump_padding_loop; \ + signature_dump_end: \ + j signature_dump_end + +//TODO: declare the start of your signature region here. Nothing else to be used here. +// The .align 4 ensures that the signature ends at a 16-byte boundary +#define RVMODEL_DATA_BEGIN \ + .align 4; .global begin_signature; begin_signature: + +//TODO: declare the end of the signature region here. Add other target specific contents here. +//neorv32: DO NOT use align_4 here! end_signature is used to indicate the actual "number" of signature words +#define RVMODEL_DATA_END \ + .global end_signature; end_signature: \ + RVMODEL_DATA_SECTION + +//RVMODEL_BOOT +// neorv32: enable UART0 (ctrl(28)) and enable UART0_SIM_MODE (ctrl(12)) +// neorv32: initialize the complete RVTEST_DATA section in data RAM (DMEM) with 0xBABECAFE +// neorv32: initialize the complete SIGNATURE section (that is a multiple of four 32-bit entries) in data RAM (DMEM) with 0xDEADBEEF +// neorv32: this code also provides a dummy trap handler that just moves on to the next instruction +// neorv32: -> this trap handler can be overridden by the compliance-suite by modifying mtval +// neorv32: -> the dummy trap handler is required to deal with the neorv32 X extension (-> all illegal/undefined instruction trigger an exception) +#ifdef NEORV32_NO_DATA_INIT +// ------------------------- WITHOUT DATA INIT ------------------------- +#define RVMODEL_BOOT \ + core_init: \ + la x1, core_dummy_trap_handler; \ + csrw mtvec, x1; \ + csrw mie, x0; \ + j uart0_sim_mode_init; \ +nop; \ +nop; \ + .balign 4; \ + core_dummy_trap_handler: \ + csrw mscratch, sp; \ + la sp, end_signature; \ + addi sp, sp, 32; \ + sw x8, 0(sp); \ + sw x9, 4(sp); \ + csrr x8, mcause; \ + blt x8, zero, core_dummy_trap_handler_irq; \ + csrr x8, mepc; \ + core_dummy_trap_handler_exc_c_check: \ + lh x9, 0(x8); \ + andi x9, x9, 3; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + addi x8, zero, 3; \ + bne x8, x9, core_dummy_trap_handler_irq; \ + core_dummy_trap_handler_exc_uncrompressed: \ + csrr x8, mepc; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + core_dummy_trap_handler_irq: \ + lw x9, 0(sp); \ + lw x8, 4(sp); \ + csrr sp, mscratch; \ + mret; \ +nop; \ +nop; \ + uart0_sim_mode_init: \ + li a0, 0xFFFFFFA0; \ + sw zero, 0(a0); \ + li a1, 1 << 28; \ + li a2, 1 << 12; \ + or a1, a1, a2; \ + sw a1, 0(a0); + +#else + +// ------------------------- WITH DATA INIT ------------------------- +#define RVMODEL_BOOT \ + core_init: \ + la x1, core_dummy_trap_handler; \ + csrw mtvec, x1; \ + csrw mie, x0; \ +nop; \ +nop; \ + init_rvtest_data: \ + la a0, rvtest_data_begin; \ + la a1, rvtest_data_end; \ + li a2, 0xBABECAFE; \ + init_rvtest_data_loop: \ + beq a0, a1, init_rvtest_data_loop_end; \ + sw a2, 0(a0); \ + addi a0, a0, 4; \ + j init_rvtest_data_loop; \ + init_rvtest_data_loop_end: \ +nop; \ +nop; \ + init_signature: \ + la a0, begin_signature; \ + la a1, end_signature; \ + li a2, 0xDEADBEEF; \ + init_signature_loop: \ + beq a0, a1, init_signature_loop_end; \ + sw a2, 0(a0); \ + addi a0, a0, 4; \ + j init_signature_loop; \ + init_signature_loop_end: \ + j uart0_sim_mode_init; \ +nop; \ +nop; \ + .balign 4; \ + core_dummy_trap_handler: \ + csrw mscratch, sp; \ + la sp, end_signature; \ + addi sp, sp, 32; \ + sw x8, 0(sp); \ + sw x9, 4(sp); \ + csrr x8, mcause; \ + blt x8, zero, core_dummy_trap_handler_irq; \ + csrr x8, mepc; \ + core_dummy_trap_handler_exc_c_check: \ + lh x9, 0(x8); \ + andi x9, x9, 3; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + addi x8, zero, 3; \ + bne x8, x9, core_dummy_trap_handler_irq; \ + core_dummy_trap_handler_exc_uncrompressed: \ + csrr x8, mepc; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + core_dummy_trap_handler_irq: \ + lw x9, 0(sp); \ + lw x8, 4(sp); \ + csrr sp, mscratch; \ + mret; \ +nop; \ +nop; \ + uart0_sim_mode_init: \ + li a0, 0xFFFFFFA0; \ + sw zero, 0(a0); \ + li a1, 1 << 28; \ + li a2, 1 << 12; \ + or a1, a1, a2; \ + sw a1, 0(a0); + +#endif + + +//RVTEST_IO_INIT +#define RVMODEL_IO_INIT +//RVTEST_IO_WRITE_STR +#define RVMODEL_IO_WRITE_STR(_R, _STR) +//RVTEST_IO_CHECK +#define RVMODEL_IO_CHECK() + +//RVTEST_IO_ASSERT_GPR_EQ +#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) +//RVTEST_IO_ASSERT_SFPR_EQ +#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) +//RVTEST_IO_ASSERT_DFPR_EQ +#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +// TODO: specify the routine for setting machine software interrupt +#define RVMODEL_SET_MSW_INT + +// TODO: specify the routine for clearing machine software interrupt +#define RVMODEL_CLEAR_MSW_INT + +// TODO: specify the routine for clearing machine timer interrupt +#define RVMODEL_CLEAR_MTIMER_INT + +// TODO: specify the routine for clearing machine external interrupt +#define RVMODEL_CLEAR_MEXT_INT + +#endif // _COMPLIANCE_MODEL_H diff --git a/Libs/RiscV/NEORV32/sw/lib/README.md b/Libs/RiscV/NEORV32/sw/lib/README.md new file mode 100644 index 0000000..b29f0ea --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/README.md @@ -0,0 +1,6 @@ +## NEORV32 Core Library + +This folder provides the hardware abstraction layer (HAL) libraries for the CPU itself and the individual processor modules (peripheral/IO devices). + +The `source` folder contains the actual C-code hardware driver functions (*.c*) while the `include` folder provides the according header files (*.h). +Application programs should only include the *main NEORV32 define file* `include/neorv32.h`. This file automatically includes all other provided header files. diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32.h new file mode 100644 index 0000000..636d8fc --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32.h @@ -0,0 +1,1311 @@ +// ################################################################################################# +// # << NEORV32: neorv32.h - Main Core Library File >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32.h + * @author Stephan Nolting + * + * @brief Main NEORV32 core library include file. + **************************************************************************/ + +#ifndef neorv32_h +#define neorv32_h + +#ifdef __cplusplus +extern "C" { +#endif + + +// Standard libraries +#include +#include +#include + + +/**********************************************************************//** + * Available CPU Control and Status Registers (CSRs) + **************************************************************************/ +enum NEORV32_CSR_enum { + CSR_FFLAGS = 0x001, /**< 0x001 - fflags (r/w): Floating-point accrued exception flags */ + CSR_FRM = 0x002, /**< 0x002 - frm (r/w): Floating-point dynamic rounding mode */ + CSR_FCSR = 0x003, /**< 0x003 - fcsr (r/w): Floating-point control/staturs register (frm + fflags) */ + + CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */ + CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */ + CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */ + CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */ + CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */ + + CSR_MENVCFG = 0x30a, /**< 0x30a - menvcfg (r/-): Machine environment configuration register */ + + CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/w): Machine status register - high word */ + + CSR_MENVCFGH = 0x31a, /**< 0x31a - menvcfgh (r/-): Machine environment configuration register - high word */ + + CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */ + + CSR_MHPMEVENT3 = 0x323, /**< 0x323 - mhpmevent3 (r/w): Machine hardware performance monitor event selector 3 */ + CSR_MHPMEVENT4 = 0x324, /**< 0x324 - mhpmevent4 (r/w): Machine hardware performance monitor event selector 4 */ + CSR_MHPMEVENT5 = 0x325, /**< 0x325 - mhpmevent5 (r/w): Machine hardware performance monitor event selector 5 */ + CSR_MHPMEVENT6 = 0x326, /**< 0x326 - mhpmevent6 (r/w): Machine hardware performance monitor event selector 6 */ + CSR_MHPMEVENT7 = 0x327, /**< 0x327 - mhpmevent7 (r/w): Machine hardware performance monitor event selector 7 */ + CSR_MHPMEVENT8 = 0x328, /**< 0x328 - mhpmevent8 (r/w): Machine hardware performance monitor event selector 8 */ + CSR_MHPMEVENT9 = 0x329, /**< 0x329 - mhpmevent9 (r/w): Machine hardware performance monitor event selector 9 */ + CSR_MHPMEVENT10 = 0x32a, /**< 0x32a - mhpmevent10 (r/w): Machine hardware performance monitor event selector 10 */ + CSR_MHPMEVENT11 = 0x32b, /**< 0x32b - mhpmevent11 (r/w): Machine hardware performance monitor event selector 11 */ + CSR_MHPMEVENT12 = 0x32c, /**< 0x32c - mhpmevent12 (r/w): Machine hardware performance monitor event selector 12 */ + CSR_MHPMEVENT13 = 0x32d, /**< 0x32d - mhpmevent13 (r/w): Machine hardware performance monitor event selector 13 */ + CSR_MHPMEVENT14 = 0x32e, /**< 0x32e - mhpmevent14 (r/w): Machine hardware performance monitor event selector 14 */ + CSR_MHPMEVENT15 = 0x32f, /**< 0x32f - mhpmevent15 (r/w): Machine hardware performance monitor event selector 15 */ + CSR_MHPMEVENT16 = 0x330, /**< 0x330 - mhpmevent16 (r/w): Machine hardware performance monitor event selector 16 */ + CSR_MHPMEVENT17 = 0x331, /**< 0x331 - mhpmevent17 (r/w): Machine hardware performance monitor event selector 17 */ + CSR_MHPMEVENT18 = 0x332, /**< 0x332 - mhpmevent18 (r/w): Machine hardware performance monitor event selector 18 */ + CSR_MHPMEVENT19 = 0x333, /**< 0x333 - mhpmevent19 (r/w): Machine hardware performance monitor event selector 19 */ + CSR_MHPMEVENT20 = 0x334, /**< 0x334 - mhpmevent20 (r/w): Machine hardware performance monitor event selector 20 */ + CSR_MHPMEVENT21 = 0x335, /**< 0x335 - mhpmevent21 (r/w): Machine hardware performance monitor event selector 21 */ + CSR_MHPMEVENT22 = 0x336, /**< 0x336 - mhpmevent22 (r/w): Machine hardware performance monitor event selector 22 */ + CSR_MHPMEVENT23 = 0x337, /**< 0x337 - mhpmevent23 (r/w): Machine hardware performance monitor event selector 23 */ + CSR_MHPMEVENT24 = 0x338, /**< 0x338 - mhpmevent24 (r/w): Machine hardware performance monitor event selector 24 */ + CSR_MHPMEVENT25 = 0x339, /**< 0x339 - mhpmevent25 (r/w): Machine hardware performance monitor event selector 25 */ + CSR_MHPMEVENT26 = 0x33a, /**< 0x33a - mhpmevent26 (r/w): Machine hardware performance monitor event selector 26 */ + CSR_MHPMEVENT27 = 0x33b, /**< 0x33b - mhpmevent27 (r/w): Machine hardware performance monitor event selector 27 */ + CSR_MHPMEVENT28 = 0x33c, /**< 0x33c - mhpmevent28 (r/w): Machine hardware performance monitor event selector 28 */ + CSR_MHPMEVENT29 = 0x33d, /**< 0x33d - mhpmevent29 (r/w): Machine hardware performance monitor event selector 29 */ + CSR_MHPMEVENT30 = 0x33e, /**< 0x33e - mhpmevent30 (r/w): Machine hardware performance monitor event selector 30 */ + CSR_MHPMEVENT31 = 0x33f, /**< 0x33f - mhpmevent31 (r/w): Machine hardware performance monitor event selector 31 */ + + CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */ + CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */ + CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */ + CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */ + CSR_MIP = 0x344, /**< 0x344 - mip (r/-): Machine interrupt pending register */ + + CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */ + CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */ + CSR_PMPCFG2 = 0x3a2, /**< 0x3a2 - pmpcfg2 (r/w): Physical memory protection configuration register 2 */ + CSR_PMPCFG3 = 0x3a3, /**< 0x3a3 - pmpcfg3 (r/w): Physical memory protection configuration register 3 */ + CSR_PMPCFG4 = 0x3a4, /**< 0x3a4 - pmpcfg4 (r/w): Physical memory protection configuration register 4 */ + CSR_PMPCFG5 = 0x3a5, /**< 0x3a5 - pmpcfg5 (r/w): Physical memory protection configuration register 5 */ + CSR_PMPCFG6 = 0x3a6, /**< 0x3a6 - pmpcfg6 (r/w): Physical memory protection configuration register 6 */ + CSR_PMPCFG7 = 0x3a7, /**< 0x3a7 - pmpcfg7 (r/w): Physical memory protection configuration register 7 */ + CSR_PMPCFG8 = 0x3a8, /**< 0x3a8 - pmpcfg8 (r/w): Physical memory protection configuration register 8 */ + CSR_PMPCFG9 = 0x3a9, /**< 0x3a9 - pmpcfg9 (r/w): Physical memory protection configuration register 9 */ + CSR_PMPCFG10 = 0x3aa, /**< 0x3aa - pmpcfg10 (r/w): Physical memory protection configuration register 10 */ + CSR_PMPCFG11 = 0x3ab, /**< 0x3ab - pmpcfg11 (r/w): Physical memory protection configuration register 11 */ + CSR_PMPCFG12 = 0x3ac, /**< 0x3ac - pmpcfg12 (r/w): Physical memory protection configuration register 12 */ + CSR_PMPCFG13 = 0x3ad, /**< 0x3ad - pmpcfg13 (r/w): Physical memory protection configuration register 13 */ + CSR_PMPCFG14 = 0x3ae, /**< 0x3ae - pmpcfg14 (r/w): Physical memory protection configuration register 14 */ + CSR_PMPCFG15 = 0x3af, /**< 0x3af - pmpcfg15 (r/w): Physical memory protection configuration register 15 */ + + CSR_PMPADDR0 = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */ + CSR_PMPADDR1 = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */ + CSR_PMPADDR2 = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */ + CSR_PMPADDR3 = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */ + CSR_PMPADDR4 = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */ + CSR_PMPADDR5 = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */ + CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */ + CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */ + CSR_PMPADDR8 = 0x3b8, /**< 0x3b8 - pmpaddr8 (r/w): Physical memory protection address register 8 */ + CSR_PMPADDR9 = 0x3b9, /**< 0x3b9 - pmpaddr9 (r/w): Physical memory protection address register 9 */ + CSR_PMPADDR10 = 0x3ba, /**< 0x3ba - pmpaddr10 (r/w): Physical memory protection address register 10 */ + CSR_PMPADDR11 = 0x3bb, /**< 0x3bb - pmpaddr11 (r/w): Physical memory protection address register 11 */ + CSR_PMPADDR12 = 0x3bc, /**< 0x3bc - pmpaddr12 (r/w): Physical memory protection address register 12 */ + CSR_PMPADDR13 = 0x3bd, /**< 0x3bd - pmpaddr13 (r/w): Physical memory protection address register 13 */ + CSR_PMPADDR14 = 0x3be, /**< 0x3be - pmpaddr14 (r/w): Physical memory protection address register 14 */ + CSR_PMPADDR15 = 0x3bf, /**< 0x3bf - pmpaddr15 (r/w): Physical memory protection address register 15 */ + CSR_PMPADDR16 = 0x3c0, /**< 0x3c0 - pmpaddr16 (r/w): Physical memory protection address register 16 */ + CSR_PMPADDR17 = 0x3c1, /**< 0x3c1 - pmpaddr17 (r/w): Physical memory protection address register 17 */ + CSR_PMPADDR18 = 0x3c2, /**< 0x3c2 - pmpaddr18 (r/w): Physical memory protection address register 18 */ + CSR_PMPADDR19 = 0x3c3, /**< 0x3c3 - pmpaddr19 (r/w): Physical memory protection address register 19 */ + CSR_PMPADDR20 = 0x3c4, /**< 0x3c4 - pmpaddr20 (r/w): Physical memory protection address register 20 */ + CSR_PMPADDR21 = 0x3c5, /**< 0x3c5 - pmpaddr21 (r/w): Physical memory protection address register 21 */ + CSR_PMPADDR22 = 0x3c6, /**< 0x3c6 - pmpaddr22 (r/w): Physical memory protection address register 22 */ + CSR_PMPADDR23 = 0x3c7, /**< 0x3c7 - pmpaddr23 (r/w): Physical memory protection address register 23 */ + CSR_PMPADDR24 = 0x3c8, /**< 0x3c8 - pmpaddr24 (r/w): Physical memory protection address register 24 */ + CSR_PMPADDR25 = 0x3c9, /**< 0x3c9 - pmpaddr25 (r/w): Physical memory protection address register 25 */ + CSR_PMPADDR26 = 0x3ca, /**< 0x3ca - pmpaddr26 (r/w): Physical memory protection address register 26 */ + CSR_PMPADDR27 = 0x3cb, /**< 0x3cb - pmpaddr27 (r/w): Physical memory protection address register 27 */ + CSR_PMPADDR28 = 0x3cc, /**< 0x3cc - pmpaddr28 (r/w): Physical memory protection address register 28 */ + CSR_PMPADDR29 = 0x3cd, /**< 0x3cd - pmpaddr29 (r/w): Physical memory protection address register 29 */ + CSR_PMPADDR30 = 0x3ce, /**< 0x3ce - pmpaddr30 (r/w): Physical memory protection address register 30 */ + CSR_PMPADDR31 = 0x3cf, /**< 0x3cf - pmpaddr31 (r/w): Physical memory protection address register 31 */ + CSR_PMPADDR32 = 0x3d0, /**< 0x3d0 - pmpaddr32 (r/w): Physical memory protection address register 32 */ + CSR_PMPADDR33 = 0x3d1, /**< 0x3d1 - pmpaddr33 (r/w): Physical memory protection address register 33 */ + CSR_PMPADDR34 = 0x3d2, /**< 0x3d2 - pmpaddr34 (r/w): Physical memory protection address register 34 */ + CSR_PMPADDR35 = 0x3d3, /**< 0x3d3 - pmpaddr35 (r/w): Physical memory protection address register 35 */ + CSR_PMPADDR36 = 0x3d4, /**< 0x3d4 - pmpaddr36 (r/w): Physical memory protection address register 36 */ + CSR_PMPADDR37 = 0x3d5, /**< 0x3d5 - pmpaddr37 (r/w): Physical memory protection address register 37 */ + CSR_PMPADDR38 = 0x3d6, /**< 0x3d6 - pmpaddr38 (r/w): Physical memory protection address register 38 */ + CSR_PMPADDR39 = 0x3d7, /**< 0x3d7 - pmpaddr39 (r/w): Physical memory protection address register 39 */ + CSR_PMPADDR40 = 0x3d8, /**< 0x3d8 - pmpaddr40 (r/w): Physical memory protection address register 40 */ + CSR_PMPADDR41 = 0x3d9, /**< 0x3d9 - pmpaddr41 (r/w): Physical memory protection address register 41 */ + CSR_PMPADDR42 = 0x3da, /**< 0x3da - pmpaddr42 (r/w): Physical memory protection address register 42 */ + CSR_PMPADDR43 = 0x3db, /**< 0x3db - pmpaddr43 (r/w): Physical memory protection address register 43 */ + CSR_PMPADDR44 = 0x3dc, /**< 0x3dc - pmpaddr44 (r/w): Physical memory protection address register 44 */ + CSR_PMPADDR45 = 0x3dd, /**< 0x3dd - pmpaddr45 (r/w): Physical memory protection address register 45 */ + CSR_PMPADDR46 = 0x3de, /**< 0x3de - pmpaddr46 (r/w): Physical memory protection address register 46 */ + CSR_PMPADDR47 = 0x3df, /**< 0x3df - pmpaddr47 (r/w): Physical memory protection address register 47 */ + CSR_PMPADDR48 = 0x3e0, /**< 0x3e0 - pmpaddr48 (r/w): Physical memory protection address register 48 */ + CSR_PMPADDR49 = 0x3e1, /**< 0x3e1 - pmpaddr49 (r/w): Physical memory protection address register 49 */ + CSR_PMPADDR50 = 0x3e2, /**< 0x3e2 - pmpaddr50 (r/w): Physical memory protection address register 50 */ + CSR_PMPADDR51 = 0x3e3, /**< 0x3e3 - pmpaddr51 (r/w): Physical memory protection address register 51 */ + CSR_PMPADDR52 = 0x3e4, /**< 0x3e4 - pmpaddr52 (r/w): Physical memory protection address register 52 */ + CSR_PMPADDR53 = 0x3e5, /**< 0x3e5 - pmpaddr53 (r/w): Physical memory protection address register 53 */ + CSR_PMPADDR54 = 0x3e6, /**< 0x3e6 - pmpaddr54 (r/w): Physical memory protection address register 54 */ + CSR_PMPADDR55 = 0x3e7, /**< 0x3e7 - pmpaddr55 (r/w): Physical memory protection address register 55 */ + CSR_PMPADDR56 = 0x3e8, /**< 0x3e8 - pmpaddr56 (r/w): Physical memory protection address register 56 */ + CSR_PMPADDR57 = 0x3e9, /**< 0x3e9 - pmpaddr57 (r/w): Physical memory protection address register 57 */ + CSR_PMPADDR58 = 0x3ea, /**< 0x3ea - pmpaddr58 (r/w): Physical memory protection address register 58 */ + CSR_PMPADDR59 = 0x3eb, /**< 0x3eb - pmpaddr59 (r/w): Physical memory protection address register 59 */ + CSR_PMPADDR60 = 0x3ec, /**< 0x3ec - pmpaddr60 (r/w): Physical memory protection address register 60 */ + CSR_PMPADDR61 = 0x3ed, /**< 0x3ed - pmpaddr61 (r/w): Physical memory protection address register 61 */ + CSR_PMPADDR62 = 0x3ee, /**< 0x3ee - pmpaddr62 (r/w): Physical memory protection address register 62 */ + CSR_PMPADDR63 = 0x3ef, /**< 0x3ef - pmpaddr63 (r/w): Physical memory protection address register 63 */ + + CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */ + CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */ + + CSR_MHPMCOUNTER3 = 0xb03, /**< 0xb03 - mhpmcounter3 (r/w): Machine hardware performance monitor 3 counter low word */ + CSR_MHPMCOUNTER4 = 0xb04, /**< 0xb04 - mhpmcounter4 (r/w): Machine hardware performance monitor 4 counter low word */ + CSR_MHPMCOUNTER5 = 0xb05, /**< 0xb05 - mhpmcounter5 (r/w): Machine hardware performance monitor 5 counter low word */ + CSR_MHPMCOUNTER6 = 0xb06, /**< 0xb06 - mhpmcounter6 (r/w): Machine hardware performance monitor 6 counter low word */ + CSR_MHPMCOUNTER7 = 0xb07, /**< 0xb07 - mhpmcounter7 (r/w): Machine hardware performance monitor 7 counter low word */ + CSR_MHPMCOUNTER8 = 0xb08, /**< 0xb08 - mhpmcounter8 (r/w): Machine hardware performance monitor 8 counter low word */ + CSR_MHPMCOUNTER9 = 0xb09, /**< 0xb09 - mhpmcounter9 (r/w): Machine hardware performance monitor 9 counter low word */ + CSR_MHPMCOUNTER10 = 0xb0a, /**< 0xb0a - mhpmcounter10 (r/w): Machine hardware performance monitor 10 counter low word */ + CSR_MHPMCOUNTER11 = 0xb0b, /**< 0xb0b - mhpmcounter11 (r/w): Machine hardware performance monitor 11 counter low word */ + CSR_MHPMCOUNTER12 = 0xb0c, /**< 0xb0c - mhpmcounter12 (r/w): Machine hardware performance monitor 12 counter low word */ + CSR_MHPMCOUNTER13 = 0xb0d, /**< 0xb0d - mhpmcounter13 (r/w): Machine hardware performance monitor 13 counter low word */ + CSR_MHPMCOUNTER14 = 0xb0e, /**< 0xb0e - mhpmcounter14 (r/w): Machine hardware performance monitor 14 counter low word */ + CSR_MHPMCOUNTER15 = 0xb0f, /**< 0xb0f - mhpmcounter15 (r/w): Machine hardware performance monitor 15 counter low word */ + CSR_MHPMCOUNTER16 = 0xb10, /**< 0xb10 - mhpmcounter16 (r/w): Machine hardware performance monitor 16 counter low word */ + CSR_MHPMCOUNTER17 = 0xb11, /**< 0xb11 - mhpmcounter17 (r/w): Machine hardware performance monitor 17 counter low word */ + CSR_MHPMCOUNTER18 = 0xb12, /**< 0xb12 - mhpmcounter18 (r/w): Machine hardware performance monitor 18 counter low word */ + CSR_MHPMCOUNTER19 = 0xb13, /**< 0xb13 - mhpmcounter19 (r/w): Machine hardware performance monitor 19 counter low word */ + CSR_MHPMCOUNTER20 = 0xb14, /**< 0xb14 - mhpmcounter20 (r/w): Machine hardware performance monitor 20 counter low word */ + CSR_MHPMCOUNTER21 = 0xb15, /**< 0xb15 - mhpmcounter21 (r/w): Machine hardware performance monitor 21 counter low word */ + CSR_MHPMCOUNTER22 = 0xb16, /**< 0xb16 - mhpmcounter22 (r/w): Machine hardware performance monitor 22 counter low word */ + CSR_MHPMCOUNTER23 = 0xb17, /**< 0xb17 - mhpmcounter23 (r/w): Machine hardware performance monitor 23 counter low word */ + CSR_MHPMCOUNTER24 = 0xb18, /**< 0xb18 - mhpmcounter24 (r/w): Machine hardware performance monitor 24 counter low word */ + CSR_MHPMCOUNTER25 = 0xb19, /**< 0xb19 - mhpmcounter25 (r/w): Machine hardware performance monitor 25 counter low word */ + CSR_MHPMCOUNTER26 = 0xb1a, /**< 0xb1a - mhpmcounter26 (r/w): Machine hardware performance monitor 26 counter low word */ + CSR_MHPMCOUNTER27 = 0xb1b, /**< 0xb1b - mhpmcounter27 (r/w): Machine hardware performance monitor 27 counter low word */ + CSR_MHPMCOUNTER28 = 0xb1c, /**< 0xb1c - mhpmcounter28 (r/w): Machine hardware performance monitor 28 counter low word */ + CSR_MHPMCOUNTER29 = 0xb1d, /**< 0xb1d - mhpmcounter29 (r/w): Machine hardware performance monitor 29 counter low word */ + CSR_MHPMCOUNTER30 = 0xb1e, /**< 0xb1e - mhpmcounter30 (r/w): Machine hardware performance monitor 30 counter low word */ + CSR_MHPMCOUNTER31 = 0xb1f, /**< 0xb1f - mhpmcounter31 (r/w): Machine hardware performance monitor 31 counter low word */ + + CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */ + CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */ + + CSR_MHPMCOUNTER3H = 0xb83, /**< 0xb83 - mhpmcounter3h (r/w): Machine hardware performance monitor 3 counter high word */ + CSR_MHPMCOUNTER4H = 0xb84, /**< 0xb84 - mhpmcounter4h (r/w): Machine hardware performance monitor 4 counter high word */ + CSR_MHPMCOUNTER5H = 0xb85, /**< 0xb85 - mhpmcounter5h (r/w): Machine hardware performance monitor 5 counter high word */ + CSR_MHPMCOUNTER6H = 0xb86, /**< 0xb86 - mhpmcounter6h (r/w): Machine hardware performance monitor 6 counter high word */ + CSR_MHPMCOUNTER7H = 0xb87, /**< 0xb87 - mhpmcounter7h (r/w): Machine hardware performance monitor 7 counter high word */ + CSR_MHPMCOUNTER8H = 0xb88, /**< 0xb88 - mhpmcounter8h (r/w): Machine hardware performance monitor 8 counter high word */ + CSR_MHPMCOUNTER9H = 0xb89, /**< 0xb89 - mhpmcounter9h (r/w): Machine hardware performance monitor 9 counter high word */ + CSR_MHPMCOUNTER10H = 0xb8a, /**< 0xb8a - mhpmcounter10h (r/w): Machine hardware performance monitor 10 counter high word */ + CSR_MHPMCOUNTER11H = 0xb8b, /**< 0xb8b - mhpmcounter11h (r/w): Machine hardware performance monitor 11 counter high word */ + CSR_MHPMCOUNTER12H = 0xb8c, /**< 0xb8c - mhpmcounter12h (r/w): Machine hardware performance monitor 12 counter high word */ + CSR_MHPMCOUNTER13H = 0xb8d, /**< 0xb8d - mhpmcounter13h (r/w): Machine hardware performance monitor 13 counter high word */ + CSR_MHPMCOUNTER14H = 0xb8e, /**< 0xb8e - mhpmcounter14h (r/w): Machine hardware performance monitor 14 counter high word */ + CSR_MHPMCOUNTER15H = 0xb8f, /**< 0xb8f - mhpmcounter15h (r/w): Machine hardware performance monitor 15 counter high word */ + CSR_MHPMCOUNTER16H = 0xb90, /**< 0xb90 - mhpmcounter16h (r/w): Machine hardware performance monitor 16 counter high word */ + CSR_MHPMCOUNTER17H = 0xb91, /**< 0xb91 - mhpmcounter17h (r/w): Machine hardware performance monitor 17 counter high word */ + CSR_MHPMCOUNTER18H = 0xb92, /**< 0xb92 - mhpmcounter18h (r/w): Machine hardware performance monitor 18 counter high word */ + CSR_MHPMCOUNTER19H = 0xb93, /**< 0xb93 - mhpmcounter19h (r/w): Machine hardware performance monitor 19 counter high word */ + CSR_MHPMCOUNTER20H = 0xb94, /**< 0xb94 - mhpmcounter20h (r/w): Machine hardware performance monitor 20 counter high word */ + CSR_MHPMCOUNTER21H = 0xb95, /**< 0xb95 - mhpmcounter21h (r/w): Machine hardware performance monitor 21 counter high word */ + CSR_MHPMCOUNTER22H = 0xb96, /**< 0xb96 - mhpmcounter22h (r/w): Machine hardware performance monitor 22 counter high word */ + CSR_MHPMCOUNTER23H = 0xb97, /**< 0xb97 - mhpmcounter23h (r/w): Machine hardware performance monitor 23 counter high word */ + CSR_MHPMCOUNTER24H = 0xb98, /**< 0xb98 - mhpmcounter24h (r/w): Machine hardware performance monitor 24 counter high word */ + CSR_MHPMCOUNTER25H = 0xb99, /**< 0xb99 - mhpmcounter25h (r/w): Machine hardware performance monitor 25 counter high word */ + CSR_MHPMCOUNTER26H = 0xb9a, /**< 0xb9a - mhpmcounter26h (r/w): Machine hardware performance monitor 26 counter high word */ + CSR_MHPMCOUNTER27H = 0xb9b, /**< 0xb9b - mhpmcounter27h (r/w): Machine hardware performance monitor 27 counter high word */ + CSR_MHPMCOUNTER28H = 0xb9c, /**< 0xb9c - mhpmcounter28h (r/w): Machine hardware performance monitor 28 counter high word */ + CSR_MHPMCOUNTER29H = 0xb9d, /**< 0xb9d - mhpmcounter29h (r/w): Machine hardware performance monitor 29 counter high word */ + CSR_MHPMCOUNTER30H = 0xb9e, /**< 0xb9e - mhpmcounter30h (r/w): Machine hardware performance monitor 30 counter high word */ + CSR_MHPMCOUNTER31H = 0xb9f, /**< 0xb9f - mhpmcounter31h (r/w): Machine hardware performance monitor 31 counter high word */ + + CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */ + CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */ + CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */ + + CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */ + CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */ + CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */ + + CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */ + CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */ + CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */ + CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */ + CSR_MCONFIGPTR = 0xf15 /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */ +}; + + +/**********************************************************************//** + * CPU mstatus CSR (r/w): Machine status (RISC-V spec.) + **************************************************************************/ +enum NEORV32_CSR_MSTATUS_enum { + CSR_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */ + CSR_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */ + CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */ + CSR_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */ +}; + + +/**********************************************************************//** + * CPU mcounteren CSR (r/w): Machine counter enable (RISC-V spec.) + **************************************************************************/ +enum NEORV32_CSR_MCOUNTEREN_enum { + CSR_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */ + CSR_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */ + CSR_MCOUNTEREN_IR = 2 /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */ +}; + + +/**********************************************************************//** + * CPU mcountinhibit CSR (r/w): Machine counter-inhibit (RISC-V spec.) + **************************************************************************/ +enum NEORV32_CSR_MCOUNTINHIBIT_enum { + CSR_MCOUNTINHIBIT_CY = 0, /**< CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w) */ + CSR_MCOUNTINHIBIT_IR = 2, /**< CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) */ + + CSR_MCOUNTINHIBIT_HPM3 = 3, /**< CPU mcountinhibit CSR (3): HPM3 - Enable auto-increment of hpmcnt3[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM4 = 4, /**< CPU mcountinhibit CSR (4): HPM4 - Enable auto-increment of hpmcnt4[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM5 = 5, /**< CPU mcountinhibit CSR (5): HPM5 - Enable auto-increment of hpmcnt5[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM6 = 6, /**< CPU mcountinhibit CSR (6): HPM6 - Enable auto-increment of hpmcnt6[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM7 = 7, /**< CPU mcountinhibit CSR (7): HPM7 - Enable auto-increment of hpmcnt7[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM8 = 8, /**< CPU mcountinhibit CSR (8): HPM8 - Enable auto-increment of hpmcnt8[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM9 = 9, /**< CPU mcountinhibit CSR (9): HPM9 - Enable auto-increment of hpmcnt9[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM10 = 10, /**< CPU mcountinhibit CSR (10): HPM10 - Enable auto-increment of hpmcnt10[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM11 = 11, /**< CPU mcountinhibit CSR (11): HPM11 - Enable auto-increment of hpmcnt11[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM12 = 12, /**< CPU mcountinhibit CSR (12): HPM12 - Enable auto-increment of hpmcnt12[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM13 = 13, /**< CPU mcountinhibit CSR (13): HPM13 - Enable auto-increment of hpmcnt13[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM14 = 14, /**< CPU mcountinhibit CSR (14): HPM14 - Enable auto-increment of hpmcnt14[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM15 = 15, /**< CPU mcountinhibit CSR (15): HPM15 - Enable auto-increment of hpmcnt15[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM16 = 16, /**< CPU mcountinhibit CSR (16): HPM16 - Enable auto-increment of hpmcnt16[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM17 = 17, /**< CPU mcountinhibit CSR (17): HPM17 - Enable auto-increment of hpmcnt17[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM18 = 18, /**< CPU mcountinhibit CSR (18): HPM18 - Enable auto-increment of hpmcnt18[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM19 = 19, /**< CPU mcountinhibit CSR (19): HPM19 - Enable auto-increment of hpmcnt19[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM20 = 20, /**< CPU mcountinhibit CSR (20): HPM20 - Enable auto-increment of hpmcnt20[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM21 = 21, /**< CPU mcountinhibit CSR (21): HPM21 - Enable auto-increment of hpmcnt21[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM22 = 22, /**< CPU mcountinhibit CSR (22): HPM22 - Enable auto-increment of hpmcnt22[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM23 = 23, /**< CPU mcountinhibit CSR (23): HPM23 - Enable auto-increment of hpmcnt23[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM24 = 24, /**< CPU mcountinhibit CSR (24): HPM24 - Enable auto-increment of hpmcnt24[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM25 = 25, /**< CPU mcountinhibit CSR (25): HPM25 - Enable auto-increment of hpmcnt25[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM26 = 26, /**< CPU mcountinhibit CSR (26): HPM26 - Enable auto-increment of hpmcnt26[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM27 = 27, /**< CPU mcountinhibit CSR (27): HPM27 - Enable auto-increment of hpmcnt27[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM28 = 28, /**< CPU mcountinhibit CSR (28): HPM28 - Enable auto-increment of hpmcnt28[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM29 = 29, /**< CPU mcountinhibit CSR (29): HPM29 - Enable auto-increment of hpmcnt29[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM30 = 30, /**< CPU mcountinhibit CSR (30): HPM30 - Enable auto-increment of hpmcnt30[h] when set (r/w) */ + CSR_MCOUNTINHIBIT_HPM31 = 31 /**< CPU mcountinhibit CSR (31): HPM31 - Enable auto-increment of hpmcnt31[h] when set (r/w) */ +}; + + +/**********************************************************************//** + * CPU mie CSR (r/w): Machine interrupt enable (RISC-V spec.) + **************************************************************************/ +enum NEORV32_CSR_MIE_enum { + CSR_MIE_MSIE = 3, /**< CPU mie CSR (3): MSIE - Machine software interrupt enable (r/w) */ + CSR_MIE_MTIE = 7, /**< CPU mie CSR (7): MTIE - Machine timer interrupt enable bit (r/w) */ + CSR_MIE_MEIE = 11, /**< CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) */ + + CSR_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */ + CSR_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */ + CSR_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */ + CSR_MIE_FIRQ3E = 19, /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */ + CSR_MIE_FIRQ4E = 20, /**< CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w) */ + CSR_MIE_FIRQ5E = 21, /**< CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w) */ + CSR_MIE_FIRQ6E = 22, /**< CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w) */ + CSR_MIE_FIRQ7E = 23, /**< CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w) */ + CSR_MIE_FIRQ8E = 24, /**< CPU mie CSR (24): FIRQ8E - Fast interrupt channel 8 enable bit (r/w) */ + CSR_MIE_FIRQ9E = 25, /**< CPU mie CSR (25): FIRQ9E - Fast interrupt channel 9 enable bit (r/w) */ + CSR_MIE_FIRQ10E = 26, /**< CPU mie CSR (26): FIRQ10E - Fast interrupt channel 10 enable bit (r/w) */ + CSR_MIE_FIRQ11E = 27, /**< CPU mie CSR (27): FIRQ11E - Fast interrupt channel 11 enable bit (r/w) */ + CSR_MIE_FIRQ12E = 28, /**< CPU mie CSR (28): FIRQ12E - Fast interrupt channel 12 enable bit (r/w) */ + CSR_MIE_FIRQ13E = 29, /**< CPU mie CSR (29): FIRQ13E - Fast interrupt channel 13 enable bit (r/w) */ + CSR_MIE_FIRQ14E = 30, /**< CPU mie CSR (30): FIRQ14E - Fast interrupt channel 14 enable bit (r/w) */ + CSR_MIE_FIRQ15E = 31 /**< CPU mie CSR (31): FIRQ15E - Fast interrupt channel 15 enable bit (r/w) */ +}; + + +/**********************************************************************//** + * CPU mip CSR (r/-): Machine interrupt pending (RISC-V spec.) + **************************************************************************/ +enum NEORV32_CSR_MIP_enum { + CSR_MIP_MSIP = 3, /**< CPU mip CSR (3): MSIP - Machine software interrupt pending (r/-) */ + CSR_MIP_MTIP = 7, /**< CPU mip CSR (7): MTIP - Machine timer interrupt pending (r/-) */ + CSR_MIP_MEIP = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */ + + CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */ + CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */ + CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */ + CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */ + CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */ + CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */ + CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */ + CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */ + CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/-) */ + CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/-) */ + CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/-) */ + CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/-) */ + CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/-) */ + CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/-) */ + CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/-) */ + CSR_MIP_FIRQ15P = 31 /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/-) */ +}; + + +/**********************************************************************//** + * CPU misa CSR (r/-): Machine instruction set extensions (RISC-V spec.) + **************************************************************************/ +enum NEORV32_CSR_MISA_enum { + CSR_MISA_A = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/ + CSR_MISA_B = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/ + CSR_MISA_C = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/ + CSR_MISA_D = 3, /**< CPU misa CSR (3): D: Double-precision floating-point extension available (r/-)*/ + CSR_MISA_E = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */ + CSR_MISA_F = 5, /**< CPU misa CSR (5): F: Single-precision floating-point extension available (r/-)*/ + CSR_MISA_I = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */ + CSR_MISA_M = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/ + CSR_MISA_U = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/ + CSR_MISA_X = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */ + CSR_MISA_MXL_LO = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */ + CSR_MISA_MXL_HI = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */ +}; + + +/**********************************************************************//** + * CPU mhpmevent hardware performance monitor events + **************************************************************************/ +enum NEORV32_HPMCNT_EVENT_enum { + HPMCNT_EVENT_CY = 0, /**< CPU mhpmevent CSR (0): Active cycle */ + HPMCNT_EVENT_IR = 2, /**< CPU mhpmevent CSR (2): Retired instruction */ + + HPMCNT_EVENT_CIR = 3, /**< CPU mhpmevent CSR (3): Retired compressed instruction */ + HPMCNT_EVENT_WAIT_IF = 4, /**< CPU mhpmevent CSR (4): Instruction fetch memory wait cycle */ + HPMCNT_EVENT_WAIT_II = 5, /**< CPU mhpmevent CSR (5): Instruction issue wait cycle */ + HPMCNT_EVENT_WAIT_MC = 6, /**< CPU mhpmevent CSR (6): Multi-cycle ALU-operation wait cycle */ + HPMCNT_EVENT_LOAD = 7, /**< CPU mhpmevent CSR (7): Load operation */ + HPMCNT_EVENT_STORE = 8, /**< CPU mhpmevent CSR (8): Store operation */ + HPMCNT_EVENT_WAIT_LS = 9, /**< CPU mhpmevent CSR (9): Load/store memory wait cycle */ + + HPMCNT_EVENT_JUMP = 10, /**< CPU mhpmevent CSR (10): Unconditional jump */ + HPMCNT_EVENT_BRANCH = 11, /**< CPU mhpmevent CSR (11): Conditional branch (taken or not taken) */ + HPMCNT_EVENT_TBRANCH = 12, /**< CPU mhpmevent CSR (12): Conditional taken branch */ + + HPMCNT_EVENT_TRAP = 13, /**< CPU mhpmevent CSR (13): Entered trap */ + HPMCNT_EVENT_ILLEGAL = 14 /**< CPU mhpmevent CSR (14): Illegal instruction exception */ +}; + + +/**********************************************************************//** + * CPU pmpcfg PMP configuration attributed + **************************************************************************/ +enum NEORV32_PMPCFG_ATTRIBUTES_enum { + PMPCFG_R = 0, /**< CPU pmpcfg attribute (0): Read */ + PMPCFG_W = 1, /**< CPU pmpcfg attribute (1): Write */ + PMPCFG_X = 2, /**< CPU pmpcfg attribute (2): Execute */ + PMPCFG_A_LSB = 3, /**< CPU pmpcfg attribute (3): Mode LSB */ + PMPCFG_A_MSB = 4, /**< CPU pmpcfg attribute (4): Mode MSB */ + PMPCFG_L = 7 /**< CPU pmpcfg attribute (7): Locked */ +}; + +/**********************************************************************//** + * PMP modes + **************************************************************************/ +#define PMPCFG_MODE_NAPOT 3 + + +/**********************************************************************//** + * Trap codes from mcause CSR. + **************************************************************************/ +enum NEORV32_EXCEPTION_CODES_enum { + TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */ + TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */ + TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */ + TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */ + TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */ + TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */ + TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */ + TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */ + TRAP_CODE_UENV_CALL = 0x00000008, /**< 0.8: Environment call from user mode (ECALL instruction) */ + TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */ + TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */ + TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */ + TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */ + TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */ + TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */ + TRAP_CODE_FIRQ_2 = 0x80000012, /**< 1.18: Fast interrupt channel 2 */ + TRAP_CODE_FIRQ_3 = 0x80000013, /**< 1.19: Fast interrupt channel 3 */ + TRAP_CODE_FIRQ_4 = 0x80000014, /**< 1.20: Fast interrupt channel 4 */ + TRAP_CODE_FIRQ_5 = 0x80000015, /**< 1.21: Fast interrupt channel 5 */ + TRAP_CODE_FIRQ_6 = 0x80000016, /**< 1.22: Fast interrupt channel 6 */ + TRAP_CODE_FIRQ_7 = 0x80000017, /**< 1.23: Fast interrupt channel 7 */ + TRAP_CODE_FIRQ_8 = 0x80000018, /**< 1.24: Fast interrupt channel 8 */ + TRAP_CODE_FIRQ_9 = 0x80000019, /**< 1.25: Fast interrupt channel 9 */ + TRAP_CODE_FIRQ_10 = 0x8000001a, /**< 1.26: Fast interrupt channel 10 */ + TRAP_CODE_FIRQ_11 = 0x8000001b, /**< 1.27: Fast interrupt channel 11 */ + TRAP_CODE_FIRQ_12 = 0x8000001c, /**< 1.28: Fast interrupt channel 12 */ + TRAP_CODE_FIRQ_13 = 0x8000001d, /**< 1.29: Fast interrupt channel 13 */ + TRAP_CODE_FIRQ_14 = 0x8000001e, /**< 1.30: Fast interrupt channel 14 */ + TRAP_CODE_FIRQ_15 = 0x8000001f /**< 1.31: Fast interrupt channel 15 */ +}; + + +/**********************************************************************//** + * Processor clock prescaler select + **************************************************************************/ +enum NEORV32_CLOCK_PRSC_enum { + CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */ + CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */ + CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */ + CLK_PRSC_64 = 3, /**< CPU_CLK (from clk_i top signal) / 64 */ + CLK_PRSC_128 = 4, /**< CPU_CLK (from clk_i top signal) / 128 */ + CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */ + CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */ + CLK_PRSC_4096 = 7 /**< CPU_CLK (from clk_i top signal) / 4096 */ +}; + + +/**********************************************************************//** + * Official NEORV32 >RISC-V open-source architecture ID< + * https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md + **************************************************************************/ +#define NEORV32_ARCHID 19 + + +/**********************************************************************//** + * @defgroup FIRQ_ALIASES Fast Interrupt Requests (FIRQ) Aliases (MIE, MIP, MCAUSE, RTE-ID) + * @name Fast Interrupt Requests (FIRQ) Aliases (MIE, MIP, MCAUSE, RTE-ID) + **************************************************************************/ +/**@{*/ +/** @name Watchdog Timer (WDT) */ +/**@{*/ +#define WDT_FIRQ_ENABLE CSR_MIE_FIRQ0E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define WDT_FIRQ_PENDING CSR_MIP_FIRQ0P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define WDT_RTE_ID RTE_TRAP_FIRQ_0 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define WDT_TRAP_CODE TRAP_CODE_FIRQ_0 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name Custom Functions Subsystem (CFS) */ +/**@{*/ +#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define CFS_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name Primary Universal Asynchronous Receiver/Transmitter (UART0) */ +/**@{*/ +#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_4 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name Secondary Universal Asynchronous Receiver/Transmitter (UART1) */ +/**@{*/ +#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name Serial Peripheral Interface (SPI) */ +/**@{*/ +#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define SPI_RTE_ID RTE_TRAP_FIRQ_6 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name Two-Wire Interface (TWI) */ +/**@{*/ +#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define TWI_RTE_ID RTE_TRAP_FIRQ_7 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name External Interrupt Controller (XIRQ) */ +/**@{*/ +#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name Smart LED Controller (NEOLED) */ +/**@{*/ +#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name Stream Link Interface (SLINK) */ +/**@{*/ +#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ10E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ10P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_10 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_10 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ11E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ11P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_11 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_11 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/** @name General Purpose Timer (GPTMR) */ +/**@{*/ +#define GPTMR_FIRQ_ENABLE CSR_MIE_FIRQ12E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */ +#define GPTMR_FIRQ_PENDING CSR_MIP_FIRQ12P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */ +#define GPTMR_RTE_ID RTE_TRAP_FIRQ_12 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */ +#define GPTMR_TRAP_CODE TRAP_CODE_FIRQ_12 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */ +/**@}*/ +/**@}*/ + + +/**********************************************************************//** + * @name Address space sections + **************************************************************************/ +/**@{*/ +/** instruction memory base address (r/w/x) */ +// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry +/** data memory base address (r/w/x) */ +// -> configured via dspace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry +/** bootloader memory base address (r/-/x) */ +#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL) +/** on-chip debugger complex base address (r/w/x) */ +#define OCD_BASE_ADDRESS (0XFFFFF800UL) +/** peripheral/IO devices memory base address (r/w/-) */ +#define IO_BASE_ADDRESS (0xFFFFFE00UL) +/**@}*/ + + +// ############################################################################################################################ +// On-Chip Debugger (should NOT be used by application software) +// ############################################################################################################################ +/**@{*/ +/** on-chip debugger - debug module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + const uint32_t CODE[32]; /**< offset 0: park loop code ROM (r/-) */ + const uint32_t PBUF[4]; /**< offset 128: program buffer (r/-) */ + const uint32_t reserved1[28]; /**< offset 144..252: reserved */ + uint32_t DATA; /**< offset 256: data exchange register (r/w) */ + const uint32_t reserved2[31]; /**< offset 260..380: reserved */ + uint32_t SREG; /**< offset 384: control and status register (r/w) (#NEORV32_OCD_DM_SREG_enum) */ + const uint32_t reserved3[31]; /**< offset 388..508: reserved */ +} neorv32_dm_t; + +/** on-chip debugger debug module hardware access (#neorv32_dm_t) */ +#define NEORV32_DM (*((volatile neorv32_dm_t*) (0XFFFFF800UL))) + +/** on-chip debugger debug module control and status register bits */ +enum NEORV32_OCD_DM_SREG_enum { + OCD_DM_SREG_HALT_ACK = 0, /**< OCD.DM control and status register(0) (-/w): CPU is halted in debug mode and waits in park loop */ + OCD_DM_SREG_RESUME_REQ = 1, /**< OCD.DM control and status register(1) (r/-): DM requests CPU to resume */ + OCD_DM_SREG_RESUME_ACK = 2, /**< OCD.DM control and status register(2) (-/w): CPU starts resuming */ + OCD_DM_SREG_EXECUTE_REQ = 3, /**< OCD.DM control and status register(3) (r/-): DM requests to execute program buffer */ + OCD_DM_SREG_EXECUTE_ACK = 4, /**< OCD.DM control and status register(4) (-/w): CPU starts to execute program buffer */ + OCD_DM_SREG_EXCEPTION_ACK = 5 /**< OCD.DM control and status register(5) (-/w): CPU has detected an exception */ +}; +/**@}*/ + + +// ############################################################################################################################ +// Peripheral/IO Devices - IO Address Space +// ############################################################################################################################ + + +/**********************************************************************//** + * @name Helper macros for easy memory-mapped register access (DEPRECATED!) + **************************************************************************/ +/**@{*/ +/** memory-mapped byte (8-bit) read/write register */ +#define IO_REG8 (volatile uint8_t*) +/** memory-mapped half-word (16-bit) read/write register */ +#define IO_REG16 (volatile uint16_t*) +/** memory-mapped word (32-bit) read/write register */ +#define IO_REG32 (volatile uint32_t*) +/** memory-mapped double-word (64-bit) read/write register */ +#define IO_REG64 (volatile uint64_t*) +/** memory-mapped byte (8-bit) read-only register */ +#define IO_ROM8 (const volatile uint8_t*) +/** memory-mapped half-word (16-bit) read-only register */ +#define IO_ROM16 (const volatile uint16_t*) +/** memory-mapped word (32-bit) read-only register */ +#define IO_ROM32 (const volatile uint32_t*) +/** memory-mapped double-word (64-bit) read-only register */ +#define IO_ROM64 (const volatile uint64_t*) +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Custom Functions Subsystem (CFS) + **************************************************************************/ +/**@{*/ +/** CFS module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t REG[32]; /**< offset 4*0..4*31: CFS register 0..31, user-defined */ +} neorv32_cfs_t; + +/** CFS module hardware access (#neorv32_cfs_t) */ +#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (0xFFFFFE00UL))) +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Pulse Width Modulation Controller (PWM) + **************************************************************************/ +/**@{*/ +/** PWM module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_PWM_CTRL_enum) */ + uint32_t DUTY[15]; /**< offset 4..60: duty cycle register 0..14 */ +} neorv32_pwm_t; + +/** PWM module hardware access (#neorv32_pwm_t) */ +#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (0xFFFFFE80UL))) + +/** PWM control register bits */ +enum NEORV32_PWM_CTRL_enum { + PWM_CTRL_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */ + PWM_CTRL_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */ + PWM_CTRL_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */ + PWM_CTRL_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Stream link interface (SLINK) + **************************************************************************/ +/**@{*/ +/** SLINK module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_SLINK_CTRL_enum) */ + const uint32_t reserved0; /**< offset 4: reserved */ + uint32_t IRQ; /**< offset 8: interrupt configuration register (#NEORV32_SLINK_IRQ_enum) */ + const uint32_t reserved1; /**< offset 12: reserved */ + const uint32_t STATUS; /**< offset 16: status register (#NEORV32_SLINK_STATUS_enum) */ + const uint32_t reserved2[3]; /**< offset 20..28: reserved */ + uint32_t DATA[8]; /**< offset 32..60: stream link data channel 0..7 */ +} neorv32_slink_t; + +/** SLINK module hardware access (#neorv32_slink_t) */ +#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (0xFFFFFEC0UL))) + +/** SLINK control register bits */ +enum NEORV32_SLINK_CTRL_enum { + SLINK_CTRL_RX_NUM0 = 0, /**< SLINK control register(0) (r/-): number of implemented RX links bit 0 */ + SLINK_CTRL_RX_NUM1 = 1, /**< SLINK control register(1) (r/-): number of implemented RX links bit 1 */ + SLINK_CTRL_RX_NUM2 = 2, /**< SLINK control register(2) (r/-): number of implemented RX links bit 2 */ + SLINK_CTRL_RX_NUM3 = 3, /**< SLINK control register(3) (r/-): number of implemented RX links bit 3 */ + + SLINK_CTRL_TX_NUM0 = 4, /**< SLINK control register(4) (r/-): number of implemented TX links bit 0 */ + SLINK_CTRL_TX_NUM1 = 5, /**< SLINK control register(5) (r/-): number of implemented TX links bit 1 */ + SLINK_CTRL_TX_NUM2 = 6, /**< SLINK control register(6) (r/-): number of implemented TX links bit 2 */ + SLINK_CTRL_TX_NUM3 = 7, /**< SLINK control register(7) (r/-): number of implemented TX links bit 3 */ + + SLINK_CTRL_RX_FIFO_S0 = 8, /**< SLINK control register( 8) (r/-): log2(RX FIFO size) bit 0 */ + SLINK_CTRL_RX_FIFO_S1 = 9, /**< SLINK control register( 9) (r/-): log2(RX FIFO size) bit 1 */ + SLINK_CTRL_RX_FIFO_S2 = 10, /**< SLINK control register(10) (r/-): log2(RX FIFO size) bit 2 */ + SLINK_CTRL_RX_FIFO_S3 = 11, /**< SLINK control register(11) (r/-): log2(RX FIFO size) bit 3 */ + + SLINK_CTRL_TX_FIFO_S0 = 12, /**< SLINK control register(12) (r/-): log2(TX FIFO size) bit 0 */ + SLINK_CTRL_TX_FIFO_S1 = 13, /**< SLINK control register(13) (r/-): log2(TX FIFO size) bit 1 */ + SLINK_CTRL_TX_FIFO_S2 = 14, /**< SLINK control register(14) (r/-): log2(TX FIFO size) bit 2 */ + SLINK_CTRL_TX_FIFO_S3 = 15, /**< SLINK control register(15) (r/-): log2(TX FIFO size) bit 3 */ + + SLINK_CTRL_EN = 31, /**< SLINK control register(0) (r/w): SLINK controller enable */ +}; + +/** SLINK interrupt control register bits */ +enum NEORV32_SLINK_IRQ_enum { + SLINK_IRQ_RX_EN_LSB = 0, /**< SLINK IRQ configuration register( 0) (r/w): RX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */ + SLINK_IRQ_RX_EN_MSB = 7, /**< SLINK IRQ configuration register( 7) (r/w): RX IRQ enable MSB (link 7) (#NEORV32_SLINK_IRQ_EN_enum) */ + SLINK_IRQ_RX_MODE_LSB = 8, /**< SLINK IRQ configuration register( 8) (r/w): RX IRQ mode LSB (link 0) (#NEORV32_SLINK_IRQ_RX_TYPE_enum) */ + SLINK_IRQ_RX_MODE_MSB = 15, /**< SLINK IRQ configuration register(15) (r/w): RX IRQ mode MSB (link 7) (#NEORV32_SLINK_IRQ_RX_TYPE_enum) */ + + SLINK_IRQ_TX_EN_LSB = 16, /**< SLINK IRQ configuration register(16) (r/w): TX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */ + SLINK_IRQ_TX_EN_MSB = 23, /**< SLINK IRQ configuration register(23) (r/w): TX IRQ enable MSB (link 7) (#NEORV32_SLINK_IRQ_EN_enum) */ + SLINK_IRQ_TX_MODE_LSB = 24, /**< SLINK IRQ configuration register(24) (r/w): TX IRQ mode LSB (link 0) (#NEORV32_SLINK_IRQ_TX_TYPE_enum) */ + SLINK_IRQ_TX_MODE_MSB = 31 /**< SLINK IRQ configuration register(31) (r/w): TX IRQ mode MSB (link 7) (#NEORV32_SLINK_IRQ_TX_TYPE_enum) */ +}; + +/** SLINK interrupt configuration enable (per link) */ +enum NEORV32_SLINK_IRQ_EN_enum { + SLINK_IRQ_DISABLE = 0, /**< '1': IRQ disabled */ + SLINK_IRQ_ENABLE = 1 /**< '0': IRQ enabled */ +}; + +/** SLINK RX interrupt configuration type (per link) */ +enum NEORV32_SLINK_IRQ_RX_TYPE_enum { + SLINK_IRQ_RX_NOT_EMPTY = 0, /**< '1': RX FIFO is not empty */ + SLINK_IRQ_RX_FIFO_HALF = 1 /**< '0': RX FIFO fill-level rises above half-full */ +}; + +/** SLINK TX interrupt configuration type (per link) */ +enum NEORV32_SLINK_IRQ_TX_TYPE_enum { + SLINK_IRQ_TX_NOT_FULL = 0, /**< '1': TX FIFO is not FULL */ + SLINK_IRQ_TX_FIFO_HALF = 1 /**< '0': TX FIFO fill-level falls below half-full */ +}; + +/** SLINK status register bits */ +enum NEORV32_SLINK_STATUS_enum { + SLINK_STATUS_RX0_AVAIL = 0, /**< SLINK status register(0) (r/-): RX link 0 FIFO is NOT empty (data available) */ + SLINK_STATUS_RX1_AVAIL = 1, /**< SLINK status register(1) (r/-): RX link 1 FIFO is NOT empty (data available) */ + SLINK_STATUS_RX2_AVAIL = 2, /**< SLINK status register(2) (r/-): RX link 2 FIFO is NOT empty (data available) */ + SLINK_STATUS_RX3_AVAIL = 3, /**< SLINK status register(3) (r/-): RX link 3 FIFO is NOT empty (data available) */ + SLINK_STATUS_RX4_AVAIL = 4, /**< SLINK status register(4) (r/-): RX link 4 FIFO is NOT empty (data available) */ + SLINK_STATUS_RX5_AVAIL = 5, /**< SLINK status register(5) (r/-): RX link 5 FIFO is NOT empty (data available) */ + SLINK_STATUS_RX6_AVAIL = 6, /**< SLINK status register(6) (r/-): RX link 6 FIFO is NOT empty (data available) */ + SLINK_STATUS_RX7_AVAIL = 7, /**< SLINK status register(7) (r/-): RX link 7 FIFO is NOT empty (data available) */ + + SLINK_STATUS_TX0_FREE = 8, /**< SLINK status register(8) (r/-): TX link 0 FIFO is NOT full (ready to send) */ + SLINK_STATUS_TX1_FREE = 9, /**< SLINK status register(9) (r/-): TX link 1 FIFO is NOT full (ready to send) */ + SLINK_STATUS_TX2_FREE = 10, /**< SLINK status register(10) (r/-): TX link 2 FIFO is NOT full (ready to send) */ + SLINK_STATUS_TX3_FREE = 11, /**< SLINK status register(11) (r/-): TX link 3 FIFO is NOT full (ready to send) */ + SLINK_STATUS_TX4_FREE = 12, /**< SLINK status register(12) (r/-): TX link 4 FIFO is NOT full (ready to send) */ + SLINK_STATUS_TX5_FREE = 13, /**< SLINK status register(13) (r/-): TX link 5 FIFO is NOT full (ready to send) */ + SLINK_STATUS_TX6_FREE = 14, /**< SLINK status register(14) (r/-): TX link 6 FIFO is NOT full (ready to send) */ + SLINK_STATUS_TX7_FREE = 15, /**< SLINK status register(15) (r/-): TX link 7 FIFO is NOT full (ready to send) */ + + SLINK_STATUS_RX0_HALF = 16, /**< SLINK status register(16) (r/-): RX link 0 FIFO fill level is >= half-full */ + SLINK_STATUS_RX1_HALF = 17, /**< SLINK status register(17) (r/-): RX link 1 FIFO fill level is >= half-full */ + SLINK_STATUS_RX2_HALF = 18, /**< SLINK status register(18) (r/-): RX link 2 FIFO fill level is >= half-full */ + SLINK_STATUS_RX3_HALF = 19, /**< SLINK status register(19) (r/-): RX link 3 FIFO fill level is >= half-full */ + SLINK_STATUS_RX4_HALF = 20, /**< SLINK status register(20) (r/-): RX link 4 FIFO fill level is >= half-full */ + SLINK_STATUS_RX5_HALF = 21, /**< SLINK status register(21) (r/-): RX link 5 FIFO fill level is >= half-full */ + SLINK_STATUS_RX6_HALF = 22, /**< SLINK status register(22) (r/-): RX link 6 FIFO fill level is >= half-full */ + SLINK_STATUS_RX7_HALF = 23, /**< SLINK status register(23) (r/-): RX link 7 FIFO fill level is >= half-full */ + + SLINK_STATUS_TX0_HALF = 24, /**< SLINK status register(24) (r/-): TX link 0 FIFO fill level is > half-full */ + SLINK_STATUS_TX1_HALF = 25, /**< SLINK status register(25) (r/-): TX link 1 FIFO fill level is > half-full */ + SLINK_STATUS_TX2_HALF = 26, /**< SLINK status register(26) (r/-): TX link 2 FIFO fill level is > half-full */ + SLINK_STATUS_TX3_HALF = 27, /**< SLINK status register(27) (r/-): TX link 3 FIFO fill level is > half-full */ + SLINK_STATUS_TX4_HALF = 28, /**< SLINK status register(28) (r/-): TX link 4 FIFO fill level is > half-full */ + SLINK_STATUS_TX5_HALF = 29, /**< SLINK status register(29) (r/-): TX link 5 FIFO fill level is > half-full */ + SLINK_STATUS_TX6_HALF = 30, /**< SLINK status register(30) (r/-): TX link 6 FIFO fill level is > half-full */ + SLINK_STATUS_TX7_HALF = 31 /**< SLINK status register(31) (r/-): TX link 7 FIFO fill level is > half-full */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: General Purpose Timer (GPTMR) + **************************************************************************/ +/**@{*/ +/** GPTMR module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_GPTMR_CTRL_enum) */ + uint32_t THRES; /**< offset 4: threshold register */ + uint32_t COUNT; /**< offset 8: counter register */ + const uint32_t reserved; /**< offset 12: reserved */ +} neorv32_gptmr_t; + +/** GPTMR module hardware access (#neorv32_gptmr_t) */ +#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (0xFFFFFF60UL))) + +/** GPTMR control/data register bits */ +enum NEORV32_GPTMR_CTRL_enum { + GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */ + GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */ + GPTMR_CTRL_PRSC1 = 2, /**< GPTIMR control register(2) (r/w): Clock prescaler select bit 1 */ + GPTMR_CTRL_PRSC2 = 3, /**< GPTIMR control register(3) (r/w): Clock prescaler select bit 2 */ + GPTMR_CTRL_MODE = 4 /**< GPTIMR control register(4) (r/w): Timer mode: 0=single-shot mode, 1=continuous mode */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Bus Monitor (BUSKEEPER) + **************************************************************************/ +/**@{*/ +/** BUSKEEPER module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */ +} neorv32_buskeeper_t; + +/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */ +#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL))) + +/** BUSKEEPER control/data register bits */ +enum NEORV32_BUSKEEPER_CTRL_enum { + BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */ + BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/c): Sticky error flag, clears after read or write access */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: External Interrupt Controller (XIRQ) + **************************************************************************/ +/**@{*/ +/** XIRQ module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t IER; /**< offset 0: IRQ input enable register */ + uint32_t IPR; /**< offset 4: pending IRQ register /ack/clear */ + uint32_t SCR; /**< offset 8: interrupt source register */ + const uint32_t reserved; /**< offset 12: reserved */ +} neorv32_xirq_t; + +/** XIRQ module hardware access (#neorv32_xirq_t) */ +#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (0xFFFFFF80UL))) +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Machine System Timer (MTIME) + **************************************************************************/ +/**@{*/ +/** MTIME module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t TIME_LO; /**< offset 0: time register low word */ + uint32_t TIME_HI; /**< offset 4: time register high word */ + uint32_t TIMECMP_LO; /**< offset 8: compare register low word */ + uint32_t TIMECMP_HI; /**< offset 12: compare register high word */ +} neorv32_mtime_t; + +/** MTIME module hardware access (#neorv32_mtime_t) */ +#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (0xFFFFFF90UL))) +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1) + **************************************************************************/ +/**@{*/ +/** UART0 module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */ +} neorv32_uart0_t; + +/** UART0 module hardware access (#neorv32_uart0_t) */ +#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (0xFFFFFFA0UL))) + +/** UART1 module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */ +} neorv32_uart1_t; + +/** UART1 module hardware access (#neorv32_uart1_t) */ +#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (0xFFFFFFD0UL))) + +/** UART0/UART1 control register bits */ +enum NEORV32_UART_CTRL_enum { + UART_CTRL_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bit, bit 0) */ + UART_CTRL_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bit, bit 1) */ + UART_CTRL_BAUD02 = 2, /**< UART control register(2) (r/w): BAUD rate config value (12-bit, bit 2) */ + UART_CTRL_BAUD03 = 3, /**< UART control register(3) (r/w): BAUD rate config value (12-bit, bit 3) */ + UART_CTRL_BAUD04 = 4, /**< UART control register(4) (r/w): BAUD rate config value (12-bit, bit 4) */ + UART_CTRL_BAUD05 = 5, /**< UART control register(5) (r/w): BAUD rate config value (12-bit, bit 4) */ + UART_CTRL_BAUD06 = 6, /**< UART control register(6) (r/w): BAUD rate config value (12-bit, bit 5) */ + UART_CTRL_BAUD07 = 7, /**< UART control register(7) (r/w): BAUD rate config value (12-bit, bit 6) */ + UART_CTRL_BAUD08 = 8, /**< UART control register(8) (r/w): BAUD rate config value (12-bit, bit 7) */ + UART_CTRL_BAUD09 = 9, /**< UART control register(9) (r/w): BAUD rate config value (12-bit, bit 8) */ + UART_CTRL_BAUD10 = 10, /**< UART control register(10) (r/w): BAUD rate config value (12-bit, bit 9) */ + UART_CTRL_BAUD11 = 11, /**< UART control register(11) (r/w): BAUD rate config value msb (12-bit, bit 0) */ + UART_CTRL_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */ + UART_CTRL_RX_EMPTY = 13, /**< UART control register(13) (r/-): RX FIFO is empty */ + UART_CTRL_RX_HALF = 14, /**< UART control register(14) (r/-): RX FIFO is at least half-full */ + UART_CTRL_RX_FULL = 15, /**< UART control register(15) (r/-): RX FIFO is full */ + UART_CTRL_TX_EMPTY = 16, /**< UART control register(16) (r/-): TX FIFO is empty */ + UART_CTRL_TX_HALF = 17, /**< UART control register(17) (r/-): TX FIFO is at least half-full */ + UART_CTRL_TX_FULL = 18, /**< UART control register(18) (r/-): TX FIFO is full */ + + UART_CTRL_RTS_EN = 20, /**< UART control register(20) (r/w): Enable hardware flow control: Assert RTS output if UART.RX is ready to receive */ + UART_CTRL_CTS_EN = 21, /**< UART control register(21) (r/w): Enable hardware flow control: UART.TX starts sending only if CTS input is asserted */ + UART_CTRL_PMODE0 = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */ + UART_CTRL_PMODE1 = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */ + UART_CTRL_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */ + UART_CTRL_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */ + UART_CTRL_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */ + UART_CTRL_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */ + UART_CTRL_EN = 28, /**< UART control register(28) (r/w): UART global enable */ + UART_CTRL_RX_IRQ = 29, /**< UART control register(29) (r/w): RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty */ + UART_CTRL_TX_IRQ = 30, /**< UART control register(30) (r/w): TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full */ + UART_CTRL_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */ +}; + +/** UART0/UART1 parity configuration */ +enum NEORV32_UART_PARITY_enum { + PARITY_NONE = 0b00, /**< 0b00: No parity bit at all */ + PARITY_EVEN = 0b10, /**< 0b10: Even parity */ + PARITY_ODD = 0b11 /**< 0b11: Odd parity */ +}; + +/** UART0/UART1 hardware flow control configuration */ +enum NEORV32_UART_FLOW_CONTROL_enum { + FLOW_CONTROL_NONE = 0b00, /**< 0b00: No hardware flow control */ + FLOW_CONTROL_RTS = 0b01, /**< 0b01: Assert RTS output if UART.RX is ready to receive */ + FLOW_CONTROL_CTS = 0b10, /**< 0b10: UART.TX starts sending only if CTS input is asserted */ + FLOW_CONTROL_RTSCTS = 0b11 /**< 0b11: Assert RTS output if UART.RX is ready to receive & UART.TX starts sending only if CTS input is asserted */ +}; + +/** UART0/UART1 receive/transmit data register bits */ +enum NEORV32_UART_DATA_enum { + UART_DATA_LSB = 0, /**< UART receive/transmit data register(0) (r/w): Receive/transmit data LSB (bit 0) */ + UART_DATA_MSB = 7, /**< UART receive/transmit data register(7) (r/w): Receive/transmit data MSB (bit 7) */ + + UART_DATA_PERR = 28, /**< UART receive/transmit data register(18) (r/-): RX parity error detected when set */ + UART_DATA_FERR = 29, /**< UART receive/transmit data register(29) (r/-): RX frame error (no valid stop bit) detected when set */ + UART_DATA_OVERR = 30, /**< UART receive/transmit data register(30) (r/-): RX data overrun when set */ + UART_DATA_AVAIL = 31 /**< UART receive/transmit data register(31) (r/-): RX data available when set */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Serial Peripheral Interface Controller (SPI) + **************************************************************************/ +/**@{*/ +/** SPI module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register */ +} neorv32_spi_t; + +/** SPI module hardware access (#neorv32_spi_t) */ +#define NEORV32_SPI (*((volatile neorv32_spi_t*) (0xFFFFFFA8UL))) + +/** SPI control register bits */ +enum NEORV32_SPI_CTRL_enum { + SPI_CTRL_CS0 = 0, /**< SPI control register(0) (r/w): Direct chip select line 0 (output is low when set) */ + SPI_CTRL_CS1 = 1, /**< SPI control register(1) (r/w): Direct chip select line 1 (output is low when set) */ + SPI_CTRL_CS2 = 2, /**< SPI control register(2) (r/w): Direct chip select line 2 (output is low when set) */ + SPI_CTRL_CS3 = 3, /**< SPI control register(3) (r/w): Direct chip select line 3 (output is low when set) */ + SPI_CTRL_CS4 = 4, /**< SPI control register(4) (r/w): Direct chip select line 4 (output is low when set) */ + SPI_CTRL_CS5 = 5, /**< SPI control register(5) (r/w): Direct chip select line 5 (output is low when set) */ + SPI_CTRL_CS6 = 6, /**< SPI control register(6) (r/w): Direct chip select line 6 (output is low when set) */ + SPI_CTRL_CS7 = 7, /**< SPI control register(7) (r/w): Direct chip select line 7 (output is low when set) */ + SPI_CTRL_EN = 8, /**< SPI control register(8) (r/w): SPI unit enable */ + SPI_CTRL_CPHA = 9, /**< SPI control register(9) (r/w): Clock phase */ + SPI_CTRL_PRSC0 = 10, /**< SPI control register(10) (r/w): Clock prescaler select bit 0 */ + SPI_CTRL_PRSC1 = 11, /**< SPI control register(11) (r/w): Clock prescaler select bit 1 */ + SPI_CTRL_PRSC2 = 12, /**< SPI control register(12) (r/w): Clock prescaler select bit 2 */ + SPI_CTRL_SIZE0 = 13, /**< SPI control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ + SPI_CTRL_SIZE1 = 14, /**< SPI control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ + SPI_CTRL_CPOL = 15, /**< SPI control register(15) (r/w): Clock polarity */ + + SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Two-Wire Interface Controller (TWI) + **************************************************************************/ +/**@{*/ +/** TWI module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_TWI_CTRL_enum) */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */ +} neorv32_twi_t; + +/** TWI module hardware access (#neorv32_twi_t) */ +#define NEORV32_TWI (*((volatile neorv32_twi_t*) (0xFFFFFFB0UL))) + +/** TWI control register bits */ +enum NEORV32_TWI_CTRL_enum { + TWI_CTRL_EN = 0, /**< TWI control register(0) (r/w): TWI enable */ + TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */ + TWI_CTRL_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */ + TWI_CTRL_PRSC0 = 3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */ + TWI_CTRL_PRSC1 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */ + TWI_CTRL_PRSC2 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */ + TWI_CTRL_MACK = 6, /**< TWI control register(6) (r/w): Generate ACK by controller for each transmission */ + + TWI_CTRL_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */ + TWI_CTRL_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */ +}; + +/** WTD receive/transmit data register bits */ +enum NEORV32_TWI_DATA_enum { + TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */ + TWI_DATA_MSB = 7 /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: True Random Number Generator (TRNG) + **************************************************************************/ +/**@{*/ +/** TRNG module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */ +} neorv32_trng_t; + +/** TRNG module hardware access (#neorv32_trng_t) */ +#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (0xFFFFFFB8UL))) + +/** TRNG control/data register bits */ +enum NEORV32_TRNG_CTRL_enum { + TRNG_CTRL_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */ + TRNG_CTRL_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */ + + TRNG_CTRL_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */ + TRNG_CTRL_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Watchdog Timer (WDT) + **************************************************************************/ +/**@{*/ +/** WDT module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */ +} neorv32_wdt_t; + +/** WDT module hardware access (#neorv32_wdt_t) */ +#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (0xFFFFFFBCUL))) + +/** WTD control register bits */ +enum NEORV32_WDT_CTRL_enum { + WDT_CTRL_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */ + WDT_CTRL_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */ + WDT_CTRL_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */ + WDT_CTRL_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */ + WDT_CTRL_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */ + WDT_CTRL_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */ + WDT_CTRL_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */ + WDT_CTRL_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */ + WDT_CTRL_LOCK = 8, /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */ + WDT_CTRL_DBEN = 9, /**< WDT control register(9) (r/w): Allow WDT to continue operation even when in debug mode */ + WDT_CTRL_HALF = 10 /**< WDT control register(10) (r/-): Set if at least half of the max. timeout counter value has been reached */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: General Purpose Input/Output Port Unit (GPIO) + **************************************************************************/ +/**@{*/ +/** GPIO module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit */ + const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit */ + uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */ + uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */ +} neorv32_gpio_t; + +/** GPIO module hardware access (#neorv32_gpio_t) */ +#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (0xFFFFFFC0UL))) +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: Smart LED Hardware Interface (NEOLED) + **************************************************************************/ +/**@{*/ +/** NEOLED module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + uint32_t CTRL; /**< offset 0: control register */ + uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */ +} neorv32_neoled_t; + +/** NEOLED module hardware access (#neorv32_neoled_t) */ +#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (0xFFFFFFD8UL))) + +/** NEOLED control register bits */ +enum NEORV32_NEOLED_CTRL_enum { + NEOLED_CTRL_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */ + NEOLED_CTRL_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */ + NEOLED_CTRL_STROBE = 2, /**< NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) */ + NEOLED_CTRL_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */ + NEOLED_CTRL_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */ + NEOLED_CTRL_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */ + // + NEOLED_CTRL_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */ + NEOLED_CTRL_BUFS_1 = 7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */ + NEOLED_CTRL_BUFS_2 = 8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */ + NEOLED_CTRL_BUFS_3 = 9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */ + // + NEOLED_CTRL_T_TOT_0 = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */ + NEOLED_CTRL_T_TOT_1 = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */ + NEOLED_CTRL_T_TOT_2 = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */ + NEOLED_CTRL_T_TOT_3 = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */ + NEOLED_CTRL_T_TOT_4 = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */ + // + NEOLED_CTRL_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */ + NEOLED_CTRL_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */ + NEOLED_CTRL_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */ + NEOLED_CTRL_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */ + NEOLED_CTRL_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */ + // + NEOLED_CTRL_T_ONE_H_0 = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */ + NEOLED_CTRL_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */ + NEOLED_CTRL_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */ + NEOLED_CTRL_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */ + NEOLED_CTRL_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */ + // + NEOLED_CTRL_IRQ_CONF = 27, /**< NEOLED control register(27) (r/w): TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty */ + NEOLED_CTRL_TX_EMPTY = 28, /**< NEOLED control register(28) (r/-): TX FIFO is empty */ + NEOLED_CTRL_TX_HALF = 29, /**< NEOLED control register(29) (r/-): TX FIFO is at least half-full */ + NEOLED_CTRL_TX_FULL = 30, /**< NEOLED control register(30) (r/-): TX FIFO is full */ + NEOLED_CTRL_TX_BUSY = 31 /**< NEOLED control register(31) (r/-): busy flag */ +}; +/**@}*/ + + +/**********************************************************************//** + * @name IO Device: System Configuration Information Memory (SYSINFO) + **************************************************************************/ +/**@{*/ +/** SYSINFO module prototype */ +typedef struct __attribute__((packed,aligned(4))) { + const uint32_t CLK; /**< offset 0: clock speed in Hz */ + const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */ + const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */ + const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */ + const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */ + const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */ + const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */ + const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */ +} neorv32_sysinfo_t; + +/** SYSINFO module hardware access (#neorv32_sysinfo_t) */ +#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL))) + +/** NEORV32_SYSINFO.CPU (r/-): Implemented CPU sub-extensions/features */ +enum NEORV32_SYSINFO_CPU_enum { + SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */ + SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */ + SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */ + + SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */ + SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */ + SYSINFO_CPU_ZICNTR = 7, /**< SYSINFO_CPU (7): Basic CPU counters available when set (r/-) */ + SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */ + SYSINFO_CPU_ZIHPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */ + SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */ + + SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */ + SYSINFO_CPU_FASTSHIFT = 31 /**< SYSINFO_CPU (31): fast shifts (via FAST_SHIFT_EN generic) available when set (r/-) */ +}; + +/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */ +enum NEORV32_SYSINFO_SOC_enum { + SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */ + SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */ + SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */ + SYSINFO_SOC_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */ + SYSINFO_SOC_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */ + SYSINFO_SOC_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */ + + SYSINFO_SOC_IS_SIM = 13, /**< SYSINFO_FEATURES (13) (r/-): Set during simulation (not guaranteed) */ + SYSINFO_SOC_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */ + SYSINFO_SOC_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */ + + SYSINFO_SOC_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */ + SYSINFO_SOC_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */ + SYSINFO_SOC_IO_UART0 = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */ + SYSINFO_SOC_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */ + SYSINFO_SOC_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */ + SYSINFO_SOC_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */ + SYSINFO_SOC_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */ + SYSINFO_SOC_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */ + SYSINFO_SOC_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */ + SYSINFO_SOC_IO_SLINK = 25, /**< SYSINFO_FEATURES (25) (r/-): Stream link interface implemented when 1 (via SLINK_NUM_RX & SLINK_NUM_TX generics) */ + SYSINFO_SOC_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */ + SYSINFO_SOC_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */ + SYSINFO_SOC_IO_XIRQ = 28, /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */ + SYSINFO_SOC_IO_GPTMR = 29 /**< SYSINFO_FEATURES (29) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */ +}; + +/** NEORV32_SYSINFO.CACHE (r/-): Cache configuration */ + enum NEORV32_SYSINFO_CACHE_enum { + SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */ + SYSINFO_CACHE_IC_BLOCK_SIZE_1 = 1, /**< SYSINFO_CACHE (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */ + SYSINFO_CACHE_IC_BLOCK_SIZE_2 = 2, /**< SYSINFO_CACHE (2) (r/-): i-cache: log2(Block size in bytes), bit 2 (via ICACHE_BLOCK_SIZE generic) */ + SYSINFO_CACHE_IC_BLOCK_SIZE_3 = 3, /**< SYSINFO_CACHE (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) */ + + SYSINFO_CACHE_IC_NUM_BLOCKS_0 = 4, /**< SYSINFO_CACHE (4) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 0 (via ICACHE_NUM_BLOCKS generic) */ + SYSINFO_CACHE_IC_NUM_BLOCKS_1 = 5, /**< SYSINFO_CACHE (5) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 1 (via ICACHE_NUM_BLOCKS generic) */ + SYSINFO_CACHE_IC_NUM_BLOCKS_2 = 6, /**< SYSINFO_CACHE (6) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 2 (via ICACHE_NUM_BLOCKS generic) */ + SYSINFO_CACHE_IC_NUM_BLOCKS_3 = 7, /**< SYSINFO_CACHE (7) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 3 (via ICACHE_NUM_BLOCKS generic) */ + + SYSINFO_CACHE_IC_ASSOCIATIVITY_0 = 8, /**< SYSINFO_CACHE (8) (r/-): i-cache: log2(associativity), bit 0 (via ICACHE_ASSOCIATIVITY generic) */ + SYSINFO_CACHE_IC_ASSOCIATIVITY_1 = 9, /**< SYSINFO_CACHE (9) (r/-): i-cache: log2(associativity), bit 1 (via ICACHE_ASSOCIATIVITY generic) */ + SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, /**< SYSINFO_CACHE (10) (r/-): i-cache: log2(associativity), bit 2 (via ICACHE_ASSOCIATIVITY generic) */ + SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, /**< SYSINFO_CACHE (11) (r/-): i-cache: log2(associativity), bit 3 (via ICACHE_ASSOCIATIVITY generic) */ + + SYSINFO_CACHE_IC_REPLACEMENT_0 = 12, /**< SYSINFO_CACHE (12) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 0 */ + SYSINFO_CACHE_IC_REPLACEMENT_1 = 13, /**< SYSINFO_CACHE (13) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 1 */ + SYSINFO_CACHE_IC_REPLACEMENT_2 = 14, /**< SYSINFO_CACHE (14) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 2 */ + SYSINFO_CACHE_IC_REPLACEMENT_3 = 15, /**< SYSINFO_CACHE (15) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 3 */ +}; +/**@}*/ + + +// ---------------------------------------------------------------------------- +// Include all IO driver headers +// ---------------------------------------------------------------------------- +// cpu core +#include "neorv32_cpu.h" + +// intrinsics +#include "neorv32_intrinsics.h" + +// neorv32 runtime environment +#include "neorv32_rte.h" + +// io/peripheral devices +#include "neorv32_cfs.h" +#include "neorv32_gpio.h" +#include "neorv32_gptmr.h" +#include "neorv32_mtime.h" +#include "neorv32_neoled.h" +#include "neorv32_pwm.h" +#include "neorv32_slink.h" +#include "neorv32_spi.h" +#include "neorv32_trng.h" +#include "neorv32_twi.h" +#include "neorv32_uart.h" +#include "neorv32_wdt.h" +#include "neorv32_xirq.h" + +#ifdef __cplusplus +} +#endif + +#endif // neorv32_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_cfs.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_cfs.h new file mode 100644 index 0000000..55fdc59 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_cfs.h @@ -0,0 +1,53 @@ +// ################################################################################################# +// # << NEORV32: neorv32_cfs.h - Custom Functions Subsystem (CFS)) HW Driver (stub) >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_cfs.h + * @author Stephan Nolting + * @brief Custom Functions Subsystem (CFS)) HW driver header file. + * + * @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware. + * @warning Hence, the CFS designer has to provide the actual driver functions. + * + * @note These functions should only be used if the CFS was synthesized (IO_CFS_EN = true). + **************************************************************************/ + +#ifndef neorv32_cfs_h +#define neorv32_cfs_h + +// prototypes +int neorv32_cfs_available(void); + +#endif // neorv32_cfs_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_cpu.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_cpu.h new file mode 100644 index 0000000..10fc180 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_cpu.h @@ -0,0 +1,306 @@ +// ################################################################################################# +// # << NEORV32: neorv32_cpu.h - CPU Core Functions HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_cpu.h + * @author Stephan Nolting + * @brief CPU Core Functions HW driver header file. + **************************************************************************/ + +#ifndef neorv32_cpu_h +#define neorv32_cpu_h + +// prototypes +int neorv32_cpu_irq_enable(uint8_t irq_sel); +int neorv32_cpu_irq_disable(uint8_t irq_sel); +uint64_t neorv32_cpu_get_cycle(void); +void neorv32_cpu_set_mcycle(uint64_t value); +uint64_t neorv32_cpu_get_instret(void); +void neorv32_cpu_set_minstret(uint64_t value); +uint64_t neorv32_cpu_get_systime(void); +void neorv32_cpu_delay_ms(uint32_t time_ms); +void __attribute__((naked)) neorv32_cpu_goto_user_mode(void); +uint32_t neorv32_cpu_pmp_get_num_regions(void); +uint32_t neorv32_cpu_pmp_get_granularity(void); +int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config); +uint32_t neorv32_cpu_hpm_get_counters(void); +uint32_t neorv32_cpu_hpm_get_size(void); + + +/**********************************************************************//** + * Prototype for "after-main handler". This function is called if main() returns. + * + * @param[in] return_code Return value of main() function. + * @return Return value is irrelevant (there is no one left to check for it...). + **************************************************************************/ +extern int __neorv32_crt0_after_main(int32_t return_code) __attribute__ ((weak)); + + +/**********************************************************************//** + * Store unsigned word to address space if atomic access reservation is still valid. + * + * @note An unaligned access address will raise an alignment exception. + * + * @param[in] addr Address (32-bit). + * @param[in] wdata Data word (32-bit) to store. + * @return Operation status (32-bit, zero if success). + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_store_conditional(uint32_t addr, uint32_t wdata) { + +#if defined __riscv_atomic || defined __riscv_a + register uint32_t reg_addr = addr; + register uint32_t reg_data = wdata; + register uint32_t reg_status; + + asm volatile ("sc.w %[status], %[da], (%[ad])" : [status] "=r" (reg_status) : [da] "r" (reg_data), [ad] "r" (reg_addr)); + + return reg_status; +#else + return 1; // always failing +#endif +} + + +/**********************************************************************//** + * Conditional store unsigned word to address space. + * + * @note An unaligned access address will raise an alignment exception. + * + * @param[in] addr Address (32-bit). + * @param[in] wdata Data word (32-bit) to store. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_word(uint32_t addr, uint32_t wdata) { + + register uint32_t reg_addr = addr; + register uint32_t reg_data = wdata; + + asm volatile ("sw %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr)); +} + + +/**********************************************************************//** + * Store unsigned half-word to address space. + * + * @note An unaligned access address will raise an alignment exception. + * + * @param[in] addr Address (32-bit). + * @param[in] wdata Data half-word (16-bit) to store. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_half(uint32_t addr, uint16_t wdata) { + + register uint32_t reg_addr = addr; + register uint32_t reg_data = (uint32_t)wdata; + + asm volatile ("sh %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr)); +} + + +/**********************************************************************//** + * Store unsigned byte to address space. + * + * @param[in] addr Address (32-bit). + * @param[in] wdata Data byte (8-bit) to store. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_byte(uint32_t addr, uint8_t wdata) { + + register uint32_t reg_addr = addr; + register uint32_t reg_data = (uint32_t)wdata; + + asm volatile ("sb %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr)); +} + + +/**********************************************************************//** + * Load unsigned word from address space and make reservation for atomic access. + * + * @note An unaligned access address will raise an alignment exception. + * + * @param[in] addr Address (32-bit). + * @return Read data word (32-bit). + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_reservate_word(uint32_t addr) { + + register uint32_t reg_addr = addr; + register uint32_t reg_data; + +#if defined __riscv_atomic || defined __riscv_a + asm volatile ("lr.w %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr)); +#else + asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr)); +#endif + + return (uint32_t)reg_data; +} + + + +/**********************************************************************//** + * Load unsigned word from address space. + * + * @note An unaligned access address will raise an alignment exception. + * + * @param[in] addr Address (32-bit). + * @return Read data word (32-bit). + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_word(uint32_t addr) { + + register uint32_t reg_addr = addr; + register uint32_t reg_data; + + asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr)); + + return (uint32_t)reg_data; +} + + +/**********************************************************************//** + * Load unsigned half-word from address space. + * + * @note An unaligned access address will raise an alignment exception. + * + * @param[in] addr Address (32-bit). + * @return Read data half-word (16-bit). + **************************************************************************/ +inline uint16_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_half(uint32_t addr) { + + register uint32_t reg_addr = addr; + register uint32_t reg_data; + + asm volatile ("lhu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr)); + + return (uint16_t)reg_data; +} + + +/**********************************************************************//** + * Load unsigned byte from address space. + * + * @param[in] addr Address (32-bit). + * @return Read data byte (8-bit). + **************************************************************************/ +inline uint8_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_byte(uint32_t addr) { + + register uint32_t reg_addr = addr; + register uint32_t reg_data; + + asm volatile ("lbu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr)); + + return (uint8_t)reg_data; +} + + +/**********************************************************************//** + * Read data from CPU configuration and status register (CSR). + * + * @param[in] csr_id ID of CSR to read. See #NEORV32_CSR_enum. + * @return Read data (uint32_t). + **************************************************************************/ +inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) { + + register uint32_t csr_data; + + asm volatile ("csrr %[result], %[input_i]" : [result] "=r" (csr_data) : [input_i] "i" (csr_id)); + + return csr_data; +} + + +/**********************************************************************//** + * Write data to CPU configuration and status register (CSR). + * + * @param[in] csr_id ID of CSR to write. See #NEORV32_CSR_enum. + * @param[in] data Data to write (uint32_t). + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) { + + register uint32_t csr_data = data; + + asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data)); +} + + +/**********************************************************************//** + * Put CPU into "sleep" mode. + * + * @note This function executes the WFI instruction. + * The WFI (wait for interrupt) instruction will make the CPU stall until + * an interrupt request is detected. Interrupts have to be globally enabled + * and at least one external source must be enabled (like the MTI machine + * timer interrupt) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled, + * this will permanently stall the CPU. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) { + + asm volatile ("wfi"); +} + + +/**********************************************************************//** + * Enable global CPU interrupts (via MIE flag in mstatus CSR). + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) { + + asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE)); +} + + +/**********************************************************************//** + * Disable global CPU interrupts (via MIE flag in mstatus CSR). + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) { + + asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE)); +} + + +/**********************************************************************//** + * Trigger breakpoint exception (via EBREAK instruction). + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_breakpoint(void) { + + asm volatile ("ebreak"); +} + + +/**********************************************************************//** + * Trigger "environment call" exception (via ECALL instruction). + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_cpu_env_call(void) { + + asm volatile ("ecall"); +} + + +#endif // neorv32_cpu_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_gpio.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_gpio.h new file mode 100644 index 0000000..a4eabf6 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_gpio.h @@ -0,0 +1,57 @@ +// ################################################################################################# +// # << NEORV32: neorv32_gpio.h - General Purpose Input/Output Port HW Driver (Header) >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_gpio.h + * @author Stephan Nolting + * @brief General purpose input/output port unit (GPIO) HW driver header file. + * + * @note These functions should only be used if the GPIO unit was synthesized (IO_GPIO_EN = true). + **************************************************************************/ + +#ifndef neorv32_gpio_h +#define neorv32_gpio_h + +// prototypes +int neorv32_gpio_available(void); +void neorv32_gpio_pin_set(int pin); +void neorv32_gpio_pin_clr(int pin); +void neorv32_gpio_pin_toggle(int pin); +uint32_t neorv32_gpio_pin_get(int pin); + +void neorv32_gpio_port_set(uint64_t d); +uint64_t neorv32_gpio_port_get(void); + +#endif // neorv32_gpio_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_gptmr.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_gptmr.h new file mode 100644 index 0000000..4700c4f --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_gptmr.h @@ -0,0 +1,54 @@ +// ################################################################################################# +// # << NEORV32: neorv32_gptmr.h - General Purpose Timer (GPTMR) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_gptmr.h + * @author Stephan Nolting + * @brief General purpose timer (GPTMR) HW driver header file. + * + * @note These functions should only be used if the GPTMR unit was synthesized (IO_GPTMR_EN = true). + **************************************************************************/ + +#ifndef neorv32_gptmr_h +#define neorv32_gptmr_h + +// prototypes +int neorv32_gptmr_available(void); +void neorv32_gptmr_setup(uint8_t prsc, uint8_t mode, uint32_t threshold); +void neorv32_gptmr_disable(void); +void neorv32_gptmr_enable(void); +void neorv32_gptmr_restart(void); + +#endif // neorv32_gptmr_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_intrinsics.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_intrinsics.h new file mode 100644 index 0000000..b27e803 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_intrinsics.h @@ -0,0 +1,166 @@ +// ################################################################################################# +// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_intrinsics.h + * @author Stephan Nolting + * @brief Helper functions and macros for custom "intrinsics" / instructions. + **************************************************************************/ + +#ifndef neorv32_intrinsics_h +#define neorv32_intrinsics_h + +/**********************************************************************//** + * @name Custom instructions / intrinsics helper macros + **************************************************************************/ +/**@{*/ + +//** Selection helper macro */ +#define STR1(x) #x +//** Selection helper macro 2 */ +#define STR(x) STR1(x) + +//** Register address converter */ +#define GET_REG_ADDR(x) REG_ADDR_##x + +#define REG_ADDR_x0 0 /**< register 0 */ +#define REG_ADDR_x1 1 /**< register 1 */ +#define REG_ADDR_x2 2 /**< register 2 */ +#define REG_ADDR_x3 3 /**< register 3 */ +#define REG_ADDR_x4 4 /**< register 4 */ +#define REG_ADDR_x5 5 /**< register 5 */ +#define REG_ADDR_x6 6 /**< register 6 */ +#define REG_ADDR_x7 7 /**< register 7 */ +#define REG_ADDR_x8 8 /**< register 8 */ +#define REG_ADDR_x9 9 /**< register 9 */ +#define REG_ADDR_x10 10 /**< register 10 */ +#define REG_ADDR_x11 11 /**< register 11 */ +#define REG_ADDR_x12 12 /**< register 12 */ +#define REG_ADDR_x13 13 /**< register 13 */ +#define REG_ADDR_x14 14 /**< register 14 */ +#define REG_ADDR_x15 15 /**< register 15 */ +#define REG_ADDR_x16 16 /**< register 16 */ +#define REG_ADDR_x17 17 /**< register 17 */ +#define REG_ADDR_x18 18 /**< register 18 */ +#define REG_ADDR_x19 19 /**< register 19 */ +#define REG_ADDR_x20 20 /**< register 20 */ +#define REG_ADDR_x21 21 /**< register 21 */ +#define REG_ADDR_x22 22 /**< register 22 */ +#define REG_ADDR_x23 23 /**< register 23 */ +#define REG_ADDR_x24 24 /**< register 24 */ +#define REG_ADDR_x25 25 /**< register 25 */ +#define REG_ADDR_x26 26 /**< register 26 */ +#define REG_ADDR_x27 27 /**< register 27 */ +#define REG_ADDR_x28 28 /**< register 28 */ +#define REG_ADDR_x29 29 /**< register 29 */ +#define REG_ADDR_x30 30 /**< register 30 */ +#define REG_ADDR_x31 31 /**< register 31 */ +#define REG_ADDR_zero 0 /**< register 0 - according to calling convention */ +#define REG_ADDR_ra 1 /**< register 1 - according to calling convention */ +#define REG_ADDR_sp 2 /**< register 2 - according to calling convention */ +#define REG_ADDR_gp 3 /**< register 3 - according to calling convention */ +#define REG_ADDR_tp 4 /**< register 4 - according to calling convention */ +#define REG_ADDR_t0 5 /**< register 5 - according to calling convention */ +#define REG_ADDR_t1 6 /**< register 6 - according to calling convention */ +#define REG_ADDR_t2 7 /**< register 7 - according to calling convention */ +#define REG_ADDR_s0 8 /**< register 8 - according to calling convention */ +#define REG_ADDR_s1 9 /**< register 9 - according to calling convention */ +#define REG_ADDR_a0 10 /**< register 10 - according to calling convention */ +#define REG_ADDR_a1 11 /**< register 11 - according to calling convention */ +#define REG_ADDR_a2 12 /**< register 12 - according to calling convention */ +#define REG_ADDR_a3 13 /**< register 13 - according to calling convention */ +#define REG_ADDR_a4 14 /**< register 14 - according to calling convention */ +#define REG_ADDR_a5 15 /**< register 15 - according to calling convention */ +#define REG_ADDR_a6 16 /**< register 16 - according to calling convention */ +#define REG_ADDR_a7 17 /**< register 17 - according to calling convention */ +#define REG_ADDR_s2 18 /**< register 18 - according to calling convention */ +#define REG_ADDR_s3 19 /**< register 19 - according to calling convention */ +#define REG_ADDR_s4 20 /**< register 20 - according to calling convention */ +#define REG_ADDR_s5 21 /**< register 21 - according to calling convention */ +#define REG_ADDR_s6 22 /**< register 22 - according to calling convention */ +#define REG_ADDR_s7 23 /**< register 23 - according to calling convention */ +#define REG_ADDR_s8 24 /**< register 24 - according to calling convention */ +#define REG_ADDR_s9 25 /**< register 25 - according to calling convention */ +#define REG_ADDR_s10 26 /**< register 26 - according to calling convention */ +#define REG_ADDR_s11 27 /**< register 27 - according to calling convention */ +#define REG_ADDR_t3 28 /**< register 28 - according to calling convention */ +#define REG_ADDR_t4 29 /**< register 29 - according to calling convention */ +#define REG_ADDR_t5 30 /**< register 30 - according to calling convention */ +#define REG_ADDR_t6 31 /**< register 31 - according to calling convention */ + +//** Construct instruction word (32-bit) for R2-type instruction */ +#define CMD_WORD_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \ + ( (opcode & 0x7f) << 0 ) + \ + ( (rd & 0x1f) << 7 ) + \ + ( (funct3 & 0x1f) << 12 ) + \ + ( (rs1 & 0x1f) << 15 ) + \ + ( (rs2 & 0x1f) << 20 ) + \ + ( (funct7 & 0x7f) << 25 ) + +//** Construct instruction word (32-bit) for R3-type instruction */ +#define CMD_WORD_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \ + ( (opcode & 0x7f) << 0 ) + \ + ( (rd & 0x1f) << 7 ) + \ + ( (funct3 & 0x1f) << 12 ) + \ + ( (rs1 & 0x1f) << 15 ) + \ + ( (rs2 & 0x1f) << 20 ) + \ + ( (rs3 & 0x1f) << 27 ) + +//** Construct instruction word (32-bit) for I-type instruction */ +#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \ + ( (opcode & 0x7f) << 0 ) + \ + ( (rd & 0x1f) << 7 ) + \ + ( (funct3 & 0x1f) << 12 ) + \ + ( (rs1_f5 & 0x1f) << 15 ) + \ + ( (imm12 & 0xfff) << 20 ) + +//** Construct custom R3-type instruction (4 registers, funct3, opcode) */ +#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \ + asm volatile (".word " STR(CMD_WORD_R3_TYPE(GET_REG_ADDR(rs3), GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); + +//** Construct custom R2-type instruction (3 registers, funct3, funct7, opcode) */ +#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \ + asm volatile (".word " STR(CMD_WORD_R2_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); + +//** Construct custom R1-type instruction (2 registers, funct3, funct7, funct5, opcode) */ +#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \ + asm volatile (".word " STR(CMD_WORD_R2_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); + +//** Construct custom I-type instruction (2 registers, funct3, imm12, opcode) */ +#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \ + asm volatile (".word " STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n"); +/**@}*/ + +#endif // neorv32_intrinsics_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_mtime.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_mtime.h new file mode 100644 index 0000000..e9e2df9 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_mtime.h @@ -0,0 +1,54 @@ +// ################################################################################################# +// # << NEORV32: neorv32_mtime.h - Machine System Timer (MTIME) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_mtime.h + * @author Stephan Nolting + * @brief Machine System Timer (MTIME) HW driver header file. + * + * @note These functions should only be used if the MTIME unit was synthesized (IO_MTIME_EN = true). + **************************************************************************/ + +#ifndef neorv32_mtime_h +#define neorv32_mtime_h + +// prototypes +int neorv32_mtime_available(void); +void neorv32_mtime_set_time(uint64_t time); +uint64_t neorv32_mtime_get_time(void); +void neorv32_mtime_set_timecmp(uint64_t timecmp); +uint64_t neorv32_mtime_get_timecmp(void); + +#endif // neorv32_mtime_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_neoled.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_neoled.h new file mode 100644 index 0000000..f0d7ff7 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_neoled.h @@ -0,0 +1,72 @@ +// ################################################################################################# +// # << NEORV32: neorv32_neoled.h - Smart LED Interface (NEOLED) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_neoled.h + * @author Stephan Nolting + * @brief Smart LED Interface (NEOLED) HW driver header file. + * + * @note These functions should only be used if the NEOLED unit was synthesized (IO_NEOLED_EN = true). + **************************************************************************/ + +#ifndef neorv32_neoled_h +#define neorv32_neoled_h + +// prototypes +int neorv32_neoled_available(void); +void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one); +void neorv32_neoled_setup_ws2812(void); +void neorv32_neoled_set_mode(uint32_t mode); +void neorv32_neoled_strobe_blocking(void); +void neorv32_neoled_strobe_nonblocking(void); +void neorv32_neoled_enable(void); +void neorv32_neoled_disable(void); +void neorv32_neoled_write_blocking(uint32_t data); +uint32_t neorv32_neoled_get_buffer_size(void); + + +/**********************************************************************//** + * Send single RGB(W) data word to NEOLED module (non-blocking). + * + * @warning This function uses NO busy/flag checks at all! + * + * @param[in] data LSB-aligned 24-bit RGB or 32-bit RGBW data + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_neoled_write_nonblocking(uint32_t data) { + + NEORV32_NEOLED.DATA = data; // send new LED data +} + +#endif // neorv32_neoled_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_pwm.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_pwm.h new file mode 100644 index 0000000..2ca2d19 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_pwm.h @@ -0,0 +1,56 @@ +// ################################################################################################# +// # << NEORV32: neorv32_pwm.h - Pulse Width Modulation Controller (PWM) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_pwm.h + * @author Stephan Nolting + * @brief Pulse-Width Modulation Controller (PWM) HW driver header file. + * + * @note These functions should only be used if the PWM unit was synthesized (IO_PWM_EN = true). + **************************************************************************/ + +#ifndef neorv32_pwm_h +#define neorv32_pwm_h + +// prototypes +int neorv32_pwm_available(void); +void neorv32_pwm_setup(uint8_t prsc); +void neorv32_pwm_disable(void); +void neorv32_pwm_enable(void); +int neorv32_pmw_get_num_channels(void); +void neorv32_pwm_set(uint8_t channel, uint8_t duty); +uint8_t neorv32_pwm_get(uint8_t channel); + +#endif // neorv32_pwm_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_rte.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_rte.h new file mode 100644 index 0000000..30e292c --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_rte.h @@ -0,0 +1,101 @@ +// ################################################################################################# +// # << NEORV32: neorv32_rte.h - NEORV32 Runtime Environment >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_rte.h + * @author Stephan Nolting + * @brief NEORV32 Runtime Environment. + **************************************************************************/ + +#ifndef neorv32_rte_h +#define neorv32_rte_h + +/**********************************************************************//** + * NEORV32 runtime environment trap IDs. + **************************************************************************/ +enum NEORV32_RTE_TRAP_enum { + RTE_TRAP_I_MISALIGNED = 0, /**< Instruction address misaligned */ + RTE_TRAP_I_ACCESS = 1, /**< Instruction (bus) access fault */ + RTE_TRAP_I_ILLEGAL = 2, /**< Illegal instruction */ + RTE_TRAP_BREAKPOINT = 3, /**< Breakpoint (EBREAK instruction) */ + RTE_TRAP_L_MISALIGNED = 4, /**< Load address misaligned */ + RTE_TRAP_L_ACCESS = 5, /**< Load (bus) access fault */ + RTE_TRAP_S_MISALIGNED = 6, /**< Store address misaligned */ + RTE_TRAP_S_ACCESS = 7, /**< Store (bus) access fault */ + RTE_TRAP_UENV_CALL = 8, /**< Environment call from user mode (ECALL instruction) */ + RTE_TRAP_MENV_CALL = 9, /**< Environment call from machine mode (ECALL instruction) */ + RTE_TRAP_MSI = 10, /**< Machine software interrupt */ + RTE_TRAP_MTI = 11, /**< Machine timer interrupt */ + RTE_TRAP_MEI = 12, /**< Machine external interrupt */ + RTE_TRAP_FIRQ_0 = 13, /**< Fast interrupt channel 0 */ + RTE_TRAP_FIRQ_1 = 14, /**< Fast interrupt channel 1 */ + RTE_TRAP_FIRQ_2 = 15, /**< Fast interrupt channel 2 */ + RTE_TRAP_FIRQ_3 = 16, /**< Fast interrupt channel 3 */ + RTE_TRAP_FIRQ_4 = 17, /**< Fast interrupt channel 4 */ + RTE_TRAP_FIRQ_5 = 18, /**< Fast interrupt channel 5 */ + RTE_TRAP_FIRQ_6 = 19, /**< Fast interrupt channel 6 */ + RTE_TRAP_FIRQ_7 = 20, /**< Fast interrupt channel 7 */ + RTE_TRAP_FIRQ_8 = 21, /**< Fast interrupt channel 8 */ + RTE_TRAP_FIRQ_9 = 22, /**< Fast interrupt channel 9 */ + RTE_TRAP_FIRQ_10 = 23, /**< Fast interrupt channel 10 */ + RTE_TRAP_FIRQ_11 = 24, /**< Fast interrupt channel 11 */ + RTE_TRAP_FIRQ_12 = 25, /**< Fast interrupt channel 12 */ + RTE_TRAP_FIRQ_13 = 26, /**< Fast interrupt channel 13 */ + RTE_TRAP_FIRQ_14 = 27, /**< Fast interrupt channel 14 */ + RTE_TRAP_FIRQ_15 = 28 /**< Fast interrupt channel 15 */ +}; + + +/**********************************************************************//** + * NEORV32 runtime environment: Number of available traps. + **************************************************************************/ +#define NEORV32_RTE_NUM_TRAPS 29 + + +// prototypes +void neorv32_rte_setup(void); +int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)); +int neorv32_rte_exception_uninstall(uint8_t id); + +void neorv32_rte_print_hw_config(void); +void neorv32_rte_print_hw_version(void); +void neorv32_rte_print_credits(void); +void neorv32_rte_print_logo(void); +void neorv32_rte_print_license(void); + +uint32_t neorv32_rte_get_compiler_isa(void); +int neorv32_rte_check_isa(int silent); + +#endif // neorv32_rte_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_slink.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_slink.h new file mode 100644 index 0000000..11803e4 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_slink.h @@ -0,0 +1,269 @@ +// ################################################################################################# +// # << NEORV32: neorv32_slink.h - Stream Link Interface HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_slink.h + * @author Stephan Nolting + * @brief Stream Link Interface HW driver header file. + **************************************************************************/ + +#ifndef neorv32_slink_h +#define neorv32_slink_h + +// prototypes +int neorv32_slink_available(void); +void neorv32_slink_enable(void); +void neorv32_slink_disable(void); +void neorv32_slink_rx_irq_config(int link_id, int irq_en, int irq_type); +void neorv32_slink_tx_irq_config(int link_id, int irq_en, int irq_type); +int neorv32_slink_get_rx_num(void); +int neorv32_slink_get_tx_num(void); +int neorv32_slink_get_rx_depth(void); +int neorv32_slink_get_tx_depth(void); +int neorv32_slink_check_rx_half_full(int link_id); +int neorv32_slink_check_tx_half_full(int link_id); +// non-blocking transmit +int neorv32_slink_tx0_nonblocking(uint32_t tx_data); +int neorv32_slink_tx1_nonblocking(uint32_t tx_data); +int neorv32_slink_tx2_nonblocking(uint32_t tx_data); +int neorv32_slink_tx3_nonblocking(uint32_t tx_data); +int neorv32_slink_tx4_nonblocking(uint32_t tx_data); +int neorv32_slink_tx5_nonblocking(uint32_t tx_data); +int neorv32_slink_tx6_nonblocking(uint32_t tx_data); +int neorv32_slink_tx7_nonblocking(uint32_t tx_data); +// non-blocking receive +int neorv32_slink_rx0_nonblocking(uint32_t *rx_data); +int neorv32_slink_rx1_nonblocking(uint32_t *rx_data); +int neorv32_slink_rx2_nonblocking(uint32_t *rx_data); +int neorv32_slink_rx3_nonblocking(uint32_t *rx_data); +int neorv32_slink_rx4_nonblocking(uint32_t *rx_data); +int neorv32_slink_rx5_nonblocking(uint32_t *rx_data); +int neorv32_slink_rx6_nonblocking(uint32_t *rx_data); +int neorv32_slink_rx7_nonblocking(uint32_t *rx_data); + + +/**********************************************************************//** + * Write data to TX stream link 0 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx0_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[0] = tx_data; +} + + +/**********************************************************************//** + * Write data to TX stream link 1 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx1_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[1] = tx_data; +} + + +/**********************************************************************//** + * Write data to TX stream link 2 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx2_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[2] = tx_data; +} + + +/**********************************************************************//** + * Write data to TX stream link 3 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx3_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[3] = tx_data; +} + + +/**********************************************************************//** + * Write data to TX stream link 4 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx4_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[4] = tx_data; +} + + +/**********************************************************************//** + * Write data to TX stream link 5 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx5_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[5] = tx_data; +} + + +/**********************************************************************//** + * Write data to TX stream link 6 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx6_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[6] = tx_data; +} + + +/**********************************************************************//** + * Write data to TX stream link 7 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in] tx_data Data to send to link. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_tx7_blocking(uint32_t tx_data) { + NEORV32_SLINK.DATA[7] = tx_data; +} + + +/**********************************************************************//** + * Read data from RX stream link 0 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx0_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[0]; +} + + +/**********************************************************************//** + * Read data from RX stream link 1 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx1_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[1]; +} + + +/**********************************************************************//** + * Read data from RX stream link 2 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx2_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[2]; +} + + +/**********************************************************************//** + * Read data from RX stream link 3 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx3_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[3]; +} + + +/**********************************************************************//** + * Read data from RX stream link 4 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx4_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[4]; +} + + +/**********************************************************************//** + * Read data from RX stream link 5 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx5_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[5]; +} + + +/**********************************************************************//** + * Read data from RX stream link 6 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx6_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[6]; +} + + +/**********************************************************************//** + * Read data from RX stream link 7 (blocking!) + * + * @warning This function will raise an exception when the bus access times out! + * + * @param[in,out] rx_data Pointer to return read data. + **************************************************************************/ +inline void __attribute__ ((always_inline)) neorv32_slink_rx7_blocking(uint32_t *rx_data) { + *rx_data = NEORV32_SLINK.DATA[7]; +} + + +#endif // neorv32_slink_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_spi.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_spi.h new file mode 100644 index 0000000..20d313b --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_spi.h @@ -0,0 +1,59 @@ +// ################################################################################################# +// # << NEORV32: neorv32_spi.h - Serial Peripheral Interface Controller (SPI) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_spi.h + * @author Stephan Nolting + * @brief Serial peripheral interface controller (SPI) HW driver header file. + * + * @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true). + **************************************************************************/ + +#ifndef neorv32_spi_h +#define neorv32_spi_h + +// prototypes +int neorv32_spi_available(void); +void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size); +void neorv32_spi_disable(void); +void neorv32_spi_enable(void); +void neorv32_spi_cs_en(uint8_t cs); +void neorv32_spi_cs_dis(uint8_t cs); +uint32_t neorv32_spi_trans(uint32_t tx_data); +void neorv32_spi_put_nonblocking(uint32_t tx_data); +uint32_t neorv32_spi_get_nonblocking(void); +int neorv32_spi_busy(void); + +#endif // neorv32_spi_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_trng.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_trng.h new file mode 100644 index 0000000..0e59297 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_trng.h @@ -0,0 +1,53 @@ +// ################################################################################################# +// # << NEORV32: neorv32_trng.h - True Random Number Generator (TRNG) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_trng.h + * @author Stephan Nolting + * @brief True Random Number Generator (TRNG) HW driver header file. + * + * @note These functions should only be used if the TRNG unit was synthesized (IO_TRNG_EN = true). + **************************************************************************/ + +#ifndef neorv32_trng_h +#define neorv32_trng_h + +// prototypes +int neorv32_trng_available(void); +void neorv32_trng_enable(void); +void neorv32_trng_disable(void); +int neorv32_trng_get(uint8_t *data); + +#endif // neorv32_trng_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_twi.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_twi.h new file mode 100644 index 0000000..7ed224a --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_twi.h @@ -0,0 +1,61 @@ +// ################################################################################################# +// # << NEORV32: neorv32_twi.h - Two-Wire Interface Controller (TWI) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_twi.h + * @author Stephan Nolting + * @brief Two-Wire Interface Controller (TWI) HW driver header file. + * + * @note These functions should only be used if the TWI unit was synthesized (IO_TWI_EN = true). + **************************************************************************/ + +#ifndef neorv32_twi_h +#define neorv32_twi_h + +// prototypes +int neorv32_twi_available(void); +void neorv32_twi_setup(uint8_t prsc); +void neorv32_twi_disable(void); +void neorv32_twi_enable(void); +void neorv32_twi_mack_enable(void); +void neorv32_twi_mack_disable(void); +int neorv32_twi_busy(void); +int neorv32_twi_start_trans(uint8_t a); +int neorv32_twi_trans(uint8_t d); +uint8_t neorv32_twi_get_data(void); +void neorv32_twi_generate_stop(void); +void neorv32_twi_generate_start(void); + +#endif // neorv32_twi_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_uart.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_uart.h new file mode 100644 index 0000000..65d3812 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_uart.h @@ -0,0 +1,82 @@ +// ################################################################################################# +// # << NEORV32: neorv32_uart.h - Universal Asynchronous Receiver/Transmitter (UART) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_uart.h + * @author Stephan Nolting + * @brief Universal asynchronous receiver/transmitter (UART0/UART1) HW driver header file + * + * @warning UART0 (primary UART) is used as default user console interface for all NEORV32 software framework/library functions. + * + * @note These functions should only be used if the UART0/UART1 unit was synthesized (IO_UART0_EN = true / IO_UART1_EN = true). + **************************************************************************/ + +#ifndef neorv32_uart_h +#define neorv32_uart_h + +// Libs required by functions +#include + +// prototypes for UART0 (primary UART) +int neorv32_uart0_available(void); +void neorv32_uart0_setup(uint32_t baudrate, uint8_t parity, uint8_t flow_con); +void neorv32_uart0_disable(void); +void neorv32_uart0_enable(void); +void neorv32_uart0_putc(char c); +int neorv32_uart0_tx_busy(void); +char neorv32_uart0_getc(void); +int neorv32_uart0_char_received(void); +int neorv32_uart0_getc_safe(char *data); +char neorv32_uart0_char_received_get(void); +void neorv32_uart0_print(const char *s); +void neorv32_uart0_printf(const char *format, ...); +int neorv32_uart0_scan(char *buffer, int max_size, int echo); + +// prototypes for UART1 (secondary UART) +int neorv32_uart1_available(void); +void neorv32_uart1_setup(uint32_t baudrate, uint8_t parity, uint8_t flow_con); +void neorv32_uart1_disable(void); +void neorv32_uart1_enable(void); +void neorv32_uart1_putc(char c); +int neorv32_uart1_tx_busy(void); +char neorv32_uart1_getc(void); +int neorv32_uart1_char_received(void); +int neorv32_uart1_getc_safe(char *data); +char neorv32_uart1_char_received_get(void); +void neorv32_uart1_print(const char *s); +void neorv32_uart1_printf(const char *format, ...); +int neorv32_uart1_scan(char *buffer, int max_size, int echo); + +#endif // neorv32_uart_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_wdt.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_wdt.h new file mode 100644 index 0000000..6ed0580 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_wdt.h @@ -0,0 +1,55 @@ +// ################################################################################################# +// # << NEORV32: neorv32_wdt.h - Watchdog Timer (WDT) HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_wdt.h + * @author Stephan Nolting + * @brief Watchdog Timer (WDT) HW driver header file. + * + * @note These functions should only be used if the WDT unit was synthesized (IO_WDT_EN = true). + **************************************************************************/ + +#ifndef neorv32_wdt_h +#define neorv32_wdt_h + +// prototypes +int neorv32_wdt_available(void); +void neorv32_wdt_setup(uint8_t prsc, uint8_t mode, uint8_t lock); +int neorv32_wdt_disable(void); +void neorv32_wdt_reset(void); +int neorv32_wdt_get_cause(void); +void neorv32_wdt_force(void); + +#endif // neorv32_wdt_h diff --git a/Libs/RiscV/NEORV32/sw/lib/include/neorv32_xirq.h b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_xirq.h new file mode 100644 index 0000000..08f9b1f --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/lib/include/neorv32_xirq.h @@ -0,0 +1,59 @@ +// ################################################################################################# +// # << NEORV32: neorv32_xirq.h - External Interrupt controller HW Driver >> # +// # ********************************************************************************************* # +// # BSD 3-Clause License # +// # # +// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +// # # +// # Redistribution and use in source and binary forms, with or without modification, are # +// # permitted provided that the following conditions are met: # +// # # +// # 1. Redistributions of source code must retain the above copyright notice, this list of # +// # conditions and the following disclaimer. # +// # # +// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +// # conditions and the following disclaimer in the documentation and/or other materials # +// # provided with the distribution. # +// # # +// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +// # endorse or promote products derived from this software without specific prior written # +// # permission. # +// # # +// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +// # OF THE POSSIBILITY OF SUCH DAMAGE. # +// # ********************************************************************************************* # +// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +// ################################################################################################# + + +/**********************************************************************//** + * @file neorv32_xirq.h + * @author Stephan Nolting + * @brief External Interrupt controller HW driver header file. + **************************************************************************/ + +#ifndef neorv32_xirq_h +#define neorv32_xirq_h + +// prototypes +int neorv32_xirq_available(void); +int neorv32_xirq_setup(void); +void neorv32_xirq_global_enable(void); +void neorv32_xirq_global_disable(void); +int neorv32_xirq_get_num(void); +void neorv32_xirq_clear_pending(uint8_t ch); +void neorv32_xirq_channel_enable(uint8_t ch); +void neorv32_xirq_channel_disable(uint8_t ch); + +int neorv32_xirq_install(uint8_t ch, void (*handler)(void)); +int neorv32_xirq_uninstall(uint8_t ch); + + +#endif // neorv32_xirq_h diff --git a/Libs/RiscV/NEORV32/sw/ocd-firmware/.gitignore b/Libs/RiscV/NEORV32/sw/ocd-firmware/.gitignore new file mode 100644 index 0000000..ed70f60 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/ocd-firmware/.gitignore @@ -0,0 +1 @@ +*.vhd diff --git a/Libs/RiscV/NEORV32/sw/ocd-firmware/README.md b/Libs/RiscV/NEORV32/sw/ocd-firmware/README.md new file mode 100644 index 0000000..9821d35 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/ocd-firmware/README.md @@ -0,0 +1,18 @@ +# NEORV32 On-Chip Debugger (OCD) - "Park Loop" Code + +This folder contains the ASM sources for the *execution-based* debugger code ROM. +`park_loop.S` contains the "park loop" that is executed when the CPU is in debug mode. This code is used to communicate +with the *debug module (DM)* and is responsible for: + +* acknowledging halt requests +* processing and acknowledging resume requests +* processing and acknowledging "execute program buffer" requests +* executing the program buffer (provided by the DM) +* catching exceptions while in debug mode + +The park loop code is implemented as endless loop that polls the status register of the *debug memory (DBMEM)* module +to check for requests from the DM and sets according flags in the status register to acknowledge these requests. + +:warning: Executing `make clean_all all` will **NOT** update the actual debugger code ROM that will be synthesized. +The interface with the DM will break if there are any bugs in this code. However, if you wish to update the code ROM, +copy the array content from `neorv32_debug_mem.code.vhd` to the `code_rom_file` constant in `rtl/core/neorv32_debug_dbmem.vhd`. diff --git a/Libs/RiscV/NEORV32/sw/ocd-firmware/debug_rom.ld b/Libs/RiscV/NEORV32/sw/ocd-firmware/debug_rom.ld new file mode 100644 index 0000000..1c9dcd8 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/ocd-firmware/debug_rom.ld @@ -0,0 +1,67 @@ +/* ################################################################################################# */ +/* # << NEORV32 - RISC-V GCC Linker Script >> # */ +/* # ********************************************************************************************* # */ +/* # For the execution based on-chip debugger code memory (/ROM() - "park loop" code # */ +/* # ********************************************************************************************* # */ +/* # BSD 3-Clause License # */ +/* # # */ +/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */ +/* # # */ +/* # Redistribution and use in source and binary forms, with or without modification, are # */ +/* # permitted provided that the following conditions are met: # */ +/* # # */ +/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */ +/* # conditions and the following disclaimer. # */ +/* # # */ +/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */ +/* # conditions and the following disclaimer in the documentation and/or other materials # */ +/* # provided with the distribution. # */ +/* # # */ +/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */ +/* # endorse or promote products derived from this software without specific prior written # */ +/* # permission. # */ +/* # # */ +/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */ +/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */ +/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */ +/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */ +/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */ +/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */ +/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */ +/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */ +/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */ +/* # ********************************************************************************************* # */ +/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */ +/* ################################################################################################# */ + +/* Default linker script, for normal executables */ +/* Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copying and distribution of this script, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. */ + +/* modified for the NEORV32 processor by Stephan Nolting */ + + +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(_start) +SEARCH_DIR("/opt/riscv/riscv32-unknown-elf/lib"); SEARCH_DIR("=/opt/riscv/riscv64-unknown-linux-gnu/lib"); SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib"); + +MEMORY +{ + debug_mem (rx) : ORIGIN = 0xFFFFF800, LENGTH = 128 +} +/* ************************************************************************* */ + +SECTIONS +{ + + /* Actual instructions */ + .text : + { + KEEP(*(.text)); + + } > debug_mem + +} diff --git a/Libs/RiscV/NEORV32/sw/ocd-firmware/makefile b/Libs/RiscV/NEORV32/sw/ocd-firmware/makefile new file mode 100644 index 0000000..ea759b2 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/ocd-firmware/makefile @@ -0,0 +1,294 @@ +################################################################################################# +# << NEORV32 - Application Makefile >> # +# ********************************************************************************************* # +# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. # +# ********************************************************************************************* # +# FOR DEBUGGER "PARK LOOP" CODE ONLY! # +# ********************************************************************************************* # +# BSD 3-Clause License # +# # +# Copyright (c) 2021, Stephan Nolting. All rights reserved. # +# # +# Redistribution and use in source and binary forms, with or without modification, are # +# permitted provided that the following conditions are met: # +# # +# 1. Redistributions of source code must retain the above copyright notice, this list of # +# conditions and the following disclaimer. # +# # +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +# conditions and the following disclaimer in the documentation and/or other materials # +# provided with the distribution. # +# # +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +# endorse or promote products derived from this software without specific prior written # +# permission. # +# # +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +# OF THE POSSIBILITY OF SUCH DAMAGE. # +# ********************************************************************************************* # +# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +################################################################################################# + + +# ***************************************************************************** +# USER CONFIGURATION +# ***************************************************************************** +# User's application sources (*.c, *.cpp, *.s, *.S); add additional files here +APP_SRC ?= $(wildcard ./*.S) + +# User's application include folders (don't forget the '-I' before each entry) +APP_INC ?= -I . +# User's application include folders - for assembly files only (don't forget the '-I' before each entry) +ASM_INC ?= -I . + +# Optimization +EFFORT ?= -Os + +# Compiler toolchain +RISCV_PREFIX ?= riscv32-unknown-elf- + +# CPU architecture and ABI +MARCH = rv32i +MABI = ilp32 + +# User flags for additional configuration (will be added to compiler flags) +USER_FLAGS ?= + +# Relative or absolute path to the NEORV32 home folder +NEORV32_HOME ?= ../.. +# ***************************************************************************** + + + +# ----------------------------------------------------------------------------- +# NEORV32 framework +# ----------------------------------------------------------------------------- +# Path to NEORV32 linker script and startup file +NEORV32_COM_PATH = $(NEORV32_HOME)/sw/common +# Path to main NEORV32 library include files +NEORV32_INC_PATH = $(NEORV32_HOME)/sw/lib/include +# Path to main NEORV32 library source files +NEORV32_SRC_PATH = $(NEORV32_HOME)/sw/lib/source +# Path to NEORV32 executable generator +NEORV32_EXG_PATH = $(NEORV32_HOME)/sw/image_gen +# Path to NEORV32 core rtl folder +NEORV32_RTL_PATH = $(NEORV32_HOME)/rtl/core +# Marker file to check for NEORV32 home folder +NEORV32_HOME_MARKER = $(NEORV32_INC_PATH)/neorv32.h + +# Linker script +LD_SCRIPT = ./debug_rom.ld + +# Main output files +APP_ASM = main.asm +APP_IMG = neorv32_debug_mem.code.vhd + + +# ----------------------------------------------------------------------------- +# Sources and objects +# ----------------------------------------------------------------------------- +# Define all sources +SRC = $(APP_SRC) + +# Define all object files +OBJ = $(SRC:%=%.o) + + +# ----------------------------------------------------------------------------- +# Tools and flags +# ----------------------------------------------------------------------------- +# Compiler tools +CC = $(RISCV_PREFIX)gcc +OBJDUMP = $(RISCV_PREFIX)objdump +OBJCOPY = $(RISCV_PREFIX)objcopy +SIZE = $(RISCV_PREFIX)size + +# Host native compiler +CC_X86 = g++ -Wall -O -g + +# NEORV32 executable image generator +IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen + +# Compiler & linker flags +CC_OPTS = -march=$(MARCH) -mabi=$(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv +CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc +# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) +CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 +CC_OPTS += $(USER_FLAGS) + + +# ----------------------------------------------------------------------------- +# Application output definitions +# ----------------------------------------------------------------------------- +.PHONY: check info help elf_info clean clean_all bootloader +.DEFAULT_GOAL := help + +# 'compile' is still here for compatibility +compile: $(APP_ASM) +install: $(APP_ASM) $(APP_IMG) +all: $(APP_ASM) $(APP_IMG) + +# Check if making bootloader +# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) +# Also define "make_bootloader" for crt0.S +target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader + + +# ----------------------------------------------------------------------------- +# Image generator targets +# ----------------------------------------------------------------------------- +# install/compile tools +$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.c + @echo Compiling $(IMAGE_GEN) + @$(CC_X86) $< -o $(IMAGE_GEN) + + +# ----------------------------------------------------------------------------- +# General targets: Assemble, compile, link, dump +# ----------------------------------------------------------------------------- +# Compile app *.s sources (assembly) +%.s.o: %.s + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ + +# Compile app *.S sources (assembly + C pre-processor) +%.S.o: %.S + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ + +# Compile app *.c sources +%.c.o: %.c + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ + +# Compile app *.cpp sources +%.cpp.o: %.cpp + @$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ + +# Link object files and show memory utilization +main.elf: $(OBJ) + @$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm + @echo "Memory utilization:" + @$(SIZE) main.elf + +# Assembly listing file (for debugging) +$(APP_ASM): main.elf + @$(OBJDUMP) -d -S -z $< > $@ + +# Generate final executable from .text only +main.bin: main.elf $(APP_ASM) + @$(OBJCOPY) -I elf32-little $< -j .text -O binary text.bin + @cat text.bin > $@ + @rm -f text.bin + + +# ----------------------------------------------------------------------------- +# Application targets: install (as VHDL file) +# ----------------------------------------------------------------------------- + +# Generate NEORV32 executable VHDL boot image +$(APP_IMG): main.bin $(IMAGE_GEN) + @set -e + @$(IMAGE_GEN) -app_img $< $@ $(shell basename $(CURDIR)) + + +# ----------------------------------------------------------------------------- +# Check toolchain +# ----------------------------------------------------------------------------- +check: $(IMAGE_GEN) + @echo "---------------- Check: NEORV32_HOME folder ----------------" +ifneq ($(shell [ -e $(NEORV32_HOME_MARKER) ] && echo 1 || echo 0 ), 1) +$(error NEORV32_HOME folder not found!) +endif + @echo "NEORV32_HOME: $(NEORV32_HOME)" + @echo "---------------- Check: $(CC) ----------------" + @$(CC) -v + @echo "---------------- Check: $(OBJDUMP) ----------------" + @$(OBJDUMP) -V + @echo "---------------- Check: $(OBJCOPY) ----------------" + @$(OBJCOPY) -V + @echo "---------------- Check: $(SIZE) ----------------" + @$(SIZE) -V + @echo "---------------- Check: NEORV32 image_gen ----------------" + @$(IMAGE_GEN) -help + @echo "---------------- Check: Native GCC ----------------" + @$(CC_X86) -v + @echo + @echo "Toolchain check OK" + + +# ----------------------------------------------------------------------------- +# Show configuration +# ----------------------------------------------------------------------------- +info: + @echo "---------------- Info: Project ----------------" + @echo "Project folder: $(shell basename $(CURDIR))" + @echo "Source files: $(APP_SRC)" + @echo "Include folder(s): $(APP_INC)" + @echo "ASM include folder(s): $(ASM_INC)" + @echo "---------------- Info: NEORV32 ----------------" + @echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" + @echo "IMAGE_GEN: $(IMAGE_GEN)" + @echo "Core source files:" + @echo "$(CORE_SRC)" + @echo "Core include folder:" + @echo "$(NEORV32_INC_PATH)" + @echo "---------------- Info: Objects ----------------" + @echo "Project object files:" + @echo "$(OBJ)" + @echo "---------------- Info: RISC-V CPU ----------------" + @echo "MARCH: $(MARCH)" + @echo "MABI: $(MABI)" + @echo "---------------- Info: Toolchain ----------------" + @echo "Toolchain: $(RISCV_TOLLCHAIN)" + @echo "CC: $(CC)" + @echo "OBJDUMP: $(OBJDUMP)" + @echo "OBJCOPY: $(OBJCOPY)" + @echo "SIZE: $(SIZE)" + @echo "---------------- Info: Compiler Libraries ----------------" + @echo "LIBGCC:" + @$(CC) -print-libgcc-file-name + @echo "SEARCH-DIRS:" + @$(CC) -print-search-dirs + @echo "---------------- Info: Flags ----------------" + @echo "USER_FLAGS: $(USER_FLAGS)" + @echo "CC_OPTS: $(CC_OPTS)" + @echo "---------------- Info: Host Native GCC Flags ----------------" + @echo "CC_X86: $(CC_X86)" + + +# ----------------------------------------------------------------------------- +# Show final ELF details (just for debugging) +# ----------------------------------------------------------------------------- +elf_info: main.elf + @$(OBJDUMP) -x main.elf + + +# ----------------------------------------------------------------------------- +# Help +# ----------------------------------------------------------------------------- +help: + @echo "<<< NEORV32 Application Makefile >>>" + @echo "Make sure to add the bin folder of RISC-V GCC to your PATH variable." + @echo "Targets:" + @echo " help - show this text" + @echo " check - check toolchain" + @echo " info - show makefile/toolchain configuration" + @echo " exe - compile and generate executable for upload via bootloader" + @echo " all - compile and generate executable for upload via bootloader and generate and install VHDL IMEM boot image (for application)" + @echo " clean - clean up project" + @echo " clean_all - clean up project, core libraries and image generator" + + +# ----------------------------------------------------------------------------- +# Clean up +# ----------------------------------------------------------------------------- +clean: + @rm -f *.elf *.o *.bin *.out *.asm *.vhd + +clean_all: clean + @rm -f $(OBJ) $(IMAGE_GEN) diff --git a/Libs/RiscV/NEORV32/sw/ocd-firmware/park_loop.S b/Libs/RiscV/NEORV32/sw/ocd-firmware/park_loop.S new file mode 100644 index 0000000..5c02185 --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/ocd-firmware/park_loop.S @@ -0,0 +1,103 @@ +/* ################################################################################################# */ +/* # << NEORV32 - park_loop.S - Execution-Based On-Chip Debugger - Park Loop Code >> # */ +/* # ********************************************************************************************* # */ +/* # BSD 3-Clause License # */ +/* # # */ +/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */ +/* # # */ +/* # Redistribution and use in source and binary forms, with or without modification, are # */ +/* # permitted provided that the following conditions are met: # */ +/* # # */ +/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */ +/* # conditions and the following disclaimer. # */ +/* # # */ +/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */ +/* # conditions and the following disclaimer in the documentation and/or other materials # */ +/* # provided with the distribution. # */ +/* # # */ +/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */ +/* # endorse or promote products derived from this software without specific prior written # */ +/* # permission. # */ +/* # # */ +/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */ +/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */ +/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */ +/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */ +/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */ +/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */ +/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */ +/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */ +/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */ +/* # ********************************************************************************************* # */ +/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */ +/* ################################################################################################# */ + +// debug memory address map +.equ DBMEM_CODE_BASE, 0xfffff800 // base address of dbmem.code_memory +.equ DBMEM_PBUF_BASE, 0xfffff880 // base address of dbmem.program_buffer +.equ DBMEM_DBUF_BASE, 0xfffff900 // base address of dbmem.data_buffer +.equ DBMEM_SREG_BASE, 0xfffff980 // base address of dbmem.status_register + +// status register (SREG) bits +.equ SREG_HALTED_ACK, (1<<0) // -/w: CPU is halted in debug mode and waits in park loop +.equ SREG_RESUME_REQ, (1<<1) // r/-: DM requests CPU to resume +.equ SREG_RESUME_ACK, (1<<2) // -/w: CPU starts resuming +.equ SREG_EXECUTE_REQ, (1<<3) // r/-: DM requests to execute program buffer +.equ SREG_EXECUTE_ACK, (1<<4) // -/w: CPU starts to execute program buffer +.equ SREG_EXCEPTION_ACK, (1<<5) // -/w: CPU has detected an exception + +.file "park_loop.S" +.section .text +.balign 4 +.option norvc +.global _start +.global entry_normal +.global entry_exception + + +_start: + +// BASE + 0: entry for ebreak in debug-mode, halt request or return from single-stepped instruction +entry_normal: + jal zero, parking_loop_start + +// BASE + 4: entry for exceptions - signal EXCEPTION to DM and restart parking loop +entry_exception: + csrw dscratch0, s0 // save s0 to dscratch0 so we have a general purpose register available + addi s0, zero, SREG_EXCEPTION_ACK // mask exception acknowledge flag + sw s0, DBMEM_SREG_BASE(zero) // trigger exception acknowledge to inform DM + csrr s0, dscratch0 // restore s0 from dscratch0 + ebreak // restart parking loop + +// "parking loop": endless loop that polls the status register to check if the DM +// wants to execute code from the program buffer or to resume normal CPU/application operation +parking_loop_start: + csrw dscratch0, s0 // save s0 to dscratch0 so we have a general purpose register available + addi s0, zero, SREG_HALTED_ACK + sw s0, DBMEM_SREG_BASE(zero) // ACK that CPU has halted + +parking_loop: + lw s0, DBMEM_SREG_BASE(zero) // get status register + andi s0, s0, SREG_EXECUTE_REQ // request to execute program buffer? + bnez s0, execute_progbuf // execute program buffer + + lw s0, DBMEM_SREG_BASE(zero) // get status register + andi s0, s0, SREG_RESUME_REQ // request to resume? + bnez s0, resume // resume normal operation + + jal zero, parking_loop // restart parking loop polling + +// resume normal operation +resume: + addi s0, zero, SREG_RESUME_ACK + sw s0, DBMEM_SREG_BASE(zero) // ACK that CPU is about to resume + csrr s0, dscratch0 // restore s0 from dscratch0 + dret // end debug mode + +// execute program buffer +execute_progbuf: + addi s0, zero, SREG_EXECUTE_ACK + sw s0, DBMEM_SREG_BASE(zero) // ACK that execution is about to start + csrr s0, dscratch0 // restore s0 from dscratch0 + fence.i // synchronize i-cache & prefetch with memory (program buffer) + jalr zero, zero, %lo(DBMEM_PBUF_BASE) // jump to beginning of program buffer diff --git a/Libs/RiscV/NEORV32/sw/openocd/openocd_neorv32.cfg b/Libs/RiscV/NEORV32/sw/openocd/openocd_neorv32.cfg new file mode 100644 index 0000000..cbe1e3e --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/openocd/openocd_neorv32.cfg @@ -0,0 +1,41 @@ +# openOCD configuration file for generic FT2232H-based USB-jtag interface +# references: https://mcuoneclipse.com/2019/10/20/jtag-debugging-the-esp32-with-ft2232-and-openocd/ + +# ---------------------------------------------- +# Interface configuration +# ---------------------------------------------- + +# FT2232H pinout: +# TCK: D0 +# TDI: D1 +# TDO: D2 +# TMS: D3 +# TRST: D4 (low-active, optional - pull input pin high if not used) + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0x0038 0x003b + +adapter speed 1000 +ftdi_layout_signal nTRST -ndata 0x0010 -noe 0x0040 +transport select jtag + +# ---------------------------------------------- +# Target configuration +# ---------------------------------------------- + +set _CHIPNAME neorv32 +set _JTAGID 0x0cafe001 +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_JTAGID + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME + +# ---------------------------------------------- +# Scratch pad RAM +# ---------------------------------------------- + +# work area ("scratch pad RAM"): beginning of (internal) DMEM, 256 bytes, requires(!) backup +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 256 -work-area-backup 1 diff --git a/Libs/RiscV/NEORV32/sw/svd/README.md b/Libs/RiscV/NEORV32/sw/svd/README.md new file mode 100644 index 0000000..10b7c2e --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/svd/README.md @@ -0,0 +1,10 @@ +# NEORV32 System View Description (SVD) File + +Manually created from `sw/lib/include/neorv32.h`. + +* Format: CMSIS-SVD +* Copyright by ARM Ltd, Apache-2.0 License +* Documentation: + * https://www.keil.com/pack/doc/CMSIS/SVD/html/index.html + * https://github.com/ARM-software/CMSIS + * https://github.com/ARM-software/CMSIS_5 diff --git a/Libs/RiscV/NEORV32/sw/svd/neorv32.svd b/Libs/RiscV/NEORV32/sw/svd/neorv32.svd new file mode 100644 index 0000000..4e9371c --- /dev/null +++ b/Libs/RiscV/NEORV32/sw/svd/neorv32.svd @@ -0,0 +1,1189 @@ + + + + stnolting + neorv32 + RISC-V + 1.6.4 + The NEORV32 RISC-V Processor + + + + NEORV32 + r2p0 + little + true + true + false + false + true + true + 0 + false + + + + 8 + 32 + 32 + read-write + 0x00000000 + 0x00000000 + + + + + + + CFS + Custom functions subsystem + CFS + 0xFFFFFE00 + + CFS_FIRQ1 + + + 0 + 0x80 + registers + + + + REG0Application-defined0x00 + REG1Application-defined0x04 + REG2Application-defined0x08 + REG3Application-defined0x0C + REG4Application-defined0x10 + REG5Application-defined0x14 + REG6Application-defined0x18 + REG7Application-defined0x1C + REG8Application-defined0x20 + REG9Application-defined0x24 + REG10Application-defined0x28 + REG11Application-defined0x2C + REG12Application-defined0x30 + REG13Application-defined0x34 + REG14Application-defined0x38 + REG15Application-defined0x3C + REG16Application-defined0x40 + REG17Application-defined0x44 + REG18Application-defined0x48 + REG19Application-defined0x4C + REG20Application-defined0x50 + REG21Application-defined0x54 + REG22Application-defined0x58 + REG23Application-defined0x5C + REG24Application-defined0x60 + REG25Application-defined0x64 + REG26Application-defined0x68 + REG27Application-defined0x6C + REG28Application-defined0x70 + REG29Application-defined0x74 + REG30Application-defined0x78 + REG31Application-defined0x7C + + + + + + PWM + Pulse-width modulation controller + PWM + 0xFFFFFE80 + + + 0 + 0x40 + registers + + + + + CTRL + Control register + 0x00 + + + PWM_CTRL_EN + [0:0] + PWM controller enable flag + + + PWM_CTRL_PRSCx + [3:1] + Clock prescaler select + + + + + DUTY0 + Duty cycle register 0 + 0x04 + + + DUTY1 + Duty cycle register 1 + 0x08 + + + DUTY2 + Duty cycle register 2 + 0x0C + + + DUTY3 + Duty cycle register 3 + 0x10 + + + DUTY4 + Duty cycle register 4 + 0x14 + + + DUTY5 + Duty cycle register 5 + 0x18 + + + DUTY6 + Duty cycle register 6 + 0x1C + + + DUTY7 + Duty cycle register 7 + 0x20 + + + DUTY8 + Duty cycle register 8 + 0x24 + + + DUTY9 + Duty cycle register 9 + 0x28 + + + DUTY10 + Duty cycle register 10 + 0x2C + + + DUTY11 + Duty cycle register 11 + 0x30 + + + DUTY12 + Duty cycle register 12 + 0x34 + + + DUTY13 + Duty cycle register 13 + 0x38 + + + DUTY14 + Duty cycle register 14 + 0x3C + + + + + + + SLINK + Stream link interface + SLINK + 0xFFFFFEC0 + + SLINK_RX_FIRQ10 + SLINK_TX_FIRQ11 + + + 0 + 0x40 + registers + + + + + CTRL + Control register + 0x00 + + + SLINK_CTRL_RX_NUMx + read-only + [3:0] + Number of implemented RX links + + + SLINK_CTRL_TX_NUMx + read-only + [7:4] + Number of implemented TX links + + + SLINK_CTRL_RX_FIFO_Sx + read-only + [11:8] + log2(RX FIFO size) + + + SLINK_CTRL_TX_FIFO_Sx + read-only + [15:12] + log2(TX FIFO size) + + + SLINK_CTRL_EN + read-write + [31:31] + SLINK enable flag + + + + + IRQ + Link interrupt configuration register + 0x08 + + + SLINK_IRQ_RX_EN + [7:0] + RX link interrupt enable + + + SLINK_IRQ_RX_MODE + [15:8] + RX link interrupt mode + + + SLINK_IRQ_TX_EN + [23:16] + TX link interrupt enable + + + SLINK_IRQ_TX_MODE + [31:24] + TX link interrupt mode + + + + + STATUS + Link status register + 0x10 + + + SLINK_STATUS_RX_AVAIL + [7:0] + RX link n FIFO is NOT empty (data available) + + + SLINK_STATUS_TX_FREE + [15:8] + TX link n FIFO is NOT full (ready to send) + + + SLINK_STATUS_RX_HALF + [23:16] + RX link n FIFO fill level is >= half-full + + + SLINK_STATUS_TX_HALF + [31:24] + TX link 0 FIFO fill level is > half-full + + + + + DATA0 + Link 0 RTX data register + 0x20 + + + DATA1 + Link 1 RTX data register + 0x24 + + + DATA2 + Link 2 RTX data register + 0x28 + + + DATA3 + Link 3 RTX data register + 0x2C + + + DATA4 + Link 4 RTX data register + 0x30 + + + DATA5 + Link 5 RTX data register + 0x34 + + + DATA6 + Link 6 RTX data register + 0x38 + + + DATA7 + Link 7 RTX data register + 0x3C + + + + + + + GPTMR + General purpose timer + GPTMR + 0xFFFFFF60 + + GPTMR_FIRQ12 + + + 0 + 0x10 + registers + + + + + CTRL + Control register + 0x00 + + + GPTMR_CTRL_EN + [0:0] + Timer enable flag + + + GPTMR_CTRL_PRSC + [3:1] + Clock prescaler select + + + GPTMR_CTRL_MODE + [4:4] + Timer mode: 0=single-shot mode, 1=continuous mode + + + + + THRES + Threshold register + 0x04 + + + COUNT + Counter register + 0x08 + + + + + + + BUSKEEPER + Bus keeper + BUSKEEPER + 0xFFFFFF7C + + + 0 + 0x04 + registers + + + + + CTRL + Control register + 0x00 + + + BUSKEEPER_ERR_TYPE + [0:0] + read-only + Bus error type: 0=device error, 1=access timeout + + + BUSKEEPER_ERR_FLAG + [31:31] + Sticky error flag, clears after read or write access + + + + + + + + + XIRQ + External interrupts controller + XIRQ + 0xFFFFFF80 + + XIRQ_FIRQ8 + + + 0 + 0x10 + registers + + + + + IER + IRQ input enable register + 0x00 + + + IPR + IRQ pending/ack/clear register + 0x04 + + + SCR + IRQ source register + 0x08 + + + + + + + MTIME + Machine timer + MTIME + 0xFFFFFF90 + + + 0 + 0x10 + registers + + + + + TIME_LO + System time register - low + 0x00 + + + TIME_HI + System time register - high + 0x04 + + + TIMECMP_LO + Time compare register - low + 0x08 + + + TIMECMP_HI + Time compare register - high + 0x0C + + + + + + + UART0 + Primary universal asynchronous receiver and transmitter + UART0 + 0xFFFFFFA0 + + UART0_RX_FIRQ2 + UART0_TX_FIRQ3 + + + 0 + 0x08 + registers + + + + + CTRL + Control register + 0x00 + + + UART_CTRL_BAUD + [11:0] + Baud rate divisor + + + UART_CTRL_SIM_MODE + [12:12] + Simulation output override enable, for use in simulation only + + + UART_CTRL_RX_EMPTY + [13:13] + read-only + RX FIFO is empty + + + UART_CTRL_RX_HALF + [14:14] + read-only + RX FIFO is at least half-full + + + UART_CTRL_RX_FULL + [15:15] + read-only + RX FIFO is full + + + UART_CTRL_TX_EMPTY + [16:16] + read-only + TX FIFO is empty + + + UART_CTRL_TX_HALF + [17:17] + read-only + TX FIFO is at least half-full + + + UART_CTRL_TX_FULL + [18:18] + read-only + TX FIFO is full + + + UART_CTRL_RTS_EN + [20:20] + Enable hardware flow control: Assert RTS output if UART.RX is ready to receive + + + UART_CTRL_CTS_EN + [21:21] + Enable hardware flow control: UART.TX starts sending only if CTS input is asserted + + + UART_CTRL_PMODE0 + [22:22] + Parity configuration (0=even; 1=odd) + + + UART_CTRL_PMODE1 + [23:23] + Parity bit enabled when set + + + UART_CTRL_PRSC + [26:24] + Clock prescaler select + + + UART_CTRL_CTS + [27:27] + read-only + current state of CTS input + + + UART_CTRL_EN + [28:28] + UART enable flag + + + UART_CTRL_RX_IRQ + [29:29] + RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty + + + UART_CTRL_TX_IRQ + [30:30] + TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full + + + UART_CTRL_TX_BUSY + [31:31] + read-only + Transmitter is busy when set + + + + + DATA + RX/TX data register + 0x04 + + + UART_DATA + [7:0] + Receive/transmit data + + + UART_DATA_PERR + [28:28] + read-only + RX parity error detected when set + + + UART_DATA_FERR + [29:29] + read-only + RX frame error (no valid stop bit) detected when set + + + UART_DATA_OVERR + [30:30] + read-only + RX parity error detected when set + + + UART_DATA_AVAIL + [31:31] + read-only + RX data available when set + + + + + + + + + UART1 + Secondary universal asynchronous receiver and transmitter + UART1 + 0xFFFFFFD0 + + UART1_RX_FIRQ4 + UART1_TX_FIRQ5 + + + 0 + 0x08 + registers + + + + + + + SPI + Serial peripheral interface controller + SPI + 0xFFFFFFA8 + + SPI_FIRQ6 + + + 0 + 0x08 + registers + + + + + CTRL + Control register + 0x00 + + + SPI_CTRL_CS + [7:0] + Direct chip select line + + + SPI_CTRL_EN + [8:8] + SPI enable flag + + + SPI_CTRL_CPHA + [9:9] + Clock phase + + + SPI_CTRL_PRSC + [12:10] + Clock prescaler select + + + SPI_CTRL_SIZE + [14:13] + Data transfer size + + + SPI_CTRL_CPOL + [15:15] + Clock polarity + + + SPI_CTRL_BUSY + [31:31] + read-only + SPI busy flag + + + + + DATA + RX/TX data register + 0x04 + + + + + + + TWI + Two-wire interface controller + SPI + 0xFFFFFFB0 + + TWI_FIRQ7 + + + 0 + 0x08 + registers + + + + + CTRL + Control register + 0x00 + + + TWI_CTRL_EN + [0:0] + TWI enable flag + + + TWI_CTRL_START + [1:1] + Generate START condition, auto-clears + + + TWI_CTRL_STOP + [2:2] + Generate STOP condition, auto-clears + + + TWI_CTRL_PRSC + [5:3] + Clock prescaler select + + + TWI_CTRL_MACK + [6:6] + Generate ACK by controller for each transmission + + + TWI_CTRL_ACK + [30:30] + read-only + ACK received when set + + + TWI_CTRL_BUSY + [31:31] + read-only + Transfer in progress, busy flag + + + + + DATA + RX/TX data register + 0x04 + + + TWI_DATA + [7:0] + RX/TX data + + + + + + + + + TRNG + True random number generator + TRNG + 0xFFFFFFB8 + + + 0 + 0x04 + registers + + + + + CTRL + Control and data register + 0x00 + + + TRNG_CTRL_DATA + [7:0] + read-only + Random data + + + TRNG_CTRL_EN + [30:30] + TRNG enable flag + + + TRNG_CTRL_VALID + [31:31] + read-only + Random data output valid + + + + + + + + + WDT + Watchdog timer + WDT + 0xFFFFFFBC + + WDT_FIRQ0 + + + 0 + 0x04 + registers + + + + + CTRL + Control register + 0x00 + + + WDT_CTRL_EN + [0:0] + WDT enable flag + + + WDT_CTRL_CLK_SEL + [3:1] + Clock prescaler select + + + WDT_CTRL_MODE + [4:4] + Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset + + + WDT_CTRL_RCAUSE + [5:5] + read-only + Cause of last system reset: 0=external reset, 1=watchdog + + + WDT_CTRL_RESET + [6:6] + Reset WDT counter when set, auto-clears + + + WDT_CTRL_FORCE + [7:7] + Force WDT action, auto-clears + + + WDT_CTRL_LOCK + [8:8] + Lock write access to control register, clears on reset (HW or WDT) only + + + WDT_CTRL_DBEN + [9:9] + Allow WDT to continue operation even when in debug mode + + + WDT_CTRL_HALF + [10:10] + read-only + Set if at least half of the max. timeout counter value has been reached + + + + + + + + + GPIO + General purpose input/output port + GPIO + 0xFFFFFFc0 + + + 0 + 0x10 + registers + + + + + INPUT_LO + Parallel input register - low + 0x00 + read-only + + + INPUT_HI + Parallel input register - high + 0x04 + read-only + + + OUTPUT_LO + Parallel output register - low + 0x08 + + + OUTPUT_HI + Parallel output register - high + 0x0C + + + + + + + NEOLED + Smart LED hardware interface + NEOLED + 0xFFFFFFD8 + + NEOLED_FIRQ9 + + + 0 + 0x08 + registers + + + + + CTRL + Control register + 0x00 + + + NEOLED_CTRL_EN + [0:0] + NEOLED enable flag + + + NEOLED_CTRL_MODE + [1:1] + TX mode (0=24-bit, 1=32-bit) + + + NEOLED_CTRL_STROBE + [2:2] + Strobe (0=send normal data, 1=send RESET command on data write) + + + NEOLED_CTRL_PRSC + [5:3] + Clock prescaler select + + + NEOLED_CTRL_BUFS + [9:6] + read-only + log2(tx buffer size) + + + NEOLED_CTRL_T_TOT + [14:10] + pulse-clock ticks per total period bit + + + NEOLED_CTRL_T_ZERO_H + [19:15] + pulse-clock ticks per ZERO high-time + + + NEOLED_CTRL_T_ONE_H + [24:20] + pulse-clock ticks per ONE high-time + + + NEOLED_CTRL_IRQ_CONF + [27:27] + TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty + + + NEOLED_CTRL_TX_EMPTY + [28:28] + read-only + TX FIFO is empty + + + NEOLED_CTRL_TX_HALF + [29:29] + read-only + TX FIFO is at least half-full + + + NEOLED_CTRL_TX_FULL + [30:30] + read-only + TX FIFO is full + + + NEOLED_CTRL_TX_BUSY + [31:31] + read-only + busy flag + + + + + DATA + Data register + 0x04 + + + + + + + SYSINFO + System configuration information memory + SYSINFO + 0xFFFFFFE0 + + + 0 + 0x20 + registers + + + + + CLK + Clock speed in Hz + 0x00 + read-only + + + CPU + CPU core features + 0x04 + read-only + + SYSINFO_CPU_ZICSR[0:0]Zicsr extension (I sub-extension) available when set + SYSINFO_CPU_ZIFENCEI[1:1]Zifencei extension (I sub-extension) available when set + SYSINFO_CPU_ZMMUL[2:2]Zmmul extension (M sub-extension) available when set + SYSINFO_CPU_ZFINX[5:5]Zfinx extension (F sub-/alternative-extension) available when set + SYSINFO_CPU_ZXSCNT[6:6]Custom extension - Small CPU counters + SYSINFO_CPU_ZICNTR[7:7]Basic CPU counters available when set + SYSINFO_CPU_PMP[8:8]PMP (physical memory protection) extension available when set + SYSINFO_CPU_ZIHPM[9:9]HPM (hardware performance monitors) extension available when set + SYSINFO_CPU_DEBUGMODE[10:10]RISC-V CPU debug mode available when set + SYSINFO_CPU_FASTMUL[30:30]fast multiplications (via FAST_MUL_EN generic) available when set + SYSINFO_CPU_FASTSHIFT[31:31]fast shifts (via FAST_SHIFT_EN generic) available when set + + + + SOC + SoC features + 0x08 + read-only + + SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented + SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented + SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented + SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented + SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order + SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented + SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated + SYSINFO_SOC_OCD[14:14]On-chip debugger implemented + SYSINFO_SOC_HW_RESET[15:15]Dedicated hardware reset of core registers implemented + SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented + SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented + SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented + SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented + SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented + SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented + SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented + SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented + SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented + SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented + SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented + SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented + SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented + SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented + + + + CACHE + Cache configuration + 0x0C + read-only + + SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes) + SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines) + SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity) + SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0) + + + + ISPACE_BASE + Instruction memory address space base address + 0x10 + read-only + + + DSPACE_BASE + Data memory address space base address + 0x14 + read-only + + + IMEM_SIZE + Internal instruction memory (IMEM) size in bytes + 0x18 + read-only + + + DMEM_SIZE + Internal data memory (DMEM) size in bytes + 0x1C + read-only + + + + + + diff --git a/Libs/RiscV/NEORV32_test/hdl/.gitkeep b/Libs/RiscV/NEORV32_test/hdl/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/Libs/RiscV/NEORV32_test/hds/.gitkeep b/Libs/RiscV/NEORV32_test/hds/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/Libs/RiscV_test/NEORV32_test/README.md b/Libs/RiscV_test/NEORV32_test/README.md new file mode 100644 index 0000000..8dddbc3 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/README.md @@ -0,0 +1,58 @@ +# Simulation Source Folder + + +## [simple](simple) + +Simple testbench for the NEORV32 Processor and script for simulation using GHDL. + +- [`ghdl.setup.sh`](simple/ghdl.setup.sh) +- [`ghdl.run.sh`](simple/ghdl.run.sh) +- [`ghdl.sh`](simple/ghdl.sh) +- [`neorv32_tb.simple.vhd`](simple/neorv32_tb.simple.vhd) +- [`neorv32_imem.simple.vhd`](simple/neorv32_imem.simple.vhd): memory component optimized for simulation. +- [`neorv32_imem.iram.simple.vhd`](simple/neorv32_imem.iram.simple.vhd) +- [`uart_rx.simple.vhd`](simple/uart_rx.simple.vhd) + + +## VUnit testbench + +VUnit testbench for the NEORV32 Processor. + +- [`run.py`](run.py) +- [`neorv32_tb.vhd`](neorv32_tb.vhd) +- [`uart_rx_pkg.vhd`](uart_rx_pkg.vhd) +- [`uart_rx.vhd`](uart_rx.vhd) + + +## [`run_riscv_arch_test.sh`](run_riscv_arch_test.sh): NEORV32 RISC-V Architecture Test Framework + +This script tests the NEORV32 Processor for RISC-V compatibility using the +[official RISC-V architecture test suite v2+](https://github.com/riscv/riscv-arch-test). +The core's HDL sources are *simulated* using `GHDL` to provide a virtual execution platform for the test framework: + +* `rv32i_m/C` - compressed instructions +* `rv32i_m/I` - base ISA +* `rv32i_m/M` - hardware integer multiplication and division +* `rv32i_m/privilege` - privileged architecture +* `rv32i_m/Zifencei` - instruction stream synchronization (for example for self-modifying code) + +:warning: The RISC-V GCC toolchain (`riscv{32|64}-unknown-elf`) is required for program compilation, and the simulation + depends on `simple/ghdl_sim.sh`. + +To execute all the supported tests open a terminal and run [`./sim/run_riscv_arch_test.sh`](run_riscv_arch_test.sh), +which does the following: + +* Make a local copy of the NEORV32 `rtl` folder in `work/`, to keep the project's core files clean. +* Clone (as `git submodule`) the [riscv-arch-test repository](https://github.com/riscv/riscv-arch-test) into `sw/isa-test/riscv-arch-test`. +* Install (copy) the custom `neorv32` test target from `sw/isa-test/port-neorv32` to the +test suite's target folder `work/riscv-arch-test/riscv-target/neorv32`. +* Run the actual tests. + +:warning: Simulating all the test cases takes quite some time. Some tests use an optimised description of IMEM + (`neorv32_imem.simple.vhd`), but others require the original because they execute self-modifying code. + +:warning: If the simulation of a test does not generate any signature output at all or if the signature is truncated, +try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in `run_riscv_arch_test.sh`. + +More datails regarding the actual simulation process can be found in the +[target's `README`](../sw/riscv-arch-test/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md). diff --git a/Libs/RiscV_test/NEORV32_test/neorv32_tb.vhd b/Libs/RiscV_test/NEORV32_test/neorv32_tb.vhd new file mode 100644 index 0000000..df9cba3 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/neorv32_tb.vhd @@ -0,0 +1,685 @@ +-- ################################################################################################# +-- # << NEORV32 - Default Processor Testbench >> # +-- # ********************************************************************************************* # +-- # The processor is configured to use a maximum of functional units (for testing purpose). # +-- # Use the "User Configuration" section to configure the testbench according to your needs. # +-- # See NEORV32 data sheet for more information. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library vunit_lib; +context vunit_lib.vunit_context; +context vunit_lib.com_context; +context vunit_lib.vc_context; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library neorv32; +use neorv32.neorv32_package.all; +use neorv32.neorv32_application_image.all; -- this file is generated by the image generator +use std.textio.all; + +library osvvm; +use osvvm.RandomPkg.all; + +use work.uart_rx_pkg.all; + +entity neorv32_tb is + generic (runner_cfg : string := runner_cfg_default; + ci_mode : boolean := false); +end neorv32_tb; + +architecture neorv32_tb_rtl of neorv32_tb is + + -- User Configuration --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- general -- + constant ext_imem_c : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A) + constant ext_dmem_c : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B) + constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A + constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B + constant f_clock_c : natural := 100000000; -- main clock in Hz + constant baud0_rate_c : natural := 19200; -- simulation UART0 (primary UART) baud rate + constant baud1_rate_c : natural := 19200; -- simulation UART1 (secondary UART) baud rate + -- simulated external Wishbone memory A (can be used as external IMEM) -- + constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base) + constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes + constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay + -- simulated external Wishbone memory B (can be used as external DMEM) -- + constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base) + constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes + constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay + -- simulated external Wishbone memory C (can be used to simulate external IO access) -- + constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area) + constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes + constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay + -- simulation interrupt trigger -- + constant irq_trigger_base_addr_c : std_ulogic_vector(31 downto 0) := x"FF000000"; + -- ------------------------------------------------------------------------------------------- + + -- internals - hands off! -- + constant int_imem_c : boolean := not ext_imem_c; + constant int_dmem_c : boolean := not ext_dmem_c; + constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c); + constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c); + constant t_clock_c : time := (1 sec) / f_clock_c; + + -- generators -- + signal clk_gen, rst_gen : std_ulogic := '0'; + + -- uart -- + signal uart0_txd : std_ulogic; -- local loop-back + signal uart0_cts : std_ulogic; -- local loop-back + signal uart1_txd : std_ulogic; -- local loop-back + signal uart1_cts : std_ulogic; -- local loop-back + + -- gpio -- + signal gpio : std_ulogic_vector(63 downto 0); + + -- twi -- + signal twi_scl, twi_sda : std_logic; + + -- spi -- + signal spi_data : std_ulogic; + + -- irq -- + signal msi_ring, mei_ring : std_ulogic; + + -- Wishbone bus -- + type wishbone_t is record + addr : std_ulogic_vector(31 downto 0); -- address + wdata : std_ulogic_vector(31 downto 0); -- master write data + rdata : std_ulogic_vector(31 downto 0); -- master read data + we : std_ulogic; -- write enable + sel : std_ulogic_vector(03 downto 0); -- byte enable + stb : std_ulogic; -- strobe + cyc : std_ulogic; -- valid cycle + ack : std_ulogic; -- transfer acknowledge + err : std_ulogic; -- transfer error + tag : std_ulogic_vector(02 downto 0); -- request tag + lock : std_ulogic; -- exclusive access request + end record; + signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t; + + -- Wishbone access latency type -- + type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0); + + -- exclusive access / reservation -- + signal ext_mem_c_atomic_reservation : std_ulogic := '0'; + + -- simulated external memory c (IO) -- + signal ext_ram_c : mem32_t(0 to ext_mem_c_size_c/4-1); -- uninitialized, used to simulate external IO + + -- simulated external memory bus feedback type -- + type ext_mem_t is record + rdata : ext_mem_read_latency_t; + acc_en : std_ulogic; + ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0); + end record; + signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t; + + -- stream link interface - local echo -- + signal slink_dat : sdata_8x32_t; + signal slink_val : std_ulogic_vector(7 downto 0); + signal slink_rdy : std_ulogic_vector(7 downto 0); + + signal slink_transmitter_dat, slink_receiver_dat : sdata_8x32_t; + signal slink_transmitter_val, slink_receiver_val : std_ulogic_vector(7 downto 0); + signal slink_transmitter_rdy, slink_receiver_rdy : std_ulogic_vector(7 downto 0); + + constant uart0_rx_logger : logger_t := get_logger("UART0.RX"); + constant uart1_rx_logger : logger_t := get_logger("UART1.RX"); + constant uart0_rx_handle : uart_rx_t := new_uart_rx(uart0_baud_val_c, uart0_rx_logger); + constant uart1_rx_handle : uart_rx_t := new_uart_rx(uart1_baud_val_c, uart1_rx_logger); + + type axi_stream_master_vec_t is array(integer range <>) of axi_stream_master_t; + type axi_stream_slave_vec_t is array(integer range <>) of axi_stream_slave_t; + + impure function init_slink_transmitters return axi_stream_master_vec_t is + variable result : axi_stream_master_vec_t(slink_transmitter_val'range); + begin + for idx in result'range loop + result(idx) := new_axi_stream_master( + data_length => slink_transmitter_dat(idx)'length, + stall_config => new_stall_config(0.05, 1, 10) + ); + end loop; + + return result; + end; + + impure function init_slink_receivers return axi_stream_slave_vec_t is + variable result : axi_stream_slave_vec_t(slink_receiver_val'range); + begin + for idx in result'range loop + result(idx) := new_axi_stream_slave( + data_length => slink_receiver_dat(idx)'length, + stall_config => new_stall_config(0.05, 1, 10) + ); + end loop; + + return result; + end; + + constant slink_transmitters : axi_stream_master_vec_t := init_slink_transmitters; + constant slink_receivers : axi_stream_slave_vec_t := init_slink_receivers; + +begin + test_runner : process + variable msg : msg_t; + variable rnd : RandomPType; + variable value : std_logic_vector(slink_transmitter_dat(0)'range); + begin + test_runner_setup(runner, runner_cfg); + + rnd.InitSeed(test_runner'path_name); + + -- Show passing checks for UART0 on the display (stdout) + show(uart0_rx_logger, display_handler, pass); + show(uart1_rx_logger, display_handler, pass); + + if ci_mode then + check_uart(net, uart0_rx_handle, nul & nul); + else + check_uart(net, uart0_rx_handle, "Blinking LED demo program" & cr & lf); + end if; + + if ci_mode then + -- No need to send the full expectation in one big chunk + check_uart(net, uart1_rx_handle, nul & nul); + check_uart(net, uart1_rx_handle, "0/46" & cr & lf); + end if; + + -- Apply some random data on each SLINK inputs and expect it to + -- be echoed by the CPU. No blocking. Let the SLINK transmitters + -- and receivers do this work in parallel. + for idx in slink_transmitters'range loop + for iter in 1 to 100 loop + value := rnd.RandSlv(value'length); + + -- SLINK is AXI Stream compatible so the SLINK transmitters and + -- and receivers are AXI Stream master and slave verification components (VCs). + -- The full-featured AXI Stream verification component interface (VCI) is used + -- but the AXI stream VCs also implements the basic stream VCI which also works + -- for simple transactions like these. To use that interface for pushing data + -- the AXI Steam VC must be "cast" to a basic stream VC using "as_stream" + -- + -- push_stream(net, as_stream(slink_transmitters(idx)), value); + + push_axi_stream(net, slink_transmitters(idx), value); + check_axi_stream(net, slink_receivers(idx), value, blocking => false); + end loop; + end loop; + + -- Wait until all expected data has been received + -- + -- wait_until_idle can take the VC actor as argument but + -- the more abstract view is that wait_until_idle is part + -- of the sync VCI and to use it a VC must be cast + -- to a sync VC + wait_until_idle(net, as_sync(uart0_rx_handle)); + wait_until_idle(net, as_sync(uart1_rx_handle)); + for idx in slink_receivers'range loop + wait_until_idle(net, as_sync(slink_receivers(idx))); + end loop; + + -- Wait a bit more if some extra unexpected data is produced. If so, + -- uart_rx will fail + wait for (20 * (1e9 / baud0_rate_c)) * ns; + + test_runner_cleanup(runner); + end process; + + -- In case we get stuck waiting there is a watchdog timeout to terminate and fail the + -- testbench + test_runner_watchdog(runner, 50 ms); + + -- Clock/Reset Generator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + clk_gen <= not clk_gen after (t_clock_c/2); + rst_gen <= '0', '1' after 60*(t_clock_c/2); + + + -- The Core of the Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz + HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit) + INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => true, -- implement atomic extension? + CPU_EXTENSION_RISCV_B => true, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension? + CPU_EXTENSION_RISCV_U => true, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => true, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.? + -- Extension Options -- + FAST_MUL_EN => false, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => false, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64) + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => 8, -- number of regions (0..64) + PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => int_dmem_c, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN => true, -- implement instruction cache + ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => 2, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External memory interface -- + MEM_EXT_EN => true, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 256, -- cycles after a pending bus access auto-terminates (0 = disabled) + -- Stream link interface -- + SLINK_NUM_TX => 8, -- number of TX links (0..8) + SLINK_NUM_RX => 8, -- number of TX links (0..8) + SLINK_TX_FIFO => 4, -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO => 1, -- RX fifo depth, has to be a power of two + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH => 32, -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE => (others => '1'), -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO => 32, -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO => 32, -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO => 1, -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO => 1, -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN => true, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => true, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => 30, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => true, -- implement watch dog timer (WDT)? + IO_TRNG_EN => false, -- trng cannot be simulated + IO_CFS_EN => true, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NEOLED_EN => true, -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO => 8, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN => true -- implement general purpose timer (GPTMR)? + ) + port map ( + -- Global control -- + clk_i => clk_gen, -- global clock, rising edge + rstn_i => rst_gen, -- global reset, low-active, async + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => '1', -- low-active TAP reset (optional) + jtag_tck_i => '0', -- serial clock + jtag_tdi_i => '0', -- serial data input + jtag_tdo_o => open, -- serial data output + jtag_tms_i => '0', -- mode select + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => wb_cpu.tag, -- request tag + wb_adr_o => wb_cpu.addr, -- address + wb_dat_i => wb_cpu.rdata, -- read data + wb_dat_o => wb_cpu.wdata, -- write data + wb_we_o => wb_cpu.we, -- read/write + wb_sel_o => wb_cpu.sel, -- byte enable + wb_stb_o => wb_cpu.stb, -- strobe + wb_cyc_o => wb_cpu.cyc, -- valid cycle + wb_lock_o => wb_cpu.lock, -- exclusive access request + wb_ack_i => wb_cpu.ack, -- transfer acknowledge + wb_err_i => wb_cpu.err, -- transfer error + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o => slink_dat, -- output data + slink_tx_val_o => slink_val, -- valid output + slink_tx_rdy_i => slink_rdy, -- ready to send + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i => slink_dat, -- input data + slink_rx_val_i => slink_val, -- valid input + slink_rx_rdy_o => slink_rdy, -- ready to receive + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => gpio, -- parallel output + gpio_i => gpio, -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd, -- UART0 send data + uart0_rxd_i => uart0_txd, -- UART0 receive data + uart0_rts_o => uart0_cts, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => uart0_cts, -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => uart1_txd, -- UART1 send data + uart1_rxd_i => uart1_txd, -- UART1 receive data + uart1_rts_o => uart1_cts, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => uart1_cts, -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => open, -- SPI serial clock + spi_sdo_o => spi_data, -- controller data out, peripheral data in + spi_sdi_i => spi_data, -- controller data in, peripheral data out + spi_csn_o => open, -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda, -- twi serial data line + twi_scl_io => twi_scl, -- twi serial clock line + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => open, -- pwm channels + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom CFS inputs + cfs_out_o => open, -- custom CFS outputs + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i => gpio(31 downto 0), -- IRQ channels + -- CPU Interrupts -- + mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false + msw_irq_i => msi_ring, -- machine software interrupt + mext_irq_i => mei_ring -- machine external interrupt + ); + + -- TWI termination (pull-ups) -- + twi_scl <= 'H'; + twi_sda <= 'H'; + + uart0_checker: entity work.uart_rx + generic map (uart0_rx_handle) + port map ( + clk => clk_gen, + uart_txd => uart0_txd); + + uart1_checker: entity work.uart_rx + generic map (uart1_rx_handle) + port map ( + clk => clk_gen, + uart_txd => uart1_txd); + + slink_transmitters_gen: for idx in slink_transmitters'range generate + slink_transmitter : entity vunit_lib.axi_stream_master + generic map( + master => slink_transmitters(idx) + ) + port map( + aclk => clk_gen, + tvalid => slink_transmitter_val(idx), + tready => slink_transmitter_rdy(idx), + std_ulogic_vector(tdata) => slink_transmitter_dat(idx) + ); + end generate; + + slink_receivers_gen: for idx in slink_receivers'range generate + begin + slink_receiver : entity vunit_lib.axi_stream_slave + generic map( + slave => slink_receivers(idx) + ) + port map( + aclk => clk_gen, + tvalid => slink_receiver_val(idx), + tready => slink_receiver_rdy(idx), + tdata => std_logic_vector(slink_receiver_dat(idx)) + ); + end generate; + + -- TODO: connect these to the CPU SLINK interface once the + -- loopback SW has been implemented + temporary_connection : for idx in slink_transmitters'range generate + slink_receiver_val(idx) <= slink_transmitter_val(idx); + slink_transmitter_rdy(idx) <= slink_receiver_rdy(idx); + slink_receiver_dat(idx) <= slink_transmitter_dat(idx); + end generate; + + + -- Wishbone Fabric ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + -- CPU broadcast signals -- + wb_mem_a.addr <= wb_cpu.addr; + wb_mem_a.wdata <= wb_cpu.wdata; + wb_mem_a.we <= wb_cpu.we; + wb_mem_a.sel <= wb_cpu.sel; + wb_mem_a.tag <= wb_cpu.tag; + wb_mem_a.cyc <= wb_cpu.cyc; + wb_mem_a.lock <= wb_cpu.lock; + + wb_mem_b.addr <= wb_cpu.addr; + wb_mem_b.wdata <= wb_cpu.wdata; + wb_mem_b.we <= wb_cpu.we; + wb_mem_b.sel <= wb_cpu.sel; + wb_mem_b.tag <= wb_cpu.tag; + wb_mem_b.cyc <= wb_cpu.cyc; + wb_mem_b.lock <= wb_cpu.lock; + + wb_mem_c.addr <= wb_cpu.addr; + wb_mem_c.wdata <= wb_cpu.wdata; + wb_mem_c.we <= wb_cpu.we; + wb_mem_c.sel <= wb_cpu.sel; + wb_mem_c.tag <= wb_cpu.tag; + wb_mem_c.cyc <= wb_cpu.cyc; + wb_mem_c.lock <= wb_cpu.lock; + + wb_irq.addr <= wb_cpu.addr; + wb_irq.wdata <= wb_cpu.wdata; + wb_irq.we <= wb_cpu.we; + wb_irq.sel <= wb_cpu.sel; + wb_irq.tag <= wb_cpu.tag; + wb_irq.cyc <= wb_cpu.cyc; + + -- CPU read-back signals (no mux here since peripherals have "output gates") -- + wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata; + wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack; + wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err; + + -- peripheral select via STROBE signal -- + wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0'; + wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0'; + wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0'; + wb_irq.stb <= wb_cpu.stb when (wb_cpu.addr = irq_trigger_base_addr_c) else '0'; + + + -- Wishbone Memory A (simulated external IMEM) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + generate_ext_imem: + if ext_imem_c generate + ext_mem_a_access: process(clk_gen) + variable ext_ram_a : mem32_t(0 to ext_mem_a_size_c/4-1) := mem32_init_f(application_init_image, ext_mem_a_size_c/4); -- initialized, used to simulate external IMEM + begin + if rising_edge(clk_gen) then + -- control -- + ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge + + -- write access -- + if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access + for i in 0 to 3 loop + if (wb_mem_a.sel(i) = '1') then + ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_a.wdata(7+i*8 downto 0+i*8); + end if; + end loop; -- i + end if; + + -- read access -- + ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned + -- virtual read and ack latency -- + if (ext_mem_a_latency_c > 1) then + for i in 1 to ext_mem_a_latency_c-1 loop + ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1); + ext_mem_a.ack(i) <= ext_mem_a.ack(i-1) and wb_mem_a.cyc; + end loop; + end if; + + -- bus output register -- + wb_mem_a.err <= '0'; + if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_a.cyc = '1') and (wb_mem_a.ack = '0') then + wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1); + wb_mem_a.ack <= '1'; + else + wb_mem_a.rdata <= (others => '0'); + wb_mem_a.ack <= '0'; + end if; + end if; + end process ext_mem_a_access; + end generate; + + generate_ext_imem_false: + if (ext_imem_c = false) generate + wb_mem_a.rdata <= (others => '0'); + wb_mem_a.ack <= '0'; + wb_mem_a.err <= '0'; + end generate; + + + -- Wishbone Memory B (simulated external DMEM) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ext_mem_b_access: process(clk_gen) + variable ext_ram_b : mem32_t(0 to ext_mem_b_size_c/4-1) := (others => (others => '0')); -- zero, used to simulate external DMEM + begin + if rising_edge(clk_gen) then + -- control -- + ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge + + -- write access -- + if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access + for i in 0 to 3 loop + if (wb_mem_b.sel(i) = '1') then + ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_b.wdata(7+i*8 downto 0+i*8); + end if; + end loop; -- i + end if; + + -- read access -- + ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned + -- virtual read and ack latency -- + if (ext_mem_b_latency_c > 1) then + for i in 1 to ext_mem_b_latency_c-1 loop + ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1); + ext_mem_b.ack(i) <= ext_mem_b.ack(i-1) and wb_mem_b.cyc; + end loop; + end if; + + -- bus output register -- + wb_mem_b.err <= '0'; + if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then + wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1); + wb_mem_b.ack <= '1'; + else + wb_mem_b.rdata <= (others => '0'); + wb_mem_b.ack <= '0'; + end if; + end if; + end process ext_mem_b_access; + + + -- Wishbone Memory C (simulated external IO) ---------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ext_mem_c_access: process(clk_gen) + begin + if rising_edge(clk_gen) then + -- control -- + ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge + + -- write access -- + if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access + for i in 0 to 3 loop + if (wb_mem_c.sel(i) = '1') then + ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8); + end if; + end loop; -- i + end if; + + -- read access -- + ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned + -- virtual read and ack latency -- + if (ext_mem_c_latency_c > 1) then + for i in 1 to ext_mem_c_latency_c-1 loop + ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1); + ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc; + end loop; + end if; + + -- EXCLUSIVE bus access ----------------------------------------------------- + -- ----------------------------------------------------------------------------- + -- Since there is only one CPU in this design, the exclusive access reservation in THIS memory CANNOT fail. + -- However, this memory module is used to simulated failing LR/SC accesses. + if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') then -- valid access + ext_mem_c_atomic_reservation <= wb_mem_c.lock; -- make reservation + end if; + -- ----------------------------------------------------------------------------- + + -- bus output register -- + if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then + wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1); + wb_mem_c.ack <= '1'; + wb_mem_c.err <= ext_mem_c_atomic_reservation; -- issue a bus error if there is an exclusive access request + else + wb_mem_c.rdata <= (others => '0'); + wb_mem_c.ack <= '0'; + wb_mem_c.err <= '0'; + end if; + end if; + end process ext_mem_c_access; + + + -- Wishbone IRQ Triggers ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + irq_trigger: process(rst_gen, clk_gen) + begin + if (rst_gen = '0') then + msi_ring <= '0'; + mei_ring <= '0'; + elsif rising_edge(clk_gen) then + -- bus interface -- + wb_irq.rdata <= (others => '0'); + wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel); + wb_irq.err <= '0'; + -- trigger RISC-V platform IRQs -- + if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel)) = '1') then + msi_ring <= wb_irq.wdata(03); -- machine software interrupt + mei_ring <= wb_irq.wdata(11); -- machine software interrupt + end if; + end if; + end process irq_trigger; + + +end neorv32_tb_rtl; diff --git a/Libs/RiscV_test/NEORV32_test/run.py b/Libs/RiscV_test/NEORV32_test/run.py new file mode 100644 index 0000000..426b7d8 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/run.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 + +from pathlib import Path +from vunit import VUnit, VUnitCLI + +cli = VUnitCLI() +cli.parser.add_argument( + "--ci-mode", + action="store_true", + default=False, + help="Enable special settings used by the CI", +) +args = cli.parse_args() + +PRJ = VUnit.from_args(args=args) +PRJ.add_com() +PRJ.add_verification_components() +PRJ.add_osvvm() + +ROOT = Path(__file__).parent + +NEORV32 = PRJ.add_library("neorv32") +NEORV32.add_source_files([ + ROOT / "*.vhd", + ROOT / ".." / "rtl" / "**" / "*.vhd", + # In VUnit <=v4.5.0, the glob search is not recursive, + # hence subdir 'mem' is not picked by the previous pattern + ROOT / ".." / "rtl" / "core" / "mem" / "*.vhd" +]) + +NEORV32.test_bench("neorv32_tb").set_generic("ci_mode", args.ci_mode) + +PRJ.set_sim_option("disable_ieee_warnings", True) +PRJ.set_sim_option("ghdl.sim_flags", ["--max-stack-alloc=256"]) + +PRJ.main() diff --git a/Libs/RiscV_test/NEORV32_test/run_riscv_arch_test.sh b/Libs/RiscV_test/NEORV32_test/run_riscv_arch_test.sh new file mode 100644 index 0000000..fe0c1c5 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/run_riscv_arch_test.sh @@ -0,0 +1,63 @@ +#!/usr/bin/env bash + +# Abort if any command returns != 0 +set -e + +cd $(dirname "$0") + +header() { + echo "--------------------------------------------------------------------------" + echo "> $@..." + echo "--------------------------------------------------------------------------" +} + +RISCV_PREFIX="${RISCV_PREFIX:-riscv32-unknown-elf-}" + +header "Checking RISC-V GCC toolchain" +"$RISCV_PREFIX"gcc -v + +header "Checking 'riscv-arch-test' GitHub repository (submodule)" +git submodule update --init + +header "Copying neorv32 test-target into riscv-arch-test framework" +( + cd ../sw/isa-test + target_device='riscv-arch-test/riscv-target/neorv32' + if [ -d "$target_device" ]; then rm -rf "$target_device"; fi + cp -vr port-neorv32 "$target_device" +) + +header "Making local copy of NEORV32 'rtl' and 'sim' folders" + +export NEORV32_LOCAL_RTL=${NEORV32_LOCAL_RTL:-$(pwd)/work} + +rm -rf "$NEORV32_LOCAL_RTL" +cp -r ../rtl "$NEORV32_LOCAL_RTL" + +header "Starting RISC-V architecture tests" + +./simple/ghdl.setup.sh + +# work in progress FIXME +printf "\n\e[1;33mWARNING! 'rv32e/*' tests are work in progress! \e[0m\n\n" + +makeArgs="-C $(pwd)/../sw/isa-test/riscv-arch-test NEORV32_ROOT=$(pwd)/.. XLEN=32 RISCV_TARGET=neorv32" +makeTargets='clean build run verify' + +[ -n "$1" ] && SUITES="$@" || SUITES='I C M privilege Zifencei' + +for suite in $SUITES; do + case "$suite" in + I) make --silent $makeArgs SIM_TIME=850us RISCV_DEVICE=I $makeTargets;; + C) make --silent $makeArgs SIM_TIME=400us RISCV_DEVICE=C $makeTargets;; + M) make --silent $makeArgs SIM_TIME=800us RISCV_DEVICE=M $makeTargets;; + privilege) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=privilege $makeTargets;; + Zifencei) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT $makeTargets;; + + rv32e_C) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/C $makeTargets;; + rv32e_E) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/E $makeTargets;; + rv32e_M) make --silent $makeArgs SIM_TIME=200us RISCV_DEVICE=../rv32e_unratified/M $makeTargets;; + esac +done + +printf "\nRISC-V architecture tests completed successfully" diff --git a/Libs/RiscV_test/NEORV32_test/simple/ghdl.run.sh b/Libs/RiscV_test/NEORV32_test/simple/ghdl.run.sh new file mode 100644 index 0000000..72d6661 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/simple/ghdl.run.sh @@ -0,0 +1,40 @@ +#!/usr/bin/env bash + +set -e + +cd $(dirname "$0") + +echo "Tip: Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to auto-enable UART[0/1]'s simulation mode (redirect UART output to simulator console)." + +# Prepare simulation output files for UART0 and UART 1 +# - Testbench receiver log file (neorv32.testbench_uart?.out) +# - Direct simulation output (neorv32.uart?.sim_mode.[text|data].out) +for uart in 0 1; do + for item in \ + testbench_uart"$uart" \ + uart"$uart".sim_mode.text \ + uart"$uart".sim_mode.data; do + touch neorv32."$item".out + chmod 777 neorv32."$item".out + done +done + +GHDL="${GHDL:-ghdl}" + +$GHDL -m --work=neorv32 --workdir=build neorv32_tb_simple + +GHDL_RUN_ARGS="${@:---stop-time=10ms}" +echo "Using simulation runtime args: $GHDL_RUN_ARGS"; + +runcmd="$GHDL -r --work=neorv32 --workdir=build neorv32_tb_simple \ + --max-stack-alloc=0 \ + --ieee-asserts=disable \ + --assert-level=error $GHDL_RUN_ARGS" + +if [ -n "$GHDL_DEVNULL" ]; then + $runcmd >> /dev/null +else + $runcmd +fi + +cat neorv32.uart0.sim_mode.text.out | grep "CPU TEST COMPLETED SUCCESSFULLY!" diff --git a/Libs/RiscV_test/NEORV32_test/simple/ghdl.setup.sh b/Libs/RiscV_test/NEORV32_test/simple/ghdl.setup.sh new file mode 100644 index 0000000..c0f040e --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/simple/ghdl.setup.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash + +set -e + +cd $(dirname "$0") + +NEORV32_LOCAL_RTL=${NEORV32_LOCAL_RTL:-../../rtl} + +mkdir -p build + +ghdl -i --work=neorv32 --workdir=build \ + "$NEORV32_LOCAL_RTL"/core/*.vhd \ + "$NEORV32_LOCAL_RTL"/core/mem/*.vhd \ + "$NEORV32_LOCAL_RTL"/processor_templates/*.vhd \ + "$NEORV32_LOCAL_RTL"/system_integration/*.vhd \ + "$NEORV32_LOCAL_RTL"/test_setups/*.vhd \ + neorv32_tb.simple.vhd \ + uart_rx.simple.vhd diff --git a/Libs/RiscV_test/NEORV32_test/simple/ghdl.sh b/Libs/RiscV_test/NEORV32_test/simple/ghdl.sh new file mode 100644 index 0000000..eae1928 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/simple/ghdl.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash + +# `GHDL` is used to check all VHDL files for syntax errors and to simulate the default testbench. The previously +# installed CPU test program is executed and the console output (UART0 primary UART) is dumped to a text file. After the +# simulation has finished, the text file is searched for a specific string. If the string is found, the CPU test was +# successful. + +# Abort if any command returns != 0 +set -e + +cd $(dirname "$0") + +./ghdl.setup.sh +./ghdl.run.sh diff --git a/Libs/RiscV_test/NEORV32_test/simple/neorv32_imem.iram.simple.vhd b/Libs/RiscV_test/NEORV32_test/simple/neorv32_imem.iram.simple.vhd new file mode 100644 index 0000000..cebfd90 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/simple/neorv32_imem.iram.simple.vhd @@ -0,0 +1,136 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> # +-- # ********************************************************************************************* # +-- # This version is intended for SIMULATION ONLY! # +-- # It implements the IMEM as pre-initialized RAM. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; +use neorv32.neorv32_application_image.all; -- this file is generated by the image generator + +architecture neorv32_imem_rtl of neorv32_imem is + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0); + + -- ---------------------------------------------------- -- + -- << SIMULATION ONLY!!! >> IMEM as pre-initialized RAM -- + -- ---------------------------------------------------- -- + + -- application (image) size in bytes -- + constant imem_app_size_c : natural := (application_init_image'length)*4; + + -- RAM - initialized with executable code -- + signal mem_ram : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4); + + -- read data -- + signal mem_ram_rd : std_ulogic_vector(31 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal [SIM-only!] IMEM as RAM (" & natural'image(IMEM_SIZE) & + " bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note; + -- + assert not (imem_app_size_c > IMEM_SIZE) report "NEORV32 PROCESSOR CONFIG ERROR: Application (image = " & natural'image(imem_app_size_c) & + " bytes) does not fit into processor-internal IMEM (" & natural'image(IMEM_SIZE) & " bytes)!" severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned + + + -- Implement IMEM as pre-initialized RAM -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + mem_access: process(clk_i) + begin + if rising_edge(clk_i) then + if (acc_en = '1') then + if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0 + mem_ram(to_integer(unsigned(addr)))(07 downto 00) <= data_i(07 downto 00); + else + mem_ram_rd(07 downto 00) <= mem_ram(to_integer(unsigned(addr)))(07 downto 00); + end if; + if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1 + mem_ram(to_integer(unsigned(addr)))(15 downto 08) <= data_i(15 downto 08); + else + mem_ram_rd(15 downto 08) <= mem_ram(to_integer(unsigned(addr)))(15 downto 08); + end if; + if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2 + mem_ram(to_integer(unsigned(addr)))(23 downto 16) <= data_i(23 downto 16); + else + mem_ram_rd(23 downto 16) <= mem_ram(to_integer(unsigned(addr)))(23 downto 16); + end if; + if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3 + mem_ram(to_integer(unsigned(addr)))(31 downto 24) <= data_i(31 downto 24); + else + mem_ram_rd(31 downto 24) <= mem_ram(to_integer(unsigned(addr)))(31 downto 24); + end if; + end if; + end if; + end process mem_access; + + -- read data -- + rdata <= mem_ram_rd; + + + -- Bus Feedback --------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + bus_feedback: process(clk_i) + begin + if rising_edge(clk_i) then + rden <= acc_en and rden_i; + ack_o <= acc_en and (rden_i or wren_i); + end if; + end process bus_feedback; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_imem_rtl; diff --git a/Libs/RiscV_test/NEORV32_test/simple/neorv32_imem.simple.vhd b/Libs/RiscV_test/NEORV32_test/simple/neorv32_imem.simple.vhd new file mode 100644 index 0000000..cde2729 --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/simple/neorv32_imem.simple.vhd @@ -0,0 +1,95 @@ +-- ################################################################################################# +-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> # +-- # ********************************************************************************************* # +-- # This version is intended for SIMULATION ONLY! # +-- # It only allows an implementation as ROM and is initialized using "application_init_image". # +-- # Optimized for simulation to allow LARGE read-only IMEMs. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; +use neorv32.neorv32_application_image.all; -- this file is generated by the image generator + +architecture neorv32_imem_rtl of neorv32_imem is + + -- IO space: module base address -- + constant hi_abb_c : natural := 31; -- high address boundary bit + constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit + + -- local signals -- + signal acc_en : std_ulogic; + signal rdata : std_ulogic_vector(31 downto 0); + signal rden : std_ulogic; + signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0); + +begin + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not (IMEM_AS_IROM = false) report "NEORV32 PROCESSOR CONFIG ERROR! Simulation-optimized IMEM can only be used as pre-initialized ROM!" severity error; + + + -- Access Control ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0'; + addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned + + + -- Memory Access -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + imem_file_access: process(clk_i) + variable addr_v : integer; + begin + if rising_edge(clk_i) then + rden <= acc_en and rden_i; + ack_o <= acc_en and (rden_i or wren_i); + if (acc_en = '1') then -- reduce switching activity when not accessed + addr_v := to_integer(unsigned(addr)); + if (addr_v > application_init_image'length) then + rdata <= (others => '0'); + else + rdata <= application_init_image(addr_v); + end if; + end if; + end if; + end process imem_file_access; + + -- output gate -- + data_o <= rdata when (rden = '1') else (others => '0'); + + +end neorv32_imem_rtl; diff --git a/Libs/RiscV_test/NEORV32_test/simple/neorv32_tb.simple.vhd b/Libs/RiscV_test/NEORV32_test/simple/neorv32_tb.simple.vhd new file mode 100644 index 0000000..380b8cb --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/simple/neorv32_tb.simple.vhd @@ -0,0 +1,554 @@ +-- ################################################################################################# +-- # << NEORV32 - Default Processor Testbench >> # +-- # ********************************************************************************************* # +-- # The processor is configured to use a maximum of functional units (for testing purpose). # +-- # Use the "User Configuration" section to configure the testbench according to your needs. # +-- # See NEORV32 data sheet for more information. # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library neorv32; +use neorv32.neorv32_package.all; +use neorv32.neorv32_application_image.all; -- this file is generated by the image generator +use std.textio.all; + +entity neorv32_tb_simple is + generic ( + CPU_EXTENSION_RISCV_A : boolean := true; + CPU_EXTENSION_RISCV_B : boolean := true; + CPU_EXTENSION_RISCV_C : boolean := true; + CPU_EXTENSION_RISCV_E : boolean := false; + CPU_EXTENSION_RISCV_M : boolean := true; + CPU_EXTENSION_RISCV_U : boolean := true; + CPU_EXTENSION_RISCV_Zicsr : boolean := true; + CPU_EXTENSION_RISCV_Zifencei : boolean := true; + EXT_IMEM_C : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A) + MEM_INT_IMEM_SIZE : natural := 16*1024 -- size in bytes of processor-internal IMEM / external mem A + ); +end neorv32_tb_simple; + +architecture neorv32_tb_simple_rtl of neorv32_tb_simple is + + -- User Configuration --------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- general -- + constant ext_dmem_c : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B) + constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B + constant f_clock_c : natural := 100000000; -- main clock in Hz + constant baud0_rate_c : natural := 19200; -- simulation UART0 (primary UART) baud rate + constant baud1_rate_c : natural := 19200; -- simulation UART1 (secondary UART) baud rate + -- simulated external Wishbone memory A (can be used as external IMEM) -- + constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base) + constant ext_mem_a_size_c : natural := MEM_INT_IMEM_SIZE; -- wishbone memory size in bytes + constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay + -- simulated external Wishbone memory B (can be used as external DMEM) -- + constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base) + constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes + constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay + -- simulated external Wishbone memory C (can be used to simulate external IO access) -- + constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area) + constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes + constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay + -- simulation interrupt trigger -- + constant irq_trigger_base_addr_c : std_ulogic_vector(31 downto 0) := x"FF000000"; + -- ------------------------------------------------------------------------------------------- + + -- internals - hands off! -- + constant int_imem_c : boolean := not EXT_IMEM_C; + constant int_dmem_c : boolean := not ext_dmem_c; + constant uart0_baud_val_c : real := real(f_clock_c) / real(baud0_rate_c); + constant uart1_baud_val_c : real := real(f_clock_c) / real(baud1_rate_c); + constant t_clock_c : time := (1 sec) / f_clock_c; + + -- generators -- + signal clk_gen, rst_gen : std_ulogic := '0'; + + -- text.io -- + file file_uart0_tx_out : text open write_mode is "neorv32.testbench_uart0.out"; + + -- uart -- + signal uart0_txd : std_ulogic; -- local loop-back + signal uart0_cts : std_ulogic; -- local loop-back + signal uart1_txd : std_ulogic; -- local loop-back + signal uart1_cts : std_ulogic; -- local loop-back + + -- gpio -- + signal gpio : std_ulogic_vector(63 downto 0); + + -- twi -- + signal twi_scl, twi_sda : std_logic; + + -- spi -- + signal spi_data : std_ulogic; + + -- irq -- + signal msi_ring, mei_ring : std_ulogic; + + -- Wishbone bus -- + type wishbone_t is record + addr : std_ulogic_vector(31 downto 0); -- address + wdata : std_ulogic_vector(31 downto 0); -- master write data + rdata : std_ulogic_vector(31 downto 0); -- master read data + we : std_ulogic; -- write enable + sel : std_ulogic_vector(03 downto 0); -- byte enable + stb : std_ulogic; -- strobe + cyc : std_ulogic; -- valid cycle + ack : std_ulogic; -- transfer acknowledge + err : std_ulogic; -- transfer error + tag : std_ulogic_vector(02 downto 0); -- request tag + lock : std_ulogic; -- exclusive access request + end record; + signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t; + + -- Wishbone access latency type -- + type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0); + + -- exclusive access / reservation -- + signal ext_mem_c_atomic_reservation : std_ulogic := '0'; + + -- simulated external memory c (IO) -- + signal ext_ram_c : mem32_t(0 to ext_mem_c_size_c/4-1); -- uninitialized, used to simulate external IO + + -- simulated external memory bus feedback type -- + type ext_mem_t is record + rdata : ext_mem_read_latency_t; + acc_en : std_ulogic; + ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0); + end record; + signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t; + + -- stream link interface - local echo -- + signal slink_dat : sdata_8x32_t; + signal slink_val : std_ulogic_vector(7 downto 0); + signal slink_rdy : std_ulogic_vector(7 downto 0); + +begin + + -- Clock/Reset Generator ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + clk_gen <= not clk_gen after (t_clock_c/2); + rst_gen <= '0', '1' after 60*(t_clock_c/2); + + + -- The Core of the Problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_top_inst: neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz + HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit) + INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => true, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension? + -- Extension Options -- + FAST_MUL_EN => false, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => false, -- use barrel shifter for shift operations + CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64) + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => 8, -- number of regions (0..64) + PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64) + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => int_dmem_c, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN => true, -- implement instruction cache + ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => 2, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + -- External memory interface -- + MEM_EXT_EN => true, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 256, -- cycles after a pending bus access auto-terminates (0 = disabled) + -- Stream link interface -- + SLINK_NUM_TX => 8, -- number of TX links (0..8) + SLINK_NUM_RX => 8, -- number of TX links (0..8) + SLINK_TX_FIFO => 4, -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO => 1, -- RX fifo depth, has to be a power of two + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH => 32, -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE => (others => '1'), -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + -- Processor peripherals -- + IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => true, -- implement machine system timer (MTIME)? + IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO => 32, -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO => 32, -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO => 1, -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO => 1, -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN => true, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => true, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => 30, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => true, -- implement watch dog timer (WDT)? + IO_TRNG_EN => false, -- trng cannot be simulated + IO_CFS_EN => true, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NEOLED_EN => true, -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO => 8, -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN => true -- implement general purpose timer (GPTMR)? + ) + port map ( + -- Global control -- + clk_i => clk_gen, -- global clock, rising edge + rstn_i => rst_gen, -- global reset, low-active, async + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => '1', -- low-active TAP reset (optional) + jtag_tck_i => '0', -- serial clock + jtag_tdi_i => '0', -- serial data input + jtag_tdo_o => open, -- serial data output + jtag_tms_i => '0', -- mode select + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => wb_cpu.tag, -- request tag + wb_adr_o => wb_cpu.addr, -- address + wb_dat_i => wb_cpu.rdata, -- read data + wb_dat_o => wb_cpu.wdata, -- write data + wb_we_o => wb_cpu.we, -- read/write + wb_sel_o => wb_cpu.sel, -- byte enable + wb_stb_o => wb_cpu.stb, -- strobe + wb_cyc_o => wb_cpu.cyc, -- valid cycle + wb_lock_o => wb_cpu.lock, -- exclusive access request + wb_ack_i => wb_cpu.ack, -- transfer acknowledge + wb_err_i => wb_cpu.err, -- transfer error + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o => slink_dat, -- output data + slink_tx_val_o => slink_val, -- valid output + slink_tx_rdy_i => slink_rdy, -- ready to send + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i => slink_dat, -- input data + slink_rx_val_i => slink_val, -- valid input + slink_rx_rdy_o => slink_rdy, -- ready to receive + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => gpio, -- parallel output + gpio_i => gpio, -- parallel input + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart0_txd, -- UART0 send data + uart0_rxd_i => uart0_txd, -- UART0 receive data + uart0_rts_o => uart0_cts, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => uart0_cts, -- hw flow control: UART0.TX allowed to transmit, low-active, optional + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => uart1_txd, -- UART1 send data + uart1_rxd_i => uart1_txd, -- UART1 receive data + uart1_rts_o => uart1_cts, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => uart1_cts, -- hw flow control: UART1.TX allowed to transmit, low-active, optional + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => open, -- SPI serial clock + spi_sdo_o => spi_data, -- controller data out, peripheral data in + spi_sdi_i => spi_data, -- controller data in, peripheral data out + spi_csn_o => open, -- SPI CS + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => twi_sda, -- twi serial data line + twi_scl_io => twi_scl, -- twi serial clock line + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => open, -- pwm channels + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom CFS inputs + cfs_out_o => open, -- custom CFS outputs + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i => gpio(31 downto 0), -- IRQ channels + -- CPU Interrupts -- + mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false + msw_irq_i => msi_ring, -- machine software interrupt + mext_irq_i => mei_ring -- machine external interrupt + ); + + -- TWI termination (pull-ups) -- + twi_scl <= 'H'; + twi_sda <= 'H'; + + + -- UART Simulation Receiver --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + uart0_checker: entity work.uart_rx_simple + generic map ( + name => "uart0", + uart_baud_val_c => uart0_baud_val_c + ) + port map ( + clk => clk_gen, + uart_txd => uart0_txd + ); + + uart1_checker: entity work.uart_rx_simple + generic map ( + name => "uart1", + uart_baud_val_c => uart1_baud_val_c + ) + port map ( + clk => clk_gen, + uart_txd => uart1_txd + ); + + + -- Wishbone Fabric ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + -- CPU broadcast signals -- + wb_mem_a.addr <= wb_cpu.addr; + wb_mem_a.wdata <= wb_cpu.wdata; + wb_mem_a.we <= wb_cpu.we; + wb_mem_a.sel <= wb_cpu.sel; + wb_mem_a.tag <= wb_cpu.tag; + wb_mem_a.cyc <= wb_cpu.cyc; + wb_mem_a.lock <= wb_cpu.lock; + + wb_mem_b.addr <= wb_cpu.addr; + wb_mem_b.wdata <= wb_cpu.wdata; + wb_mem_b.we <= wb_cpu.we; + wb_mem_b.sel <= wb_cpu.sel; + wb_mem_b.tag <= wb_cpu.tag; + wb_mem_b.cyc <= wb_cpu.cyc; + wb_mem_b.lock <= wb_cpu.lock; + + wb_mem_c.addr <= wb_cpu.addr; + wb_mem_c.wdata <= wb_cpu.wdata; + wb_mem_c.we <= wb_cpu.we; + wb_mem_c.sel <= wb_cpu.sel; + wb_mem_c.tag <= wb_cpu.tag; + wb_mem_c.cyc <= wb_cpu.cyc; + wb_mem_c.lock <= wb_cpu.lock; + + wb_irq.addr <= wb_cpu.addr; + wb_irq.wdata <= wb_cpu.wdata; + wb_irq.we <= wb_cpu.we; + wb_irq.sel <= wb_cpu.sel; + wb_irq.tag <= wb_cpu.tag; + wb_irq.cyc <= wb_cpu.cyc; + + -- CPU read-back signals (no mux here since peripherals have "output gates") -- + wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata; + wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack; + wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err; + + -- peripheral select via STROBE signal -- + wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0'; + wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0'; + wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0'; + wb_irq.stb <= wb_cpu.stb when (wb_cpu.addr = irq_trigger_base_addr_c) else '0'; + + + -- Wishbone Memory A (simulated external IMEM) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + generate_ext_imem: + if (EXT_IMEM_C = true) generate + ext_mem_a_access: process(clk_gen) + variable ext_ram_a : mem32_t(0 to ext_mem_a_size_c/4-1) := mem32_init_f(application_init_image, ext_mem_a_size_c/4); -- initialized, used to simulate external IMEM + begin + if rising_edge(clk_gen) then + -- control -- + ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge + + -- write access -- + if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access + for i in 0 to 3 loop + if (wb_mem_a.sel(i) = '1') then + ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_a.wdata(7+i*8 downto 0+i*8); + end if; + end loop; -- i + end if; + + -- read access -- + ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned + -- virtual read and ack latency -- + if (ext_mem_a_latency_c > 1) then + for i in 1 to ext_mem_a_latency_c-1 loop + ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1); + ext_mem_a.ack(i) <= ext_mem_a.ack(i-1) and wb_mem_a.cyc; + end loop; + end if; + + -- bus output register -- + wb_mem_a.err <= '0'; + if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_a.cyc = '1') and (wb_mem_a.ack = '0') then + wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1); + wb_mem_a.ack <= '1'; + else + wb_mem_a.rdata <= (others => '0'); + wb_mem_a.ack <= '0'; + end if; + end if; + end process ext_mem_a_access; + end generate; + + generate_ext_imem_false: + if (EXT_IMEM_C = false) generate + wb_mem_a.rdata <= (others => '0'); + wb_mem_a.ack <= '0'; + wb_mem_a.err <= '0'; + end generate; + + + -- Wishbone Memory B (simulated external DMEM) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ext_mem_b_access: process(clk_gen) + variable ext_ram_b : mem32_t(0 to ext_mem_b_size_c/4-1) := (others => (others => '0')); -- zero, used to simulate external DMEM + begin + if rising_edge(clk_gen) then + -- control -- + ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge + + -- write access -- + if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access + for i in 0 to 3 loop + if (wb_mem_b.sel(i) = '1') then + ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) := wb_mem_b.wdata(7+i*8 downto 0+i*8); + end if; + end loop; -- i + end if; + + -- read access -- + ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned + -- virtual read and ack latency -- + if (ext_mem_b_latency_c > 1) then + for i in 1 to ext_mem_b_latency_c-1 loop + ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1); + ext_mem_b.ack(i) <= ext_mem_b.ack(i-1) and wb_mem_b.cyc; + end loop; + end if; + + -- bus output register -- + wb_mem_b.err <= '0'; + if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then + wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1); + wb_mem_b.ack <= '1'; + else + wb_mem_b.rdata <= (others => '0'); + wb_mem_b.ack <= '0'; + end if; + end if; + end process ext_mem_b_access; + + + -- Wishbone Memory C (simulated external IO) ---------------------------------------------- + -- ------------------------------------------------------------------------------------------- + ext_mem_c_access: process(clk_gen) + begin + if rising_edge(clk_gen) then + -- control -- + ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge + + -- write access -- + if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access + for i in 0 to 3 loop + if (wb_mem_c.sel(i) = '1') then + ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8); + end if; + end loop; -- i + end if; + + -- read access -- + ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned + -- virtual read and ack latency -- + if (ext_mem_c_latency_c > 1) then + for i in 1 to ext_mem_c_latency_c-1 loop + ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1); + ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc; + end loop; + end if; + + -- EXCLUSIVE bus access ----------------------------------------------------- + -- ----------------------------------------------------------------------------- + -- Since there is only one CPU in this design, the exclusive access reservation in THIS memory CANNOT fail. + -- However, this memory module is used to simulated failing LR/SC accesses. + if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') then -- valid access + ext_mem_c_atomic_reservation <= wb_mem_c.lock; -- make reservation + end if; + -- ----------------------------------------------------------------------------- + + -- bus output register -- + if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then + wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1); + wb_mem_c.ack <= '1'; + wb_mem_c.err <= ext_mem_c_atomic_reservation; -- issue a bus error if there is an exclusive access request + else + wb_mem_c.rdata <= (others => '0'); + wb_mem_c.ack <= '0'; + wb_mem_c.err <= '0'; + end if; + end if; + end process ext_mem_c_access; + + + -- Wishbone IRQ Triggers ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + irq_trigger: process(rst_gen, clk_gen) + begin + if (rst_gen = '0') then + msi_ring <= '0'; + mei_ring <= '0'; + elsif rising_edge(clk_gen) then + -- bus interface -- + wb_irq.rdata <= (others => '0'); + wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel); + wb_irq.err <= '0'; + -- trigger RISC-V platform IRQs -- + if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel)) = '1') then + msi_ring <= wb_irq.wdata(03); -- machine software interrupt + mei_ring <= wb_irq.wdata(11); -- machine software interrupt + end if; + end if; + end process irq_trigger; + + +end neorv32_tb_simple_rtl; diff --git a/Libs/RiscV_test/NEORV32_test/simple/uart_rx.simple.vhd b/Libs/RiscV_test/NEORV32_test/simple/uart_rx.simple.vhd new file mode 100644 index 0000000..64d82ce --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/simple/uart_rx.simple.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +use std.textio.all; + +entity uart_rx_simple is + generic ( + name : string; + uart_baud_val_c : real); + + port ( + clk : in std_ulogic; + uart_txd : in std_ulogic + ); +end entity; + +architecture a of uart_rx_simple is + signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1'); + signal uart_rx_busy : std_ulogic := '0'; + signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0'); + signal uart_rx_baud_cnt : real; + signal uart_rx_bitcnt : natural; + + file file_uart_tx_out : text open write_mode is "neorv32.testbench_" & name & ".out"; + +begin + uart_rx_console : process(clk) + variable i : integer; + variable l : line; + begin + -- "UART" -- + if rising_edge(clk) then + -- synchronizer -- + uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd; + -- arbiter -- + if (uart_rx_busy = '0') then -- idle + uart_rx_busy <= '0'; + uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c); + uart_rx_bitcnt <= 9; + if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge) + uart_rx_busy <= '1'; + end if; + else + if (uart_rx_baud_cnt <= 0.0) then + if (uart_rx_bitcnt = 1) then + uart_rx_baud_cnt <= round(0.5 * uart_baud_val_c); + else + uart_rx_baud_cnt <= round(uart_baud_val_c); + end if; + if (uart_rx_bitcnt = 0) then + uart_rx_busy <= '0'; -- done + i := to_integer(unsigned(uart_rx_sreg(8 downto 1))); + + if (i < 32) or (i > 32+95) then -- printable char? + report name & ".tx: (" & integer'image(i) & ")"; -- print code + else + report name & ".tx: " & character'val(i); -- print ASCII + end if; + + if (i = 10) then -- Linux line break + writeline(file_uart_tx_out, l); + elsif (i /= 13) then -- Remove additional carriage return + write(l, character'val(i)); + end if; + else + uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1); + uart_rx_bitcnt <= uart_rx_bitcnt - 1; + end if; + else + uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0; + end if; + end if; + end if; + end process uart_rx_console; +end architecture; diff --git a/Libs/RiscV_test/NEORV32_test/uart_rx.vhd b/Libs/RiscV_test/NEORV32_test/uart_rx.vhd new file mode 100644 index 0000000..4c9149c --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/uart_rx.vhd @@ -0,0 +1,119 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +use std.textio.all; + +library vunit_lib; +context vunit_lib.vunit_context; +context vunit_lib.com_context; +context vunit_lib.vc_context; + +use work.uart_rx_pkg.all; + +entity uart_rx is + generic (handle : uart_rx_t); + port ( + clk : in std_ulogic; + uart_txd : in std_ulogic + ); +end entity; + +architecture a of uart_rx is + signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1'); + signal uart_rx_busy : std_ulogic := '0'; + signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0'); + signal uart_rx_baud_cnt : real; + signal uart_rx_bitcnt : natural; + + file file_uart_tx_out : text open write_mode is "neorv32.testbench_" & get_name(handle.p_logger) & ".out"; + constant checker : checker_t := new_checker(handle.p_logger); + constant character_queue : queue_t := new_queue; + +begin + control : process + variable request_msg, reply_msg : msg_t; + variable msg_type : msg_type_t; + + procedure put_characters_in_queue(s : string) is + begin + for idx in s'range loop + push(character_queue, s(idx)); + end loop; + end procedure put_characters_in_queue; + begin + receive(net, handle.p_actor, request_msg); + msg_type := message_type(request_msg); + + -- Standard handling of standard wait_for_time messages = wait for the given time + -- before proceeeding + handle_wait_for_time(net, msg_type, request_msg); + + if msg_type = check_uart_msg then + put_characters_in_queue(pop(request_msg)); + + -- Custom handling of standard wait_until_idle message + elsif msg_type = wait_until_idle_msg then + while not is_empty(character_queue) loop + wait until rising_edge(clk); + end loop; + reply_msg := new_msg(wait_until_idle_reply_msg); + reply(net, request_msg, reply_msg); + + else + unexpected_msg_type(msg_type); + end if; + end process; + + uart_rx_console : process(clk) + variable i : integer; + variable l : line; + variable expected_character : character; + begin + -- "UART" -- + if rising_edge(clk) then + -- synchronizer -- + uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd; + -- arbiter -- + if (uart_rx_busy = '0') then -- idle + uart_rx_busy <= '0'; + uart_rx_baud_cnt <= round(0.5 * handle.p_baud_val); + uart_rx_bitcnt <= 9; + if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge) + uart_rx_busy <= '1'; + end if; + else + if (uart_rx_baud_cnt <= 0.0) then + if (uart_rx_bitcnt = 1) then + uart_rx_baud_cnt <= round(0.5 * handle.p_baud_val); + else + uart_rx_baud_cnt <= round(handle.p_baud_val); + end if; + if (uart_rx_bitcnt = 0) then + uart_rx_busy <= '0'; -- done + i := to_integer(unsigned(uart_rx_sreg(8 downto 1))); + + if is_empty(character_queue) then + check_failed(checker, "Extra characters received"); + else + expected_character := pop(character_queue); + check_equal(checker, character'val(i), expected_character); + end if; + + if (i = 10) then -- Linux line break + writeline(file_uart_tx_out, l); + elsif (i /= 13) then -- Remove additional carriage return + write(l, character'val(i)); + end if; + else + uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1); + uart_rx_bitcnt <= uart_rx_bitcnt - 1; + end if; + else + uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0; + end if; + end if; + end if; + end process uart_rx_console; +end architecture; diff --git a/Libs/RiscV_test/NEORV32_test/uart_rx_pkg.vhd b/Libs/RiscV_test/NEORV32_test/uart_rx_pkg.vhd new file mode 100644 index 0000000..97cf0ca --- /dev/null +++ b/Libs/RiscV_test/NEORV32_test/uart_rx_pkg.vhd @@ -0,0 +1,60 @@ +library vunit_lib; +context vunit_lib.vunit_context; +context vunit_lib.com_context; +use vunit_lib.sync_pkg.all; + +package uart_rx_pkg is + constant check_uart_msg : msg_type_t := new_msg_type("check_uart"); + + type uart_rx_t is record + p_baud_val : real; + p_logger : logger_t; + p_actor : actor_t; + end record; + + impure function new_uart_rx( + baud_val : real; + logger : logger_t := null_logger; + actor : actor_t := null_actor) return uart_rx_t; + + function as_sync(handle : uart_rx_t) return sync_handle_t; + + procedure check_uart( + signal net : inout network_t; + constant handle : in uart_rx_t; + constant data : in string); +end package uart_rx_pkg; + +package body uart_rx_pkg is + constant uart_rx_logger : logger_t := get_logger("neorv32_lib:uart_rx_pkg"); + + impure function new_uart_rx( + baud_val : real; + logger : logger_t := null_logger; + actor : actor_t := null_actor) return uart_rx_t is + variable result : uart_rx_t; + begin + result.p_baud_val := baud_val; + result.p_logger := logger when logger /= null_logger else uart_rx_logger; + result.p_actor := actor when actor /= null_actor else new_actor; + + return result; + end; + + function as_sync(handle : uart_rx_t) return sync_handle_t is + begin + return handle.p_actor; + end; + + procedure check_uart( + signal net : inout network_t; + constant handle : in uart_rx_t; + constant data : in string) is + variable msg : msg_t; + begin + msg := new_msg(check_uart_msg); + push(msg, data); + send(net, handle.p_actor, msg); + end; + +end package body uart_rx_pkg; diff --git a/README.md b/README.md new file mode 100644 index 0000000..20d0345 --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +# sem-labs +HEVs laboratory files for course SEm