-- VHDL Entity SplineInterpolator.sineGen.symbol
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 13:00:40 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY sineGen IS
    GENERIC( 
        signalBitNb : positive := 16;
        phaseBitNb  : positive := 10
    );
    PORT( 
        clock    : IN     std_ulogic;
        reset    : IN     std_ulogic;
        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
        sawtooth : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
    );

-- Declarations

END sineGen ;