-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface
--
-- Created:
--          by - zas.UNKNOWN (ZELL)
--          at - 17:08:42 02/17/2020
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;
LIBRARY AhbLite;
  USE AhbLite.ahbLite.all;

ENTITY ahbUart_tester IS
    GENERIC( 
        clockFrequency : real
    );
    PORT( 
        TxD      : IN     std_ulogic;
        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
        hReady   : IN     std_uLogic;
        hResp    : IN     std_uLogic;
        RxD      : OUT    std_ulogic;
        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
        hClk     : OUT    std_uLogic;
        hReset_n : OUT    std_uLogic;
        hSel     : OUT    std_uLogic;
        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
        hWrite   : OUT    std_uLogic
    );

-- Declarations

END ahbUart_tester ;