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tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 990,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 991,0
text (MLText
uid 992,0
va (VaSet
font "Verdana,8,0"
)
xt "107000,22600,125100,24600"
st "signalBitNb = signalBitNb    ( positive ) 
shiftBitNb  = 8              ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "shiftBitNb"
type "positive"
value "8"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*39 (Net
uid 1033,0
decl (Decl
n "lowpassIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 14
suid 12,0
)
declText (MLText
uid 1034,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,29600,27000,30600"
st "SIGNAL lowpassIn  : unsigned(signalBitNb-1 DOWNTO 0)
"
)
)
*40 (Net
uid 1035,0
decl (Decl
n "lowpassOut"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 15
suid 13,0
)
declText (MLText
uid 1036,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,30600,27300,31600"
st "SIGNAL lowpassOut : unsigned(signalBitNb-1 DOWNTO 0)
"
)
)
*41 (Net
uid 1290,0
decl (Decl
n "selSinCos"
t "std_ulogic"
o 21
suid 14,0
)
declText (MLText
uid 1291,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,36600,15800,37600"
st "SIGNAL selSinCos  : std_ulogic
"
)
)
*42 (Net
uid 1477,0
decl (Decl
n "outZ"
t "std_ulogic"
o 18
suid 15,0
)
declText (MLText
uid 1478,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,33600,15300,34600"
st "SIGNAL outZ       : std_ulogic
"
)
)
*43 (SaComponent
uid 1599,0
optionalChildren [
*44 (CptPort
uid 1519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,31625,49000,32375"
)
tg (CPTG
uid 1521,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1522,0
va (VaSet
)
xt "50000,31400,53400,32600"
st "clock"
blo "50000,32400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 3
)
)
)
*45 (CptPort
uid 1523,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1524,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,5625,49000,6375"
)
tg (CPTG
uid 1525,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1526,0
va (VaSet
)
xt "50000,5400,52900,6600"
st "addr"
blo "50000,6400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 2
)
)
)
*46 (CptPort
uid 1527,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1528,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,5625,65750,6375"
)
tg (CPTG
uid 1529,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1530,0
va (VaSet
)
xt "61001,5400,64001,6600"
st "outX"
ju 2
blo "64001,6400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outX"
t "std_ulogic"
o 1
)
)
)
*47 (CptPort
uid 1531,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1532,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,33625,49000,34375"
)
tg (CPTG
uid 1533,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1534,0
va (VaSet
)
xt "50000,33400,53300,34600"
st "reset"
blo "50000,34400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
)
)
)
*48 (CptPort
uid 1535,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1536,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,7625,65750,8375"
)
tg (CPTG
uid 1537,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1538,0
va (VaSet
)
xt "61001,7400,64001,8600"
st "outY"
ju 2
blo "64001,8400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outY"
t "std_ulogic"
o 5
)
)
)
*49 (CptPort
uid 1539,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1540,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,7625,49000,8375"
)
tg (CPTG
uid 1541,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1542,0
va (VaSet
)
xt "50000,7400,54000,8600"
st "dataIn"
blo "50000,8400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
)
)
)
*50 (CptPort
uid 1543,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1544,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,13625,49000,14375"
)
tg (CPTG
uid 1545,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1546,0
va (VaSet
)
xt "50000,13400,51700,14600"
st "rd"
blo "50000,14400"
)
)
thePort (LogicalPort
decl (Decl
n "rd"
t "std_ulogic"
o 7
)
)
)
*51 (CptPort
uid 1547,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1548,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,15625,49000,16375"
)
tg (CPTG
uid 1549,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1550,0
va (VaSet
)
xt "50000,15400,52600,16600"
st "wrH"
blo "50000,16400"
)
)
thePort (LogicalPort
decl (Decl
n "wrH"
t "std_ulogic"
o 8
)
)
)
*52 (CptPort
uid 1551,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1552,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,19625,49000,20375"
)
tg (CPTG
uid 1553,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1554,0
va (VaSet
)
xt "50000,19400,51900,20600"
st "cs"
blo "50000,20400"
)
)
thePort (LogicalPort
decl (Decl
n "cs"
t "std_ulogic"
o 9
)
)
)
*53 (CptPort
uid 1555,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1556,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,17625,49000,18375"
)
tg (CPTG
uid 1557,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1558,0
va (VaSet
)
xt "50000,17400,52400,18600"
st "wrL"
blo "50000,18400"
)
)
thePort (LogicalPort
decl (Decl
n "wrL"
t "std_ulogic"
o 10
)
)
)
*54 (CptPort
uid 1559,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1560,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "48250,9625,49000,10375"
)
tg (CPTG
uid 1561,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1562,0
va (VaSet
)
xt "50000,9400,54800,10600"
st "dataOut"
blo "50000,10400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
)
)
)
*55 (CptPort
uid 1563,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1564,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,31625,65750,32375"
)
tg (CPTG
uid 1565,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1566,0
va (VaSet
)
xt "59401,31400,64001,32600"
st "testOut"
ju 2
blo "64001,32400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO 16)"
o 12
)
)
)
*56 (CptPort
uid 1567,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1568,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,29625,65750,30375"
)
tg (CPTG
uid 1569,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1570,0
va (VaSet
)
xt "58201,29400,64001,30600"
st "selSinCos"
ju 2
blo "64001,30400"
)
)
thePort (LogicalPort
decl (Decl
n "selSinCos"
t "std_ulogic"
o 13
)
)
)
*57 (CptPort
uid 1571,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1572,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,9625,65750,10375"
)
tg (CPTG
uid 1573,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1574,0
va (VaSet
)
xt "61001,9400,64001,10600"
st "outZ"
ju 2
blo "64001,10400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outZ"
t "std_ulogic"
o 14
)
)
)
*58 (CptPort
uid 1575,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1576,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,15625,65750,16375"
)
tg (CPTG
uid 1577,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1578,0
va (VaSet
)
xt "59900,15400,64000,16600"
st "CLK_X"
ju 2
blo "64000,16400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_X"
t "std_ulogic"
o 17
)
)
)
*59 (CptPort
uid 1579,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1580,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,13625,65750,14375"
)
tg (CPTG
uid 1581,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1582,0
va (VaSet
)
xt "59300,13400,64000,14600"
st "CS_X_n"
ju 2
blo "64000,14400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CS_X_n"
t "std_ulogic"
o 15
)
)
)
*60 (CptPort
uid 1583,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1584,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,17625,65750,18375"
)
tg (CPTG
uid 1585,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1586,0
va (VaSet
)
xt "60000,17400,64000,18600"
st "SDI_X"
ju 2
blo "64000,18400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SDI_X"
t "std_ulogic"
o 16
)
)
)
*61 (CptPort
uid 1587,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1588,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,21625,65750,22375"
)
tg (CPTG
uid 1589,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1590,0
va (VaSet
)
xt "59300,21400,64000,22600"
st "CS_Y_n"
ju 2
blo "64000,22400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CS_Y_n"
t "std_ulogic"
o 19
)
)
)
*62 (CptPort
uid 1591,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1592,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,25625,65750,26375"
)
tg (CPTG
uid 1593,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1594,0
va (VaSet
)
xt "60000,25400,64000,26600"
st "SDI_Y"
ju 2
blo "64000,26400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SDI_Y"
t "std_ulogic"
o 20
)
)
)
*63 (CptPort
uid 1595,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1596,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "65000,23625,65750,24375"
)
tg (CPTG
uid 1597,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1598,0
va (VaSet
)
xt "59900,23400,64000,24600"
st "CLK_Y"
ju 2
blo "64000,24400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_Y"
t "std_ulogic"
o 18
)
)
)
]
shape (Rectangle
uid 1600,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "49000,2000,65000,36000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1601,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*64 (Text
uid 1602,0
va (VaSet
)
xt "49600,35800,53900,37000"
st "Curves"
blo "49600,36800"
tm "BdLibraryNameMgr"
)
*65 (Text
uid 1603,0
va (VaSet
)
xt "49600,36800,62900,38000"
st "beamerPeriphBlanking"
blo "49600,37800"
tm "CptNameMgr"
)
*66 (Text
uid 1604,0
va (VaSet
)
xt "49600,37800,51500,39000"
st "I0"
blo "49600,38800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1605,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1606,0
text (MLText
uid 1607,0
va (VaSet
font "Verdana,8,0"
)
xt "49000,39600,64000,41600"
st "dataBitNb    = 16    ( positive ) 
addressBitNb = 24    ( positive ) "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "16"
)
(GiElement
name "addressBitNb"
type "positive"
value "24"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*67 (SaComponent
uid 1624,0
optionalChildren [
*68 (CptPort
uid 1608,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1609,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,32625,107000,33375"
)
tg (CPTG
uid 1610,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1611,0
va (VaSet
)
xt "108000,32400,110800,33600"
st "CLK"
blo "108000,33400"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_ulogic"
o 17
)
)
)
*69 (CptPort
uid 1612,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1613,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,28625,107000,29375"
)
tg (CPTG
uid 1614,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1615,0
va (VaSet
)
xt "108000,28400,111400,29600"
st "CS_n"
blo "108000,29400"
)
)
thePort (LogicalPort
decl (Decl
n "CS_n"
t "std_ulogic"
o 15
)
)
)
*70 (CptPort
uid 1616,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1617,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,30625,107000,31375"
)
tg (CPTG
uid 1618,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1619,0
va (VaSet
)
xt "108000,30400,110700,31600"
st "SDI"
blo "108000,31400"
)
)
thePort (LogicalPort
decl (Decl
n "SDI"
t "std_ulogic"
o 16
)
)
)
*71 (CptPort
uid 1620,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1621,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "115000,28625,115750,29375"
)
tg (CPTG
uid 1622,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1623,0
va (VaSet
)
xt "111200,28400,114000,29600"
st "Iout"
ju 2
blo "114000,29400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Iout"
t "natural"
o 4
)
)
)
]
shape (Rectangle
uid 1625,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "107000,27000,115000,35000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1626,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*72 (Text
uid 1627,0
va (VaSet
)
xt "107600,34800,115200,36000"
st "Curves_test"
blo "107600,35800"
tm "BdLibraryNameMgr"
)
*73 (Text
uid 1628,0
va (VaSet
)
xt "107600,35800,114100,37000"
st "DAC_5543"
blo "107600,36800"
tm "CptNameMgr"
)
*74 (Text
uid 1629,0
va (VaSet
)
xt "107600,36800,109500,38000"
st "I2"
blo "107600,37800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1630,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1631,0
text (MLText
uid 1632,0
va (VaSet
font "Verdana,8,0"
)
xt "72000,12000,72000,12000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*75 (SaComponent
uid 1649,0
optionalChildren [
*76 (CptPort
uid 1658,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1659,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,48625,107000,49375"
)
tg (CPTG
uid 1660,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1661,0
va (VaSet
)
xt "108000,48400,110800,49600"
st "CLK"
blo "108000,49400"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_ulogic"
o 17
)
)
)
*77 (CptPort
uid 1662,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1663,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,44625,107000,45375"
)
tg (CPTG
uid 1664,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1665,0
va (VaSet
)
xt "108000,44400,111400,45600"
st "CS_n"
blo "108000,45400"
)
)
thePort (LogicalPort
decl (Decl
n "CS_n"
t "std_ulogic"
o 15
)
)
)
*78 (CptPort
uid 1666,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1667,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,46625,107000,47375"
)
tg (CPTG
uid 1668,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1669,0
va (VaSet
)
xt "108000,46400,110700,47600"
st "SDI"
blo "108000,47400"
)
)
thePort (LogicalPort
decl (Decl
n "SDI"
t "std_ulogic"
o 16
)
)
)
*79 (CptPort
uid 1670,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1671,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "115000,44625,115750,45375"
)
tg (CPTG
uid 1672,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1673,0
va (VaSet
)
xt "111200,44400,114000,45600"
st "Iout"
ju 2
blo "114000,45400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Iout"
t "natural"
o 4
)
)
)
]
shape (Rectangle
uid 1650,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "107000,43000,115000,51000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1651,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*80 (Text
uid 1652,0
va (VaSet
)
xt "107600,50800,115200,52000"
st "Curves_test"
blo "107600,51800"
tm "BdLibraryNameMgr"
)
*81 (Text
uid 1653,0
va (VaSet
)
xt "107600,51800,114100,53000"
st "DAC_5543"
blo "107600,52800"
tm "CptNameMgr"
)
*82 (Text
uid 1654,0
va (VaSet
)
xt "107600,52800,109500,54000"
st "I4"
blo "107600,53800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1655,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1656,0
text (MLText
uid 1657,0
va (VaSet
font "Verdana,8,0"
)
xt "72000,28000,72000,28000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*83 (Net
uid 1674,0
decl (Decl
n "CS_X_n"
t "std_ulogic"
o 3
suid 16,0
)
declText (MLText
uid 1675,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,18600,16000,19600"
st "SIGNAL CS_X_n     : std_ulogic
"
)
)
*84 (Net
uid 1682,0
decl (Decl
n "CLK_X"
t "std_ulogic"
o 1
suid 17,0
)
declText (MLText
uid 1683,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,16600,15800,17600"
st "SIGNAL CLK_X      : std_ulogic
"
)
)
*85 (Net
uid 1690,0
decl (Decl
n "SDI_X"
t "std_ulogic"
o 7
suid 18,0
)
declText (MLText
uid 1691,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,22600,15600,23600"
st "SIGNAL SDI_X      : std_ulogic
"
)
)
*86 (Net
uid 1698,0
decl (Decl
n "CS_Y_n"
t "std_ulogic"
o 4
suid 19,0
)
declText (MLText
uid 1699,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,19600,16000,20600"
st "SIGNAL CS_Y_n     : std_ulogic
"
)
)
*87 (Net
uid 1706,0
decl (Decl
n "CLK_Y"
t "std_ulogic"
o 2
suid 20,0
)
declText (MLText
uid 1707,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,17600,15800,18600"
st "SIGNAL CLK_Y      : std_ulogic
"
)
)
*88 (Net
uid 1714,0
decl (Decl
n "SDI_Y"
t "std_ulogic"
o 8
suid 21,0
)
declText (MLText
uid 1715,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,23600,15600,24600"
st "SIGNAL SDI_Y      : std_ulogic
"
)
)
*89 (Net
uid 1786,0
decl (Decl
n "IoutX"
t "natural"
o 5
suid 22,0
)
declText (MLText
uid 1787,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,20600,14100,21600"
st "SIGNAL IoutX      : natural
"
)
)
*90 (Net
uid 1788,0
decl (Decl
n "IoutY"
t "natural"
o 6
suid 23,0
)
declText (MLText
uid 1789,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,21600,14100,22600"
st "SIGNAL IoutY      : natural
"
)
)
*91 (Wire
uid 47,0
shape (OrthoPolyLine
uid 48,0
va (VaSet
vasetType 3
)
xt "45000,34000,48250,44000"
pts [
"45000,44000"
"45000,34000"
"48250,34000"
]
)
start &14
end &47
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 51,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 52,0
va (VaSet
font "Verdana,12,0"
)
xt "45000,32600,49100,34000"
st "reset"
blo "45000,33800"
tm "WireNameMgr"
)
)
on &1
)
*92 (Wire
uid 55,0
shape (OrthoPolyLine
uid 56,0
va (VaSet
vasetType 3
)
xt "43000,32000,48250,44000"
pts [
"43000,44000"
"43000,32000"
"48250,32000"
]
)
start &14
end &44
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 59,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 60,0
va (VaSet
font "Verdana,12,0"
)
xt "45000,30600,48800,32000"
st "clock"
blo "45000,31800"
tm "WireNameMgr"
)
)
on &2
)
*93 (Wire
uid 760,0
shape (OrthoPolyLine
uid 761,0
va (VaSet
vasetType 3
)
xt "39000,20000,48250,44000"
pts [
"48250,20000"
"39000,20000"
"39000,44000"
]
)
start &52
end &14
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 764,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 765,0
va (VaSet
font "Verdana,12,0"
)
xt "46250,18600,48350,20000"
st "cs"
blo "46250,19800"
tm "WireNameMgr"
)
)
on &18
)
*94 (Wire
uid 768,0
shape (OrthoPolyLine
uid 769,0
va (VaSet
vasetType 3
)
xt "37000,18000,48250,44000"
pts [
"48250,18000"
"37000,18000"
"37000,44000"
]
)
start &53
end &14
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 772,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 773,0
va (VaSet
font "Verdana,12,0"
)
xt "45250,16600,48350,18000"
st "wrL"
blo "45250,17800"
tm "WireNameMgr"
)
)
on &19
)
*95 (Wire
uid 776,0
shape (OrthoPolyLine
uid 777,0
va (VaSet
vasetType 3
)
xt "35000,16000,48250,44000"
pts [
"48250,16000"
"35000,16000"
"35000,44000"
]
)
start &51
end &14
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 780,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 781,0
va (VaSet
font "Verdana,12,0"
)
xt "44250,14600,47550,16000"
st "wrH"
blo "44250,15800"
tm "WireNameMgr"
)
)
on &20
)
*96 (Wire
uid 784,0
shape (OrthoPolyLine
uid 785,0
va (VaSet
vasetType 3
)
xt "33000,14000,48250,44000"
pts [
"48250,14000"
"33000,14000"
"33000,44000"
]
)
start &50
end &14
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 788,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 789,0
va (VaSet
font "Verdana,12,0"
)
xt "46250,12600,48350,14000"
st "rd"
blo "46250,13800"
tm "WireNameMgr"
)
)
on &21
)
*97 (Wire
uid 792,0
shape (OrthoPolyLine
uid 793,0
va (VaSet
vasetType 3
)
xt "65750,8000,79000,44000"
pts [
"65750,8000"
"79000,8000"
"79000,44000"
]
)
start &48
end &14
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 796,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 797,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,6600,71350,8000"
st "outY"
blo "67750,7800"
tm "WireNameMgr"
)
)
on &22
)
*98 (Wire
uid 800,0
shape (OrthoPolyLine
uid 801,0
va (VaSet
vasetType 3
)
xt "65750,6000,81000,44000"
pts [
"65750,6000"
"81000,6000"
"81000,44000"
]
)
start &46
end &14
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 804,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 805,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,4600,71450,6000"
st "outX"
blo "67750,5800"
tm "WireNameMgr"
)
)
on &23
)
*99 (Wire
uid 808,0
shape (OrthoPolyLine
uid 809,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "29000,10000,48250,44000"
pts [
"48250,10000"
"29000,10000"
"29000,44000"
]
)
start &54
end &14
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 812,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 813,0
va (VaSet
font "Verdana,12,0"
)
xt "42250,8600,48250,10000"
st "dataOut"
blo "42250,9800"
tm "WireNameMgr"
)
)
on &24
)
*100 (Wire
uid 816,0
shape (OrthoPolyLine
uid 817,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "27000,8000,48250,44000"
pts [
"48250,8000"
"27000,8000"
"27000,44000"
]
)
start &49
end &14
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 820,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 821,0
va (VaSet
font "Verdana,12,0"
)
xt "43250,6600,48250,8000"
st "dataIn"
blo "43250,7800"
tm "WireNameMgr"
)
)
on &25
)
*101 (Wire
uid 824,0
shape (OrthoPolyLine
uid 825,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "25000,6000,48250,44000"
pts [
"48250,6000"
"25000,6000"
"25000,44000"
]
)
start &45
end &14
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 828,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 829,0
va (VaSet
font "Verdana,12,0"
)
xt "44250,4600,47950,6000"
st "addr"
blo "44250,5800"
tm "WireNameMgr"
)
)
on &26
)
*102 (Wire
uid 1009,0
shape (OrthoPolyLine
uid 1010,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "99000,11000,106250,11000"
pts [
"106250,11000"
"99000,11000"
]
)
start &35
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1013,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1014,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,9600,108300,11000"
st "lowpassIn"
blo "101000,10800"
tm "WireNameMgr"
)
)
on &39
)
*103 (Wire
uid 1015,0
shape (OrthoPolyLine
uid 1016,0
va (VaSet
vasetType 3
)
xt "103000,15000,106250,15000"
pts [
"103000,15000"
"106250,15000"
]
)
end &32
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1019,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1020,0
va (VaSet
font "Verdana,12,0"
)
xt "102000,13600,105800,15000"
st "clock"
blo "102000,14800"
tm "WireNameMgr"
)
)
on &2
)
*104 (Wire
uid 1021,0
shape (OrthoPolyLine
uid 1022,0
va (VaSet
vasetType 3
)
xt "103000,17000,106250,17000"
pts [
"103000,17000"
"106250,17000"
]
)
end &34
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1025,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1026,0
va (VaSet
font "Verdana,12,0"
)
xt "102000,15600,106100,17000"
st "reset"
blo "102000,16800"
tm "WireNameMgr"
)
)
on &1
)
*105 (Wire
uid 1027,0
shape (OrthoPolyLine
uid 1028,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "123750,11000,131000,11000"
pts [
"123750,11000"
"131000,11000"
]
)
start &33
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1031,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1032,0
va (VaSet
font "Verdana,12,0"
)
xt "126750,9600,135850,11000"
st "lowpassOut"
blo "126750,10800"
tm "WireNameMgr"
)
)
on &40
)
*106 (Wire
uid 1191,0
shape (OrthoPolyLine
uid 1192,0
va (VaSet
vasetType 3
)
xt "65750,30000,73000,44000"
pts [
"65750,30000"
"73000,30000"
"73000,44000"
]
)
start &56
end &14
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1195,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1196,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,28600,74650,30000"
st "selSinCos"
blo "67750,29800"
tm "WireNameMgr"
)
)
on &41
)
*107 (Wire
uid 1479,0
shape (OrthoPolyLine
uid 1480,0
va (VaSet
vasetType 3
)
xt "65750,10000,77000,44000"
pts [
"65750,10000"
"77000,10000"
"77000,44000"
]
)
start &57
end &14
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1483,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1484,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,8600,71450,10000"
st "outZ"
blo "67750,9800"
tm "WireNameMgr"
)
)
on &42
)
*108 (Wire
uid 1676,0
shape (OrthoPolyLine
uid 1677,0
va (VaSet
vasetType 3
)
xt "65750,14000,73000,14000"
pts [
"65750,14000"
"73000,14000"
]
)
start &59
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1680,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1681,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,12600,73450,14000"
st "CS_X_n"
blo "67750,13800"
tm "WireNameMgr"
)
)
on &83
)
*109 (Wire
uid 1684,0
shape (OrthoPolyLine
uid 1685,0
va (VaSet
vasetType 3
)
xt "65750,16000,73000,16000"
pts [
"65750,16000"
"73000,16000"
]
)
start &58
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1688,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1689,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,14600,72550,16000"
st "CLK_X"
blo "67750,15800"
tm "WireNameMgr"
)
)
on &84
)
*110 (Wire
uid 1692,0
shape (OrthoPolyLine
uid 1693,0
va (VaSet
vasetType 3
)
xt "65750,18000,73000,18000"
pts [
"65750,18000"
"73000,18000"
]
)
start &60
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1696,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1697,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,16600,72350,18000"
st "SDI_X"
blo "67750,17800"
tm "WireNameMgr"
)
)
on &85
)
*111 (Wire
uid 1700,0
shape (OrthoPolyLine
uid 1701,0
va (VaSet
vasetType 3
)
xt "65750,22000,73000,22000"
pts [
"65750,22000"
"73000,22000"
]
)
start &61
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1704,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1705,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,20600,73350,22000"
st "CS_Y_n"
blo "67750,21800"
tm "WireNameMgr"
)
)
on &86
)
*112 (Wire
uid 1708,0
shape (OrthoPolyLine
uid 1709,0
va (VaSet
vasetType 3
)
xt "65750,24000,73000,24000"
pts [
"65750,24000"
"73000,24000"
]
)
start &63
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1712,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1713,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,22600,72450,24000"
st "CLK_Y"
blo "67750,23800"
tm "WireNameMgr"
)
)
on &87
)
*113 (Wire
uid 1716,0
shape (OrthoPolyLine
uid 1717,0
va (VaSet
vasetType 3
)
xt "65750,26000,73000,26000"
pts [
"65750,26000"
"73000,26000"
]
)
start &62
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1720,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1721,0
va (VaSet
font "Verdana,12,0"
)
xt "67750,24600,72250,26000"
st "SDI_Y"
blo "67750,25800"
tm "WireNameMgr"
)
)
on &88
)
*114 (Wire
uid 1722,0
shape (OrthoPolyLine
uid 1723,0
va (VaSet
vasetType 3
)
xt "99000,29000,106250,29000"
pts [
"99000,29000"
"106250,29000"
]
)
end &69
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1728,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1729,0
va (VaSet
font "Verdana,12,0"
)
xt "99000,27600,104700,29000"
st "CS_X_n"
blo "99000,28800"
tm "WireNameMgr"
)
)
on &83
)
*115 (Wire
uid 1730,0
shape (OrthoPolyLine
uid 1731,0
va (VaSet
vasetType 3
)
xt "99000,47000,106250,47000"
pts [
"99000,47000"
"106250,47000"
]
)
end &78
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1736,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1737,0
va (VaSet
font "Verdana,12,0"
)
xt "99000,45600,103500,47000"
st "SDI_Y"
blo "99000,46800"
tm "WireNameMgr"
)
)
on &88
)
*116 (Wire
uid 1738,0
shape (OrthoPolyLine
uid 1739,0
va (VaSet
vasetType 3
)
xt "99000,49000,106250,49000"
pts [
"99000,49000"
"106250,49000"
]
)
end &76
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1744,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1745,0
va (VaSet
font "Verdana,12,0"
)
xt "99000,47600,103700,49000"
st "CLK_Y"
blo "99000,48800"
tm "WireNameMgr"
)
)
on &87
)
*117 (Wire
uid 1746,0
shape (OrthoPolyLine
uid 1747,0
va (VaSet
vasetType 3
)
xt "99000,33000,106250,33000"
pts [
"99000,33000"
"106250,33000"
]
)
end &68
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1752,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
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elements [
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tm "HdlTextNumberMgr"
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tm "HdlTextMgr"
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tm "WireNameMgr"
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xt "500,-375,2000,375"
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tm "WireNameMgr"
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stg "STSignalDisplayStrategy"
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tm "WireNameMgr"
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)
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sat 32
eat 32
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sat 32
eat 32
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xt "0,9600,4800,10600"
st "Pre User:"
blo "0,10400"
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preUserText (MLText
uid 5,0
va (VaSet
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xt "2000,10600,22100,15600"
st "constant addressBitNb: positive := 24;
constant dataBitNb: positive := 16;
constant signalBitNb: positive := 16;
constant clockFrequency : real := 60.0E6;
--constant clockFrequency : real := 66.0E6;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
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xt "0,15600,9000,16600"
st "Diagram Signals:"
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va (VaSet
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xt "0,7600,6000,8600"
st "Post User:"
blo "0,8400"
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postUserText (MLText
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va (VaSet
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font "Verdana,8,0"
)
xt "0,7600,0,7600"
tm "BdDeclarativeTextMgr"
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usingSuid 1
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*158 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*159 (GroupColHdr
tm "GroupColHdrMgr"
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*160 (NameColHdr
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*161 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
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*162 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
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*163 (BoundsColHdr
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*175 (LeafLogPort
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suid 10,0
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*176 (LeafLogPort
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suid 11,0
)
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*177 (LeafLogPort
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*178 (LeafLogPort
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*182 (LeafLogPort
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suid 17,0
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uid 1822,0
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*183 (LeafLogPort
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decl (Decl
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)
)
uid 1824,0
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*184 (LeafLogPort
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suid 19,0
)
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*185 (LeafLogPort
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o 2
suid 20,0
)
)
uid 1828,0
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*186 (LeafLogPort
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m 4
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o 8
suid 21,0
)
)
uid 1830,0
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*187 (LeafLogPort
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m 4
decl (Decl
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o 5
suid 22,0
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*188 (LeafLogPort
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uid 1834,0
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pdm (PhysicalDM
uid 1850,0
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groupVa (MVa
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uid 1809,0
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uid 1862,0
)
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pos 6
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uid 1863,0
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uid 1864,0
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fixedCol 4
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genericsCommonDM (CommonDM
ldm (LogicalDM
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uid 1866,0
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*227 (TitleRowHdr
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*228 (FilterRowHdr
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*229 (RefLabelColHdr
tm "RefLabelColHdrMgr"
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*230 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*231 (GroupColHdr
tm "GroupColHdrMgr"
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*232 (NameColHdr
tm "GenericNameColHdrMgr"
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*233 (TypeColHdr
tm "GenericTypeColHdrMgr"
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*234 (InitColHdr
tm "GenericValueColHdrMgr"
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*235 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
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*236 (EolColHdr
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groupVa (MVa
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sheetCol (SheetCol
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activeModelName "BlockDiag"
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