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    if reset = '1' then
      txSend <= '0';
    elsif rising_edge(clock) then
      if ( (txFifoEmpty = '0') and (txBusy = '0') ) then
        txSend <= '1';
      else
        txSend <= '0';
      end if;
    end if;
  end process;
      
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 14000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 1411,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "53000,51000,69000,67000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1412,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*32 (Text
uid 1413,0
va (VaSet
)
xt "53400,67000,56000,68200"
st "eb1"
blo "53400,68000"
tm "HdlTextNameMgr"
)
*33 (Text
uid 1414,0
va (VaSet
)
xt "53400,68000,54800,69200"
st "1"
blo "53400,69000"
tm "HdlTextNumberMgr"
)
]
)
)
*34 (PortIoOut
uid 1431,0
shape (CompositeShape
uid 1432,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1433,0
sl 0
ro 270
xt "105500,64625,107000,65375"
)
(Line
uid 1434,0
sl 0
ro 270
xt "105000,65000,105500,65000"
pts [
"105000,65000"
"105500,65000"
]
)
]
)
tg (WTG
uid 1435,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1436,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "108000,64300,112100,65700"
st "txFull"
blo "108000,65500"
tm "WireNameMgr"
)
)
)
*35 (Net
uid 1443,0
decl (Decl
n "txFull"
t "std_ulogic"
o 9
suid 25,0
)
declText (MLText
uid 1444,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,13500,12200,14500"
st "txFull      : std_ulogic"
)
)
*36 (PortIoIn
uid 1445,0
shape (CompositeShape
uid 1446,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1447,0
sl 0
ro 90
xt "105500,48625,107000,49375"
)
(Line
uid 1448,0
sl 0
ro 90
xt "105000,49000,105500,49000"
pts [
"105500,49000"
"105000,49000"
]
)
]
)
tg (WTG
uid 1449,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1450,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "108000,48300,111800,49700"
st "txWr"
blo "108000,49500"
tm "WireNameMgr"
)
)
)
*37 (Net
uid 1457,0
decl (Decl
n "txWr"
t "std_ulogic"
o 10
suid 26,0
)
declText (MLText
uid 1458,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,14300,12500,15300"
st "txWr        : std_ulogic"
)
)
*38 (PortIoOut
uid 1459,0
shape (CompositeShape
uid 1460,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1461,0
sl 0
ro 270
xt "77500,24625,79000,25375"
)
(Line
uid 1462,0
sl 0
ro 270
xt "77000,25000,77500,25000"
pts [
"77000,25000"
"77500,25000"
]
)
]
)
tg (WTG
uid 1463,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1464,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "80000,24300,103800,25700"
st "rxData : (dataBitNb-1 DOWNTO 0)"
blo "80000,25500"
tm "WireNameMgr"
)
)
)
*39 (Net
uid 1465,0
decl (Decl
n "rxData"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 7
suid 27,0
)
declText (MLText
uid 1466,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,11900,26600,12900"
st "rxData      : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*40 (Net
uid 1469,0
decl (Decl
n "txData"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 28,0
)
declText (MLText
uid 1470,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,12700,26600,13700"
st "txData      : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*41 (PortIoIn
uid 1471,0
shape (CompositeShape
uid 1472,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1473,0
sl 0
ro 90
xt "105500,46625,107000,47375"
)
(Line
uid 1474,0
sl 0
ro 90
xt "105000,47000,105500,47000"
pts [
"105500,47000"
"105000,47000"
]
)
]
)
tg (WTG
uid 1475,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1476,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "108000,46500,131800,47900"
st "txData : (dataBitNb-1 DOWNTO 0)"
blo "108000,47700"
tm "WireNameMgr"
)
)
)
*42 (SaComponent
uid 1663,0
optionalChildren [
*43 (CptPort
uid 1643,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1644,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "24250,24625,25000,25375"
)
tg (CPTG
uid 1645,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1646,0
va (VaSet
)
xt "26000,24400,28800,25600"
st "RxD"
blo "26000,25400"
)
)
thePort (LogicalPort
decl (Decl
n "RxD"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*44 (CptPort
uid 1647,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1648,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "24250,28625,25000,29375"
)
tg (CPTG
uid 1649,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1650,0
va (VaSet
)
xt "26000,28400,29400,29600"
st "clock"
blo "26000,29400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*45 (CptPort
uid 1651,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1652,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "24250,30625,25000,31375"
)
tg (CPTG
uid 1653,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1654,0
va (VaSet
)
xt "26000,30400,29300,31600"
st "reset"
blo "26000,31400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*46 (CptPort
uid 1655,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1656,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,24625,41750,25375"
)
tg (CPTG
uid 1657,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1658,0
va (VaSet
)
xt "35201,24400,40001,25600"
st "dataOut"
ju 2
blo "40001,25400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*47 (CptPort
uid 1659,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1660,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,26625,41750,27375"
)
tg (CPTG
uid 1661,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1662,0
va (VaSet
)
xt "34500,26400,40000,27600"
st "dataValid"
ju 2
blo "40000,27400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataValid"
t "std_ulogic"
o 5
suid 5,0
)
)
)
]
shape (Rectangle
uid 1664,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "25000,21000,41000,33000"
)
oxt "34000,16000,50000,28000"
ttg (MlTextGroup
uid 1665,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*48 (Text
uid 1666,0
va (VaSet
font "Verdana,9,1"
)
xt "25600,32800,29300,34000"
st "RS232"
blo "25600,33800"
tm "BdLibraryNameMgr"
)
*49 (Text
uid 1667,0
va (VaSet
font "Verdana,9,1"
)
xt "25600,34000,36000,35200"
st "serialPortReceiver"
blo "25600,35000"
tm "CptNameMgr"
)
*50 (Text
uid 1668,0
va (VaSet
font "Verdana,9,1"
)
xt "25600,35200,28300,36400"
st "I_rx"
blo "25600,36200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1669,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1670,0
text (MLText
uid 1671,0
va (VaSet
font "Verdana,8,0"
)
xt "25000,36400,47400,38400"
st "dataBitNb      = dataBitNb         ( positive )  
baudRateDivide = baudRateDivide    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "baudRateDivide"
type "positive"
value "baudRateDivide"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*51 (SaComponent
uid 1696,0
optionalChildren [
*52 (CptPort
uid 1672,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1673,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "24250,46625,25000,47375"
)
tg (CPTG
uid 1674,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1675,0
va (VaSet
)
xt "26000,46400,28800,47600"
st "TxD"
blo "26000,47400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "TxD"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*53 (CptPort
uid 1676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1677,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,54625,41750,55375"
)
tg (CPTG
uid 1678,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1679,0
va (VaSet
)
xt "36600,54400,40000,55600"
st "clock"
ju 2
blo "40000,55400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*54 (CptPort
uid 1680,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1681,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,56625,41750,57375"
)
tg (CPTG
uid 1682,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1683,0
va (VaSet
)
xt "36700,56400,40000,57600"
st "reset"
ju 2
blo "40000,57400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*55 (CptPort
uid 1684,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1685,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,46625,41750,47375"
)
tg (CPTG
uid 1686,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1687,0
va (VaSet
)
xt "36001,46400,40001,47600"
st "dataIn"
ju 2
blo "40001,47400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*56 (CptPort
uid 1688,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1689,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,48625,41750,49375"
)
tg (CPTG
uid 1690,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1691,0
va (VaSet
)
xt "36900,48400,40000,49600"
st "send"
ju 2
blo "40000,49400"
)
)
thePort (LogicalPort
decl (Decl
n "send"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*57 (CptPort
uid 1692,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1693,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "41000,50625,41750,51375"
)
tg (CPTG
uid 1694,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1695,0
va (VaSet
)
xt "36900,50400,40000,51600"
st "busy"
ju 2
blo "40000,51400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "busy"
t "std_ulogic"
o 6
suid 6,0
)
)
)
]
shape (Rectangle
uid 1697,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "25000,43000,41000,59000"
)
oxt "34000,12000,50000,28000"
ttg (MlTextGroup
uid 1698,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*58 (Text
uid 1699,0
va (VaSet
font "Verdana,9,1"
)
xt "25600,58800,29300,60000"
st "RS232"
blo "25600,59800"
tm "BdLibraryNameMgr"
)
*59 (Text
uid 1700,0
va (VaSet
font "Verdana,9,1"
)
xt "25600,60000,38200,61200"
st "serialPortTransmitter"
blo "25600,61000"
tm "CptNameMgr"
)
*60 (Text
uid 1701,0
va (VaSet
font "Verdana,9,1"
)
xt "25600,61200,28400,62400"
st "I_tx"
blo "25600,62200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1702,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1703,0
text (MLText
uid 1704,0
va (VaSet
font "Verdana,8,0"
)
xt "25000,62400,47400,64400"
st "dataBitNb      = dataBitNb         ( positive )  
baudRateDivide = baudRateDivide    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "baudRateDivide"
type "positive"
value "baudRateDivide"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*61 (SaComponent
uid 1778,0
optionalChildren [
*62 (CptPort
uid 1746,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1747,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52250,26625,53000,27375"
)
tg (CPTG
uid 1748,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1749,0
va (VaSet
)
xt "54000,26400,57100,27600"
st "write"
blo "54000,27400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*63 (CptPort
uid 1750,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1751,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52250,30625,53000,31375"
)
tg (CPTG
uid 1752,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1753,0
va (VaSet
)
xt "54000,30400,57400,31600"
st "clock"
blo "54000,31400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*64 (CptPort
uid 1754,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1755,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52250,32625,53000,33375"
)
tg (CPTG
uid 1756,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1757,0
va (VaSet
)
xt "54000,32400,57300,33600"
st "reset"
blo "54000,33400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*65 (CptPort
uid 1758,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1759,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "69000,24625,69750,25375"
)
tg (CPTG
uid 1760,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1761,0
va (VaSet
)
xt "63201,24400,68001,25600"
st "dataOut"
ju 2
blo "68001,25400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*66 (CptPort
uid 1762,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1763,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "69000,26625,69750,27375"
)
tg (CPTG
uid 1764,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1765,0
va (VaSet
)
xt "65100,26400,68000,27600"
st "read"
ju 2
blo "68000,27400"
)
)
thePort (LogicalPort
decl (Decl
n "read"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*67 (CptPort
uid 1766,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1767,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "52250,24625,53000,25375"
)
tg (CPTG
uid 1768,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1769,0
va (VaSet
)
xt "53999,24400,57999,25600"
st "dataIn"
blo "53999,25400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*68 (CptPort
uid 1770,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1771,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "69000,28625,69750,29375"
)
tg (CPTG
uid 1772,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1773,0
va (VaSet
)
xt "64200,28400,68000,29600"
st "empty"
ju 2
blo "68000,29400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "empty"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*69 (CptPort
uid 1774,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1775,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "69000,30625,69750,31375"
)
tg (CPTG
uid 1776,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1777,0
va (VaSet
)
xt "65800,30400,68000,31600"
st "full"
ju 2
blo "68000,31400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "full"
t "std_ulogic"
o 8
suid 8,0
)
)
)
]
shape (Rectangle
uid 1779,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "53000,21000,69000,35000"
)
oxt "34000,14000,50000,28000"
ttg (MlTextGroup
uid 1780,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*70 (Text
uid 1781,0
va (VaSet
font "Verdana,9,1"
)
xt "53600,34800,58200,36000"
st "memory"
blo "53600,35800"
tm "BdLibraryNameMgr"
)
*71 (Text
uid 1782,0
va (VaSet
font "Verdana,9,1"
)
xt "53600,36000,56700,37200"
st "FIFO"
blo "53600,37000"
tm "CptNameMgr"
)
*72 (Text
uid 1783,0
va (VaSet
font "Verdana,9,1"
)
xt "53600,37200,58300,38400"
st "I_rxFifo"
blo "53600,38200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1784,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1785,0
text (MLText
uid 1786,0
va (VaSet
font "Verdana,8,0"
)
xt "53000,38400,71000,40400"
st "dataBitNb = dataBitNb      ( positive )  
depth     = rxFifoDepth    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "depth"
type "positive"
value "rxFifoDepth"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*73 (SaComponent
uid 1819,0
optionalChildren [
*74 (CptPort
uid 1787,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1788,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,48625,97750,49375"
)
tg (CPTG
uid 1789,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1790,0
va (VaSet
)
xt "92900,48400,96000,49600"
st "write"
ju 2
blo "96000,49400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*75 (CptPort
uid 1791,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1792,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,52625,97750,53375"
)
tg (CPTG
uid 1793,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1794,0
va (VaSet
)
xt "92600,52400,96000,53600"
st "clock"
ju 2
blo "96000,53400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*76 (CptPort
uid 1795,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1796,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,54625,97750,55375"
)
tg (CPTG
uid 1797,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1798,0
va (VaSet
)
xt "92700,54400,96000,55600"
st "reset"
ju 2
blo "96000,55400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*77 (CptPort
uid 1799,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1800,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,46625,81000,47375"
)
tg (CPTG
uid 1801,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1802,0
va (VaSet
)
xt "81999,46400,86799,47600"
st "dataOut"
blo "81999,47400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*78 (CptPort
uid 1803,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1804,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,48625,81000,49375"
)
tg (CPTG
uid 1805,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1806,0
va (VaSet
)
xt "82000,48400,84900,49600"
st "read"
blo "82000,49400"
)
)
thePort (LogicalPort
decl (Decl
n "read"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*79 (CptPort
uid 1807,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1808,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "97000,46625,97750,47375"
)
tg (CPTG
uid 1809,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1810,0
va (VaSet
)
xt "92001,46400,96001,47600"
st "dataIn"
ju 2
blo "96001,47400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*80 (CptPort
uid 1811,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1812,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,50625,81000,51375"
)
tg (CPTG
uid 1813,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1814,0
va (VaSet
)
xt "82000,50400,85800,51600"
st "empty"
blo "82000,51400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "empty"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*81 (CptPort
uid 1815,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1816,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "80250,52625,81000,53375"
)
tg (CPTG
uid 1817,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1818,0
va (VaSet
)
xt "82000,52400,84200,53600"
st "full"
blo "82000,53400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "full"
t "std_ulogic"
o 8
suid 8,0
)
)
)
]
shape (Rectangle
uid 1820,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "81000,43000,97000,57000"
)
oxt "34000,14000,50000,28000"
ttg (MlTextGroup
uid 1821,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*82 (Text
uid 1822,0
va (VaSet
font "Verdana,9,1"
)
xt "81600,56800,86200,58000"
st "memory"
blo "81600,57800"
tm "BdLibraryNameMgr"
)
*83 (Text
uid 1823,0
va (VaSet
font "Verdana,9,1"
)
xt "81600,58000,84700,59200"
st "FIFO"
blo "81600,59000"
tm "CptNameMgr"
)
*84 (Text
uid 1824,0
va (VaSet
font "Verdana,9,1"
)
xt "81600,59200,86400,60400"
st "I_txFifo"
blo "81600,60200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1825,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1826,0
text (MLText
uid 1827,0
va (VaSet
font "Verdana,8,0"
)
xt "81000,60400,99000,62400"
st "dataBitNb = dataBitNb      ( positive )  
depth     = txFifoDepth    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "depth"
type "positive"
value "txFifoDepth"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*85 (Wire
uid 59,0
shape (OrthoPolyLine
uid 60,0
va (VaSet
vasetType 3
)
xt "17000,29000,24250,29000"
pts [
"17000,29000"
"24250,29000"
]
)
start &12
end &44
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 63,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 64,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,27600,22800,29000"
st "clock"
blo "19000,28800"
tm "WireNameMgr"
)
)
on &13
)
*86 (Wire
uid 101,0
shape (OrthoPolyLine
uid 102,0
va (VaSet
vasetType 3
)
xt "17000,31000,24250,31000"
pts [
"17000,31000"
"24250,31000"
]
)
start &14
end &45
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 105,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 106,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,29600,23100,31000"
st "reset"
blo "19000,30800"
tm "WireNameMgr"
)
)
on &15
)
*87 (Wire
uid 115,0
shape (OrthoPolyLine
uid 116,0
va (VaSet
vasetType 3
)
xt "17000,25000,24250,25000"
pts [
"17000,25000"
"24250,25000"
]
)
start &16
end &43
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 119,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 120,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,23600,22200,25000"
st "RxD"
blo "19000,24800"
tm "WireNameMgr"
)
)
on &17
)
*88 (Wire
uid 143,0
shape (OrthoPolyLine
uid 144,0
va (VaSet
vasetType 3
)
xt "17000,47000,24250,47000"
pts [
"24250,47000"
"17000,47000"
]
)
start &52
end &18
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 147,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 148,0
va (VaSet
font "Verdana,12,0"
)
xt "20000,44600,23100,46000"
st "TxD"
blo "20000,45800"
tm "WireNameMgr"
)
)
on &19
)
*89 (Wire
uid 230,0
shape (OrthoPolyLine
uid 231,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "41750,25000,52250,25000"
pts [
"41750,25000"
"52250,25000"
]
)
start &46
end &67
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 234,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 235,0
va (VaSet
font "Verdana,12,0"
)
xt "43000,23600,48400,25000"
st "rxWord"
blo "43000,24800"
tm "WireNameMgr"
)
)
on &27
)
*90 (Wire
uid 240,0
shape (OrthoPolyLine
uid 241,0
va (VaSet
vasetType 3
)
xt "41750,27000,52250,27000"
pts [
"41750,27000"
"52250,27000"
]
)
start &47
end &62
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 244,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 245,0
va (VaSet
font "Verdana,12,0"
)
xt "43000,25600,52200,27000"
st "rxWordValid"
blo "43000,26800"
tm "WireNameMgr"
)
)
on &29
)
*91 (Wire
uid 374,0
shape (OrthoPolyLine
uid 375,0
va (VaSet
vasetType 3
)
xt "49000,33000,52250,33000"
pts [
"49000,33000"
"52250,33000"
]
)
end &64
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 381,0
va (VaSet
font "Verdana,12,0"
)
xt "48000,31600,52100,33000"
st "reset"
blo "48000,32800"
tm "WireNameMgr"
)
)
on &15
)
*92 (Wire
uid 382,0
shape (OrthoPolyLine
uid 383,0
va (VaSet
vasetType 3
)
xt "49000,31000,52250,31000"
pts [
"49000,31000"
"52250,31000"
]
)
end &63
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
font "Verdana,12,0"
)
xt "48000,29600,51800,31000"
st "clock"
blo "48000,30800"
tm "WireNameMgr"
)
)
on &13
)
*93 (Wire
uid 444,0
shape (OrthoPolyLine
uid 445,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "69750,25000,77000,25000"
pts [
"69750,25000"
"77000,25000"
]
)
start &65
end &38
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 448,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 449,0
va (VaSet
font "Verdana,12,0"
)
xt "72000,23600,77000,25000"
st "rxData"
blo "72000,24800"
tm "WireNameMgr"
)
)
on &39
)
*94 (Wire
uid 601,0
shape (OrthoPolyLine
uid 602,0
va (VaSet
vasetType 3
)
xt "97750,55000,101000,55000"
pts [
"101000,55000"
"97750,55000"
]
)
end &76
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 607,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 608,0
va (VaSet
font "Verdana,12,0"
)
xt "99000,53600,103100,55000"
st "reset"
blo "99000,54800"
tm "WireNameMgr"
)
)
on &15
)
*95 (Wire
uid 609,0
shape (OrthoPolyLine
uid 610,0
va (VaSet
vasetType 3
)
xt "97750,53000,101000,53000"
pts [
"101000,53000"
"97750,53000"
]
)
end &75
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 615,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 616,0
va (VaSet
font "Verdana,12,0"
)
xt "99000,51600,102800,53000"
st "clock"
blo "99000,52800"
tm "WireNameMgr"
)
)
on &13
)
*96 (Wire
uid 654,0
shape (OrthoPolyLine
uid 655,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "97750,47000,105000,47000"
pts [
"97750,47000"
"105000,47000"
]
)
start &79
end &41
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 658,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 659,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,45600,106000,47000"
st "txData"
blo "101000,46800"
tm "WireNameMgr"
)
)
on &40
)
*97 (Wire
uid 664,0
shape (OrthoPolyLine
uid 665,0
va (VaSet
vasetType 3
)
xt "69000,51000,80250,55000"
pts [
"80250,51000"
"73000,51000"
"73000,55000"
"69000,55000"
]
)
start &80
end &30
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 668,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 669,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,49600,79900,51000"
st "txFifoEmpty"
blo "71000,50800"
tm "WireNameMgr"
)
)
on &20
)
*98 (Wire
uid 674,0
shape (OrthoPolyLine
uid 675,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "41750,47000,80250,47000"
pts [
"80250,47000"
"41750,47000"
]
)
start &77
end &55
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 678,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 679,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,45600,79400,47000"
st "txWord"
blo "74000,46800"
tm "WireNameMgr"
)
)
on &28
)
*99 (Wire
uid 739,0
shape (OrthoPolyLine
uid 740,0
va (VaSet
vasetType 3
)
xt "41750,57000,45000,57000"
pts [
"45000,57000"
"41750,57000"
]
)
end &54
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 745,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 746,0
va (VaSet
font "Verdana,12,0"
)
xt "43000,55600,47100,57000"
st "reset"
blo "43000,56800"
tm "WireNameMgr"
)
)
on &15
)
*100 (Wire
uid 747,0
shape (OrthoPolyLine
uid 748,0
va (VaSet
vasetType 3
)
xt "41750,55000,45000,55000"
pts [
"45000,55000"
"41750,55000"
]
)
end &53
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 753,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 754,0
va (VaSet
font "Verdana,12,0"
)
xt "43000,53600,46800,55000"
st "clock"
blo "43000,54800"
tm "WireNameMgr"
)
)
on &13
)
*101 (Wire
uid 757,0
shape (OrthoPolyLine
uid 758,0
va (VaSet
vasetType 3
)
xt "41750,51000,53000,57000"
pts [
"41750,51000"
"49000,51000"
"49000,57000"
"53000,57000"
]
)
start &57
end &30
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 761,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 762,0
va (VaSet
font "Verdana,12,0"
)
xt "43750,49600,48750,51000"
st "txBusy"
blo "43750,50800"
tm "WireNameMgr"
)
)
on &21
)
*102 (Wire
uid 765,0
optionalChildren [
*103 (BdJunction
uid 1425,0
ps "OnConnectorStrategy"
shape (Circle
uid 1426,0
va (VaSet
vasetType 1
)
xt "50600,48600,51400,49400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 766,0
va (VaSet
vasetType 3
)
xt "41750,49000,80250,49000"
pts [
"80250,49000"
"41750,49000"
]
)
start &78
end &56
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 771,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 772,0
va (VaSet
font "Verdana,12,0"
)
xt "43000,47600,48200,49000"
st "txSend"
blo "43000,48800"
tm "WireNameMgr"
)
)
on &22
)
*104 (Wire
uid 1376,0
shape (OrthoPolyLine
uid 1377,0
va (VaSet
vasetType 3
)
xt "69750,29000,77000,29000"
pts [
"69750,29000"
"77000,29000"
]
)
start &68
end &23
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1381,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,27600,76900,29000"
st "rxEmpty"
blo "71000,28800"
tm "WireNameMgr"
)
)
on &24
)
*105 (Wire
uid 1390,0
shape (OrthoPolyLine
uid 1391,0
va (VaSet
vasetType 3
)
xt "69750,27000,77000,27000"
pts [
"77000,27000"
"69750,27000"
]
)
start &25
end &66
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1394,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1395,0
va (VaSet
font "Verdana,12,0"
)
xt "73000,25600,76600,27000"
st "rxRd"
blo "73000,26800"
tm "WireNameMgr"
)
)
on &26
)
*106 (Wire
uid 1419,0
shape (OrthoPolyLine
uid 1420,0
va (VaSet
vasetType 3
)
xt "51000,49000,53000,55000"
pts [
"51000,49000"
"51000,55000"
"53000,55000"
]
)
start &103
end &30
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1423,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1424,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "47000,50600,52200,52000"
st "txSend"
blo "47000,51800"
tm "WireNameMgr"
)
)
on &22
)
*107 (Wire
uid 1437,0
shape (OrthoPolyLine
uid 1438,0
va (VaSet
vasetType 3
)
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sat 32
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