DocumentHdrVersion "1.1" Header (DocumentHdr version 2 dialect 11 dmPackageRefs [ (DmPackageRef library "ieee" unitName "std_logic_1164" ) (DmPackageRef library "ieee" unitName "numeric_std" ) (DmPackageRef library "gates" unitName "gates" ) ] libraryRefs [ "ieee" "gates" ] ) version "32.1" appVersion "2019.2 (Build 5)" noEmbeddedEditors 1 model (BlockDiag VExpander (VariableExpander vvMap [ (vvPair variable "HDLDir" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hdl" ) (vvPair variable "HDSDir" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds" ) (vvPair variable "SideDataDesignDir" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\students@version.bd.info" ) (vvPair variable "SideDataUserDir" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\students@version.bd.user" ) (vvPair variable "SourceDir" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "studentsVersion" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit" ) (vvPair variable "d_logical" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit" ) (vvPair variable "date" value "03.11.2022" ) (vvPair variable "day" value "jeu." ) (vvPair variable "day_long" value "jeudi" ) (vvPair variable "dd" value "03" ) (vvPair variable "entity_name" value "controlUnit" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "students@version.bd" ) (vvPair variable "f_logical" value "studentsVersion.bd" ) (vvPair variable "f_noext" value "students@version" ) (vvPair variable "graphical_source_author" value "axel.amand" ) (vvPair variable "graphical_source_date" value "03.11.2022" ) (vvPair variable "graphical_source_group" value "UNKNOWN" ) (vvPair variable "graphical_source_host" value "WE7860" ) (vvPair variable "graphical_source_time" value "14:53:54" ) (vvPair variable "group" value "UNKNOWN" ) (vvPair variable "host" value "WE7860" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "HEIRV32_SC" ) (vvPair variable "library_downstream_Concatenation" value "$HDS_PROJECT_DIR/../Board/concat" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/SingleCycle/work" ) (vvPair variable "mm" value "11" ) (vvPair variable "module_name" value "controlUnit" ) (vvPair variable "month" value "nov." ) (vvPair variable "month_long" value "novembre" ) (vvPair variable "p" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\students@version.bd" ) (vvPair variable "p_logical" value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit\\studentsVersion.bd" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "this_ext" value "bd" ) (vvPair variable "this_file" value "students@version" ) (vvPair variable "this_file_logical" value "studentsVersion" ) (vvPair variable "time" value "14:53:54" ) (vvPair variable "unit" value "controlUnit" ) (vvPair variable "user" value "axel.amand" ) (vvPair variable "version" value "2019.2 (Build 5)" ) (vvPair variable "view" value "studentsVersion" ) (vvPair variable "year" value "2022" ) (vvPair variable "yy" value "22" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 228,0 optionalChildren [ *1 (PortIoIn uid 9,0 shape (CompositeShape uid 10,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 11,0 sl 0 ro 270 xt "1000,36625,2500,37375" ) (Line uid 12,0 sl 0 ro 270 xt "2500,37000,3000,37000" pts [ "2500,37000" "3000,37000" ] ) ] ) stc 0 sf 1 tg (WTG uid 13,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 14,0 va (VaSet ) xt "-3900,36400,0,37600" st "funct3" ju 2 blo "0,37400" tm "WireNameMgr" ) ) ) *2 (Net uid 21,0 lang 11 decl (Decl n "funct3" t "std_ulogic_vector" b "(2 DOWNTO 0)" o 1 suid 1,0 ) declText (MLText uid 22,0 va (VaSet font "Courier New,8,0" ) xt "22000,2400,45000,3200" st "funct3 : std_ulogic_vector(2 DOWNTO 0)" ) ) *3 (PortIoIn uid 23,0 shape (CompositeShape uid 24,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 25,0 sl 0 ro 270 xt "1000,40625,2500,41375" ) (Line uid 26,0 sl 0 ro 270 xt "2500,41000,3000,41000" pts [ "2500,41000" "3000,41000" ] ) ] ) stc 0 sf 1 tg (WTG uid 27,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 28,0 va (VaSet ) xt "-3900,40400,0,41600" st "funct7" ju 2 blo "0,41400" tm "WireNameMgr" ) ) ) *4 (Net uid 35,0 lang 11 decl (Decl n "funct7" t "std_ulogic" o 2 suid 2,0 ) declText (MLText uid 36,0 va (VaSet font "Courier New,8,0" ) xt "22000,3200,35000,4000" st "funct7 : std_ulogic" ) ) *5 (PortIoIn uid 37,0 shape (CompositeShape uid 38,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 39,0 sl 0 ro 270 xt "1000,44625,2500,45375" ) (Line uid 40,0 sl 0 ro 270 xt "2500,45000,3000,45000" pts [ "2500,45000" "3000,45000" ] ) ] ) stc 0 sf 1 tg (WTG uid 41,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 42,0 va (VaSet ) xt "-1900,44400,0,45600" st "op" ju 2 blo "0,45400" tm "WireNameMgr" ) ) ) *6 (Net uid 49,0 lang 11 decl (Decl n "op" t "std_ulogic_vector" b "(6 DOWNTO 0)" o 3 suid 3,0 ) declText (MLText uid 50,0 va (VaSet font "Courier New,8,0" ) xt "22000,4000,45000,4800" st "op : std_ulogic_vector(6 DOWNTO 0)" ) ) *7 (PortIoIn uid 51,0 shape (CompositeShape uid 52,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 53,0 sl 0 ro 270 xt "1000,48625,2500,49375" ) (Line uid 54,0 sl 0 ro 270 xt "2500,49000,3000,49000" pts [ "2500,49000" "3000,49000" ] ) ] ) stc 0 sf 1 tg (WTG uid 55,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 56,0 va (VaSet ) xt "-2800,48400,0,49600" st "zero" ju 2 blo "0,49400" tm "WireNameMgr" ) ) ) *8 (Net uid 63,0 lang 11 decl (Decl n "zero" t "std_ulogic" o 4 suid 4,0 ) declText (MLText uid 64,0 va (VaSet font "Courier New,8,0" ) xt "22000,4800,35000,5600" st "zero : std_ulogic" ) ) *9 (PortIoOut uid 65,0 shape (CompositeShape uid 66,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 67,0 sl 0 ro 270 xt "87500,31625,89000,32375" ) (Line uid 68,0 sl 0 ro 270 xt "87000,32000,87500,32000" pts [ "87000,32000" "87500,32000" ] ) ] ) stc 0 sf 1 tg (WTG uid 69,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 70,0 va (VaSet ) xt "90000,31400,97300,32600" st "ALUControl" blo "90000,32400" tm "WireNameMgr" ) ) ) *10 (Net uid 77,0 lang 11 decl (Decl n "ALUControl" t "std_ulogic_vector" b "(2 DOWNTO 0)" o 5 suid 5,0 ) declText (MLText uid 78,0 va (VaSet font "Courier New,8,0" ) xt "22000,5600,45000,6400" st "ALUControl : std_ulogic_vector(2 DOWNTO 0)" ) ) *11 (PortIoOut uid 79,0 shape (CompositeShape uid 80,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 81,0 sl 0 ro 270 xt "87500,35625,89000,36375" ) (Line uid 82,0 sl 0 ro 270 xt "87000,36000,87500,36000" pts [ "87000,36000" "87500,36000" ] ) ] ) stc 0 sf 1 tg (WTG uid 83,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 84,0 va (VaSet ) xt "90000,35400,94600,36600" st "ALUSrc" blo "90000,36400" tm "WireNameMgr" ) ) ) *12 (Net uid 91,0 lang 11 decl (Decl n "ALUSrc" t "std_uLogic" o 6 suid 6,0 ) declText (MLText uid 92,0 va (VaSet font "Courier New,8,0" ) xt "22000,6400,35000,7200" st "ALUSrc : std_uLogic" ) ) *13 (PortIoOut uid 93,0 shape (CompositeShape uid 94,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 95,0 sl 0 ro 270 xt "87500,39625,89000,40375" ) (Line uid 96,0 sl 0 ro 270 xt "87000,40000,87500,40000" pts [ "87000,40000" "87500,40000" ] ) ] ) stc 0 sf 1 tg (WTG uid 97,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 98,0 va (VaSet ) xt "90000,39400,93900,40600" st "PCSrc" blo "90000,40400" tm "WireNameMgr" ) ) ) *14 (Net uid 105,0 lang 11 decl (Decl n "PCSrc" t "std_uLogic" o 7 suid 7,0 ) declText (MLText uid 106,0 va (VaSet font "Courier New,8,0" ) xt "22000,7200,35000,8000" st "PCSrc : std_uLogic" ) ) *15 (PortIoOut uid 107,0 shape (CompositeShape uid 108,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 109,0 sl 0 ro 270 xt "87500,43625,89000,44375" ) (Line uid 110,0 sl 0 ro 270 xt "87000,44000,87500,44000" pts [ "87000,44000" "87500,44000" ] ) ] ) stc 0 sf 1 tg (WTG uid 111,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 112,0 va (VaSet ) xt "90000,43400,94500,44600" st "immSrc" blo "90000,44400" tm "WireNameMgr" ) ) ) *16 (Net uid 119,0 lang 11 decl (Decl n "immSrc" t "std_ulogic_vector" b "(1 DOWNTO 0)" o 8 suid 8,0 ) declText (MLText uid 120,0 va (VaSet font "Courier New,8,0" ) xt "22000,8000,45000,8800" st "immSrc : std_ulogic_vector(1 DOWNTO 0)" ) ) *17 (PortIoOut uid 121,0 shape (CompositeShape uid 122,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 123,0 sl 0 ro 270 xt "87500,47625,89000,48375" ) (Line uid 124,0 sl 0 ro 270 xt "87000,48000,87500,48000" pts [ "87000,48000" "87500,48000" ] ) ] ) stc 0 sf 1 tg (WTG uid 125,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 126,0 va (VaSet ) xt "90000,47400,95700,48600" st "memWrite" blo "90000,48400" tm "WireNameMgr" ) ) ) *18 (Net uid 133,0 lang 11 decl (Decl n "memWrite" t "std_ulogic" o 9 suid 9,0 ) declText (MLText uid 134,0 va (VaSet font "Courier New,8,0" ) xt "22000,8800,35000,9600" st "memWrite : std_ulogic" ) ) *19 (PortIoOut uid 135,0 shape (CompositeShape uid 136,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 137,0 sl 0 ro 270 xt "87500,51625,89000,52375" ) (Line uid 138,0 sl 0 ro 270 xt "87000,52000,87500,52000" pts [ "87000,52000" "87500,52000" ] ) ] ) stc 0 sf 1 tg (WTG uid 139,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 140,0 va (VaSet ) xt "90000,51400,94700,52600" st "regwrite" blo "90000,52400" tm "WireNameMgr" ) ) ) *20 (Net uid 147,0 lang 11 decl (Decl n "regwrite" t "std_ulogic" o 10 suid 10,0 ) declText (MLText uid 148,0 va (VaSet font "Courier New,8,0" ) xt "22000,9600,35000,10400" st "regwrite : std_ulogic" ) ) *21 (PortIoOut uid 149,0 shape (CompositeShape uid 150,0 va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon uid 151,0 sl 0 ro 270 xt "87500,55625,89000,56375" ) (Line uid 152,0 sl 0 ro 270 xt "87000,56000,87500,56000" pts [ "87000,56000" "87500,56000" ] ) ] ) stc 0 sf 1 tg (WTG uid 153,0 ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text uid 154,0 va (VaSet ) xt "90000,55400,95300,56600" st "resultSrc" blo "90000,56400" tm "WireNameMgr" ) ) ) *22 (Net uid 161,0 lang 11 decl (Decl n "resultSrc" t "std_ulogic_vector" b "(1 DOWNTO 0)" o 11 suid 11,0 ) declText (MLText uid 162,0 va (VaSet font "Courier New,8,0" ) xt "22000,10400,45000,11200" st "resultSrc : std_ulogic_vector(1 DOWNTO 0)" ) ) *23 (Grouping uid 185,0 optionalChildren [ *24 (CommentText uid 187,0 shape (Rectangle uid 188,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "57000,4000,74000,5000" ) oxt "18000,70000,35000,71000" text (MLText uid 189,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "57200,4000,68700,5000" st " by %user on %dd %month %year " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) *25 (CommentText uid 190,0 shape (Rectangle uid 191,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "74000,0,78000,1000" ) oxt "35000,66000,39000,67000" text (MLText uid 192,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "74200,0,77200,1000" st " Project: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *26 (CommentText uid 193,0 shape (Rectangle uid 194,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "57000,2000,74000,3000" ) oxt "18000,68000,35000,69000" text (MLText uid 195,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "57200,2000,67200,3000" st " " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) *27 (CommentText uid 196,0 shape (Rectangle uid 197,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,2000,57000,3000" ) oxt "14000,68000,18000,69000" text (MLText uid 198,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "53200,2000,55300,3000" st " Title: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *28 (CommentText uid 199,0 shape (Rectangle uid 200,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "74000,1000,94000,5000" ) oxt "35000,67000,55000,71000" text (MLText uid 201,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "74200,1200,83600,2200" st " " tm "CommentText" wrapOption 3 visibleHeight 4000 visibleWidth 20000 ) ignorePrefs 1 titleBlock 1 ) *29 (CommentText uid 202,0 shape (Rectangle uid 203,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "78000,0,94000,1000" ) oxt "39000,66000,55000,67000" text (MLText uid 204,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "78200,0,79800,1000" st " %project_name " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 16000 ) position 1 ignorePrefs 1 titleBlock 1 ) *30 (CommentText uid 205,0 shape (Rectangle uid 206,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,0,74000,2000" ) oxt "14000,66000,35000,68000" text (MLText uid 207,0 va (VaSet fg "32768,0,0" ) xt "58350,400,68650,1600" st " " ju 0 tm "CommentText" wrapOption 3 visibleHeight 2000 visibleWidth 21000 ) position 1 ignorePrefs 1 titleBlock 1 ) *31 (CommentText uid 208,0 shape (Rectangle uid 209,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,3000,57000,4000" ) oxt "14000,69000,18000,70000" text (MLText uid 210,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "53200,3000,55300,4000" st " Path: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *32 (CommentText uid 211,0 shape (Rectangle uid 212,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,4000,57000,5000" ) oxt "14000,70000,18000,71000" text (MLText uid 213,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "53200,4000,55900,5000" st " Edited: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *33 (CommentText uid 214,0 shape (Rectangle uid 215,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "57000,3000,74000,4000" ) oxt "18000,69000,35000,70000" text (MLText uid 216,0 va (VaSet fg "0,0,32768" bg "0,0,32768" font "Arial,8,0" ) xt "57200,3000,72600,4000" st " %library/%unit/%view " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) ] shape (GroupingShape uid 186,0 va (VaSet vasetType 1 fg "65535,65535,65535" lineStyle 2 lineWidth 2 ) xt "53000,0,94000,5000" ) oxt "14000,66000,55000,71000" ) *34 (Wire uid 15,0 shape (OrthoPolyLine uid 16,0 va (VaSet vasetType 3 lineWidth 2 ) xt "3000,37000,13000,37000" pts [ "3000,37000" "13000,37000" ] ) start &1 sat 32 eat 16 sty 1 st 0 sf 1 si 0 tg (WTG uid 19,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 20,0 va (VaSet isHidden 1 ) xt "5000,35800,13200,37000" st "funct3 : (2:0)" blo "5000,36800" tm "WireNameMgr" ) ) on &2 ) *35 (Wire uid 29,0 shape (OrthoPolyLine uid 30,0 va (VaSet vasetType 3 ) xt "3000,41000,13000,41000" pts [ "3000,41000" "13000,41000" ] ) start &3 sat 32 eat 16 st 0 sf 1 si 0 tg (WTG uid 33,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 34,0 va (VaSet isHidden 1 ) xt "5000,39800,8900,41000" st "funct7" blo "5000,40800" tm "WireNameMgr" ) ) on &4 ) *36 (Wire uid 43,0 shape (OrthoPolyLine uid 44,0 va (VaSet vasetType 3 lineWidth 2 ) xt "3000,45000,13000,45000" pts [ "3000,45000" "13000,45000" ] ) start &5 sat 32 eat 16 sty 1 st 0 sf 1 si 0 tg (WTG uid 47,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 48,0 va (VaSet isHidden 1 ) xt "5000,43800,11200,45000" st "op : (6:0)" blo "5000,44800" tm "WireNameMgr" ) ) on &6 ) *37 (Wire uid 57,0 shape (OrthoPolyLine uid 58,0 va (VaSet vasetType 3 ) xt "3000,49000,13000,49000" pts [ "3000,49000" "13000,49000" ] ) start &7 sat 32 eat 16 st 0 sf 1 si 0 tg (WTG uid 61,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 62,0 va (VaSet isHidden 1 ) xt "5000,47800,7800,49000" st "zero" blo "5000,48800" tm "WireNameMgr" ) ) on &8 ) *38 (Wire uid 71,0 shape (OrthoPolyLine uid 72,0 va (VaSet vasetType 3 lineWidth 2 ) xt "77000,32000,87000,32000" pts [ "87000,32000" "77000,32000" ] ) start &9 sat 32 eat 16 sty 1 st 0 sf 1 si 0 tg (WTG uid 75,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 76,0 va (VaSet isHidden 1 ) xt "86000,30800,96900,32000" st "ALUControl : (2:0)" blo "86000,31800" tm "WireNameMgr" ) ) on &10 ) *39 (Wire uid 85,0 shape (OrthoPolyLine uid 86,0 va (VaSet vasetType 3 ) xt "77000,36000,87000,36000" pts [ "87000,36000" "77000,36000" ] ) start &11 sat 32 eat 16 st 0 sf 1 si 0 tg (WTG uid 89,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 90,0 va (VaSet isHidden 1 ) xt "86000,34800,90600,36000" st "ALUSrc" blo "86000,35800" tm "WireNameMgr" ) ) on &12 ) *40 (Wire uid 99,0 shape (OrthoPolyLine uid 100,0 va (VaSet vasetType 3 ) xt "77000,40000,87000,40000" pts [ "87000,40000" "77000,40000" ] ) start &13 sat 32 eat 16 st 0 sf 1 si 0 tg (WTG uid 103,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 104,0 va (VaSet isHidden 1 ) xt "86000,38800,89900,40000" st "PCSrc" blo "86000,39800" tm "WireNameMgr" ) ) on &14 ) *41 (Wire uid 113,0 shape (OrthoPolyLine uid 114,0 va (VaSet vasetType 3 lineWidth 2 ) xt "77000,44000,87000,44000" pts [ "87000,44000" "77000,44000" ] ) start &15 sat 32 eat 16 sty 1 st 0 sf 1 si 0 tg (WTG uid 117,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 118,0 va (VaSet isHidden 1 ) xt "86000,42800,94800,44000" st "immSrc : (1:0)" blo "86000,43800" tm "WireNameMgr" ) ) on &16 ) *42 (Wire uid 127,0 shape (OrthoPolyLine uid 128,0 va (VaSet vasetType 3 ) xt "77000,48000,87000,48000" pts [ "87000,48000" "77000,48000" ] ) start &17 sat 32 eat 16 st 0 sf 1 si 0 tg (WTG uid 131,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 132,0 va (VaSet isHidden 1 ) xt "86000,46800,91700,48000" st "memWrite" blo "86000,47800" tm "WireNameMgr" ) ) on &18 ) *43 (Wire uid 141,0 shape (OrthoPolyLine uid 142,0 va (VaSet vasetType 3 ) xt "77000,52000,87000,52000" pts [ "87000,52000" "77000,52000" ] ) start &19 sat 32 eat 16 st 0 sf 1 si 0 tg (WTG uid 145,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 146,0 va (VaSet isHidden 1 ) xt "86000,50800,90700,52000" st "regwrite" blo "86000,51800" tm "WireNameMgr" ) ) on &20 ) *44 (Wire uid 155,0 shape (OrthoPolyLine uid 156,0 va (VaSet vasetType 3 lineWidth 2 ) xt "77000,56000,87000,56000" pts [ "87000,56000" "77000,56000" ] ) start &21 sat 32 eat 16 sty 1 st 0 sf 1 si 0 tg (WTG uid 159,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 160,0 va (VaSet isHidden 1 ) xt "86000,54800,95600,56000" st "resultSrc : (1:0)" blo "86000,55800" tm "WireNameMgr" ) ) on &22 ) ] bg "65535,65535,65535" grid (Grid origin "0,0" isVisible 0 isActive 1 xSpacing 1000 xySpacing 1000 xShown 1 yShown 1 color "26368,26368,26368" ) packageList *45 (PackageList uid 217,0 stg "VerticalLayoutStrategy" textVec [ *46 (Text uid 218,0 va (VaSet font "Verdana,9,1" ) xt "0,0,7600,1200" st "Package List" blo "0,1000" ) *47 (MLText uid 219,0 va (VaSet ) xt "0,1200,17500,7200" st "LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; LIBRARY gates; USE gates.gates.all;" tm "PackageList" ) ] ) compDirBlock (MlTextGroup uid 220,0 stg "VerticalLayoutStrategy" textVec [ *48 (Text uid 221,0 va (VaSet isHidden 1 font "Verdana,9,1" ) xt "20000,0,30800,1200" st "Compiler Directives" blo "20000,1000" ) *49 (Text uid 222,0 va (VaSet isHidden 1 font "Verdana,9,1" ) xt "20000,1200,33100,2400" st "Pre-module directives:" blo "20000,2200" ) *50 (MLText uid 223,0 va (VaSet isHidden 1 ) xt "20000,2400,32100,4800" st "`resetall `timescale 1ns/10ps" tm "BdCompilerDirectivesTextMgr" ) *51 (Text uid 224,0 va (VaSet isHidden 1 font "Verdana,9,1" ) xt "20000,4800,33700,6000" st "Post-module directives:" blo "20000,5800" ) *52 (MLText uid 225,0 va (VaSet isHidden 1 ) xt "20000,0,20000,0" tm "BdCompilerDirectivesTextMgr" ) *53 (Text uid 226,0 va (VaSet isHidden 1 font "Verdana,9,1" ) xt "20000,6000,33200,7200" st "End-module directives:" blo "20000,7000" ) *54 (MLText uid 227,0 va (VaSet isHidden 1 ) xt "20000,7200,20000,7200" tm "BdCompilerDirectivesTextMgr" ) ] associable 1 ) windowSize "-8,-8,1928,1048" viewArea "-5384,-1609,105872,58839" cachedDiagramExtent "-3900,0,97300,56600" pageSetupInfo (PageSetupInfo ptrCmd "" toPrinter 1 xMargin 49 yMargin 49 paperWidth 761 paperHeight 1077 windowsPaperWidth 761 windowsPaperHeight 1077 paperType "A4 (210 x 297 mm)" windowsPaperName "A4 (210 x 297 mm)" windowsPaperType 9 useAdjustTo 0 exportedDirectories [ "$HDS_PROJECT_DIR/HTMLExport" ] boundaryWidth 0 exportStdIncludeRefs 1 exportStdPackageRefs 1 ) hasePageBreakOrigin 1 pageBreakOrigin "-7000,0" lastUid 284,0 defaultCommentText (CommentText shape (Rectangle layer 0 va (VaSet vasetType 1 fg "65280,65280,46080" lineColor "0,0,32768" ) xt "0,0,15000,5000" ) text (MLText va (VaSet fg "0,0,32768" ) xt "200,200,3200,1400" st " Text " tm "CommentText" wrapOption 3 visibleHeight 4600 visibleWidth 14600 ) ) defaultRequirementText (RequirementText shape (ZoomableIcon layer 0 va (VaSet vasetType 1 fg "59904,39936,65280" lineColor "0,0,32768" ) xt "0,0,1500,1750" iconName "reqTracerRequirement.bmp" iconMaskName "reqTracerRequirement.msk" ) autoResize 1 text (MLText va (VaSet fg "0,0,32768" font "arial,8,0" ) xt "500,2150,1400,3150" st " Text " tm "RequirementText" wrapOption 3 visibleHeight 1350 visibleWidth 1100 ) ) defaultPanel (Panel shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "32768,0,0" lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (Text va (VaSet font "Verdana,9,1" ) xt "1000,1000,5000,2200" st "Panel0" blo "1000,2000" tm "PanelText" ) ) ) defaultBlk (Blk shape (Rectangle va (VaSet vasetType 1 fg "39936,56832,65280" lineColor "0,0,32768" lineWidth 2 ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *55 (Text va (VaSet font "Verdana,9,1" ) xt "1300,3200,6700,4400" st "" blo "1300,4200" tm "BdLibraryNameMgr" ) *56 (Text va (VaSet font "Verdana,9,1" ) xt "1300,4400,6100,5600" st "" blo "1300,5400" tm "BlkNameMgr" ) *57 (Text va (VaSet font "Verdana,9,1" ) xt "1300,5600,3800,6800" st "U_0" blo "1300,6600" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet font "Courier New,8,0" ) xt "1300,13200,1300,13200" ) header "" ) elements [ ] ) viewicon (ZoomableIcon sl 0 va (VaSet vasetType 1 fg "49152,49152,49152" ) xt "0,0,1500,1500" iconName "UnknownFile.png" iconMaskName "UnknownFile.msk" ) viewiconposition 0 ) defaultMWComponent (MWC shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "-850,0,8850,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *58 (Text va (VaSet font "Verdana,9,1" ) xt "-350,3200,3750,4400" st "Library" blo "-350,4200" ) *59 (Text va (VaSet font "Verdana,9,1" ) xt "-350,4400,8350,5600" st "MWComponent" blo "-350,5400" ) *60 (Text va (VaSet font "Verdana,9,1" ) xt "-350,5600,2150,6800" st "U_0" blo "-350,6600" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet font "Courier New,8,0" ) xt "-7350,1200,-7350,1200" ) header "" ) elements [ ] ) portVis (PortSigDisplay ) prms (Property pclass "params" pname "params" ptn "String" ) visOptions (mwParamsVisibilityOptions ) ) defaultSaComponent (SaComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *61 (Text va (VaSet font "Verdana,9,1" ) xt "0,3200,4100,4400" st "Library" blo "0,4200" tm "BdLibraryNameMgr" ) *62 (Text va (VaSet font "Verdana,9,1" ) xt "0,4400,8000,5600" st "SaComponent" blo "0,5400" tm "CptNameMgr" ) *63 (Text va (VaSet font "Verdana,9,1" ) xt "0,5600,2500,6800" st "U_0" blo "0,6600" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet font "Courier New,8,0" ) xt "-7000,1200,-7000,1200" ) header "" ) elements [ ] ) viewicon (ZoomableIcon sl 0 va (VaSet vasetType 1 fg "49152,49152,49152" ) xt "0,0,1500,1500" iconName "UnknownFile.png" iconMaskName "UnknownFile.msk" ) viewiconposition 0 portVis (PortSigDisplay ) archFileType "UNKNOWN" ) defaultVhdlComponent (VhdlComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "-1000,0,9000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *64 (Text va (VaSet font "Verdana,9,1" ) xt "-500,3200,3600,4400" st "Library" blo "-500,4200" ) *65 (Text va (VaSet font "Verdana,9,1" ) xt "-500,4400,8500,5600" st "VhdlComponent" blo "-500,5400" ) *66 (Text va (VaSet font "Verdana,9,1" ) xt "-500,5600,2000,6800" st "U_0" blo "-500,6600" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet font "Courier New,8,0" ) xt "-7500,1200,-7500,1200" ) header "" ) elements [ ] ) portVis (PortSigDisplay ) entityPath "" archName "" archPath "" ) defaultVerilogComponent (VerilogComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "-1650,0,9650,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *67 (Text va (VaSet font "Verdana,9,1" ) xt "-1150,3200,2950,4400" st "Library" blo "-1150,4200" ) *68 (Text va (VaSet font "Verdana,9,1" ) xt "-1150,4400,9150,5600" st "VerilogComponent" blo "-1150,5400" ) *69 (Text va (VaSet font "Verdana,9,1" ) xt "-1150,5600,1350,6800" st "U_0" blo "-1150,6600" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet font "Courier New,8,0" ) xt "-8150,1200,-8150,1200" ) header "" ) elements [ ] ) entityPath "" ) defaultHdlText (HdlText shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,37120" lineColor "0,0,32768" lineWidth 2 ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *70 (Text va (VaSet font "Verdana,9,1" ) xt "2800,3800,5200,5000" st "eb1" blo "2800,4800" tm "HdlTextNameMgr" ) *71 (Text va (VaSet font "Verdana,9,1" ) xt "2800,5000,4000,6200" st "1" blo "2800,6000" tm "HdlTextNumberMgr" ) ] ) viewicon (ZoomableIcon sl 0 va (VaSet vasetType 1 fg "49152,49152,49152" ) xt "0,0,1500,1500" iconName "UnknownFile.png" iconMaskName "UnknownFile.msk" ) viewiconposition 0 ) defaultEmbeddedText (EmbeddedText commentText (CommentText ps "CenterOffsetStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "0,0,32768" lineWidth 2 ) xt "0,0,18000,5000" ) text (MLText va (VaSet ) xt "200,200,3200,1400" st " Text " tm "HdlTextMgr" wrapOption 3 visibleHeight 4600 visibleWidth 17600 ) ) ) defaultGlobalConnector (GlobalConnector shape (Circle va (VaSet vasetType 1 fg "65535,65535,0" ) xt "-1000,-1000,1000,1000" radius 1000 ) name (Text va (VaSet font "Verdana,9,1" ) xt "-650,-600,650,600" st "G" blo "-650,400" ) ) defaultRipper (Ripper ps "OnConnectorStrategy" shape (Line2D pts [ "0,0" "1000,1000" ] va (VaSet vasetType 1 ) xt "0,0,1000,1000" ) ) defaultBdJunction (BdJunction ps "OnConnectorStrategy" shape (Circle va (VaSet vasetType 1 ) xt "-400,-400,400,400" radius 400 ) ) defaultPortIoIn (PortIoIn shape (CompositeShape va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon sl 0 ro 270 xt "-2000,-375,-500,375" ) (Line sl 0 ro 270 xt "-500,0,0,0" pts [ "-500,0" "0,0" ] ) ] ) stc 0 sf 1 tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet ) xt "-1375,-1000,-1375,-1000" ju 2 blo "-1375,-1000" tm "WireNameMgr" ) ) ) defaultPortIoOut (PortIoOut shape (CompositeShape va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon sl 0 ro 270 xt "500,-375,2000,375" ) (Line sl 0 ro 270 xt "0,0,500,0" pts [ "0,0" "500,0" ] ) ] ) stc 0 sf 1 tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet ) xt "625,-1000,625,-1000" blo "625,-1000" tm "WireNameMgr" ) ) ) defaultPortIoInOut (PortIoInOut shape (CompositeShape va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Hexagon sl 0 xt "500,-375,2000,375" ) (Line sl 0 xt "0,0,500,0" pts [ "0,0" "500,0" ] ) ] ) stc 0 sf 1 tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet ) xt "0,-375,0,-375" blo "0,-375" tm "WireNameMgr" ) ) ) defaultPortIoBuffer (PortIoBuffer shape (CompositeShape va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "0,0,32768" ) optionalChildren [ (Hexagon sl 0 xt "500,-375,2000,375" ) (Line sl 0 xt "0,0,500,0" pts [ "0,0" "500,0" ] ) ] ) stc 0 sf 1 tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet ) xt "0,-375,0,-375" blo "0,-375" tm "WireNameMgr" ) ) ) defaultSignal (Wire shape (OrthoPolyLine va (VaSet vasetType 3 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 st 0 sf 1 si 0 tg (WTG ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet ) xt "0,0,2900,1200" st "sig0" blo "0,1000" tm "WireNameMgr" ) ) ) defaultBus (Wire shape (OrthoPolyLine va (VaSet vasetType 3 lineWidth 2 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 sty 1 st 0 sf 1 si 0 tg (WTG ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet ) xt "0,0,3800,1200" st "dbus0" blo "0,1000" tm "WireNameMgr" ) ) ) defaultBundle (Bundle shape (OrthoPolyLine va (VaSet vasetType 3 lineColor "32768,0,0" lineWidth 2 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 textGroup (BiTextGroup ps "ConnStartEndStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet ) xt "0,0,4700,1200" st "bundle0" blo "0,1000" tm "BundleNameMgr" ) second (MLText va (VaSet ) xt "0,1200,1500,2400" st "()" tm "BundleContentsMgr" ) ) bundleNet &0 ) defaultPortMapFrame (PortMapFrame ps "PortMapFrameStrategy" shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "0,0,32768" lineWidth 2 ) xt "0,0,10000,12000" ) portMapText (BiTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" first (MLText va (VaSet ) ) second (MLText va (VaSet ) tm "PortMapTextMgr" ) ) ) defaultGenFrame (Frame shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "26368,26368,26368" lineStyle 2 lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (MLText va (VaSet ) xt "0,-1300,18500,-100" st "g0: FOR i IN 0 TO n GENERATE" tm "FrameTitleTextMgr" ) ) seqNum (FrameSequenceNumber ps "TopLeftStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "50,50,1850,1650" ) num (Text va (VaSet ) xt "250,250,1650,1450" st "1" blo "250,1250" tm "FrameSeqNumMgr" ) ) decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *72 (Text va (VaSet font "Verdana,9,1" ) xt "11200,20000,22000,21200" st "Frame Declarations" blo "11200,21000" ) *73 (MLText va (VaSet ) xt "11200,21200,11200,21200" tm "BdFrameDeclTextMgr" ) ] ) ) defaultBlockFrame (Frame shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "26368,26368,26368" lineStyle 1 lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (MLText va (VaSet ) xt "0,-1300,11000,-100" st "b0: BLOCK (guard)" tm "FrameTitleTextMgr" ) ) seqNum (FrameSequenceNumber ps "TopLeftStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "50,50,1850,1650" ) num (Text va (VaSet ) xt "250,250,1650,1450" st "1" blo "250,1250" tm "FrameSeqNumMgr" ) ) decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *74 (Text va (VaSet font "Verdana,9,1" ) xt "11200,20000,22000,21200" st "Frame Declarations" blo "11200,21000" ) *75 (MLText va (VaSet ) xt "11200,21200,11200,21200" tm "BdFrameDeclTextMgr" ) ] ) style 3 ) defaultSaCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,2800,1950" st "Port" blo "0,1750" ) ) thePort (LogicalPort lang 11 decl (Decl n "Port" t "" o 0 ) ) ) defaultSaCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,2800,1950" st "Port" blo "0,1750" ) ) thePort (LogicalPort lang 11 m 3 decl (Decl n "Port" t "" o 0 ) ) ) defaultDeclText (MLText va (VaSet font "Courier New,8,0" ) ) archDeclarativeBlock (BdArchDeclBlock uid 1,0 stg "BdArchDeclBlockLS" declLabel (Text uid 2,0 va (VaSet font "Verdana,9,1" ) xt "20000,0,27400,1200" st "Declarations" blo "20000,1000" ) portLabel (Text uid 3,0 va (VaSet font "Verdana,9,1" ) xt "20000,1200,23700,2400" st "Ports:" blo "20000,2200" ) preUserLabel (Text uid 4,0 va (VaSet isHidden 1 font "Verdana,9,1" ) xt "20000,0,25200,1200" st "Pre User:" blo "20000,1000" ) preUserText (MLText uid 5,0 va (VaSet isHidden 1 font "Courier New,8,0" ) xt "20000,0,20000,0" tm "BdDeclarativeTextMgr" ) diagSignalLabel (Text uid 6,0 va (VaSet font "Verdana,9,1" ) xt "20000,11200,29500,12400" st "Diagram Signals:" blo "20000,12200" ) postUserLabel (Text uid 7,0 va (VaSet isHidden 1 font "Verdana,9,1" ) xt "20000,0,26400,1200" st "Post User:" blo "20000,1000" ) postUserText (MLText uid 8,0 va (VaSet isHidden 1 font "Courier New,8,0" ) xt "20000,0,20000,0" tm "BdDeclarativeTextMgr" ) ) commonDM (CommonDM ldm (LogicalDM suid 11,0 usingSuid 1 emptyRow *76 (LEmptyRow ) uid 230,0 optionalChildren [ *77 (RefLabelRowHdr ) *78 (TitleRowHdr ) *79 (FilterRowHdr ) *80 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *81 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *82 (GroupColHdr tm "GroupColHdrMgr" ) *83 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) *84 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) *85 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) *86 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) *87 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) *88 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) *89 (LeafLogPort port (LogicalPort lang 11 decl (Decl n "funct3" t "std_ulogic_vector" b "(2 DOWNTO 0)" o 1 suid 1,0 ) ) uid 163,0 ) *90 (LeafLogPort port (LogicalPort lang 11 decl (Decl n "funct7" t "std_ulogic" o 2 suid 2,0 ) ) uid 165,0 ) *91 (LeafLogPort port (LogicalPort lang 11 decl (Decl n "op" t "std_ulogic_vector" b "(6 DOWNTO 0)" o 3 suid 3,0 ) ) uid 167,0 ) *92 (LeafLogPort port (LogicalPort lang 11 decl (Decl n "zero" t "std_ulogic" o 4 suid 4,0 ) ) uid 169,0 ) *93 (LeafLogPort port (LogicalPort lang 11 m 1 decl (Decl n "ALUControl" t "std_ulogic_vector" b "(2 DOWNTO 0)" o 5 suid 5,0 ) ) uid 171,0 ) *94 (LeafLogPort port (LogicalPort lang 11 m 1 decl (Decl n "ALUSrc" t "std_uLogic" o 6 suid 6,0 ) ) uid 173,0 ) *95 (LeafLogPort port (LogicalPort lang 11 m 1 decl (Decl n "PCSrc" t "std_uLogic" o 7 suid 7,0 ) ) uid 175,0 ) *96 (LeafLogPort port (LogicalPort lang 11 m 1 decl (Decl n "immSrc" t "std_ulogic_vector" b "(1 DOWNTO 0)" o 8 suid 8,0 ) ) uid 177,0 ) *97 (LeafLogPort port (LogicalPort lang 11 m 1 decl (Decl n "memWrite" t "std_ulogic" o 9 suid 9,0 ) ) uid 179,0 ) *98 (LeafLogPort port (LogicalPort lang 11 m 1 decl (Decl n "regwrite" t "std_ulogic" o 10 suid 10,0 ) ) uid 181,0 ) *99 (LeafLogPort port (LogicalPort lang 11 m 1 decl (Decl n "resultSrc" t "std_ulogic_vector" b "(1 DOWNTO 0)" o 11 suid 11,0 ) ) uid 183,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 243,0 optionalChildren [ *100 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *101 (MRCItem litem &76 pos 11 dimension 20 ) uid 245,0 optionalChildren [ *102 (MRCItem litem &77 pos 0 dimension 20 uid 246,0 ) *103 (MRCItem litem &78 pos 1 dimension 23 uid 247,0 ) *104 (MRCItem litem &79 pos 2 hidden 1 dimension 20 uid 248,0 ) *105 (MRCItem litem &89 pos 0 dimension 20 uid 164,0 ) *106 (MRCItem litem &90 pos 1 dimension 20 uid 166,0 ) *107 (MRCItem litem &91 pos 2 dimension 20 uid 168,0 ) *108 (MRCItem litem &92 pos 3 dimension 20 uid 170,0 ) *109 (MRCItem litem &93 pos 4 dimension 20 uid 172,0 ) *110 (MRCItem litem &94 pos 5 dimension 20 uid 174,0 ) *111 (MRCItem litem &95 pos 6 dimension 20 uid 176,0 ) *112 (MRCItem litem &96 pos 7 dimension 20 uid 178,0 ) *113 (MRCItem litem &97 pos 8 dimension 20 uid 180,0 ) *114 (MRCItem litem &98 pos 9 dimension 20 uid 182,0 ) *115 (MRCItem litem &99 pos 10 dimension 20 uid 184,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 249,0 optionalChildren [ *116 (MRCItem litem &80 pos 0 dimension 20 uid 250,0 ) *117 (MRCItem litem &82 pos 1 dimension 50 uid 251,0 ) *118 (MRCItem litem &83 pos 2 dimension 100 uid 252,0 ) *119 (MRCItem litem &84 pos 3 dimension 50 uid 253,0 ) *120 (MRCItem litem &85 pos 4 dimension 100 uid 254,0 ) *121 (MRCItem litem &86 pos 5 dimension 100 uid 255,0 ) *122 (MRCItem litem &87 pos 6 dimension 50 uid 256,0 ) *123 (MRCItem litem &88 pos 7 dimension 80 uid 257,0 ) ] ) fixedCol 4 fixedRow 2 name "Ports" uid 244,0 vaOverrides [ ] ) ] ) uid 229,0 ) genericsCommonDM (CommonDM ldm (LogicalDM emptyRow *124 (LEmptyRow ) uid 259,0 optionalChildren [ *125 (RefLabelRowHdr ) *126 (TitleRowHdr ) *127 (FilterRowHdr ) *128 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *129 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *130 (GroupColHdr tm "GroupColHdrMgr" ) *131 (NameColHdr tm "GenericNameColHdrMgr" ) *132 (TypeColHdr tm "GenericTypeColHdrMgr" ) *133 (InitColHdr tm "GenericValueColHdrMgr" ) *134 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) *135 (EolColHdr tm "GenericEolColHdrMgr" ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 271,0 optionalChildren [ *136 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *137 (MRCItem litem &124 pos 0 dimension 20 ) uid 273,0 optionalChildren [ *138 (MRCItem litem &125 pos 0 dimension 20 uid 274,0 ) *139 (MRCItem litem &126 pos 1 dimension 23 uid 275,0 ) *140 (MRCItem litem &127 pos 2 hidden 1 dimension 20 uid 276,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 277,0 optionalChildren [ *141 (MRCItem litem &128 pos 0 dimension 20 uid 278,0 ) *142 (MRCItem litem &130 pos 1 dimension 50 uid 279,0 ) *143 (MRCItem litem &131 pos 2 dimension 100 uid 280,0 ) *144 (MRCItem litem &132 pos 3 dimension 100 uid 281,0 ) *145 (MRCItem litem &133 pos 4 dimension 50 uid 282,0 ) *146 (MRCItem litem &134 pos 5 dimension 50 uid 283,0 ) *147 (MRCItem litem &135 pos 6 dimension 80 uid 284,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 272,0 vaOverrides [ ] ) ] ) uid 258,0 type 1 ) activeModelName "BlockDiag" )