DocumentHdrVersion "1.1" Header (DocumentHdr version 2 dialect 11 dmPackageRefs [ (DmPackageRef library "ieee" unitName "std_logic_1164" ) (DmPackageRef library "ieee" unitName "numeric_std" ) ] libraryRefs [ "ieee" ] ) version "26.1" appVersion "2018.1 (Build 12)" model (Symbol commonDM (CommonDM ldm (LogicalDM suid 32,0 usingSuid 1 emptyRow *1 (LEmptyRow ) uid 77,0 optionalChildren [ *2 (RefLabelRowHdr ) *3 (TitleRowHdr ) *4 (FilterRowHdr ) *5 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *6 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *7 (GroupColHdr tm "GroupColHdrMgr" ) *8 (NameColHdr tm "NameColHdrMgr" ) *9 (ModeColHdr tm "ModeColHdrMgr" ) *10 (TypeColHdr tm "TypeColHdrMgr" ) *11 (BoundsColHdr tm "BoundsColHdrMgr" ) *12 (InitColHdr tm "InitColHdrMgr" ) *13 (EolColHdr tm "EolColHdrMgr" ) *14 (LogPort port (LogicalPort m 1 decl (Decl n "clock" t "std_ulogic" o 1 suid 25,0 ) ) uid 403,0 ) *15 (LogPort port (LogicalPort m 1 decl (Decl n "dataIn" t "std_ulogic_vector" b "(dataBitNb-1 DOWNTO 0)" o 2 suid 26,0 ) ) uid 405,0 ) *16 (LogPort port (LogicalPort decl (Decl n "dataOut" t "std_ulogic_vector" b "(dataBitNb-1 DOWNTO 0)" o 3 suid 27,0 ) ) uid 407,0 ) *17 (LogPort port (LogicalPort decl (Decl n "empty" t "std_ulogic" o 4 suid 28,0 ) ) uid 409,0 ) *18 (LogPort port (LogicalPort decl (Decl n "full" t "std_ulogic" o 5 suid 29,0 ) ) uid 411,0 ) *19 (LogPort port (LogicalPort m 1 decl (Decl n "read" t "std_ulogic" o 6 suid 30,0 ) ) uid 413,0 ) *20 (LogPort port (LogicalPort m 1 decl (Decl n "reset" t "std_ulogic" o 7 suid 31,0 ) ) uid 415,0 ) *21 (LogPort port (LogicalPort m 1 decl (Decl n "write" t "std_ulogic" o 8 suid 32,0 ) ) uid 417,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 90,0 optionalChildren [ *22 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "courier,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "courier,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "courier,10,0" ) emptyMRCItem *23 (MRCItem litem &1 pos 8 dimension 20 ) uid 92,0 optionalChildren [ *24 (MRCItem litem &2 pos 0 dimension 20 uid 93,0 ) *25 (MRCItem litem &3 pos 1 dimension 23 uid 94,0 ) *26 (MRCItem litem &4 pos 2 hidden 1 dimension 20 uid 95,0 ) *27 (MRCItem litem &14 pos 0 dimension 20 uid 404,0 ) *28 (MRCItem litem &15 pos 1 dimension 20 uid 406,0 ) *29 (MRCItem litem &16 pos 2 dimension 20 uid 408,0 ) *30 (MRCItem litem &17 pos 3 dimension 20 uid 410,0 ) *31 (MRCItem litem &18 pos 4 dimension 20 uid 412,0 ) *32 (MRCItem litem &19 pos 5 dimension 20 uid 414,0 ) *33 (MRCItem litem &20 pos 6 dimension 20 uid 416,0 ) *34 (MRCItem litem &21 pos 7 dimension 20 uid 418,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "courier,10,0" textAngle 90 ) uid 96,0 optionalChildren [ *35 (MRCItem litem &5 pos 0 dimension 20 uid 97,0 ) *36 (MRCItem litem &7 pos 1 dimension 50 uid 98,0 ) *37 (MRCItem litem &8 pos 2 dimension 100 uid 99,0 ) *38 (MRCItem litem &9 pos 3 dimension 50 uid 100,0 ) *39 (MRCItem litem &10 pos 4 dimension 100 uid 101,0 ) *40 (MRCItem litem &11 pos 5 dimension 100 uid 102,0 ) *41 (MRCItem litem &12 pos 6 dimension 50 uid 103,0 ) *42 (MRCItem litem &13 pos 7 dimension 80 uid 104,0 ) ] ) fixedCol 4 fixedRow 2 name "Ports" uid 91,0 vaOverrides [ ] ) ] ) uid 76,0 ) genericsCommonDM (CommonDM ldm (LogicalDM emptyRow *43 (LEmptyRow ) uid 106,0 optionalChildren [ *44 (RefLabelRowHdr ) *45 (TitleRowHdr ) *46 (FilterRowHdr ) *47 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *48 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *49 (GroupColHdr tm "GroupColHdrMgr" ) *50 (NameColHdr tm "GenericNameColHdrMgr" ) *51 (TypeColHdr tm "GenericTypeColHdrMgr" ) *52 (InitColHdr tm "GenericValueColHdrMgr" ) *53 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) *54 (EolColHdr tm "GenericEolColHdrMgr" ) *55 (LogGeneric generic (GiElement name "dataBitNb" type "positive" value "8" ) uid 155,0 ) *56 (LogGeneric generic (GiElement name "fifoDepth" type "positive" value "64" ) uid 157,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 118,0 optionalChildren [ *57 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "courier,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "courier,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "courier,10,0" ) emptyMRCItem *58 (MRCItem litem &43 pos 2 dimension 20 ) uid 120,0 optionalChildren [ *59 (MRCItem litem &44 pos 0 dimension 20 uid 121,0 ) *60 (MRCItem litem &45 pos 1 dimension 23 uid 122,0 ) *61 (MRCItem litem &46 pos 2 hidden 1 dimension 20 uid 123,0 ) *62 (MRCItem litem &55 pos 0 dimension 20 uid 156,0 ) *63 (MRCItem litem &56 pos 1 dimension 20 uid 158,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "courier,10,0" textAngle 90 ) uid 124,0 optionalChildren [ *64 (MRCItem litem &47 pos 0 dimension 20 uid 125,0 ) *65 (MRCItem litem &49 pos 1 dimension 50 uid 126,0 ) *66 (MRCItem litem &50 pos 2 dimension 100 uid 127,0 ) *67 (MRCItem litem &51 pos 3 dimension 100 uid 128,0 ) *68 (MRCItem litem &52 pos 4 dimension 50 uid 129,0 ) *69 (MRCItem litem &53 pos 5 dimension 50 uid 130,0 ) *70 (MRCItem litem &54 pos 6 dimension 80 uid 131,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 119,0 vaOverrides [ ] ) ] ) uid 105,0 type 1 ) VExpander (VariableExpander vvMap [ (vvPair variable " " value " " ) (vvPair variable "HDLDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl" ) (vvPair variable "HDSDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds" ) (vvPair variable "SideDataDesignDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface.info" ) (vvPair variable "SideDataUserDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface.user" ) (vvPair variable "SourceDir" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "interface" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester" ) (vvPair variable "d_logical" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester" ) (vvPair variable "date" value "08/28/19" ) (vvPair variable "day" value "Wed" ) (vvPair variable "day_long" value "Wednesday" ) (vvPair variable "dd" value "28" ) (vvPair variable "designName" value "$DESIGN_NAME" ) (vvPair variable "entity_name" value "fifo_tester" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "interface" ) (vvPair variable "f_logical" value "interface" ) (vvPair variable "f_noext" value "interface" ) (vvPair variable "graphical_source_author" value "francois" ) (vvPair variable "graphical_source_date" value "08/28/19" ) (vvPair variable "graphical_source_group" value "francois" ) (vvPair variable "graphical_source_host" value "Aphelia" ) (vvPair variable "graphical_source_time" value "13:45:28" ) (vvPair variable "group" value "francois" ) (vvPair variable "host" value "Aphelia" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "Memory_test" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/Libs/Memory_test/work" ) (vvPair variable "mm" value "08" ) (vvPair variable "module_name" value "fifo_tester" ) (vvPair variable "month" value "Aug" ) (vvPair variable "month_long" value "August" ) (vvPair variable "p" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface" ) (vvPair variable "p_logical" value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/fifo_tester/interface" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_ActelPath" value "$ACTEL_HOME" ) (vvPair variable "task_ActelProjectPath" value "$SCRATCH_DIR\\$DESIGN_NAME\\$ACTEL_WORK_DIR" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME\\win32" ) (vvPair variable "this_ext" value "" ) (vvPair variable "this_file" value "interface" ) (vvPair variable "this_file_logical" value "interface" ) (vvPair variable "time" value "13:45:28" ) (vvPair variable "unit" value "fifo_tester" ) (vvPair variable "user" value "francois" ) (vvPair variable "version" value "2018.1 (Build 12)" ) (vvPair variable "view" value "interface" ) (vvPair variable "year" value "2019" ) (vvPair variable "yy" value "19" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 75,0 optionalChildren [ *71 (SymbolBody uid 8,0 optionalChildren [ *72 (CptPort uid 363,0 ps "OnEdgeStrategy" shape (Triangle uid 364,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "30625,5250,31375,6000" ) tg (CPTG uid 365,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 366,0 ro 270 va (VaSet font "courier,8,0" ) xt "30550,7000,31450,9500" st "clock" ju 2 blo "31250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 367,0 va (VaSet font "courier,8,0" ) xt "44000,4700,59500,5600" st "clock : OUT std_ulogic ; " ) thePort (LogicalPort m 1 decl (Decl n "clock" t "std_ulogic" o 1 suid 25,0 ) ) ) *73 (CptPort uid 368,0 ps "OnEdgeStrategy" shape (Triangle uid 369,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "22625,5250,23375,6000" ) tg (CPTG uid 370,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 371,0 ro 270 va (VaSet font "courier,8,0" ) xt "22550,7000,23450,10000" st "dataIn" ju 2 blo "23250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 372,0 va (VaSet font "courier,8,0" ) xt "44000,5600,74000,6500" st "dataIn : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ; " ) thePort (LogicalPort m 1 decl (Decl n "dataIn" t "std_ulogic_vector" b "(dataBitNb-1 DOWNTO 0)" o 2 suid 26,0 ) ) ) *74 (CptPort uid 373,0 ps "OnEdgeStrategy" shape (Triangle uid 374,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "58625,5250,59375,6000" ) tg (CPTG uid 375,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 376,0 ro 270 va (VaSet font "courier,8,0" ) xt "58550,7000,59450,10500" st "dataOut" ju 2 blo "59250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 377,0 va (VaSet font "courier,8,0" ) xt "44000,2000,74000,2900" st "dataOut : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0) ; " ) thePort (LogicalPort decl (Decl n "dataOut" t "std_ulogic_vector" b "(dataBitNb-1 DOWNTO 0)" o 3 suid 27,0 ) ) ) *75 (CptPort uid 378,0 ps "OnEdgeStrategy" shape (Triangle uid 379,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "56625,5250,57375,6000" ) tg (CPTG uid 380,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 381,0 ro 270 va (VaSet font "courier,8,0" ) xt "56550,7000,57450,9500" st "empty" ju 2 blo "57250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 382,0 va (VaSet font "courier,8,0" ) xt "44000,2900,59500,3800" st "empty : IN std_ulogic ; " ) thePort (LogicalPort decl (Decl n "empty" t "std_ulogic" o 4 suid 28,0 ) ) ) *76 (CptPort uid 383,0 ps "OnEdgeStrategy" shape (Triangle uid 384,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "24625,5250,25375,6000" ) tg (CPTG uid 385,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 386,0 ro 270 va (VaSet font "courier,8,0" ) xt "24550,7000,25450,9000" st "full" ju 2 blo "25250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 387,0 va (VaSet font "courier,8,0" ) xt "44000,3800,59500,4700" st "full : IN std_ulogic ; " ) thePort (LogicalPort decl (Decl n "full" t "std_ulogic" o 5 suid 29,0 ) ) ) *77 (CptPort uid 388,0 ps "OnEdgeStrategy" shape (Triangle uid 389,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "54625,5250,55375,6000" ) tg (CPTG uid 390,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 391,0 ro 270 va (VaSet font "courier,8,0" ) xt "54550,7000,55450,9000" st "read" ju 2 blo "55250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 392,0 va (VaSet font "courier,8,0" ) xt "44000,6500,59500,7400" st "read : OUT std_ulogic ; " ) thePort (LogicalPort m 1 decl (Decl n "read" t "std_ulogic" o 6 suid 30,0 ) ) ) *78 (CptPort uid 393,0 ps "OnEdgeStrategy" shape (Triangle uid 394,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "32625,5250,33375,6000" ) tg (CPTG uid 395,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 396,0 ro 270 va (VaSet font "courier,8,0" ) xt "32550,7000,33450,9500" st "reset" ju 2 blo "33250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 397,0 va (VaSet font "courier,8,0" ) xt "44000,7400,59500,8300" st "reset : OUT std_ulogic ; " ) thePort (LogicalPort m 1 decl (Decl n "reset" t "std_ulogic" o 7 suid 31,0 ) ) ) *79 (CptPort uid 398,0 ps "OnEdgeStrategy" shape (Triangle uid 399,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "26625,5250,27375,6000" ) tg (CPTG uid 400,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 401,0 ro 270 va (VaSet font "courier,8,0" ) xt "26550,7000,27450,9500" st "write" ju 2 blo "27250,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 402,0 va (VaSet font "courier,8,0" ) xt "44000,8300,58500,9200" st "write : OUT std_ulogic " ) thePort (LogicalPort m 1 decl (Decl n "write" t "std_ulogic" o 8 suid 32,0 ) ) ) ] shape (Rectangle uid 9,0 va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,67000,14000" ) oxt "15000,6000,75000,14000" biTextGroup (BiTextGroup uid 10,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text uid 11,0 va (VaSet ) xt "37400,9000,44600,10000" st "Memory_test" blo "37400,9800" ) second (Text uid 12,0 va (VaSet ) xt "37400,10000,44600,11000" st "fifo_tester" blo "37400,10800" ) ) gi *80 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" matrix (Matrix uid 14,0 text (MLText uid 15,0 va (VaSet font "courier,8,0" ) xt "13000,6000,25000,9600" st "Generic Declarations dataBitNb positive 8 fifoDepth positive 64 " ) header "Generic Declarations" showHdrWhenContentsEmpty 1 ) elements [ (GiElement name "dataBitNb" type "positive" value "8" ) (GiElement name "fifoDepth" type "positive" value "64" ) ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay sTC 0 sF 0 ) portVis (PortSigDisplay sTC 0 sF 0 ) ) ] bg "65535,65535,65535" grid (Grid origin "0,0" isVisible 1 isActive 1 xSpacing 1000 xySpacing 1000 xShown 1 yShown 1 color "65535,0,0" ) packageList *81 (PackageList uid 16,0 stg "VerticalLayoutStrategy" textVec [ *82 (Text uid 17,0 va (VaSet font "courier,8,1" ) xt "0,0,5400,1000" st "Package List" blo "0,800" ) *83 (MLText uid 18,0 va (VaSet font "courier,8,0" ) xt "0,1000,15500,3700" st "LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;" tm "PackageList" ) ] ) windowSize "191,89,1207,779" viewArea "-500,-500,71230,48820" cachedDiagramExtent "0,0,75000,14000" hasePageBreakOrigin 1 pageBreakOrigin "0,0" defaultCommentText (CommentText shape (Rectangle layer 0 va (VaSet vasetType 1 fg "65280,65280,46080" lineColor "0,0,32768" ) xt "0,0,15000,5000" ) text (MLText va (VaSet fg "0,0,32768" font "courier,8,0" ) xt "200,200,2200,1100" st " Text " tm "CommentText" wrapOption 3 visibleHeight 4600 visibleWidth 14600 ) ) defaultRequirementText (RequirementText shape (ZoomableIcon layer 0 va (VaSet vasetType 1 fg "59904,39936,65280" lineColor "0,0,32768" ) xt "0,0,1500,1750" iconName "reqTracerRequirement.bmp" iconMaskName "reqTracerRequirement.msk" ) autoResize 1 text (MLText va (VaSet fg "0,0,32768" font "courier,8,0" ) xt "450,2150,1450,3050" st " Text " tm "RequirementText" wrapOption 3 visibleHeight 1350 visibleWidth 1100 ) ) defaultPanel (Panel shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "32768,0,0" lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (Text va (VaSet ) xt "1000,1000,5200,2200" st "Panel0" blo "1000,2000" tm "PanelText" ) ) ) parentGraphicsRef (HdmGraphicsRef libraryName "Memory_test" entityName "fifo_tb" viewName "struct.bd" ) defaultSymbolBody (SymbolBody shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,41000,26000" ) biTextGroup (BiTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet ) xt "25350,14800,30650,16000" st "" blo "25350,15800" ) second (Text va (VaSet ) xt "25350,16000,29250,17200" st "" blo "25350,17000" ) ) gi *84 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix text (MLText va (VaSet font "courier,8,0" ) xt "0,12000,10500,12900" st "Generic Declarations" ) header "Generic Declarations" showHdrWhenContentsEmpty 1 ) elements [ ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay sIVOD 1 ) portVis (PortSigDisplay sIVOD 1 ) ) defaultCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet font "courier,8,0" ) xt "0,750,1500,1650" st "In0" blo "0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "courier,8,0" ) ) thePort (LogicalPort lang 11 decl (Decl n "In0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) defaultCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" bg "0,0,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet font "courier,8,0" ) xt "0,750,3500,1650" st "Buffer0" blo "0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "courier,8,0" ) ) thePort (LogicalPort lang 11 m 3 decl (Decl n "Buffer0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) DeclarativeBlock *85 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" declLabel (Text uid 2,0 va (VaSet font "courier,8,1" ) xt "42000,0,49000,1000" st "Declarations" blo "42000,800" ) portLabel (Text uid 3,0 va (VaSet font "courier,8,1" ) xt "42000,1000,45400,2000" st "Ports:" blo "42000,1800" ) externalLabel (Text uid 4,0 va (VaSet font "courier,8,1" ) xt "42000,9200,44500,10100" st "User:" blo "42000,9900" ) internalLabel (Text uid 6,0 va (VaSet isHidden 1 font "courier,8,1" ) xt "42000,0,49600,1000" st "Internal User:" blo "42000,800" ) externalText (MLText uid 5,0 va (VaSet font "courier,8,0" ) xt "44000,10100,44000,10100" tm "SyDeclarativeTextMgr" ) internalText (MLText uid 7,0 va (VaSet isHidden 1 font "courier,8,0" ) xt "42000,0,42000,0" tm "SyDeclarativeTextMgr" ) ) lastUid 418,0 activeModelName "Symbol:GEN" )