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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1624,0
va (VaSet
)
xt "64000,39400,67400,40600"
st "clock"
blo "64000,40400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*33 (CptPort
uid 1625,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1626,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "79000,35625,79750,36375"
)
tg (CPTG
uid 1627,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1628,0
va (VaSet
)
xt "70700,35400,78000,36600"
st "lowpassOut"
ju 2
blo "78000,36400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "lowpassOut"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 1
)
)
)
*34 (CptPort
uid 1629,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1630,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62250,41625,63000,42375"
)
tg (CPTG
uid 1631,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1632,0
va (VaSet
)
xt "64000,41400,67300,42600"
st "reset"
blo "64000,42400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*35 (CptPort
uid 1633,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1634,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62250,35625,63000,36375"
)
tg (CPTG
uid 1635,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1636,0
va (VaSet
)
xt "64000,35400,69800,36600"
st "lowpassIn"
blo "64000,36400"
)
)
thePort (LogicalPort
decl (Decl
n "lowpassIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 4
)
)
)
]
shape (Rectangle
uid 1613,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "63000,32000,79000,44000"
)
oxt "32000,10000,48000,22000"
ttg (MlTextGroup
uid 1614,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*36 (Text
uid 1615,0
va (VaSet
font "Verdana,9,1"
)
xt "63600,43800,75100,45000"
st "WaveformGenerator"
blo "63600,44800"
tm "BdLibraryNameMgr"
)
*37 (Text
uid 1616,0
va (VaSet
font "Verdana,9,1"
)
xt "63600,44700,68200,45900"
st "lowpass"
blo "63600,45700"
tm "CptNameMgr"
)
*38 (Text
uid 1617,0
va (VaSet
font "Verdana,9,1"
)
xt "63600,45600,67600,46800"
st "I_filtX"
blo "63600,46600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1618,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1619,0
text (MLText
uid 1620,0
va (VaSet
font "Verdana,8,0"
)
xt "63000,47600,83800,49600"
st "signalBitNb = signalBitNb          ( positive )  
shiftBitNb  = lowpassShiftBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "shiftBitNb"
type "positive"
value "lowpassShiftBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*39 (Net
uid 1683,0
decl (Decl
n "ySerial"
t "std_ulogic"
o 3
suid 15,0
)
declText (MLText
uid 1684,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,24400,15300,25400"
st "SIGNAL ySerial    : std_ulogic"
)
)
*40 (Net
uid 1693,0
decl (Decl
n "xSerial"
t "std_ulogic"
o 6
suid 17,0
)
declText (MLText
uid 1694,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,21400,15300,22400"
st "SIGNAL xSerial    : std_ulogic"
)
)
*41 (Net
uid 1695,0
decl (Decl
n "xLowapss"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 4
suid 18,0
)
declText (MLText
uid 1696,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,19400,27200,20400"
st "SIGNAL xLowapss   : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*42 (Net
uid 1697,0
decl (Decl
n "xParallel"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 19,0
)
declText (MLText
uid 1698,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,20400,26400,21400"
st "SIGNAL xParallel  : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*43 (SaComponent
uid 1699,0
optionalChildren [
*44 (CptPort
uid 1708,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1709,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62250,19625,63000,20375"
)
tg (CPTG
uid 1710,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1711,0
va (VaSet
)
xt "64000,19400,67400,20600"
st "clock"
blo "64000,20400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*45 (CptPort
uid 1712,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1713,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "79000,15625,79750,16375"
)
tg (CPTG
uid 1714,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1715,0
va (VaSet
)
xt "70700,15400,78000,16600"
st "lowpassOut"
ju 2
blo "78000,16400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "lowpassOut"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 1
)
)
)
*46 (CptPort
uid 1716,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1717,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62250,21625,63000,22375"
)
tg (CPTG
uid 1718,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1719,0
va (VaSet
)
xt "64000,21400,67300,22600"
st "reset"
blo "64000,22400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*47 (CptPort
uid 1720,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1721,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62250,15625,63000,16375"
)
tg (CPTG
uid 1722,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1723,0
va (VaSet
)
xt "64000,15400,69800,16600"
st "lowpassIn"
blo "64000,16400"
)
)
thePort (LogicalPort
decl (Decl
n "lowpassIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 4
)
)
)
]
shape (Rectangle
uid 1700,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "63000,12000,79000,24000"
)
oxt "32000,10000,48000,22000"
ttg (MlTextGroup
uid 1701,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*48 (Text
uid 1702,0
va (VaSet
font "Verdana,9,1"
)
xt "63600,23800,75100,25000"
st "WaveformGenerator"
blo "63600,24800"
tm "BdLibraryNameMgr"
)
*49 (Text
uid 1703,0
va (VaSet
font "Verdana,9,1"
)
xt "63600,24700,68200,25900"
st "lowpass"
blo "63600,25700"
tm "CptNameMgr"
)
*50 (Text
uid 1704,0
va (VaSet
font "Verdana,9,1"
)
xt "63600,25600,67500,26800"
st "I_filty"
blo "63600,26600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1705,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1706,0
text (MLText
uid 1707,0
va (VaSet
font "Verdana,8,0"
)
xt "63000,27600,83800,29600"
st "signalBitNb = signalBitNb          ( positive )  
shiftBitNb  = lowpassShiftBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "shiftBitNb"
type "positive"
value "lowpassShiftBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*51 (Net
uid 1744,0
decl (Decl
n "yLowpass"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 7
suid 21,0
)
declText (MLText
uid 1745,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,22400,27200,23400"
st "SIGNAL yLowpass   : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*52 (Net
uid 1762,0
decl (Decl
n "yParallel"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 8
suid 23,0
)
declText (MLText
uid 1763,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,23400,26400,24400"
st "SIGNAL yParallel  : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*53 (Net
uid 1827,0
decl (Decl
n "triggerOut"
t "std_ulogic"
o 9
suid 24,0
)
declText (MLText
uid 1828,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,18400,15700,19400"
st "SIGNAL triggerOut : std_ulogic"
)
)
*54 (Wire
uid 1556,0
shape (OrthoPolyLine
uid 1557,0
va (VaSet
vasetType 3
)
xt "21000,42000,22250,52000"
pts [
"22250,42000"
"21000,42000"
"21000,52000"
]
)
start &23
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1560,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1561,0
va (VaSet
font "Verdana,12,0"
)
xt "17250,40700,21350,42100"
st "reset"
blo "17250,41900"
tm "WireNameMgr"
)
)
on &16
)
*55 (Wire
uid 1564,0
shape (OrthoPolyLine
uid 1565,0
va (VaSet
vasetType 3
)
xt "19000,40000,22250,52000"
pts [
"22250,40000"
"19000,40000"
"19000,52000"
]
)
start &19
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1568,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1569,0
va (VaSet
font "Verdana,12,0"
)
xt "17250,38700,21050,40100"
st "clock"
blo "17250,39900"
tm "WireNameMgr"
)
)
on &17
)
*56 (Wire
uid 1637,0
optionalChildren [
*57 (BdJunction
uid 1645,0
ps "OnConnectorStrategy"
shape (Circle
uid 1646,0
va (VaSet
vasetType 1
)
xt "46600,35600,47400,36400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1638,0
va (VaSet
vasetType 3
)
xt "39750,36000,47000,52000"
pts [
"39750,36000"
"47000,36000"
"47000,52000"
]
)
start &22
end &12
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1643,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1644,0
va (VaSet
font "Verdana,12,0"
)
xt "41000,34600,46000,36000"
st "ySerial"
blo "41000,35800"
tm "WireNameMgr"
)
)
on &39
)
*58 (Wire
uid 1647,0
shape (OrthoPolyLine
uid 1648,0
va (VaSet
vasetType 3
)
xt "47000,8000,47000,36000"
pts [
"47000,36000"
"47000,8000"
]
)
start &57
end &27
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1651,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1652,0
ro 270
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "45600,31500,47000,36500"
st "ySerial"
blo "46800,36500"
tm "WireNameMgr"
)
)
on &39
)
*59 (Wire
uid 1653,0
shape (OrthoPolyLine
uid 1654,0
va (VaSet
vasetType 3
)
xt "59000,42000,62250,42000"
pts [
"59000,42000"
"62250,42000"
]
)
end &34
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1657,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1658,0
va (VaSet
font "Verdana,12,0"
)
xt "59000,40600,63100,42000"
st "reset"
blo "59000,41800"
tm "WireNameMgr"
)
)
on &16
)
*60 (Wire
uid 1659,0
shape (OrthoPolyLine
uid 1660,0
va (VaSet
vasetType 3
)
xt "59000,40000,62250,40000"
pts [
"59000,40000"
"62250,40000"
]
)
end &32
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1663,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1664,0
va (VaSet
font "Verdana,12,0"
)
xt "59000,38600,62800,40000"
st "clock"
blo "59000,39800"
tm "WireNameMgr"
)
)
on &17
)
*61 (Wire
uid 1665,0
shape (OrthoPolyLine
uid 1666,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "79750,36000,83000,52000"
pts [
"79750,36000"
"83000,36000"
"83000,52000"
]
)
start &33
end &12
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1669,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1670,0
va (VaSet
font "Verdana,12,0"
)
xt "81750,34600,88850,36000"
st "xLowapss"
blo "81750,35800"
tm "WireNameMgr"
)
)
on &41
)
*62 (Wire
uid 1671,0
shape (OrthoPolyLine
uid 1672,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "55000,8000,62250,36000"
pts [
"62250,36000"
"55000,36000"
"55000,8000"
]
)
start &35
end &27
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1675,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1676,0
va (VaSet
font "Verdana,12,0"
)
xt "56000,34600,62100,36000"
st "xParallel"
blo "56000,35800"
tm "WireNameMgr"
)
)
on &42
)
*63 (Wire
uid 1687,0
optionalChildren [
*64 (BdJunction
uid 1752,0
ps "OnConnectorStrategy"
shape (Circle
uid 1753,0
va (VaSet
vasetType 1
)
xt "44600,37600,45400,38400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1688,0
va (VaSet
vasetType 3
)
xt "39750,38000,45000,52000"
pts [
"39750,38000"
"45000,38000"
"45000,52000"
]
)
start &21
end &12
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1691,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1692,0
va (VaSet
font "Verdana,12,0"
)
xt "41000,36700,46000,38100"
st "xSerial"
blo "41000,37900"
tm "WireNameMgr"
)
)
on &40
)
*65 (Wire
uid 1724,0
shape (OrthoPolyLine
uid 1725,0
va (VaSet
vasetType 3
)
xt "59000,20000,62250,20000"
pts [
"59000,20000"
"62250,20000"
]
)
end &44
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1728,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1729,0
va (VaSet
font "Verdana,12,0"
)
xt "59000,18600,62800,20000"
st "clock"
blo "59000,19800"
tm "WireNameMgr"
)
)
on &17
)
*66 (Wire
uid 1730,0
shape (OrthoPolyLine
uid 1731,0
va (VaSet
vasetType 3
)
xt "59000,22000,62250,22000"
pts [
"59000,22000"
"62250,22000"
]
)
end &46
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1735,0
va (VaSet
font "Verdana,12,0"
)
xt "59000,20600,63100,22000"
st "reset"
blo "59000,21800"
tm "WireNameMgr"
)
)
on &16
)
*67 (Wire
uid 1738,0
shape (OrthoPolyLine
uid 1739,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "79750,16000,85000,52000"
pts [
"79750,16000"
"85000,16000"
"85000,52000"
]
)
start &45
end &12
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1742,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1743,0
va (VaSet
font "Verdana,12,0"
)
xt "81750,14700,88850,16100"
st "yLowpass"
blo "81750,15900"
tm "WireNameMgr"
)
)
on &51
)
*68 (Wire
uid 1746,0
shape (OrthoPolyLine
uid 1747,0
va (VaSet
vasetType 3
)
xt "45000,8000,45000,38000"
pts [
"45000,38000"
"45000,8000"
]
)
start &64
end &27
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1750,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1751,0
ro 270
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "43700,9900,45100,14900"
st "xSerial"
blo "44900,14900"
tm "WireNameMgr"
)
)
on &40
)
*69 (Wire
uid 1756,0
shape (OrthoPolyLine
uid 1757,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "57000,8000,62250,16000"
pts [
"62250,16000"
"57000,16000"
"57000,8000"
]
)
start &47
end &27
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1760,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1761,0
va (VaSet
font "Verdana,12,0"
)
xt "55250,14700,61350,16100"
st "yParallel"
blo "55250,15900"
tm "WireNameMgr"
)
)
on &52
)
*70 (Wire
uid 1829,0
shape (OrthoPolyLine
uid 1830,0
va (VaSet
vasetType 3
)
xt "39750,40000,43000,52000"
pts [
"39750,40000"
"43000,40000"
"43000,52000"
]
)
start &20
end &12
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1834,0
va (VaSet
font "Verdana,12,0"
)
xt "41000,38700,49100,40100"
st "triggerOut"
blo "41000,39900"
tm "WireNameMgr"
)
)
on &53
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *71 (PackageList
uid 142,0
stg "VerticalLayoutStrategy"
textVec [
*72 (Text
uid 143,0
va (VaSet
font "Verdana,8,1"
)
xt "0,0,6900,1000"
st "Package List"
blo "0,800"
)
*73 (MLText
uid 144,0
va (VaSet
)
xt "0,1000,17500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 145,0
stg "VerticalLayoutStrategy"
textVec [
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