-- VHDL Entity DigitalToAnalogConverter.DAC.symbol
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 13:06:08 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY DAC IS
    GENERIC( 
        signalBitNb : positive := 16
    );
    PORT( 
        serialOut  : OUT    std_ulogic;
        parallelIn : IN     unsigned (signalBitNb-1 DOWNTO 0);
        clock      : IN     std_ulogic;
        reset      : IN     std_ulogic
    );

-- Declarations

END DAC ;