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library "ieee"
unitName "std_logic_1164"
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(DmPackageRef
library "ieee"
unitName "numeric_std"
)
(DmPackageRef
library "AhbLite"
unitName "ahbLite"
)
]
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ro 270
va (VaSet
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xt "150300,7000,151700,18100"
st "hReadyPeriph1"
ju 2
blo "151500,7000"
tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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xt "44000,11600,63500,12400"
st "hReadyPeriph1 : OUT    std_uLogic  ;
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m 1
decl (Decl
n "hReadyPeriph1"
t "std_uLogic"
o 12
suid 132,0
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ps "OnEdgeStrategy"
shape (Triangle
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va (VaSet
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fg "0,65535,0"
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xt "140625,5250,141375,6000"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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ro 270
va (VaSet
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xt "140300,7000,141700,18100"
st "hReadyPeriph2"
ju 2
blo "141500,7000"
tm "CptPortNameMgr"
)
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dt (MLText
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va (VaSet
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xt "44000,12400,63500,13200"
st "hReadyPeriph2 : OUT    std_uLogic  ;
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thePort (LogicalPort
m 1
decl (Decl
n "hReadyPeriph2"
t "std_uLogic"
o 13
suid 133,0
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ps "OnEdgeStrategy"
shape (Triangle
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ro 180
va (VaSet
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xt "58625,5250,59375,6000"
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tg (CPTG
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f (Text
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ro 270
va (VaSet
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xt "58300,7000,59700,13800"
st "hReset_n"
ju 2
blo "59500,7000"
tm "CptPortNameMgr"
)
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dt (MLText
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va (VaSet
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xt "44000,3600,63500,4400"
st "hReset_n      : IN     std_uLogic  ;
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)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_uLogic"
o 15
suid 134,0
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ps "OnEdgeStrategy"
shape (Triangle
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va (VaSet
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xt "148625,5250,149375,6000"
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stg "RightVerticalLayoutStrategy"
f (Text
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ro 270
va (VaSet
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xt "148300,7000,149700,17300"
st "hRespPeriph1"
ju 2
blo "149500,7000"
tm "CptPortNameMgr"
)
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dt (MLText
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va (VaSet
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xt "44000,13200,63500,14000"
st "hRespPeriph1  : OUT    std_uLogic  ;
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thePort (LogicalPort
m 1
decl (Decl
n "hRespPeriph1"
t "std_uLogic"
o 17
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ps "OnEdgeStrategy"
shape (Triangle
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va (VaSet
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xt "138625,5250,139375,6000"
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tg (CPTG
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ro 270
va (VaSet
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xt "138300,7000,139700,17300"
st "hRespPeriph2"
ju 2
blo "139500,7000"
tm "CptPortNameMgr"
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)
dt (MLText
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va (VaSet
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xt "44000,14000,63500,14800"
st "hRespPeriph2  : OUT    std_uLogic  ;
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m 1
decl (Decl
n "hRespPeriph2"
t "std_uLogic"
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suid 136,0
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shape (Triangle
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ro 180
va (VaSet
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xt "154625,5250,155375,6000"
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tg (CPTG
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xt "154300,7000,155700,16100"
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blo "155500,7000"
tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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xt "44000,4400,63500,5200"
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decl (Decl
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suid 137,0
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ps "OnEdgeStrategy"
shape (Triangle
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ro 180
va (VaSet
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xt "144625,5250,145375,6000"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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blo "145500,7000"
tm "CptPortNameMgr"
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va (VaSet
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xt "44000,5200,63500,6000"
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ro 180
va (VaSet
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xt "130625,5250,131375,6000"
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tg (CPTG
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st "hTrans"
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blo "131500,7000"
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ro 180
va (VaSet
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xt "132625,5250,133375,6000"
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tm "CptPortNameMgr"
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xt "44000,6800,80000,7600"
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decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 25
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)
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shape (Triangle
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ro 180
va (VaSet
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xt "128625,5250,129375,6000"
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tg (CPTG
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stg "RightVerticalLayoutStrategy"
f (Text
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ro 270
va (VaSet
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xt "128300,7000,129700,12000"
st "hWrite"
ju 2
blo "129500,7000"
tm "CptPortNameMgr"
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va (VaSet
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xt "44000,7600,63500,8400"
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decl (Decl
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o 26
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ps "OnEdgeStrategy"
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xt "36625,5250,37375,6000"
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blo "37500,7000"
tm "CptPortNameMgr"
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va (VaSet
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xt "44000,14800,63500,15600"
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xt "22625,5250,23375,6000"
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ro 270
va (VaSet
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xt "22300,7000,23700,14500"
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blo "23500,7000"
tm "CptPortNameMgr"
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xt "44000,15600,77000,16400"
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decl (Decl
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ro 180
va (VaSet
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xt "26625,5250,27375,6000"
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tg (CPTG
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ro 270
va (VaSet
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xt "26300,7000,27700,13700"
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blo "27500,7000"
tm "CptPortNameMgr"
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xt "44000,8400,80000,9200"
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decl (Decl
n "upDataIn"
t "std_ulogic_vector"
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xt "24625,5250,25375,6000"
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ro 270
va (VaSet
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xt "24300,7000,25700,14700"
st "upDataOut"
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blo "25500,7000"
tm "CptPortNameMgr"
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va (VaSet
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xt "44000,16400,80000,17200"
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m 1
decl (Decl
n "upDataOut"
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va (VaSet
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tm "CptPortNameMgr"
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xt "44000,17200,63500,18000"
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tm "CptPortNameMgr"
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va (VaSet
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xt "44000,18000,62500,18800"
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decl (Decl
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