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tg (CPTG
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tg (CPTG
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tg (CPTG
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xt "20800,45400,26000,46600"
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "10250,53625,11000,54375"
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tg (CPTG
uid 3663,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "12000,53400,15300,54600"
st "reset"
blo "12000,54400"
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)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
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uid 3665,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3666,0
ro 90
va (VaSet
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fg "0,65535,0"
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xt "10250,45625,11000,46375"
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tg (CPTG
uid 3667,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3668,0
va (VaSet
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xt "12000,45400,14900,46600"
st "step"
blo "12000,46400"
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thePort (LogicalPort
decl (Decl
n "step"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 4
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uid 3669,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3670,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "10250,49625,11000,50375"
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tg (CPTG
uid 3671,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3672,0
va (VaSet
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xt "12000,49400,13900,50600"
st "en"
blo "12000,50400"
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thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
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suid 5,0
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shape (Rectangle
uid 3674,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
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xt "11000,42000,27000,56000"
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stg "VerticalLayoutStrategy"
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uid 3676,0
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xt "11600,55800,23100,57000"
st "WaveformGenerator"
blo "11600,56800"
tm "BdLibraryNameMgr"
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uid 3677,0
va (VaSet
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xt "11600,56700,19500,57900"
st "sawtoothGen"
blo "11600,57700"
tm "CptNameMgr"
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uid 3678,0
va (VaSet
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xt "11600,57600,15300,58800"
st "I_saw"
blo "11600,58600"
tm "InstanceNameMgr"
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3680,0
text (MLText
uid 3681,0
va (VaSet
font "Verdana,8,0"
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xt "11000,59600,26700,60600"
st "bitNb = phaseBitNb    ( positive )  "
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header ""
)
elements [
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name "bitNb"
type "positive"
value "phaseBitNb"
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ordering 1
portVis (PortSigDisplay
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archFileType "UNKNOWN"
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uid 3698,0
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ro 90
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xt "51000,79625,51750,80375"
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tg (CPTG
uid 3684,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "43400,79400,50000,80600"
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blo "50000,80400"
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thePort (LogicalPort
m 1
decl (Decl
n "triggerOut"
t "std_ulogic"
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ro 90
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xt "34250,83625,35000,84375"
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tg (CPTG
uid 3688,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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xt "36000,83400,39400,84600"
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thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
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uid 3690,0
ps "OnEdgeStrategy"
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "34250,85625,35000,86375"
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tg (CPTG
uid 3692,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3693,0
va (VaSet
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xt "36000,85400,39300,86600"
st "reset"
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thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
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uid 3694,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3695,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "34250,79625,35000,80375"
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tg (CPTG
uid 3696,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "36000,79400,37900,80600"
st "en"
blo "36000,80400"
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thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
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shape (Rectangle
uid 3699,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
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xt "35000,76000,51000,88000"
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oxt "32000,6000,48000,18000"
ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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uid 3701,0
va (VaSet
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xt "35600,87800,46000,89000"
st "SplineInterpolator"
blo "35600,88800"
tm "BdLibraryNameMgr"
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uid 3702,0
va (VaSet
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xt "35600,88700,46300,89900"
st "interpolatorTrigger"
blo "35600,89700"
tm "CptNameMgr"
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uid 3703,0
va (VaSet
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xt "35600,89600,39100,90800"
st "I_trig"
blo "35600,90600"
tm "InstanceNameMgr"
)
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ga (GenericAssociation
uid 3704,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3705,0
text (MLText
uid 3706,0
va (VaSet
font "Verdana,8,0"
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xt "35000,91600,57100,92600"
st "counterBitNb = sampleCountBitNb    ( positive )  "
)
header ""
)
elements [
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name "counterBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
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uid 3739,0
optionalChildren [
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uid 3707,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "66250,67625,67000,68375"
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tg (CPTG
uid 3709,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "68000,67400,71400,68600"
st "clock"
blo "68000,68400"
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)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
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uid 3711,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3712,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "66250,69625,67000,70375"
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tg (CPTG
uid 3713,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3714,0
va (VaSet
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xt "68000,69400,71300,70600"
st "reset"
blo "68000,70400"
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)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
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)
)
*92 (CptPort
uid 3715,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3716,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "66250,63625,67000,64375"
)
tg (CPTG
uid 3717,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3718,0
va (VaSet
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xt "68000,63400,75900,64600"
st "shiftSamples"
blo "68000,64400"
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)
thePort (LogicalPort
decl (Decl
n "shiftSamples"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*93 (CptPort
uid 3719,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3720,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "66250,61625,67000,62375"
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tg (CPTG
uid 3721,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3722,0
va (VaSet
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xt "68000,61400,73400,62600"
st "sampleIn"
blo "68000,62400"
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)
thePort (LogicalPort
decl (Decl
n "sampleIn"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 4
suid 4,0
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)
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uid 3723,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3724,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "83000,61625,83750,62375"
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tg (CPTG
uid 3725,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3726,0
va (VaSet
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xt "77000,61400,82000,62600"
st "sample1"
ju 2
blo "82000,62400"
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)
thePort (LogicalPort
m 1
decl (Decl
n "sample1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 5,0
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)
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uid 3727,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3728,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "83000,63625,83750,64375"
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tg (CPTG
uid 3729,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3730,0
va (VaSet
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xt "77000,63400,82000,64600"
st "sample2"
ju 2
blo "82000,64400"
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)
thePort (LogicalPort
m 1
decl (Decl
n "sample2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*96 (CptPort
uid 3731,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3732,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "83000,65625,83750,66375"
)
tg (CPTG
uid 3733,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3734,0
va (VaSet
)
xt "77000,65400,82000,66600"
st "sample3"
ju 2
blo "82000,66400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
*97 (CptPort
uid 3735,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3736,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "83000,67625,83750,68375"
)
tg (CPTG
uid 3737,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3738,0
va (VaSet
)
xt "77000,67400,82000,68600"
st "sample4"
ju 2
blo "82000,68400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 8
suid 8,0
)
)
)
]
shape (Rectangle
uid 3740,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "67000,58000,83000,72000"
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oxt "35000,9000,51000,23000"
ttg (MlTextGroup
uid 3741,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 3742,0
va (VaSet
font "Verdana,9,1"
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xt "67600,71800,78000,73000"
st "SplineInterpolator"
blo "67600,72800"
tm "BdLibraryNameMgr"
)
*99 (Text
uid 3743,0
va (VaSet
font "Verdana,9,1"
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xt "67600,72700,82100,73900"
st "interpolatorShiftRegister"
blo "67600,73700"
tm "CptNameMgr"
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*100 (Text
uid 3744,0
va (VaSet
font "Verdana,9,1"
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xt "67600,73600,72300,74800"
st "I_shReg"
blo "67600,74600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3745,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3746,0
text (MLText
uid 3747,0
va (VaSet
font "Verdana,8,0"
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xt "67000,75600,85400,76600"
st "signalBitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
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name "signalBitNb"
type "positive"
value "signalBitNb"
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]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
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*101 (SaComponent
uid 3784,0
optionalChildren [
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uid 3748,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3749,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "90250,61625,91000,62375"
)
tg (CPTG
uid 3750,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3751,0
va (VaSet
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xt "92000,61400,97000,62600"
st "sample1"
blo "92000,62400"
)
)
thePort (LogicalPort
decl (Decl
n "sample1"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 1
suid 1,0
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)
)
*103 (CptPort
uid 3752,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3753,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "90250,63625,91000,64375"
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tg (CPTG
uid 3754,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3755,0
va (VaSet
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xt "92000,63400,97000,64600"
st "sample2"
blo "92000,64400"
)
)
thePort (LogicalPort
decl (Decl
n "sample2"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
suid 2,0
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)
*104 (CptPort
uid 3756,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3757,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "90250,65625,91000,66375"
)
tg (CPTG
uid 3758,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3759,0
va (VaSet
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xt "92000,65400,97000,66600"
st "sample3"
blo "92000,66400"
)
)
thePort (LogicalPort
decl (Decl
n "sample3"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
*105 (CptPort
uid 3760,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3761,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "90250,67625,91000,68375"
)
tg (CPTG
uid 3762,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3763,0
va (VaSet
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xt "92000,67400,97000,68600"
st "sample4"
blo "92000,68400"
)
)
thePort (LogicalPort
decl (Decl
n "sample4"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*106 (CptPort
uid 3764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "107000,61625,107750,62375"
)
tg (CPTG
uid 3766,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3767,0
va (VaSet
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xt "104700,61400,106000,62600"
st "a"
ju 2
blo "106000,62400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*107 (CptPort
uid 3768,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3769,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "107000,63625,107750,64375"
)
tg (CPTG
uid 3770,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3771,0
va (VaSet
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xt "104700,63400,106000,64600"
st "b"
ju 2
blo "106000,64400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*108 (CptPort
uid 3772,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3773,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "107000,67625,107750,68375"
)
tg (CPTG
uid 3774,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3775,0
va (VaSet
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xt "104700,67400,106000,68600"
st "d"
ju 2
blo "106000,68400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
suid 7,0
)
)
)
*109 (CptPort
uid 3776,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3777,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "107000,65625,107750,66375"
)
tg (CPTG
uid 3778,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3779,0
va (VaSet
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xt "104700,65400,106000,66600"
st "c"
ju 2
blo "106000,66400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
suid 8,0
)
)
)
*110 (CptPort
uid 3780,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3781,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "90250,69625,91000,70375"
)
tg (CPTG
uid 3782,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3783,0
va (VaSet
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xt "92000,69400,101900,70600"
st "interpolateLinear"
blo "92000,70400"
)
)
thePort (LogicalPort
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
suid 9,0
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)
)
]
shape (Rectangle
uid 3785,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "91000,58000,107000,74000"
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oxt "33000,11000,49000,27000"
ttg (MlTextGroup
uid 3786,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 3787,0
va (VaSet
font "Verdana,9,1"
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xt "91600,73800,102000,75000"
st "SplineInterpolator"
blo "91600,74800"
tm "BdLibraryNameMgr"
)
*112 (Text
uid 3788,0
va (VaSet
font "Verdana,9,1"
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xt "91600,74700,105500,75900"
st "interpolatorCoefficients"
blo "91600,75700"
tm "CptNameMgr"
)
*113 (Text
uid 3789,0
va (VaSet
font "Verdana,9,1"
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xt "91600,75600,96500,76800"
st "I_coeffs"
blo "91600,76600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3790,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3791,0
text (MLText
uid 3792,0
va (VaSet
font "Verdana,8,0"
)
xt "91000,77800,109100,79800"
st "bitNb      = signalBitNb    ( positive )  
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)
header ""
)
elements [
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name "bitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
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*114 (SaComponent
uid 3829,0
optionalChildren [
*115 (CptPort
uid 3793,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3794,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,75625,115000,76375"
)
tg (CPTG
uid 3795,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3796,0
va (VaSet
)
xt "116000,75400,119400,76600"
st "clock"
blo "116000,76400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*116 (CptPort
uid 3797,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3798,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,77625,115000,78375"
)
tg (CPTG
uid 3799,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3800,0
va (VaSet
)
xt "116000,77400,119300,78600"
st "reset"
blo "116000,78400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*117 (CptPort
uid 3801,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3802,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,69625,115000,70375"
)
tg (CPTG
uid 3803,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3804,0
va (VaSet
)
xt "116000,69400,125100,70600"
st "restartPolynom"
blo "116000,70400"
)
)
thePort (LogicalPort
decl (Decl
n "restartPolynom"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*118 (CptPort
uid 3805,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3806,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,67625,115000,68375"
)
tg (CPTG
uid 3807,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3808,0
va (VaSet
)
xt "116000,67400,117300,68600"
st "d"
blo "116000,68400"
)
)
thePort (LogicalPort
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*119 (CptPort
uid 3809,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3810,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "131000,61625,131750,62375"
)
tg (CPTG
uid 3811,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3812,0
va (VaSet
)
xt "123800,61400,130000,62600"
st "sampleOut"
ju 2
blo "130000,62400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sampleOut"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*120 (CptPort
uid 3813,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3814,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,65625,115000,66375"
)
tg (CPTG
uid 3815,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3816,0
va (VaSet
)
xt "116000,65400,117300,66600"
st "c"
blo "116000,66400"
)
)
thePort (LogicalPort
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
*121 (CptPort
uid 3817,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3818,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,63625,115000,64375"
)
tg (CPTG
uid 3819,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3820,0
va (VaSet
)
xt "116000,63400,117300,64600"
st "b"
blo "116000,64400"
)
)
thePort (LogicalPort
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
*122 (CptPort
uid 3821,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3822,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,61625,115000,62375"
)
tg (CPTG
uid 3823,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3824,0
va (VaSet
)
xt "116000,61400,117300,62600"
st "a"
blo "116000,62400"
)
)
thePort (LogicalPort
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
suid 8,0
)
)
)
*123 (CptPort
uid 3825,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3826,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,73625,115000,74375"
)
tg (CPTG
uid 3827,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3828,0
va (VaSet
)
xt "116000,73400,117900,74600"
st "en"
blo "116000,74400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 3830,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "115000,58000,131000,81000"
)
oxt "37000,7000,53000,30000"
ttg (MlTextGroup
uid 3831,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*124 (Text
uid 3832,0
va (VaSet
font "Verdana,9,1"
)
xt "115600,80800,126000,82000"
st "SplineInterpolator"
blo "115600,81800"
tm "BdLibraryNameMgr"
)
*125 (Text
uid 3833,0
va (VaSet
font "Verdana,9,1"
)
xt "115600,81700,132300,82900"
st "interpolatorCalculatePolynom"
blo "115600,82700"
tm "CptNameMgr"
)
*126 (Text
uid 3834,0
va (VaSet
font "Verdana,9,1"
)
xt "115600,82600,120200,83800"
st "I_spline"
blo "115600,83600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3835,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3836,0
text (MLText
uid 3837,0
va (VaSet
font "Verdana,8,0"
)
xt "115000,85000,139500,88000"
st "signalBitNb       = signalBitNb         ( positive )  
coeffBitNb        = coeffBitNb          ( positive )  
oversamplingBitNb = sampleCountBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
(GiElement
name "oversamplingBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*127 (SaComponent
uid 3846,0
optionalChildren [
*128 (CptPort
uid 3838,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3839,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "131000,37625,131750,38375"
)
tg (CPTG
uid 3840,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3841,0
va (VaSet
)
xt "122200,37400,130000,38600"
st "unsignedOut"
ju 2
blo "130000,38400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "unsignedOut"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*129 (CptPort
uid 3842,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3843,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "114250,37625,115000,38375"
)
tg (CPTG
uid 3844,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3845,0
va (VaSet
)
xt "116000,37400,121100,38600"
st "signedIn"
blo "116000,38400"
)
)
thePort (LogicalPort
decl (Decl
n "signedIn"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
]
shape (Rectangle
uid 3847,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "115000,34000,131000,42000"
)
oxt "32000,10000,48000,18000"
ttg (MlTextGroup
uid 3848,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*130 (Text
uid 3849,0
va (VaSet
font "Verdana,9,1"
)
xt "115600,41800,126000,43000"
st "SplineInterpolator"
blo "115600,42800"
tm "BdLibraryNameMgr"
)
*131 (Text
uid 3850,0
va (VaSet
font "Verdana,9,1"
)
xt "115600,42700,125700,43900"
st "offsetToUnsigned"
blo "115600,43700"
tm "CptNameMgr"
)
*132 (Text
uid 3851,0
va (VaSet
font "Verdana,9,1"
)
xt "115600,43600,122300,44800"
st "I_unsigned"
blo "115600,44600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3852,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3853,0
text (MLText
uid 3854,0
va (VaSet
font "Verdana,8,0"
)
xt "115000,45800,130600,46800"
st "bitNb = signalBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*133 (Wire
uid 15,0
shape (OrthoPolyLine
uid 16,0
va (VaSet
vasetType 3
)
xt "3000,52000,10250,52000"
pts [
"3000,52000"
"10250,52000"
]
)
start &1
end &73
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20,0
va (VaSet
font "Verdana,12,0"
)
xt "3000,50600,6800,52000"
st "clock"
blo "3000,51800"
tm "WireNameMgr"
)
)
on &2
)
*134 (Wire
uid 237,0
shape (OrthoPolyLine
uid 238,0
va (VaSet
vasetType 3
)
xt "3000,54000,10250,54000"
pts [
"3000,54000"
"10250,54000"
]
)
start &3
end &75
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 243,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 244,0
va (VaSet
font "Verdana,12,0"
)
xt "3000,52600,7100,54000"
st "reset"
blo "3000,53800"
tm "WireNameMgr"
)
)
on &4
)
*135 (Wire
uid 414,0
optionalChildren [
*136 (BdJunction
uid 476,0
ps "OnConnectorStrategy"
shape (Circle
uid 477,0
va (VaSet
vasetType 1
)
xt "30600,45600,31400,46400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 415,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "27750,46000,34250,46000"
pts [
"27750,46000"
"34250,46000"
]
)
start &74
end &62
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 416,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 417,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,44600,32700,46000"
st "phase"
blo "28000,45800"
tm "WireNameMgr"
)
)
on &24
)
*137 (Wire
uid 424,0
shape (OrthoPolyLine
uid 425,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "83750,46000,91000,46000"
pts [
"83750,46000"
"91000,46000"
]
)
start &55
end &22
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
font "Verdana,12,0"
)
xt "87000,44600,92600,46000"
st "triangle"
blo "87000,45800"
tm "WireNameMgr"
)
)
on &17
)
*138 (Wire
uid 472,0
shape (OrthoPolyLine
uid 473,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "31000,46000,34250,62000"
pts [
"31000,46000"
"31000,62000"
"34250,62000"
]
)
start &136
end &68
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 474,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 475,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "29000,43600,33700,45000"
st "phase"
blo "29000,44800"
tm "WireNameMgr"
)
)
on &24
)
*139 (Wire
uid 480,0
shape (OrthoPolyLine
uid 481,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "83750,30000,91000,30000"
pts [
"83750,30000"
"91000,30000"
]
)
start &49
end &21
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 485,0
va (VaSet
font "Verdana,12,0"
)
xt "87000,28600,92200,30000"
st "square"
blo "87000,29800"
tm "WireNameMgr"
)
)
on &18
)
*140 (Wire
uid 562,0
shape (OrthoPolyLine
uid 563,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "131750,38000,139000,38000"
pts [
"131750,38000"
"139000,38000"
]
)
start &128
end &23
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 566,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 567,0
va (VaSet
font "Verdana,12,0"
)
xt "135000,36600,138400,38000"
st "sine"
blo "135000,37800"
tm "WireNameMgr"
)
)
on &19
)
*141 (Wire
uid 601,0
optionalChildren [
*142 (BdJunction
uid 862,0
ps "OnConnectorStrategy"
shape (Circle
uid 863,0
va (VaSet
vasetType 1
)
xt "58600,45600,59400,46400"
radius 400
)
)
*143 (BdJunction
uid 891,0
ps "OnConnectorStrategy"
shape (Circle
uid 892,0
va (VaSet
vasetType 1
)
xt "58600,29600,59400,30400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 602,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "51750,18000,91000,46000"
pts [
"51750,46000"
"59000,46000"
"59000,18000"
"91000,18000"
]
)
start &61
end &20
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 605,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 606,0
va (VaSet
font "Verdana,12,0"
)
xt "85000,16600,91800,18000"
st "sawtooth"
blo "85000,17800"
tm "WireNameMgr"
)
)
on &16
)
*144 (Wire
uid 781,0
shape (OrthoPolyLine
uid 782,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3000,46000,10250,46000"
pts [
"10250,46000"
"3000,46000"
]
)
start &76
end &47
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 785,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 786,0
va (VaSet
font "Verdana,12,0"
)
xt "7000,43600,10600,45000"
st "step"
blo "7000,44800"
tm "WireNameMgr"
)
)
on &25
)
*145 (Wire
uid 858,0
shape (OrthoPolyLine
uid 859,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,46000,66250,46000"
pts [
"59000,46000"
"66250,46000"
]
)
start &142
end &56
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 860,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 861,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "55250,60600,62050,62000"
st "sawtooth"
blo "55250,61800"
tm "WireNameMgr"
)
)
on &16
)
*146 (Wire
uid 887,0
shape (OrthoPolyLine
uid 888,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,30000,66250,30000"
pts [
"59000,30000"
"66250,30000"
]
)
start &143
end &50
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 889,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 890,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "55250,28600,62050,30000"
st "sawtooth"
blo "55250,29800"
tm "WireNameMgr"
)
)
on &16
)
*147 (Wire
uid 985,0
shape (OrthoPolyLine
uid 986,0
va (VaSet
vasetType 3
)
xt "31000,84000,34250,84000"
pts [
"31000,84000"
"34250,84000"
]
)
end &83
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 991,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 992,0
va (VaSet
font "Verdana,12,0"
)
xt "30000,82600,33800,84000"
st "clock"
blo "30000,83800"
tm "WireNameMgr"
)
)
on &2
)
*148 (Wire
uid 993,0
shape (OrthoPolyLine
uid 994,0
va (VaSet
vasetType 3
)
xt "31000,86000,34250,86000"
pts [
"31000,86000"
"34250,86000"
]
)
end &84
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 999,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1000,0
va (VaSet
font "Verdana,12,0"
)
xt "30000,84600,34100,86000"
st "reset"
blo "30000,85800"
tm "WireNameMgr"
)
)
on &4
)
*149 (Wire
uid 1096,0
shape (OrthoPolyLine
uid 1097,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "51750,62000,66250,62000"
pts [
"51750,62000"
"66250,62000"
]
)
start &67
end &93
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1100,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1101,0
va (VaSet
font "Verdana,12,0"
)
xt "55000,60600,64500,62000"
st "sineSamples"
blo "55000,61800"
tm "WireNameMgr"
)
)
on &26
)
*150 (Wire
uid 1106,0
optionalChildren [
*151 (BdJunction
uid 1834,0
ps "OnConnectorStrategy"
shape (Circle
uid 1835,0
va (VaSet
vasetType 1
)
xt "58600,79600,59400,80400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1107,0
va (VaSet
vasetType 3
)
xt "51750,64000,66250,80000"
pts [
"51750,80000"
"59000,80000"
"59000,64000"
"66250,64000"
]
)
start &82
end &92
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1110,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1111,0
va (VaSet
font "Verdana,12,0"
)
xt "54000,78600,63600,80000"
st "newPolynom"
blo "54000,79800"
tm "WireNameMgr"
)
)
on &31
)
*152 (Wire
uid 1220,0
shape (OrthoPolyLine
uid 1221,0
va (VaSet
vasetType 3
)
xt "63000,70000,66250,70000"
pts [
"63000,70000"
"66250,70000"
]
)
end &91
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1226,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1227,0
va (VaSet
font "Verdana,12,0"
)
xt "62000,68600,66100,70000"
st "reset"
blo "62000,69800"
tm "WireNameMgr"
)
)
on &4
)
*153 (Wire
uid 1228,0
shape (OrthoPolyLine
uid 1229,0
va (VaSet
vasetType 3
)
xt "63000,68000,66250,68000"
pts [
"63000,68000"
"66250,68000"
]
)
end &90
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1234,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1235,0
va (VaSet
font "Verdana,12,0"
)
xt "62000,66600,65800,68000"
st "clock"
blo "62000,67800"
tm "WireNameMgr"
)
)
on &2
)
*154 (Wire
uid 1279,0
shape (OrthoPolyLine
uid 1280,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "83750,62000,90250,62000"
pts [
"83750,62000"
"90250,62000"
]
)
start &94
end &102
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1283,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1284,0
va (VaSet
font "Verdana,12,0"
)
xt "84000,60600,90100,62000"
st "sample1"
blo "84000,61800"
tm "WireNameMgr"
)
)
on &27
)
*155 (Wire
uid 1287,0
shape (OrthoPolyLine
uid 1288,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "83750,64000,90250,64000"
pts [
"83750,64000"
"90250,64000"
]
)
start &95
end &103
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1291,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1292,0
va (VaSet
font "Verdana,12,0"
)
xt "84000,62600,90100,64000"
st "sample2"
blo "84000,63800"
tm "WireNameMgr"
)
)
on &28
)
*156 (Wire
uid 1295,0
shape (OrthoPolyLine
uid 1296,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "83750,66000,90250,66000"
pts [
"83750,66000"
"90250,66000"
]
)
start &96
end &104
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1299,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1300,0
va (VaSet
font "Verdana,12,0"
)
xt "84000,64600,90100,66000"
st "sample3"
blo "84000,65800"
tm "WireNameMgr"
)
)
on &29
)
*157 (Wire
uid 1303,0
shape (OrthoPolyLine
uid 1304,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "83750,68000,90250,68000"
pts [
"83750,68000"
"90250,68000"
]
)
start &97
end &105
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1307,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1308,0
va (VaSet
font "Verdana,12,0"
)
xt "84000,66600,90100,68000"
st "sample4"
blo "84000,67800"
tm "WireNameMgr"
)
)
on &30
)
*158 (Wire
uid 1703,0
shape (OrthoPolyLine
uid 1704,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107750,62000,114250,62000"
pts [
"107750,62000"
"114250,62000"
]
)
start &106
end &122
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1707,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1708,0
va (VaSet
font "Verdana,12,0"
)
xt "109750,60600,111350,62000"
st "a"
blo "109750,61800"
tm "WireNameMgr"
)
)
on &32
)
*159 (Wire
uid 1711,0
shape (OrthoPolyLine
uid 1712,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107750,64000,114250,64000"
pts [
"107750,64000"
"114250,64000"
]
)
start &107
end &121
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1715,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1716,0
va (VaSet
font "Verdana,12,0"
)
xt "109750,62600,111350,64000"
st "b"
blo "109750,63800"
tm "WireNameMgr"
)
)
on &33
)
*160 (Wire
uid 1719,0
shape (OrthoPolyLine
uid 1720,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107750,66000,114250,66000"
pts [
"107750,66000"
"114250,66000"
]
)
start &109
end &120
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1723,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1724,0
va (VaSet
font "Verdana,12,0"
)
xt "109750,64600,111150,66000"
st "c"
blo "109750,65800"
tm "WireNameMgr"
)
)
on &34
)
*161 (Wire
uid 1727,0
shape (OrthoPolyLine
uid 1728,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107750,68000,114250,68000"
pts [
"107750,68000"
"114250,68000"
]
)
start &108
end &118
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1731,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1732,0
va (VaSet
font "Verdana,12,0"
)
xt "109750,66600,111350,68000"
st "d"
blo "109750,67800"
tm "WireNameMgr"
)
)
on &35
)
*162 (Wire
uid 1814,0
shape (OrthoPolyLine
uid 1815,0
va (VaSet
vasetType 3
)
xt "111000,76000,114250,76000"
pts [
"111000,76000"
"114250,76000"
]
)
end &115
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1820,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1821,0
va (VaSet
font "Verdana,12,0"
)
xt "110000,74600,113800,76000"
st "clock"
blo "110000,75800"
tm "WireNameMgr"
)
)
on &2
)
*163 (Wire
uid 1822,0
shape (OrthoPolyLine
uid 1823,0
va (VaSet
vasetType 3
)
xt "111000,78000,114250,78000"
pts [
"111000,78000"
"114250,78000"
]
)
end &116
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1828,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1829,0
va (VaSet
font "Verdana,12,0"
)
xt "110000,76600,114100,78000"
st "reset"
blo "110000,77800"
tm "WireNameMgr"
)
)
on &4
)
*164 (Wire
uid 1830,0
shape (OrthoPolyLine
uid 1831,0
va (VaSet
vasetType 3
)
xt "59000,70000,114250,80000"
pts [
"59000,80000"
"109000,80000"
"109000,70000"
"114250,70000"
]
)
start &151
end &117
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1832,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1833,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "71000,80600,80600,82000"
st "newPolynom"
blo "71000,81800"
tm "WireNameMgr"
)
)
on &31
)
*165 (Wire
uid 2219,0
shape (OrthoPolyLine
uid 2220,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107000,38000,139000,62000"
pts [
"131750,62000"
"139000,62000"
"139000,50000"
"107000,50000"
"107000,38000"
"114250,38000"
]
)
start &119
end &129
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2225,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2226,0
va (VaSet
font "Verdana,12,0"
)
xt "133000,60600,141500,62000"
st "sineSigned"
blo "133000,61800"
tm "WireNameMgr"
)
)
on &36
)
*166 (Wire
uid 2386,0
shape (OrthoPolyLine
uid 2387,0
va (VaSet
vasetType 3
)
xt "27000,80000,34250,80000"
pts [
"34250,80000"
"27000,80000"
]
)
start &85
end &37
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2390,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2391,0
va (VaSet
font "Verdana,12,0"
)
xt "30000,78600,34400,80000"
st "logic1"
blo "30000,79800"
tm "WireNameMgr"
)
)
on &41
)
*167 (Wire
uid 2394,0
shape (OrthoPolyLine
uid 2395,0
va (VaSet
vasetType 3
)
xt "111000,74000,114250,74000"
pts [
"114250,74000"
"111000,74000"
]
)
start &123
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2398,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2399,0
va (VaSet
font "Verdana,12,0"
)
xt "110000,72600,114400,74000"
st "logic1"
blo "110000,73800"
tm "WireNameMgr"
)
)
on &41
)
*168 (Wire
uid 2449,0
shape (OrthoPolyLine
uid 2450,0
va (VaSet
vasetType 3
)
xt "3000,50000,10250,50000"
pts [
"10250,50000"
"3000,50000"
]
)
start &77
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2455,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2456,0
va (VaSet
font "Verdana,12,0"
)
xt "6000,48600,10400,50000"
st "logic1"
blo "6000,49800"
tm "WireNameMgr"
)
)
on &41
)
*169 (Wire
uid 2571,0
shape (OrthoPolyLine
uid 2572,0
va (VaSet
vasetType 3
)
xt "83000,70000,90250,86000"
pts [
"90250,70000"
"87000,70000"
"87000,86000"
"83000,86000"
]
)
start &110
end &42
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2577,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2578,0
va (VaSet
font "Verdana,12,0"
)
xt "84000,84600,88400,86000"
st "logic0"
blo "84000,85800"
tm "WireNameMgr"
)
)
on &46
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *170 (PackageList
uid 84,0
stg "VerticalLayoutStrategy"
textVec [
*171 (Text
uid 85,0
va (VaSet
font "Verdana,8,1"
)
xt "-3000,0,3900,1000"
st "Package List"
blo "-3000,800"
)
*172 (MLText
uid 86,0
va (VaSet
)
xt "-3000,1000,14500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 87,0
stg "VerticalLayoutStrategy"
textVec [
*173 (Text
uid 88,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30200,1000"
st "Compiler Directives"
blo "20000,800"
)
*174 (Text
uid 89,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,32200,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*175 (MLText
uid 90,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*176 (Text
uid 91,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32800,5000"
st "Post-module directives:"
blo "20000,4800"
)
*177 (MLText
uid 92,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*178 (Text
uid 93,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,32400,6000"
st "End-module directives:"
blo "20000,5800"
)
*179 (MLText
uid 94,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-5150,-2146,185748,101574"
cachedDiagramExtent "-21700,0,164400,99000"
pageSetupInfo (PageSetupInfo
ptrCmd "Generic PostScript Printer,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
xMargin 48
yMargin 48
paperWidth 1077
paperHeight 761
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 1077
windowsPaperHeight 761
paperType "A4"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4"
scale 50
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-3000,0"
lastUid 3983,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*180 (Text
va (VaSet
)
xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*181 (Text
va (VaSet
)
xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*182 (Text
va (VaSet
)
xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1700,13200,1700,13200"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*183 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*184 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*185 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*186 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*187 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*188 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*189 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*190 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*191 (Text
va (VaSet
)
xt "950,5500,1550,6500"
st "I0"
blo "950,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6050,1500,-6050,1500"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-50,0,8050,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*192 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*193 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*194 (Text
va (VaSet
)
xt "450,5500,1050,6500"
st "I0"
blo "450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6550,1500,-6550,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*195 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*196 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
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]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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font "Verdana,12,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
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xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
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)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
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xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
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)
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defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
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)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
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xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
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xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
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pts [
"0,0"
"0,0"
]
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ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
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xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
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st "()"
tm "BundleContentsMgr"
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bundleNet &0
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defaultPortMapFrame (PortMapFrame
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shape (RectFrame
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vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
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xt "0,0,10000,12000"
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portMapText (BiTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
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xt "0,1000,9600,2200"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
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xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
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)
seqNum (FrameSequenceNumber
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shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
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num (Text
va (VaSet
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xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
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decls (MlTextGroup
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stg "VerticalLayoutStrategy"
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font "Verdana,8,1"
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xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
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*198 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
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xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
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shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
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num (Text
va (VaSet
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xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
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)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
font "Verdana,8,1"
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xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*200 (MLText
va (VaSet
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xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
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tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Verdana,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
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xt "-3000,5600,4000,6600"
st "Declarations"
blo "-3000,6400"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "-3000,6500,400,7500"
st "Ports:"
blo "-3000,7300"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "-3000,13700,1800,14700"
st "Pre User:"
blo "-3000,14500"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "-1000,14600,31300,17600"
st "constant tableAddressBitNb : positive := 3;
constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
constant coeffBitNb : positive := signalBitNb+4;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,8,1"
)
xt "-3000,17300,6000,18300"
st "Diagram Signals:"
blo "-3000,18100"
)
postUserLabel (Text
uid 7,0
va (VaSet
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font "Verdana,8,1"
)
xt "-3000,5600,3000,6600"
st "Post User:"
blo "-3000,6400"
)
postUserText (MLText
uid 8,0
va (VaSet
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font "Verdana,8,0"
)
xt "-3000,5600,-3000,5600"
tm "BdDeclarativeTextMgr"
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commonDM (CommonDM
ldm (LogicalDM
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usingSuid 1
emptyRow *201 (LEmptyRow
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uid 2778,0
optionalChildren [
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*203 (TitleRowHdr
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*204 (FilterRowHdr
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*205 (RefLabelColHdr
tm "RefLabelColHdrMgr"
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*206 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*207 (GroupColHdr
tm "GroupColHdrMgr"
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*208 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
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*209 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
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*210 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
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*211 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
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*212 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
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*213 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
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*214 (LeafLogPort
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decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
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*215 (LeafLogPort
port (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2,0
)
)
uid 2735,0
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*216 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "sawtooth"
t "unsigned"
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o 4
suid 3,0
)
)
uid 2737,0
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*217 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "triangle"
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o 7
suid 4,0
)
)
uid 2739,0
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*218 (LeafLogPort
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m 1
decl (Decl
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o 6
suid 5,0
)
)
uid 2741,0
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*219 (LeafLogPort
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m 1
decl (Decl
n "sine"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 5
suid 6,0
)
)
uid 2743,0
)
*220 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "phase"
t "unsigned"
b "(phaseBitNb-1 DOWNTO 0)"
o 15
suid 7,0
)
)
uid 2745,0
)
*221 (LeafLogPort
port (LogicalPort
decl (Decl
n "step"
t "unsigned"
b "(phaseBitNb-1 DOWNTO 0)"
o 3
suid 8,0
)
)
uid 2747,0
)
*222 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sineSamples"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 20
suid 9,0
)
)
uid 2749,0
)
*223 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sample1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 16
suid 10,0
)
)
uid 2751,0
)
*224 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sample2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 17
suid 11,0
)
)
uid 2753,0
)
*225 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sample3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 18
suid 12,0
)
)
uid 2755,0
)
*226 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sample4"
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b "(signalBitNb-1 DOWNTO 0)"
o 19
suid 13,0
)
)
uid 2757,0
)
*227 (LeafLogPort
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m 4
decl (Decl
n "newPolynom"
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o 14
suid 14,0
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uid 2759,0
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*228 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "a"
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b "(coeffBitNb-1 DOWNTO 0)"
o 8
suid 15,0
)
)
uid 2761,0
)
*229 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 9
suid 16,0
)
)
uid 2763,0
)
*230 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 10
suid 17,0
)
)
uid 2765,0
)
*231 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "d"
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o 11
suid 18,0
)
)
uid 2767,0
)
*232 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sineSigned"
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o 21
suid 19,0
)
)
uid 2769,0
)
*233 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "logic1"
t "std_ulogic"
o 13
suid 20,0
)
)
uid 2771,0
)
*234 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "logic0"
t "std_ulogic"
o 12
suid 21,0
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uid 2773,0
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pdm (PhysicalDM
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editShortBounds 1
uid 2791,0
optionalChildren [
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font "Tahoma,10,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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pos 21
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uid 2793,0
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litem &202
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pos 2
hidden 1
dimension 20
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litem &215
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dimension 20
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litem &216
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dimension 20
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pos 3
dimension 20
uid 2740,0
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dimension 20
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pos 5
dimension 20
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pos 6
dimension 20
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dimension 20
uid 2750,0
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dimension 20
uid 2752,0
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litem &224
pos 10
dimension 20
uid 2754,0
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litem &225
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dimension 20
uid 2756,0
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litem &226
pos 12
dimension 20
uid 2758,0
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dimension 20
uid 2760,0
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*254 (MRCItem
litem &228
pos 14
dimension 20
uid 2762,0
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*255 (MRCItem
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pos 15
dimension 20
uid 2764,0
)
*256 (MRCItem
litem &230
pos 16
dimension 20
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pos 17
dimension 20
uid 2768,0
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*258 (MRCItem
litem &232
pos 18
dimension 20
uid 2770,0
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dimension 20
uid 2772,0
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pos 20
dimension 20
uid 2774,0
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sheetCol (SheetCol
propVa (MVa
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uid 2797,0
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litem &208
pos 2
dimension 100
uid 2800,0
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litem &209
pos 3
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*265 (MRCItem
litem &210
pos 4
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pos 5
dimension 100
uid 2803,0
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litem &212
pos 6
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pos 7
dimension 80
uid 2805,0
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fixedCol 4
fixedRow 2
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vaOverrides [
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genericsCommonDM (CommonDM
ldm (LogicalDM
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uid 2807,0
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*272 (FilterRowHdr
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*273 (RefLabelColHdr
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*274 (RowExpandColHdr
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*275 (GroupColHdr
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*276 (NameColHdr
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*277 (TypeColHdr
tm "GenericTypeColHdrMgr"
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*278 (InitColHdr
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*279 (PragmaColHdr
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*280 (EolColHdr
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*281 (LogGeneric
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uid 2854,0
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uid 2856,0
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pdm (PhysicalDM
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
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font "Tahoma,10,0"
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dimension 20
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uid 2821,0
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*287 (MRCItem
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hidden 1
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pos 0
dimension 20
uid 2853,0
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*289 (MRCItem
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dimension 20
uid 2855,0
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sheetCol (SheetCol
propVa (MVa
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uid 2825,0
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*292 (MRCItem
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*293 (MRCItem
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pos 3
dimension 100
uid 2829,0
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*294 (MRCItem
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pos 4
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uid 2830,0
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*295 (MRCItem
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pos 5
dimension 50
uid 2831,0
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*296 (MRCItem
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uid 2832,0
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fixedCol 3
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uid 2806,0
type 1
)
activeModelName "BlockDiag"
)