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variable "version" value "2007.1a (Build 13)" ) (vvPair variable "view" value "interface" ) (vvPair variable "year" value "2010" ) (vvPair variable "yy" value "10" ) ] ) LanguageMgr "VhdlLangMgr" uid 71,0 optionalChildren [ *63 (SymbolBody uid 8,0 optionalChildren [ *64 (CptPort uid 183,0 ps "OnEdgeStrategy" shape (Triangle uid 184,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "22625,5250,23375,6000" ) tg (CPTG uid 185,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 186,0 ro 270 va (VaSet ) xt "22500,7000,23500,9100" st "clock" ju 2 blo "23300,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 187,0 va (VaSet font "Courier New,8,0" ) xt "44000,4400,62000,5200" st "clock : OUT std_ulogic ; " ) thePort (LogicalPort m 1 decl (Decl n "clock" t "std_ulogic" o 3 suid 2005,0 ) ) ) *65 (CptPort uid 188,0 ps "OnEdgeStrategy" shape (Triangle uid 189,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "24625,5250,25375,6000" ) tg (CPTG uid 190,0 ps "CptPortTextPlaceStrategy" stg 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"1000,1000,4400,2200" st "Panel0" blo "1000,2000" tm "PanelText" ) ) ) parentGraphicsRef (HdmGraphicsRef libraryName "SineInterpolator_test" entityName "FPGA_sineGen_tb" viewName "struct.bd" ) defaultSymbolBody (SymbolBody shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,35000,26000" ) biTextGroup (BiTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet font "Verdana,9,1" ) xt "22600,14800,27400,16000" st "" blo "22600,15800" ) second (Text va (VaSet font "Verdana,9,1" ) xt "22600,16000,25900,17200" st "" blo "22600,17000" ) ) gi *84 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 font "Courier New,8,0" ) xt "0,12000,0,12000" ) header "Generic Declarations" ) elements [ ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay ) ) defaultCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) 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