DocumentHdrVersion "1.1" Header (DocumentHdr version 2 dialect 10 dmPackageRefs [ (DmPackageRef library "ieee" unitName "std_logic_1164" ) (DmPackageRef library "ieee" unitName "numeric_std" itemName "ALL" ) ] libraryRefs [ "ieee" ] ) version "27.1" appVersion "2019.2 (Build 5)" model (Symbol commonDM (CommonDM ldm (LogicalDM suid 12,0 usingSuid 1 emptyRow *1 (LEmptyRow ) uid 74,0 optionalChildren [ *2 (RefLabelRowHdr ) *3 (TitleRowHdr ) *4 (FilterRowHdr ) *5 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *6 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *7 (GroupColHdr tm "GroupColHdrMgr" ) *8 (NameColHdr tm "NameColHdrMgr" ) *9 (ModeColHdr tm "ModeColHdrMgr" ) *10 (TypeColHdr tm "TypeColHdrMgr" ) *11 (BoundsColHdr tm "BoundsColHdrMgr" ) *12 (InitColHdr tm "InitColHdrMgr" ) *13 (EolColHdr tm "EolColHdrMgr" ) *14 (LogPort port (LogicalPort m 1 decl (Decl n "clock" t "std_ulogic" o 1 suid 10,0 ) ) uid 303,0 ) *15 (LogPort port (LogicalPort decl (Decl n "countOut" t "unsigned" b "(counterBitNb-1 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(PragmaColHdr tm "GenericPragmaColHdrMgr" ) *44 (EolColHdr tm "GenericEolColHdrMgr" ) *45 (LogGeneric generic (GiElement name "counterBitNb" type "positive" value "32" ) uid 152,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 115,0 optionalChildren [ *46 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *47 (MRCItem litem &33 pos 1 dimension 20 ) uid 117,0 optionalChildren [ *48 (MRCItem litem &34 pos 0 dimension 20 uid 118,0 ) *49 (MRCItem litem &35 pos 1 dimension 23 uid 119,0 ) *50 (MRCItem litem &36 pos 2 hidden 1 dimension 20 uid 120,0 ) *51 (MRCItem litem &45 pos 0 dimension 20 uid 153,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 121,0 optionalChildren [ *52 (MRCItem litem &37 pos 0 dimension 20 uid 122,0 ) *53 (MRCItem litem &39 pos 1 dimension 50 uid 123,0 ) *54 (MRCItem litem &40 pos 2 dimension 100 uid 124,0 ) *55 (MRCItem litem &41 pos 3 dimension 100 uid 125,0 ) *56 (MRCItem litem &42 pos 4 dimension 50 uid 126,0 ) *57 (MRCItem litem &43 pos 5 dimension 50 uid 127,0 ) *58 (MRCItem litem &44 pos 6 dimension 80 uid 128,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 116,0 vaOverrides [ ] ) ] ) uid 102,0 type 1 ) VExpander (VariableExpander vvMap [ (vvPair variable "HDLDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl" ) (vvPair variable "HDSDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds" ) (vvPair variable "SideDataDesignDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester\\interface.info" ) (vvPair variable "SideDataUserDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester\\interface.user" ) (vvPair variable "SourceDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "interface" ) (vvPair variable "asm_file" value "beamer.asm" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester" ) (vvPair variable "d_logical" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tester" ) (vvPair variable "date" value "02/17/2020" ) (vvPair variable "day" value "Mon" ) (vvPair variable "day_long" value "Monday" ) (vvPair variable "dd" value "17" ) (vvPair variable "designName" value "$DESIGN_NAME" ) (vvPair variable "entity_name" value "pipelineCounter_tester" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "interface" ) (vvPair variable "f_logical" value "interface" ) (vvPair variable "f_noext" value "interface" ) (vvPair variable "graphical_source_author" value "zas" ) (vvPair variable "graphical_source_date" value "02/17/2020" ) (vvPair variable "graphical_source_group" value "UNKNOWN" ) (vvPair variable "graphical_source_host" value "ZELL" ) (vvPair variable "graphical_source_time" value "17:11:08" ) (vvPair variable "group" value "UNKNOWN" ) (vvPair variable "host" value "ZELL" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "PipelinedOperators_test" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/PipelinedOperators_test" ) (vvPair variable "mm" value "02" ) (vvPair variable "module_name" value "pipelineCounter_tester" ) (vvPair variable "month" value "Feb" ) (vvPair variable "month_long" value "February" ) (vvPair variable "p" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tester\\interface" ) (vvPair variable "p_logical" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tester\\interface" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_AsmPath" value "$HEI_LIBS_DIR/NanoBlaze/hdl" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$ISE_WORK_DIR" ) (vvPair variable "task_ModelSimPath" value "/usr/opt/Modelsim/modeltech/bin" ) (vvPair variable "this_ext" value "" ) (vvPair variable "this_file" value "interface" ) (vvPair variable "this_file_logical" value "interface" ) (vvPair variable "time" value "17:11:08" ) (vvPair variable "unit" value "pipelineCounter_tester" ) (vvPair variable "user" value "zas" ) (vvPair variable "version" value "2019.2 (Build 5)" ) (vvPair variable "view" value "interface" ) (vvPair variable "year" value "2020" ) (vvPair variable "yy" value "20" ) ] ) LanguageMgr "Vhdl2002LangMgr" uid 72,0 optionalChildren [ *59 (SymbolBody uid 8,0 optionalChildren [ *60 (CptPort uid 288,0 ps "OnEdgeStrategy" shape (Triangle uid 289,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "22625,5250,23375,6000" ) tg (CPTG uid 290,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 291,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "22300,7000,23700,10800" st "clock" ju 2 blo "23500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 292,0 va (VaSet font "Courier New,8,0" ) xt "44000,2600,61000,3400" st "clock : OUT std_ulogic ; " ) thePort (LogicalPort m 1 decl (Decl n "clock" t "std_ulogic" o 1 suid 10,0 ) ) ) *61 (CptPort uid 293,0 ps "OnEdgeStrategy" shape (Triangle uid 294,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "46625,5250,47375,6000" ) tg (CPTG uid 295,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 296,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "46300,7000,47700,13600" st "countOut" ju 2 blo "47500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 297,0 va (VaSet font "Courier New,8,0" ) xt "44000,1800,73000,2600" st "countOut : IN unsigned (counterBitNb-1 downto 0) ; " ) thePort (LogicalPort decl (Decl n "countOut" t "unsigned" b "(counterBitNb-1 downto 0)" o 2 suid 11,0 ) ) ) *62 (CptPort uid 298,0 ps "OnEdgeStrategy" shape (Triangle uid 299,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "24625,5250,25375,6000" ) tg (CPTG uid 300,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 301,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "24300,7000,25700,11100" st "reset" ju 2 blo "25500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 302,0 va (VaSet font "Courier New,8,0" ) xt "44000,3400,60000,4200" st "reset : OUT std_ulogic " ) thePort (LogicalPort m 1 decl (Decl n "reset" t "std_ulogic" o 3 suid 12,0 ) ) ) ] shape (Rectangle uid 9,0 va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,55000,14000" ) biTextGroup (BiTextGroup uid 10,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text uid 11,0 va (VaSet font "Verdana,8,1" ) xt "28450,9050,41550,10050" st "PipelinedOperators_test" blo "28450,9850" ) second (Text uid 12,0 va (VaSet font "Verdana,8,1" ) xt "28450,10050,40950,11050" st "pipelineCounter_tester" blo "28450,10850" ) ) gi *63 (GenericInterface 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"Verdana,8,0" ) xt "0,900,13600,3900" st "LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.ALL;" tm "PackageList" ) ] ) windowSize "57,32,1072,722" viewArea "-500,-500,83100,45260" cachedDiagramExtent "0,0,71500,51000" hasePageBreakOrigin 1 pageBreakOrigin "0,0" defaultCommentText (CommentText shape (Rectangle layer 0 va (VaSet vasetType 1 fg "65280,65280,46080" lineColor "0,0,32768" ) xt "0,0,15000,5000" ) text (MLText va (VaSet fg "0,0,32768" font "Verdana,8,0" ) xt "200,200,2500,1200" st " Text " tm "CommentText" wrapOption 3 visibleHeight 4600 visibleWidth 14600 ) ) defaultRequirementText (RequirementText shape (ZoomableIcon layer 0 va (VaSet vasetType 1 fg "59904,39936,65280" lineColor "0,0,32768" ) xt "0,0,1500,1750" iconName "reqTracerRequirement.bmp" iconMaskName "reqTracerRequirement.msk" ) autoResize 1 text (MLText va (VaSet fg "0,0,32768" font "Verdana,8,0" ) xt "450,2150,1450,3150" st " Text " tm "RequirementText" wrapOption 3 visibleHeight 1350 visibleWidth 1100 ) ) defaultPanel (Panel shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "32768,0,0" lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (Text va (VaSet font "Verdana,8,1" ) xt "1000,1000,4000,1900" st "Panel0" blo "1000,1700" tm "PanelText" ) ) ) parentGraphicsRef (HdmGraphicsRef libraryName "PipelinedOperators_test" entityName "pipelineCounter_tb" viewName "struct.bd" ) defaultSymbolBody (SymbolBody shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,39000,26000" ) biTextGroup (BiTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet font "Verdana,8,1" ) xt "24750,15100,29250,16000" st "" blo "24750,15800" ) second (Text va (VaSet font "Verdana,8,1" ) xt "24750,16000,27750,16900" st "" blo "24750,16700" ) ) gi *78 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix text (MLText va (VaSet font "Verdana,8,0" ) xt "0,12000,9700,13000" st "Generic Declarations" ) header "Generic Declarations" showHdrWhenContentsEmpty 1 ) elements [ ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay sIVOD 1 ) portVis (PortSigDisplay sIVOD 1 ) ) defaultCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet font "Verdana,8,0" ) xt "0,750,1500,1650" st "In0" blo "0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "Verdana,8,0" ) ) thePort (LogicalPort lang 10 decl (Decl n "In0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) defaultCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" bg "0,0,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet font "Verdana,8,0" ) xt "0,750,3500,1650" st "Buffer0" blo "0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "Verdana,8,0" ) ) thePort (LogicalPort lang 10 m 3 decl (Decl n "Buffer0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) DeclarativeBlock *79 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" declLabel (Text uid 2,0 va (VaSet font "Verdana,8,1" ) xt "42000,0,48500,900" st "Declarations" blo "42000,700" ) portLabel (Text uid 3,0 va (VaSet font "Verdana,8,1" ) xt "42000,900,45000,1800" st "Ports:" blo "42000,1600" ) externalLabel (Text uid 4,0 va (VaSet font "Verdana,8,1" ) xt "42000,4200,44500,5100" st "User:" blo "42000,4900" ) internalLabel (Text uid 6,0 va (VaSet isHidden 1 font "Verdana,8,1" ) xt "42000,0,49500,900" st "Internal User:" blo "42000,700" ) externalText (MLText uid 5,0 va (VaSet font "Verdana,8,0" ) xt "44000,5100,44000,5100" tm "SyDeclarativeTextMgr" ) internalText (MLText uid 7,0 va (VaSet isHidden 1 font "Verdana,8,0" ) xt "42000,0,42000,0" tm "SyDeclarativeTextMgr" ) ) lastUid 308,0 activeModelName "Symbol:GEN" )