-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 17:45:49 01.05.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY lissajousGenerator_circuit_EBS3 IS
    PORT( 
        clock      : IN     std_ulogic;
        reset_N    : IN     std_ulogic;
        triggerOut : OUT    std_ulogic;
        xOut       : OUT    std_ulogic;
        yOut       : OUT    std_ulogic
    );

-- Declarations

END lissajousGenerator_circuit_EBS3 ;