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library "ieee"
unitName "std_logic_1164"
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library "ieee"
unitName "numeric_std"
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library "AhbLite"
unitName "ahbLite"
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version "32.1"
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variable "date"
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(vvPair
variable "day"
value "ven."
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(vvPair
variable "day_long"
value "vendredi"
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(vvPair
variable "dd"
value "28"
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variable "designName"
value "$DESIGN_NAME"
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variable "entity_name"
value "ahbGpio_tb"
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variable "ext"
value "<TBD>"
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variable "f"
value "struct.bd"
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variable "f_logical"
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variable "f_noext"
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value "axel.amand"
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value "28.04.2023"
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variable "graphical_source_group"
value "UNKNOWN"
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variable "graphical_source_host"
value "WE7860"
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variable "graphical_source_time"
value "15:06:49"
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variable "group"
value "UNKNOWN"
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variable "host"
value "WE7860"
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variable "language"
value "VHDL"
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variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/AhbLiteComponents_test"
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variable "mm"
value "04"
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variable "module_name"
value "ahbGpio_tb"
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variable "month"
value "avr."
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variable "month_long"
value "avril"
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variable "project_name"
value "hds"
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(vvPair
variable "series"
value "HDL Designer Series"
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(vvPair
variable "task_ADMS"
value "<TBD>"
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variable "task_AsmPath"
value "$HDS_LIBS_DIR\\NanoBlaze\\hdl"
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(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
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(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
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value "$ISE_HOME"
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(vvPair
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value "$ISE_SCRATCH_WORK_DIR"
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(vvPair
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)
xt "71250,48625,72000,49375"
)
tg (CPTG
uid 13164,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13165,0
va (VaSet
font "Verdana,12,0"
)
xt "73000,48300,78500,49700"
st "hReady"
blo "73000,49500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_uLogic"
o 7
suid 2061,0
)
)
)
*33 (CptPort
uid 13166,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13167,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,50625,72000,51375"
)
tg (CPTG
uid 13168,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13169,0
va (VaSet
font "Verdana,12,0"
)
xt "73000,50300,77700,51700"
st "hResp"
blo "73000,51500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_uLogic"
o 9
suid 2062,0
)
)
)
*34 (CptPort
uid 13170,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13171,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,54625,72000,55375"
)
tg (CPTG
uid 13172,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13173,0
va (VaSet
font "Verdana,12,0"
)
xt "73000,54300,76500,55700"
st "hClk"
blo "73000,55500"
)
)
thePort (LogicalPort
decl (Decl
n "hClk"
t "std_uLogic"
o 5
suid 2063,0
)
)
)
*35 (CptPort
uid 13174,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13175,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,56625,72000,57375"
)
tg (CPTG
uid 13176,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13177,0
va (VaSet
font "Verdana,12,0"
)
xt "73000,56300,79800,57700"
st "hReset_n"
blo "73000,57500"
)
)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_uLogic"
o 8
suid 2064,0
)
)
)
*36 (CptPort
uid 13178,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13179,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88000,38625,88750,39375"
)
tg (CPTG
uid 13180,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 13181,0
va (VaSet
font "Verdana,12,0"
)
xt "82800,38300,87000,39700"
st "ioOut"
ju 2
blo "87000,39500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 10
suid 2065,0
)
)
)
*37 (CptPort
uid 13182,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13183,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,44625,72000,45375"
)
tg (CPTG
uid 13184,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13185,0
va (VaSet
font "Verdana,12,0"
)
xt "73000,44300,76500,45700"
st "hSel"
blo "73000,45500"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_uLogic"
o 11
suid 2066,0
)
)
)
*38 (CptPort
uid 13186,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13187,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88000,40625,88750,41375"
)
tg (CPTG
uid 13188,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 13189,0
va (VaSet
font "Verdana,12,0"
)
xt "83800,40300,87000,41700"
st "ioIn"
ju 2
blo "87000,41500"
)
)
thePort (LogicalPort
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 12
suid 2067,0
)
)
)
*39 (CptPort
uid 13190,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13191,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "88000,36625,88750,37375"
)
tg (CPTG
uid 13192,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 13193,0
va (VaSet
font "Verdana,12,0"
)
xt "83500,36300,87000,37700"
st "ioEn"
ju 2
blo "87000,37500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 13
suid 2068,0
)
)
)
]
shape (Rectangle
uid 13195,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "72000,33000,88000,59000"
)
oxt "47000,16000,63000,42000"
ttg (MlTextGroup
uid 13196,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*40 (Text
uid 13197,0
va (VaSet
)
xt "72100,58700,79600,59700"
st "AhbLiteComponents"
blo "72100,59500"
tm "BdLibraryNameMgr"
)
*41 (Text
uid 13198,0
va (VaSet
)
xt "72100,59700,75300,60700"
st "ahbGpio"
blo "72100,60500"
tm "CptNameMgr"
)
*42 (Text
uid 13199,0
va (VaSet
)
xt "72100,60700,74800,61700"
st "I_DUT"
blo "72100,61500"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 13200,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 13201,0
text (MLText
uid 13202,0
va (VaSet
font "Courier New,8,0"
)
xt "72000,63000,88000,63800"
st "ioNb = ioNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "ioNb"
type "positive"
value "ioNb"
)
]
)
viewicon (ZoomableIcon
uid 13203,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "72250,57250,73750,58750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*43 (HdlText
uid 13204,0
optionalChildren [
*44 (EmbeddedText
uid 13246,0
commentText (CommentText
uid 13247,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 13248,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "104000,34000,120000,44000"
)
oxt "0,0,18000,5000"
text (MLText
uid 13249,0
va (VaSet
)
xt "104200,34200,119200,43800"
st "
tristate: process(ioEn, ioOut)
begin
  for index in io'range loop
    if ioEn(index) = '1' then
      io(index) <= ioOut(index);
    else
      io(index) <= 'Z';
    end if;
  end loop;
end process tristate;

ioIn <= std_ulogic_vector(io);

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 13205,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "104000,33000,120000,45000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 13206,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*45 (Text
uid 13207,0
va (VaSet
font "Verdana,8,1"
)
xt "103850,45000,106150,46000"
st "eb1"
blo "103850,45800"
tm "HdlTextNameMgr"
)
*46 (Text
uid 13208,0
va (VaSet
font "Verdana,8,1"
)
xt "103850,46000,105050,47000"
st "1"
blo "103850,46800"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
uid 13209,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "104250,43250,105750,44750"
iconName "TextFile.png"
iconMaskName "TextFile.msk"
ftype 21
)
viewiconposition 0
)
*47 (Net
uid 13210,0
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 12
suid 118,0
)
declText (MLText
uid 13211,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,28000,1200"
st "SIGNAL ioEn     : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
)
)
*48 (Net
uid 13218,0
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 14
suid 119,0
)
declText (MLText
uid 13219,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,28000,1200"
st "SIGNAL ioOut    : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
)
)
*49 (Net
uid 13226,0
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 13
suid 120,0
)
declText (MLText
uid 13227,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,28000,1200"
st "SIGNAL ioIn     : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
)
)
*50 (Net
uid 13244,0
decl (Decl
n "io"
t "std_logic_vector"
b "(ioNb-1 DOWNTO 0)"
o 11
suid 122,0
)
declText (MLText
uid 13245,0
va (VaSet
isHidden 1
font "Courier New,9,0"
)
xt "0,0,27500,1200"
st "SIGNAL io       : std_logic_vector(ioNb-1 DOWNTO 0)
"
)
)
*51 (Wire
uid 12557,0
shape (OrthoPolyLine
uid 12558,0
va (VaSet
vasetType 3
)
xt "70000,57000,71250,67000"
pts [
"71250,57000"
"70000,57000"
"70000,67000"
]
)
start &35
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12561,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12562,0
va (VaSet
font "Verdana,12,0"
)
xt "63250,55600,70050,57000"
st "hReset_n"
blo "63250,56800"
tm "WireNameMgr"
)
)
on &12
)
*52 (Wire
uid 12565,0
shape (OrthoPolyLine
uid 12566,0
va (VaSet
vasetType 3
)
xt "68000,55000,71250,67000"
pts [
"71250,55000"
"68000,55000"
"68000,67000"
]
)
start &34
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12569,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12570,0
va (VaSet
font "Verdana,12,0"
)
xt "66250,53600,69750,55000"
st "hClk"
blo "66250,54800"
tm "WireNameMgr"
)
)
on &13
)
*53 (Wire
uid 12573,0
shape (OrthoPolyLine
uid 12574,0
va (VaSet
vasetType 3
)
xt "64000,51000,71250,67000"
pts [
"71250,51000"
"64000,51000"
"64000,67000"
]
)
start &33
end &22
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12577,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12578,0
va (VaSet
font "Verdana,12,0"
)
xt "65250,49600,69950,51000"
st "hResp"
blo "65250,50800"
tm "WireNameMgr"
)
)
on &14
)
*54 (Wire
uid 12581,0
shape (OrthoPolyLine
uid 12582,0
va (VaSet
vasetType 3
)
xt "62000,49000,71250,67000"
pts [
"71250,49000"
"62000,49000"
"62000,67000"
]
)
start &32
end &22
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12585,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12586,0
va (VaSet
font "Verdana,12,0"
)
xt "64250,47600,69750,49000"
st "hReady"
blo "64250,48800"
tm "WireNameMgr"
)
)
on &15
)
*55 (Wire
uid 12589,0
shape (OrthoPolyLine
uid 12590,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "60000,47000,71250,67000"
pts [
"71250,47000"
"60000,47000"
"60000,67000"
]
)
start &29
end &22
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12593,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12594,0
va (VaSet
font "Verdana,12,0"
)
xt "65250,45600,70650,47000"
st "hRData"
blo "65250,46800"
tm "WireNameMgr"
)
)
on &16
)
*56 (Wire
uid 12597,0
shape (OrthoPolyLine
uid 12598,0
va (VaSet
vasetType 3
)
xt "58000,45000,71250,67000"
pts [
"71250,45000"
"58000,45000"
"58000,67000"
]
)
start &37
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12601,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12602,0
va (VaSet
font "Verdana,12,0"
)
xt "66250,43600,69750,45000"
st "hSel"
blo "66250,44800"
tm "WireNameMgr"
)
)
on &17
)
*57 (Wire
uid 12605,0
shape (OrthoPolyLine
uid 12606,0
va (VaSet
vasetType 3
)
xt "56000,43000,71250,67000"
pts [
"71250,43000"
"56000,43000"
"56000,67000"
]
)
start &30
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12609,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12610,0
va (VaSet
font "Verdana,12,0"
)
xt "65250,41600,70250,43000"
st "hWrite"
blo "65250,42800"
tm "WireNameMgr"
)
)
on &18
)
*58 (Wire
uid 12613,0
shape (OrthoPolyLine
uid 12614,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "54000,41000,71250,67000"
pts [
"71250,41000"
"54000,41000"
"54000,67000"
]
)
start &31
end &22
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12617,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12618,0
va (VaSet
font "Verdana,12,0"
)
xt "65250,39600,70350,41000"
st "hTrans"
blo "65250,40800"
tm "WireNameMgr"
)
)
on &19
)
*59 (Wire
uid 12621,0
shape (OrthoPolyLine
uid 12622,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "52000,39000,71250,67000"
pts [
"71250,39000"
"52000,39000"
"52000,67000"
]
)
start &28
end &22
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12625,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12626,0
va (VaSet
font "Verdana,12,0"
)
xt "64250,37600,70150,39000"
st "hWData"
blo "64250,38800"
tm "WireNameMgr"
)
)
on &20
)
*60 (Wire
uid 12629,0
shape (OrthoPolyLine
uid 12630,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "50000,37000,71250,67000"
pts [
"71250,37000"
"50000,37000"
"50000,67000"
]
)
start &27
end &22
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12633,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12634,0
va (VaSet
font "Verdana,12,0"
)
xt "65250,35600,69750,37000"
st "hAddr"
blo "65250,36800"
tm "WireNameMgr"
)
)
on &21
)
*61 (Wire
uid 13212,0
shape (OrthoPolyLine
uid 13213,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "88750,37000,104000,37000"
pts [
"88750,37000"
"104000,37000"
]
)
start &39
end &43
sat 32
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 13216,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13217,0
va (VaSet
font "Verdana,12,0"
)
xt "90750,35600,94250,37000"
st "ioEn"
blo "90750,36800"
tm "WireNameMgr"
)
)
on &47
)
*62 (Wire
uid 13220,0
shape (OrthoPolyLine
uid 13221,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "88750,39000,104000,39000"
pts [
"88750,39000"
"104000,39000"
]
)
start &36
end &43
sat 32
eat 1
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 13224,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13225,0
va (VaSet
font "Verdana,12,0"
)
xt "90750,37600,94950,39000"
st "ioOut"
blo "90750,38800"
tm "WireNameMgr"
)
)
on &48
)
*63 (Wire
uid 13228,0
shape (OrthoPolyLine
uid 13229,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "88750,41000,104000,41000"
pts [
"88750,41000"
"104000,41000"
]
)
start &38
end &43
sat 32
eat 2
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 13232,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13233,0
va (VaSet
font "Verdana,12,0"
)
xt "90750,39600,93950,41000"
st "ioIn"
blo "90750,40800"
tm "WireNameMgr"
)
)
on &49
)
*64 (Wire
uid 13236,0
shape (OrthoPolyLine
uid 13237,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "120000,37000,124000,67000"
pts [
"120000,37000"
"124000,37000"
"124000,67000"
]
)
start &43
end &22
sat 4
eat 4
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13242,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13243,0
va (VaSet
font "Verdana,12,0"
)
xt "122000,35600,123900,37000"
st "io"
blo "122000,36800"
tm "WireNameMgr"
)
)
on &50
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "32768,32768,32768"
)
packageList *65 (PackageList
uid 187,0
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
uid 1297,0
va (VaSet
font "Verdana,8,1"
)
xt "29000,19000,35900,20000"
st "Package List"
blo "29000,19800"
)
*67 (MLText
uid 1298,0
va (VaSet
)
xt "29000,20000,46500,26000"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;
LIBRARY AhbLite;
  USE AhbLite.ahbLite.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 190,0
stg "VerticalLayoutStrategy"
textVec [
*68 (Text
uid 191,0
va (VaSet
isHidden 1
font "arial,10,1"
)
xt "20000,0,31000,1200"
st "Compiler Directives"
blo "20000,1000"
)
*69 (Text
uid 192,0
va (VaSet
isHidden 1
font "arial,10,1"
)
xt "20000,1400,33000,2600"
st "Pre-module directives:"
blo "20000,2400"
)
*70 (MLText
uid 193,0
va (VaSet
isHidden 1
font "arial,10,0"
)
xt "20000,2800,30400,5400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*71 (Text
uid 194,0
va (VaSet
isHidden 1
font "arial,10,1"
)
xt "20000,5600,33500,6800"
st "Post-module directives:"
blo "20000,6600"
)
*72 (MLText
uid 195,0
va (VaSet
isHidden 1
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