DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
]
instances [
(Instance
name "I_cnt"
duLibraryName "Morse"
duName "unitCounter"
elements [
(GiElement
name "unitCountDivide"
type "positive"
value "unitCountDivide"
)
(GiElement
name "unitCountBitNb"
type "positive"
value "unitCountBitNb"
)
]
mwi 0
uid 427,0
)
(Instance
name "I_ctl"
duLibraryName "Morse"
duName "charToMorseController"
elements [
(GiElement
name "characterBitNb"
type "positive"
value "characterBitNb"
)
(GiElement
name "unitCountBitNb"
type "positive"
value "unitCountBitNb"
)
]
mwi 0
uid 806,0
)
]
libraryRefs [
"ieee"
]
)
version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "asm_file"
value "beamer.asm"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse"
)
(vvPair
variable "d_logical"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse"
)
(vvPair
variable "date"
value "10.04.2024"
)
(vvPair
variable "day"
value "mer."
)
(vvPair
variable "day_long"
value "mercredi"
)
(vvPair
variable "dd"
value "10"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "charToMorse"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "remi.heredero"
)
(vvPair
variable "graphical_source_date"
value "10.04.2024"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE2330808"
)
(vvPair
variable "graphical_source_time"
value "13:09:12"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE2330808"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Morse"
)
(vvPair
variable "library_downstream_Concatenation"
value "$HDS_PROJECT_DIR/../Morse/concat"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Morse"
)
(vvPair
variable "mm"
value "04"
)
(vvPair
variable "module_name"
value "charToMorse"
)
(vvPair
variable "month"
value "avr."
)
(vvPair
variable "month_long"
value "avril"
)
(vvPair
variable "p"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\char@to@morse\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\05-Morse\\Prefs\\..\\Morse\\hds\\charToMorse\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_AsmPath"
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$ISE_WORK_DIR"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME/modeltech/bin"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "13:09:12"
)
(vvPair
variable "unit"
value "charToMorse"
)
(vvPair
variable "user"
value "remi.heredero"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2024"
)
(vvPair
variable "yy"
value "24"
)
]
)
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stc 0
sf 1
tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "42000,26500,47700,27700"
st "morseOut"
blo "42000,27500"
tm "WireNameMgr"
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)
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suid 1,0
)
declText (MLText
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tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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xt "600,34500,4000,35700"
st "clock"
ju 2
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decl (Decl
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declText (MLText
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va (VaSet
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xt "-5000,7700,8100,8900"
st "clock        : std_ulogic"
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shape (CompositeShape
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va (VaSet
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optionalChildren [
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tg (WTG
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declText (MLText
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
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blo "4000,27500"
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decl (Decl
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suid 5,0
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declText (MLText
uid 78,0
va (VaSet
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bg "0,0,32768"
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xt "53200,65500,53200,65500"
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tm "CommentText"
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titleBlock 1
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bg "0,0,32768"
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xt "70200,61500,70200,61500"
st "
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wrapOption 3
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bg "0,0,32768"
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xt "49200,63500,49200,63500"
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tm "CommentText"
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xt "74200,61500,74200,61500"
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ju 0
tm "CommentText"
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text (MLText
uid 116,0
va (VaSet
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bg "0,0,32768"
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xt "49200,64500,49200,64500"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
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shape (Rectangle
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text (MLText
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va (VaSet
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decl (Decl
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declText (MLText
uid 366,0
va (VaSet
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xt "-5000,14900,14200,16100"
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uid 371,0
decl (Decl
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declText (MLText
uid 372,0
va (VaSet
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xt "-5000,15800,12600,17000"
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decl (Decl
n "unitNb"
t "unsigned"
b "(unitCountBitNb-1 downto 0)"
o 8
suid 8,0
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declText (MLText
uid 378,0
va (VaSet
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matrix (Matrix
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header ""
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iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*32 (PortIoOut
uid 578,0
shape (CompositeShape
uid 579,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 580,0
sl 0
ro 90
xt "5000,30625,6500,31375"
)
(Line
uid 581,0
sl 0
ro 90
xt "6500,31000,7000,31000"
pts [
"7000,31000"
"6500,31000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 582,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 583,0
va (VaSet
isHidden 1
)
xt "-1300,30500,4000,31700"
st "readChar"
ju 2
blo "4000,31500"
tm "WireNameMgr"
)
)
)
*33 (Net
uid 590,0
decl (Decl
n "readChar"
t "std_ulogic"
o 5
suid 10,0
)
declText (MLText
uid 591,0
va (VaSet
)
xt "-5000,10400,9100,11600"
st "readChar     : std_ulogic"
)
)
*34 (PortIoIn
uid 627,0
shape (CompositeShape
uid 628,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 629,0
sl 0
ro 270
xt "5000,28625,6500,29375"
)
(Line
uid 630,0
sl 0
ro 270
xt "6500,29000,7000,29000"
pts [
"6500,29000"
"7000,29000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 631,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 632,0
va (VaSet
isHidden 1
)
xt "-4500,28500,4000,29700"
st "charNotReady"
ju 2
blo "4000,29500"
tm "WireNameMgr"
)
)
)
*35 (Net
uid 639,0
decl (Decl
n "charNotReady"
t "std_ulogic"
o 9
suid 11,0
)
declText (MLText
uid 640,0
va (VaSet
)
xt "-5000,11300,10400,12500"
st "charNotReady : std_ulogic"
)
)
*36 (SaComponent
uid 806,0
optionalChildren [
*37 (CptPort
uid 770,0
ps "OnEdgeStrategy"
shape (Triangle
uid 771,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "31000,26625,31750,27375"
)
tg (CPTG
uid 772,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 773,0
va (VaSet
)
xt "24300,26400,30000,27600"
st "morseOut"
ju 2
blo "30000,27400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "morseOut"
t "std_ulogic"
o 1
suid 2007,0
)
)
)
*38 (CptPort
uid 774,0
ps "OnEdgeStrategy"
shape (Triangle
uid 775,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,34625,15000,35375"
)
tg (CPTG
uid 776,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 777,0
va (VaSet
)
xt "16000,34400,19400,35600"
st "clock"
blo "16000,35400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2008,0
)
)
)
*39 (CptPort
uid 778,0
ps "OnEdgeStrategy"
shape (Triangle
uid 779,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,36625,15000,37375"
)
tg (CPTG
uid 780,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 781,0
va (VaSet
)
xt "16000,36400,19300,37600"
st "reset"
blo "16000,37400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 2009,0
)
)
)
*40 (CptPort
uid 782,0
ps "OnEdgeStrategy"
shape (Triangle
uid 783,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,28625,15000,29375"
)
tg (CPTG
uid 784,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 785,0
va (VaSet
)
xt "16000,28400,24500,29600"
st "charNotReady"
blo "16000,29400"
)
)
thePort (LogicalPort
decl (Decl
n "charNotReady"
t "std_ulogic"
o 4
suid 2010,0
)
)
)
*41 (CptPort
uid 786,0
ps "OnEdgeStrategy"
shape (Triangle
uid 787,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,26625,15000,27375"
)
tg (CPTG
uid 788,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 789,0
va (VaSet
)
xt "16000,26400,18900,27600"
st "char"
blo "16000,27400"
)
)
thePort (LogicalPort
decl (Decl
n "char"
t "std_ulogic_vector"
b "(characterBitNb-1 DOWNTO 0)"
o 5
suid 2011,0
)
)
)
*42 (CptPort
uid 790,0
ps "OnEdgeStrategy"
shape (Triangle
uid 791,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "31000,30625,31750,31375"
)
tg (CPTG
uid 792,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 793,0
va (VaSet
)
xt "22200,30400,30000,31600"
st "startCounter"
ju 2
blo "30000,31400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "startCounter"
t "std_ulogic"
o 6
suid 2012,0
)
)
)
*43 (CptPort
uid 794,0
ps "OnEdgeStrategy"
shape (Triangle
uid 795,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "31000,32625,31750,33375"
)
tg (CPTG
uid 796,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 797,0
va (VaSet
)
xt "26000,32400,30000,33600"
st "unitNb"
ju 2
blo "30000,33400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "unitNb"
t "unsigned"
b "(unitCountBitNb-1 downto 0)"
o 7
suid 2013,0
)
)
)
*44 (CptPort
uid 798,0
ps "OnEdgeStrategy"
shape (Triangle
uid 799,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "31000,34625,31750,35375"
)
tg (CPTG
uid 800,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 801,0
va (VaSet
)
xt "22200,34400,30000,35600"
st "counterDone"
ju 2
blo "30000,35400"
)
)
thePort (LogicalPort
decl (Decl
n "counterDone"
t "std_ulogic"
o 8
suid 2014,0
)
)
)
*45 (CptPort
uid 802,0
ps "OnEdgeStrategy"
shape (Triangle
uid 803,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,30625,15000,31375"
)
tg (CPTG
uid 804,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 805,0
va (VaSet
)
xt "16000,30550,21300,31750"
st "readChar"
blo "16000,31550"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "readChar"
t "std_ulogic"
o 9
suid 2015,0
)
)
)
]
shape (Rectangle
uid 807,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,23000,31000,39000"
)
oxt "40000,6000,56000,22000"
ttg (MlTextGroup
uid 808,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*46 (Text
uid 809,0
va (VaSet
font "Verdana,9,1"
)
xt "15600,38800,19100,40000"
st "Morse"
blo "15600,39800"
tm "BdLibraryNameMgr"
)
*47 (Text
uid 810,0
va (VaSet
font "Verdana,9,1"
)
xt "15600,39700,28500,40900"
st "charToMorseController"
blo "15600,40700"
tm "CptNameMgr"
)
*48 (Text
uid 811,0
va (VaSet
font "Verdana,9,1"
)
xt "15600,40600,18600,41800"
st "I_ctl"
blo "15600,41600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 812,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 813,0
text (MLText
uid 814,0
va (VaSet
)
xt "12000,42600,38700,45000"
st "characterBitNb = characterBitNb    ( positive )  
unitCountBitNb = unitCountBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "characterBitNb"
type "positive"
value "characterBitNb"
)
(GiElement
name "unitCountBitNb"
type "positive"
value "unitCountBitNb"
)
]
)
viewicon (ZoomableIcon
uid 815,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "15250,37250,16750,38750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*49 (Wire
uid 15,0
shape (OrthoPolyLine
uid 16,0
va (VaSet
vasetType 3
)
xt "31750,27000,39000,27000"
pts [
"39000,27000"
"31750,27000"
]
)
start &1
end &37
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 19,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20,0
va (VaSet
)
xt "36000,26000,41700,27200"
st "morseOut"
blo "36000,27000"
tm "WireNameMgr"
)
)
on &2
)
*50 (Wire
uid 29,0
shape (OrthoPolyLine
uid 30,0
va (VaSet
vasetType 3
)
xt "7000,35000,14250,35000"
pts [
"7000,35000"
"14250,35000"
]
)
start &3
end &38
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 33,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 34,0
va (VaSet
)
xt "7000,34000,10400,35200"
st "clock"
blo "7000,35000"
tm "WireNameMgr"
)
)
on &4
)
*51 (Wire
uid 43,0
shape (OrthoPolyLine
uid 44,0
va (VaSet
vasetType 3
)
xt "7000,37000,14250,37000"
pts [
"7000,37000"
"14250,37000"
]
)
start &5
end &39
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 47,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 48,0
va (VaSet
)
xt "7000,36000,10300,37200"
st "reset"
blo "7000,37000"
tm "WireNameMgr"
)
)
on &6
)
*52 (Wire
uid 71,0
shape (OrthoPolyLine
uid 72,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "7000,27000,14250,27000"
pts [
"7000,27000"
"14250,27000"
]
)
start &7
end &41
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 75,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 76,0
va (VaSet
)
xt "7000,26000,11000,27200"
st "charIn"
blo "7000,27000"
tm "WireNameMgr"
)
)
on &8
)
*53 (Wire
uid 367,0
shape (OrthoPolyLine
uid 368,0
va (VaSet
vasetType 3
)
xt "31750,31000,46250,31000"
pts [
"31750,31000"
"46250,31000"
]
)
start &42
end &26
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 369,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 370,0
va (VaSet
)
xt "34000,29800,41800,31000"
st "startCounter"
blo "34000,30800"
tm "WireNameMgr"
)
)
on &20
)
*54 (Wire
uid 373,0
shape (OrthoPolyLine
uid 374,0
va (VaSet
vasetType 3
)
xt "31750,31000,67000,45000"
pts [
"63750,31000"
"67000,31000"
"67000,45000"
"35000,45000"
"35000,35000"
"31750,35000"
]
)
start &28
end &44
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 375,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 376,0
va (VaSet
)
xt "65750,30000,68850,31200"
st "done"
blo "65750,31000"
tm "WireNameMgr"
)
)
on &21
)
*55 (Wire
uid 379,0
shape (OrthoPolyLine
uid 380,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "31750,33000,46250,33000"
pts [
"31750,33000"
"46250,33000"
]
)
start &43
end &27
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 381,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 382,0
va (VaSet
)
xt "34000,31800,38000,33000"
st "unitNb"
blo "34000,32800"
tm "WireNameMgr"
)
)
on &22
)
*56 (Wire
uid 389,0
shape (OrthoPolyLine
uid 390,0
va (VaSet
vasetType 3
)
xt "43000,39000,46250,39000"
pts [
"43000,39000"
"46250,39000"
]
)
end &25
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 395,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 396,0
va (VaSet
)
xt "43000,38000,46300,39200"
st "reset"
blo "43000,39000"
tm "WireNameMgr"
)
)
on &6
)
*57 (Wire
uid 397,0
shape (OrthoPolyLine
uid 398,0
va (VaSet
vasetType 3
)
xt "43000,37000,46250,37000"
pts [
"43000,37000"
"46250,37000"
]
)
end &24
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 403,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 404,0
va (VaSet
)
xt "43000,36000,46400,37200"
st "clock"
blo "43000,37000"
tm "WireNameMgr"
)
)
on &4
)
*58 (Wire
uid 584,0
shape (OrthoPolyLine
uid 585,0
va (VaSet
vasetType 3
)
xt "7000,31000,14250,31000"
pts [
"14250,31000"
"7000,31000"
]
)
start &45
end &32
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 588,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 589,0
va (VaSet
)
xt "7000,30000,12300,31200"
st "readChar"
blo "7000,31000"
tm "WireNameMgr"
)
)
on &33
)
*59 (Wire
uid 633,0
shape (OrthoPolyLine
uid 634,0
va (VaSet
vasetType 3
)
xt "7000,29000,14250,29000"
pts [
"7000,29000"
"14250,29000"
]
)
start &34
end &40
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 637,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 638,0
va (VaSet
)
xt "7000,28000,15500,29200"
st "charNotReady"
blo "7000,29000"
tm "WireNameMgr"
)
)
on &35
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *60 (PackageList
uid 123,0
stg "VerticalLayoutStrategy"
textVec [
*61 (Text
uid 124,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,0,-100,1000"
st "Package List"
blo "-7000,800"
)
*62 (MLText
uid 125,0
va (VaSet
)
xt "-7000,1000,10500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 126,0
stg "VerticalLayoutStrategy"
textVec [
*63 (Text
uid 127,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30200,1000"
st "Compiler Directives"
blo "20000,800"
)
*64 (Text
uid 128,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,32200,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*65 (MLText
uid 129,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*66 (Text
uid 130,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32800,5000"
st "Post-module directives:"
blo "20000,4800"
)
*67 (MLText
uid 131,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*68 (Text
uid 132,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,32400,6000"
st "End-module directives:"
blo "20000,5800"
)
*69 (MLText
uid 133,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "301,100,1557,827"
viewArea "-750,11425,76350,54400"
cachedDiagramExtent "-7000,0,90000,66000"
pageSetupInfo (PageSetupInfo
ptrCmd ""
toPrinter 1
xMargin 48
yMargin 48
paperWidth 761
paperHeight 1077
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4"
windowsPaperType 9
scale 75
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
exportStdIncludeRefs 1
exportStdPackageRefs 1
)
hasePageBreakOrigin 1
pageBreakOrigin "-7000,0"
lastUid 950,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "450,2150,1450,3350"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,8,1"
)
xt "1000,1000,3800,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*70 (Text
va (VaSet
font "Verdana,8,1"
)
xt "2200,3500,5800,4500"
st "<library>"
blo "2200,4300"
tm "BdLibraryNameMgr"
)
*71 (Text
va (VaSet
font "Verdana,8,1"
)
xt "2200,4500,5600,5500"
st "<block>"
blo "2200,5300"
tm "BlkNameMgr"
)
*72 (Text
va (VaSet
font "Verdana,8,1"
)
xt "2200,5500,4000,6500"
st "U_0"
blo "2200,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
)
xt "2200,13500,2200,13500"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "0,0,8000,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
font "Verdana,8,1"
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xt "550,3500,3450,4500"
st "Library"
blo "550,4300"
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va (VaSet
font "Verdana,8,1"
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xt "550,4500,7450,5500"
st "MWComponent"
blo "550,5300"
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va (VaSet
font "Verdana,8,1"
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xt "550,5500,2350,6500"
st "U_0"
blo "550,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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xt "-6450,1500,-6450,1500"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
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lineColor "0,32896,0"
lineWidth 2
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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tm "BdLibraryNameMgr"
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blo "900,5300"
tm "CptNameMgr"
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va (VaSet
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st "U_0"
blo "900,6300"
tm "InstanceNameMgr"
)
]
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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xt "-6100,1500,-6100,1500"
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header ""
)
elements [
]
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viewicon (ZoomableIcon
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va (VaSet
vasetType 1
fg "49152,49152,49152"
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xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
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viewiconposition 0
portVis (PortSigDisplay
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archFileType "UNKNOWN"
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defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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xt "500,3500,3400,4500"
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blo "500,4300"
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va (VaSet
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xt "500,4500,7500,5500"
st "VhdlComponent"
blo "500,5300"
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va (VaSet
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xt "500,5500,2300,6500"
st "U_0"
blo "500,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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xt "-6500,1500,-6500,1500"
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header ""
)
elements [
]
)
portVis (PortSigDisplay
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entityPath ""
archName ""
archPath ""
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shape (Rectangle
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vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "-450,0,8450,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "50,6300"
tm "InstanceNameMgr"
)
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)
ga (GenericAssociation
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matrix (Matrix
text (MLText
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header ""
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elements [
]
)
entityPath ""
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defaultHdlText (HdlText
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vasetType 1
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lineWidth 2
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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tm "HdlTextNameMgr"
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blo "3150,5800"
tm "HdlTextNumberMgr"
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viewicon (ZoomableIcon
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va (VaSet
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xt "0,0,1500,1500"
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iconMaskName "UnknownFile.msk"
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viewiconposition 0
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defaultEmbeddedText (EmbeddedText
commentText (CommentText
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shape (Rectangle
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vasetType 1
fg "65535,65535,65535"
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xt "0,0,18000,5000"
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text (MLText
va (VaSet
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xt "200,200,3200,1400"
st "
Text
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tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
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vasetType 1
fg "65535,65535,0"
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xt "-1000,-1000,1000,1000"
radius 1000
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name (Text
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shape (Line2D
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va (VaSet
vasetType 1
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xt "0,0,1000,1000"
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defaultBdJunction (BdJunction
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shape (Circle
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xt "-400,-400,400,400"
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defaultPortIoIn (PortIoIn
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va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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ro 270
xt "-2000,-375,-500,375"
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(Line
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ro 270
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stc 0
sf 1
tg (WTG
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stg "STSignalDisplayStrategy"
f (Text
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ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
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defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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sl 0
ro 270
xt "500,-375,2000,375"
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(Line
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ro 270
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pts [
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)
stc 0
sf 1
tg (WTG
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stg "STSignalDisplayStrategy"
f (Text
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blo "625,-1000"
tm "WireNameMgr"
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)
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defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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xt "500,-375,2000,375"
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(Line
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xt "0,0,500,0"
pts [
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)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
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optionalChildren [
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sl 0
xt "500,-375,2000,375"
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(Line
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xt "0,0,500,0"
pts [
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)
]
)
stc 0
sf 1
tg (WTG
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stg "STSignalDisplayStrategy"
f (Text
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xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
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)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
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]
)
ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "0,0,1900,1000"
st "sig0"
blo "0,800"
tm "WireNameMgr"
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)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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xt "0,0,2400,1000"
st "dbus0"
blo "0,800"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
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ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
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stg "VerticalLayoutStrategy"
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xt "0,0,3000,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
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second (MLText
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tm "BundleContentsMgr"
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bundleNet &0
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defaultPortMapFrame (PortMapFrame
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shape (RectFrame
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vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
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xt "0,0,10000,12000"
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portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
)
second (MLText
va (VaSet
)
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*88 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1250,1450"
)
num (Text
va (VaSet
)
xt "250,250,1050,1250"
st "1"
blo "250,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*90 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1800,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
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xt "-7000,5000,0,6000"
st "Declarations"
blo "-7000,5800"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,5900,-3600,6900"
st "Ports:"
blo "-7000,6700"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,12200,-2200,13200"
st "Pre User:"
blo "-7000,13000"
)
preUserText (MLText
uid 5,0
va (VaSet
)
xt "-5000,13100,17000,14300"
st "constant unitCountBitNb: positive := 3;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,8,1"
)
xt "-7000,14000,2000,15000"
st "Diagram Signals:"
blo "-7000,14800"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "-7000,5000,-1000,6000"
st "Post User:"
blo "-7000,5800"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
)
xt "-7000,5000,-7000,5000"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
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suid 11,0
usingSuid 1
emptyRow *91 (LEmptyRow
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uid 136,0
optionalChildren [
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*93 (TitleRowHdr
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*94 (FilterRowHdr
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*95 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*96 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*97 (GroupColHdr
tm "GroupColHdrMgr"
)
*98 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*99 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*100 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
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*101 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*102 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*103 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*104 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "morseOut"
t "std_ulogic"
o 1
suid 1,0
)
)
uid 79,0
)
*105 (LeafLogPort
port (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
uid 81,0
)
*106 (LeafLogPort
port (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
uid 83,0
)
*107 (LeafLogPort
port (LogicalPort
decl (Decl
n "charIn"
t "std_ulogic_vector"
b "(characterBitNb-1 DOWNTO 0)"
o 4
suid 5,0
)
)
uid 87,0
)
*108 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
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t "std_ulogic"
o 6
suid 6,0
)
)
uid 383,0
)
*109 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "done"
t "std_ulogic"
o 7
suid 7,0
)
)
uid 385,0
)
*110 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "unitNb"
t "unsigned"
b "(unitCountBitNb-1 downto 0)"
o 8
suid 8,0
)
)
uid 387,0
)
*111 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "readChar"
t "std_ulogic"
o 5
suid 10,0
)
)
uid 563,0
)
*112 (LeafLogPort
port (LogicalPort
decl (Decl
n "charNotReady"
t "std_ulogic"
o 9
suid 11,0
)
)
uid 626,0
)
]
)
pdm (PhysicalDM
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editShortBounds 1
uid 149,0
optionalChildren [
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sheetRow (SheetRow
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
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font "Tahoma,10,0"
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emptyMRCItem *114 (MRCItem
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pos 9
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optionalChildren [
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hidden 1
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pos 5
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pos 3
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sheetCol (SheetCol
propVa (MVa
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optionalChildren [
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dimension 50
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pos 2
dimension 100
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pos 3
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pos 4
dimension 100
uid 160,0
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pos 5
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pos 6
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vaOverrides [
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genericsCommonDM (CommonDM
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uid 165,0
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*137 (TitleRowHdr
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*139 (RefLabelColHdr
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*140 (RowExpandColHdr
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*141 (GroupColHdr
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*142 (NameColHdr
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*143 (TypeColHdr
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*144 (InitColHdr
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*145 (PragmaColHdr
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*146 (EolColHdr
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*147 (LogGeneric
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