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variable "day_long" value "Monday" ) (vvPair variable "dd" value "15" ) (vvPair variable "designName" value "$DESIGN_NAME" ) (vvPair variable "entity_name" value "FPGA_beamer" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "symbol.sb" ) (vvPair variable "f_logical" value "symbol.sb" ) (vvPair variable "f_noext" value "symbol" ) (vvPair variable "graphical_source_author" value "francois" ) (vvPair variable "graphical_source_date" value "04/15/19" ) (vvPair variable "graphical_source_group" value "francois" ) (vvPair variable "graphical_source_host" value "Aphelia" ) (vvPair variable "graphical_source_time" value "14:26:55" ) (vvPair variable "group" value "francois" ) (vvPair variable "host" value "Aphelia" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "Board" ) (vvPair variable "library_downstream_Concatenation" value "$HDS_PROJECT_DIR/../Board/concat" ) (vvPair variable "library_downstream_Generic_1_file" value "U:\\SEm_curves\\Synthesis" ) (vvPair variable "library_downstream_ModelSim" value "D:\\Users\\ELN_labs\\VHDL_comp" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/Board" ) (vvPair variable "library_downstream_SpyGlass" value "U:\\SEm_curves\\Synthesis" ) (vvPair variable "mm" value "04" ) (vvPair variable "module_name" value "FPGA_beamer" ) (vvPair variable "month" value "Apr" ) (vvPair variable "month_long" value "April" ) (vvPair variable "p" value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../Board/hds/@f@p@g@a_beamer/symbol.sb" ) (vvPair variable "p_logical" value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../Board/hds/FPGA_beamer/symbol.sb" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "systemOnChip" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_ADMS" value "" ) (vvPair variable "task_AsmPath" value "$HEI_LIBS_DIR/NanoBlaze/hdl" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$ISE_WORK_DIR" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME/modeltech/bin" ) (vvPair variable "task_NC" value "" ) (vvPair variable "task_PrecisionRTLPath" value "" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "sb" ) (vvPair variable "this_file" value "symbol" ) (vvPair variable "this_file_logical" value "symbol" ) (vvPair variable "time" value "14:26:55" ) (vvPair variable "unit" value "FPGA_beamer" ) (vvPair variable "user" value "francois" ) (vvPair variable "version" value "2018.1 (Build 12)" ) (vvPair variable "view" value "symbol" ) (vvPair variable "year" value "2019" ) (vvPair variable "yy" value "19" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 51,0 optionalChildren [ *75 (SymbolBody uid 8,0 optionalChildren [ *76 (CptPort uid 52,0 ps "OnEdgeStrategy" shape (Triangle uid 72,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,25625,34000,26375" ) tg (CPTG uid 54,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 55,0 va (VaSet font "courier,9,0" ) xt "35000,25400,38400,26600" st "clock" blo "35000,26400" tm "CptPortNameMgr" ) ) dt (MLText uid 56,0 va (VaSet font "courier,8,0" ) xt "2000,11000,19500,11900" st "clock : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "clock" t "std_ulogic" o 1 suid 1,0 ) ) ) *77 (CptPort uid 83,0 ps "OnEdgeStrategy" shape (Triangle uid 84,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,27625,34000,28375" ) tg (CPTG uid 85,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 86,0 va (VaSet font "courier,9,0" ) xt "35000,27400,39700,28600" st "reset_N" blo "35000,28400" tm "CptPortNameMgr" ) ) dt (MLText uid 87,0 va (VaSet font "courier,8,0" ) xt "2000,11900,19500,12800" st "reset_N : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "reset_N" t "std_ulogic" o 2 suid 2,0 ) ) ) *78 (CptPort uid 93,0 ps "OnEdgeStrategy" shape (Triangle uid 94,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "52000,9625,52750,10375" ) tg (CPTG uid 95,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 96,0 va (VaSet font "courier,9,0" ) xt "47800,9400,51000,10600" st "xOut" ju 2 blo "51000,10400" tm "CptPortNameMgr" ) ) dt (MLText uid 97,0 va (VaSet font "courier,8,0" ) xt "2000,18200,19500,19100" st "xOut : OUT std_ulogic ;" ) thePort (LogicalPort m 1 decl (Decl n "xOut" t "std_ulogic" o 9 suid 3,0 ) ) ) *79 (CptPort uid 98,0 ps "OnEdgeStrategy" shape (Triangle uid 99,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "52000,11625,52750,12375" ) tg (CPTG uid 100,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 101,0 va (VaSet font "courier,9,0" ) xt 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"txd0 : OUT std_ulogic ;" ) thePort (LogicalPort m 1 decl (Decl n "txd0" t "std_ulogic" o 8 suid 2040,0 ) ) ) *85 (CptPort uid 832,0 ps "OnEdgeStrategy" shape (Triangle uid 833,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "33250,29625,34000,30375" ) tg (CPTG uid 834,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 835,0 va (VaSet font "courier,9,0" ) xt "35000,29400,38000,30600" st "rxd0" blo "35000,30400" tm "CptPortNameMgr" ) ) dt (MLText uid 836,0 va (VaSet font "courier,8,0" ) xt "2000,12800,19500,13700" st "rxd0 : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "rxd0" t "std_ulogic" o 3 suid 2041,0 ) ) ) ] shape (Rectangle uid 81,0 va (VaSet vasetType 1 fg "0,65535,0" bg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "34000,6000,52000,40000" ) oxt "15000,6000,35000,26000" biTextGroup (BiTextGroup uid 10,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text uid 11,0 va (VaSet font "courier,9,1" ) xt "34600,29800,37100,30700" st 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"0,1450" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "courier,8,0" ) ) thePort (LogicalPort lang 11 m 3 decl (Decl n "Buffer0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) DeclarativeBlock *102 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" declLabel (Text uid 2,0 va (VaSet font "courier,8,1" ) xt "0,9000,5400,10000" st "Declarations" blo "0,9800" ) portLabel (Text uid 3,0 va (VaSet font "courier,8,1" ) xt "0,10000,2700,11000" st "Ports:" blo "0,10800" ) externalLabel (Text uid 4,0 va (VaSet font "courier,8,1" ) xt "0,20000,2500,20900" st "User:" blo "0,20700" ) internalLabel (Text uid 6,0 va (VaSet isHidden 1 font "courier,8,1" ) xt "0,9000,5800,10000" st "Internal User:" blo "0,9800" ) externalText (MLText uid 5,0 va (VaSet font "courier,8,0" ) xt "2000,20900,2000,20900" tm "SyDeclarativeTextMgr" ) internalText (MLText uid 7,0 va (VaSet isHidden 1 font "courier,8,0" ) xt "0,9000,0,9000" tm "SyDeclarativeTextMgr" ) ) lastUid 882,0 okToSyncOnLoad 1 OkToSyncGenericsOnLoad 1 activeModelName "Symbol" )