-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 13:00:24 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY interpolatorShiftRegister IS
    GENERIC( 
        signalBitNb : positive := 16
    );
    PORT( 
        clock        : IN     std_ulogic;
        reset        : IN     std_ulogic;
        shiftSamples : IN     std_ulogic;
        sampleIn     : IN     signed (signalBitNb-1 DOWNTO 0);
        sample1      : OUT    signed (signalBitNb-1 DOWNTO 0);
        sample2      : OUT    signed (signalBitNb-1 DOWNTO 0);
        sample3      : OUT    signed (signalBitNb-1 DOWNTO 0);
        sample4      : OUT    signed (signalBitNb-1 DOWNTO 0)
    );

-- Declarations

END interpolatorShiftRegister ;