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(vvPair variable "year" value "2022" ) (vvPair variable "yy" value "22" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 149,0 optionalChildren [ *69 (SymbolBody uid 8,0 optionalChildren [ *70 (CptPort uid 79,0 ps "OnEdgeStrategy" shape (Triangle uid 80,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "38250,26625,39000,27375" ) tg (CPTG uid 81,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 82,0 va (VaSet ) xt "40000,26500,43400,27700" st "clock" blo "40000,27500" tm "CptPortNameMgr" ) ) dt (MLText uid 83,0 va (VaSet font "Verdana,8,0" ) xt "2000,9200,15100,10200" st "clock : IN std_ulogic ;" ) thePort (LogicalPort lang 11 decl (Decl n "clock" t "std_ulogic" o 1 suid 1,0 ) ) ) *71 (CptPort uid 89,0 ps "OnEdgeStrategy" shape (Triangle uid 90,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "38250,24625,39000,25375" ) tg (CPTG uid 91,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 92,0 va (VaSet ) xt "40000,24500,41900,25700" st "en" blo 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