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font "Verdana,12,0"
)
xt "35000,37400,38200,38800"
st "CLK"
blo "35000,38600"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*34 (CptPort
uid 1063,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1064,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "36625,40000,37375,40750"
)
tg (CPTG
uid 1065,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1066,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,38600,39200,40000"
st "CLR"
blo "36000,39800"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*35 (CptPort
uid 1067,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1068,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "40000,33625,40750,34375"
)
tg (CPTG
uid 1069,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1070,0
va (VaSet
font "Verdana,12,0"
)
xt "37200,33300,39000,34700"
st "Q"
ju 2
blo "39000,34500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 1072,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "34000,32000,40000,40000"
)
showPorts 0
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1073,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*36 (Text
uid 1074,0
va (VaSet
)
xt "38600,39700,42200,40900"
st "Board"
blo "38600,40700"
tm "BdLibraryNameMgr"
)
*37 (Text
uid 1075,0
va (VaSet
)
xt "38600,40700,41300,41900"
st "DFF"
blo "38600,41700"
tm "CptNameMgr"
)
*38 (Text
uid 1076,0
va (VaSet
)
xt "38600,41700,41600,42900"
st "I_dff"
blo "38600,42700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1077,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1078,0
text (MLText
uid 1079,0
va (VaSet
)
xt "11000,29000,11000,29000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*39 (SaComponent
uid 1806,0
optionalChildren [
*40 (CptPort
uid 1797,0
optionalChildren [
*41 (Circle
uid 1801,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "44092,33546,45000,34454"
radius 454
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 1798,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "43342,33625,44092,34375"
)
tg (CPTG
uid 1799,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1800,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "45000,33500,47700,34900"
st "in1"
blo "45000,34700"
)
s (Text
uid 1815,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "45000,34900,45000,34900"
blo "45000,34900"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
suid 1,0
)
)
)
*42 (CptPort
uid 1802,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1803,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "50000,33625,50750,34375"
)
tg (CPTG
uid 1804,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1805,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "46050,33500,49750,34900"
st "out1"
ju 2
blo "49750,34700"
)
s (Text
uid 1816,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "49750,34900,49750,34900"
ju 2
blo "49750,34900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
suid 2,0
)
)
)
]
shape (Buf
uid 1807,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "45000,31000,50000,37000"
)
showPorts 0
oxt "23000,4000,28000,10000"
ttg (MlTextGroup
uid 1808,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*43 (Text
uid 1809,0
va (VaSet
)
xt "46460,36700,50060,37900"
st "Board"
blo "46460,37700"
tm "BdLibraryNameMgr"
)
*44 (Text
uid 1810,0
va (VaSet
)
xt "46460,37700,52860,38900"
st "inverterIn"
blo "46460,38700"
tm "CptNameMgr"
)
*45 (Text
uid 1811,0
va (VaSet
)
xt "46460,38700,50460,39900"
st "I_inv2"
blo "46460,39700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1812,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1813,0
text (MLText
uid 1814,0
va (VaSet
)
xt "45000,37400,45000,37400"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*46 (SaComponent
uid 1817,0
optionalChildren [
*47 (CptPort
uid 1826,0
optionalChildren [
*48 (Circle
uid 1831,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "22092,41546,23000,42454"
radius 454
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 1827,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "21342,41625,22092,42375"
)
tg (CPTG
uid 1828,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1829,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "23000,41500,25700,42900"
st "in1"
blo "23000,42700"
)
s (Text
uid 1830,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "23000,42900,23000,42900"
blo "23000,42900"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*49 (CptPort
uid 1832,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1833,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "28000,41625,28750,42375"
)
tg (CPTG
uid 1834,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1835,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "24050,41500,27750,42900"
st "out1"
ju 2
blo "27750,42700"
)
s (Text
uid 1836,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "27750,42900,27750,42900"
ju 2
blo "27750,42900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 1818,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "23000,39000,28000,45000"
)
showPorts 0
oxt "23000,4000,28000,10000"
ttg (MlTextGroup
uid 1819,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*50 (Text
uid 1820,0
va (VaSet
)
xt "24460,44700,28060,45900"
st "Board"
blo "24460,45700"
tm "BdLibraryNameMgr"
)
*51 (Text
uid 1821,0
va (VaSet
)
xt "24460,45700,30860,46900"
st "inverterIn"
blo "24460,46700"
tm "CptNameMgr"
)
*52 (Text
uid 1822,0
va (VaSet
)
xt "24460,46700,28460,47900"
st "I_inv1"
blo "24460,47700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1823,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1824,0
text (MLText
uid 1825,0
va (VaSet
)
xt "23000,45400,23000,45400"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*53 (SaComponent
uid 2310,0
optionalChildren [
*54 (CptPort
uid 2290,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2291,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "56250,29625,57000,30375"
)
tg (CPTG
uid 2292,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2293,0
va (VaSet
)
xt "58000,29400,61400,30600"
st "clock"
blo "58000,30400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*55 (CptPort
uid 2294,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2295,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73000,29625,73750,30375"
)
tg (CPTG
uid 2296,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2297,0
va (VaSet
)
xt "65400,29400,72000,30600"
st "triggerOut"
ju 2
blo "72000,30400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "triggerOut"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*56 (CptPort
uid 2298,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2299,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73000,27625,73750,28375"
)
tg (CPTG
uid 2300,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2301,0
va (VaSet
)
xt "68800,27400,72000,28600"
st "xOut"
ju 2
blo "72000,28400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "xOut"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*57 (CptPort
uid 2302,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2303,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73000,25625,73750,26375"
)
tg (CPTG
uid 2304,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2305,0
va (VaSet
)
xt "68800,25400,72000,26600"
st "yOut"
ju 2
blo "72000,26400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "yOut"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*58 (CptPort
uid 2306,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2307,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "56250,31625,57000,32375"
)
tg (CPTG
uid 2308,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2309,0
va (VaSet
)
xt "58000,31500,61300,32700"
st "reset"
blo "58000,32500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
suid 2006,0
)
)
)
]
shape (Rectangle
uid 2311,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "57000,22000,73000,34000"
)
oxt "32000,10000,48000,22000"
ttg (MlTextGroup
uid 2312,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*59 (Text
uid 2313,0
va (VaSet
font "Verdana,9,1"
)
xt "57600,33800,62800,35000"
st "Lissajous"
blo "57600,34800"
tm "BdLibraryNameMgr"
)
*60 (Text
uid 2314,0
va (VaSet
font "Verdana,9,1"
)
xt "57600,34700,68100,35900"
st "lissajousGenerator"
blo "57600,35700"
tm "CptNameMgr"
)
*61 (Text
uid 2315,0
va (VaSet
font "Verdana,9,1"
)
xt "57600,35600,61700,36800"
st "I_main"
blo "57600,36600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2316,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2317,0
text (MLText
uid 2318,0
va (VaSet
)
xt "57000,37600,80500,42400"
st "signalBitNb = signalBitNb    ( positive )  
phaseBitNb  = phaseBitNb     ( positive )  
stepX       = stepX          ( positive )  
stepY       = stepY          ( positive )  "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "phaseBitNb"
type "positive"
value "phaseBitNb"
)
(GiElement
name "stepX"
type "positive"
value "stepX"
)
(GiElement
name "stepY"
type "positive"
value "stepY"
)
]
)
connectByName 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*62 (Wire
uid 15,0
shape (OrthoPolyLine
uid 16,0
va (VaSet
vasetType 3
)
xt "17000,30000,56250,30000"
pts [
"17000,30000"
"56250,30000"
]
)
start &1
end &54
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20,0
va (VaSet
font "Verdana,12,0"
)
xt "17000,28600,20800,30000"
st "clock"
blo "17000,29800"
tm "WireNameMgr"
)
)
on &2
)
*63 (Wire
uid 29,0
shape (OrthoPolyLine
uid 30,0
va (VaSet
vasetType 3
)
xt "73750,26000,81000,26000"
pts [
"81000,26000"
"73750,26000"
]
)
start &3
end &57
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 33,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 34,0
va (VaSet
font "Verdana,12,0"
)
xt "76000,24600,79800,26000"
st "yOut"
blo "76000,25800"
tm "WireNameMgr"
)
)
on &22
)
*64 (Wire
uid 43,0
shape (OrthoPolyLine
uid 44,0
va (VaSet
vasetType 3
)
xt "17000,42000,22092,42000"
pts [
"17000,42000"
"22092,42000"
]
)
start &4
end &47
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 47,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 48,0
va (VaSet
font "Verdana,12,0"
)
xt "16000,40600,21800,42000"
st "reset_N"
blo "16000,41800"
tm "WireNameMgr"
)
)
on &17
)
*65 (Wire
uid 245,0
shape (OrthoPolyLine
uid 246,0
va (VaSet
vasetType 3
)
xt "50000,32000,56250,34000"
pts [
"50000,34000"
"53000,34000"
"53000,32000"
"56250,32000"
]
)
start &42
end &58
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 251,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 252,0
va (VaSet
font "Verdana,12,0"
)
xt "50000,30600,58600,32000"
st "resetSynch"
blo "50000,31800"
tm "WireNameMgr"
)
)
on &29
)
*66 (Wire
uid 435,0
shape (OrthoPolyLine
uid 436,0
va (VaSet
vasetType 3
)
xt "73750,30000,81000,30000"
pts [
"81000,30000"
"73750,30000"
]
)
start &18
end &55
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 439,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 440,0
va (VaSet
font "Verdana,12,0"
)
xt "76000,28600,84100,30000"
st "triggerOut"
blo "76000,29800"
tm "WireNameMgr"
)
)
on &19
)
*67 (Wire
uid 575,0
shape (OrthoPolyLine
uid 576,0
va (VaSet
vasetType 3
)
xt "73750,28000,81000,28000"
pts [
"81000,28000"
"73750,28000"
]
)
start &21
end &56
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 577,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 578,0
va (VaSet
font "Verdana,12,0"
)
xt "76000,26600,79800,28000"
st "xOut"
blo "76000,27800"
tm "WireNameMgr"
)
)
on &20
)
*68 (Wire
uid 873,0
shape (OrthoPolyLine
uid 874,0
va (VaSet
vasetType 3
)
xt "32000,38000,34000,38000"
pts [
"32000,38000"
"34000,38000"
]
)
end &32
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 877,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 878,0
va (VaSet
font "Verdana,12,0"
)
xt "30000,36600,33800,38000"
st "clock"
blo "30000,37800"
tm "WireNameMgr"
)
)
on &2
)
*69 (Wire
uid 879,0
shape (OrthoPolyLine
uid 880,0
va (VaSet
vasetType 3
)
xt "28000,40000,37000,42000"
pts [
"28000,42000"
"37000,42000"
"37000,40000"
]
)
start &49
end &34
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 881,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 882,0
va (VaSet
font "Verdana,12,0"
)
xt "29000,40600,33100,42000"
st "reset"
blo "29000,41800"
tm "WireNameMgr"
)
)
on &5
)
*70 (Wire
uid 883,0
shape (OrthoPolyLine
uid 884,0
va (VaSet
vasetType 3
)
xt "40000,34000,44092,34000"
pts [
"40000,34000"
"44092,34000"
]
)
start &35
end &40
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 885,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 886,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,32600,48600,34000"
st "resetSnch_N"
blo "39000,33800"
tm "WireNameMgr"
)
)
on &27
)
*71 (Wire
uid 887,0
shape (OrthoPolyLine
uid 888,0
va (VaSet
vasetType 3
)
xt "29000,34000,34000,34000"
pts [
"34000,34000"
"29000,34000"
]
)
start &31
end &23
sat 32
eat 2
stc 0
sf 1
si 0
tg (WTG
uid 891,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 892,0
va (VaSet
font "Verdana,12,0"
)
xt "30000,32600,34400,34000"
st "logic1"
blo "30000,33800"
tm "WireNameMgr"
)
)
on &28
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *72 (PackageList
uid 84,0
stg "VerticalLayoutStrategy"
textVec [
*73 (Text
uid 85,0
va (VaSet
font "Verdana,8,1"
)
xt "-3000,0,3900,1000"
st "Package List"
blo "-3000,800"
)
*74 (MLText
uid 86,0
va (VaSet
)
xt "-3000,1000,14500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 87,0
stg "VerticalLayoutStrategy"
textVec [
*75 (Text
uid 88,0
va (VaSet
isHidden 1
font "Verdana,8,1"
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