ARCHITECTURE studentVersion OF interpolatorShiftRegister IS

subtype sample_type is signed(sampleIn'range);
type samples_type is array (1 to 4) of sample_type;
signal samples: samples_type;

BEGIN

  process(clock, reset) begin
    if reset = '1' then
      samples <= (others => (others => '0'));
    elsif rising_edge(clock) then
      if shiftSamples then
        for i in samples_type'low to samples_type'high-1 loop
          samples(i+1) <= samples(i);
        end loop;
        samples(1) <= sampleIn;
      end if;
    end if;
  end process;

  sample1 <= samples(1);
  sample2 <= samples(2);
  sample3 <= samples(3);
  sample4 <= samples(4);
END ARCHITECTURE studentVersion;