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value "UNKNOWN" ) (vvPair variable "host" value "WE7860" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "Board" ) (vvPair variable "library_downstream_Concatenation" value "$HDS_PROJECT_DIR/../Board/concat" ) (vvPair variable "library_downstream_Generic_1_file" value "U:\\SEm_curves\\Synthesis" ) (vvPair variable "library_downstream_ModelSim" value "D:\\Users\\ELN_labs\\VHDL_comp" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/Board" ) (vvPair variable "library_downstream_SpyGlass" value "U:\\SEm_curves\\Synthesis" ) (vvPair variable "mm" value "04" ) (vvPair variable "module_name" value "morse_circuit" ) (vvPair variable "month" value "avr." ) (vvPair variable "month_long" value "avril" ) (vvPair variable "p" value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds\\morse_circuit\\symbol.sb" ) (vvPair variable "p_logical" value "C:\\dev\\sem-labs\\05-Morse\\Prefs\\..\\Board\\hds\\morse_circuit\\symbol.sb" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_ADMS" value "" ) (vvPair variable "task_AsmPath" value "$HEI_LIBS_DIR/NanoBlaze/hdl" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$SCRATCH_DIR\\$DESIGN_NAME\\$ISE_WORK_DIR" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME" ) (vvPair variable "task_NC" value "" ) (vvPair variable "task_PrecisionRTLPath" value "" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "sb" ) (vvPair variable "this_file" value "symbol" ) (vvPair variable "this_file_logical" value "symbol" ) (vvPair variable "time" value "14:49:40" ) (vvPair variable "unit" value "morse_circuit" ) (vvPair variable "user" value "axel.amand" ) (vvPair variable "version" value "2019.2 (Build 5)" ) (vvPair variable "view" value "symbol" ) (vvPair variable "year" value "2023" ) (vvPair variable "yy" value "23" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 51,0 optionalChildren [ *69 (SymbolBody uid 8,0 optionalChildren [ *70 (CptPort uid 52,0 ps "OnEdgeStrategy" shape (Triangle uid 72,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "31250,17625,32000,18375" ) tg (CPTG uid 54,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 55,0 va (VaSet font "Arial,9,0" ) xt "33000,17400,35700,18600" st "clock" blo "33000,18300" tm "CptPortNameMgr" ) ) dt (MLText uid 56,0 va (VaSet ) xt "2000,12000,19200,13200" st "clock : IN std_ulogic ;" ) thePort (LogicalPort decl (Decl n "clock" t "std_ulogic" o 2 suid 1,0 ) ) ) *71 (CptPort uid 83,0 ps "OnEdgeStrategy" shape (Triangle uid 84,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "31250,19625,32000,20375" ) tg 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