DocumentHdrVersion "1.1" Header (DocumentHdr version 2 dmPackageRefs [ (DmPackageRef library "ieee" unitName "std_logic_1164" ) (DmPackageRef library "ieee" unitName "numeric_std" ) (DmPackageRef library "AhbLite" unitName "ahbLite" ) ] libraryRefs [ "ieee" "AhbLite" ] ) version "27.1" appVersion "2019.2 (Build 5)" model (Symbol commonDM (CommonDM ldm (LogicalDM suid 58,0 usingSuid 1 emptyRow *1 (LEmptyRow ) uid 123,0 optionalChildren [ *2 (RefLabelRowHdr ) *3 (TitleRowHdr ) *4 (FilterRowHdr ) *5 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *6 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *7 (GroupColHdr tm "GroupColHdrMgr" ) *8 (NameColHdr tm "NameColHdrMgr" ) *9 (ModeColHdr tm "ModeColHdrMgr" ) *10 (TypeColHdr tm "TypeColHdrMgr" ) *11 (BoundsColHdr tm "BoundsColHdrMgr" ) *12 (InitColHdr tm "InitColHdrMgr" ) *13 (EolColHdr tm "EolColHdrMgr" ) *14 (LogPort port (LogicalPort m 1 decl (Decl n "hAddr" t "unsigned" b "( ahbAddressBitNb-1 DOWNTO 0 )" o 3 suid 47,0 ) ) uid 1274,0 ) *15 (LogPort port (LogicalPort m 1 decl (Decl n "hClk" t "std_uLogic" o 4 suid 48,0 ) ) uid 1276,0 ) *16 (LogPort port (LogicalPort decl (Decl n "hRData" t "std_ulogic_vector" b "(ahbDataBitNb-1 DOWNTO 0)" o 5 suid 49,0 ) ) uid 1278,0 ) *17 (LogPort port (LogicalPort decl (Decl n "hReady" t "std_uLogic" o 6 suid 50,0 ) ) uid 1280,0 ) *18 (LogPort port (LogicalPort m 1 decl (Decl n "hReset_n" t "std_uLogic" o 7 suid 51,0 ) ) uid 1282,0 ) *19 (LogPort port (LogicalPort decl (Decl n "hResp" t "std_uLogic" o 8 suid 52,0 ) ) uid 1284,0 ) *20 (LogPort port (LogicalPort m 1 decl (Decl n "hSel" t "std_uLogic" o 9 suid 53,0 ) ) uid 1286,0 ) *21 (LogPort port (LogicalPort m 1 decl (Decl n "hTrans" t "std_ulogic_vector" b "(ahbTransBitNb-1 DOWNTO 0)" o 10 suid 54,0 ) ) uid 1288,0 ) *22 (LogPort port (LogicalPort m 1 decl (Decl n "hWData" t "std_ulogic_vector" b "(ahbDataBitNb-1 DOWNTO 0)" o 11 suid 55,0 ) ) uid 1290,0 ) *23 (LogPort port (LogicalPort m 1 decl (Decl n "hWrite" t "std_uLogic" o 12 suid 56,0 ) ) uid 1292,0 ) *24 (LogPort port (LogicalPort m 1 decl (Decl n "RxD" t "std_ulogic" o 1 suid 57,0 ) ) uid 1294,0 ) *25 (LogPort port (LogicalPort decl (Decl n "TxD" t "std_ulogic" o 2 suid 58,0 ) ) uid 1296,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 136,0 optionalChildren [ *26 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *27 (MRCItem litem &1 pos 12 dimension 20 ) uid 138,0 optionalChildren [ *28 (MRCItem litem &2 pos 0 dimension 20 uid 139,0 ) *29 (MRCItem litem &3 pos 1 dimension 23 uid 140,0 ) *30 (MRCItem litem &4 pos 2 hidden 1 dimension 20 uid 141,0 ) *31 (MRCItem litem &14 pos 0 dimension 20 uid 1275,0 ) *32 (MRCItem litem &15 pos 1 dimension 20 uid 1277,0 ) *33 (MRCItem litem &16 pos 2 dimension 20 uid 1279,0 ) *34 (MRCItem litem &17 pos 3 dimension 20 uid 1281,0 ) *35 (MRCItem litem &18 pos 4 dimension 20 uid 1283,0 ) *36 (MRCItem litem &19 pos 5 dimension 20 uid 1285,0 ) *37 (MRCItem litem &20 pos 6 dimension 20 uid 1287,0 ) *38 (MRCItem litem &21 pos 7 dimension 20 uid 1289,0 ) *39 (MRCItem litem &22 pos 8 dimension 20 uid 1291,0 ) *40 (MRCItem litem &23 pos 9 dimension 20 uid 1293,0 ) *41 (MRCItem litem &24 pos 10 dimension 20 uid 1295,0 ) *42 (MRCItem litem &25 pos 11 dimension 20 uid 1297,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 142,0 optionalChildren [ *43 (MRCItem litem &5 pos 0 dimension 20 uid 143,0 ) *44 (MRCItem litem &7 pos 1 dimension 50 uid 144,0 ) *45 (MRCItem litem &8 pos 2 dimension 100 uid 145,0 ) *46 (MRCItem litem &9 pos 3 dimension 50 uid 146,0 ) *47 (MRCItem litem &10 pos 4 dimension 100 uid 147,0 ) *48 (MRCItem litem &11 pos 5 dimension 100 uid 148,0 ) *49 (MRCItem litem &12 pos 6 dimension 50 uid 149,0 ) *50 (MRCItem litem &13 pos 7 dimension 80 uid 150,0 ) ] ) fixedCol 4 fixedRow 2 name "Ports" uid 137,0 vaOverrides [ ] ) ] ) uid 122,0 ) genericsCommonDM (CommonDM ldm (LogicalDM emptyRow *51 (LEmptyRow ) uid 152,0 optionalChildren [ *52 (RefLabelRowHdr ) *53 (TitleRowHdr ) *54 (FilterRowHdr ) *55 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *56 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *57 (GroupColHdr tm "GroupColHdrMgr" ) *58 (NameColHdr tm "GenericNameColHdrMgr" ) *59 (TypeColHdr tm "GenericTypeColHdrMgr" ) *60 (InitColHdr tm "GenericValueColHdrMgr" ) *61 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) *62 (EolColHdr tm "GenericEolColHdrMgr" ) *63 (LogGeneric generic (GiElement name "clockFrequency" type "real" value "" ) uid 446,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 164,0 optionalChildren [ *64 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *65 (MRCItem litem &51 pos 1 dimension 20 ) uid 166,0 optionalChildren [ *66 (MRCItem litem &52 pos 0 dimension 20 uid 167,0 ) *67 (MRCItem litem &53 pos 1 dimension 23 uid 168,0 ) *68 (MRCItem litem &54 pos 2 hidden 1 dimension 20 uid 169,0 ) *69 (MRCItem litem &63 pos 0 dimension 20 uid 447,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 170,0 optionalChildren [ *70 (MRCItem litem &55 pos 0 dimension 20 uid 171,0 ) *71 (MRCItem litem &57 pos 1 dimension 50 uid 172,0 ) *72 (MRCItem litem &58 pos 2 dimension 100 uid 173,0 ) *73 (MRCItem litem &59 pos 3 dimension 100 uid 174,0 ) *74 (MRCItem litem &60 pos 4 dimension 50 uid 175,0 ) *75 (MRCItem litem &61 pos 5 dimension 50 uid 176,0 ) *76 (MRCItem litem &62 pos 6 dimension 80 uid 177,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 165,0 vaOverrides [ ] ) ] ) uid 151,0 type 1 ) VExpander (VariableExpander vvMap [ (vvPair variable "HDLDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" ) (vvPair variable "HDSDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" ) (vvPair variable "SideDataDesignDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@uart_tester\\interface.info" ) (vvPair variable "SideDataUserDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@uart_tester\\interface.user" ) (vvPair variable "SourceDir" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "interface" ) (vvPair variable "asm_file" value "beamer.asm" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@uart_tester" ) (vvPair variable "d_logical" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbUart_tester" ) (vvPair variable "date" value "02/17/2020" ) (vvPair variable "day" value "Mon" ) (vvPair variable "day_long" value "Monday" ) (vvPair variable "dd" value "17" ) (vvPair variable "designName" value "$DESIGN_NAME" ) (vvPair variable "entity_name" value "ahbUart_tester" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "interface" ) (vvPair variable "f_logical" value "interface" ) (vvPair variable "f_noext" value "interface" ) (vvPair variable "graphical_source_author" value "zas" ) (vvPair variable "graphical_source_date" value "02/17/2020" ) (vvPair variable "graphical_source_group" value "UNKNOWN" ) (vvPair variable "graphical_source_host" value "ZELL" ) (vvPair variable "graphical_source_time" value "17:08:42" ) (vvPair variable "group" value "UNKNOWN" ) (vvPair variable "host" value "ZELL" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "AhbLiteComponents_test" ) (vvPair variable "library_downstream_Concatenation" value "$HDS_LIBS_DIR/AhbLiteComponents_test/concat" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/AhbLiteComponents_test" ) (vvPair variable "mm" value "02" ) (vvPair variable "module_name" value "ahbUart_tester" ) (vvPair variable "month" value "Feb" ) (vvPair variable "month_long" value "February" ) (vvPair variable "p" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@uart_tester\\interface" ) (vvPair variable "p_logical" value "C:\\work\\repo\\edu\\sem\\labo\\solution\\hd-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbUart_tester\\interface" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_AsmPath" value "$HDS_LIBS_DIR\\NanoBlaze\\hdl" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$ISE_SCRATCH_WORK_DIR" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME\\win32" ) (vvPair variable "this_ext" value "" ) (vvPair variable "this_file" value "interface" ) (vvPair variable "this_file_logical" value "interface" ) (vvPair variable "time" value "17:08:42" ) (vvPair variable "unit" value "ahbUart_tester" ) (vvPair variable "user" value "zas" ) (vvPair variable "version" value "2019.2 (Build 5)" ) (vvPair variable "view" value "interface" ) (vvPair variable "year" value "2020" ) (vvPair variable "yy" value "20" ) ] ) LanguageMgr "VhdlLangMgr" uid 121,0 optionalChildren [ *77 (SymbolBody uid 8,0 optionalChildren [ *78 (CptPort uid 1214,0 ps "OnEdgeStrategy" shape (Triangle uid 1215,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "22625,5250,23375,6000" ) tg (CPTG uid 1216,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1217,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "22300,7000,23700,11500" st "hAddr" ju 2 blo "23500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1218,0 va (VaSet font "Courier New,8,0" ) xt "44000,6000,75500,6800" st "hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ) ; " ) thePort (LogicalPort m 1 decl (Decl n "hAddr" t "unsigned" b "( ahbAddressBitNb-1 DOWNTO 0 )" o 3 suid 47,0 ) ) ) *79 (CptPort uid 1219,0 ps "OnEdgeStrategy" shape (Triangle uid 1220,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "40625,5250,41375,6000" ) tg (CPTG uid 1221,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1222,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "40300,7000,41700,10500" st "hClk" ju 2 blo "41500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1223,0 va (VaSet font "Courier New,8,0" ) xt "44000,6800,61000,7600" st "hClk : OUT std_uLogic ; " ) thePort (LogicalPort m 1 decl (Decl n "hClk" t "std_uLogic" o 4 suid 48,0 ) ) ) *80 (CptPort uid 1224,0 ps "OnEdgeStrategy" shape (Triangle uid 1225,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "32625,5250,33375,6000" ) tg (CPTG uid 1226,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1227,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "32300,7000,33700,12400" st "hRData" ju 2 blo "33500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1228,0 va (VaSet font "Courier New,8,0" ) xt "44000,2800,77500,3600" st "hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; " ) thePort (LogicalPort decl (Decl n "hRData" t "std_ulogic_vector" b "(ahbDataBitNb-1 DOWNTO 0)" o 5 suid 49,0 ) ) ) *81 (CptPort uid 1229,0 ps "OnEdgeStrategy" shape (Triangle uid 1230,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "34625,5250,35375,6000" ) tg (CPTG uid 1231,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1232,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "34300,7000,35700,12500" st "hReady" ju 2 blo "35500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1233,0 va (VaSet font "Courier New,8,0" ) xt "44000,3600,61000,4400" st "hReady : IN std_uLogic ; " ) thePort (LogicalPort decl (Decl n "hReady" t "std_uLogic" o 6 suid 50,0 ) ) ) *82 (CptPort uid 1234,0 ps "OnEdgeStrategy" shape (Triangle uid 1235,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "42625,5250,43375,6000" ) tg (CPTG uid 1236,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1237,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "42300,7000,43700,13800" st "hReset_n" ju 2 blo "43500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1238,0 va (VaSet font "Courier New,8,0" ) xt "44000,7600,61000,8400" st "hReset_n : OUT std_uLogic ; " ) thePort (LogicalPort m 1 decl (Decl n "hReset_n" t "std_uLogic" o 7 suid 51,0 ) ) ) *83 (CptPort uid 1239,0 ps "OnEdgeStrategy" shape (Triangle uid 1240,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "36625,5250,37375,6000" ) tg (CPTG uid 1241,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1242,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "36300,7000,37700,11700" st "hResp" ju 2 blo "37500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1243,0 va (VaSet font "Courier New,8,0" ) xt "44000,4400,61000,5200" st "hResp : IN std_uLogic ; " ) thePort (LogicalPort decl (Decl n "hResp" t "std_uLogic" o 8 suid 52,0 ) ) ) *84 (CptPort uid 1244,0 ps "OnEdgeStrategy" shape (Triangle uid 1245,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "30625,5250,31375,6000" ) tg (CPTG uid 1246,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1247,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "30300,7000,31700,10500" st "hSel" ju 2 blo "31500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1248,0 va (VaSet font "Courier New,8,0" ) xt "44000,8400,61000,9200" st "hSel : OUT std_uLogic ; " ) thePort (LogicalPort m 1 decl (Decl n "hSel" t "std_uLogic" o 9 suid 53,0 ) ) ) *85 (CptPort uid 1249,0 ps "OnEdgeStrategy" shape (Triangle uid 1250,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "26625,5250,27375,6000" ) tg (CPTG uid 1251,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1252,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "26300,7000,27700,12100" st "hTrans" ju 2 blo "27500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1253,0 va (VaSet font "Courier New,8,0" ) xt "44000,9200,78000,10000" st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ; " ) thePort (LogicalPort m 1 decl (Decl n "hTrans" t "std_ulogic_vector" b "(ahbTransBitNb-1 DOWNTO 0)" o 10 suid 54,0 ) ) ) *86 (CptPort uid 1254,0 ps "OnEdgeStrategy" shape (Triangle uid 1255,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "24625,5250,25375,6000" ) tg (CPTG uid 1256,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1257,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "24300,7000,25700,12900" st "hWData" ju 2 blo "25500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1258,0 va (VaSet font "Courier New,8,0" ) xt "44000,10000,77500,10800" st "hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ; " ) thePort (LogicalPort m 1 decl (Decl n "hWData" t "std_ulogic_vector" b "(ahbDataBitNb-1 DOWNTO 0)" o 11 suid 55,0 ) ) ) *87 (CptPort uid 1259,0 ps "OnEdgeStrategy" shape (Triangle uid 1260,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "28625,5250,29375,6000" ) tg (CPTG uid 1261,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1262,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "28300,7000,29700,12000" st "hWrite" ju 2 blo "29500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1263,0 va (VaSet font "Courier New,8,0" ) xt "44000,10800,60000,11600" st "hWrite : OUT std_uLogic " ) thePort (LogicalPort m 1 decl (Decl n "hWrite" t "std_uLogic" o 12 suid 56,0 ) ) ) *88 (CptPort uid 1264,0 ps "OnEdgeStrategy" shape (Triangle uid 1265,0 va (VaSet vasetType 1 fg "0,65535,0" ) xt "64625,5250,65375,6000" ) tg (CPTG uid 1266,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1267,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "64300,7000,65700,10200" st "RxD" ju 2 blo "65500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1268,0 va (VaSet font "Courier New,8,0" ) xt "44000,5200,61000,6000" st "RxD : OUT std_ulogic ; " ) thePort (LogicalPort m 1 decl (Decl n "RxD" t "std_ulogic" o 1 suid 57,0 ) ) ) *89 (CptPort uid 1269,0 ps "OnEdgeStrategy" shape (Triangle uid 1270,0 ro 180 va (VaSet vasetType 1 fg "0,65535,0" ) xt "66625,5250,67375,6000" ) tg (CPTG uid 1271,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 1272,0 ro 270 va (VaSet font "Verdana,12,0" ) xt "66300,7000,67700,10100" st "TxD" ju 2 blo "67500,7000" tm "CptPortNameMgr" ) ) dt (MLText uid 1273,0 va (VaSet font "Courier New,8,0" ) xt "44000,2000,61000,2800" st "TxD : IN std_ulogic ; " ) thePort (LogicalPort decl (Decl n "TxD" t "std_ulogic" o 2 suid 58,0 ) ) ) ] shape (Rectangle uid 9,0 va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,75000,14000" ) oxt "15000,6000,73000,14000" biTextGroup (BiTextGroup uid 10,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text uid 11,0 va (VaSet font "Arial,8,1" ) xt "39600,9000,50400,10000" st "AhbLiteComponents_test" blo "39600,9800" ) second (Text uid 12,0 va (VaSet font "Arial,8,1" ) xt "39600,10000,45900,11000" st "ahbUart_tester" blo "39600,10800" ) ) gi *90 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" matrix (Matrix uid 14,0 text (MLText uid 15,0 va (VaSet font "Courier New,8,0" ) xt "21000,6000,33500,8400" st "Generic Declarations clockFrequency real " ) header "Generic Declarations" showHdrWhenContentsEmpty 1 ) elements [ (GiElement name "clockFrequency" type "real" value "" ) ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay sTC 0 sF 0 ) portVis (PortSigDisplay sTC 0 sF 0 ) ) *91 (Grouping uid 16,0 optionalChildren [ *92 (CommentText uid 18,0 shape (Rectangle uid 19,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "36000,48000,53000,49000" ) oxt "18000,70000,35000,71000" text (MLText uid 20,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "36200,48500,36200,48500" st " by %user on %dd %month %year " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) *93 (CommentText uid 21,0 shape (Rectangle uid 22,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,44000,57000,45000" ) oxt "35000,66000,39000,67000" text (MLText uid 23,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "53200,44500,53200,44500" st " Project: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *94 (CommentText uid 24,0 shape (Rectangle uid 25,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "36000,46000,53000,47000" ) oxt "18000,68000,35000,69000" text (MLText uid 26,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "36200,46500,36200,46500" st " " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) *95 (CommentText uid 27,0 shape (Rectangle uid 28,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,46000,36000,47000" ) oxt "14000,68000,18000,69000" text (MLText uid 29,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "32200,46500,32200,46500" st " Title: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *96 (CommentText uid 30,0 shape (Rectangle uid 31,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,45000,73000,49000" ) oxt "35000,67000,55000,71000" text (MLText uid 32,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "53200,45200,67300,46400" st " " tm "CommentText" wrapOption 3 visibleHeight 4000 visibleWidth 20000 ) ignorePrefs 1 titleBlock 1 ) *97 (CommentText uid 33,0 shape (Rectangle uid 34,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "57000,44000,73000,45000" ) oxt "39000,66000,55000,67000" text (MLText uid 35,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "57200,44500,57200,44500" st " %project_name " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 16000 ) position 1 ignorePrefs 1 titleBlock 1 ) *98 (CommentText uid 36,0 shape (Rectangle uid 37,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,44000,53000,46000" ) oxt "14000,66000,35000,68000" text (MLText uid 38,0 va (VaSet fg "32768,0,0" ) xt "37350,44400,47650,45600" st " " ju 0 tm "CommentText" wrapOption 3 visibleHeight 2000 visibleWidth 21000 ) position 1 ignorePrefs 1 titleBlock 1 ) *99 (CommentText uid 39,0 shape (Rectangle uid 40,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,47000,36000,48000" ) oxt "14000,69000,18000,70000" text (MLText uid 41,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "32200,47500,32200,47500" st " Path: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *100 (CommentText uid 42,0 shape (Rectangle uid 43,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,48000,36000,49000" ) oxt "14000,70000,18000,71000" text (MLText uid 44,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "32200,48500,32200,48500" st " Edited: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 titleBlock 1 ) *101 (CommentText uid 45,0 shape (Rectangle uid 46,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "36000,47000,53000,48000" ) oxt "18000,69000,35000,70000" text (MLText uid 47,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "36200,47500,36200,47500" st " %library/%unit/%view " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 titleBlock 1 ) ] shape (GroupingShape uid 17,0 va (VaSet vasetType 1 fg "65535,65535,65535" lineStyle 2 lineWidth 2 ) xt "32000,44000,73000,49000" ) oxt "14000,66000,55000,71000" ) ] bg "65535,65535,65535" grid (Grid origin "0,0" isVisible 1 isActive 1 xSpacing 1000 xySpacing 1000 xShown 1 yShown 1 color "26368,26368,26368" ) packageList *102 (PackageList uid 48,0 stg "VerticalLayoutStrategy" textVec [ *103 (Text uid 49,0 va (VaSet font "arial,8,1" ) xt "0,0,5400,1000" st "Package List" blo "0,800" ) *104 (MLText uid 50,0 va (VaSet ) xt "0,1000,17500,7000" st "LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; LIBRARY AhbLite; USE AhbLite.ahbLite.all;" tm "PackageList" ) ] ) windowSize "246,67,1263,757" viewArea "-500,-500,71320,48820" cachedDiagramExtent "0,0,78000,49000" hasePageBreakOrigin 1 pageBreakOrigin "0,0" defaultCommentText (CommentText shape (Rectangle layer 0 va (VaSet vasetType 1 fg "65280,65280,46080" lineColor "0,0,32768" ) xt "0,0,15000,5000" ) text (MLText va (VaSet fg "0,0,32768" ) xt "200,200,3200,1400" st " Text " tm "CommentText" wrapOption 3 visibleHeight 4600 visibleWidth 14600 ) ) defaultRequirementText (RequirementText shape (ZoomableIcon layer 0 va (VaSet vasetType 1 fg "59904,39936,65280" lineColor "0,0,32768" ) xt "0,0,1500,1750" iconName "reqTracerRequirement.bmp" iconMaskName "reqTracerRequirement.msk" ) autoResize 1 text (MLText va (VaSet fg "0,0,32768" font "arial,8,0" ) xt "500,2150,1400,3150" st " Text " tm "RequirementText" wrapOption 3 visibleHeight 1350 visibleWidth 1100 ) ) defaultPanel (Panel shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "32768,0,0" lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (Text va (VaSet font "Arial,8,1" ) xt "1000,1000,3800,2000" st "Panel0" blo "1000,1800" tm "PanelText" ) ) ) parentGraphicsRef (HdmGraphicsRef libraryName "AhbLiteComponents_test" entityName "ahbUart_tb" viewName "struct.bd" ) defaultSymbolBody (SymbolBody shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "15000,6000,33000,26000" ) biTextGroup (BiTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet font "Arial,8,1" ) xt "22200,15000,25800,16000" st "" blo "22200,15800" ) second (Text va (VaSet font "Arial,8,1" ) xt "22200,16000,24800,17000" st "" blo "22200,16800" ) ) gi *105 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix text (MLText va (VaSet font "Courier New,8,0" ) xt "0,12000,11500,12800" st "Generic Declarations" ) header "Generic Declarations" showHdrWhenContentsEmpty 1 ) elements [ ] ) portInstanceVisAsIs 1 portInstanceVis (PortSigDisplay sIVOD 1 ) portVis (PortSigDisplay sIVOD 1 ) ) defaultCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,1400,1750" st "In0" blo "0,1550" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "Courier New,8,0" ) ) thePort (LogicalPort decl (Decl n "In0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) defaultCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" bg "0,0,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,2800,1750" st "Buffer0" blo "0,1550" tm "CptPortNameMgr" ) ) dt (MLText va (VaSet font "Courier New,8,0" ) ) thePort (LogicalPort m 3 decl (Decl n "Buffer0" t "std_logic_vector" b "(15 DOWNTO 0)" o 0 ) ) ) DeclarativeBlock *106 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" declLabel (Text uid 2,0 va (VaSet font "Arial,8,1" ) xt "42000,0,47400,1000" st "Declarations" blo "42000,800" ) portLabel (Text uid 3,0 va (VaSet font "Arial,8,1" ) xt "42000,1000,44700,2000" st "Ports:" blo "42000,1800" ) externalLabel (Text uid 4,0 va (VaSet font "Arial,8,1" ) xt "42000,11600,44400,12600" st "User:" blo "42000,12400" ) internalLabel (Text uid 6,0 va (VaSet isHidden 1 font "Arial,8,1" ) xt "42000,0,47800,1000" st "Internal User:" blo "42000,800" ) externalText (MLText uid 5,0 va (VaSet font "Courier New,8,0" ) xt "44000,12600,44000,12600" tm "SyDeclarativeTextMgr" ) internalText (MLText uid 7,0 va (VaSet isHidden 1 font "Courier New,8,0" ) xt "42000,0,42000,0" tm "SyDeclarativeTextMgr" ) ) lastUid 1297,0 activeModelName "Symbol:GEN" )