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ju 2
blo "0,32500"
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xt "214000,3100,238600,4100"
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tg (WTG
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tg (WTG
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tg (WTG
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blo "16000,96500"
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tg (WTG
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blo "68000,26500"
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tg (WTG
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shape (CompositeShape
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tg (WTG
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blo "16000,80500"
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tg (CPTG
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ps "OnEdgeStrategy"
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ro 90
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xt "281000,153625,281750,154375"
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tg (CPTG
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xt "274601,153400,280001,154600"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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xt "264250,159625,265000,160375"
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tg (CPTG
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xt "265000,165600,283100,166600"
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xt "257000,153625,257750,154375"
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tg (CPTG
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ro 90
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xt "240250,153625,241000,154375"
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tg (CPTG
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tm "BdLibraryNameMgr"
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tm "CptNameMgr"
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tm "InstanceNameMgr"
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ga (GenericAssociation
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xt "241000,161800,256300,162800"
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xt "214000,59800,240700,60800"
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decl (Decl
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xt "214000,80500,241800,81500"
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decl (Decl
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xt "214000,70600,240800,71600"
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xt "214000,60700,240900,61700"
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xt "214000,61600,240900,62600"
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xt "214000,63400,240900,64400"
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xt "214000,28300,239500,29300"
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xt "214000,33700,239500,34700"
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decl (Decl
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xt "214000,35500,239400,36500"
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xt "214000,40900,239500,41900"
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ps "OnEdgeStrategy"
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ro 90
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xt "257000,116625,257750,117375"
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tg (CPTG
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xt "248200,116400,256000,117600"
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ps "OnEdgeStrategy"
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ro 90
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xt "240250,116625,241000,117375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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f (Text
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xt "242000,116400,247100,117600"
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blo "242000,117400"
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vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "241000,113000,257000,121000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 727,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*59 (Text
uid 728,0
va (VaSet
)
xt "241600,121800,245900,123000"
st "Curves"
blo "241600,122800"
tm "BdLibraryNameMgr"
)
*60 (Text
uid 729,0
va (VaSet
)
xt "241600,122800,251800,124000"
st "offsetToUnsigned"
blo "241600,123800"
tm "CptNameMgr"
)
*61 (Text
uid 730,0
va (VaSet
)
xt "241600,123800,244200,125000"
st "I14"
blo "241600,124800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 731,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 732,0
text (MLText
uid 733,0
va (VaSet
font "Verdana,8,0"
)
xt "241000,124800,256300,125800"
st "bitNb = signalBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*62 (SaComponent
uid 742,0
optionalChildren [
*63 (CptPort
uid 751,0
ps "OnEdgeStrategy"
shape (Triangle
uid 752,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,120625,265000,121375"
)
tg (CPTG
uid 753,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 754,0
va (VaSet
)
xt "266000,120400,269400,121600"
st "clock"
blo "266000,121400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 3
)
)
)
*64 (CptPort
uid 755,0
ps "OnEdgeStrategy"
shape (Triangle
uid 756,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,116625,265000,117375"
)
tg (CPTG
uid 757,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 758,0
va (VaSet
)
xt "266000,116400,272200,117600"
st "parallelIn"
blo "266000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "parallelIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 2
)
)
)
*65 (CptPort
uid 759,0
ps "OnEdgeStrategy"
shape (Triangle
uid 760,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,116625,281750,117375"
)
tg (CPTG
uid 761,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 762,0
va (VaSet
)
xt "274601,116400,280001,117600"
st "serialOut"
ju 2
blo "280001,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "serialOut"
t "std_ulogic"
o 1
)
)
)
*66 (CptPort
uid 763,0
ps "OnEdgeStrategy"
shape (Triangle
uid 764,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,122625,265000,123375"
)
tg (CPTG
uid 765,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 766,0
va (VaSet
)
xt "266000,122400,269300,123600"
st "reset"
blo "266000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
)
)
)
]
shape (Rectangle
uid 743,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "265000,113000,281000,125000"
)
oxt "114000,86000,130000,98000"
ttg (MlTextGroup
uid 744,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*67 (Text
uid 745,0
va (VaSet
)
xt "265600,124800,269900,126000"
st "Curves"
blo "265600,125800"
tm "BdLibraryNameMgr"
)
*68 (Text
uid 746,0
va (VaSet
)
xt "265600,125800,268700,127000"
st "DAC"
blo "265600,126800"
tm "CptNameMgr"
)
*69 (Text
uid 747,0
va (VaSet
)
xt "265600,126800,267500,128000"
st "I1"
blo "265600,127800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 748,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 749,0
text (MLText
uid 750,0
va (VaSet
font "Verdana,8,0"
)
xt "265000,128600,283100,129600"
st "signalBitNb = signalBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*70 (Net
uid 865,0
decl (Decl
n "samplesY"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 69
suid 22,0
)
declText (MLText
uid 866,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,71500,240800,72500"
st "SIGNAL samplesY            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*71 (Net
uid 867,0
decl (Decl
n "sampleY1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 62
suid 23,0
)
declText (MLText
uid 868,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,65200,240900,66200"
st "SIGNAL sampleY1            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*72 (Net
uid 869,0
decl (Decl
n "sampleY2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 63
suid 24,0
)
declText (MLText
uid 870,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,66100,240900,67100"
st "SIGNAL sampleY2            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*73 (Net
uid 871,0
decl (Decl
n "sampleY3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 64
suid 25,0
)
declText (MLText
uid 872,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,67000,240900,68000"
st "SIGNAL sampleY3            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*74 (Net
uid 873,0
decl (Decl
n "sampleY4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 65
suid 26,0
)
declText (MLText
uid 874,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,67900,240900,68900"
st "SIGNAL sampleY4            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*75 (Net
uid 875,0
decl (Decl
n "aY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 22
suid 27,0
)
declText (MLText
uid 876,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,29200,239500,30200"
st "SIGNAL aY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*76 (Net
uid 877,0
decl (Decl
n "bY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 28
suid 28,0
)
declText (MLText
uid 878,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,34600,239500,35600"
st "SIGNAL bY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*77 (Net
uid 879,0
decl (Decl
n "cY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 30
suid 29,0
)
declText (MLText
uid 880,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,36400,239400,37400"
st "SIGNAL cY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*78 (Net
uid 881,0
decl (Decl
n "dY"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 36
suid 30,0
)
declText (MLText
uid 882,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,41800,239500,42800"
st "SIGNAL dY                  : signed(coeffBitNb-1 DOWNTO 0)"
)
)
*79 (Net
uid 883,0
decl (Decl
n "sampleY"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 61
suid 31,0
)
declText (MLText
uid 884,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,64300,240700,65300"
st "SIGNAL sampleY             : signed(signalBitNb-1 DOWNTO 0)"
)
)
*80 (Net
uid 885,0
decl (Decl
n "unsignedY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 80
suid 32,0
)
declText (MLText
uid 886,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,81400,241800,82400"
st "SIGNAL unsignedY           : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*81 (Net
uid 990,0
decl (Decl
n "selControl"
t "std_ulogic"
o 71
suid 33,0
)
declText (MLText
uid 991,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,73300,230400,74300"
st "SIGNAL selControl          : std_ulogic"
)
)
*82 (Net
uid 1047,0
decl (Decl
n "selSize"
t "std_ulogic"
o 72
suid 34,0
)
declText (MLText
uid 1048,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,74200,230000,75200"
st "SIGNAL selSize             : std_ulogic"
)
)
*83 (Net
uid 1055,0
decl (Decl
n "selSpeed"
t "std_ulogic"
o 73
suid 35,0
)
declText (MLText
uid 1056,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,75100,230600,76100"
st "SIGNAL selSpeed            : std_ulogic"
)
)
*84 (Net
uid 1063,0
decl (Decl
n "selX"
t "std_ulogic"
o 74
suid 36,0
)
declText (MLText
uid 1064,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,76000,229800,77000"
st "SIGNAL selX                : std_ulogic"
)
)
*85 (Net
uid 1071,0
decl (Decl
n "selY"
t "std_ulogic"
o 75
suid 37,0
)
declText (MLText
uid 1072,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,76900,229800,77900"
st "SIGNAL selY                : std_ulogic"
)
)
*86 (Net
uid 1348,0
decl (Decl
n "run"
t "std_ulogic"
o 55
suid 38,0
)
declText (MLText
uid 1349,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,58900,229800,59900"
st "SIGNAL run                 : std_ulogic"
)
)
*87 (Net
uid 1356,0
decl (Decl
n "updatePattern"
t "std_ulogic"
o 81
suid 39,0
)
declText (MLText
uid 1357,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,82300,231200,83300"
st "SIGNAL updatePattern       : std_ulogic"
)
)
*88 (Net
uid 1470,0
decl (Decl
n "patternSize"
t "unsigned"
b "(dataBitNb/2-1 DOWNTO 0)"
o 53
suid 40,0
)
declText (MLText
uid 1471,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,57100,242000,58100"
st "SIGNAL patternSize         : unsigned(dataBitNb/2-1 DOWNTO 0)"
)
)
*89 (PortIoIn
uid 1565,0
shape (CompositeShape
uid 1566,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1567,0
sl 0
ro 270
xt "17000,9625,18500,10375"
)
(Line
uid 1568,0
sl 0
ro 270
xt "18500,10000,19000,10000"
pts [
"18500,10000"
"19000,10000"
]
)
]
)
tg (WTG
uid 1569,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1570,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-7800,9300,16000,10700"
st "dataIn : (dataBitNb-1 DOWNTO 0)"
ju 2
blo "16000,10500"
tm "WireNameMgr"
)
)
)
*90 (PortIoOut
uid 1577,0
shape (CompositeShape
uid 1578,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1579,0
sl 0
ro 90
xt "17000,3625,18500,4375"
)
(Line
uid 1580,0
sl 0
ro 90
xt "18500,4000,19000,4000"
pts [
"19000,4000"
"18500,4000"
]
)
]
)
tg (WTG
uid 1581,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1582,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-8800,3300,16000,4700"
st "dataOut : (dataBitNb-1 DOWNTO 0)"
ju 2
blo "16000,4500"
tm "WireNameMgr"
)
)
)
*91 (Net
uid 1589,0
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
suid 41,0
)
declText (MLText
uid 1590,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,11200,240700,12200"
st "dataOut             : std_logic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*92 (Net
uid 1776,0
decl (Decl
n "updatePeriod"
t "unsigned"
b "(dataBitNb-1 DOWNTO 0)"
o 82
suid 42,0
)
declText (MLText
uid 1777,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,83200,241600,84200"
st "SIGNAL updatePeriod        : unsigned(dataBitNb-1 DOWNTO 0)"
)
)
*93 (SaComponent
uid 1816,0
optionalChildren [
*94 (CptPort
uid 1784,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1785,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,67625,91750,68375"
)
tg (CPTG
uid 1786,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1787,0
va (VaSet
)
xt "82000,67400,90000,68600"
st "updatePeriod"
ju 2
blo "90000,68400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "updatePeriod"
t "unsigned"
b "(dataBitNb-1 DOWNTO 0)"
o 1
)
)
)
*95 (CptPort
uid 1788,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1789,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,67625,75000,68375"
)
tg (CPTG
uid 1790,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1791,0
va (VaSet
)
xt "76000,67400,80000,68600"
st "dataIn"
blo "76000,68400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
)
)
)
*96 (CptPort
uid 1792,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1793,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,69625,75000,70375"
)
tg (CPTG
uid 1794,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1795,0
va (VaSet
)
xt "76000,69400,80800,70600"
st "dataOut"
blo "76000,70400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
)
)
)
*97 (CptPort
uid 1796,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1797,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,73625,75000,74375"
)
tg (CPTG
uid 1798,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1799,0
va (VaSet
)
xt "76000,73400,84400,74600"
st "writeHighByte"
blo "76000,74400"
)
)
thePort (LogicalPort
decl (Decl
n "writeHighByte"
t "std_ulogic"
o 4
)
)
)
*98 (CptPort
uid 1800,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1801,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,77625,75000,78375"
)
tg (CPTG
uid 1802,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1803,0
va (VaSet
)
xt "76000,77400,77900,78600"
st "en"
blo "76000,78400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 5
)
)
)
*99 (CptPort
uid 1804,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1805,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,81625,75000,82375"
)
tg (CPTG
uid 1806,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1807,0
va (VaSet
)
xt "76000,81400,79400,82600"
st "clock"
blo "76000,82400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 6
)
)
)
*100 (CptPort
uid 1808,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1809,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,83625,75000,84375"
)
tg (CPTG
uid 1810,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1811,0
va (VaSet
)
xt "76000,83400,79300,84600"
st "reset"
blo "76000,84400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 7
)
)
)
*101 (CptPort
uid 1812,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1813,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,75625,75000,76375"
)
tg (CPTG
uid 1814,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1815,0
va (VaSet
)
xt "76000,75400,84000,76600"
st "writeLowByte"
blo "76000,76400"
)
)
thePort (LogicalPort
decl (Decl
n "writeLowByte"
t "std_ulogic"
o 8
)
)
)
]
shape (Rectangle
uid 1817,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,64000,91000,86000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1818,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*102 (Text
uid 1819,0
va (VaSet
)
xt "75600,85800,79900,87000"
st "Curves"
blo "75600,86800"
tm "BdLibraryNameMgr"
)
*103 (Text
uid 1820,0
va (VaSet
)
xt "75600,86800,85100,88000"
st "periphSpeedReg"
blo "75600,87800"
tm "CptNameMgr"
)
*104 (Text
uid 1821,0
va (VaSet
)
xt "75600,87800,77500,89000"
st "I3"
blo "75600,88800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1822,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1823,0
text (MLText
uid 1824,0
va (VaSet
font "Verdana,8,0"
)
xt "75000,89600,91600,90600"
st "dataBitNb = dataBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*105 (SaComponent
uid 1853,0
optionalChildren [
*106 (CptPort
uid 1825,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1826,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,39625,91750,40375"
)
tg (CPTG
uid 1827,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1828,0
va (VaSet
)
xt "82900,39400,90000,40600"
st "patternSize"
ju 2
blo "90000,40400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "patternSize"
t "unsigned"
b "(dataBitNb/2-1 DOWNTO 0)"
o 1
)
)
)
*107 (CptPort
uid 1829,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1830,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,39625,75000,40375"
)
tg (CPTG
uid 1831,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1832,0
va (VaSet
)
xt "76000,39400,80000,40600"
st "dataIn"
blo "76000,40400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
)
)
)
*108 (CptPort
uid 1833,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1834,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,41625,75000,42375"
)
tg (CPTG
uid 1835,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1836,0
va (VaSet
)
xt "76000,41400,80800,42600"
st "dataOut"
blo "76000,42400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
)
)
)
*109 (CptPort
uid 1837,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1838,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,45625,75000,46375"
)
tg (CPTG
uid 1839,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1840,0
va (VaSet
)
xt "76000,45400,79100,46600"
st "write"
blo "76000,46400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 4
)
)
)
*110 (CptPort
uid 1841,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1842,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,47625,75000,48375"
)
tg (CPTG
uid 1843,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1844,0
va (VaSet
)
xt "76000,47400,77900,48600"
st "en"
blo "76000,48400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 5
)
)
)
*111 (CptPort
uid 1845,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1846,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,51625,75000,52375"
)
tg (CPTG
uid 1847,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1848,0
va (VaSet
)
xt "76000,51400,79400,52600"
st "clock"
blo "76000,52400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 6
)
)
)
*112 (CptPort
uid 1849,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1850,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,53625,75000,54375"
)
tg (CPTG
uid 1851,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1852,0
va (VaSet
)
xt "76000,53400,79300,54600"
st "reset"
blo "76000,54400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 7
)
)
)
]
shape (Rectangle
uid 1854,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,36000,91000,56000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1855,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*113 (Text
uid 1856,0
va (VaSet
)
xt "75600,55800,79900,57000"
st "Curves"
blo "75600,56800"
tm "BdLibraryNameMgr"
)
*114 (Text
uid 1857,0
va (VaSet
)
xt "75600,56800,84100,58000"
st "periphSizeReg"
blo "75600,57800"
tm "CptNameMgr"
)
*115 (Text
uid 1858,0
va (VaSet
)
xt "75600,57800,77500,59000"
st "I5"
blo "75600,58800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1859,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1860,0
text (MLText
uid 1861,0
va (VaSet
font "Verdana,8,0"
)
xt "75000,59600,91600,60600"
st "dataBitNb = dataBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*116 (SaComponent
uid 1919,0
optionalChildren [
*117 (CptPort
uid 1903,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1904,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,175625,177750,176375"
)
tg (CPTG
uid 1905,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1906,0
va (VaSet
)
xt "169400,175400,176000,176600"
st "triggerOut"
ju 2
blo "176000,176400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "triggerOut"
t "std_ulogic"
o 1
)
)
)
*118 (CptPort
uid 1907,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1908,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,179625,161000,180375"
)
tg (CPTG
uid 1909,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1910,0
va (VaSet
)
xt "162000,179400,165400,180600"
st "clock"
blo "162000,180400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*119 (CptPort
uid 1911,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1912,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,181625,161000,182375"
)
tg (CPTG
uid 1913,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1914,0
va (VaSet
)
xt "162000,181400,165300,182600"
st "reset"
blo "162000,182400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*120 (CptPort
uid 1915,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1916,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,175625,161000,176375"
)
tg (CPTG
uid 1917,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1918,0
va (VaSet
)
xt "162000,175400,163900,176600"
st "en"
blo "162000,176400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 4
)
)
)
]
shape (Rectangle
uid 1920,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,172000,177000,184000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1921,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*121 (Text
uid 1922,0
va (VaSet
)
xt "161600,184800,165900,186000"
st "Curves"
blo "161600,185800"
tm "BdLibraryNameMgr"
)
*122 (Text
uid 1923,0
va (VaSet
)
xt "161600,185800,172400,187000"
st "interpolatorTrigger"
blo "161600,186800"
tm "CptNameMgr"
)
*123 (Text
uid 1924,0
va (VaSet
)
xt "161600,186800,163500,188000"
st "I6"
blo "161600,187800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1925,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1926,0
text (MLText
uid 1927,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,187600,182800,188600"
st "counterBitNb = sampleCountBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "counterBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*124 (Net
uid 1993,0
decl (Decl
n "interpolationEnable"
t "std_ulogic"
o 41
suid 43,0
)
declText (MLText
uid 1994,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,46300,231400,47300"
st "SIGNAL interpolationEnable : std_ulogic"
)
)
*125 (Net
uid 2776,0
decl (Decl
n "addrX"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 24
suid 44,0
)
declText (MLText
uid 2777,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,31000,244900,32000"
st "SIGNAL addrX               : unsigned(patternAddressBitNb-1 DOWNTO 0)"
)
)
*126 (Net
uid 2850,0
decl (Decl
n "cntIncrX"
t "std_ulogic"
o 31
suid 45,0
)
declText (MLText
uid 2851,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,37300,230200,38300"
st "SIGNAL cntIncrX            : std_ulogic"
)
)
*127 (Net
uid 2852,0
decl (Decl
n "memWrX"
t "std_ulogic"
o 46
suid 46,0
)
declText (MLText
uid 2853,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,50800,231300,51800"
st "SIGNAL memWrX              : std_ulogic"
)
)
*128 (Net
uid 2854,0
decl (Decl
n "memEnX"
t "std_ulogic"
o 43
suid 47,0
)
declText (MLText
uid 2855,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,48100,231200,49100"
st "SIGNAL memEnX              : std_ulogic"
)
)
*129 (HdlText
uid 3135,0
optionalChildren [
*130 (EmbeddedText
uid 3140,0
commentText (CommentText
uid 3141,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 3142,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "132000,152000,146000,156000"
)
oxt "0,0,18000,5000"
text (MLText
uid 3143,0
va (VaSet
)
xt "132200,152200,144900,155800"
st "
samplesX <= cosine when selSinCos = '1'
  else signed(memX);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 3136,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "131000,150000,147000,158000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3137,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*131 (Text
uid 3138,0
va (VaSet
)
xt "131400,158000,134000,159200"
st "eb2"
blo "131400,159000"
tm "HdlTextNameMgr"
)
*132 (Text
uid 3139,0
va (VaSet
)
xt "131400,159000,132800,160200"
st "2"
blo "131400,160000"
tm "HdlTextNumberMgr"
)
]
)
)
*133 (Net
uid 3152,0
decl (Decl
n "memX"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 49
suid 48,0
)
declText (MLText
uid 3153,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,53500,244700,54500"
st "SIGNAL memX                : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*134 (SaComponent
uid 3378,0
optionalChildren [
*135 (CptPort
uid 3354,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3355,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,159625,75000,160375"
)
tg (CPTG
uid 3356,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3357,0
va (VaSet
)
xt "76000,159400,77900,160600"
st "en"
blo "76000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 1
)
)
)
*136 (CptPort
uid 3358,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3359,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,163625,75000,164375"
)
tg (CPTG
uid 3360,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3361,0
va (VaSet
)
xt "76000,163400,79400,164600"
st "clock"
blo "76000,164400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*137 (CptPort
uid 3362,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3363,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,165625,75000,166375"
)
tg (CPTG
uid 3364,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3365,0
va (VaSet
)
xt "76000,165400,79300,166600"
st "reset"
blo "76000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*138 (CptPort
uid 3366,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3367,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,157625,75000,158375"
)
tg (CPTG
uid 3368,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3369,0
va (VaSet
)
xt "76000,157400,82500,158600"
st "updateMem"
blo "76000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "updateMem"
t "std_ulogic"
o 4
)
)
)
*139 (CptPort
uid 3370,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3371,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,155625,91750,156375"
)
tg (CPTG
uid 3372,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3373,0
va (VaSet
)
xt "87100,155400,90000,156600"
st "addr"
ju 2
blo "90000,156400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 5
)
)
)
*140 (CptPort
uid 3374,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3375,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,155625,75000,156375"
)
tg (CPTG
uid 3376,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3377,0
va (VaSet
)
xt "76000,155400,83100,156600"
st "patternSize"
blo "76000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "patternSize"
t "unsigned"
b "(patternSizeBitNb-1 DOWNTO 0)"
o 6
)
)
)
]
shape (Rectangle
uid 3379,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,152000,91000,168000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3380,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*141 (Text
uid 3381,0
va (VaSet
)
xt "75600,167800,79900,169000"
st "Curves"
blo "75600,168800"
tm "BdLibraryNameMgr"
)
*142 (Text
uid 3382,0
va (VaSet
)
xt "75600,168800,91000,170000"
st "blockRAMAddressCounter"
blo "75600,169800"
tm "CptNameMgr"
)
*143 (Text
uid 3383,0
va (VaSet
)
xt "75600,169800,78200,171000"
st "I18"
blo "75600,170800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3384,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3385,0
text (MLText
uid 3386,0
va (VaSet
font "Verdana,8,0"
)
xt "75000,171600,98800,173600"
st "addressBitNb     = patternAddressBitNb    ( positive ) 
patternSizeBitNb = dataBitNb/2            ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "patternSizeBitNb"
type "positive"
value "dataBitNb/2"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*144 (SaComponent
uid 3623,0
optionalChildren [
*145 (CptPort
uid 3603,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3604,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "123000,65625,123750,66375"
)
tg (CPTG
uid 3605,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3606,0
va (VaSet
)
xt "116100,65400,122000,66600"
st "enableOut"
ju 2
blo "122000,66400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "enableOut"
t "std_ulogic"
o 1
)
)
)
*146 (CptPort
uid 3607,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3608,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,71625,107000,72375"
)
tg (CPTG
uid 3609,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3610,0
va (VaSet
)
xt "108000,71400,111400,72600"
st "clock"
blo "108000,72400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*147 (CptPort
uid 3611,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3612,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,73625,107000,74375"
)
tg (CPTG
uid 3613,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3614,0
va (VaSet
)
xt "108000,73400,111300,74600"
st "reset"
blo "108000,74400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*148 (CptPort
uid 3615,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3616,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,67625,107000,68375"
)
tg (CPTG
uid 3617,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3618,0
va (VaSet
)
xt "108000,67400,116000,68600"
st "updatePeriod"
blo "108000,68400"
)
)
thePort (LogicalPort
decl (Decl
n "updatePeriod"
t "unsigned"
b "(dataBitNb-1 DOWNTO 0)"
o 4
)
)
)
*149 (CptPort
uid 3619,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3620,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,65625,107000,66375"
)
tg (CPTG
uid 3621,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3622,0
va (VaSet
)
xt "108000,65400,113100,66600"
st "enableIn"
blo "108000,66400"
)
)
thePort (LogicalPort
decl (Decl
n "enableIn"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 3624,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "107000,62000,123000,76000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3625,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*150 (Text
uid 3626,0
va (VaSet
)
xt "107600,75800,111900,77000"
st "Curves"
blo "107600,76800"
tm "BdLibraryNameMgr"
)
*151 (Text
uid 3627,0
va (VaSet
)
xt "107600,76800,120900,78000"
st "periphSpeedController"
blo "107600,77800"
tm "CptNameMgr"
)
*152 (Text
uid 3628,0
va (VaSet
)
xt "107600,77800,110200,79000"
st "I15"
blo "107600,78800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3629,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3630,0
text (MLText
uid 3631,0
va (VaSet
font "Verdana,8,0"
)
xt "107000,79600,123600,80600"
st "dataBitNb = dataBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*153 (SaComponent
uid 3681,0
optionalChildren [
*154 (CptPort
uid 3690,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3691,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,109625,75000,110375"
)
tg (CPTG
uid 3692,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3693,0
va (VaSet
)
xt "76000,109400,77900,110600"
st "en"
blo "76000,110400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 1
)
)
)
*155 (CptPort
uid 3694,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3695,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,113625,75000,114375"
)
tg (CPTG
uid 3696,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3697,0
va (VaSet
)
xt "76000,113400,79400,114600"
st "clock"
blo "76000,114400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*156 (CptPort
uid 3698,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3699,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,115625,75000,116375"
)
tg (CPTG
uid 3700,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3701,0
va (VaSet
)
xt "76000,115400,79300,116600"
st "reset"
blo "76000,116400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*157 (CptPort
uid 3702,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3703,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,107625,75000,108375"
)
tg (CPTG
uid 3704,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3705,0
va (VaSet
)
xt "76000,107400,82500,108600"
st "updateMem"
blo "76000,108400"
)
)
thePort (LogicalPort
decl (Decl
n "updateMem"
t "std_ulogic"
o 4
)
)
)
*158 (CptPort
uid 3706,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3707,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,105625,91750,106375"
)
tg (CPTG
uid 3708,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 3709,0
va (VaSet
)
xt "87100,105400,90000,106600"
st "addr"
ju 2
blo "90000,106400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 5
)
)
)
*159 (CptPort
uid 3710,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3711,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,105625,75000,106375"
)
tg (CPTG
uid 3712,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3713,0
va (VaSet
)
xt "76000,105400,83100,106600"
st "patternSize"
blo "76000,106400"
)
)
thePort (LogicalPort
decl (Decl
n "patternSize"
t "unsigned"
b "(patternSizeBitNb-1 DOWNTO 0)"
o 6
)
)
)
]
shape (Rectangle
uid 3682,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,102000,91000,118000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3683,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*160 (Text
uid 3684,0
va (VaSet
)
xt "75600,117800,79900,119000"
st "Curves"
blo "75600,118800"
tm "BdLibraryNameMgr"
)
*161 (Text
uid 3685,0
va (VaSet
)
xt "75600,118800,91000,120000"
st "blockRAMAddressCounter"
blo "75600,119800"
tm "CptNameMgr"
)
*162 (Text
uid 3686,0
va (VaSet
)
xt "75600,119800,78200,121000"
st "I20"
blo "75600,120800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 3687,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 3688,0
text (MLText
uid 3689,0
va (VaSet
font "Verdana,8,0"
)
xt "75000,121600,98800,123600"
st "addressBitNb     = patternAddressBitNb    ( positive ) 
patternSizeBitNb = dataBitNb/2            ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "patternSizeBitNb"
type "positive"
value "dataBitNb/2"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*163 (Net
uid 3827,0
decl (Decl
n "cntIncrY"
t "std_ulogic"
o 32
suid 49,0
)
declText (MLText
uid 3828,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,38200,230200,39200"
st "SIGNAL cntIncrY            : std_ulogic"
)
)
*164 (Net
uid 3890,0
decl (Decl
n "addrY"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 25
suid 50,0
)
declText (MLText
uid 3891,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,31900,244900,32900"
st "SIGNAL addrY               : unsigned(patternAddressBitNb-1 DOWNTO 0)"
)
)
*165 (Net
uid 3892,0
decl (Decl
n "memWrY"
t "std_ulogic"
o 47
suid 51,0
)
declText (MLText
uid 3893,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,51700,231300,52700"
st "SIGNAL memWrY              : std_ulogic"
)
)
*166 (Net
uid 3894,0
decl (Decl
n "memEnY"
t "std_ulogic"
o 44
suid 52,0
)
declText (MLText
uid 3895,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,49000,231200,50000"
st "SIGNAL memEnY              : std_ulogic"
)
)
*167 (HdlText
uid 3896,0
optionalChildren [
*168 (EmbeddedText
uid 3901,0
commentText (CommentText
uid 3902,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 3903,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "132000,115000,146000,119000"
)
oxt "0,0,18000,5000"
text (MLText
uid 3904,0
va (VaSet
)
xt "132200,115200,144900,118800"
st "
samplesY <= sine when selSinCos = '1'
  else signed(memY);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 3897,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "131000,113000,147000,121000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 3898,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*169 (Text
uid 3899,0
va (VaSet
)
xt "131400,121000,134000,122200"
st "eb1"
blo "131400,122000"
tm "HdlTextNameMgr"
)
*170 (Text
uid 3900,0
va (VaSet
)
xt "131400,122000,132800,123200"
st "1"
blo "131400,123000"
tm "HdlTextNumberMgr"
)
]
)
)
*171 (Net
uid 3913,0
decl (Decl
n "memY"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 50
suid 53,0
)
declText (MLText
uid 3914,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,54400,244700,55400"
st "SIGNAL memY                : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*172 (PortIoOut
uid 4041,0
shape (CompositeShape
uid 4042,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4043,0
sl 0
ro 270
xt "289500,5625,291000,6375"
)
(Line
uid 4044,0
sl 0
ro 270
xt "289000,6000,289500,6000"
pts [
"289000,6000"
"289500,6000"
]
)
]
)
tg (WTG
uid 4045,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4046,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "292000,5300,305600,6700"
st "testOut : (1 TO 16)"
blo "292000,6500"
tm "WireNameMgr"
)
)
)
*173 (Net
uid 4053,0
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO 16)"
o 12
suid 54,0
)
declText (MLText
uid 4054,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,12100,234500,13100"
st "testOut             : std_ulogic_vector(1 TO 16)"
)
)
*174 (HdlText
uid 4055,0
optionalChildren [
*175 (EmbeddedText
uid 4060,0
commentText (CommentText
uid 4061,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 4062,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "266000,5000,280000,27000"
)
oxt "0,0,18000,5000"
text (MLText
uid 4063,0
va (VaSet
)
xt "266200,5200,278400,26800"
st "
testout(1) <= run;
testout(2) <= updatePattern;
testout(3) <= interpolationEnable;
testout(4) <= newPolynom;
testout(5) <= selSinCos;
testout(6) <= cs;
testout(7) <= rd;
testout(8) <= wrH;
testout(9) <= wrL;
testout(10) <= addrReg(1);
testout(11) <= dataInReg(0);
--testout(10) <= selControl;
--testout(11) <= selSize;
testout(12) <= selSpeed;
testout(13) <= selX;
testout(14) <= selY;
testout(15) <= cntIncrX;
testout(16) <= cntIncrY;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 22000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 4056,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "265000,4000,281000,28000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4057,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*176 (Text
uid 4058,0
va (VaSet
)
xt "265400,28000,268000,29200"
st "eb3"
blo "265400,29000"
tm "HdlTextNameMgr"
)
*177 (Text
uid 4059,0
va (VaSet
)
xt "265400,29000,266800,30200"
st "3"
blo "265400,30000"
tm "HdlTextNumberMgr"
)
]
)
)
*178 (SaComponent
uid 4245,0
optionalChildren [
*179 (CptPort
uid 4225,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4226,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,57625,43750,58375"
)
tg (CPTG
uid 4227,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4228,0
va (VaSet
)
xt "35400,57400,42000,58600"
st "writePulse"
ju 2
blo "42000,58400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "writePulse"
t "std_ulogic"
o 1
)
)
)
*180 (CptPort
uid 4229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4230,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,57625,27000,58375"
)
tg (CPTG
uid 4231,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4232,0
va (VaSet
)
xt "28000,57400,31100,58600"
st "write"
blo "28000,58400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 2
)
)
)
*181 (CptPort
uid 4233,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4234,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,59625,27000,60375"
)
tg (CPTG
uid 4235,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4236,0
va (VaSet
)
xt "28000,59400,34700,60600"
st "chipSelect"
blo "28000,60400"
)
)
thePort (LogicalPort
decl (Decl
n "chipSelect"
t "std_ulogic"
o 3
)
)
)
*182 (CptPort
uid 4237,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4238,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,63625,27000,64375"
)
tg (CPTG
uid 4239,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4240,0
va (VaSet
)
xt "28000,63400,31400,64600"
st "clock"
blo "28000,64400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
)
)
)
*183 (CptPort
uid 4241,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4242,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,65625,27000,66375"
)
tg (CPTG
uid 4243,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4244,0
va (VaSet
)
xt "28000,65400,31300,66600"
st "reset"
blo "28000,66400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 4246,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "27000,54000,43000,68000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4247,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*184 (Text
uid 4248,0
va (VaSet
)
xt "27600,67800,31900,69000"
st "Curves"
blo "27600,68800"
tm "BdLibraryNameMgr"
)
*185 (Text
uid 4249,0
va (VaSet
)
xt "27600,68800,37500,70000"
st "periphWritePulse"
blo "27600,69800"
tm "CptNameMgr"
)
*186 (Text
uid 4250,0
va (VaSet
)
xt "27600,69800,30200,71000"
st "I22"
blo "27600,70800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4251,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4252,0
text (MLText
uid 4253,0
va (VaSet
font "Verdana,8,0"
)
xt "-7000,45000,-7000,45000"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*187 (Net
uid 4290,0
decl (Decl
n "wrHPulse"
t "std_ulogic"
o 85
suid 55,0
)
declText (MLText
uid 4291,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,85900,230700,86900"
st "SIGNAL wrHPulse            : std_ulogic"
)
)
*188 (SaComponent
uid 4300,0
optionalChildren [
*189 (CptPort
uid 4309,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4310,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,79625,43750,80375"
)
tg (CPTG
uid 4311,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4312,0
va (VaSet
)
xt "35400,79400,42000,80600"
st "writePulse"
ju 2
blo "42000,80400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "writePulse"
t "std_ulogic"
o 1
)
)
)
*190 (CptPort
uid 4313,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4314,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,79625,27000,80375"
)
tg (CPTG
uid 4315,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4316,0
va (VaSet
)
xt "28000,79400,31100,80600"
st "write"
blo "28000,80400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 2
)
)
)
*191 (CptPort
uid 4317,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4318,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,81625,27000,82375"
)
tg (CPTG
uid 4319,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4320,0
va (VaSet
)
xt "28000,81400,34700,82600"
st "chipSelect"
blo "28000,82400"
)
)
thePort (LogicalPort
decl (Decl
n "chipSelect"
t "std_ulogic"
o 3
)
)
)
*192 (CptPort
uid 4321,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4322,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,85625,27000,86375"
)
tg (CPTG
uid 4323,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4324,0
va (VaSet
)
xt "28000,85400,31400,86600"
st "clock"
blo "28000,86400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
)
)
)
*193 (CptPort
uid 4325,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4326,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,87625,27000,88375"
)
tg (CPTG
uid 4327,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4328,0
va (VaSet
)
xt "28000,87400,31300,88600"
st "reset"
blo "28000,88400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 4301,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "27000,76000,43000,90000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4302,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*194 (Text
uid 4303,0
va (VaSet
)
xt "27600,89800,31900,91000"
st "Curves"
blo "27600,90800"
tm "BdLibraryNameMgr"
)
*195 (Text
uid 4304,0
va (VaSet
)
xt "27600,90800,37500,92000"
st "periphWritePulse"
blo "27600,91800"
tm "CptNameMgr"
)
*196 (Text
uid 4305,0
va (VaSet
)
xt "27600,91800,30200,93000"
st "I23"
blo "27600,92800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4306,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4307,0
text (MLText
uid 4308,0
va (VaSet
font "Verdana,8,0"
)
xt "-7000,67000,-7000,67000"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*197 (Net
uid 4347,0
decl (Decl
n "wrLPulse"
t "std_ulogic"
o 86
suid 56,0
)
declText (MLText
uid 4348,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,86800,230500,87800"
st "SIGNAL wrLPulse            : std_ulogic"
)
)
*198 (HdlText
uid 4719,0
optionalChildren [
*199 (EmbeddedText
uid 4724,0
commentText (CommentText
uid 4725,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 4726,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "150000,75000,164000,77000"
)
oxt "0,0,18000,5000"
text (MLText
uid 4727,0
va (VaSet
)
xt "150200,75200,164000,76400"
st "
step <= to_unsigned(1, step'length);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 4720,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "149000,74000,165000,78000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4721,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*200 (Text
uid 4722,0
va (VaSet
)
xt "149400,78000,152000,79200"
st "eb4"
blo "149400,79000"
tm "HdlTextNameMgr"
)
*201 (Text
uid 4723,0
va (VaSet
)
xt "149400,79000,150800,80200"
st "4"
blo "149400,80000"
tm "HdlTextNumberMgr"
)
]
)
)
*202 (Net
uid 4800,0
decl (Decl
n "phase"
t "unsigned"
b "(phaseBitNb-1 DOWNTO 0)"
o 54
suid 57,0
)
declText (MLText
uid 4801,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,58000,241400,59000"
st "SIGNAL phase               : unsigned(phaseBitNb-1 DOWNTO 0)"
)
)
*203 (Net
uid 4802,0
decl (Decl
n "step"
t "unsigned"
b "(phaseBitNb-1 DOWNTO 0)"
o 78
suid 58,0
)
declText (MLText
uid 4803,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,79600,241000,80600"
st "SIGNAL step                : unsigned(phaseBitNb-1 DOWNTO 0)"
)
)
*204 (Net
uid 4858,0
decl (Decl
n "sine"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 77
suid 59,0
)
declText (MLText
uid 4859,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,78700,239800,79700"
st "SIGNAL sine                : signed(signalBitNb-1 DOWNTO 0)"
)
)
*205 (SaComponent
uid 4923,0
optionalChildren [
*206 (CptPort
uid 4903,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4904,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,89625,161000,90375"
)
tg (CPTG
uid 4905,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4906,0
va (VaSet
)
xt "162000,89400,165400,90600"
st "clock"
blo "162000,90400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*207 (CptPort
uid 4907,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4908,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,83625,177750,84375"
)
tg (CPTG
uid 4909,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4910,0
va (VaSet
)
xt "170800,83400,176000,84600"
st "sawtooth"
ju 2
blo "176000,84400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sawtooth"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 1
)
)
)
*208 (CptPort
uid 4911,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4912,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,91625,161000,92375"
)
tg (CPTG
uid 4913,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4914,0
va (VaSet
)
xt "162000,91400,165300,92600"
st "reset"
blo "162000,92400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*209 (CptPort
uid 4915,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4916,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,83625,161000,84375"
)
tg (CPTG
uid 4917,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4918,0
va (VaSet
)
xt "162000,83400,164900,84600"
st "step"
blo "162000,84400"
)
)
thePort (LogicalPort
decl (Decl
n "step"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 4
)
)
)
*210 (CptPort
uid 4919,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4920,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,85625,161000,86375"
)
tg (CPTG
uid 4921,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4922,0
va (VaSet
)
xt "162000,85400,163900,86600"
st "en"
blo "162000,86400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 4924,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,80000,177000,94000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4925,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*211 (Text
uid 4926,0
va (VaSet
)
xt "161600,93800,165900,95000"
st "Curves"
blo "161600,94800"
tm "BdLibraryNameMgr"
)
*212 (Text
uid 4927,0
va (VaSet
)
xt "161600,94800,169500,96000"
st "sawtoothGen"
blo "161600,95800"
tm "CptNameMgr"
)
*213 (Text
uid 4928,0
va (VaSet
)
xt "161600,95800,164200,97000"
st "I24"
blo "161600,96800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4929,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4930,0
text (MLText
uid 4931,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,96600,176400,97600"
st "bitNb = phaseBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "phaseBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*214 (PortIoIn
uid 5080,0
shape (CompositeShape
uid 5081,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5082,0
sl 0
ro 270
xt "151000,69625,152500,70375"
)
(Line
uid 5083,0
sl 0
ro 270
xt "152500,70000,153000,70000"
pts [
"152500,70000"
"153000,70000"
]
)
]
)
tg (WTG
uid 5084,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5085,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "143100,69300,150000,70700"
st "selSinCos"
ju 2
blo "150000,70500"
tm "WireNameMgr"
)
)
)
*215 (HdlText
uid 5244,0
optionalChildren [
*216 (EmbeddedText
uid 5249,0
commentText (CommentText
uid 5250,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 5251,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "162000,65000,176000,71000"
)
oxt "0,0,18000,5000"
text (MLText
uid 5252,0
va (VaSet
)
xt "162200,65200,176100,71200"
st "
interpolationEnable <= '1' when selSinCos = '1'
  else interpolationEn;
--interpolateLinear <= '1' when selSinCos = '1'
--  else interpolateLin;
interpolateLinear <= interpolateLin;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 6000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 5245,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "161000,64000,177000,72000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 5246,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*217 (Text
uid 5247,0
va (VaSet
)
xt "161400,72000,164000,73200"
st "eb5"
blo "161400,73000"
tm "HdlTextNameMgr"
)
*218 (Text
uid 5248,0
va (VaSet
)
xt "161400,73000,162800,74200"
st "5"
blo "161400,74000"
tm "HdlTextNumberMgr"
)
]
)
)
*219 (Net
uid 5261,0
decl (Decl
n "interpolationEn"
t "std_ulogic"
o 40
suid 60,0
)
declText (MLText
uid 5262,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,45400,230900,46400"
st "SIGNAL interpolationEn     : std_ulogic"
)
)
*220 (Net
uid 5936,0
decl (Decl
n "cosine"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 34
suid 61,0
)
declText (MLText
uid 5937,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,40000,240100,41000"
st "SIGNAL cosine              : signed(signalBitNb-1 DOWNTO 0)"
)
)
*221 (SaComponent
uid 5956,0
optionalChildren [
*222 (CptPort
uid 5944,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5945,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,83625,201750,84375"
)
tg (CPTG
uid 5946,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5947,0
va (VaSet
)
xt "197200,83400,200000,84600"
st "sine"
ju 2
blo "200000,84400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sine"
t "signed"
b "(outputBitNb-1 DOWNTO 0)"
o 1
)
)
)
*223 (CptPort
uid 5948,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5949,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,83625,185000,84375"
)
tg (CPTG
uid 5950,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5951,0
va (VaSet
)
xt "186000,83400,189700,84600"
st "phase"
blo "186000,84400"
)
)
thePort (LogicalPort
decl (Decl
n "phase"
t "unsigned"
b "(inputBitNb-1 DOWNTO 0)"
o 2
)
)
)
*224 (CptPort
uid 5952,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5953,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,85625,201750,86375"
)
tg (CPTG
uid 5954,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5955,0
va (VaSet
)
xt "196000,85400,200000,86600"
st "cosine"
ju 2
blo "200000,86400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cosine"
t "signed"
b "(outputBitNb-1 DOWNTO 0)"
o 3
)
)
)
]
shape (Rectangle
uid 5957,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "185000,80000,201000,90000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 5958,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*225 (Text
uid 5959,0
va (VaSet
)
xt "185600,89800,189900,91000"
st "Curves"
blo "185600,90800"
tm "BdLibraryNameMgr"
)
*226 (Text
uid 5960,0
va (VaSet
)
xt "185600,90800,193300,92000"
st "sinCosTable"
blo "185600,91800"
tm "CptNameMgr"
)
*227 (Text
uid 5961,0
va (VaSet
)
xt "185600,91800,188200,93000"
st "I25"
blo "185600,92800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5962,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5963,0
text (MLText
uid 5964,0
va (VaSet
font "Verdana,8,0"
)
xt "185000,93000,208700,96000"
st "inputBitNb        = phaseBitNb           ( positive ) 
outputBitNb       = signalBitNb          ( positive ) 
tableAddressBitNb = tableAddressBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "inputBitNb"
type "positive"
value "phaseBitNb"
)
(GiElement
name "outputBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "tableAddressBitNb"
type "positive"
value "tableAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*228 (HdlText
uid 6125,0
optionalChildren [
*229 (EmbeddedText
uid 6130,0
commentText (CommentText
uid 6131,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 6132,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "28000,151000,42000,165000"
)
oxt "0,0,18000,5000"
text (MLText
uid 6133,0
va (VaSet
)
xt "28200,151200,42200,164400"
st "
writeX: process(selX, memX)
begin
  if selX = '1' then
    dataOut <= std_logic_vector(memX);
  else
    dataOut <= (others => 'Z');
  end if;
end process writeX;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 14000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 6126,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "27000,150000,43000,166000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 6127,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*230 (Text
uid 6128,0
va (VaSet
)
xt "27400,166000,30000,167200"
st "eb6"
blo "27400,167000"
tm "HdlTextNameMgr"
)
*231 (Text
uid 6129,0
va (VaSet
)
xt "27400,167000,28800,168200"
st "6"
blo "27400,168000"
tm "HdlTextNumberMgr"
)
]
)
)
*232 (Net
uid 6503,0
decl (Decl
n "selSinCos"
t "std_ulogic"
o 13
suid 62,0
)
declText (MLText
uid 6504,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,13000,227300,14000"
st "selSinCos           : std_ulogic"
)
)
*233 (HdlText
uid 6825,0
optionalChildren [
*234 (EmbeddedText
uid 6830,0
commentText (CommentText
uid 6831,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 6832,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "28000,171000,42000,185000"
)
oxt "0,0,18000,5000"
text (MLText
uid 6833,0
va (VaSet
)
xt "28200,171200,42200,184400"
st "
writeCounters: process(addr, addrX, addrY)
begin
  if addr = 16#84# then
    dataOut <= std_logic_vector(addrX & addrY);
  else
    dataOut <= (others => 'Z');
  end if;
end process writeCounters;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 14000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 6826,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "27000,170000,43000,186000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 6827,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*235 (Text
uid 6828,0
va (VaSet
)
xt "27400,186000,30000,187200"
st "eb7"
blo "27400,187000"
tm "HdlTextNameMgr"
)
*236 (Text
uid 6829,0
va (VaSet
)
xt "27400,187000,28800,188200"
st "7"
blo "27400,188000"
tm "HdlTextNumberMgr"
)
]
)
)
*237 (SaComponent
uid 7019,0
optionalChildren [
*238 (CptPort
uid 6994,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6995,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,15625,27000,16375"
)
tg (CPTG
uid 6996,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6997,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,15300,31800,16700"
st "clock"
blo "28000,16500"
)
s (Text
uid 6998,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "28000,16700,28000,16700"
blo "9000,34900"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*239 (CptPort
uid 6999,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7000,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,9625,27000,10375"
)
tg (CPTG
uid 7001,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7002,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,9300,33000,10700"
st "dataIn"
blo "28000,10500"
)
s (Text
uid 7003,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "28000,10700,28000,10700"
blo "-37800,34100"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(registerNbBits-1 DOWNTO 0)"
o 1
)
)
)
*240 (CptPort
uid 7004,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7005,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,9625,43750,10375"
)
tg (CPTG
uid 7006,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7007,0
va (VaSet
font "Verdana,12,0"
)
xt "36000,9300,42000,10700"
st "dataOut"
ju 2
blo "42000,10500"
)
s (Text
uid 7008,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "42000,10700,42000,10700"
ju 2
blo "-23600,-18900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(registerNbBits-1 DOWNTO 0)"
o 3
)
)
)
*241 (CptPort
uid 7009,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7010,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,13625,27000,14375"
)
tg (CPTG
uid 7011,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7012,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,13300,33100,14700"
st "enable"
blo "28000,14500"
)
s (Text
uid 7013,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "28000,14700,28000,14700"
blo "9000,34900"
)
)
thePort (LogicalPort
decl (Decl
n "enable"
t "std_ulogic"
o 4
)
)
)
*242 (CptPort
uid 7014,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7015,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,17625,27000,18375"
)
tg (CPTG
uid 7016,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7017,0
va (VaSet
font "Verdana,12,0"
)
xt "28000,17300,32100,18700"
st "reset"
blo "28000,18500"
)
s (Text
uid 7018,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "28000,18700,28000,18700"
blo "9000,34900"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 7020,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27000,6000,43000,20000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 7021,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*243 (Text
uid 7022,0
va (VaSet
)
xt "26910,20700,33510,21900"
st "sequential"
blo "26910,21700"
tm "BdLibraryNameMgr"
)
*244 (Text
uid 7023,0
va (VaSet
)
xt "26910,21700,39810,22900"
st "registerULogicVector"
blo "26910,22700"
tm "CptNameMgr"
)
*245 (Text
uid 7024,0
va (VaSet
)
xt "26910,22700,29510,23900"
st "I26"
blo "26910,23700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7025,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7026,0
text (MLText
uid 7027,0
va (VaSet
)
xt "27000,23600,50300,26000"
st "delay          = 1 ns         ( time     ) 
registerNbBits = dataBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
(GiElement
name "registerNbBits"
type "positive"
value "dataBitNb"
)
]
)
portVis (PortSigDisplay
disp 1
sTC 0
sT 1
sIVOD 1
)
archFileType "UNKNOWN"
)
*246 (Net
uid 7053,0
decl (Decl
n "dataInReg"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 37
suid 63,0
)
declText (MLText
uid 7054,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,42700,244800,43700"
st "SIGNAL dataInReg           : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*247 (Net
uid 7073,0
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 6
suid 64,0
)
declText (MLText
uid 7074,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,6700,240900,7700"
st "dataIn              : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*248 (SaComponent
uid 7075,0
optionalChildren [
*249 (CptPort
uid 7084,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7085,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "6250,37625,7000,38375"
)
tg (CPTG
uid 7086,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7087,0
va (VaSet
font "Verdana,12,0"
)
xt "8000,37300,11800,38700"
st "clock"
blo "8000,38500"
)
s (Text
uid 7088,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "8000,38700,8000,38700"
blo "-11000,56900"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*250 (CptPort
uid 7089,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7090,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "6250,31625,7000,32375"
)
tg (CPTG
uid 7091,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7092,0
va (VaSet
font "Verdana,12,0"
)
xt "8000,31300,13000,32700"
st "dataIn"
blo "8000,32500"
)
s (Text
uid 7093,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "8000,32700,8000,32700"
blo "-57800,56100"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "unsigned"
b "(registerNbBits-1 DOWNTO 0)"
o 1
)
)
)
*251 (CptPort
uid 7094,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7095,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,31625,23750,32375"
)
tg (CPTG
uid 7096,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7097,0
va (VaSet
font "Verdana,12,0"
)
xt "16000,31300,22000,32700"
st "dataOut"
ju 2
blo "22000,32500"
)
s (Text
uid 7098,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "22000,32700,22000,32700"
ju 2
blo "-43600,3100"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "unsigned"
b "(registerNbBits-1 DOWNTO 0)"
o 3
)
)
)
*252 (CptPort
uid 7099,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7100,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "6250,35625,7000,36375"
)
tg (CPTG
uid 7101,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7102,0
va (VaSet
font "Verdana,12,0"
)
xt "8000,35300,13100,36700"
st "enable"
blo "8000,36500"
)
s (Text
uid 7103,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "8000,36700,8000,36700"
blo "-11000,56900"
)
)
thePort (LogicalPort
decl (Decl
n "enable"
t "std_ulogic"
o 4
)
)
)
*253 (CptPort
uid 7104,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7105,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "6250,39625,7000,40375"
)
tg (CPTG
uid 7106,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7107,0
va (VaSet
font "Verdana,12,0"
)
xt "8000,39300,12100,40700"
st "reset"
blo "8000,40500"
)
s (Text
uid 7108,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "8000,40700,8000,40700"
blo "-11000,56900"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 7076,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "7000,28000,23000,42000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 7077,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*254 (Text
uid 7078,0
va (VaSet
)
xt "6910,42700,13510,43900"
st "sequential"
blo "6910,43700"
tm "BdLibraryNameMgr"
)
*255 (Text
uid 7079,0
va (VaSet
)
xt "6910,43700,16910,44900"
st "registerUnsigned"
blo "6910,44700"
tm "CptNameMgr"
)
*256 (Text
uid 7080,0
va (VaSet
)
xt "6910,44700,9510,45900"
st "I27"
blo "6910,45700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7081,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7082,0
text (MLText
uid 7083,0
va (VaSet
)
xt "7000,45600,32100,48000"
st "delay          = 1 ns            ( time     ) 
registerNbBits = addressBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
(GiElement
name "registerNbBits"
type "positive"
value "addressBitNb"
)
]
)
portVis (PortSigDisplay
disp 1
sTC 0
sT 1
sIVOD 1
)
archFileType "UNKNOWN"
)
*257 (Net
uid 7115,0
decl (Decl
n "addrReg"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 23
suid 65,0
)
declText (MLText
uid 7116,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,30100,242500,31100"
st "SIGNAL addrReg             : unsigned(addressBitNb-1 DOWNTO 0)"
)
)
*258 (HdlText
uid 7149,0
optionalChildren [
*259 (EmbeddedText
uid 7154,0
commentText (CommentText
uid 7155,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 7156,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "12000,13000,18000,15000"
)
oxt "0,0,18000,5000"
text (MLText
uid 7157,0
va (VaSet
)
xt "12200,13200,17700,14400"
st "
logic1 <= '1';
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 6000
)
)
)
]
shape (Rectangle
uid 7150,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "11000,12000,19000,16000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 7151,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*260 (Text
uid 7152,0
va (VaSet
)
xt "11400,16000,14000,17200"
st "eb8"
blo "11400,17000"
tm "HdlTextNameMgr"
)
*261 (Text
uid 7153,0
va (VaSet
)
xt "11400,17000,12800,18200"
st "8"
blo "11400,18000"
tm "HdlTextNumberMgr"
)
]
)
)
*262 (Net
uid 7166,0
decl (Decl
n "logic1"
t "std_ulogic"
o 42
suid 66,0
)
declText (MLText
uid 7167,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,47200,229900,48200"
st "SIGNAL logic1              : std_ulogic"
)
)
*263 (SaComponent
uid 7695,0
optionalChildren [
*264 (CptPort
uid 7704,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7705,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,107625,43750,108375"
)
tg (CPTG
uid 7706,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7707,0
va (VaSet
)
xt "35400,107400,42000,108600"
st "writePulse"
ju 2
blo "42000,108400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "writePulse"
t "std_ulogic"
o 1
)
)
)
*265 (CptPort
uid 7708,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7709,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,107625,27000,108375"
)
tg (CPTG
uid 7710,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7711,0
va (VaSet
)
xt "28000,107400,31100,108600"
st "write"
blo "28000,108400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 2
)
)
)
*266 (CptPort
uid 7712,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7713,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,109625,27000,110375"
)
tg (CPTG
uid 7714,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7715,0
va (VaSet
)
xt "28000,109400,34700,110600"
st "chipSelect"
blo "28000,110400"
)
)
thePort (LogicalPort
decl (Decl
n "chipSelect"
t "std_ulogic"
o 3
)
)
)
*267 (CptPort
uid 7716,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7717,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,113625,27000,114375"
)
tg (CPTG
uid 7718,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7719,0
va (VaSet
)
xt "28000,113400,31400,114600"
st "clock"
blo "28000,114400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
)
)
)
*268 (CptPort
uid 7720,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7721,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,115625,27000,116375"
)
tg (CPTG
uid 7722,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7723,0
va (VaSet
)
xt "28000,115400,31300,116600"
st "reset"
blo "28000,116400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
]
shape (Rectangle
uid 7696,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "27000,104000,43000,118000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 7697,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*269 (Text
uid 7698,0
va (VaSet
)
xt "27600,117800,31900,119000"
st "Curves"
blo "27600,118800"
tm "BdLibraryNameMgr"
)
*270 (Text
uid 7699,0
va (VaSet
)
xt "27600,118800,37500,120000"
st "periphWritePulse"
blo "27600,119800"
tm "CptNameMgr"
)
*271 (Text
uid 7700,0
va (VaSet
)
xt "27600,119800,30200,121000"
st "I28"
blo "27600,120800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7701,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7702,0
text (MLText
uid 7703,0
va (VaSet
font "Verdana,8,0"
)
xt "-7000,95000,-7000,95000"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*272 (Net
uid 7756,0
decl (Decl
n "wr16Pulse"
t "std_ulogic"
o 84
suid 67,0
)
declText (MLText
uid 7757,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,85000,230800,86000"
st "SIGNAL wr16Pulse           : std_ulogic"
)
)
*273 (SaComponent
uid 7770,0
optionalChildren [
*274 (CptPort
uid 7758,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7759,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "10250,105625,11000,106375"
)
tg (CPTG
uid 7760,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7761,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "11000,105400,22600,106800"
st "in1 : std_uLogic"
blo "11000,106600"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*275 (CptPort
uid 7762,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7763,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "10250,109625,11000,110375"
)
tg (CPTG
uid 7764,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7765,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "11000,109400,22600,110800"
st "in2 : std_uLogic"
blo "11000,110600"
)
)
thePort (LogicalPort
decl (Decl
n "in2"
t "std_uLogic"
o 2
)
)
)
*276 (CptPort
uid 7766,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7767,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "17950,107625,18700,108375"
)
tg (CPTG
uid 7768,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7769,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "5400,107350,18000,108750"
st "out1 : std_uLogic"
ju 2
blo "18000,108550"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 3
)
)
)
]
shape (And
uid 7771,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "11000,105000,18000,111000"
)
showPorts 0
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 7772,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*277 (Text
uid 7773,0
va (VaSet
isHidden 1
)
xt "13600,105700,17100,106900"
st "gates"
blo "13600,106700"
tm "BdLibraryNameMgr"
)
*278 (Text
uid 7774,0
va (VaSet
isHidden 1
)
xt "13600,106700,16800,107900"
st "and2"
blo "13600,107700"
tm "CptNameMgr"
)
*279 (Text
uid 7775,0
va (VaSet
)
xt "13600,106700,16200,107900"
st "I29"
blo "13600,107700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7776,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7777,0
text (MLText
uid 7778,0
va (VaSet
isHidden 1
)
xt "11000,111400,24400,112600"
st "delay = 1 ns    ( time ) "
)
header ""
)
elements [
(GiElement
name "delay"
type "time"
value "1 ns"
)
]
)
portVis (PortSigDisplay
sN 0
sT 1
)
archFileType "UNKNOWN"
)
*280 (Net
uid 7799,0
decl (Decl
n "wr16"
t "std_ulogic"
o 83
suid 68,0
)
declText (MLText
uid 7800,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,84100,230200,85100"
st "SIGNAL wr16                : std_ulogic"
)
)
*281 (SaComponent
uid 8139,0
optionalChildren [
*282 (CptPort
uid 8103,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8104,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,11625,91750,12375"
)
tg (CPTG
uid 8105,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8106,0
va (VaSet
)
xt "87700,11400,90000,12600"
st "run"
ju 2
blo "90000,12400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "run"
t "std_ulogic"
o 1
)
)
)
*283 (CptPort
uid 8107,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8108,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,11625,75000,12375"
)
tg (CPTG
uid 8109,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8110,0
va (VaSet
)
xt "76000,11400,80000,12600"
st "dataIn"
blo "76000,12400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
)
)
)
*284 (CptPort
uid 8111,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8112,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,13625,91750,14375"
)
tg (CPTG
uid 8113,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8114,0
va (VaSet
)
xt "81500,13400,90000,14600"
st "updatePattern"
ju 2
blo "90000,14400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "updatePattern"
t "std_ulogic"
o 3
)
)
)
*285 (CptPort
uid 8115,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8116,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,13625,75000,14375"
)
tg (CPTG
uid 8117,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8118,0
va (VaSet
)
xt "76000,13400,80800,14600"
st "dataOut"
blo "76000,14400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
)
)
)
*286 (CptPort
uid 8119,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8120,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,17625,75000,18375"
)
tg (CPTG
uid 8121,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8122,0
va (VaSet
)
xt "76000,17400,79100,18600"
st "write"
blo "76000,18400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 5
)
)
)
*287 (CptPort
uid 8123,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8124,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,19625,75000,20375"
)
tg (CPTG
uid 8125,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8126,0
va (VaSet
)
xt "76000,19400,77900,20600"
st "en"
blo "76000,20400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 6
)
)
)
*288 (CptPort
uid 8127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,23625,75000,24375"
)
tg (CPTG
uid 8129,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8130,0
va (VaSet
)
xt "76000,23400,79400,24600"
st "clock"
blo "76000,24400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 7
)
)
)
*289 (CptPort
uid 8131,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8132,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,25625,75000,26375"
)
tg (CPTG
uid 8133,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8134,0
va (VaSet
)
xt "76000,25400,79300,26600"
st "reset"
blo "76000,26400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 8
)
)
)
*290 (CptPort
uid 8135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8136,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,15625,91750,16375"
)
tg (CPTG
uid 8137,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8138,0
va (VaSet
)
xt "80100,15400,90000,16600"
st "interpolateLinear"
ju 2
blo "90000,16400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 8140,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,8000,91000,28000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 8141,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 8142,0
va (VaSet
)
xt "75600,27800,79900,29000"
st "Curves"
blo "75600,28800"
tm "BdLibraryNameMgr"
)
*292 (Text
uid 8143,0
va (VaSet
)
xt "75600,28800,85700,30000"
st "periphControlReg"
blo "75600,29800"
tm "CptNameMgr"
)
*293 (Text
uid 8144,0
va (VaSet
)
xt "75600,29800,77500,31000"
st "I4"
blo "75600,30800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8145,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8146,0
text (MLText
uid 8147,0
va (VaSet
font "Verdana,8,0"
)
xt "75000,31600,91600,32600"
st "dataBitNb = dataBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*294 (Net
uid 8148,0
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 39
suid 69,0
)
declText (MLText
uid 8149,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,44500,231000,45500"
st "SIGNAL interpolateLinear   : std_ulogic"
)
)
*295 (SaComponent
uid 8192,0
optionalChildren [
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uid 8156,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8157,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,153625,185000,154375"
)
tg (CPTG
uid 8158,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8159,0
va (VaSet
)
xt "186000,153400,191000,154600"
st "sample1"
blo "186000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "sample1"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 1
)
)
)
*297 (CptPort
uid 8160,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8161,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,155625,185000,156375"
)
tg (CPTG
uid 8162,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8163,0
va (VaSet
)
xt "186000,155400,191000,156600"
st "sample2"
blo "186000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "sample2"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
)
)
)
*298 (CptPort
uid 8164,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8165,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,157625,185000,158375"
)
tg (CPTG
uid 8166,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8167,0
va (VaSet
)
xt "186000,157400,191000,158600"
st "sample3"
blo "186000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "sample3"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 3
)
)
)
*299 (CptPort
uid 8168,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8169,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,159625,185000,160375"
)
tg (CPTG
uid 8170,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8171,0
va (VaSet
)
xt "186000,159400,191000,160600"
st "sample4"
blo "186000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "sample4"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 4
)
)
)
*300 (CptPort
uid 8172,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8173,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,153625,201750,154375"
)
tg (CPTG
uid 8174,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8175,0
va (VaSet
)
xt "198700,153400,200000,154600"
st "a"
ju 2
blo "200000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 5
)
)
)
*301 (CptPort
uid 8176,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8177,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,155625,201750,156375"
)
tg (CPTG
uid 8178,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8179,0
va (VaSet
)
xt "198700,155400,200000,156600"
st "b"
ju 2
blo "200000,156400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
)
)
)
*302 (CptPort
uid 8180,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8181,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,159625,201750,160375"
)
tg (CPTG
uid 8182,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8183,0
va (VaSet
)
xt "198700,159400,200000,160600"
st "d"
ju 2
blo "200000,160400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
)
)
)
*303 (CptPort
uid 8184,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8185,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,157625,201750,158375"
)
tg (CPTG
uid 8186,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8187,0
va (VaSet
)
xt "198700,157400,200000,158600"
st "c"
ju 2
blo "200000,158400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
)
)
)
*304 (CptPort
uid 8188,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8189,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,161625,185000,162375"
)
tg (CPTG
uid 8190,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8191,0
va (VaSet
)
xt "186000,161400,195900,162600"
st "interpolateLinear"
blo "186000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 8193,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "185000,150000,201000,166000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 8194,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*305 (Text
uid 8195,0
va (VaSet
)
xt "185600,165800,189900,167000"
st "Curves"
blo "185600,166800"
tm "BdLibraryNameMgr"
)
*306 (Text
uid 8196,0
va (VaSet
)
xt "185600,166800,199500,168000"
st "interpolatorCoefficients"
blo "185600,167800"
tm "CptNameMgr"
)
*307 (Text
uid 8197,0
va (VaSet
)
xt "185600,167800,187500,169000"
st "I8"
blo "185600,168800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8198,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8199,0
text (MLText
uid 8200,0
va (VaSet
font "Verdana,8,0"
)
xt "185000,169800,202800,171800"
st "bitNb      = signalBitNb    ( positive ) 
coeffBitNb = coeffBitNb     ( positive ) "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*308 (SaComponent
uid 8237,0
optionalChildren [
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uid 8201,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8202,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,116625,185000,117375"
)
tg (CPTG
uid 8203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8204,0
va (VaSet
)
xt "186000,116400,191000,117600"
st "sample1"
blo "186000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "sample1"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 1
)
)
)
*310 (CptPort
uid 8205,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8206,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,118625,185000,119375"
)
tg (CPTG
uid 8207,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8208,0
va (VaSet
)
xt "186000,118400,191000,119600"
st "sample2"
blo "186000,119400"
)
)
thePort (LogicalPort
decl (Decl
n "sample2"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 2
)
)
)
*311 (CptPort
uid 8209,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8210,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,120625,185000,121375"
)
tg (CPTG
uid 8211,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8212,0
va (VaSet
)
xt "186000,120400,191000,121600"
st "sample3"
blo "186000,121400"
)
)
thePort (LogicalPort
decl (Decl
n "sample3"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 3
)
)
)
*312 (CptPort
uid 8213,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8214,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,122625,185000,123375"
)
tg (CPTG
uid 8215,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8216,0
va (VaSet
)
xt "186000,122400,191000,123600"
st "sample4"
blo "186000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "sample4"
t "signed"
b "(bitNb-1 DOWNTO 0)"
o 4
)
)
)
*313 (CptPort
uid 8217,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8218,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,116625,201750,117375"
)
tg (CPTG
uid 8219,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8220,0
va (VaSet
)
xt "198700,116400,200000,117600"
st "a"
ju 2
blo "200000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 5
)
)
)
*314 (CptPort
uid 8221,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8222,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,118625,201750,119375"
)
tg (CPTG
uid 8223,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8224,0
va (VaSet
)
xt "198700,118400,200000,119600"
st "b"
ju 2
blo "200000,119400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
)
)
)
*315 (CptPort
uid 8225,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8226,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,122625,201750,123375"
)
tg (CPTG
uid 8227,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8228,0
va (VaSet
)
xt "198700,122400,200000,123600"
st "d"
ju 2
blo "200000,123400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
)
)
)
*316 (CptPort
uid 8229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8230,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "201000,120625,201750,121375"
)
tg (CPTG
uid 8231,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8232,0
va (VaSet
)
xt "198700,120400,200000,121600"
st "c"
ju 2
blo "200000,121400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
)
)
)
*317 (CptPort
uid 8233,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8234,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "184250,124625,185000,125375"
)
tg (CPTG
uid 8235,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8236,0
va (VaSet
)
xt "186000,124400,195900,125600"
st "interpolateLinear"
blo "186000,125400"
)
)
thePort (LogicalPort
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 8238,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "185000,113000,201000,129000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 8239,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*318 (Text
uid 8240,0
va (VaSet
)
xt "185600,128800,189900,130000"
st "Curves"
blo "185600,129800"
tm "BdLibraryNameMgr"
)
*319 (Text
uid 8241,0
va (VaSet
)
xt "185600,129800,199500,131000"
st "interpolatorCoefficients"
blo "185600,130800"
tm "CptNameMgr"
)
*320 (Text
uid 8242,0
va (VaSet
)
xt "185600,130800,188200,132000"
st "I12"
blo "185600,131800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8243,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8244,0
text (MLText
uid 8245,0
va (VaSet
font "Verdana,8,0"
)
xt "185000,132800,202800,134800"
st "bitNb      = signalBitNb    ( positive ) 
coeffBitNb = coeffBitNb     ( positive ) "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*321 (SaComponent
uid 8656,0
optionalChildren [
*322 (CptPort
uid 8628,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8629,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,116625,107000,117375"
)
tg (CPTG
uid 8630,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8631,0
va (VaSet
)
xt "108000,116400,112000,117600"
st "dataIn"
blo "108000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 1
)
)
)
*323 (CptPort
uid 8632,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8633,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "123000,116625,123750,117375"
)
tg (CPTG
uid 8634,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8635,0
va (VaSet
)
xt "117200,116400,122000,117600"
st "dataOut"
ju 2
blo "122000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
)
)
)
*324 (CptPort
uid 8636,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8637,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,124625,107000,125375"
)
tg (CPTG
uid 8638,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8639,0
va (VaSet
)
xt "108000,124400,109900,125600"
st "en"
blo "108000,125400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
)
)
)
*325 (CptPort
uid 8640,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8641,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,128625,107000,129375"
)
tg (CPTG
uid 8642,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8643,0
va (VaSet
)
xt "108000,128400,111400,129600"
st "clock"
blo "108000,129400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
)
)
)
*326 (CptPort
uid 8644,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8645,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,130625,107000,131375"
)
tg (CPTG
uid 8646,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8647,0
va (VaSet
)
xt "108000,130400,111300,131600"
st "reset"
blo "108000,131400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
*327 (CptPort
uid 8648,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8649,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,122625,107000,123375"
)
tg (CPTG
uid 8650,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8651,0
va (VaSet
)
xt "108000,122400,111100,123600"
st "write"
blo "108000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 6
)
)
)
*328 (CptPort
uid 8652,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8653,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,118625,107000,119375"
)
tg (CPTG
uid 8654,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8655,0
va (VaSet
)
xt "108000,118400,110900,119600"
st "addr"
blo "108000,119400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
)
)
)
]
shape (Rectangle
uid 8657,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "107000,113000,123000,133000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 8658,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*329 (Text
uid 8659,0
va (VaSet
)
xt "107600,132800,111900,134000"
st "Curves"
blo "107600,133800"
tm "BdLibraryNameMgr"
)
*330 (Text
uid 8660,0
va (VaSet
)
xt "107600,133800,113400,135000"
st "blockRAM"
blo "107600,134800"
tm "CptNameMgr"
)
*331 (Text
uid 8661,0
va (VaSet
)
xt "107600,134800,110200,136000"
st "I21"
blo "107600,135800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8662,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8663,0
text (MLText
uid 8664,0
va (VaSet
font "Verdana,8,0"
)
xt "107000,136600,129600,138600"
st "addressBitNb = patternAddressBitNb    ( positive ) 
dataBitNb    = dataBitNb              ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*332 (SaComponent
uid 8693,0
optionalChildren [
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uid 8665,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8666,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,153625,107000,154375"
)
tg (CPTG
uid 8667,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8668,0
va (VaSet
)
xt "108000,153400,112000,154600"
st "dataIn"
blo "108000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 1
)
)
)
*334 (CptPort
uid 8669,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8670,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "123000,153625,123750,154375"
)
tg (CPTG
uid 8671,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8672,0
va (VaSet
)
xt "117200,153400,122000,154600"
st "dataOut"
ju 2
blo "122000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
)
)
)
*335 (CptPort
uid 8673,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8674,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,161625,107000,162375"
)
tg (CPTG
uid 8675,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8676,0
va (VaSet
)
xt "108000,161400,109900,162600"
st "en"
blo "108000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
)
)
)
*336 (CptPort
uid 8677,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8678,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,165625,107000,166375"
)
tg (CPTG
uid 8679,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8680,0
va (VaSet
)
xt "108000,165400,111400,166600"
st "clock"
blo "108000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
)
)
)
*337 (CptPort
uid 8681,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8682,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,167625,107000,168375"
)
tg (CPTG
uid 8683,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8684,0
va (VaSet
)
xt "108000,167400,111300,168600"
st "reset"
blo "108000,168400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
*338 (CptPort
uid 8685,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8686,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,159625,107000,160375"
)
tg (CPTG
uid 8687,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8688,0
va (VaSet
)
xt "108000,159400,111100,160600"
st "write"
blo "108000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 6
)
)
)
*339 (CptPort
uid 8689,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8690,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,155625,107000,156375"
)
tg (CPTG
uid 8691,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8692,0
va (VaSet
)
xt "108000,155400,110900,156600"
st "addr"
blo "108000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
)
)
)
]
shape (Rectangle
uid 8694,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "107000,150000,123000,170000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 8695,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*340 (Text
uid 8696,0
va (VaSet
)
xt "107600,169800,111900,171000"
st "Curves"
blo "107600,170800"
tm "BdLibraryNameMgr"
)
*341 (Text
uid 8697,0
va (VaSet
)
xt "107600,170800,113400,172000"
st "blockRAM"
blo "107600,171800"
tm "CptNameMgr"
)
*342 (Text
uid 8698,0
va (VaSet
)
xt "107600,171800,110200,173000"
st "I16"
blo "107600,172800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8699,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8700,0
text (MLText
uid 8701,0
va (VaSet
font "Verdana,8,0"
)
xt "107000,173600,129600,175600"
st "addressBitNb = patternAddressBitNb    ( positive ) 
dataBitNb    = dataBitNb              ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*343 (SaComponent
uid 9102,0
optionalChildren [
*344 (CptPort
uid 9070,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9071,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,122625,161000,123375"
)
tg (CPTG
uid 9072,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9073,0
va (VaSet
)
xt "162000,122400,165400,123600"
st "clock"
blo "162000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
)
)
)
*345 (CptPort
uid 9074,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9075,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,124625,161000,125375"
)
tg (CPTG
uid 9076,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9077,0
va (VaSet
)
xt "162000,124400,165300,125600"
st "reset"
blo "162000,125400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
)
)
)
*346 (CptPort
uid 9078,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9079,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,118625,161000,119375"
)
tg (CPTG
uid 9080,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9081,0
va (VaSet
)
xt "162000,118400,169900,119600"
st "shiftSamples"
blo "162000,119400"
)
)
thePort (LogicalPort
decl (Decl
n "shiftSamples"
t "std_ulogic"
o 3
)
)
)
*347 (CptPort
uid 9082,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9083,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,116625,161000,117375"
)
tg (CPTG
uid 9084,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9085,0
va (VaSet
)
xt "162000,116400,167400,117600"
st "sampleIn"
blo "162000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "sampleIn"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 4
)
)
)
*348 (CptPort
uid 9086,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9087,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,116625,177750,117375"
)
tg (CPTG
uid 9088,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9089,0
va (VaSet
)
xt "171000,116400,176000,117600"
st "sample1"
ju 2
blo "176000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
)
)
)
*349 (CptPort
uid 9090,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9091,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,118625,177750,119375"
)
tg (CPTG
uid 9092,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9093,0
va (VaSet
)
xt "171000,118400,176000,119600"
st "sample2"
ju 2
blo "176000,119400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 6
)
)
)
*350 (CptPort
uid 9094,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9095,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,120625,177750,121375"
)
tg (CPTG
uid 9096,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9097,0
va (VaSet
)
xt "171000,120400,176000,121600"
st "sample3"
ju 2
blo "176000,121400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 7
)
)
)
*351 (CptPort
uid 9098,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9099,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,122625,177750,123375"
)
tg (CPTG
uid 9100,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9101,0
va (VaSet
)
xt "171000,122400,176000,123600"
st "sample4"
ju 2
blo "176000,123400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 8
)
)
)
]
shape (Rectangle
uid 9103,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,113000,177000,127000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 9104,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*352 (Text
uid 9105,0
va (VaSet
)
xt "161600,126800,165900,128000"
st "Curves"
blo "161600,127800"
tm "BdLibraryNameMgr"
)
*353 (Text
uid 9106,0
va (VaSet
)
xt "161600,127800,176000,129000"
st "interpolatorShiftRegister"
blo "161600,128800"
tm "CptNameMgr"
)
*354 (Text
uid 9107,0
va (VaSet
)
xt "161600,128800,164200,130000"
st "I11"
blo "161600,129800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9108,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9109,0
text (MLText
uid 9110,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,130600,179100,131600"
st "signalBitNb = signalBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*355 (SaComponent
uid 9143,0
optionalChildren [
*356 (CptPort
uid 9111,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9112,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,159625,161000,160375"
)
tg (CPTG
uid 9113,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9114,0
va (VaSet
)
xt "162000,159400,165400,160600"
st "clock"
blo "162000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
)
)
)
*357 (CptPort
uid 9115,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9116,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,161625,161000,162375"
)
tg (CPTG
uid 9117,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9118,0
va (VaSet
)
xt "162000,161400,165300,162600"
st "reset"
blo "162000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
)
)
)
*358 (CptPort
uid 9119,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9120,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,155625,161000,156375"
)
tg (CPTG
uid 9121,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9122,0
va (VaSet
)
xt "162000,155400,169900,156600"
st "shiftSamples"
blo "162000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "shiftSamples"
t "std_ulogic"
o 3
)
)
)
*359 (CptPort
uid 9123,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9124,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,153625,161000,154375"
)
tg (CPTG
uid 9125,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9126,0
va (VaSet
)
xt "162000,153400,167400,154600"
st "sampleIn"
blo "162000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "sampleIn"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 4
)
)
)
*360 (CptPort
uid 9127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,153625,177750,154375"
)
tg (CPTG
uid 9129,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9130,0
va (VaSet
)
xt "171000,153400,176000,154600"
st "sample1"
ju 2
blo "176000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
)
)
)
*361 (CptPort
uid 9131,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9132,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,155625,177750,156375"
)
tg (CPTG
uid 9133,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9134,0
va (VaSet
)
xt "171000,155400,176000,156600"
st "sample2"
ju 2
blo "176000,156400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 6
)
)
)
*362 (CptPort
uid 9135,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9136,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,157625,177750,158375"
)
tg (CPTG
uid 9137,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9138,0
va (VaSet
)
xt "171000,157400,176000,158600"
st "sample3"
ju 2
blo "176000,158400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 7
)
)
)
*363 (CptPort
uid 9139,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9140,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,159625,177750,160375"
)
tg (CPTG
uid 9141,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9142,0
va (VaSet
)
xt "171000,159400,176000,160600"
st "sample4"
ju 2
blo "176000,160400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 8
)
)
)
]
shape (Rectangle
uid 9144,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,150000,177000,164000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 9145,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*364 (Text
uid 9146,0
va (VaSet
)
xt "161600,163800,165900,165000"
st "Curves"
blo "161600,164800"
tm "BdLibraryNameMgr"
)
*365 (Text
uid 9147,0
va (VaSet
)
xt "161600,164800,176000,166000"
st "interpolatorShiftRegister"
blo "161600,165800"
tm "CptNameMgr"
)
*366 (Text
uid 9148,0
va (VaSet
)
xt "161600,165800,163500,167000"
st "I7"
blo "161600,166800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9149,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9150,0
text (MLText
uid 9151,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,167600,179100,168600"
st "signalBitNb = signalBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*367 (SaComponent
uid 9190,0
optionalChildren [
*368 (CptPort
uid 9154,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9155,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,130625,217000,131375"
)
tg (CPTG
uid 9156,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9157,0
va (VaSet
)
xt "218000,130400,221400,131600"
st "clock"
blo "218000,131400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
)
)
)
*369 (CptPort
uid 9158,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9159,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,132625,217000,133375"
)
tg (CPTG
uid 9160,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9161,0
va (VaSet
)
xt "218000,132400,221300,133600"
st "reset"
blo "218000,133400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
)
)
)
*370 (CptPort
uid 9162,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9163,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,124625,217000,125375"
)
tg (CPTG
uid 9164,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9165,0
va (VaSet
)
xt "218000,124400,227100,125600"
st "restartPolynom"
blo "218000,125400"
)
)
thePort (LogicalPort
decl (Decl
n "restartPolynom"
t "std_ulogic"
o 3
)
)
)
*371 (CptPort
uid 9166,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9167,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,122625,217000,123375"
)
tg (CPTG
uid 9168,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9169,0
va (VaSet
)
xt "218000,122400,219300,123600"
st "d"
blo "218000,123400"
)
)
thePort (LogicalPort
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 4
)
)
)
*372 (CptPort
uid 9170,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9171,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "233000,116625,233750,117375"
)
tg (CPTG
uid 9172,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9173,0
va (VaSet
)
xt "225800,116400,232000,117600"
st "sampleOut"
ju 2
blo "232000,117400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sampleOut"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
)
)
)
*373 (CptPort
uid 9174,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9175,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,120625,217000,121375"
)
tg (CPTG
uid 9176,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9177,0
va (VaSet
)
xt "218000,120400,219300,121600"
st "c"
blo "218000,121400"
)
)
thePort (LogicalPort
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
)
)
)
*374 (CptPort
uid 9178,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9179,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,118625,217000,119375"
)
tg (CPTG
uid 9180,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9181,0
va (VaSet
)
xt "218000,118400,219300,119600"
st "b"
blo "218000,119400"
)
)
thePort (LogicalPort
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
)
)
)
*375 (CptPort
uid 9182,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9183,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,116625,217000,117375"
)
tg (CPTG
uid 9184,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9185,0
va (VaSet
)
xt "218000,116400,219300,117600"
st "a"
blo "218000,117400"
)
)
thePort (LogicalPort
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
)
)
)
*376 (CptPort
uid 9186,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9187,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,128625,217000,129375"
)
tg (CPTG
uid 9188,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9189,0
va (VaSet
)
xt "218000,128400,219900,129600"
st "en"
blo "218000,129400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 9191,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "217000,113000,233000,136000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 9192,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*377 (Text
uid 9193,0
va (VaSet
)
xt "217600,135800,221900,137000"
st "Curves"
blo "217600,136800"
tm "BdLibraryNameMgr"
)
*378 (Text
uid 9194,0
va (VaSet
)
xt "217600,136800,234600,138000"
st "interpolatorCalculatePolynom"
blo "217600,137800"
tm "CptNameMgr"
)
*379 (Text
uid 9195,0
va (VaSet
)
xt "217600,137800,220200,139000"
st "I13"
blo "217600,138800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9196,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9197,0
text (MLText
uid 9198,0
va (VaSet
font "Verdana,8,0"
)
xt "217000,139000,241200,142000"
st "signalBitNb       = signalBitNb         ( positive ) 
coeffBitNb        = coeffBitNb          ( positive ) 
oversamplingBitNb = sampleCountBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
(GiElement
name "oversamplingBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*380 (SaComponent
uid 9235,0
optionalChildren [
*381 (CptPort
uid 9199,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9200,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,167625,217000,168375"
)
tg (CPTG
uid 9201,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9202,0
va (VaSet
)
xt "218000,167400,221400,168600"
st "clock"
blo "218000,168400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
)
)
)
*382 (CptPort
uid 9203,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9204,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,169625,217000,170375"
)
tg (CPTG
uid 9205,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9206,0
va (VaSet
)
xt "218000,169400,221300,170600"
st "reset"
blo "218000,170400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
)
)
)
*383 (CptPort
uid 9207,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9208,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,161625,217000,162375"
)
tg (CPTG
uid 9209,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9210,0
va (VaSet
)
xt "218000,161400,227100,162600"
st "restartPolynom"
blo "218000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "restartPolynom"
t "std_ulogic"
o 3
)
)
)
*384 (CptPort
uid 9211,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9212,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,159625,217000,160375"
)
tg (CPTG
uid 9213,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9214,0
va (VaSet
)
xt "218000,159400,219300,160600"
st "d"
blo "218000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "d"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 4
)
)
)
*385 (CptPort
uid 9215,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9216,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "233000,153625,233750,154375"
)
tg (CPTG
uid 9217,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 9218,0
va (VaSet
)
xt "225800,153400,232000,154600"
st "sampleOut"
ju 2
blo "232000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sampleOut"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
)
)
)
*386 (CptPort
uid 9219,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9220,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,157625,217000,158375"
)
tg (CPTG
uid 9221,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9222,0
va (VaSet
)
xt "218000,157400,219300,158600"
st "c"
blo "218000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "c"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 6
)
)
)
*387 (CptPort
uid 9223,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9224,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,155625,217000,156375"
)
tg (CPTG
uid 9225,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9226,0
va (VaSet
)
xt "218000,155400,219300,156600"
st "b"
blo "218000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "b"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 7
)
)
)
*388 (CptPort
uid 9227,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9228,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,153625,217000,154375"
)
tg (CPTG
uid 9229,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9230,0
va (VaSet
)
xt "218000,153400,219300,154600"
st "a"
blo "218000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "a"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 8
)
)
)
*389 (CptPort
uid 9231,0
ps "OnEdgeStrategy"
shape (Triangle
uid 9232,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "216250,165625,217000,166375"
)
tg (CPTG
uid 9233,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 9234,0
va (VaSet
)
xt "218000,165400,219900,166600"
st "en"
blo "218000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 9236,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "217000,150000,233000,173000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 9237,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*390 (Text
uid 9238,0
va (VaSet
)
xt "217600,172800,221900,174000"
st "Curves"
blo "217600,173800"
tm "BdLibraryNameMgr"
)
*391 (Text
uid 9239,0
va (VaSet
)
xt "217600,173800,234600,175000"
st "interpolatorCalculatePolynom"
blo "217600,174800"
tm "CptNameMgr"
)
*392 (Text
uid 9240,0
va (VaSet
)
xt "217600,174800,219500,176000"
st "I9"
blo "217600,175800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 9241,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 9242,0
text (MLText
uid 9243,0
va (VaSet
font "Verdana,8,0"
)
xt "217000,176000,241200,179000"
st "signalBitNb       = signalBitNb         ( positive ) 
coeffBitNb        = coeffBitNb          ( positive ) 
oversamplingBitNb = sampleCountBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "coeffBitNb"
type "positive"
value "coeffBitNb"
)
(GiElement
name "oversamplingBitNb"
type "positive"
value "sampleCountBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*393 (Net
uid 9646,0
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 38
suid 70,0
)
declText (MLText
uid 9647,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,43600,230600,44600"
st "SIGNAL interpolateLin      : std_ulogic"
)
)
*394 (SaComponent
uid 10416,0
optionalChildren [
*395 (CptPort
uid 10425,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10426,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,209625,75000,210375"
)
tg (CPTG
uid 10427,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10428,0
va (VaSet
)
xt "76000,209400,77900,210600"
st "en"
blo "76000,210400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 1
)
)
)
*396 (CptPort
uid 10429,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10430,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,213625,75000,214375"
)
tg (CPTG
uid 10431,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10432,0
va (VaSet
)
xt "76000,213400,79400,214600"
st "clock"
blo "76000,214400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*397 (CptPort
uid 10433,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10434,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,215625,75000,216375"
)
tg (CPTG
uid 10435,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10436,0
va (VaSet
)
xt "76000,215400,79300,216600"
st "reset"
blo "76000,216400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*398 (CptPort
uid 10437,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10438,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,207625,75000,208375"
)
tg (CPTG
uid 10439,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10440,0
va (VaSet
)
xt "76000,207400,82500,208600"
st "updateMem"
blo "76000,208400"
)
)
thePort (LogicalPort
decl (Decl
n "updateMem"
t "std_ulogic"
o 4
)
)
)
*399 (CptPort
uid 10441,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10442,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,205625,91750,206375"
)
tg (CPTG
uid 10443,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10444,0
va (VaSet
)
xt "87100,205400,90000,206600"
st "addr"
ju 2
blo "90000,206400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 5
)
)
)
*400 (CptPort
uid 10445,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10446,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,205625,75000,206375"
)
tg (CPTG
uid 10447,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10448,0
va (VaSet
)
xt "76000,205400,83100,206600"
st "patternSize"
blo "76000,206400"
)
)
thePort (LogicalPort
decl (Decl
n "patternSize"
t "unsigned"
b "(patternSizeBitNb-1 DOWNTO 0)"
o 6
)
)
)
]
shape (Rectangle
uid 10417,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,202000,91000,218000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 10418,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*401 (Text
uid 10419,0
va (VaSet
)
xt "75600,217800,79900,219000"
st "Curves"
blo "75600,218800"
tm "BdLibraryNameMgr"
)
*402 (Text
uid 10420,0
va (VaSet
)
xt "75600,218800,91000,220000"
st "blockRAMAddressCounter"
blo "75600,219800"
tm "CptNameMgr"
)
*403 (Text
uid 10421,0
va (VaSet
)
xt "75600,219800,78200,221000"
st "I30"
blo "75600,220800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 10422,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 10423,0
text (MLText
uid 10424,0
va (VaSet
font "Verdana,8,0"
)
xt "75000,221600,98800,223600"
st "addressBitNb     = patternAddressBitNb    ( positive ) 
patternSizeBitNb = dataBitNb/2            ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "patternSizeBitNb"
type "positive"
value "dataBitNb/2"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*404 (SaComponent
uid 10494,0
optionalChildren [
*405 (CptPort
uid 10503,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10504,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,203625,107000,204375"
)
tg (CPTG
uid 10505,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10506,0
va (VaSet
)
xt "108000,203400,112000,204600"
st "dataIn"
blo "108000,204400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 1
)
)
)
*406 (CptPort
uid 10507,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10508,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "123000,203625,123750,204375"
)
tg (CPTG
uid 10509,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10510,0
va (VaSet
)
xt "117200,203400,122000,204600"
st "dataOut"
ju 2
blo "122000,204400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
)
)
)
*407 (CptPort
uid 10511,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10512,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,211625,107000,212375"
)
tg (CPTG
uid 10513,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10514,0
va (VaSet
)
xt "108000,211400,109900,212600"
st "en"
blo "108000,212400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
)
)
)
*408 (CptPort
uid 10515,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10516,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,215625,107000,216375"
)
tg (CPTG
uid 10517,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10518,0
va (VaSet
)
xt "108000,215400,111400,216600"
st "clock"
blo "108000,216400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
)
)
)
*409 (CptPort
uid 10519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,217625,107000,218375"
)
tg (CPTG
uid 10521,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10522,0
va (VaSet
)
xt "108000,217400,111300,218600"
st "reset"
blo "108000,218400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
)
)
)
*410 (CptPort
uid 10523,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10524,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,209625,107000,210375"
)
tg (CPTG
uid 10525,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10526,0
va (VaSet
)
xt "108000,209400,111100,210600"
st "write"
blo "108000,210400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 6
)
)
)
*411 (CptPort
uid 10527,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10528,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "106250,205625,107000,206375"
)
tg (CPTG
uid 10529,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10530,0
va (VaSet
)
xt "108000,205400,110900,206600"
st "addr"
blo "108000,206400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
)
)
)
]
shape (Rectangle
uid 10495,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "107000,200000,123000,220000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 10496,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*412 (Text
uid 10497,0
va (VaSet
)
xt "107600,219800,111900,221000"
st "Curves"
blo "107600,220800"
tm "BdLibraryNameMgr"
)
*413 (Text
uid 10498,0
va (VaSet
)
xt "107600,220800,113400,222000"
st "blockRAM"
blo "107600,221800"
tm "CptNameMgr"
)
*414 (Text
uid 10499,0
va (VaSet
)
xt "107600,221800,110200,223000"
st "I32"
blo "107600,222800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 10500,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 10501,0
text (MLText
uid 10502,0
va (VaSet
font "Verdana,8,0"
)
xt "107000,223600,129600,225600"
st "addressBitNb = patternAddressBitNb    ( positive ) 
dataBitNb    = dataBitNb              ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*415 (Net
uid 10607,0
decl (Decl
n "cntIncrZ"
t "std_ulogic"
o 33
suid 71,0
)
declText (MLText
uid 10608,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,39100,230200,40100"
st "SIGNAL cntIncrZ            : std_ulogic"
)
)
*416 (Net
uid 10609,0
decl (Decl
n "addrZ"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 26
suid 72,0
)
declText (MLText
uid 10610,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,32800,244900,33800"
st "SIGNAL addrZ               : unsigned(patternAddressBitNb-1 DOWNTO 0)"
)
)
*417 (Net
uid 10611,0
decl (Decl
n "memZ"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 51
suid 73,0
)
declText (MLText
uid 10612,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,55300,244700,56300"
st "SIGNAL memZ                : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*418 (Net
uid 10613,0
decl (Decl
n "memWrZ"
t "std_ulogic"
o 48
suid 74,0
)
declText (MLText
uid 10614,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,52600,231300,53600"
st "SIGNAL memWrZ              : std_ulogic"
)
)
*419 (Net
uid 10615,0
decl (Decl
n "memEnZ"
t "std_ulogic"
o 45
suid 75,0
)
declText (MLText
uid 10616,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,49900,231200,50900"
st "SIGNAL memEnZ              : std_ulogic"
)
)
*420 (SaComponent
uid 10651,0
optionalChildren [
*421 (CptPort
uid 10623,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10624,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,31625,43750,32375"
)
tg (CPTG
uid 10625,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10626,0
va (VaSet
)
xt "35400,31400,42000,32600"
st "selControl"
ju 2
blo "42000,32400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selControl"
t "std_ulogic"
o 1
)
)
)
*422 (CptPort
uid 10627,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10628,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "26250,31625,27000,32375"
)
tg (CPTG
uid 10629,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 10630,0
va (VaSet
)
xt "28000,31400,30900,32600"
st "addr"
blo "28000,32400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 2
)
)
)
*423 (CptPort
uid 10631,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10632,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,33625,43750,34375"
)
tg (CPTG
uid 10633,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10634,0
va (VaSet
)
xt "37700,33400,42000,34600"
st "selSize"
ju 2
blo "42000,34400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selSize"
t "std_ulogic"
o 3
)
)
)
*424 (CptPort
uid 10635,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10636,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,35625,43750,36375"
)
tg (CPTG
uid 10637,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10638,0
va (VaSet
)
xt "36700,35400,42000,36600"
st "selSpeed"
ju 2
blo "42000,36400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selSpeed"
t "std_ulogic"
o 4
)
)
)
*425 (CptPort
uid 10639,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10640,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,37625,43750,38375"
)
tg (CPTG
uid 10641,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10642,0
va (VaSet
)
xt "39100,37400,42000,38600"
st "selX"
ju 2
blo "42000,38400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selX"
t "std_ulogic"
o 5
)
)
)
*426 (CptPort
uid 10643,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10644,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,39625,43750,40375"
)
tg (CPTG
uid 10645,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10646,0
va (VaSet
)
xt "39100,39400,42000,40600"
st "selY"
ju 2
blo "42000,40400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selY"
t "std_ulogic"
o 6
)
)
)
*427 (CptPort
uid 10647,0
ps "OnEdgeStrategy"
shape (Triangle
uid 10648,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "43000,41625,43750,42375"
)
tg (CPTG
uid 10649,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 10650,0
va (VaSet
)
xt "39100,41400,42000,42600"
st "selZ"
ju 2
blo "42000,42400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selZ"
t "std_ulogic"
o 7
)
)
)
]
shape (Rectangle
uid 10652,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "27000,28000,43000,46000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 10653,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*428 (Text
uid 10654,0
va (VaSet
)
xt "27600,45800,31900,47000"
st "Curves"
blo "27600,46800"
tm "BdLibraryNameMgr"
)
*429 (Text
uid 10655,0
va (VaSet
)
xt "27600,46800,41200,48000"
st "periphAddressDecoder"
blo "27600,47800"
tm "CptNameMgr"
)
*430 (Text
uid 10656,0
va (VaSet
)
xt "27600,47800,29500,49000"
st "I2"
blo "27600,48800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 10657,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 10658,0
text (MLText
uid 10659,0
va (VaSet
font "Verdana,8,0"
)
xt "27000,49600,46700,50600"
st "addressBitNb = addressBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*431 (Net
uid 10660,0
decl (Decl
n "selZ"
t "std_ulogic"
o 76
suid 76,0
)
declText (MLText
uid 10661,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,77800,229800,78800"
st "SIGNAL selZ                : std_ulogic"
)
)
*432 (PortIoOut
uid 10878,0
shape (CompositeShape
uid 10879,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 10880,0
sl 0
ro 270
xt "209500,205625,211000,206375"
)
(Line
uid 10881,0
sl 0
ro 270
xt "209000,206000,209500,206000"
pts [
"209000,206000"
"209500,206000"
]
)
]
)
tg (WTG
uid 10882,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10883,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "212000,205300,215700,206700"
st "outZ"
blo "212000,206500"
tm "WireNameMgr"
)
)
)
*433 (Net
uid 10890,0
decl (Decl
n "outZ"
t "std_ulogic"
o 14
suid 77,0
)
declText (MLText
uid 10891,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,13900,226800,14900"
st "outZ                : std_ulogic"
)
)
*434 (HdlText
uid 10892,0
optionalChildren [
*435 (EmbeddedText
uid 10897,0
commentText (CommentText
uid 10898,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 10899,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "186000,204000,200300,208000"
)
oxt "0,0,18000,5000"
text (MLText
uid 10900,0
va (VaSet
)
xt "186200,204200,198500,207800"
st "
outZ <= '0' when ( (to_01(unsigned(sampleZ1)) = 0) or (to_01(unsigned(sampleZ2)) = 0) ) else '1';
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 14300
)
)
)
]
shape (Rectangle
uid 10893,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "185000,202000,201000,210000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 10894,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*436 (Text
uid 10895,0
va (VaSet
)
xt "185400,210000,188000,211200"
st "eb9"
blo "185400,211000"
tm "HdlTextNameMgr"
)
*437 (Text
uid 10896,0
va (VaSet
)
xt "185400,211000,186800,212200"
st "9"
blo "185400,212000"
tm "HdlTextNumberMgr"
)
]
)
)
*438 (SaComponent
uid 11389,0
optionalChildren [
*439 (CptPort
uid 11353,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11354,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,133625,91750,134375"
)
tg (CPTG
uid 11355,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11356,0
va (VaSet
)
xt "85600,133400,90000,134600"
st "memWr"
ju 2
blo "90000,134400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr"
t "std_ulogic"
o 1
)
)
)
*440 (CptPort
uid 11357,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11358,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,129625,75000,130375"
)
tg (CPTG
uid 11359,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11360,0
va (VaSet
)
xt "76000,129400,78200,130600"
st "sel"
blo "76000,130400"
)
)
thePort (LogicalPort
decl (Decl
n "sel"
t "std_ulogic"
o 2
)
)
)
*441 (CptPort
uid 11361,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11362,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,135625,91750,136375"
)
tg (CPTG
uid 11363,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11364,0
va (VaSet
)
xt "85600,135400,90000,136600"
st "memEn"
ju 2
blo "90000,136400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memEn"
t "std_ulogic"
o 3
)
)
)
*442 (CptPort
uid 11365,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11366,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,133625,75000,134375"
)
tg (CPTG
uid 11367,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11368,0
va (VaSet
)
xt "76000,133400,80100,134600"
st "update"
blo "76000,134400"
)
)
thePort (LogicalPort
decl (Decl
n "update"
t "std_ulogic"
o 4
)
)
)
*443 (CptPort
uid 11369,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11370,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,131625,75000,132375"
)
tg (CPTG
uid 11371,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11372,0
va (VaSet
)
xt "76000,131400,77800,132600"
st "wr"
blo "76000,132400"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_ulogic"
o 5
)
)
)
*444 (CptPort
uid 11373,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11374,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,129625,91750,130375"
)
tg (CPTG
uid 11375,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11376,0
va (VaSet
)
xt "85600,129400,90000,130600"
st "cntIncr"
ju 2
blo "90000,130400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cntIncr"
t "std_ulogic"
o 6
)
)
)
*445 (CptPort
uid 11377,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11378,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,135625,75000,136375"
)
tg (CPTG
uid 11379,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11380,0
va (VaSet
)
xt "76000,135400,82300,136600"
st "newSample"
blo "76000,136400"
)
)
thePort (LogicalPort
decl (Decl
n "newSample"
t "std_ulogic"
o 7
)
)
)
*446 (CptPort
uid 11381,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11382,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,139625,75000,140375"
)
tg (CPTG
uid 11383,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11384,0
va (VaSet
)
xt "76000,139400,79400,140600"
st "clock"
blo "76000,140400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 8
)
)
)
*447 (CptPort
uid 11385,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11386,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,141625,75000,142375"
)
tg (CPTG
uid 11387,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11388,0
va (VaSet
)
xt "76000,141400,79300,142600"
st "reset"
blo "76000,142400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 11390,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,126000,91000,144000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11391,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*448 (Text
uid 11392,0
va (VaSet
)
xt "75600,143800,79900,145000"
st "Curves"
blo "75600,144800"
tm "BdLibraryNameMgr"
)
*449 (Text
uid 11393,0
va (VaSet
)
xt "75600,144800,85800,146000"
st "blockRAMControl"
blo "75600,145800"
tm "CptNameMgr"
)
*450 (Text
uid 11394,0
va (VaSet
)
xt "75600,145800,78200,147000"
st "I19"
blo "75600,146800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11395,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11396,0
text (MLText
uid 11397,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "43000,118000,43000,118000"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*451 (SaComponent
uid 11434,0
optionalChildren [
*452 (CptPort
uid 11398,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11399,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,183625,91750,184375"
)
tg (CPTG
uid 11400,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11401,0
va (VaSet
)
xt "85600,183400,90000,184600"
st "memWr"
ju 2
blo "90000,184400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr"
t "std_ulogic"
o 1
)
)
)
*453 (CptPort
uid 11402,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11403,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,179625,75000,180375"
)
tg (CPTG
uid 11404,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11405,0
va (VaSet
)
xt "76000,179400,78200,180600"
st "sel"
blo "76000,180400"
)
)
thePort (LogicalPort
decl (Decl
n "sel"
t "std_ulogic"
o 2
)
)
)
*454 (CptPort
uid 11406,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11407,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,185625,91750,186375"
)
tg (CPTG
uid 11408,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11409,0
va (VaSet
)
xt "85600,185400,90000,186600"
st "memEn"
ju 2
blo "90000,186400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memEn"
t "std_ulogic"
o 3
)
)
)
*455 (CptPort
uid 11410,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11411,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,183625,75000,184375"
)
tg (CPTG
uid 11412,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11413,0
va (VaSet
)
xt "76000,183400,80100,184600"
st "update"
blo "76000,184400"
)
)
thePort (LogicalPort
decl (Decl
n "update"
t "std_ulogic"
o 4
)
)
)
*456 (CptPort
uid 11414,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11415,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,181625,75000,182375"
)
tg (CPTG
uid 11416,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11417,0
va (VaSet
)
xt "76000,181400,77800,182600"
st "wr"
blo "76000,182400"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_ulogic"
o 5
)
)
)
*457 (CptPort
uid 11418,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11419,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,179625,91750,180375"
)
tg (CPTG
uid 11420,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11421,0
va (VaSet
)
xt "85600,179400,90000,180600"
st "cntIncr"
ju 2
blo "90000,180400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cntIncr"
t "std_ulogic"
o 6
)
)
)
*458 (CptPort
uid 11422,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11423,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,185625,75000,186375"
)
tg (CPTG
uid 11424,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11425,0
va (VaSet
)
xt "76000,185400,82300,186600"
st "newSample"
blo "76000,186400"
)
)
thePort (LogicalPort
decl (Decl
n "newSample"
t "std_ulogic"
o 7
)
)
)
*459 (CptPort
uid 11426,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11427,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,189625,75000,190375"
)
tg (CPTG
uid 11428,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11429,0
va (VaSet
)
xt "76000,189400,79400,190600"
st "clock"
blo "76000,190400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 8
)
)
)
*460 (CptPort
uid 11430,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11431,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,191625,75000,192375"
)
tg (CPTG
uid 11432,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11433,0
va (VaSet
)
xt "76000,191400,79300,192600"
st "reset"
blo "76000,192400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 11435,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,176000,91000,194000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11436,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*461 (Text
uid 11437,0
va (VaSet
)
xt "75600,193800,79900,195000"
st "Curves"
blo "75600,194800"
tm "BdLibraryNameMgr"
)
*462 (Text
uid 11438,0
va (VaSet
)
xt "75600,194800,85800,196000"
st "blockRAMControl"
blo "75600,195800"
tm "CptNameMgr"
)
*463 (Text
uid 11439,0
va (VaSet
)
xt "75600,195800,78200,197000"
st "I17"
blo "75600,196800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11440,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11441,0
text (MLText
uid 11442,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "43000,168000,43000,168000"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*464 (SaComponent
uid 11479,0
optionalChildren [
*465 (CptPort
uid 11443,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11444,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,233625,91750,234375"
)
tg (CPTG
uid 11445,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11446,0
va (VaSet
)
xt "85600,233400,90000,234600"
st "memWr"
ju 2
blo "90000,234400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr"
t "std_ulogic"
o 1
)
)
)
*466 (CptPort
uid 11447,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11448,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,229625,75000,230375"
)
tg (CPTG
uid 11449,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11450,0
va (VaSet
)
xt "76000,229400,78200,230600"
st "sel"
blo "76000,230400"
)
)
thePort (LogicalPort
decl (Decl
n "sel"
t "std_ulogic"
o 2
)
)
)
*467 (CptPort
uid 11451,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11452,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,235625,91750,236375"
)
tg (CPTG
uid 11453,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11454,0
va (VaSet
)
xt "85600,235400,90000,236600"
st "memEn"
ju 2
blo "90000,236400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memEn"
t "std_ulogic"
o 3
)
)
)
*468 (CptPort
uid 11455,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11456,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,233625,75000,234375"
)
tg (CPTG
uid 11457,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11458,0
va (VaSet
)
xt "76000,233400,80100,234600"
st "update"
blo "76000,234400"
)
)
thePort (LogicalPort
decl (Decl
n "update"
t "std_ulogic"
o 4
)
)
)
*469 (CptPort
uid 11459,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11460,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,231625,75000,232375"
)
tg (CPTG
uid 11461,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11462,0
va (VaSet
)
xt "76000,231400,77800,232600"
st "wr"
blo "76000,232400"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_ulogic"
o 5
)
)
)
*470 (CptPort
uid 11463,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11464,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,229625,91750,230375"
)
tg (CPTG
uid 11465,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11466,0
va (VaSet
)
xt "85600,229400,90000,230600"
st "cntIncr"
ju 2
blo "90000,230400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cntIncr"
t "std_ulogic"
o 6
)
)
)
*471 (CptPort
uid 11467,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11468,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,235625,75000,236375"
)
tg (CPTG
uid 11469,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11470,0
va (VaSet
)
xt "76000,235400,82300,236600"
st "newSample"
blo "76000,236400"
)
)
thePort (LogicalPort
decl (Decl
n "newSample"
t "std_ulogic"
o 7
)
)
)
*472 (CptPort
uid 11471,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11472,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,239625,75000,240375"
)
tg (CPTG
uid 11473,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11474,0
va (VaSet
)
xt "76000,239400,79400,240600"
st "clock"
blo "76000,240400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 8
)
)
)
*473 (CptPort
uid 11475,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11476,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "74250,241625,75000,242375"
)
tg (CPTG
uid 11477,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11478,0
va (VaSet
)
xt "76000,241400,79300,242600"
st "reset"
blo "76000,242400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 9
)
)
)
]
shape (Rectangle
uid 11480,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "75000,226000,91000,244000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11481,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*474 (Text
uid 11482,0
va (VaSet
)
xt "75600,243800,79900,245000"
st "Curves"
blo "75600,244800"
tm "BdLibraryNameMgr"
)
*475 (Text
uid 11483,0
va (VaSet
)
xt "75600,244800,85800,246000"
st "blockRAMControl"
blo "75600,245800"
tm "CptNameMgr"
)
*476 (Text
uid 11484,0
va (VaSet
)
xt "75600,245800,78200,247000"
st "I31"
blo "75600,246800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11485,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11486,0
text (MLText
uid 11487,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "43000,218000,43000,218000"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*477 (SaComponent
uid 11488,0
optionalChildren [
*478 (CptPort
uid 11497,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11498,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,209625,161000,210375"
)
tg (CPTG
uid 11499,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11500,0
va (VaSet
)
xt "162000,209400,165400,210600"
st "clock"
blo "162000,210400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
)
)
)
*479 (CptPort
uid 11501,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11502,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,211625,161000,212375"
)
tg (CPTG
uid 11503,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11504,0
va (VaSet
)
xt "162000,211400,165300,212600"
st "reset"
blo "162000,212400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
)
)
)
*480 (CptPort
uid 11505,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11506,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,205625,161000,206375"
)
tg (CPTG
uid 11507,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11508,0
va (VaSet
)
xt "162000,205400,169900,206600"
st "shiftSamples"
blo "162000,206400"
)
)
thePort (LogicalPort
decl (Decl
n "shiftSamples"
t "std_ulogic"
o 3
)
)
)
*481 (CptPort
uid 11509,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11510,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "160250,203625,161000,204375"
)
tg (CPTG
uid 11511,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11512,0
va (VaSet
)
xt "162000,203400,167400,204600"
st "sampleIn"
blo "162000,204400"
)
)
thePort (LogicalPort
decl (Decl
n "sampleIn"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 4
)
)
)
*482 (CptPort
uid 11513,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11514,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,203625,177750,204375"
)
tg (CPTG
uid 11515,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11516,0
va (VaSet
)
xt "171000,203400,176000,204600"
st "sample1"
ju 2
blo "176000,204400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 5
)
)
)
*483 (CptPort
uid 11517,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11518,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,205625,177750,206375"
)
tg (CPTG
uid 11519,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11520,0
va (VaSet
)
xt "171000,205400,176000,206600"
st "sample2"
ju 2
blo "176000,206400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 6
)
)
)
*484 (CptPort
uid 11521,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11522,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,207625,177750,208375"
)
tg (CPTG
uid 11523,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11524,0
va (VaSet
)
xt "171000,207400,176000,208600"
st "sample3"
ju 2
blo "176000,208400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample3"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 7
)
)
)
*485 (CptPort
uid 11525,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11526,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "177000,209625,177750,210375"
)
tg (CPTG
uid 11527,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11528,0
va (VaSet
)
xt "171000,209400,176000,210600"
st "sample4"
ju 2
blo "176000,210400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sample4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 8
)
)
)
]
shape (Rectangle
uid 11489,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "161000,200000,177000,214000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11490,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*486 (Text
uid 11491,0
va (VaSet
)
xt "161600,213800,165900,215000"
st "Curves"
blo "161600,214800"
tm "BdLibraryNameMgr"
)
*487 (Text
uid 11492,0
va (VaSet
)
xt "161600,214800,176000,216000"
st "interpolatorShiftRegister"
blo "161600,215800"
tm "CptNameMgr"
)
*488 (Text
uid 11493,0
va (VaSet
)
xt "161600,215800,164200,217000"
st "I33"
blo "161600,216800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11494,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11495,0
text (MLText
uid 11496,0
va (VaSet
font "Verdana,8,0"
)
xt "161000,217600,179100,218600"
st "signalBitNb = signalBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*489 (Net
uid 11567,0
decl (Decl
n "sampleZ1"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 66
suid 78,0
)
declText (MLText
uid 11568,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,68800,240900,69800"
st "SIGNAL sampleZ1            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*490 (Net
uid 11569,0
decl (Decl
n "sampleZ2"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 67
suid 79,0
)
declText (MLText
uid 11570,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,69700,240900,70700"
st "SIGNAL sampleZ2            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*491 (HdlText
uid 11571,0
optionalChildren [
*492 (EmbeddedText
uid 11576,0
commentText (CommentText
uid 11577,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 11578,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "132000,202000,146300,206000"
)
oxt "0,0,18000,5000"
text (MLText
uid 11579,0
va (VaSet
)
xt "132200,202200,146500,205800"
st "
samplesZ <= (others => '1') when selSinCos = '1'
  else signed(memZ);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4000
visibleWidth 14300
)
)
)
]
shape (Rectangle
uid 11572,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "131000,200000,147000,208000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11573,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*493 (Text
uid 11574,0
va (VaSet
)
xt "131400,208000,134700,209200"
st "eb10"
blo "131400,209000"
tm "HdlTextNameMgr"
)
*494 (Text
uid 11575,0
va (VaSet
)
xt "131400,209000,133500,210200"
st "10"
blo "131400,210000"
tm "HdlTextNumberMgr"
)
]
)
)
*495 (Net
uid 11588,0
decl (Decl
n "samplesZ"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 70
suid 80,0
)
declText (MLText
uid 11589,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,72400,240800,73400"
st "SIGNAL samplesZ            : signed(signalBitNb-1 DOWNTO 0)"
)
)
*496 (SaComponent
uid 11858,0
optionalChildren [
*497 (CptPort
uid 11830,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11831,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,84625,281750,85375"
)
tg (CPTG
uid 11832,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11833,0
va (VaSet
)
xt "277200,84400,280000,85600"
st "CLK"
ju 2
blo "280000,85400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK"
t "std_ulogic"
o 17
)
)
)
*498 (CptPort
uid 11834,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11835,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,86625,265000,87375"
)
tg (CPTG
uid 11836,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11837,0
va (VaSet
)
xt "266000,86400,269400,87600"
st "clock"
blo "266000,87400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 3
)
)
)
*499 (CptPort
uid 11838,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11839,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,80625,281750,81375"
)
tg (CPTG
uid 11840,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11841,0
va (VaSet
)
xt "276600,80400,280000,81600"
st "CS_n"
ju 2
blo "280000,81400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CS_n"
t "std_ulogic"
o 15
)
)
)
*500 (CptPort
uid 11842,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11843,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,82625,265000,83375"
)
tg (CPTG
uid 11844,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11845,0
va (VaSet
)
xt "266000,82400,270500,83600"
st "enConv"
blo "266000,83400"
)
)
thePort (LogicalPort
decl (Decl
n "enConv"
t "std_uLogic"
o 37
)
)
)
*501 (CptPort
uid 11846,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11847,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,88625,265000,89375"
)
tg (CPTG
uid 11848,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11849,0
va (VaSet
)
xt "266000,88400,269300,89600"
st "reset"
blo "266000,89400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
)
)
)
*502 (CptPort
uid 11850,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11851,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,80625,265000,81375"
)
tg (CPTG
uid 11852,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11853,0
va (VaSet
)
xt "266000,80400,270000,81600"
st "dataIn"
blo "266000,81400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 56
)
)
)
*503 (CptPort
uid 11854,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11855,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,82625,281750,83375"
)
tg (CPTG
uid 11856,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11857,0
va (VaSet
)
xt "277300,82400,280000,83600"
st "SDI"
ju 2
blo "280000,83400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SDI"
t "std_ulogic"
o 16
)
)
)
]
shape (Rectangle
uid 11859,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "265000,77000,281000,91000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11860,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*504 (Text
uid 11861,0
va (VaSet
)
xt "265150,90800,269450,92000"
st "Curves"
blo "265150,91800"
tm "BdLibraryNameMgr"
)
*505 (Text
uid 11862,0
va (VaSet
)
xt "265150,91800,272950,93000"
st "dacInterface"
blo "265150,92800"
tm "CptNameMgr"
)
*506 (Text
uid 11863,0
va (VaSet
)
xt "265150,92800,267750,94000"
st "I34"
blo "265150,93800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11864,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11865,0
text (MLText
uid 11866,0
va (VaSet
font "Verdana,8,0"
)
xt "265000,94600,280300,95600"
st "bitNb = signalBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
]
)
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*507 (SaComponent
uid 11943,0
optionalChildren [
*508 (CptPort
uid 11952,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11953,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,62625,281750,63375"
)
tg (CPTG
uid 11954,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11955,0
va (VaSet
)
xt "277200,62400,280000,63600"
st "CLK"
ju 2
blo "280000,63400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK"
t "std_ulogic"
o 17
)
)
)
*509 (CptPort
uid 11956,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11957,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,64625,265000,65375"
)
tg (CPTG
uid 11958,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11959,0
va (VaSet
)
xt "266000,64400,269400,65600"
st "clock"
blo "266000,65400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 3
)
)
)
*510 (CptPort
uid 11960,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11961,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,58625,281750,59375"
)
tg (CPTG
uid 11962,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11963,0
va (VaSet
)
xt "276600,58400,280000,59600"
st "CS_n"
ju 2
blo "280000,59400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CS_n"
t "std_ulogic"
o 15
)
)
)
*511 (CptPort
uid 11964,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11965,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,60625,265000,61375"
)
tg (CPTG
uid 11966,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11967,0
va (VaSet
)
xt "266000,60400,270500,61600"
st "enConv"
blo "266000,61400"
)
)
thePort (LogicalPort
decl (Decl
n "enConv"
t "std_uLogic"
o 37
)
)
)
*512 (CptPort
uid 11968,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11969,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,66625,265000,67375"
)
tg (CPTG
uid 11970,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11971,0
va (VaSet
)
xt "266000,66400,269300,67600"
st "reset"
blo "266000,67400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 4
)
)
)
*513 (CptPort
uid 11972,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11973,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "264250,58625,265000,59375"
)
tg (CPTG
uid 11974,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 11975,0
va (VaSet
)
xt "266000,58400,270000,59600"
st "dataIn"
blo "266000,59400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "unsigned"
b "(bitNb-1 DOWNTO 0)"
o 56
)
)
)
*514 (CptPort
uid 11976,0
ps "OnEdgeStrategy"
shape (Triangle
uid 11977,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "281000,60625,281750,61375"
)
tg (CPTG
uid 11978,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 11979,0
va (VaSet
)
xt "277300,60400,280000,61600"
st "SDI"
ju 2
blo "280000,61400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SDI"
t "std_ulogic"
o 16
)
)
)
]
shape (Rectangle
uid 11944,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "265000,55000,281000,69000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 11945,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*515 (Text
uid 11946,0
va (VaSet
)
xt "265150,68800,269450,70000"
st "Curves"
blo "265150,69800"
tm "BdLibraryNameMgr"
)
*516 (Text
uid 11947,0
va (VaSet
)
xt "265150,69800,272950,71000"
st "dacInterface"
blo "265150,70800"
tm "CptNameMgr"
)
*517 (Text
uid 11948,0
va (VaSet
)
xt "265150,70800,267750,72000"
st "I35"
blo "265150,71800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 11949,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 11950,0
text (MLText
uid 11951,0
va (VaSet
font "Verdana,8,0"
)
xt "265000,72600,280300,73600"
st "bitNb = signalBitNb    ( positive ) "
)
header ""
)
elements [
(GiElement
name "bitNb"
type "positive"
value "signalBitNb"
)
]
)
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*518 (PortIoOut
uid 12050,0
shape (CompositeShape
uid 12051,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12052,0
sl 0
ro 270
xt "289500,84625,291000,85375"
)
(Line
uid 12053,0
sl 0
ro 270
xt "289000,85000,289500,85000"
pts [
"289000,85000"
"289500,85000"
]
)
]
)
tg (WTG
uid 12054,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12055,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "292000,84300,296800,85700"
st "CLK_X"
blo "292000,85500"
tm "WireNameMgr"
)
)
)
*519 (Net
uid 12062,0
decl (Decl
n "CLK_X"
t "std_ulogic"
o 17
suid 81,0
)
declText (MLText
uid 12063,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,16600,227300,17600"
st "CLK_X               : std_ulogic"
)
)
*520 (PortIoOut
uid 12064,0
shape (CompositeShape
uid 12065,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12066,0
sl 0
ro 270
xt "289500,62625,291000,63375"
)
(Line
uid 12067,0
sl 0
ro 270
xt "289000,63000,289500,63000"
pts [
"289000,63000"
"289500,63000"
]
)
]
)
tg (WTG
uid 12068,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12069,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "292000,62300,296700,63700"
st "CLK_Y"
blo "292000,63500"
tm "WireNameMgr"
)
)
)
*521 (Net
uid 12076,0
decl (Decl
n "CLK_Y"
t "std_ulogic"
o 18
suid 82,0
)
declText (MLText
uid 12077,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,17500,227300,18500"
st "CLK_Y               : std_ulogic"
)
)
*522 (PortIoOut
uid 12078,0
shape (CompositeShape
uid 12079,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12080,0
sl 0
ro 270
xt "289500,80625,291000,81375"
)
(Line
uid 12081,0
sl 0
ro 270
xt "289000,81000,289500,81000"
pts [
"289000,81000"
"289500,81000"
]
)
]
)
tg (WTG
uid 12082,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12083,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "292000,80300,297700,81700"
st "CS_X_n"
blo "292000,81500"
tm "WireNameMgr"
)
)
)
*523 (Net
uid 12090,0
decl (Decl
n "CS_X_n"
t "std_ulogic"
o 15
suid 83,0
)
declText (MLText
uid 12091,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,14800,227500,15800"
st "CS_X_n              : std_ulogic"
)
)
*524 (PortIoOut
uid 12092,0
shape (CompositeShape
uid 12093,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12094,0
sl 0
ro 270
xt "289500,58625,291000,59375"
)
(Line
uid 12095,0
sl 0
ro 270
xt "289000,59000,289500,59000"
pts [
"289000,59000"
"289500,59000"
]
)
]
)
tg (WTG
uid 12096,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12097,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "292000,58300,297600,59700"
st "CS_Y_n"
blo "292000,59500"
tm "WireNameMgr"
)
)
)
*525 (Net
uid 12104,0
decl (Decl
n "CS_Y_n"
t "std_ulogic"
o 19
suid 84,0
)
declText (MLText
uid 12105,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,18400,227500,19400"
st "CS_Y_n              : std_ulogic"
)
)
*526 (PortIoOut
uid 12106,0
shape (CompositeShape
uid 12107,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12108,0
sl 0
ro 270
xt "289500,82625,291000,83375"
)
(Line
uid 12109,0
sl 0
ro 270
xt "289000,83000,289500,83000"
pts [
"289000,83000"
"289500,83000"
]
)
]
)
tg (WTG
uid 12110,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12111,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "292000,82300,296600,83700"
st "SDI_X"
blo "292000,83500"
tm "WireNameMgr"
)
)
)
*527 (Net
uid 12118,0
decl (Decl
n "SDI_X"
t "std_ulogic"
o 16
suid 85,0
)
declText (MLText
uid 12119,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,15700,227100,16700"
st "SDI_X               : std_ulogic"
)
)
*528 (PortIoOut
uid 12120,0
shape (CompositeShape
uid 12121,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 12122,0
sl 0
ro 270
xt "289500,60625,291000,61375"
)
(Line
uid 12123,0
sl 0
ro 270
xt "289000,61000,289500,61000"
pts [
"289000,61000"
"289500,61000"
]
)
]
)
tg (WTG
uid 12124,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12125,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "292000,60300,296500,61700"
st "SDI_Y"
blo "292000,61500"
tm "WireNameMgr"
)
)
)
*529 (Net
uid 12132,0
decl (Decl
n "SDI_Y"
t "std_ulogic"
o 20
suid 86,0
)
declText (MLText
uid 12133,0
va (VaSet
font "Verdana,8,0"
)
xt "214000,19300,227100,20300"
st "SDI_Y               : std_ulogic"
)
)
*530 (Wire
uid 59,0
shape (OrthoPolyLine
uid 60,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "3000,32000,6250,32000"
pts [
"3000,32000"
"6250,32000"
]
)
start &12
end &250
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 63,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 64,0
va (VaSet
font "Verdana,12,0"
)
xt "3000,30600,6700,32000"
st "addr"
blo "3000,31800"
tm "WireNameMgr"
)
)
on &13
)
*531 (Wire
uid 73,0
shape (OrthoPolyLine
uid 74,0
va (VaSet
vasetType 3
)
xt "71000,24000,74250,24000"
pts [
"71000,24000"
"74250,24000"
]
)
start &14
end &288
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 77,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 78,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,22600,74800,24000"
st "clock"
blo "71000,23800"
tm "WireNameMgr"
)
)
on &15
)
*532 (Wire
uid 87,0
shape (OrthoPolyLine
uid 88,0
va (VaSet
vasetType 3
)
xt "19000,60000,26250,60000"
pts [
"19000,60000"
"26250,60000"
]
)
start &16
end &181
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 91,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 92,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,58600,21100,60000"
st "cs"
blo "19000,59800"
tm "WireNameMgr"
)
)
on &17
)
*533 (Wire
uid 115,0
shape (OrthoPolyLine
uid 116,0
va (VaSet
vasetType 3
)
xt "281750,154000,289000,154000"
pts [
"281750,154000"
"289000,154000"
]
)
start &34
end &18
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 119,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 120,0
va (VaSet
font "Verdana,12,0"
)
xt "286000,152600,289700,154000"
st "outX"
blo "286000,153800"
tm "WireNameMgr"
)
)
on &19
)
*534 (Wire
uid 129,0
shape (OrthoPolyLine
uid 130,0
va (VaSet
vasetType 3
)
xt "281750,117000,289000,117000"
pts [
"281750,117000"
"289000,117000"
]
)
start &65
end &20
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 133,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 134,0
va (VaSet
font "Verdana,12,0"
)
xt "286000,115600,289600,117000"
st "outY"
blo "286000,116800"
tm "WireNameMgr"
)
)
on &21
)
*535 (Wire
uid 143,0
shape (OrthoPolyLine
uid 144,0
va (VaSet
vasetType 3
)
xt "19000,96000,27000,96000"
pts [
"19000,96000"
"27000,96000"
]
)
start &22
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 147,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 148,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,94600,21100,96000"
st "rd"
blo "19000,95800"
tm "WireNameMgr"
)
)
on &23
)
*536 (Wire
uid 157,0
shape (OrthoPolyLine
uid 158,0
va (VaSet
vasetType 3
)
xt "71000,26000,74250,26000"
pts [
"71000,26000"
"74250,26000"
]
)
start &24
end &289
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 161,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 162,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,24600,75100,26000"
st "reset"
blo "71000,25800"
tm "WireNameMgr"
)
)
on &25
)
*537 (Wire
uid 171,0
shape (OrthoPolyLine
uid 172,0
va (VaSet
vasetType 3
)
xt "19000,58000,26250,58000"
pts [
"19000,58000"
"26250,58000"
]
)
start &26
end &180
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 175,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 176,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,56600,22300,58000"
st "wrH"
blo "19000,57800"
tm "WireNameMgr"
)
)
on &27
)
*538 (Wire
uid 185,0
shape (OrthoPolyLine
uid 186,0
va (VaSet
vasetType 3
)
xt "19000,80000,26250,80000"
pts [
"19000,80000"
"26250,80000"
]
)
start &28
end &190
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 189,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 190,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,78600,22100,80000"
st "wrL"
blo "19000,79800"
tm "WireNameMgr"
)
)
on &29
)
*539 (Wire
uid 354,0
optionalChildren [
*540 (BdJunction
uid 9152,0
ps "OnConnectorStrategy"
shape (Circle
uid 9153,0
va (VaSet
vasetType 1
)
xt "152600,155600,153400,156400"
radius 400
)
)
*541 (BdJunction
uid 11549,0
ps "OnConnectorStrategy"
shape (Circle
uid 11550,0
va (VaSet
vasetType 1
)
xt "152600,168600,153400,169400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 355,0
va (VaSet
vasetType 3
)
xt "153000,156000,181000,176000"
pts [
"181000,176000"
"181000,169000"
"153000,169000"
"153000,156000"
"160250,156000"
]
)
start *542 (BdJunction
uid 564,0
ps "OnConnectorStrategy"
shape (Circle
uid 565,0
va (VaSet
vasetType 1
)
xt "180600,175600,181400,176400"
radius 400
)
)
end &358
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 356,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 357,0
va (VaSet
font "Verdana,12,0"
)
xt "152000,154600,161600,156000"
st "newPolynom"
blo "152000,155800"
tm "WireNameMgr"
)
)
on &30
)
*543 (Wire
uid 360,0
optionalChildren [
&542
*544 (BdJunction
uid 9244,0
ps "OnConnectorStrategy"
shape (Circle
uid 9245,0
va (VaSet
vasetType 1
)
xt "204600,161600,205400,162400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 361,0
va (VaSet
vasetType 3
)
xt "177750,162000,216250,176000"
pts [
"177750,176000"
"205000,176000"
"205000,162000"
"216250,162000"
]
)
start &117
end &383
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 362,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 363,0
va (VaSet
font "Verdana,12,0"
)
xt "201000,174600,210600,176000"
st "newPolynom"
blo "201000,175800"
tm "WireNameMgr"
)
)
on &30
)
*545 (Wire
uid 364,0
shape (OrthoPolyLine
uid 365,0
va (VaSet
vasetType 3
)
xt "157000,182000,160250,182000"
pts [
"157000,182000"
"160250,182000"
]
)
end &119
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 368,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 369,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,180600,160100,182000"
st "reset"
blo "156000,181800"
tm "WireNameMgr"
)
)
on &25
)
*546 (Wire
uid 370,0
shape (OrthoPolyLine
uid 371,0
va (VaSet
vasetType 3
)
xt "157000,180000,160250,180000"
pts [
"157000,180000"
"160250,180000"
]
)
end &118
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 374,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 375,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,178600,159800,180000"
st "clock"
blo "156000,179800"
tm "WireNameMgr"
)
)
on &15
)
*547 (Wire
uid 376,0
shape (OrthoPolyLine
uid 377,0
va (VaSet
vasetType 3
)
xt "157000,162000,160250,162000"
pts [
"157000,162000"
"160250,162000"
]
)
end &357
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 381,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,160600,160100,162000"
st "reset"
blo "156000,161800"
tm "WireNameMgr"
)
)
on &25
)
*548 (Wire
uid 382,0
shape (OrthoPolyLine
uid 383,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,154000,160250,154000"
pts [
"147000,154000"
"160250,154000"
]
)
start &129
end &359
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 384,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 385,0
va (VaSet
font "Verdana,12,0"
)
xt "149000,152600,155800,154000"
st "samplesX"
blo "149000,153800"
tm "WireNameMgr"
)
)
on &47
)
*549 (Wire
uid 386,0
shape (OrthoPolyLine
uid 387,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,156000,184250,156000"
pts [
"177750,156000"
"184250,156000"
]
)
start &361
end &297
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,154600,184900,156000"
st "sampleX2"
blo "178000,155800"
tm "WireNameMgr"
)
)
on &49
)
*550 (Wire
uid 390,0
shape (OrthoPolyLine
uid 391,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,154000,184250,154000"
pts [
"177750,154000"
"184250,154000"
]
)
start &360
end &296
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 392,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 393,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,152600,184900,154000"
st "sampleX1"
blo "178000,153800"
tm "WireNameMgr"
)
)
on &48
)
*551 (Wire
uid 394,0
shape (OrthoPolyLine
uid 395,0
va (VaSet
vasetType 3
)
xt "157000,160000,160250,160000"
pts [
"157000,160000"
"160250,160000"
]
)
end &356
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 398,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 399,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,158600,159800,160000"
st "clock"
blo "156000,159800"
tm "WireNameMgr"
)
)
on &15
)
*552 (Wire
uid 400,0
shape (OrthoPolyLine
uid 401,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,154000,216250,154000"
pts [
"201750,154000"
"216250,154000"
]
)
start &300
end &388
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 402,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 403,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,152600,206150,154000"
st "aX"
blo "203750,153800"
tm "WireNameMgr"
)
)
on &52
)
*553 (Wire
uid 404,0
shape (OrthoPolyLine
uid 405,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,160000,184250,160000"
pts [
"177750,160000"
"184250,160000"
]
)
start &363
end &299
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 406,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 407,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,158600,184900,160000"
st "sampleX4"
blo "178000,159800"
tm "WireNameMgr"
)
)
on &51
)
*554 (Wire
uid 408,0
shape (OrthoPolyLine
uid 409,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,158000,184250,158000"
pts [
"177750,158000"
"184250,158000"
]
)
start &362
end &298
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 410,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 411,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,156600,184900,158000"
st "sampleX3"
blo "178000,157800"
tm "WireNameMgr"
)
)
on &50
)
*555 (Wire
uid 412,0
shape (OrthoPolyLine
uid 413,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,160000,216250,160000"
pts [
"201750,160000"
"216250,160000"
]
)
start &302
end &384
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 414,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 415,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,158600,206150,160000"
st "dX"
blo "203750,159800"
tm "WireNameMgr"
)
)
on &55
)
*556 (Wire
uid 416,0
shape (OrthoPolyLine
uid 417,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,158000,216250,158000"
pts [
"201750,158000"
"216250,158000"
]
)
start &303
end &386
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 418,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 419,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,156600,205950,158000"
st "cX"
blo "203750,157800"
tm "WireNameMgr"
)
)
on &54
)
*557 (Wire
uid 420,0
shape (OrthoPolyLine
uid 421,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,156000,216250,156000"
pts [
"201750,156000"
"216250,156000"
]
)
start &301
end &387
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 422,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 423,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,154600,206150,156000"
st "bX"
blo "203750,155800"
tm "WireNameMgr"
)
)
on &53
)
*558 (Wire
uid 424,0
shape (OrthoPolyLine
uid 425,0
va (VaSet
vasetType 3
)
xt "213000,170000,216250,170000"
pts [
"213000,170000"
"216250,170000"
]
)
end &382
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,168600,216100,170000"
st "reset"
blo "212000,169800"
tm "WireNameMgr"
)
)
on &25
)
*559 (Wire
uid 430,0
shape (OrthoPolyLine
uid 431,0
va (VaSet
vasetType 3
)
xt "213000,168000,216250,168000"
pts [
"213000,168000"
"216250,168000"
]
)
end &381
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 434,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 435,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,166600,215800,168000"
st "clock"
blo "212000,167800"
tm "WireNameMgr"
)
)
on &15
)
*560 (Wire
uid 497,0
shape (OrthoPolyLine
uid 498,0
va (VaSet
vasetType 3
)
xt "261000,160000,264250,160000"
pts [
"261000,160000"
"264250,160000"
]
)
end &35
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 503,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 504,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,158600,264100,160000"
st "reset"
blo "260000,159800"
tm "WireNameMgr"
)
)
on &25
)
*561 (Wire
uid 505,0
shape (OrthoPolyLine
uid 506,0
va (VaSet
vasetType 3
)
xt "261000,158000,264250,158000"
pts [
"261000,158000"
"264250,158000"
]
)
end &32
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 511,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 512,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,156600,263800,158000"
st "clock"
blo "260000,157800"
tm "WireNameMgr"
)
)
on &15
)
*562 (Wire
uid 532,0
shape (OrthoPolyLine
uid 533,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "233750,154000,240250,154000"
pts [
"233750,154000"
"240250,154000"
]
)
start &385
end &41
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 534,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 535,0
va (VaSet
font "Verdana,12,0"
)
xt "234000,152600,240100,154000"
st "sampleX"
blo "234000,153800"
tm "WireNameMgr"
)
)
on &45
)
*563 (Wire
uid 538,0
shape (OrthoPolyLine
uid 539,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "257750,154000,264250,154000"
pts [
"257750,154000"
"264250,154000"
]
)
start &40
end &33
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 540,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 541,0
va (VaSet
font "Verdana,12,0"
)
xt "258000,152600,265400,154000"
st "unsignedX"
blo "258000,153800"
tm "WireNameMgr"
)
)
on &46
)
*564 (Wire
uid 767,0
shape (OrthoPolyLine
uid 768,0
va (VaSet
vasetType 3
)
xt "205000,125000,216250,162000"
pts [
"205000,162000"
"205000,125000"
"216250,125000"
]
)
start &544
end &370
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 771,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 772,0
va (VaSet
font "Verdana,12,0"
)
xt "205000,123600,214600,125000"
st "newPolynom"
blo "205000,124800"
tm "WireNameMgr"
)
)
on &30
)
*565 (Wire
uid 775,0
shape (OrthoPolyLine
uid 776,0
va (VaSet
vasetType 3
)
xt "153000,119000,160250,156000"
pts [
"153000,156000"
"153000,119000"
"160250,119000"
]
)
start &540
end &346
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 777,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 778,0
va (VaSet
font "Verdana,12,0"
)
xt "152000,117600,161600,119000"
st "newPolynom"
blo "152000,118800"
tm "WireNameMgr"
)
)
on &30
)
*566 (Wire
uid 779,0
shape (OrthoPolyLine
uid 780,0
va (VaSet
vasetType 3
)
xt "157000,125000,160250,125000"
pts [
"157000,125000"
"160250,125000"
]
)
end &345
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 783,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 784,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,123600,160100,125000"
st "reset"
blo "156000,124800"
tm "WireNameMgr"
)
)
on &25
)
*567 (Wire
uid 785,0
shape (OrthoPolyLine
uid 786,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,117000,184250,117000"
pts [
"177750,117000"
"184250,117000"
]
)
start &348
end &309
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 787,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 788,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,115600,184800,117000"
st "sampleY1"
blo "178000,116800"
tm "WireNameMgr"
)
)
on &71
)
*568 (Wire
uid 789,0
shape (OrthoPolyLine
uid 790,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,119000,184250,119000"
pts [
"177750,119000"
"184250,119000"
]
)
start &349
end &310
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 791,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 792,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,117600,184800,119000"
st "sampleY2"
blo "178000,118800"
tm "WireNameMgr"
)
)
on &72
)
*569 (Wire
uid 793,0
shape (OrthoPolyLine
uid 794,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,117000,160250,117000"
pts [
"147000,117000"
"160250,117000"
]
)
start &167
end &347
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 797,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 798,0
va (VaSet
font "Verdana,12,0"
)
xt "148000,115600,154700,117000"
st "samplesY"
blo "148000,116800"
tm "WireNameMgr"
)
)
on &70
)
*570 (Wire
uid 799,0
shape (OrthoPolyLine
uid 800,0
va (VaSet
vasetType 3
)
xt "157000,123000,160250,123000"
pts [
"157000,123000"
"160250,123000"
]
)
end &344
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 803,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 804,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,121600,159800,123000"
st "clock"
blo "156000,122800"
tm "WireNameMgr"
)
)
on &15
)
*571 (Wire
uid 805,0
shape (OrthoPolyLine
uid 806,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,123000,216250,123000"
pts [
"201750,123000"
"216250,123000"
]
)
start &315
end &371
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 807,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 808,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,121600,206050,123000"
st "dY"
blo "203750,122800"
tm "WireNameMgr"
)
)
on &78
)
*572 (Wire
uid 809,0
shape (OrthoPolyLine
uid 810,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,121000,184250,121000"
pts [
"177750,121000"
"184250,121000"
]
)
start &350
end &311
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 811,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 812,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,119600,184800,121000"
st "sampleY3"
blo "178000,120800"
tm "WireNameMgr"
)
)
on &73
)
*573 (Wire
uid 813,0
shape (OrthoPolyLine
uid 814,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,123000,184250,123000"
pts [
"177750,123000"
"184250,123000"
]
)
start &351
end &312
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 815,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 816,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,121600,184800,123000"
st "sampleY4"
blo "178000,122800"
tm "WireNameMgr"
)
)
on &74
)
*574 (Wire
uid 817,0
shape (OrthoPolyLine
uid 818,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,117000,216250,117000"
pts [
"201750,117000"
"216250,117000"
]
)
start &313
end &375
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 819,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 820,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,115600,206050,117000"
st "aY"
blo "203750,116800"
tm "WireNameMgr"
)
)
on &75
)
*575 (Wire
uid 821,0
shape (OrthoPolyLine
uid 822,0
va (VaSet
vasetType 3
)
xt "213000,133000,216250,133000"
pts [
"213000,133000"
"216250,133000"
]
)
end &369
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 825,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 826,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,131600,216100,133000"
st "reset"
blo "212000,132800"
tm "WireNameMgr"
)
)
on &25
)
*576 (Wire
uid 827,0
shape (OrthoPolyLine
uid 828,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,119000,216250,119000"
pts [
"201750,119000"
"216250,119000"
]
)
start &314
end &374
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 829,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 830,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,117600,206050,119000"
st "bY"
blo "203750,118800"
tm "WireNameMgr"
)
)
on &76
)
*577 (Wire
uid 831,0
shape (OrthoPolyLine
uid 832,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "201750,121000,216250,121000"
pts [
"201750,121000"
"216250,121000"
]
)
start &316
end &373
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 834,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,119600,205850,121000"
st "cY"
blo "203750,120800"
tm "WireNameMgr"
)
)
on &77
)
*578 (Wire
uid 835,0
shape (OrthoPolyLine
uid 836,0
va (VaSet
vasetType 3
)
xt "261000,123000,264250,123000"
pts [
"261000,123000"
"264250,123000"
]
)
end &66
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 839,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 840,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,121600,264100,123000"
st "reset"
blo "260000,122800"
tm "WireNameMgr"
)
)
on &25
)
*579 (Wire
uid 841,0
shape (OrthoPolyLine
uid 842,0
va (VaSet
vasetType 3
)
xt "213000,131000,216250,131000"
pts [
"213000,131000"
"216250,131000"
]
)
end &368
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 845,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 846,0
va (VaSet
font "Verdana,12,0"
)
xt "212000,129600,215800,131000"
st "clock"
blo "212000,130800"
tm "WireNameMgr"
)
)
on &15
)
*580 (Wire
uid 847,0
shape (OrthoPolyLine
uid 848,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "233750,117000,240250,117000"
pts [
"233750,117000"
"240250,117000"
]
)
start &372
end &58
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 849,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 850,0
va (VaSet
font "Verdana,12,0"
)
xt "234000,115600,240000,117000"
st "sampleY"
blo "234000,116800"
tm "WireNameMgr"
)
)
on &79
)
*581 (Wire
uid 851,0
shape (OrthoPolyLine
uid 852,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "257750,117000,264250,117000"
pts [
"257750,117000"
"264250,117000"
]
)
start &57
end &64
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 853,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 854,0
va (VaSet
font "Verdana,12,0"
)
xt "258000,115600,265300,117000"
st "unsignedY"
blo "258000,116800"
tm "WireNameMgr"
)
)
on &80
)
*582 (Wire
uid 855,0
shape (OrthoPolyLine
uid 856,0
va (VaSet
vasetType 3
)
xt "261000,121000,264250,121000"
pts [
"261000,121000"
"264250,121000"
]
)
end &63
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 859,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 860,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,119600,263800,121000"
st "clock"
blo "260000,120800"
tm "WireNameMgr"
)
)
on &15
)
*583 (Wire
uid 1049,0
shape (OrthoPolyLine
uid 1050,0
va (VaSet
vasetType 3
)
xt "43750,34000,74250,48000"
pts [
"43750,34000"
"57000,34000"
"57000,48000"
"74250,48000"
]
)
start &423
end &110
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1053,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1054,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,46600,72200,48000"
st "selSize"
blo "67000,47800"
tm "WireNameMgr"
)
)
on &82
)
*584 (Wire
uid 1057,0
shape (OrthoPolyLine
uid 1058,0
va (VaSet
vasetType 3
)
xt "43750,36000,74250,78000"
pts [
"43750,36000"
"55000,36000"
"55000,78000"
"74250,78000"
]
)
start &424
end &98
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1061,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1062,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,76600,73600,78000"
st "selSpeed"
blo "67000,77800"
tm "WireNameMgr"
)
)
on &83
)
*585 (Wire
uid 1065,0
shape (OrthoPolyLine
uid 1066,0
va (VaSet
vasetType 3
)
xt "43750,38000,74250,180000"
pts [
"43750,38000"
"53000,38000"
"53000,180000"
"74250,180000"
]
)
start &425
end &453
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1069,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1070,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,178600,70400,180000"
st "selX"
blo "67000,179800"
tm "WireNameMgr"
)
)
on &84
)
*586 (Wire
uid 1073,0
shape (OrthoPolyLine
uid 1074,0
va (VaSet
vasetType 3
)
xt "43750,40000,74250,130000"
pts [
"43750,40000"
"51000,40000"
"51000,130000"
"74250,130000"
]
)
start &426
end &440
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1077,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1078,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,128600,70300,130000"
st "selY"
blo "67000,129800"
tm "WireNameMgr"
)
)
on &85
)
*587 (Wire
uid 1332,0
shape (OrthoPolyLine
uid 1333,0
va (VaSet
vasetType 3
)
xt "43750,20000,74250,32000"
pts [
"43750,32000"
"57000,32000"
"57000,20000"
"74250,20000"
]
)
start &421
end &287
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1338,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1339,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,18600,75000,20000"
st "selControl"
blo "67000,19800"
tm "WireNameMgr"
)
)
on &81
)
*588 (Wire
uid 1340,0
shape (OrthoPolyLine
uid 1341,0
va (VaSet
vasetType 3
)
xt "67000,18000,74250,18000"
pts [
"67000,18000"
"74250,18000"
]
)
end &286
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1346,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1347,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,16600,73500,18000"
st "wrLPulse"
blo "67000,17800"
tm "WireNameMgr"
)
)
on &197
)
*589 (Wire
uid 1350,0
shape (OrthoPolyLine
uid 1351,0
va (VaSet
vasetType 3
)
xt "91750,12000,106250,66000"
pts [
"91750,12000"
"103000,12000"
"103000,66000"
"106250,66000"
]
)
start &282
end &149
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1354,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1355,0
va (VaSet
font "Verdana,12,0"
)
xt "93750,10600,96650,12000"
st "run"
blo "93750,11800"
tm "WireNameMgr"
)
)
on &86
)
*590 (Wire
uid 1358,0
shape (OrthoPolyLine
uid 1359,0
va (VaSet
vasetType 3
)
xt "91750,14000,99000,14000"
pts [
"91750,14000"
"99000,14000"
]
)
start &284
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1362,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1363,0
va (VaSet
font "Verdana,12,0"
)
xt "93750,12600,104550,14000"
st "updatePattern"
blo "93750,13800"
tm "WireNameMgr"
)
)
on &87
)
*591 (Wire
uid 1472,0
shape (OrthoPolyLine
uid 1473,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,40000,99000,40000"
pts [
"91750,40000"
"99000,40000"
]
)
start &106
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1477,0
va (VaSet
font "Verdana,12,0"
)
xt "93750,38600,102650,40000"
st "patternSize"
blo "93750,39800"
tm "WireNameMgr"
)
)
on &88
)
*592 (Wire
uid 1494,0
shape (OrthoPolyLine
uid 1495,0
va (VaSet
vasetType 3
)
xt "71000,52000,74250,52000"
pts [
"71000,52000"
"74250,52000"
]
)
end &111
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1500,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1501,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,50600,74800,52000"
st "clock"
blo "71000,51800"
tm "WireNameMgr"
)
)
on &15
)
*593 (Wire
uid 1502,0
shape (OrthoPolyLine
uid 1503,0
va (VaSet
vasetType 3
)
xt "71000,54000,74250,54000"
pts [
"71000,54000"
"74250,54000"
]
)
end &112
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1508,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1509,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,52600,75100,54000"
st "reset"
blo "71000,53800"
tm "WireNameMgr"
)
)
on &25
)
*594 (Wire
uid 1510,0
shape (OrthoPolyLine
uid 1511,0
va (VaSet
vasetType 3
)
xt "67000,46000,74250,46000"
pts [
"67000,46000"
"74250,46000"
]
)
end &109
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1516,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1517,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,44600,73700,46000"
st "wrHPulse"
blo "67000,45800"
tm "WireNameMgr"
)
)
on &187
)
*595 (Wire
uid 1526,0
optionalChildren [
*596 (BdJunction
uid 1538,0
ps "OnConnectorStrategy"
shape (Circle
uid 1539,0
va (VaSet
vasetType 1
)
xt "58600,11600,59400,12400"
radius 400
)
)
*597 (BdJunction
uid 1544,0
ps "OnConnectorStrategy"
shape (Circle
uid 1545,0
va (VaSet
vasetType 1
)
xt "58600,39600,59400,40400"
radius 400
)
)
*598 (BdJunction
uid 1736,0
ps "OnConnectorStrategy"
shape (Circle
uid 1737,0
va (VaSet
vasetType 1
)
xt "58600,67600,59400,68400"
radius 400
)
)
*599 (BdJunction
uid 2476,0
ps "OnConnectorStrategy"
shape (Circle
uid 2477,0
va (VaSet
vasetType 1
)
xt "58600,149600,59400,150400"
radius 400
)
)
*600 (BdJunction
uid 3825,0
ps "OnConnectorStrategy"
shape (Circle
uid 3826,0
va (VaSet
vasetType 1
)
xt "58600,99600,59400,100400"
radius 400
)
)
*601 (BdJunction
uid 10621,0
ps "OnConnectorStrategy"
shape (Circle
uid 10622,0
va (VaSet
vasetType 1
)
xt "58600,199600,59400,200400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1527,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "43750,10000,59000,204000"
pts [
"59000,204000"
"59000,10000"
"43750,10000"
]
)
end &240
es 0
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1532,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1533,0
va (VaSet
font "Verdana,12,0"
)
xt "44000,8600,51400,10000"
st "dataInReg"
blo "44000,9800"
tm "WireNameMgr"
)
)
on &246
)
*602 (Wire
uid 1534,0
shape (OrthoPolyLine
uid 1535,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,12000,74250,12000"
pts [
"59000,12000"
"74250,12000"
]
)
start &596
end &283
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1536,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1537,0
va (VaSet
font "Verdana,12,0"
)
xt "68000,10600,75400,12000"
st "dataInReg"
blo "68000,11800"
tm "WireNameMgr"
)
)
on &246
)
*603 (Wire
uid 1540,0
shape (OrthoPolyLine
uid 1541,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,40000,74250,40000"
pts [
"59000,40000"
"74250,40000"
]
)
start &597
end &107
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1542,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1543,0
va (VaSet
font "Verdana,12,0"
)
xt "70250,38600,77650,40000"
st "dataInReg"
blo "70250,39800"
tm "WireNameMgr"
)
)
on &246
)
*604 (Wire
uid 1583,0
optionalChildren [
*605 (BdJunction
uid 2856,0
ps "OnConnectorStrategy"
shape (Circle
uid 2857,0
va (VaSet
vasetType 1
)
xt "62600,69600,63400,70400"
radius 400
)
)
*606 (BdJunction
uid 2858,0
ps "OnConnectorStrategy"
shape (Circle
uid 2859,0
va (VaSet
vasetType 1
)
xt "62600,41600,63400,42400"
radius 400
)
)
*607 (BdJunction
uid 2864,0
ps "OnConnectorStrategy"
shape (Circle
uid 2865,0
va (VaSet
vasetType 1
)
xt "62600,13600,63400,14400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1584,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "19000,4000,63000,74000"
pts [
"63000,74000"
"63000,4000"
"19000,4000"
]
)
end &90
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1587,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1588,0
va (VaSet
font "Verdana,12,0"
)
xt "18000,1600,24000,3000"
st "dataOut"
blo "18000,2800"
tm "WireNameMgr"
)
)
on &91
)
*608 (Wire
uid 1653,0
shape (OrthoPolyLine
uid 1654,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "63000,42000,74250,42000"
pts [
"74250,42000"
"63000,42000"
]
)
start &108
end &606
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1655,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1656,0
va (VaSet
font "Verdana,12,0"
)
xt "68250,40600,74250,42000"
st "dataOut"
blo "68250,41800"
tm "WireNameMgr"
)
)
on &91
)
*609 (Wire
uid 1732,0
shape (OrthoPolyLine
uid 1733,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,68000,74250,68000"
pts [
"59000,68000"
"74250,68000"
]
)
start &598
end &95
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1735,0
va (VaSet
font "Verdana,12,0"
)
xt "69250,66600,76650,68000"
st "dataInReg"
blo "69250,67800"
tm "WireNameMgr"
)
)
on &246
)
*610 (Wire
uid 1738,0
shape (OrthoPolyLine
uid 1739,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "63000,70000,74250,70000"
pts [
"63000,70000"
"74250,70000"
]
)
start &605
end &96
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1740,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1741,0
va (VaSet
font "Verdana,12,0"
)
xt "68250,68600,74250,70000"
st "dataOut"
blo "68250,69800"
tm "WireNameMgr"
)
)
on &91
)
*611 (Wire
uid 1744,0
shape (OrthoPolyLine
uid 1745,0
va (VaSet
vasetType 3
)
xt "71000,84000,74250,84000"
pts [
"71000,84000"
"74250,84000"
]
)
end &100
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1750,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1751,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,82600,75100,84000"
st "reset"
blo "71000,83800"
tm "WireNameMgr"
)
)
on &25
)
*612 (Wire
uid 1752,0
shape (OrthoPolyLine
uid 1753,0
va (VaSet
vasetType 3
)
xt "71000,82000,74250,82000"
pts [
"71000,82000"
"74250,82000"
]
)
end &99
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1758,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1759,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,80600,74800,82000"
st "clock"
blo "71000,81800"
tm "WireNameMgr"
)
)
on &15
)
*613 (Wire
uid 1760,0
shape (OrthoPolyLine
uid 1761,0
va (VaSet
vasetType 3
)
xt "67000,74000,74250,74000"
pts [
"67000,74000"
"74250,74000"
]
)
end &97
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1766,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1767,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,72600,73700,74000"
st "wrHPulse"
blo "67000,73800"
tm "WireNameMgr"
)
)
on &187
)
*614 (Wire
uid 1768,0
shape (OrthoPolyLine
uid 1769,0
va (VaSet
vasetType 3
)
xt "67000,76000,74250,76000"
pts [
"67000,76000"
"74250,76000"
]
)
end &101
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1775,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,74600,73500,76000"
st "wrLPulse"
blo "67000,75800"
tm "WireNameMgr"
)
)
on &197
)
*615 (Wire
uid 1778,0
shape (OrthoPolyLine
uid 1779,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,68000,106250,68000"
pts [
"91750,68000"
"106250,68000"
]
)
start &94
end &148
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1782,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1783,0
va (VaSet
font "Verdana,12,0"
)
xt "93000,66600,103100,68000"
st "updatePeriod"
blo "93000,67800"
tm "WireNameMgr"
)
)
on &92
)
*616 (Wire
uid 1969,0
shape (OrthoPolyLine
uid 1970,0
va (VaSet
vasetType 3
)
xt "103000,74000,106250,74000"
pts [
"103000,74000"
"106250,74000"
]
)
end &147
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1975,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1976,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,72600,107100,74000"
st "reset"
blo "103000,73800"
tm "WireNameMgr"
)
)
on &25
)
*617 (Wire
uid 1977,0
shape (OrthoPolyLine
uid 1978,0
va (VaSet
vasetType 3
)
xt "103000,72000,106250,72000"
pts [
"103000,72000"
"106250,72000"
]
)
end &146
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1983,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1984,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,70600,106800,72000"
st "clock"
blo "103000,71800"
tm "WireNameMgr"
)
)
on &15
)
*618 (Wire
uid 1987,0
shape (OrthoPolyLine
uid 1988,0
va (VaSet
vasetType 3
)
xt "123750,66000,131000,66000"
pts [
"123750,66000"
"131000,66000"
]
)
start &145
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1991,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1992,0
va (VaSet
font "Verdana,12,0"
)
xt "125750,64600,136950,66000"
st "interpolationEn"
blo "125750,65800"
tm "WireNameMgr"
)
)
on &219
)
*619 (Wire
uid 1995,0
shape (OrthoPolyLine
uid 1996,0
va (VaSet
vasetType 3
)
xt "155000,176000,160250,176000"
pts [
"155000,176000"
"160250,176000"
]
)
end &120
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2001,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2002,0
va (VaSet
font "Verdana,12,0"
)
xt "150000,174600,163900,176000"
st "interpolationEnable"
blo "150000,175800"
tm "WireNameMgr"
)
)
on &124
)
*620 (Wire
uid 2472,0
shape (OrthoPolyLine
uid 2473,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,150000,106250,154000"
pts [
"106250,154000"
"99000,154000"
"99000,150000"
"59000,150000"
]
)
start &333
end &599
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2474,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2475,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,152600,107400,154000"
st "dataInReg"
blo "100000,153800"
tm "WireNameMgr"
)
)
on &246
)
*621 (Wire
uid 2478,0
shape (OrthoPolyLine
uid 2479,0
va (VaSet
vasetType 3
)
xt "103000,166000,106250,166000"
pts [
"103000,166000"
"106250,166000"
]
)
end &336
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2485,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,164600,106800,166000"
st "clock"
blo "103000,165800"
tm "WireNameMgr"
)
)
on &15
)
*622 (Wire
uid 2486,0
shape (OrthoPolyLine
uid 2487,0
va (VaSet
vasetType 3
)
xt "103000,168000,106250,168000"
pts [
"103000,168000"
"106250,168000"
]
)
end &337
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2492,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2493,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,166600,107100,168000"
st "reset"
blo "103000,167800"
tm "WireNameMgr"
)
)
on &25
)
*623 (Wire
uid 2638,0
shape (OrthoPolyLine
uid 2639,0
va (VaSet
vasetType 3
)
xt "91750,160000,106250,184000"
pts [
"91750,184000"
"99000,184000"
"99000,160000"
"106250,160000"
]
)
start &452
end &338
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2640,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2641,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,158600,106400,160000"
st "memWrX"
blo "100000,159800"
tm "WireNameMgr"
)
)
on &127
)
*624 (Wire
uid 2644,0
shape (OrthoPolyLine
uid 2645,0
va (VaSet
vasetType 3
)
xt "91750,162000,106250,186000"
pts [
"91750,186000"
"101000,186000"
"101000,162000"
"106250,162000"
]
)
start &454
end &335
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2646,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2647,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,160600,106200,162000"
st "memEnX"
blo "100000,161800"
tm "WireNameMgr"
)
)
on &128
)
*625 (Wire
uid 2648,0
shape (OrthoPolyLine
uid 2649,0
va (VaSet
vasetType 3
)
xt "67000,184000,74250,184000"
pts [
"67000,184000"
"74250,184000"
]
)
end &455
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2654,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2655,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,182600,76800,184000"
st "updatePattern"
blo "66000,183800"
tm "WireNameMgr"
)
)
on &87
)
*626 (Wire
uid 2772,0
shape (OrthoPolyLine
uid 2773,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,156000,106250,156000"
pts [
"91750,156000"
"106250,156000"
]
)
start &139
end &339
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2775,0
va (VaSet
font "Verdana,12,0"
)
xt "102000,154600,106500,156000"
st "addrX"
blo "102000,155800"
tm "WireNameMgr"
)
)
on &125
)
*627 (Wire
uid 2778,0
shape (OrthoPolyLine
uid 2779,0
va (VaSet
vasetType 3
)
xt "71000,166000,74250,166000"
pts [
"71000,166000"
"74250,166000"
]
)
end &137
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2784,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2785,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,164600,75100,166000"
st "reset"
blo "71000,165800"
tm "WireNameMgr"
)
)
on &25
)
*628 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
)
xt "71000,164000,74250,164000"
pts [
"71000,164000"
"74250,164000"
]
)
end &136
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2792,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2793,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,162600,74800,164000"
st "clock"
blo "71000,163800"
tm "WireNameMgr"
)
)
on &15
)
*629 (Wire
uid 2844,0
shape (OrthoPolyLine
uid 2845,0
va (VaSet
vasetType 3
)
xt "69000,160000,95000,180000"
pts [
"91750,180000"
"95000,180000"
"95000,174000"
"69000,174000"
"69000,160000"
"74250,160000"
]
)
start &457
end &135
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2846,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2847,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,158600,74900,160000"
st "cntIncrX"
blo "69000,159800"
tm "WireNameMgr"
)
)
on &126
)
*630 (Wire
uid 2860,0
shape (OrthoPolyLine
uid 2861,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "63000,14000,74250,14000"
pts [
"63000,14000"
"74250,14000"
]
)
start &607
end &285
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2862,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2863,0
va (VaSet
font "Verdana,12,0"
)
xt "68250,12600,74250,14000"
st "dataOut"
blo "68250,13800"
tm "WireNameMgr"
)
)
on &91
)
*631 (Wire
uid 2866,0
shape (OrthoPolyLine
uid 2867,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,156000,74250,156000"
pts [
"67000,156000"
"74250,156000"
]
)
end &140
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2873,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,154600,74900,156000"
st "patternSize"
blo "66000,155800"
tm "WireNameMgr"
)
)
on &88
)
*632 (Wire
uid 2919,0
shape (OrthoPolyLine
uid 2920,0
va (VaSet
vasetType 3
)
xt "67000,186000,74250,186000"
pts [
"74250,186000"
"67000,186000"
]
)
start &458
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2926,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,184600,75600,186000"
st "newPolynom"
blo "66000,185800"
tm "WireNameMgr"
)
)
on &30
)
*633 (Wire
uid 2996,0
shape (OrthoPolyLine
uid 2997,0
va (VaSet
vasetType 3
)
xt "71000,192000,74250,192000"
pts [
"71000,192000"
"74250,192000"
]
)
end &460
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3002,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3003,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,190600,75100,192000"
st "reset"
blo "71000,191800"
tm "WireNameMgr"
)
)
on &25
)
*634 (Wire
uid 3004,0
shape (OrthoPolyLine
uid 3005,0
va (VaSet
vasetType 3
)
xt "71000,190000,74250,190000"
pts [
"71000,190000"
"74250,190000"
]
)
end &459
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3010,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3011,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,188600,74800,190000"
st "clock"
blo "71000,189800"
tm "WireNameMgr"
)
)
on &15
)
*635 (Wire
uid 3094,0
shape (OrthoPolyLine
uid 3095,0
va (VaSet
vasetType 3
)
xt "67000,158000,74250,158000"
pts [
"67000,158000"
"74250,158000"
]
)
end &138
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3100,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3101,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,156600,76800,158000"
st "updatePattern"
blo "66000,157800"
tm "WireNameMgr"
)
)
on &87
)
*636 (Wire
uid 3146,0
shape (OrthoPolyLine
uid 3147,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "123750,154000,131000,154000"
pts [
"123750,154000"
"131000,154000"
]
)
start &334
end &129
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3150,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3151,0
va (VaSet
font "Verdana,12,0"
)
xt "125000,152600,129600,154000"
st "memX"
blo "125000,153800"
tm "WireNameMgr"
)
)
on &133
)
*637 (Wire
uid 3432,0
shape (OrthoPolyLine
uid 3433,0
va (VaSet
vasetType 3
)
xt "209000,166000,216250,166000"
pts [
"209000,166000"
"216250,166000"
]
)
end &389
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3438,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3439,0
va (VaSet
font "Verdana,12,0"
)
xt "204000,164600,217900,166000"
st "interpolationEnable"
blo "204000,165800"
tm "WireNameMgr"
)
)
on &124
)
*638 (Wire
uid 3485,0
shape (OrthoPolyLine
uid 3486,0
va (VaSet
vasetType 3
)
xt "209000,129000,216250,129000"
pts [
"209000,129000"
"216250,129000"
]
)
end &376
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3491,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3492,0
va (VaSet
font "Verdana,12,0"
)
xt "204000,127600,217900,129000"
st "interpolationEnable"
blo "204000,128800"
tm "WireNameMgr"
)
)
on &124
)
*639 (Wire
uid 3751,0
shape (OrthoPolyLine
uid 3752,0
va (VaSet
vasetType 3
)
xt "103000,131000,106250,131000"
pts [
"103000,131000"
"106250,131000"
]
)
end &326
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3755,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3756,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,129600,107100,131000"
st "reset"
blo "103000,130800"
tm "WireNameMgr"
)
)
on &25
)
*640 (Wire
uid 3757,0
shape (OrthoPolyLine
uid 3758,0
va (VaSet
vasetType 3
)
xt "103000,129000,106250,129000"
pts [
"103000,129000"
"106250,129000"
]
)
end &325
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3761,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3762,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,127600,106800,129000"
st "clock"
blo "103000,128800"
tm "WireNameMgr"
)
)
on &15
)
*641 (Wire
uid 3763,0
shape (OrthoPolyLine
uid 3764,0
va (VaSet
vasetType 3
)
xt "67000,134000,74250,134000"
pts [
"67000,134000"
"74250,134000"
]
)
end &442
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3767,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3768,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,132600,76800,134000"
st "updatePattern"
blo "66000,133800"
tm "WireNameMgr"
)
)
on &87
)
*642 (Wire
uid 3769,0
shape (OrthoPolyLine
uid 3770,0
va (VaSet
vasetType 3
)
xt "91750,125000,106250,136000"
pts [
"91750,136000"
"101000,136000"
"101000,125000"
"106250,125000"
]
)
start &441
end &324
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3771,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3772,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,123600,106100,125000"
st "memEnY"
blo "100000,124800"
tm "WireNameMgr"
)
)
on &166
)
*643 (Wire
uid 3773,0
shape (OrthoPolyLine
uid 3774,0
va (VaSet
vasetType 3
)
xt "91750,123000,106250,134000"
pts [
"91750,134000"
"99000,134000"
"99000,123000"
"106250,123000"
]
)
start &439
end &327
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3775,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3776,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,121600,106300,123000"
st "memWrY"
blo "100000,122800"
tm "WireNameMgr"
)
)
on &165
)
*644 (Wire
uid 3777,0
shape (OrthoPolyLine
uid 3778,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,106000,106250,119000"
pts [
"91750,106000"
"99000,106000"
"99000,119000"
"106250,119000"
]
)
start &158
end &328
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3779,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3780,0
va (VaSet
font "Verdana,12,0"
)
xt "102000,117600,106400,119000"
st "addrY"
blo "102000,118800"
tm "WireNameMgr"
)
)
on &164
)
*645 (Wire
uid 3793,0
shape (OrthoPolyLine
uid 3794,0
va (VaSet
vasetType 3
)
xt "69000,110000,95000,130000"
pts [
"91750,130000"
"95000,130000"
"95000,124000"
"69000,124000"
"69000,110000"
"74250,110000"
]
)
start &444
end &154
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3795,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3796,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,108600,74800,110000"
st "cntIncrY"
blo "69000,109800"
tm "WireNameMgr"
)
)
on &163
)
*646 (Wire
uid 3797,0
shape (OrthoPolyLine
uid 3798,0
va (VaSet
vasetType 3
)
xt "67000,136000,74250,136000"
pts [
"74250,136000"
"67000,136000"
]
)
start &445
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3801,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3802,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,134600,75600,136000"
st "newPolynom"
blo "66000,135800"
tm "WireNameMgr"
)
)
on &30
)
*647 (Wire
uid 3803,0
shape (OrthoPolyLine
uid 3804,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,106000,74250,106000"
pts [
"67000,106000"
"74250,106000"
]
)
end &159
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3807,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3808,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,104600,74900,106000"
st "patternSize"
blo "66000,105800"
tm "WireNameMgr"
)
)
on &88
)
*648 (Wire
uid 3809,0
shape (OrthoPolyLine
uid 3810,0
va (VaSet
vasetType 3
)
xt "67000,108000,74250,108000"
pts [
"67000,108000"
"74250,108000"
]
)
end &157
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3813,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3814,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,106600,76800,108000"
st "updatePattern"
blo "66000,107800"
tm "WireNameMgr"
)
)
on &87
)
*649 (Wire
uid 3815,0
shape (OrthoPolyLine
uid 3816,0
va (VaSet
vasetType 3
)
xt "71000,140000,74250,140000"
pts [
"71000,140000"
"74250,140000"
]
)
end &446
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3819,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3820,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,138600,74800,140000"
st "clock"
blo "71000,139800"
tm "WireNameMgr"
)
)
on &15
)
*650 (Wire
uid 3821,0
shape (OrthoPolyLine
uid 3822,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,100000,106250,117000"
pts [
"59000,100000"
"103000,100000"
"103000,117000"
"106250,117000"
]
)
start &600
end &322
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3823,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3824,0
va (VaSet
font "Verdana,12,0"
)
xt "101250,115600,108650,117000"
st "dataInReg"
blo "101250,116800"
tm "WireNameMgr"
)
)
on &246
)
*651 (Wire
uid 3866,0
shape (OrthoPolyLine
uid 3867,0
va (VaSet
vasetType 3
)
xt "71000,114000,74250,114000"
pts [
"71000,114000"
"74250,114000"
]
)
end &155
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3873,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,112600,74800,114000"
st "clock"
blo "71000,113800"
tm "WireNameMgr"
)
)
on &15
)
*652 (Wire
uid 3874,0
shape (OrthoPolyLine
uid 3875,0
va (VaSet
vasetType 3
)
xt "71000,116000,74250,116000"
pts [
"71000,116000"
"74250,116000"
]
)
end &156
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3880,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3881,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,114600,75100,116000"
st "reset"
blo "71000,115800"
tm "WireNameMgr"
)
)
on &25
)
*653 (Wire
uid 3882,0
shape (OrthoPolyLine
uid 3883,0
va (VaSet
vasetType 3
)
xt "71000,142000,74250,142000"
pts [
"71000,142000"
"74250,142000"
]
)
end &447
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3888,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3889,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,140600,75100,142000"
st "reset"
blo "71000,141800"
tm "WireNameMgr"
)
)
on &25
)
*654 (Wire
uid 3907,0
shape (OrthoPolyLine
uid 3908,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "123750,117000,131000,117000"
pts [
"123750,117000"
"131000,117000"
]
)
start &323
end &167
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3911,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3912,0
va (VaSet
font "Verdana,12,0"
)
xt "125750,115600,130250,117000"
st "memY"
blo "125750,116800"
tm "WireNameMgr"
)
)
on &171
)
*655 (Wire
uid 4047,0
shape (OrthoPolyLine
uid 4048,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "281000,6000,289000,6000"
pts [
"281000,6000"
"289000,6000"
]
)
start &174
end &172
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4051,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4052,0
va (VaSet
font "Verdana,12,0"
)
xt "284000,4600,289600,6000"
st "testOut"
blo "284000,5800"
tm "WireNameMgr"
)
)
on &173
)
*656 (Wire
uid 4274,0
shape (OrthoPolyLine
uid 4275,0
va (VaSet
vasetType 3
)
xt "23000,66000,26250,66000"
pts [
"23000,66000"
"26250,66000"
]
)
end &183
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4280,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4281,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,64600,27100,66000"
st "reset"
blo "23000,65800"
tm "WireNameMgr"
)
)
on &25
)
*657 (Wire
uid 4282,0
shape (OrthoPolyLine
uid 4283,0
va (VaSet
vasetType 3
)
xt "23000,64000,26250,64000"
pts [
"23000,64000"
"26250,64000"
]
)
end &182
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4288,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4289,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,62600,26800,64000"
st "clock"
blo "23000,63800"
tm "WireNameMgr"
)
)
on &15
)
*658 (Wire
uid 4292,0
shape (OrthoPolyLine
uid 4293,0
va (VaSet
vasetType 3
)
xt "43750,58000,47000,58000"
pts [
"43750,58000"
"47000,58000"
]
)
start &179
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4298,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4299,0
va (VaSet
font "Verdana,12,0"
)
xt "44000,56600,50700,58000"
st "wrHPulse"
blo "44000,57800"
tm "WireNameMgr"
)
)
on &187
)
*659 (Wire
uid 4329,0
shape (OrthoPolyLine
uid 4330,0
va (VaSet
vasetType 3
)
xt "23000,86000,26250,86000"
pts [
"23000,86000"
"26250,86000"
]
)
end &192
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4333,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4334,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,84600,26800,86000"
st "clock"
blo "23000,85800"
tm "WireNameMgr"
)
)
on &15
)
*660 (Wire
uid 4335,0
shape (OrthoPolyLine
uid 4336,0
va (VaSet
vasetType 3
)
xt "23000,88000,26250,88000"
pts [
"23000,88000"
"26250,88000"
]
)
end &193
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4339,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4340,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,86600,27100,88000"
st "reset"
blo "23000,87800"
tm "WireNameMgr"
)
)
on &25
)
*661 (Wire
uid 4341,0
shape (OrthoPolyLine
uid 4342,0
va (VaSet
vasetType 3
)
xt "43750,80000,47000,80000"
pts [
"43750,80000"
"47000,80000"
]
)
start &189
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4345,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4346,0
va (VaSet
font "Verdana,12,0"
)
xt "44000,78600,50500,80000"
st "wrLPulse"
blo "44000,79800"
tm "WireNameMgr"
)
)
on &197
)
*662 (Wire
uid 4349,0
shape (OrthoPolyLine
uid 4350,0
va (VaSet
vasetType 3
)
xt "19000,82000,26250,82000"
pts [
"19000,82000"
"26250,82000"
]
)
end &191
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4355,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4356,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,80600,21100,82000"
st "cs"
blo "19000,81800"
tm "WireNameMgr"
)
)
on &17
)
*663 (Wire
uid 4770,0
shape (OrthoPolyLine
uid 4771,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,84000,184250,84000"
pts [
"177750,84000"
"184250,84000"
]
)
start &207
end &223
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4775,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,82600,182700,84000"
st "phase"
blo "178000,83800"
tm "WireNameMgr"
)
)
on &202
)
*664 (Wire
uid 4782,0
shape (OrthoPolyLine
uid 4783,0
va (VaSet
vasetType 3
)
xt "157000,92000,160250,92000"
pts [
"157000,92000"
"160250,92000"
]
)
end &208
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4786,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4787,0
va (VaSet
font "Verdana,12,0"
)
xt "157000,90600,161100,92000"
st "reset"
blo "157000,91800"
tm "WireNameMgr"
)
)
on &25
)
*665 (Wire
uid 4788,0
shape (OrthoPolyLine
uid 4789,0
va (VaSet
vasetType 3
)
xt "157000,90000,160250,90000"
pts [
"157000,90000"
"160250,90000"
]
)
end &206
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4792,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4793,0
va (VaSet
font "Verdana,12,0"
)
xt "157000,88600,160800,90000"
st "clock"
blo "157000,89800"
tm "WireNameMgr"
)
)
on &15
)
*666 (Wire
uid 4794,0
shape (OrthoPolyLine
uid 4795,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "157000,78000,160250,84000"
pts [
"160250,84000"
"157000,84000"
"157000,78000"
]
)
start &209
end &198
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4798,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4799,0
va (VaSet
font "Verdana,12,0"
)
xt "157000,82600,160600,84000"
st "step"
blo "157000,83800"
tm "WireNameMgr"
)
)
on &203
)
*667 (Wire
uid 4860,0
shape (OrthoPolyLine
uid 4861,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "129000,84000,209000,115000"
pts [
"201750,84000"
"209000,84000"
"209000,98000"
"129000,98000"
"129000,115000"
"131000,115000"
]
)
start &222
end &167
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4864,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4865,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,82600,207150,84000"
st "sine"
blo "203750,83800"
tm "WireNameMgr"
)
)
on &204
)
*668 (Wire
uid 4866,0
shape (OrthoPolyLine
uid 4867,0
va (VaSet
vasetType 3
)
xt "153000,86000,160250,86000"
pts [
"153000,86000"
"160250,86000"
]
)
end &210
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4873,0
va (VaSet
font "Verdana,12,0"
)
xt "149000,84600,162900,86000"
st "interpolationEnable"
blo "149000,85800"
tm "WireNameMgr"
)
)
on &124
)
*669 (Wire
uid 5086,0
shape (OrthoPolyLine
uid 5087,0
va (VaSet
vasetType 3
)
xt "153000,70000,161000,70000"
pts [
"153000,70000"
"161000,70000"
]
)
start &214
end &215
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5090,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5091,0
va (VaSet
font "Verdana,12,0"
)
xt "153000,68600,159900,70000"
st "selSinCos"
blo "153000,69800"
tm "WireNameMgr"
)
)
on &232
)
*670 (Wire
uid 5253,0
shape (OrthoPolyLine
uid 5254,0
va (VaSet
vasetType 3
)
xt "177000,66000,185000,66000"
pts [
"177000,66000"
"185000,66000"
]
)
start &215
sat 2
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5259,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5260,0
va (VaSet
font "Verdana,12,0"
)
xt "179750,64600,193650,66000"
st "interpolationEnable"
blo "179750,65800"
tm "WireNameMgr"
)
)
on &124
)
*671 (Wire
uid 5263,0
shape (OrthoPolyLine
uid 5264,0
va (VaSet
vasetType 3
)
xt "152750,66000,161000,66000"
pts [
"152750,66000"
"161000,66000"
]
)
end &215
sat 16
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5269,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5270,0
va (VaSet
font "Verdana,12,0"
)
xt "150000,64600,161200,66000"
st "interpolationEn"
blo "150000,65800"
tm "WireNameMgr"
)
)
on &219
)
*672 (Wire
uid 5938,0
shape (OrthoPolyLine
uid 5939,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "127000,86000,207000,152000"
pts [
"201750,86000"
"207000,86000"
"207000,97000"
"127000,97000"
"127000,152000"
"131000,152000"
]
)
start &224
end &129
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5942,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5943,0
va (VaSet
font "Verdana,12,0"
)
xt "203750,84600,208550,86000"
st "cosine"
blo "203750,85800"
tm "WireNameMgr"
)
)
on &220
)
*673 (Wire
uid 7055,0
shape (OrthoPolyLine
uid 7056,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "19000,10000,26250,10000"
pts [
"26250,10000"
"19000,10000"
]
)
start &239
end &89
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7061,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7062,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,8600,24000,10000"
st "dataIn"
blo "19000,9800"
tm "WireNameMgr"
)
)
on &247
)
*674 (Wire
uid 7111,0
shape (OrthoPolyLine
uid 7112,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "23750,32000,26250,32000"
pts [
"23750,32000"
"26250,32000"
]
)
start &251
end &422
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 7113,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7114,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,30600,29100,32000"
st "addrReg"
blo "23000,31800"
tm "WireNameMgr"
)
s (Text
uid 7337,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,32000,23000,32000"
blo "23000,32000"
tm "SignalTypeMgr"
)
)
on &257
)
*675 (Wire
uid 7117,0
shape (OrthoPolyLine
uid 7118,0
va (VaSet
vasetType 3
)
xt "23000,18000,26250,18000"
pts [
"23000,18000"
"26250,18000"
]
)
end &242
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7123,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7124,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,16600,27100,18000"
st "reset"
blo "23000,17800"
tm "WireNameMgr"
)
)
on &25
)
*676 (Wire
uid 7125,0
shape (OrthoPolyLine
uid 7126,0
va (VaSet
vasetType 3
)
xt "23000,16000,26250,16000"
pts [
"23000,16000"
"26250,16000"
]
)
end &238
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7131,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7132,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,14600,26800,16000"
st "clock"
blo "23000,15800"
tm "WireNameMgr"
)
)
on &15
)
*677 (Wire
uid 7133,0
shape (OrthoPolyLine
uid 7134,0
va (VaSet
vasetType 3
)
xt "3000,40000,6250,40000"
pts [
"3000,40000"
"6250,40000"
]
)
end &253
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7139,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7140,0
va (VaSet
font "Verdana,12,0"
)
xt "3000,38600,7100,40000"
st "reset"
blo "3000,39800"
tm "WireNameMgr"
)
)
on &25
)
*678 (Wire
uid 7141,0
shape (OrthoPolyLine
uid 7142,0
va (VaSet
vasetType 3
)
xt "3000,38000,6250,38000"
pts [
"3000,38000"
"6250,38000"
]
)
end &249
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7147,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7148,0
va (VaSet
font "Verdana,12,0"
)
xt "3000,36600,6800,38000"
st "clock"
blo "3000,37800"
tm "WireNameMgr"
)
)
on &15
)
*679 (Wire
uid 7160,0
shape (OrthoPolyLine
uid 7161,0
va (VaSet
vasetType 3
)
xt "19000,14000,26250,14000"
pts [
"26250,14000"
"19000,14000"
]
)
start &241
end &258
sat 32
eat 2
stc 0
sf 1
si 0
tg (WTG
uid 7164,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7165,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,12600,27400,14000"
st "logic1"
blo "23000,13800"
tm "WireNameMgr"
)
s (Text
uid 7348,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,14000,23000,14000"
blo "23000,14000"
tm "SignalTypeMgr"
)
)
on &262
)
*680 (Wire
uid 7168,0
shape (OrthoPolyLine
uid 7169,0
va (VaSet
vasetType 3
)
xt "3000,36000,6250,36000"
pts [
"6250,36000"
"3000,36000"
]
)
start &252
sat 32
eat 16
stc 0
sf 1
si 0
tg (WTG
uid 7174,0
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7175,0
va (VaSet
font "Verdana,12,0"
)
xt "3000,34600,7400,36000"
st "logic1"
blo "3000,35800"
tm "WireNameMgr"
)
s (Text
uid 7176,0
va (VaSet
font "Verdana,12,0"
)
xt "3000,36000,3000,36000"
blo "3000,36000"
tm "SignalTypeMgr"
)
)
on &262
)
*681 (Wire
uid 7724,0
shape (OrthoPolyLine
uid 7725,0
va (VaSet
vasetType 3
)
xt "23000,116000,26250,116000"
pts [
"23000,116000"
"26250,116000"
]
)
end &268
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7730,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7731,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,114600,27100,116000"
st "reset"
blo "23000,115800"
tm "WireNameMgr"
)
)
on &25
)
*682 (Wire
uid 7732,0
shape (OrthoPolyLine
uid 7733,0
va (VaSet
vasetType 3
)
xt "23000,114000,26250,114000"
pts [
"23000,114000"
"26250,114000"
]
)
end &267
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7738,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7739,0
va (VaSet
font "Verdana,12,0"
)
xt "23000,112600,26800,114000"
st "clock"
blo "23000,113800"
tm "WireNameMgr"
)
)
on &15
)
*683 (Wire
uid 7740,0
shape (OrthoPolyLine
uid 7741,0
va (VaSet
vasetType 3
)
xt "19000,110000,26250,110000"
pts [
"19000,110000"
"26250,110000"
]
)
end &266
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7746,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7747,0
va (VaSet
font "Verdana,12,0"
)
xt "19000,108600,21100,110000"
st "cs"
blo "19000,109800"
tm "WireNameMgr"
)
)
on &17
)
*684 (Wire
uid 7748,0
shape (OrthoPolyLine
uid 7749,0
va (VaSet
vasetType 3
)
xt "43750,108000,47000,108000"
pts [
"43750,108000"
"47000,108000"
]
)
start &264
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7754,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7755,0
va (VaSet
font "Verdana,12,0"
)
xt "44000,106600,51400,108000"
st "wr16Pulse"
blo "44000,107800"
tm "WireNameMgr"
)
)
on &272
)
*685 (Wire
uid 7793,0
shape (OrthoPolyLine
uid 7794,0
va (VaSet
vasetType 3
)
xt "17950,108000,26250,108000"
pts [
"26250,108000"
"17950,108000"
]
)
start &265
end &276
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7795,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7796,0
va (VaSet
font "Verdana,12,0"
)
xt "20000,106600,24000,108000"
st "wr16"
blo "20000,107800"
tm "WireNameMgr"
)
)
on &280
)
*686 (Wire
uid 7801,0
shape (OrthoPolyLine
uid 7802,0
va (VaSet
vasetType 3
)
xt "7000,106000,11000,106000"
pts [
"7000,106000"
"11000,106000"
]
)
end &274
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7807,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7808,0
va (VaSet
font "Verdana,12,0"
)
xt "7000,104600,10300,106000"
st "wrH"
blo "7000,105800"
tm "WireNameMgr"
)
)
on &27
)
*687 (Wire
uid 7809,0
shape (OrthoPolyLine
uid 7810,0
va (VaSet
vasetType 3
)
xt "7000,110000,11000,110000"
pts [
"7000,110000"
"11000,110000"
]
)
end &275
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7815,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7816,0
va (VaSet
font "Verdana,12,0"
)
xt "7000,108600,10100,110000"
st "wrL"
blo "7000,109800"
tm "WireNameMgr"
)
)
on &29
)
*688 (Wire
uid 7907,0
shape (OrthoPolyLine
uid 7908,0
va (VaSet
vasetType 3
)
xt "67000,132000,74250,132000"
pts [
"67000,132000"
"74250,132000"
]
)
end &443
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7913,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7914,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,130600,74400,132000"
st "wr16Pulse"
blo "67000,131800"
tm "WireNameMgr"
)
)
on &272
)
*689 (Wire
uid 7915,0
shape (OrthoPolyLine
uid 7916,0
va (VaSet
vasetType 3
)
xt "67000,182000,74250,182000"
pts [
"67000,182000"
"74250,182000"
]
)
end &456
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7921,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7922,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,180600,74400,182000"
st "wr16Pulse"
blo "67000,181800"
tm "WireNameMgr"
)
)
on &272
)
*690 (Wire
uid 8150,0
shape (OrthoPolyLine
uid 8151,0
va (VaSet
vasetType 3
)
xt "91750,16000,99000,16000"
pts [
"91750,16000"
"99000,16000"
]
)
start &290
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8154,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8155,0
va (VaSet
font "Verdana,12,0"
)
xt "93750,14600,104050,16000"
st "interpolateLin"
blo "93750,15800"
tm "WireNameMgr"
)
)
on &393
)
*691 (Wire
uid 8248,0
optionalChildren [
*692 (BdJunction
uid 8258,0
ps "OnConnectorStrategy"
shape (Circle
uid 8259,0
va (VaSet
vasetType 1
)
xt "180600,124600,181400,125400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 8249,0
va (VaSet
vasetType 3
)
xt "177000,69000,184250,162000"
pts [
"184250,162000"
"181000,162000"
"181000,69000"
"177000,69000"
]
)
start &304
end &215
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8252,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8253,0
va (VaSet
font "Verdana,12,0"
)
xt "179000,67600,191400,69000"
st "interpolateLinear"
blo "179000,68800"
tm "WireNameMgr"
)
)
on &294
)
*693 (Wire
uid 8254,0
shape (OrthoPolyLine
uid 8255,0
va (VaSet
vasetType 3
)
xt "181000,125000,184250,125000"
pts [
"184250,125000"
"181000,125000"
]
)
start &317
end &692
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8256,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8257,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "171250,123600,183650,125000"
st "interpolateLinear"
blo "171250,124800"
tm "WireNameMgr"
)
)
on &294
)
*694 (Wire
uid 9246,0
shape (OrthoPolyLine
uid 9247,0
va (VaSet
vasetType 3
)
xt "139000,121000,139000,125000"
pts [
"139000,125000"
"139000,121000"
]
)
end &167
sat 16
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9252,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9253,0
va (VaSet
font "Verdana,12,0"
)
xt "139000,123600,145900,125000"
st "selSinCos"
blo "139000,124800"
tm "WireNameMgr"
)
)
on &232
)
*695 (Wire
uid 9254,0
shape (OrthoPolyLine
uid 9255,0
va (VaSet
vasetType 3
)
xt "139000,158000,139000,162000"
pts [
"139000,162000"
"139000,158000"
]
)
end &129
sat 16
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 9260,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 9261,0
va (VaSet
font "Verdana,12,0"
)
xt "139000,160600,145900,162000"
st "selSinCos"
blo "139000,161800"
tm "WireNameMgr"
)
)
on &232
)
*696 (Wire
uid 10531,0
shape (OrthoPolyLine
uid 10532,0
va (VaSet
vasetType 3
)
xt "91750,212000,106250,236000"
pts [
"91750,236000"
"101000,236000"
"101000,212000"
"106250,212000"
]
)
start &467
end &407
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10533,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10534,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,210600,106200,212000"
st "memEnZ"
blo "100000,211800"
tm "WireNameMgr"
)
)
on &419
)
*697 (Wire
uid 10535,0
shape (OrthoPolyLine
uid 10536,0
va (VaSet
vasetType 3
)
xt "91750,210000,106250,234000"
pts [
"91750,234000"
"99000,234000"
"99000,210000"
"106250,210000"
]
)
start &465
end &410
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10537,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10538,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,208600,106400,210000"
st "memWrZ"
blo "100000,209800"
tm "WireNameMgr"
)
)
on &418
)
*698 (Wire
uid 10539,0
shape (OrthoPolyLine
uid 10540,0
va (VaSet
vasetType 3
)
xt "71000,216000,74250,216000"
pts [
"71000,216000"
"74250,216000"
]
)
end &397
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10543,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10544,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,214600,75100,216000"
st "reset"
blo "71000,215800"
tm "WireNameMgr"
)
)
on &25
)
*699 (Wire
uid 10545,0
shape (OrthoPolyLine
uid 10546,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,206000,106250,206000"
pts [
"91750,206000"
"106250,206000"
]
)
start &399
end &411
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10547,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10548,0
va (VaSet
font "Verdana,12,0"
)
xt "102000,204600,106500,206000"
st "addrZ"
blo "102000,205800"
tm "WireNameMgr"
)
)
on &416
)
*700 (Wire
uid 10549,0
shape (OrthoPolyLine
uid 10550,0
va (VaSet
vasetType 3
)
xt "67000,234000,74250,234000"
pts [
"67000,234000"
"74250,234000"
]
)
end &468
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10553,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10554,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,232600,76800,234000"
st "updatePattern"
blo "66000,233800"
tm "WireNameMgr"
)
)
on &87
)
*701 (Wire
uid 10555,0
shape (OrthoPolyLine
uid 10556,0
va (VaSet
vasetType 3
)
xt "69000,210000,95000,230000"
pts [
"91750,230000"
"95000,230000"
"95000,224000"
"69000,224000"
"69000,210000"
"74250,210000"
]
)
start &470
end &395
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10557,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10558,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,208600,74900,210000"
st "cntIncrZ"
blo "69000,209800"
tm "WireNameMgr"
)
)
on &415
)
*702 (Wire
uid 10559,0
shape (OrthoPolyLine
uid 10560,0
va (VaSet
vasetType 3
)
xt "71000,214000,74250,214000"
pts [
"71000,214000"
"74250,214000"
]
)
end &396
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10563,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10564,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,212600,74800,214000"
st "clock"
blo "71000,213800"
tm "WireNameMgr"
)
)
on &15
)
*703 (Wire
uid 10565,0
shape (OrthoPolyLine
uid 10566,0
va (VaSet
vasetType 3
)
xt "67000,236000,74250,236000"
pts [
"74250,236000"
"67000,236000"
]
)
start &471
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10569,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10570,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,234600,75600,236000"
st "newPolynom"
blo "66000,235800"
tm "WireNameMgr"
)
)
on &30
)
*704 (Wire
uid 10571,0
shape (OrthoPolyLine
uid 10572,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "67000,206000,74250,206000"
pts [
"67000,206000"
"74250,206000"
]
)
end &400
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10575,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10576,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,204600,74900,206000"
st "patternSize"
blo "66000,205800"
tm "WireNameMgr"
)
)
on &88
)
*705 (Wire
uid 10577,0
shape (OrthoPolyLine
uid 10578,0
va (VaSet
vasetType 3
)
xt "67000,208000,74250,208000"
pts [
"67000,208000"
"74250,208000"
]
)
end &398
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10581,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10582,0
va (VaSet
font "Verdana,12,0"
)
xt "66000,206600,76800,208000"
st "updatePattern"
blo "66000,207800"
tm "WireNameMgr"
)
)
on &87
)
*706 (Wire
uid 10583,0
shape (OrthoPolyLine
uid 10584,0
va (VaSet
vasetType 3
)
xt "71000,240000,74250,240000"
pts [
"71000,240000"
"74250,240000"
]
)
end &472
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10587,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10588,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,238600,74800,240000"
st "clock"
blo "71000,239800"
tm "WireNameMgr"
)
)
on &15
)
*707 (Wire
uid 10589,0
shape (OrthoPolyLine
uid 10590,0
va (VaSet
vasetType 3
)
xt "71000,242000,74250,242000"
pts [
"71000,242000"
"74250,242000"
]
)
end &473
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10593,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10594,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,240600,75100,242000"
st "reset"
blo "71000,241800"
tm "WireNameMgr"
)
)
on &25
)
*708 (Wire
uid 10595,0
shape (OrthoPolyLine
uid 10596,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "123750,204000,131000,204000"
pts [
"123750,204000"
"131000,204000"
]
)
start &406
end &491
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10599,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10600,0
va (VaSet
font "Verdana,12,0"
)
xt "127000,202600,131600,204000"
st "memZ"
blo "127000,203800"
tm "WireNameMgr"
)
)
on &417
)
*709 (Wire
uid 10601,0
shape (OrthoPolyLine
uid 10602,0
va (VaSet
vasetType 3
)
xt "67000,232000,74250,232000"
pts [
"67000,232000"
"74250,232000"
]
)
end &469
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10605,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10606,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,230600,73500,232000"
st "wrLPulse"
blo "67000,231800"
tm "WireNameMgr"
)
)
on &197
)
*710 (Wire
uid 10617,0
shape (OrthoPolyLine
uid 10618,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "59000,200000,106250,204000"
pts [
"59000,200000"
"99000,200000"
"99000,204000"
"106250,204000"
]
)
start &601
end &405
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10619,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10620,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,202600,107400,204000"
st "dataInReg"
blo "100000,203800"
tm "WireNameMgr"
)
)
on &246
)
*711 (Wire
uid 10662,0
shape (OrthoPolyLine
uid 10663,0
va (VaSet
vasetType 3
)
xt "43750,42000,74250,230000"
pts [
"43750,42000"
"49000,42000"
"49000,230000"
"74250,230000"
]
)
start &427
end &466
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10664,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10665,0
va (VaSet
font "Verdana,12,0"
)
xt "67000,228600,70400,230000"
st "selZ"
blo "67000,229800"
tm "WireNameMgr"
)
)
on &431
)
*712 (Wire
uid 10884,0
shape (OrthoPolyLine
uid 10885,0
va (VaSet
vasetType 3
)
xt "201000,206000,209000,206000"
pts [
"201000,206000"
"209000,206000"
]
)
start &434
end &432
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10888,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10889,0
va (VaSet
font "Verdana,12,0"
)
xt "205000,204600,208700,206000"
st "outZ"
blo "205000,205800"
tm "WireNameMgr"
)
)
on &433
)
*713 (Wire
uid 10901,0
shape (OrthoPolyLine
uid 10902,0
va (VaSet
vasetType 3
)
xt "103000,218000,106250,218000"
pts [
"103000,218000"
"106250,218000"
]
)
end &409
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10907,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10908,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,216600,107100,218000"
st "reset"
blo "103000,217800"
tm "WireNameMgr"
)
)
on &25
)
*714 (Wire
uid 10909,0
shape (OrthoPolyLine
uid 10910,0
va (VaSet
vasetType 3
)
xt "103000,216000,106250,216000"
pts [
"103000,216000"
"106250,216000"
]
)
end &408
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 10915,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 10916,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,214600,106800,216000"
st "clock"
blo "103000,215800"
tm "WireNameMgr"
)
)
on &15
)
*715 (Wire
uid 11529,0
shape (OrthoPolyLine
uid 11530,0
va (VaSet
vasetType 3
)
xt "157000,210000,160250,210000"
pts [
"157000,210000"
"160250,210000"
]
)
end &478
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11535,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11536,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,208600,159800,210000"
st "clock"
blo "156000,209800"
tm "WireNameMgr"
)
)
on &15
)
*716 (Wire
uid 11537,0
shape (OrthoPolyLine
uid 11538,0
va (VaSet
vasetType 3
)
xt "157000,212000,160250,212000"
pts [
"157000,212000"
"160250,212000"
]
)
end &479
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11543,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11544,0
va (VaSet
font "Verdana,12,0"
)
xt "156000,210600,160100,212000"
st "reset"
blo "156000,211800"
tm "WireNameMgr"
)
)
on &25
)
*717 (Wire
uid 11545,0
shape (OrthoPolyLine
uid 11546,0
va (VaSet
vasetType 3
)
xt "153000,169000,160250,206000"
pts [
"153000,169000"
"153000,206000"
"160250,206000"
]
)
start &541
end &480
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11547,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11548,0
va (VaSet
font "Verdana,12,0"
)
xt "153000,204600,162600,206000"
st "newPolynom"
blo "153000,205800"
tm "WireNameMgr"
)
)
on &30
)
*718 (Wire
uid 11553,0
shape (OrthoPolyLine
uid 11554,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,204000,185000,204000"
pts [
"177750,204000"
"185000,204000"
]
)
start &482
end &434
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11557,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11558,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,202600,184900,204000"
st "sampleZ1"
blo "178000,203800"
tm "WireNameMgr"
)
)
on &489
)
*719 (Wire
uid 11561,0
shape (OrthoPolyLine
uid 11562,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "177750,206000,185000,206000"
pts [
"177750,206000"
"185000,206000"
]
)
start &483
end &434
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11565,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11566,0
va (VaSet
font "Verdana,12,0"
)
xt "178000,204600,184900,206000"
st "sampleZ2"
blo "178000,205800"
tm "WireNameMgr"
)
)
on &490
)
*720 (Wire
uid 11582,0
shape (OrthoPolyLine
uid 11583,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "147000,204000,160250,204000"
pts [
"160250,204000"
"147000,204000"
]
)
start &481
end &491
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11586,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11587,0
va (VaSet
font "Verdana,12,0"
)
xt "149000,202600,155800,204000"
st "samplesZ"
blo "149000,203800"
tm "WireNameMgr"
)
)
on &495
)
*721 (Wire
uid 11590,0
shape (OrthoPolyLine
uid 11591,0
va (VaSet
vasetType 3
)
xt "139000,208000,139000,212000"
pts [
"139000,212000"
"139000,208000"
]
)
end &491
sat 16
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11596,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11597,0
va (VaSet
font "Verdana,12,0"
)
xt "139000,210600,145900,212000"
st "selSinCos"
blo "139000,211800"
tm "WireNameMgr"
)
)
on &232
)
*722 (Wire
uid 11911,0
shape (OrthoPolyLine
uid 11912,0
va (VaSet
vasetType 3
)
xt "261000,89000,264250,89000"
pts [
"261000,89000"
"264250,89000"
]
)
end &501
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11917,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11918,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,87600,264100,89000"
st "reset"
blo "260000,88800"
tm "WireNameMgr"
)
)
on &25
)
*723 (Wire
uid 11919,0
shape (OrthoPolyLine
uid 11920,0
va (VaSet
vasetType 3
)
xt "261000,87000,264250,87000"
pts [
"261000,87000"
"264250,87000"
]
)
end &498
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11926,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,85600,263800,87000"
st "clock"
blo "260000,86800"
tm "WireNameMgr"
)
)
on &15
)
*724 (Wire
uid 11927,0
shape (OrthoPolyLine
uid 11928,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "257000,81000,264250,81000"
pts [
"257000,81000"
"264250,81000"
]
)
end &502
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11933,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11934,0
va (VaSet
font "Verdana,12,0"
)
xt "258000,79600,265400,81000"
st "unsignedX"
blo "258000,80800"
tm "WireNameMgr"
)
)
on &46
)
*725 (Wire
uid 11935,0
shape (OrthoPolyLine
uid 11936,0
va (VaSet
vasetType 3
)
xt "257000,83000,264250,83000"
pts [
"257000,83000"
"264250,83000"
]
)
end &500
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11941,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11942,0
va (VaSet
font "Verdana,12,0"
)
xt "252000,81600,265900,83000"
st "interpolationEnable"
blo "252000,82800"
tm "WireNameMgr"
)
)
on &124
)
*726 (Wire
uid 11980,0
shape (OrthoPolyLine
uid 11981,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "257000,59000,264250,59000"
pts [
"257000,59000"
"264250,59000"
]
)
end &513
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11984,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11985,0
va (VaSet
font "Verdana,12,0"
)
xt "258000,57600,265300,59000"
st "unsignedY"
blo "258000,58800"
tm "WireNameMgr"
)
)
on &80
)
*727 (Wire
uid 11986,0
shape (OrthoPolyLine
uid 11987,0
va (VaSet
vasetType 3
)
xt "257000,61000,264250,61000"
pts [
"257000,61000"
"264250,61000"
]
)
end &511
es 0
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11990,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11991,0
va (VaSet
font "Verdana,12,0"
)
xt "252000,59600,265900,61000"
st "interpolationEnable"
blo "252000,60800"
tm "WireNameMgr"
)
)
on &124
)
*728 (Wire
uid 11992,0
shape (OrthoPolyLine
uid 11993,0
va (VaSet
vasetType 3
)
xt "261000,65000,264250,65000"
pts [
"261000,65000"
"264250,65000"
]
)
end &509
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 11998,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 11999,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,63600,263800,65000"
st "clock"
blo "260000,64800"
tm "WireNameMgr"
)
)
on &15
)
*729 (Wire
uid 12000,0
shape (OrthoPolyLine
uid 12001,0
va (VaSet
vasetType 3
)
xt "261000,67000,264250,67000"
pts [
"261000,67000"
"264250,67000"
]
)
end &512
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12006,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12007,0
va (VaSet
font "Verdana,12,0"
)
xt "260000,65600,264100,67000"
st "reset"
blo "260000,66800"
tm "WireNameMgr"
)
)
on &25
)
*730 (Wire
uid 12056,0
shape (OrthoPolyLine
uid 12057,0
va (VaSet
vasetType 3
)
xt "281750,85000,289000,85000"
pts [
"281750,85000"
"289000,85000"
]
)
start &497
end &518
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12060,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12061,0
va (VaSet
font "Verdana,12,0"
)
xt "285000,83600,289800,85000"
st "CLK_X"
blo "285000,84800"
tm "WireNameMgr"
)
)
on &519
)
*731 (Wire
uid 12070,0
shape (OrthoPolyLine
uid 12071,0
va (VaSet
vasetType 3
)
xt "281750,63000,289000,63000"
pts [
"281750,63000"
"289000,63000"
]
)
start &508
end &520
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12074,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12075,0
va (VaSet
font "Verdana,12,0"
)
xt "285000,61600,289700,63000"
st "CLK_Y"
blo "285000,62800"
tm "WireNameMgr"
)
)
on &521
)
*732 (Wire
uid 12084,0
shape (OrthoPolyLine
uid 12085,0
va (VaSet
vasetType 3
)
xt "281750,81000,289000,81000"
pts [
"281750,81000"
"289000,81000"
]
)
start &499
end &522
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12088,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12089,0
va (VaSet
font "Verdana,12,0"
)
xt "284000,79600,289700,81000"
st "CS_X_n"
blo "284000,80800"
tm "WireNameMgr"
)
)
on &523
)
*733 (Wire
uid 12098,0
shape (OrthoPolyLine
uid 12099,0
va (VaSet
vasetType 3
)
xt "281750,59000,289000,59000"
pts [
"281750,59000"
"289000,59000"
]
)
start &510
end &524
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12102,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12103,0
va (VaSet
font "Verdana,12,0"
)
xt "284000,57600,289600,59000"
st "CS_Y_n"
blo "284000,58800"
tm "WireNameMgr"
)
)
on &525
)
*734 (Wire
uid 12112,0
shape (OrthoPolyLine
uid 12113,0
va (VaSet
vasetType 3
)
xt "281750,83000,289000,83000"
pts [
"281750,83000"
"289000,83000"
]
)
start &503
end &526
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12116,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12117,0
va (VaSet
font "Verdana,12,0"
)
xt "285000,81600,289600,83000"
st "SDI_X"
blo "285000,82800"
tm "WireNameMgr"
)
)
on &527
)
*735 (Wire
uid 12126,0
shape (OrthoPolyLine
uid 12127,0
va (VaSet
vasetType 3
)
xt "281750,61000,289000,61000"
pts [
"281750,61000"
"289000,61000"
]
)
start &514
end &528
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12130,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12131,0
va (VaSet
font "Verdana,12,0"
)
xt "285000,59600,289500,61000"
st "SDI_Y"
blo "285000,60800"
tm "WireNameMgr"
)
)
on &529
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *736 (PackageList
uid 42,0
stg "VerticalLayoutStrategy"
textVec [
*737 (Text
uid 43,0
va (VaSet
font "Verdana,8,1"
)
xt "0,0,6900,1000"
st "Package List"
blo "0,800"
)
*738 (MLText
uid 44,0
va (VaSet
)
xt "0,1000,17500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 45,0
stg "VerticalLayoutStrategy"
textVec [
*739 (Text
uid 46,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30200,1000"
st "Compiler Directives"
blo "20000,800"
)
*740 (Text
uid 47,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,32200,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*741 (MLText
uid 48,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*742 (Text
uid 49,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32800,5000"
st "Post-module directives:"
blo "20000,4800"
)
*743 (MLText
uid 50,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*744 (Text
uid 51,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,32400,6000"
st "End-module directives:"
blo "20000,5800"
)
*745 (MLText
uid 52,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-4267,-4267,465287,250854"
cachedDiagramExtent "-24700,0,305600,246800"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
xMargin 47
yMargin 47
paperWidth 761
paperHeight 1077
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4 (210 x 297 mm)"
windowsPaperName "A4 (210 x 297 mm)"
windowsPaperType 9
scale 50
useAdjustTo 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 13426,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
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st "
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tm "RequirementText"
wrapOption 3
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xt "0,0,20000,20000"
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st "Panel0"
blo "1000,2000"
tm "PanelText"
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tm "BdLibraryNameMgr"
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tm "HdlTextNumberMgr"
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tm "HdlTextMgr"
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tm "WireNameMgr"
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tg (WTG
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tm "WireNameMgr"
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defaultPortIoBuffer (PortIoBuffer
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tm "WireNameMgr"
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defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
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ss 0
es 0
sat 32
eat 32
stc 0
st 0
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si 0
tg (WTG
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va (VaSet
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tm "WireNameMgr"
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)
)
defaultBus (Wire
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va (VaSet
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)
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)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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tm "WireNameMgr"
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defaultBundle (Bundle
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lineWidth 1
)
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ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
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stg "VerticalLayoutStrategy"
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blo "0,800"
tm "BundleNameMgr"
)
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tm "BundleContentsMgr"
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shape (RectFrame
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lineColor "0,0,50000"
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xt "0,0,10000,12000"
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portMapText (BiTextGroup
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tm "PortMapTextMgr"
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)
)
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lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
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xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
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)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
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fg "65535,65535,65535"
)
xt "50,50,1050,1450"
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num (Text
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xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
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decls (MlTextGroup
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stg "VerticalLayoutStrategy"
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xt "14100,20000,22000,21000"
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)
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tm "BdFrameDeclTextMgr"
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)
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shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
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)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
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xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
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stg "VerticalLayoutStrategy"
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xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*766 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
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va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
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)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "212000,400,219000,1400"
st "Declarations"
blo "212000,1200"
)
portLabel (Text
uid 3,0
va (VaSet
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xt "212000,1300,215400,2300"
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blo "212000,2100"
)
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uid 4,0
va (VaSet
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xt "212000,20200,216800,21200"
st "Pre User:"
blo "212000,21000"
)
preUserText (MLText
uid 5,0
va (VaSet
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)
xt "214000,21100,248100,28100"
st "constant signalBitNb: positive := 16;
constant coeffBitNb : positive := signalBitNb+3;
constant sampleCountBitNb : positive := 8;
constant patternAddressBitNb : positive := 8;
-- sinewave generator
constant tableAddressBitNb : positive := 3;
constant phaseBitNb : positive := sampleCountBitNb + tableAddressBitNb + 2;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
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)
xt "212000,27400,221000,28400"
st "Diagram Signals:"
blo "212000,28200"
)
postUserLabel (Text
uid 7,0
va (VaSet
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font "Verdana,8,1"
)
xt "212000,400,218000,1400"
st "Post User:"
blo "212000,1200"
)
postUserText (MLText
uid 8,0
va (VaSet
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font "Verdana,8,0"
)
xt "212000,400,212000,400"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
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suid 86,0
usingSuid 1
emptyRow *767 (LEmptyRow
)
uid 12307,0
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)
*769 (TitleRowHdr
)
*770 (FilterRowHdr
)
*771 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*772 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*773 (GroupColHdr
tm "GroupColHdrMgr"
)
*774 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*775 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*776 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*777 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*778 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
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*779 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
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t "unsigned"
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o 2
suid 1,0
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)
uid 12134,0
)
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decl (Decl
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o 3
suid 2,0
)
)
uid 12136,0
)
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decl (Decl
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suid 3,0
)
)
uid 12138,0
)
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m 1
decl (Decl
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o 1
suid 4,0
)
)
uid 12140,0
)
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decl (Decl
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suid 5,0
)
)
uid 12142,0
)
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o 7
suid 6,0
)
)
uid 12144,0
)
*786 (LeafLogPort
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o 4
suid 7,0
)
)
uid 12146,0
)
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o 8
suid 8,0
)
)
uid 12148,0
)
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decl (Decl
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o 10
suid 9,0
)
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)
*789 (LeafLogPort
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m 4
decl (Decl
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o 52
suid 10,0
)
)
uid 12152,0
)
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port (LogicalPort
m 4
decl (Decl
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b "(signalBitNb-1 DOWNTO 0)"
o 56
suid 11,0
)
)
uid 12154,0
)
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m 4
decl (Decl
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t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 79
suid 12,0
)
)
uid 12156,0
)
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m 4
decl (Decl
n "samplesX"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 68
suid 13,0
)
)
uid 12158,0
)
*793 (LeafLogPort
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m 4
decl (Decl
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o 57
suid 14,0
)
)
uid 12160,0
)
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o 58
suid 15,0
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)
uid 12162,0
)
*795 (LeafLogPort
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o 59
suid 16,0
)
)
uid 12164,0
)
*796 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "sampleX4"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 60
suid 17,0
)
)
uid 12166,0
)
*797 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "aX"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 21
suid 18,0
)
)
uid 12168,0
)
*798 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "bX"
t "signed"
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o 27
suid 19,0
)
)
uid 12170,0
)
*799 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "cX"
t "signed"
b "(coeffBitNb-1 DOWNTO 0)"
o 29
suid 20,0
)
)
uid 12172,0
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*800 (LeafLogPort
port (LogicalPort
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decl (Decl
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b "(coeffBitNb-1 DOWNTO 0)"
o 35
suid 21,0
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)
uid 12174,0
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m 4
decl (Decl
n "samplesY"
t "signed"
b "(signalBitNb-1 DOWNTO 0)"
o 69
suid 22,0
)
)
uid 12176,0
)
*802 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
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o 62
suid 23,0
)
)
uid 12178,0
)
*803 (LeafLogPort
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m 4
decl (Decl
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o 63
suid 24,0
)
)
uid 12180,0
)
*804 (LeafLogPort
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m 4
decl (Decl
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o 64
suid 25,0
)
)
uid 12182,0
)
*805 (LeafLogPort
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m 4
decl (Decl
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o 65
suid 26,0
)
)
uid 12184,0
)
*806 (LeafLogPort
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m 4
decl (Decl
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suid 27,0
)
)
uid 12186,0
)
*807 (LeafLogPort
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m 4
decl (Decl
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suid 28,0
)
)
uid 12188,0
)
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m 4
decl (Decl
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suid 29,0
)
)
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decl (Decl
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)
)
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suid 31,0
)
)
uid 12194,0
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*811 (LeafLogPort
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m 4
decl (Decl
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)
)
uid 12196,0
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*812 (LeafLogPort
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decl (Decl
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o 71
suid 33,0
)
)
uid 12198,0
)
*813 (LeafLogPort
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m 4
decl (Decl
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o 72
suid 34,0
)
)
uid 12200,0
)
*814 (LeafLogPort
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m 4
decl (Decl
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o 73
suid 35,0
)
)
uid 12202,0
)
*815 (LeafLogPort
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decl (Decl
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o 74
suid 36,0
)
)
uid 12204,0
)
*816 (LeafLogPort
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m 4
decl (Decl
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o 75
suid 37,0
)
)
uid 12206,0
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*817 (LeafLogPort
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m 4
decl (Decl
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suid 38,0
)
)
uid 12208,0
)
*818 (LeafLogPort
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m 4
decl (Decl
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suid 39,0
)
)
uid 12210,0
)
*819 (LeafLogPort
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m 4
decl (Decl
n "patternSize"
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o 53
suid 40,0
)
)
uid 12212,0
)
*820 (LeafLogPort
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m 1
decl (Decl
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suid 41,0
)
)
uid 12214,0
)
*821 (LeafLogPort
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m 4
decl (Decl
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o 82
suid 42,0
)
)
uid 12216,0
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*822 (LeafLogPort
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m 4
decl (Decl
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o 41
suid 43,0
)
)
uid 12218,0
)
*823 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
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suid 44,0
)
)
uid 12220,0
)
*824 (LeafLogPort
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m 4
decl (Decl
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o 31
suid 45,0
)
)
uid 12222,0
)
*825 (LeafLogPort
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decl (Decl
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o 46
suid 46,0
)
)
uid 12224,0
)
*826 (LeafLogPort
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m 4
decl (Decl
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o 43
suid 47,0
)
)
uid 12226,0
)
*827 (LeafLogPort
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m 4
decl (Decl
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suid 48,0
)
)
uid 12228,0
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*828 (LeafLogPort
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suid 49,0
)
)
uid 12230,0
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*829 (LeafLogPort
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suid 50,0
)
)
uid 12232,0
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suid 51,0
)
)
uid 12234,0
)
*831 (LeafLogPort
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suid 52,0
)
)
uid 12236,0
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*832 (LeafLogPort
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suid 53,0
)
)
uid 12238,0
)
*833 (LeafLogPort
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decl (Decl
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)
)
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*834 (LeafLogPort
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suid 55,0
)
)
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*835 (LeafLogPort
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suid 56,0
)
)
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*836 (LeafLogPort
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suid 57,0
)
)
uid 12246,0
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*837 (LeafLogPort
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suid 58,0
)
)
uid 12248,0
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suid 59,0
)
)
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suid 60,0
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*840 (LeafLogPort
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suid 61,0
)
)
uid 12254,0
)
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)
)
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*842 (LeafLogPort
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*843 (LeafLogPort
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*844 (LeafLogPort
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suid 65,0
)
)
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*845 (LeafLogPort
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suid 66,0
)
)
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*846 (LeafLogPort
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suid 67,0
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)
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*848 (LeafLogPort
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suid 69,0
)
)
uid 12270,0
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*849 (LeafLogPort
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suid 70,0
)
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*856 (LeafLogPort
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)
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uid 12286,0
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*857 (LeafLogPort
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)
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uid 12292,0
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*860 (LeafLogPort
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)
)
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*861 (LeafLogPort
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*862 (LeafLogPort
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*864 (LeafLogPort
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*865 (LeafLogPort
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uid 12327,0
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*958 (MRCItem
litem &773
pos 1
dimension 50
uid 12328,0
)
*959 (MRCItem
litem &774
pos 2
dimension 100
uid 12329,0
)
*960 (MRCItem
litem &775
pos 3
dimension 50
uid 12330,0
)
*961 (MRCItem
litem &776
pos 4
dimension 100
uid 12331,0
)
*962 (MRCItem
litem &777
pos 5
dimension 100
uid 12332,0
)
*963 (MRCItem
litem &778
pos 6
dimension 50
uid 12333,0
)
*964 (MRCItem
litem &779
pos 7
dimension 80
uid 12334,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 12321,0
vaOverrides [
]
)
]
)
uid 12306,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *965 (LEmptyRow
)
uid 12336,0
optionalChildren [
*966 (RefLabelRowHdr
)
*967 (TitleRowHdr
)
*968 (FilterRowHdr
)
*969 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*970 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*971 (GroupColHdr
tm "GroupColHdrMgr"
)
*972 (NameColHdr
tm "GenericNameColHdrMgr"
)
*973 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*974 (InitColHdr
tm "GenericValueColHdrMgr"
)
*975 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*976 (EolColHdr
tm "GenericEolColHdrMgr"
)
*977 (LogGeneric
generic (GiElement
name "dataBitNb"
type "positive"
value "16"
)
uid 12611,0
)
*978 (LogGeneric
generic (GiElement
name "addressBitNb"
type "positive"
value "24"
)
uid 12613,0
)
]
)
pdm (PhysicalDM
uid 12348,0
optionalChildren [
*979 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *980 (MRCItem
litem &965
pos 2
dimension 20
)
uid 12350,0
optionalChildren [
*981 (MRCItem
litem &966
pos 0
dimension 20
uid 12351,0
)
*982 (MRCItem
litem &967
pos 1
dimension 23
uid 12352,0
)
*983 (MRCItem
litem &968
pos 2
hidden 1
dimension 20
uid 12353,0
)
*984 (MRCItem
litem &977
pos 0
dimension 20
uid 12610,0
)
*985 (MRCItem
litem &978
pos 1
dimension 20
uid 12612,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 12354,0
optionalChildren [
*986 (MRCItem
litem &969
pos 0
dimension 20
uid 12355,0
)
*987 (MRCItem
litem &971
pos 1
dimension 50
uid 12356,0
)
*988 (MRCItem
litem &972
pos 2
dimension 100
uid 12357,0
)
*989 (MRCItem
litem &973
pos 3
dimension 100
uid 12358,0
)
*990 (MRCItem
litem &974
pos 4
dimension 50
uid 12359,0
)
*991 (MRCItem
litem &975
pos 5
dimension 50
uid 12360,0
)
*992 (MRCItem
litem &976
pos 6
dimension 80
uid 12361,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 12349,0
vaOverrides [
]
)
]
)
uid 12335,0
type 1
)
activeModelName "BlockDiag"
)