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suid 53,0
)
declText (MLText
uid 3914,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,103000,29700,104000"
st "memY               : std_ulogic_vector(signalBitNb-1 DOWNTO 0)"
)
)
*34 (PortIoOut
uid 4041,0
shape (CompositeShape
uid 4042,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4043,0
sl 0
ro 270
xt "143500,3625,145000,4375"
)
(Line
uid 4044,0
sl 0
ro 270
xt "143000,4000,143500,4000"
pts [
"143000,4000"
"143500,4000"
]
)
]
)
tg (WTG
uid 4045,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4046,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "146000,3300,166900,4700"
st "testOut : (1 TO testOutBitNb)"
blo "146000,4500"
tm "WireNameMgr"
)
)
)
*35 (Net
uid 4053,0
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 1
suid 54,0
)
declText (MLText
uid 4054,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,101200,26200,102200"
st "testOut            : std_ulogic_vector(1 TO testOutBitNb)"
)
)
*36 (HdlText
uid 4055,0
optionalChildren [
*37 (EmbeddedText
uid 4060,0
commentText (CommentText
uid 4061,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 4062,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "120000,3000,134000,25000"
)
oxt "0,0,18000,5000"
text (MLText
uid 4063,0
va (VaSet
)
xt "120200,3200,133900,24800"
st "
testout( 1) <= run_int; run <= run_int;
testout( 2) <= updatePattern;
testout( 3) <= interpolateLin_int; interpolateLin <= interpolateLin_int;
testout( 4) <= newPolynom;
testout( 5) <= newPolynom;
testout( 6) <= '0';
testout( 7) <= '0';
testout( 8) <= selControl;
testout( 9) <= selSpeed;
testout(10) <= selX;
testout(11) <= selY;
testout(12) <= '0';
testout(13) <= addr(0);
testout(14) <= addr(1);
testout(15) <= dataIn(0);
testout(16) <= dataIn(1);

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 22000
visibleWidth 14000
)
)
)
]
shape (Rectangle
uid 4056,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "119000,2000,135000,26000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4057,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*38 (Text
uid 4058,0
va (VaSet
)
xt "119400,26000,122000,27200"
st "eb3"
blo "119400,27000"
tm "HdlTextNameMgr"
)
*39 (Text
uid 4059,0
va (VaSet
)
xt "119400,27000,120800,28200"
st "3"
blo "119400,28000"
tm "HdlTextNumberMgr"
)
]
)
)
*40 (Net
uid 9646,0
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 6
suid 70,0
)
declText (MLText
uid 9647,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,105700,15100,106700"
st "interpolateLin     : std_ulogic"
)
)
*41 (PortIoOut
uid 14845,0
shape (CompositeShape
uid 14846,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14847,0
sl 0
ro 270
xt "134500,115625,136000,116375"
)
(Line
uid 14848,0
sl 0
ro 270
xt "134000,116000,134500,116000"
pts [
"134000,116000"
"134500,116000"
]
)
]
)
tg (WTG
uid 14849,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14850,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "137000,115300,161100,116700"
st "memY : (signalBitNb-1 DOWNTO 0)"
blo "137000,116500"
tm "WireNameMgr"
)
)
)
*42 (PortIoOut
uid 14851,0
shape (CompositeShape
uid 14852,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14853,0
sl 0
ro 270
xt "134500,153625,136000,154375"
)
(Line
uid 14854,0
sl 0
ro 270
xt "134000,154000,134500,154000"
pts [
"134000,154000"
"134500,154000"
]
)
]
)
tg (WTG
uid 14855,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14856,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "137000,153300,161200,154700"
st "memX : (signalBitNb-1 DOWNTO 0)"
blo "137000,154500"
tm "WireNameMgr"
)
)
)
*43 (PortIoOut
uid 14857,0
shape (CompositeShape
uid 14858,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14859,0
sl 0
ro 270
xt "109750,41625,111250,42375"
)
(Line
uid 14860,0
sl 0
ro 270
xt "109250,42000,109750,42000"
pts [
"109250,42000"
"109750,42000"
]
)
]
)
tg (WTG
uid 14861,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14862,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "112000,41300,114900,42700"
st "run"
blo "112000,42500"
tm "WireNameMgr"
)
)
)
*44 (PortIoOut
uid 14863,0
shape (CompositeShape
uid 14864,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14865,0
sl 0
ro 270
xt "109750,69625,111250,70375"
)
(Line
uid 14866,0
sl 0
ro 270
xt "109250,70000,109750,70000"
pts [
"109250,70000"
"109750,70000"
]
)
]
)
tg (WTG
uid 14867,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14868,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "112000,69300,146500,70700"
st "updatePeriod : (updatePeriodBitNb-1 DOWNTO 0)"
blo "112000,70500"
tm "WireNameMgr"
)
)
)
*45 (PortIoOut
uid 14869,0
shape (CompositeShape
uid 14870,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 14871,0
sl 0
ro 270
xt "109500,43625,111000,44375"
)
(Line
uid 14872,0
sl 0
ro 270
xt "109000,44000,109500,44000"
pts [
"109000,44000"
"109500,44000"
]
)
]
)
tg (WTG
uid 14873,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 14874,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "112000,43300,122300,44700"
st "interpolateLin"
blo "112000,44500"
tm "WireNameMgr"
)
)
)
*46 (Net
uid 16705,0
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 25
suid 74,0
)
declText (MLText
uid 16706,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,126400,31800,127400"
st "SIGNAL dataIn             : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*47 (HdlText
uid 16707,0
optionalChildren [
*48 (EmbeddedText
uid 16712,0
commentText (CommentText
uid 16713,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 16714,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "30000,39000,46000,53000"
)
oxt "0,0,18000,5000"
text (MLText
uid 16715,0
va (VaSet
)
xt "30200,39200,45400,52400"
st "
storeControls: process(reset, clock)
begin
  if reset = '1' then
    addr <= (others => '0');
    write <= '0';
  elsif rising_edge(clock) then
    write <= '0';
    if (hSel = '1') and (hTrans = transNonSeq) then
      addr <= hAddr(addr'range);
      write <= hWrite;
    end if;
  end if;
end process storeControls;

dataIn <= hWData;

"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 14000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 16708,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "30000,38000,46000,54000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 16709,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*49 (Text
uid 16710,0
va (VaSet
)
xt "30400,54000,33000,55200"
st "eb8"
blo "30400,55000"
tm "HdlTextNameMgr"
)
*50 (Text
uid 16711,0
va (VaSet
)
xt "30400,55000,31800,56200"
st "8"
blo "30400,56000"
tm "HdlTextNumberMgr"
)
]
)
)
*51 (Net
uid 16716,0
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 20
suid 75,0
)
declText (MLText
uid 16717,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,121900,29500,122900"
st "SIGNAL addr               : unsigned(addressBitNb-1 DOWNTO 0)"
)
)
*52 (HdlText
uid 17145,0
optionalChildren [
*53 (EmbeddedText
uid 17150,0
commentText (CommentText
uid 17151,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 17152,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "58000,87000,66000,93000"
)
oxt "0,0,18000,5000"
text (MLText
uid 17153,0
va (VaSet
)
xt "58200,87200,65800,92000"
st "
memDataIn <= dataIn(memDataIn'range);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 6000
visibleWidth 8000
)
)
)
]
shape (Rectangle
uid 17146,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "58000,86000,66000,94000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 17147,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*54 (Text
uid 17148,0
va (VaSet
)
xt "58400,94000,61000,95200"
st "eb9"
blo "58400,95000"
tm "HdlTextNameMgr"
)
*55 (Text
uid 17149,0
va (VaSet
)
xt "58400,95000,59800,96200"
st "9"
blo "58400,96000"
tm "HdlTextNumberMgr"
)
]
)
)
*56 (Net
uid 17162,0
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 38
suid 77,0
)
declText (MLText
uid 17163,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,138100,33600,139100"
st "SIGNAL memDataIn          : std_ulogic_vector(signalBitNb-1 DOWNTO 0)"
)
)
*57 (Net
uid 17505,0
decl (Decl
n "write"
t "std_ulogic"
o 37
suid 78,0
)
declText (MLText
uid 17506,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,137200,17600,138200"
st "SIGNAL write              : std_ulogic"
)
)
*58 (HdlText
uid 17860,0
optionalChildren [
*59 (EmbeddedText
uid 17865,0
commentText (CommentText
uid 17866,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 17867,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "30000,19000,46000,29000"
)
oxt "0,0,18000,5000"
text (MLText
uid 17868,0
va (VaSet
)
xt "30200,19200,46200,27600"
st "
hRData <= std_ulogic_vector(dataOut);

hReady <= '1';  -- no wait state
hResp  <= '0';  -- data OK
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 17861,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "30000,18000,46000,30000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 17862,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*60 (Text
uid 17863,0
va (VaSet
)
xt "30400,30000,33700,31200"
st "eb10"
blo "30400,31000"
tm "HdlTextNameMgr"
)
*61 (Text
uid 17864,0
va (VaSet
)
xt "30400,31000,32500,32200"
st "10"
blo "30400,32000"
tm "HdlTextNumberMgr"
)
]
)
)
*62 (PortIoIn
uid 18266,0
shape (CompositeShape
uid 18267,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 18268,0
sl 0
ro 270
xt "68000,135625,69500,136375"
)
(Line
uid 18269,0
sl 0
ro 270
xt "69500,136000,70000,136000"
pts [
"69500,136000"
"70000,136000"
]
)
]
)
tg (WTG
uid 18270,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18271,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "57400,135300,67000,136700"
st "newPolynom"
ju 2
blo "67000,136500"
tm "WireNameMgr"
)
)
)
*63 (PortIoIn
uid 19642,0
shape (CompositeShape
uid 19643,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19644,0
sl 0
ro 270
xt "20000,3625,21500,4375"
)
(Line
uid 19645,0
sl 0
ro 270
xt "21500,4000,22000,4000"
pts [
"21500,4000"
"22000,4000"
]
)
]
)
tg (WTG
uid 19646,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19647,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "15500,3500,19000,4900"
st "hClk"
ju 2
blo "19000,4700"
tm "WireNameMgr"
)
)
)
*64 (Net
uid 19654,0
decl (Decl
n "hClk"
t "std_ulogic"
o 8
suid 79,0
)
declText (MLText
uid 19655,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,107500,14500,108500"
st "hClk               : std_ulogic"
)
)
*65 (PortIoOut
uid 19656,0
shape (CompositeShape
uid 19657,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19658,0
sl 0
ro 90
xt "20000,21625,21500,22375"
)
(Line
uid 19659,0
sl 0
ro 90
xt "21500,22000,22000,22000"
pts [
"22000,22000"
"21500,22000"
]
)
]
)
tg (WTG
uid 19660,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19661,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-6700,21300,19000,22700"
st "hRData : (ahbDataBitNb-1 downto 0)"
ju 2
blo "19000,22500"
tm "WireNameMgr"
)
)
)
*66 (Net
uid 19668,0
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 9
suid 80,0
)
declText (MLText
uid 19669,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,108400,29900,109400"
st "hRData             : std_ulogic_vector(ahbDataBitNb-1 downto 0)"
)
)
*67 (PortIoIn
uid 19670,0
shape (CompositeShape
uid 19671,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19672,0
sl 0
ro 270
xt "20000,41625,21500,42375"
)
(Line
uid 19673,0
sl 0
ro 270
xt "21500,42000,22000,42000"
pts [
"21500,42000"
"22000,42000"
]
)
]
)
tg (WTG
uid 19674,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19675,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-7900,41500,19000,42900"
st "hAddr : (ahbAddressBitNb-1 downto 0)"
ju 2
blo "19000,42700"
tm "WireNameMgr"
)
)
)
*68 (Net
uid 19682,0
decl (Decl
n "hAddr"
t "unsigned"
b "(ahbAddressBitNb-1 downto 0)"
o 10
suid 81,0
)
declText (MLText
uid 19683,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,109300,27300,110300"
st "hAddr              : unsigned(ahbAddressBitNb-1 downto 0)"
)
)
*69 (PortIoIn
uid 19684,0
shape (CompositeShape
uid 19685,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19686,0
sl 0
ro 270
xt "20000,5625,21500,6375"
)
(Line
uid 19687,0
sl 0
ro 270
xt "21500,6000,22000,6000"
pts [
"21500,6000"
"22000,6000"
]
)
]
)
tg (WTG
uid 19688,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19689,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "12200,5500,19000,6900"
st "hReset_n"
ju 2
blo "19000,6700"
tm "WireNameMgr"
)
)
)
*70 (Net
uid 19696,0
decl (Decl
n "hReset_n"
t "std_ulogic"
o 11
suid 82,0
)
declText (MLText
uid 19697,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,110200,15300,111200"
st "hReset_n           : std_ulogic"
)
)
*71 (PortIoIn
uid 19698,0
shape (CompositeShape
uid 19699,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19700,0
sl 0
ro 270
xt "20000,43625,21500,44375"
)
(Line
uid 19701,0
sl 0
ro 270
xt "21500,44000,22000,44000"
pts [
"21500,44000"
"22000,44000"
]
)
]
)
tg (WTG
uid 19702,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19703,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-7200,43500,19000,44900"
st "hWData : (ahbDataBitNb-1 downto 0)"
ju 2
blo "19000,44700"
tm "WireNameMgr"
)
)
)
*72 (Net
uid 19710,0
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 12
suid 83,0
)
declText (MLText
uid 19711,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,111100,30100,112100"
st "hWData             : std_ulogic_vector(ahbDataBitNb-1 downto 0)"
)
)
*73 (PortIoIn
uid 19712,0
shape (CompositeShape
uid 19713,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19714,0
sl 0
ro 270
xt "20000,45625,21500,46375"
)
(Line
uid 19715,0
sl 0
ro 270
xt "21500,46000,22000,46000"
pts [
"21500,46000"
"22000,46000"
]
)
]
)
tg (WTG
uid 19716,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19717,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-6900,45500,19000,46900"
st "hTrans : (ahbTransBitNb-1 downto 0)"
ju 2
blo "19000,46700"
tm "WireNameMgr"
)
)
)
*74 (Net
uid 19724,0
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 downto 0)"
o 13
suid 84,0
)
declText (MLText
uid 19725,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,112000,29900,113000"
st "hTrans             : std_ulogic_vector(ahbTransBitNb-1 downto 0)"
)
)
*75 (PortIoIn
uid 19726,0
shape (CompositeShape
uid 19727,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19728,0
sl 0
ro 270
xt "20000,47625,21500,48375"
)
(Line
uid 19729,0
sl 0
ro 270
xt "21500,48000,22000,48000"
pts [
"21500,48000"
"22000,48000"
]
)
]
)
tg (WTG
uid 19730,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19731,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "14000,47500,19000,48900"
st "hWrite"
ju 2
blo "19000,48700"
tm "WireNameMgr"
)
)
)
*76 (Net
uid 19738,0
decl (Decl
n "hWrite"
t "std_ulogic"
o 14
suid 85,0
)
declText (MLText
uid 19739,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,112900,14700,113900"
st "hWrite             : std_ulogic"
)
)
*77 (PortIoIn
uid 19740,0
shape (CompositeShape
uid 19741,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19742,0
sl 0
ro 270
xt "20000,49625,21500,50375"
)
(Line
uid 19743,0
sl 0
ro 270
xt "21500,50000,22000,50000"
pts [
"21500,50000"
"22000,50000"
]
)
]
)
tg (WTG
uid 19744,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19745,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "15500,49500,19000,50900"
st "hSel"
ju 2
blo "19000,50700"
tm "WireNameMgr"
)
)
)
*78 (Net
uid 19752,0
decl (Decl
n "hSel"
t "std_ulogic"
o 15
suid 86,0
)
declText (MLText
uid 19753,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,113800,14400,114800"
st "hSel               : std_ulogic"
)
)
*79 (PortIoOut
uid 19754,0
shape (CompositeShape
uid 19755,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19756,0
sl 0
ro 90
xt "20000,23625,21500,24375"
)
(Line
uid 19757,0
sl 0
ro 90
xt "21500,24000,22000,24000"
pts [
"22000,24000"
"21500,24000"
]
)
]
)
tg (WTG
uid 19758,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19759,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "13500,23300,19000,24700"
st "hReady"
ju 2
blo "19000,24500"
tm "WireNameMgr"
)
)
)
*80 (Net
uid 19766,0
decl (Decl
n "hReady"
t "std_ulogic"
o 16
suid 87,0
)
declText (MLText
uid 19767,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,114700,15200,115700"
st "hReady             : std_ulogic"
)
)
*81 (PortIoOut
uid 19768,0
shape (CompositeShape
uid 19769,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 19770,0
sl 0
ro 90
xt "20000,25625,21500,26375"
)
(Line
uid 19771,0
sl 0
ro 90
xt "21500,26000,22000,26000"
pts [
"22000,26000"
"21500,26000"
]
)
]
)
tg (WTG
uid 19772,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19773,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "14300,25300,19000,26700"
st "hResp"
ju 2
blo "19000,26500"
tm "WireNameMgr"
)
)
)
*82 (Net
uid 19780,0
decl (Decl
n "hResp"
t "std_ulogic"
o 17
suid 88,0
)
declText (MLText
uid 19781,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,115600,14900,116600"
st "hResp              : std_ulogic"
)
)
*83 (HdlText
uid 20266,0
optionalChildren [
*84 (EmbeddedText
uid 20271,0
commentText (CommentText
uid 20272,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 20273,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "30000,1000,46000,9000"
)
oxt "0,0,18000,5000"
text (MLText
uid 20274,0
va (VaSet
)
xt "30200,1200,43900,4800"
st "
clock<= hClk;

reset <= not hReset_n;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 8000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 20267,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "30000,0,46000,10000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 20268,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*85 (Text
uid 20269,0
va (VaSet
)
xt "30400,10000,33700,11200"
st "eb11"
blo "30400,11000"
tm "HdlTextNameMgr"
)
*86 (Text
uid 20270,0
va (VaSet
)
xt "30400,11000,32500,12200"
st "11"
blo "30400,12000"
tm "HdlTextNumberMgr"
)
]
)
)
*87 (Net
uid 20553,0
decl (Decl
n "run_int"
t "std_ulogic"
o 39
suid 90,0
)
declText (MLText
uid 20554,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,139000,17800,140000"
st "SIGNAL run_int            : std_ulogic"
)
)
*88 (Net
uid 20563,0
decl (Decl
n "interpolateLin_int"
t "std_ulogic"
o 40
suid 92,0
)
declText (MLText
uid 20564,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,139900,18600,140900"
st "SIGNAL interpolateLin_int : std_ulogic"
)
)
*89 (SaComponent
uid 21149,0
optionalChildren [
*90 (CptPort
uid 21109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21110,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,41625,94750,42375"
)
tg (CPTG
uid 21111,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21112,0
va (VaSet
)
xt "90700,41400,93000,42600"
st "run"
ju 2
blo "93000,42400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "run"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*91 (CptPort
uid 21113,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21114,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,41625,78000,42375"
)
tg (CPTG
uid 21115,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21116,0
va (VaSet
)
xt "79000,41400,83000,42600"
st "dataIn"
blo "79000,42400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*92 (CptPort
uid 21117,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21118,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,47625,94750,48375"
)
tg (CPTG
uid 21119,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21120,0
va (VaSet
)
xt "84500,47400,93000,48600"
st "updatePattern"
ju 2
blo "93000,48400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "updatePattern"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*93 (CptPort
uid 21121,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21122,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,43625,78000,44375"
)
tg (CPTG
uid 21123,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21124,0
va (VaSet
)
xt "79000,43400,83800,44600"
st "dataOut"
blo "79000,44400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 4,0
)
)
)
*94 (CptPort
uid 21125,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21126,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,47625,78000,48375"
)
tg (CPTG
uid 21127,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21128,0
va (VaSet
)
xt "79000,47400,82100,48600"
st "write"
blo "79000,48400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*95 (CptPort
uid 21129,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21130,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,49625,78000,50375"
)
tg (CPTG
uid 21131,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21132,0
va (VaSet
)
xt "79000,49400,80900,50600"
st "en"
blo "79000,50400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*96 (CptPort
uid 21133,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21134,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,53625,78000,54375"
)
tg (CPTG
uid 21135,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21136,0
va (VaSet
)
xt "79000,53400,82400,54600"
st "clock"
blo "79000,54400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*97 (CptPort
uid 21137,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21138,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,55625,78000,56375"
)
tg (CPTG
uid 21139,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21140,0
va (VaSet
)
xt "79000,55400,82300,56600"
st "reset"
blo "79000,56400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 8
suid 8,0
)
)
)
*98 (CptPort
uid 21141,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21142,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,43625,94750,44375"
)
tg (CPTG
uid 21143,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21144,0
va (VaSet
)
xt "83100,43400,93000,44600"
st "interpolateLinear"
ju 2
blo "93000,44400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "interpolateLinear"
t "std_ulogic"
o 9
suid 9,0
)
)
)
*99 (CptPort
uid 21145,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21146,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,49625,94750,50375"
)
tg (CPTG
uid 21147,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21148,0
va (VaSet
)
xt "85900,49400,93000,50600"
st "patternSize"
ju 2
blo "93000,50400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "patternSize"
t "unsigned"
b "(patternSizeBitNb-1 downto 0)"
o 10
suid 2011,0
)
)
)
]
shape (Rectangle
uid 21150,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,38000,94000,58000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 21151,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*100 (Text
uid 21152,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,57800,87000,59000"
st "SystemOnChip"
blo "78600,58800"
tm "BdLibraryNameMgr"
)
*101 (Text
uid 21153,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,58700,88400,59900"
st "periphControlReg"
blo "78600,59700"
tm "CptNameMgr"
)
*102 (Text
uid 21154,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,59600,81600,60800"
st "I_ctl"
blo "78600,60600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21155,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21156,0
text (MLText
uid 21157,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,61600,102300,63600"
st "dataBitNb        = dataBitNb              ( positive )  
patternSizeBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "patternSizeBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*103 (SaComponent
uid 21186,0
optionalChildren [
*104 (CptPort
uid 21158,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21159,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,69625,94750,70375"
)
tg (CPTG
uid 21160,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21161,0
va (VaSet
)
xt "85000,69400,93000,70600"
st "updatePeriod"
ju 2
blo "93000,70400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*105 (CptPort
uid 21162,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21163,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,69625,78000,70375"
)
tg (CPTG
uid 21164,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21165,0
va (VaSet
)
xt "79000,69400,83000,70600"
st "dataIn"
blo "79000,70400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*106 (CptPort
uid 21166,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21167,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,71625,78000,72375"
)
tg (CPTG
uid 21168,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21169,0
va (VaSet
)
xt "79000,71400,83800,72600"
st "dataOut"
blo "79000,72400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 3
suid 3,0
)
)
)
*107 (CptPort
uid 21170,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21171,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,77625,78000,78375"
)
tg (CPTG
uid 21172,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21173,0
va (VaSet
)
xt "79000,77400,80900,78600"
st "en"
blo "79000,78400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 4
suid 5,0
)
)
)
*108 (CptPort
uid 21174,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21175,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,81625,78000,82375"
)
tg (CPTG
uid 21176,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21177,0
va (VaSet
)
xt "79000,81400,82400,82600"
st "clock"
blo "79000,82400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 5
suid 6,0
)
)
)
*109 (CptPort
uid 21178,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21179,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,83625,78000,84375"
)
tg (CPTG
uid 21180,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21181,0
va (VaSet
)
xt "79000,83400,82300,84600"
st "reset"
blo "79000,84400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 7,0
)
)
)
*110 (CptPort
uid 21182,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21183,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,75625,78000,76375"
)
tg (CPTG
uid 21184,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21185,0
va (VaSet
)
xt "79000,75400,82100,76600"
st "write"
blo "79000,76400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 7
suid 8,0
)
)
)
]
shape (Rectangle
uid 21187,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,66000,94000,86000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 21188,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*111 (Text
uid 21189,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,85800,87000,87000"
st "SystemOnChip"
blo "78600,86800"
tm "BdLibraryNameMgr"
)
*112 (Text
uid 21190,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,86700,87800,87900"
st "periphSpeedReg"
blo "78600,87700"
tm "CptNameMgr"
)
*113 (Text
uid 21191,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,87600,83200,88800"
st "I_speed"
blo "78600,88600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21192,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21193,0
text (MLText
uid 21194,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,89600,102400,91600"
st "dataBitNb         = dataBitNb            ( positive )  
updatePeriodBitNb = updatePeriodBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "updatePeriodBitNb"
type "positive"
value "updatePeriodBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*114 (SaComponent
uid 21219,0
optionalChildren [
*115 (CptPort
uid 21195,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21196,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,71625,46750,72375"
)
tg (CPTG
uid 21197,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21198,0
va (VaSet
)
xt "38400,71400,45000,72600"
st "selControl"
ju 2
blo "45000,72400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selControl"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*116 (CptPort
uid 21199,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21200,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29250,71625,30000,72375"
)
tg (CPTG
uid 21201,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21202,0
va (VaSet
)
xt "31000,71400,33900,72600"
st "addr"
blo "31000,72400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*117 (CptPort
uid 21203,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21204,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,73625,46750,74375"
)
tg (CPTG
uid 21205,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21206,0
va (VaSet
)
xt "39700,73400,45000,74600"
st "selSpeed"
ju 2
blo "45000,74400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selSpeed"
t "std_ulogic"
o 3
suid 4,0
)
)
)
*118 (CptPort
uid 21207,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21208,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,77625,46750,78375"
)
tg (CPTG
uid 21209,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21210,0
va (VaSet
)
xt "42100,77400,45000,78600"
st "selX"
ju 2
blo "45000,78400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selX"
t "std_ulogic"
o 4
suid 5,0
)
)
)
*119 (CptPort
uid 21211,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21212,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,79625,46750,80375"
)
tg (CPTG
uid 21213,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21214,0
va (VaSet
)
xt "42100,79400,45000,80600"
st "selY"
ju 2
blo "45000,80400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selY"
t "std_ulogic"
o 5
suid 6,0
)
)
)
*120 (CptPort
uid 21215,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21216,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "46000,81625,46750,82375"
)
tg (CPTG
uid 21217,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21218,0
va (VaSet
)
xt "42100,81400,45000,82600"
st "selZ"
ju 2
blo "45000,82400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "selZ"
t "std_ulogic"
o 6
suid 7,0
)
)
)
]
shape (Rectangle
uid 21220,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "30000,68000,46000,86000"
)
oxt "34000,9000,50000,27000"
ttg (MlTextGroup
uid 21221,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*121 (Text
uid 21222,0
va (VaSet
font "Verdana,9,1"
)
xt "30600,85800,39000,87000"
st "SystemOnChip"
blo "30600,86800"
tm "BdLibraryNameMgr"
)
*122 (Text
uid 21223,0
va (VaSet
font "Verdana,9,1"
)
xt "30600,86700,43500,87900"
st "periphAddressDecoder"
blo "30600,87700"
tm "CptNameMgr"
)
*123 (Text
uid 21224,0
va (VaSet
font "Verdana,9,1"
)
xt "30600,87600,36200,88800"
st "I_decoder"
blo "30600,88600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21225,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21226,0
text (MLText
uid 21227,0
va (VaSet
font "Verdana,8,0"
)
xt "30000,89600,50000,90600"
st "addressBitNb = addressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*124 (SaComponent
uid 21252,0
optionalChildren [
*125 (CptPort
uid 21228,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21229,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,109625,78000,110375"
)
tg (CPTG
uid 21230,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21231,0
va (VaSet
)
xt "79000,109400,80900,110600"
st "en"
blo "79000,110400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*126 (CptPort
uid 21232,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21233,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,113625,78000,114375"
)
tg (CPTG
uid 21234,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21235,0
va (VaSet
)
xt "79000,113400,82400,114600"
st "clock"
blo "79000,114400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*127 (CptPort
uid 21236,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21237,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,115625,78000,116375"
)
tg (CPTG
uid 21238,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21239,0
va (VaSet
)
xt "79000,115400,82300,116600"
st "reset"
blo "79000,116400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*128 (CptPort
uid 21240,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21241,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,107625,78000,108375"
)
tg (CPTG
uid 21242,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21243,0
va (VaSet
)
xt "79000,107400,85500,108600"
st "updateMem"
blo "79000,108400"
)
)
thePort (LogicalPort
decl (Decl
n "updateMem"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*129 (CptPort
uid 21244,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21245,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,105625,94750,106375"
)
tg (CPTG
uid 21246,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21247,0
va (VaSet
)
xt "90100,105400,93000,106600"
st "addr"
ju 2
blo "93000,106400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*130 (CptPort
uid 21248,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21249,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,105625,78000,106375"
)
tg (CPTG
uid 21250,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21251,0
va (VaSet
)
xt "79000,105400,86100,106600"
st "patternSize"
blo "79000,106400"
)
)
thePort (LogicalPort
decl (Decl
n "patternSize"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
]
shape (Rectangle
uid 21253,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,102000,94000,118000"
)
oxt "38000,13000,54000,29000"
ttg (MlTextGroup
uid 21254,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*131 (Text
uid 21255,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,117800,87000,119000"
st "SystemOnChip"
blo "78600,118800"
tm "BdLibraryNameMgr"
)
*132 (Text
uid 21256,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,118700,93200,119900"
st "blockRAMAddressCounter"
blo "78600,119700"
tm "CptNameMgr"
)
*133 (Text
uid 21257,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,119600,83100,120800"
st "I_addry"
blo "78600,120600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21258,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21259,0
text (MLText
uid 21260,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,121600,100900,122600"
st "addressBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*134 (SaComponent
uid 21297,0
optionalChildren [
*135 (CptPort
uid 21261,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21262,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,133625,94750,134375"
)
tg (CPTG
uid 21263,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21264,0
va (VaSet
)
xt "88600,133400,93000,134600"
st "memWr"
ju 2
blo "93000,134400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*136 (CptPort
uid 21265,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21266,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,129625,78000,130375"
)
tg (CPTG
uid 21267,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21268,0
va (VaSet
)
xt "79000,129400,81200,130600"
st "sel"
blo "79000,130400"
)
)
thePort (LogicalPort
decl (Decl
n "sel"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*137 (CptPort
uid 21269,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21270,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,135625,94750,136375"
)
tg (CPTG
uid 21271,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21272,0
va (VaSet
)
xt "88600,135400,93000,136600"
st "memEn"
ju 2
blo "93000,136400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memEn"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*138 (CptPort
uid 21273,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21274,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,133625,78000,134375"
)
tg (CPTG
uid 21275,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21276,0
va (VaSet
)
xt "79000,133400,83100,134600"
st "update"
blo "79000,134400"
)
)
thePort (LogicalPort
decl (Decl
n "update"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*139 (CptPort
uid 21277,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21278,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,131625,78000,132375"
)
tg (CPTG
uid 21279,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21280,0
va (VaSet
)
xt "79000,131400,80800,132600"
st "wr"
blo "79000,132400"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*140 (CptPort
uid 21281,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21282,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,129625,94750,130375"
)
tg (CPTG
uid 21283,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21284,0
va (VaSet
)
xt "88600,129400,93000,130600"
st "cntIncr"
ju 2
blo "93000,130400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cntIncr"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*141 (CptPort
uid 21285,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21286,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,135625,78000,136375"
)
tg (CPTG
uid 21287,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21288,0
va (VaSet
)
xt "79000,135400,85300,136600"
st "newSample"
blo "79000,136400"
)
)
thePort (LogicalPort
decl (Decl
n "newSample"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*142 (CptPort
uid 21289,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21290,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,139625,78000,140375"
)
tg (CPTG
uid 21291,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21292,0
va (VaSet
)
xt "79000,139400,82400,140600"
st "clock"
blo "79000,140400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 8
suid 8,0
)
)
)
*143 (CptPort
uid 21293,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21294,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,141625,78000,142375"
)
tg (CPTG
uid 21295,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21296,0
va (VaSet
)
xt "79000,141400,82300,142600"
st "reset"
blo "79000,142400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 21298,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,126000,94000,144000"
)
oxt "32000,8000,48000,26000"
ttg (MlTextGroup
uid 21299,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*144 (Text
uid 21300,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,143800,87000,145000"
st "SystemOnChip"
blo "78600,144800"
tm "BdLibraryNameMgr"
)
*145 (Text
uid 21301,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,144700,88300,145900"
st "blockRAMControl"
blo "78600,145700"
tm "CptNameMgr"
)
*146 (Text
uid 21302,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,145600,82200,146800"
st "I_ctly"
blo "78600,146600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21303,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21304,0
text (MLText
uid 21305,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,139800,78000,139800"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*147 (SaComponent
uid 21330,0
optionalChildren [
*148 (CptPort
uid 21306,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21307,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,159625,78000,160375"
)
tg (CPTG
uid 21308,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21309,0
va (VaSet
)
xt "79000,159400,80900,160600"
st "en"
blo "79000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*149 (CptPort
uid 21310,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21311,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,163625,78000,164375"
)
tg (CPTG
uid 21312,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21313,0
va (VaSet
)
xt "79000,163400,82400,164600"
st "clock"
blo "79000,164400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*150 (CptPort
uid 21314,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21315,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,165625,78000,166375"
)
tg (CPTG
uid 21316,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21317,0
va (VaSet
)
xt "79000,165400,82300,166600"
st "reset"
blo "79000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*151 (CptPort
uid 21318,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21319,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,157625,78000,158375"
)
tg (CPTG
uid 21320,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21321,0
va (VaSet
)
xt "79000,157400,85500,158600"
st "updateMem"
blo "79000,158400"
)
)
thePort (LogicalPort
decl (Decl
n "updateMem"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*152 (CptPort
uid 21322,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21323,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,155625,94750,156375"
)
tg (CPTG
uid 21324,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21325,0
va (VaSet
)
xt "90100,155400,93000,156600"
st "addr"
ju 2
blo "93000,156400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 5
suid 5,0
)
)
)
*153 (CptPort
uid 21326,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21327,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,155625,78000,156375"
)
tg (CPTG
uid 21328,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21329,0
va (VaSet
)
xt "79000,155400,86100,156600"
st "patternSize"
blo "79000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "patternSize"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
)
]
shape (Rectangle
uid 21331,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,152000,94000,168000"
)
oxt "38000,13000,54000,29000"
ttg (MlTextGroup
uid 21332,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*154 (Text
uid 21333,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,167800,87000,169000"
st "SystemOnChip"
blo "78600,168800"
tm "BdLibraryNameMgr"
)
*155 (Text
uid 21334,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,168700,93200,169900"
st "blockRAMAddressCounter"
blo "78600,169700"
tm "CptNameMgr"
)
*156 (Text
uid 21335,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,169600,83100,170800"
st "I_addrx"
blo "78600,170600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21336,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21337,0
text (MLText
uid 21338,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,171600,100900,172600"
st "addressBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*157 (SaComponent
uid 21375,0
optionalChildren [
*158 (CptPort
uid 21339,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21340,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,183625,94750,184375"
)
tg (CPTG
uid 21341,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21342,0
va (VaSet
)
xt "88600,183400,93000,184600"
st "memWr"
ju 2
blo "93000,184400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr"
t "std_ulogic"
o 1
suid 1,0
)
)
)
*159 (CptPort
uid 21343,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21344,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,179625,78000,180375"
)
tg (CPTG
uid 21345,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21346,0
va (VaSet
)
xt "79000,179400,81200,180600"
st "sel"
blo "79000,180400"
)
)
thePort (LogicalPort
decl (Decl
n "sel"
t "std_ulogic"
o 2
suid 2,0
)
)
)
*160 (CptPort
uid 21347,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21348,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,185625,94750,186375"
)
tg (CPTG
uid 21349,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21350,0
va (VaSet
)
xt "88600,185400,93000,186600"
st "memEn"
ju 2
blo "93000,186400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memEn"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*161 (CptPort
uid 21351,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21352,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,183625,78000,184375"
)
tg (CPTG
uid 21353,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21354,0
va (VaSet
)
xt "79000,183400,83100,184600"
st "update"
blo "79000,184400"
)
)
thePort (LogicalPort
decl (Decl
n "update"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*162 (CptPort
uid 21355,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21356,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,181625,78000,182375"
)
tg (CPTG
uid 21357,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21358,0
va (VaSet
)
xt "79000,181400,80800,182600"
st "wr"
blo "79000,182400"
)
)
thePort (LogicalPort
decl (Decl
n "wr"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*163 (CptPort
uid 21359,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21360,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "94000,179625,94750,180375"
)
tg (CPTG
uid 21361,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21362,0
va (VaSet
)
xt "88600,179400,93000,180600"
st "cntIncr"
ju 2
blo "93000,180400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cntIncr"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*164 (CptPort
uid 21363,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21364,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,185625,78000,186375"
)
tg (CPTG
uid 21365,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21366,0
va (VaSet
)
xt "79000,185400,85300,186600"
st "newSample"
blo "79000,186400"
)
)
thePort (LogicalPort
decl (Decl
n "newSample"
t "std_ulogic"
o 7
suid 7,0
)
)
)
*165 (CptPort
uid 21367,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21368,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,189625,78000,190375"
)
tg (CPTG
uid 21369,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21370,0
va (VaSet
)
xt "79000,189400,82400,190600"
st "clock"
blo "79000,190400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 8
suid 8,0
)
)
)
*166 (CptPort
uid 21371,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21372,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,191625,78000,192375"
)
tg (CPTG
uid 21373,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21374,0
va (VaSet
)
xt "79000,191400,82300,192600"
st "reset"
blo "79000,192400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 9
suid 9,0
)
)
)
]
shape (Rectangle
uid 21376,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,176000,94000,194000"
)
oxt "32000,8000,48000,26000"
ttg (MlTextGroup
uid 21377,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*167 (Text
uid 21378,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,193800,87000,195000"
st "SystemOnChip"
blo "78600,194800"
tm "BdLibraryNameMgr"
)
*168 (Text
uid 21379,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,194700,88300,195900"
st "blockRAMControl"
blo "78600,195700"
tm "CptNameMgr"
)
*169 (Text
uid 21380,0
va (VaSet
font "Verdana,9,1"
)
xt "78600,195600,82200,196800"
st "I_ctlx"
blo "78600,196600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21381,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21382,0
text (MLText
uid 21383,0
va (VaSet
font "Verdana,8,0"
)
xt "78000,189800,78000,189800"
)
header ""
)
elements [
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*170 (SaComponent
uid 21412,0
optionalChildren [
*171 (CptPort
uid 21384,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21385,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,153625,110000,154375"
)
tg (CPTG
uid 21386,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21387,0
va (VaSet
)
xt "111000,153400,115000,154600"
st "dataIn"
blo "111000,154400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*172 (CptPort
uid 21388,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21389,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126000,153625,126750,154375"
)
tg (CPTG
uid 21390,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21391,0
va (VaSet
)
xt "120200,153400,125000,154600"
st "dataOut"
ju 2
blo "125000,154400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*173 (CptPort
uid 21392,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21393,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,161625,110000,162375"
)
tg (CPTG
uid 21394,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21395,0
va (VaSet
)
xt "111000,161400,112900,162600"
st "en"
blo "111000,162400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*174 (CptPort
uid 21396,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21397,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,165625,110000,166375"
)
tg (CPTG
uid 21398,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21399,0
va (VaSet
)
xt "111000,165400,114400,166600"
st "clock"
blo "111000,166400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*175 (CptPort
uid 21400,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21401,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,167625,110000,168375"
)
tg (CPTG
uid 21402,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21403,0
va (VaSet
)
xt "111000,167400,114300,168600"
st "reset"
blo "111000,168400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*176 (CptPort
uid 21404,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21405,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,159625,110000,160375"
)
tg (CPTG
uid 21406,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21407,0
va (VaSet
)
xt "111000,159400,114100,160600"
st "write"
blo "111000,160400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*177 (CptPort
uid 21408,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21409,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,155625,110000,156375"
)
tg (CPTG
uid 21410,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21411,0
va (VaSet
)
xt "111000,155400,113900,156600"
st "addr"
blo "111000,156400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
]
shape (Rectangle
uid 21413,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "110000,150000,126000,170000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 21414,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*178 (Text
uid 21415,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,169800,119000,171000"
st "SystemOnChip"
blo "110600,170800"
tm "BdLibraryNameMgr"
)
*179 (Text
uid 21416,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,170700,116100,171900"
st "blockRAM"
blo "110600,171700"
tm "CptNameMgr"
)
*180 (Text
uid 21417,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,171600,114800,172800"
st "I_ramx"
blo "110600,172600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21418,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21419,0
text (MLText
uid 21420,0
va (VaSet
font "Verdana,8,0"
)
xt "110000,173600,137300,176600"
st "addressBitNb = patternAddressBitNb               ( positive )  
dataBitNb    = signalBitNb                       ( positive )  
initFileSpec = \"$SIMULATION_DIR/ramYInit.txt\"    ( string   )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "initFileSpec"
type "string"
value "\"$SIMULATION_DIR/ramYInit.txt\""
)
]
)
ordering 1
connectByName 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*181 (SaComponent
uid 21449,0
optionalChildren [
*182 (CptPort
uid 21421,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21422,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,115625,110000,116375"
)
tg (CPTG
uid 21423,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21424,0
va (VaSet
)
xt "111000,115400,115000,116600"
st "dataIn"
blo "111000,116400"
)
)
thePort (LogicalPort
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 1
suid 1,0
)
)
)
*183 (CptPort
uid 21425,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21426,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126000,115625,126750,116375"
)
tg (CPTG
uid 21427,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 21428,0
va (VaSet
)
xt "120200,115400,125000,116600"
st "dataOut"
ju 2
blo "125000,116400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*184 (CptPort
uid 21429,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21430,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,123625,110000,124375"
)
tg (CPTG
uid 21431,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21432,0
va (VaSet
)
xt "111000,123400,112900,124600"
st "en"
blo "111000,124400"
)
)
thePort (LogicalPort
decl (Decl
n "en"
t "std_ulogic"
o 3
suid 3,0
)
)
)
*185 (CptPort
uid 21433,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21434,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,127625,110000,128375"
)
tg (CPTG
uid 21435,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21436,0
va (VaSet
)
xt "111000,127400,114400,128600"
st "clock"
blo "111000,128400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 4
suid 4,0
)
)
)
*186 (CptPort
uid 21437,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21438,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,129625,110000,130375"
)
tg (CPTG
uid 21439,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21440,0
va (VaSet
)
xt "111000,129400,114300,130600"
st "reset"
blo "111000,130400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 5
suid 5,0
)
)
)
*187 (CptPort
uid 21441,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21442,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,121625,110000,122375"
)
tg (CPTG
uid 21443,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21444,0
va (VaSet
)
xt "111000,121400,114100,122600"
st "write"
blo "111000,122400"
)
)
thePort (LogicalPort
decl (Decl
n "write"
t "std_ulogic"
o 6
suid 6,0
)
)
)
*188 (CptPort
uid 21445,0
ps "OnEdgeStrategy"
shape (Triangle
uid 21446,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,117625,110000,118375"
)
tg (CPTG
uid 21447,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 21448,0
va (VaSet
)
xt "111000,117400,113900,118600"
st "addr"
blo "111000,118400"
)
)
thePort (LogicalPort
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 7
suid 7,0
)
)
)
]
shape (Rectangle
uid 21450,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "110000,112000,126000,132000"
)
oxt "38000,9000,54000,29000"
ttg (MlTextGroup
uid 21451,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*189 (Text
uid 21452,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,131800,119000,133000"
st "SystemOnChip"
blo "110600,132800"
tm "BdLibraryNameMgr"
)
*190 (Text
uid 21453,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,132700,116100,133900"
st "blockRAM"
blo "110600,133700"
tm "CptNameMgr"
)
*191 (Text
uid 21454,0
va (VaSet
font "Verdana,9,1"
)
xt "110600,133600,114800,134800"
st "I_ramy"
blo "110600,134600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 21455,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 21456,0
text (MLText
uid 21457,0
va (VaSet
font "Verdana,8,0"
)
xt "110000,135600,137300,138600"
st "addressBitNb = patternAddressBitNb               ( positive )  
dataBitNb    = signalBitNb                       ( positive )  
initFileSpec = \"$SIMULATION_DIR/ramXInit.txt\"    ( string   )  "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "initFileSpec"
type "string"
value "\"$SIMULATION_DIR/ramXInit.txt\""
)
]
)
ordering 1
connectByName 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*192 (Wire
uid 73,0
shape (OrthoPolyLine
uid 74,0
va (VaSet
vasetType 3
)
xt "74000,54000,77250,54000"
pts [
"74000,54000"
"77250,54000"
]
)
end &96
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 77,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 78,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,52600,77800,54000"
st "clock"
blo "74000,53800"
tm "WireNameMgr"
)
)
on &12
)
*193 (Wire
uid 157,0
shape (OrthoPolyLine
uid 158,0
va (VaSet
vasetType 3
)
xt "74000,56000,77250,56000"
pts [
"74000,56000"
"77250,56000"
]
)
end &97
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 161,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 162,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,54600,78100,56000"
st "reset"
blo "74000,55800"
tm "WireNameMgr"
)
)
on &13
)
*194 (Wire
uid 1057,0
shape (OrthoPolyLine
uid 1058,0
va (VaSet
vasetType 3
)
xt "46750,74000,77250,78000"
pts [
"46750,74000"
"58000,74000"
"58000,78000"
"77250,78000"
]
)
start &117
end &107
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1061,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1062,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,76600,76600,78000"
st "selSpeed"
blo "70000,77800"
tm "WireNameMgr"
)
)
on &16
)
*195 (Wire
uid 1065,0
shape (OrthoPolyLine
uid 1066,0
va (VaSet
vasetType 3
)
xt "46750,78000,77250,180000"
pts [
"46750,78000"
"56000,78000"
"56000,180000"
"77250,180000"
]
)
start &118
end &159
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1069,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1070,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,178600,73400,180000"
st "selX"
blo "70000,179800"
tm "WireNameMgr"
)
)
on &17
)
*196 (Wire
uid 1073,0
shape (OrthoPolyLine
uid 1074,0
va (VaSet
vasetType 3
)
xt "46750,80000,77250,130000"
pts [
"46750,80000"
"54000,80000"
"54000,130000"
"77250,130000"
]
)
start &119
end &136
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1077,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1078,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,128600,73300,130000"
st "selY"
blo "70000,129800"
tm "WireNameMgr"
)
)
on &18
)
*197 (Wire
uid 1332,0
shape (OrthoPolyLine
uid 1333,0
va (VaSet
vasetType 3
)
xt "46750,50000,77250,72000"
pts [
"46750,72000"
"58000,72000"
"58000,50000"
"77250,50000"
]
)
start &115
end &95
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1338,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1339,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,48600,78000,50000"
st "selControl"
blo "70000,49800"
tm "WireNameMgr"
)
)
on &15
)
*198 (Wire
uid 1340,0
shape (OrthoPolyLine
uid 1341,0
va (VaSet
vasetType 3
)
xt "70000,48000,77250,48000"
pts [
"70000,48000"
"77250,48000"
]
)
end &94
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1346,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1347,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,46600,74000,48000"
st "write"
blo "70000,47800"
tm "WireNameMgr"
)
)
on &57
)
*199 (Wire
uid 1350,0
shape (OrthoPolyLine
uid 1351,0
va (VaSet
vasetType 3
)
xt "104000,42000,109250,42000"
pts [
"104000,42000"
"109250,42000"
]
)
end &43
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1354,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1355,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,40600,108900,42000"
st "run"
blo "106000,41800"
tm "WireNameMgr"
)
)
on &19
)
*200 (Wire
uid 1358,0
shape (OrthoPolyLine
uid 1359,0
va (VaSet
vasetType 3
)
xt "94750,48000,102000,48000"
pts [
"94750,48000"
"102000,48000"
]
)
start &92
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1362,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1363,0
va (VaSet
font "Verdana,12,0"
)
xt "96750,46600,107550,48000"
st "updatePattern"
blo "96750,47800"
tm "WireNameMgr"
)
)
on &20
)
*201 (Wire
uid 1472,0
shape (OrthoPolyLine
uid 1473,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,50000,102000,50000"
pts [
"94750,50000"
"102000,50000"
]
)
start &99
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1477,0
va (VaSet
font "Verdana,12,0"
)
xt "96750,48600,105650,50000"
st "patternSize"
blo "96750,49800"
tm "WireNameMgr"
)
)
on &21
)
*202 (Wire
uid 1526,0
optionalChildren [
*203 (BdJunction
uid 1538,0
ps "OnConnectorStrategy"
shape (Circle
uid 1539,0
va (VaSet
vasetType 1
)
xt "61600,41600,62400,42400"
radius 400
)
)
*204 (BdJunction
uid 1736,0
ps "OnConnectorStrategy"
shape (Circle
uid 1737,0
va (VaSet
vasetType 1
)
xt "61600,69600,62400,70400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1527,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "46000,42000,62000,86000"
pts [
"62000,86000"
"62000,42000"
"46000,42000"
]
)
start &52
end &47
sat 1
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1532,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1533,0
va (VaSet
font "Verdana,12,0"
)
xt "46000,40600,51000,42000"
st "dataIn"
blo "46000,41800"
tm "WireNameMgr"
)
)
on &46
)
*205 (Wire
uid 1534,0
shape (OrthoPolyLine
uid 1535,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,42000,77250,42000"
pts [
"62000,42000"
"77250,42000"
]
)
start &203
end &91
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1536,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1537,0
va (VaSet
font "Verdana,12,0"
)
xt "71000,40600,76000,42000"
st "dataIn"
blo "71000,41800"
tm "WireNameMgr"
)
)
on &46
)
*206 (Wire
uid 1583,0
optionalChildren [
*207 (BdJunction
uid 2856,0
ps "OnConnectorStrategy"
shape (Circle
uid 2857,0
va (VaSet
vasetType 1
)
xt "65600,71600,66400,72400"
radius 400
)
)
*208 (BdJunction
uid 2864,0
ps "OnConnectorStrategy"
shape (Circle
uid 2865,0
va (VaSet
vasetType 1
)
xt "65600,43600,66400,44400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1584,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "46000,22000,66000,76000"
pts [
"66000,76000"
"66000,22000"
"46000,22000"
]
)
end &58
sat 16
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1587,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1588,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,20600,55000,22000"
st "dataOut"
blo "49000,21800"
tm "WireNameMgr"
)
)
on &22
)
*209 (Wire
uid 1732,0
shape (OrthoPolyLine
uid 1733,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,70000,77250,70000"
pts [
"62000,70000"
"77250,70000"
]
)
start &204
end &105
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1734,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1735,0
va (VaSet
font "Verdana,12,0"
)
xt "72250,68600,77250,70000"
st "dataIn"
blo "72250,69800"
tm "WireNameMgr"
)
)
on &46
)
*210 (Wire
uid 1738,0
shape (OrthoPolyLine
uid 1739,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66000,72000,77250,72000"
pts [
"66000,72000"
"77250,72000"
]
)
start &207
end &106
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1740,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1741,0
va (VaSet
font "Verdana,12,0"
)
xt "71250,70600,77250,72000"
st "dataOut"
blo "71250,71800"
tm "WireNameMgr"
)
)
on &22
)
*211 (Wire
uid 1744,0
shape (OrthoPolyLine
uid 1745,0
va (VaSet
vasetType 3
)
xt "74000,84000,77250,84000"
pts [
"74000,84000"
"77250,84000"
]
)
end &109
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1750,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1751,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,82600,78100,84000"
st "reset"
blo "74000,83800"
tm "WireNameMgr"
)
)
on &13
)
*212 (Wire
uid 1752,0
shape (OrthoPolyLine
uid 1753,0
va (VaSet
vasetType 3
)
xt "74000,82000,77250,82000"
pts [
"74000,82000"
"77250,82000"
]
)
end &108
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1758,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1759,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,80600,77800,82000"
st "clock"
blo "74000,81800"
tm "WireNameMgr"
)
)
on &12
)
*213 (Wire
uid 1778,0
shape (OrthoPolyLine
uid 1779,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,70000,109250,70000"
pts [
"94750,70000"
"109250,70000"
]
)
start &104
end &44
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1782,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1783,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,68600,106100,70000"
st "updatePeriod"
blo "96000,69800"
tm "WireNameMgr"
)
)
on &23
)
*214 (Wire
uid 2478,0
shape (OrthoPolyLine
uid 2479,0
va (VaSet
vasetType 3
)
xt "106000,166000,109250,166000"
pts [
"106000,166000"
"109250,166000"
]
)
end &174
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2485,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,164600,109800,166000"
st "clock"
blo "106000,165800"
tm "WireNameMgr"
)
)
on &12
)
*215 (Wire
uid 2486,0
shape (OrthoPolyLine
uid 2487,0
va (VaSet
vasetType 3
)
xt "106000,168000,109250,168000"
pts [
"106000,168000"
"109250,168000"
]
)
end &175
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2492,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2493,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,166600,110100,168000"
st "reset"
blo "106000,167800"
tm "WireNameMgr"
)
)
on &13
)
*216 (Wire
uid 2638,0
shape (OrthoPolyLine
uid 2639,0
va (VaSet
vasetType 3
)
xt "94750,160000,109250,184000"
pts [
"94750,184000"
"102000,184000"
"102000,160000"
"109250,160000"
]
)
start &158
end &176
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2640,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2641,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,158600,109400,160000"
st "memWrX"
blo "103000,159800"
tm "WireNameMgr"
)
)
on &26
)
*217 (Wire
uid 2644,0
shape (OrthoPolyLine
uid 2645,0
va (VaSet
vasetType 3
)
xt "94750,162000,109250,186000"
pts [
"94750,186000"
"104000,186000"
"104000,162000"
"109250,162000"
]
)
start &160
end &173
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2646,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2647,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,160600,109200,162000"
st "memEnX"
blo "103000,161800"
tm "WireNameMgr"
)
)
on &27
)
*218 (Wire
uid 2648,0
shape (OrthoPolyLine
uid 2649,0
va (VaSet
vasetType 3
)
xt "70000,184000,77250,184000"
pts [
"70000,184000"
"77250,184000"
]
)
end &161
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2654,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2655,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,182600,79800,184000"
st "updatePattern"
blo "69000,183800"
tm "WireNameMgr"
)
)
on &20
)
*219 (Wire
uid 2772,0
shape (OrthoPolyLine
uid 2773,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,156000,109250,156000"
pts [
"94750,156000"
"109250,156000"
]
)
start &152
end &177
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2774,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2775,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,154600,109500,156000"
st "addrX"
blo "105000,155800"
tm "WireNameMgr"
)
)
on &24
)
*220 (Wire
uid 2778,0
shape (OrthoPolyLine
uid 2779,0
va (VaSet
vasetType 3
)
xt "74000,166000,77250,166000"
pts [
"74000,166000"
"77250,166000"
]
)
end &150
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2784,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2785,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,164600,78100,166000"
st "reset"
blo "74000,165800"
tm "WireNameMgr"
)
)
on &13
)
*221 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
)
xt "74000,164000,77250,164000"
pts [
"74000,164000"
"77250,164000"
]
)
end &149
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2792,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2793,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,162600,77800,164000"
st "clock"
blo "74000,163800"
tm "WireNameMgr"
)
)
on &12
)
*222 (Wire
uid 2844,0
shape (OrthoPolyLine
uid 2845,0
va (VaSet
vasetType 3
)
xt "72000,160000,98000,180000"
pts [
"94750,180000"
"98000,180000"
"98000,174000"
"72000,174000"
"72000,160000"
"77250,160000"
]
)
start &163
end &148
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2846,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2847,0
va (VaSet
font "Verdana,12,0"
)
xt "72000,158600,77900,160000"
st "cntIncrX"
blo "72000,159800"
tm "WireNameMgr"
)
)
on &25
)
*223 (Wire
uid 2860,0
shape (OrthoPolyLine
uid 2861,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "66000,44000,77250,44000"
pts [
"66000,44000"
"77250,44000"
]
)
start &208
end &93
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2862,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2863,0
va (VaSet
font "Verdana,12,0"
)
xt "71250,42600,77250,44000"
st "dataOut"
blo "71250,43800"
tm "WireNameMgr"
)
)
on &22
)
*224 (Wire
uid 2866,0
shape (OrthoPolyLine
uid 2867,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,156000,77250,156000"
pts [
"70000,156000"
"77250,156000"
]
)
end &153
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2873,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,154600,77900,156000"
st "patternSize"
blo "69000,155800"
tm "WireNameMgr"
)
)
on &21
)
*225 (Wire
uid 2919,0
shape (OrthoPolyLine
uid 2920,0
va (VaSet
vasetType 3
)
xt "70000,186000,77250,186000"
pts [
"77250,186000"
"70000,186000"
]
)
start &164
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2926,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,184600,78600,186000"
st "newPolynom"
blo "69000,185800"
tm "WireNameMgr"
)
)
on &14
)
*226 (Wire
uid 2996,0
shape (OrthoPolyLine
uid 2997,0
va (VaSet
vasetType 3
)
xt "74000,192000,77250,192000"
pts [
"74000,192000"
"77250,192000"
]
)
end &166
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3002,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3003,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,190600,78100,192000"
st "reset"
blo "74000,191800"
tm "WireNameMgr"
)
)
on &13
)
*227 (Wire
uid 3004,0
shape (OrthoPolyLine
uid 3005,0
va (VaSet
vasetType 3
)
xt "74000,190000,77250,190000"
pts [
"74000,190000"
"77250,190000"
]
)
end &165
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3010,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3011,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,188600,77800,190000"
st "clock"
blo "74000,189800"
tm "WireNameMgr"
)
)
on &12
)
*228 (Wire
uid 3094,0
shape (OrthoPolyLine
uid 3095,0
va (VaSet
vasetType 3
)
xt "70000,158000,77250,158000"
pts [
"70000,158000"
"77250,158000"
]
)
end &151
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3100,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3101,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,156600,79800,158000"
st "updatePattern"
blo "69000,157800"
tm "WireNameMgr"
)
)
on &20
)
*229 (Wire
uid 3146,0
shape (OrthoPolyLine
uid 3147,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "126750,154000,134000,154000"
pts [
"126750,154000"
"134000,154000"
]
)
start &172
end &42
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3150,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3151,0
va (VaSet
font "Verdana,12,0"
)
xt "128000,152600,132600,154000"
st "memX"
blo "128000,153800"
tm "WireNameMgr"
)
)
on &28
)
*230 (Wire
uid 3751,0
shape (OrthoPolyLine
uid 3752,0
va (VaSet
vasetType 3
)
xt "106000,130000,109250,130000"
pts [
"106000,130000"
"109250,130000"
]
)
end &186
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3755,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3756,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,128600,110100,130000"
st "reset"
blo "106000,129800"
tm "WireNameMgr"
)
)
on &13
)
*231 (Wire
uid 3757,0
shape (OrthoPolyLine
uid 3758,0
va (VaSet
vasetType 3
)
xt "106000,128000,109250,128000"
pts [
"106000,128000"
"109250,128000"
]
)
end &185
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3761,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3762,0
va (VaSet
font "Verdana,12,0"
)
xt "106000,126600,109800,128000"
st "clock"
blo "106000,127800"
tm "WireNameMgr"
)
)
on &12
)
*232 (Wire
uid 3763,0
shape (OrthoPolyLine
uid 3764,0
va (VaSet
vasetType 3
)
xt "70000,134000,77250,134000"
pts [
"70000,134000"
"77250,134000"
]
)
end &138
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3767,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3768,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,132600,79800,134000"
st "updatePattern"
blo "69000,133800"
tm "WireNameMgr"
)
)
on &20
)
*233 (Wire
uid 3769,0
shape (OrthoPolyLine
uid 3770,0
va (VaSet
vasetType 3
)
xt "94750,124000,109250,136000"
pts [
"94750,136000"
"102000,136000"
"102000,124000"
"109250,124000"
]
)
start &137
end &184
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3771,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3772,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,122600,109100,124000"
st "memEnY"
blo "103000,123800"
tm "WireNameMgr"
)
)
on &32
)
*234 (Wire
uid 3773,0
shape (OrthoPolyLine
uid 3774,0
va (VaSet
vasetType 3
)
xt "94750,122000,109250,134000"
pts [
"94750,134000"
"100000,134000"
"100000,122000"
"109250,122000"
]
)
start &135
end &187
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3775,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3776,0
va (VaSet
font "Verdana,12,0"
)
xt "103000,120600,109300,122000"
st "memWrY"
blo "103000,121800"
tm "WireNameMgr"
)
)
on &31
)
*235 (Wire
uid 3777,0
shape (OrthoPolyLine
uid 3778,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "94750,106000,109250,118000"
pts [
"94750,106000"
"98000,106000"
"98000,118000"
"109250,118000"
]
)
start &129
end &188
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3779,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3780,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,116600,109400,118000"
st "addrY"
blo "105000,117800"
tm "WireNameMgr"
)
)
on &30
)
*236 (Wire
uid 3793,0
shape (OrthoPolyLine
uid 3794,0
va (VaSet
vasetType 3
)
xt "72000,110000,98000,130000"
pts [
"94750,130000"
"98000,130000"
"98000,124000"
"72000,124000"
"72000,110000"
"77250,110000"
]
)
start &140
end &125
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3795,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3796,0
va (VaSet
font "Verdana,12,0"
)
xt "72000,108600,77800,110000"
st "cntIncrY"
blo "72000,109800"
tm "WireNameMgr"
)
)
on &29
)
*237 (Wire
uid 3797,0
shape (OrthoPolyLine
uid 3798,0
va (VaSet
vasetType 3
)
xt "70000,136000,77250,136000"
pts [
"77250,136000"
"70000,136000"
]
)
start &141
end &62
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3801,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3802,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,134600,78600,136000"
st "newPolynom"
blo "69000,135800"
tm "WireNameMgr"
)
)
on &14
)
*238 (Wire
uid 3803,0
shape (OrthoPolyLine
uid 3804,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,106000,77250,106000"
pts [
"70000,106000"
"77250,106000"
]
)
end &130
sat 16
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3807,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3808,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,104600,77900,106000"
st "patternSize"
blo "69000,105800"
tm "WireNameMgr"
)
)
on &21
)
*239 (Wire
uid 3809,0
shape (OrthoPolyLine
uid 3810,0
va (VaSet
vasetType 3
)
xt "70000,108000,77250,108000"
pts [
"70000,108000"
"77250,108000"
]
)
end &128
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3813,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3814,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,106600,79800,108000"
st "updatePattern"
blo "69000,107800"
tm "WireNameMgr"
)
)
on &20
)
*240 (Wire
uid 3815,0
shape (OrthoPolyLine
uid 3816,0
va (VaSet
vasetType 3
)
xt "74000,140000,77250,140000"
pts [
"74000,140000"
"77250,140000"
]
)
end &142
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3819,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3820,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,138600,77800,140000"
st "clock"
blo "74000,139800"
tm "WireNameMgr"
)
)
on &12
)
*241 (Wire
uid 3866,0
shape (OrthoPolyLine
uid 3867,0
va (VaSet
vasetType 3
)
xt "74000,114000,77250,114000"
pts [
"74000,114000"
"77250,114000"
]
)
end &126
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3872,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3873,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,112600,77800,114000"
st "clock"
blo "74000,113800"
tm "WireNameMgr"
)
)
on &12
)
*242 (Wire
uid 3874,0
shape (OrthoPolyLine
uid 3875,0
va (VaSet
vasetType 3
)
xt "74000,116000,77250,116000"
pts [
"74000,116000"
"77250,116000"
]
)
end &127
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3880,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3881,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,114600,78100,116000"
st "reset"
blo "74000,115800"
tm "WireNameMgr"
)
)
on &13
)
*243 (Wire
uid 3882,0
shape (OrthoPolyLine
uid 3883,0
va (VaSet
vasetType 3
)
xt "74000,142000,77250,142000"
pts [
"74000,142000"
"77250,142000"
]
)
end &143
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3888,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3889,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,140600,78100,142000"
st "reset"
blo "74000,141800"
tm "WireNameMgr"
)
)
on &13
)
*244 (Wire
uid 3907,0
shape (OrthoPolyLine
uid 3908,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "126750,116000,134000,116000"
pts [
"126750,116000"
"134000,116000"
]
)
start &183
end &41
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3911,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3912,0
va (VaSet
font "Verdana,12,0"
)
xt "128750,114600,133250,116000"
st "memY"
blo "128750,115800"
tm "WireNameMgr"
)
)
on &33
)
*245 (Wire
uid 4047,0
shape (OrthoPolyLine
uid 4048,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "135000,4000,143000,4000"
pts [
"135000,4000"
"143000,4000"
]
)
start &36
end &34
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4051,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4052,0
va (VaSet
font "Verdana,12,0"
)
xt "138000,2600,143600,4000"
st "testOut"
blo "138000,3800"
tm "WireNameMgr"
)
)
on &35
)
*246 (Wire
uid 7907,0
shape (OrthoPolyLine
uid 7908,0
va (VaSet
vasetType 3
)
xt "70000,132000,77250,132000"
pts [
"70000,132000"
"77250,132000"
]
)
end &139
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7913,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7914,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,130600,74000,132000"
st "write"
blo "70000,131800"
tm "WireNameMgr"
)
)
on &57
)
*247 (Wire
uid 7915,0
shape (OrthoPolyLine
uid 7916,0
va (VaSet
vasetType 3
)
xt "70000,182000,77250,182000"
pts [
"70000,182000"
"77250,182000"
]
)
end &162
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 7921,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7922,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,180600,74000,182000"
st "write"
blo "70000,181800"
tm "WireNameMgr"
)
)
on &57
)
*248 (Wire
uid 8150,0
shape (OrthoPolyLine
uid 8151,0
va (VaSet
vasetType 3
)
xt "104000,44000,109000,44000"
pts [
"104000,44000"
"109000,44000"
]
)
end &45
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 8154,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 8155,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,42600,111300,44000"
st "interpolateLin"
blo "101000,43800"
tm "WireNameMgr"
)
)
on &40
)
*249 (Wire
uid 16718,0
shape (OrthoPolyLine
uid 16719,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "26000,44000,50000,72000"
pts [
"29250,72000"
"26000,72000"
"26000,64000"
"50000,64000"
"50000,44000"
"46000,44000"
]
)
start &116
end &47
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 16722,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 16723,0
va (VaSet
font "Verdana,12,0"
)
xt "48000,42600,51700,44000"
st "addr"
blo "48000,43800"
tm "WireNameMgr"
)
)
on &51
)
*250 (Wire
uid 17156,0
optionalChildren [
*251 (BdJunction
uid 18482,0
ps "OnConnectorStrategy"
shape (Circle
uid 18483,0
va (VaSet
vasetType 1
)
xt "61600,99600,62400,100400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 17157,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,94000,109250,116000"
pts [
"109250,116000"
"106000,116000"
"106000,100000"
"62000,100000"
"62000,94000"
]
)
start &182
end &52
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17160,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17161,0
va (VaSet
font "Verdana,12,0"
)
xt "102000,114600,110100,116000"
st "memDataIn"
blo "102000,115800"
tm "WireNameMgr"
)
)
on &56
)
*252 (Wire
uid 17164,0
shape (OrthoPolyLine
uid 17165,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62000,100000,109250,154000"
pts [
"109250,154000"
"106000,154000"
"106000,150000"
"62000,150000"
"62000,100000"
]
)
start &171
end &251
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17170,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17171,0
va (VaSet
font "Verdana,12,0"
)
xt "101000,152600,109100,154000"
st "memDataIn"
blo "101000,153800"
tm "WireNameMgr"
)
)
on &56
)
*253 (Wire
uid 17515,0
shape (OrthoPolyLine
uid 17516,0
va (VaSet
vasetType 3
)
xt "46000,46000,54000,46000"
pts [
"46000,46000"
"54000,46000"
]
)
start &47
sat 2
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 17521,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 17522,0
va (VaSet
font "Verdana,12,0"
)
xt "51000,44600,55000,46000"
st "write"
blo "51000,45800"
tm "WireNameMgr"
)
)
on &57
)
*254 (Wire
uid 18258,0
shape (OrthoPolyLine
uid 18259,0
va (VaSet
vasetType 3
)
xt "70000,76000,77250,76000"
pts [
"70000,76000"
"77250,76000"
]
)
end &110
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 18264,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 18265,0
va (VaSet
font "Verdana,12,0"
)
xt "70000,74600,74000,76000"
st "write"
blo "70000,75800"
tm "WireNameMgr"
)
)
on &57
)
*255 (Wire
uid 19648,0
shape (OrthoPolyLine
uid 19649,0
va (VaSet
vasetType 3
)
xt "22000,4000,30000,4000"
pts [
"22000,4000"
"30000,4000"
]
)
start &63
end &83
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19652,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19653,0
va (VaSet
font "Verdana,12,0"
)
xt "24000,2600,27500,4000"
st "hClk"
blo "24000,3800"
tm "WireNameMgr"
)
)
on &64
)
*256 (Wire
uid 19662,0
shape (OrthoPolyLine
uid 19663,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,22000,30000,22000"
pts [
"30000,22000"
"22000,22000"
]
)
start &58
end &65
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19666,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19667,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,20600,27400,22000"
st "hRData"
blo "22000,21800"
tm "WireNameMgr"
)
)
on &66
)
*257 (Wire
uid 19676,0
shape (OrthoPolyLine
uid 19677,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,42000,30000,42000"
pts [
"22000,42000"
"30000,42000"
]
)
start &67
end &47
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19680,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19681,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,40600,26500,42000"
st "hAddr"
blo "22000,41800"
tm "WireNameMgr"
)
)
on &68
)
*258 (Wire
uid 19690,0
shape (OrthoPolyLine
uid 19691,0
va (VaSet
vasetType 3
)
xt "22000,6000,30000,6000"
pts [
"22000,6000"
"30000,6000"
]
)
start &69
end &83
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19694,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19695,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,4600,28800,6000"
st "hReset_n"
blo "22000,5800"
tm "WireNameMgr"
)
)
on &70
)
*259 (Wire
uid 19704,0
shape (OrthoPolyLine
uid 19705,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,44000,30000,44000"
pts [
"22000,44000"
"30000,44000"
]
)
start &71
end &47
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19708,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19709,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,42600,27900,44000"
st "hWData"
blo "22000,43800"
tm "WireNameMgr"
)
)
on &72
)
*260 (Wire
uid 19718,0
shape (OrthoPolyLine
uid 19719,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "22000,46000,30000,46000"
pts [
"22000,46000"
"30000,46000"
]
)
start &73
end &47
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19722,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19723,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,44600,27100,46000"
st "hTrans"
blo "22000,45800"
tm "WireNameMgr"
)
)
on &74
)
*261 (Wire
uid 19732,0
shape (OrthoPolyLine
uid 19733,0
va (VaSet
vasetType 3
)
xt "22000,48000,30000,48000"
pts [
"22000,48000"
"30000,48000"
]
)
start &75
end &47
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19736,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19737,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,46600,27000,48000"
st "hWrite"
blo "22000,47800"
tm "WireNameMgr"
)
)
on &76
)
*262 (Wire
uid 19746,0
shape (OrthoPolyLine
uid 19747,0
va (VaSet
vasetType 3
)
xt "22000,50000,30000,50000"
pts [
"22000,50000"
"30000,50000"
]
)
start &77
end &47
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19750,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19751,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,48600,25500,50000"
st "hSel"
blo "22000,49800"
tm "WireNameMgr"
)
)
on &78
)
*263 (Wire
uid 19760,0
shape (OrthoPolyLine
uid 19761,0
va (VaSet
vasetType 3
)
xt "22000,24000,30000,24000"
pts [
"30000,24000"
"22000,24000"
]
)
start &58
end &79
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19764,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19765,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,22600,27500,24000"
st "hReady"
blo "22000,23800"
tm "WireNameMgr"
)
)
on &80
)
*264 (Wire
uid 19774,0
shape (OrthoPolyLine
uid 19775,0
va (VaSet
vasetType 3
)
xt "22000,26000,30000,26000"
pts [
"30000,26000"
"22000,26000"
]
)
start &58
end &81
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 19778,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 19779,0
va (VaSet
font "Verdana,12,0"
)
xt "22000,24600,26700,26000"
st "hResp"
blo "22000,25800"
tm "WireNameMgr"
)
)
on &82
)
*265 (Wire
uid 20275,0
shape (OrthoPolyLine
uid 20276,0
va (VaSet
vasetType 3
)
xt "46000,6000,54000,6000"
pts [
"46000,6000"
"54000,6000"
]
)
start &83
sat 2
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 20281,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20282,0
va (VaSet
font "Verdana,12,0"
)
xt "48000,4600,52100,6000"
st "reset"
blo "48000,5800"
tm "WireNameMgr"
)
)
on &13
)
*266 (Wire
uid 20283,0
shape (OrthoPolyLine
uid 20284,0
va (VaSet
vasetType 3
)
xt "46000,4000,54000,4000"
pts [
"46000,4000"
"54000,4000"
]
)
start &83
sat 2
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 20289,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20290,0
va (VaSet
font "Verdana,12,0"
)
xt "48000,2600,51800,4000"
st "clock"
blo "48000,3800"
tm "WireNameMgr"
)
)
on &12
)
*267 (Wire
uid 20547,0
shape (OrthoPolyLine
uid 20548,0
va (VaSet
vasetType 3
)
xt "94750,42000,102000,42000"
pts [
"94750,42000"
"102000,42000"
]
)
start &90
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 20551,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20552,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,40600,101300,42000"
st "run_int"
blo "96000,41800"
tm "WireNameMgr"
)
)
on &87
)
*268 (Wire
uid 20557,0
shape (OrthoPolyLine
uid 20558,0
va (VaSet
vasetType 3
)
xt "94750,44000,102000,44000"
pts [
"94750,44000"
"102000,44000"
]
)
start &98
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 20561,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 20562,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,42600,108700,44000"
st "interpolateLin_int"
blo "96000,43800"
tm "WireNameMgr"
)
)
on &88
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *269 (PackageList
uid 42,0
stg "VerticalLayoutStrategy"
textVec [
*270 (Text
uid 43,0
va (VaSet
font "Verdana,8,1"
)
xt "0,0,6900,1000"
st "Package List"
blo "0,800"
)
*271 (MLText
uid 44,0
va (VaSet
)
xt "0,1000,17500,4600"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 45,0
stg "VerticalLayoutStrategy"
textVec [
*272 (Text
uid 46,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,0,30200,1000"
st "Compiler Directives"
blo "20000,800"
)
*273 (Text
uid 47,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,1000,32200,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*274 (MLText
uid 48,0
va (VaSet
isHidden 1
)
xt "20000,2000,32100,4400"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*275 (Text
uid 49,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,4000,32800,5000"
st "Post-module directives:"
blo "20000,4800"
)
*276 (MLText
uid 50,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
*277 (Text
uid 51,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "20000,5000,32400,6000"
st "End-module directives:"
blo "20000,5800"
)
*278 (MLText
uid 52,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "-2784,-2784,374267,202077"
cachedDiagramExtent "-6900,0,167000,198000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN,winspool,"
fileName "ipp://ippsion.hevs.ch/ipp/PREA309_HPLJ3005DN"
toPrinter 1
colour 1
xMargin 47
yMargin 47
paperWidth 761
paperHeight 1077
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4 (210 x 297 mm)"
unixPaperName "A4  (210mm x 297mm)"
windowsPaperName "A4 (210 x 297 mm)"
windowsPaperType 9
scale 50
useAdjustTo 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 21727,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*279 (Text
va (VaSet
)
xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*280 (Text
va (VaSet
)
xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*281 (Text
va (VaSet
)
xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1700,13200,1700,13200"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*282 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*283 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*284 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*285 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*286 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*287 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*288 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*289 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*290 (Text
va (VaSet
)
xt "950,5500,1550,6500"
st "I0"
blo "950,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6050,1500,-6050,1500"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-50,0,8050,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*291 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*292 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*293 (Text
va (VaSet
)
xt "450,5500,1050,6500"
st "I0"
blo "450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6550,1500,-6550,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*294 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*295 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1500,2200"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,9600,2200"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,18500,100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*296 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*297 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,11000,100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*298 (Text
va (VaSet
font "Verdana,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*299 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Verdana,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "0,99400,7000,100400"
st "Declarations"
blo "0,100200"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,8,1"
)
xt "0,100300,3400,101300"
st "Ports:"
blo "0,101100"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "0,116500,4800,117500"
st "Pre User:"
blo "0,117300"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,117400,23800,119400"
st "constant addressBitNb: positive := hAddr'length;
constant dataBitNb : positive := hWData'length;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,8,1"
)
xt "0,119200,9000,120200"
st "Diagram Signals:"
blo "0,120000"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "0,99400,6000,100400"
st "Post User:"
blo "0,100200"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "0,99400,0,99400"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
ordering 1
suid 92,0
usingSuid 1
emptyRow *300 (LEmptyRow
)
uid 10774,0
optionalChildren [
*301 (RefLabelRowHdr
)
*302 (TitleRowHdr
)
*303 (FilterRowHdr
)
*304 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*305 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*306 (GroupColHdr
tm "GroupColHdrMgr"
)
*307 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
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*308 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
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*309 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
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*310 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
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*311 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
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*312 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
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*313 (LeafLogPort
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m 4
decl (Decl
n "clock"
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o 18
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*314 (LeafLogPort
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m 4
decl (Decl
n "reset"
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o 19
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uid 10645,0
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*315 (LeafLogPort
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decl (Decl
n "newPolynom"
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o 7
suid 10,0
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)
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*316 (LeafLogPort
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m 4
decl (Decl
n "selControl"
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o 32
suid 33,0
)
)
uid 10697,0
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*317 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selSpeed"
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o 33
suid 35,0
)
)
uid 10701,0
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*318 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selX"
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o 34
suid 36,0
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)
uid 10703,0
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*319 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selY"
t "std_ulogic"
o 35
suid 37,0
)
)
uid 10705,0
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*320 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "run"
t "std_ulogic"
o 4
suid 38,0
)
)
uid 10707,0
)
*321 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "updatePattern"
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o 36
suid 39,0
)
)
uid 10709,0
)
*322 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "patternSize"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 31
suid 40,0
)
)
uid 10711,0
)
*323 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dataOut"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 26
suid 41,0
)
)
uid 10713,0
)
*324 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "updatePeriod"
t "unsigned"
b "(updatePeriodBitNb-1 DOWNTO 0)"
o 5
suid 42,0
)
)
uid 10715,0
)
*325 (LeafLogPort
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m 4
decl (Decl
n "addrX"
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b "(patternAddressBitNb-1 DOWNTO 0)"
o 21
suid 44,0
)
)
uid 10719,0
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*326 (LeafLogPort
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m 4
decl (Decl
n "cntIncrX"
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o 23
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*327 (LeafLogPort
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m 4
decl (Decl
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o 29
suid 46,0
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)
uid 10723,0
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*328 (LeafLogPort
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m 4
decl (Decl
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o 27
suid 47,0
)
)
uid 10725,0
)
*329 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "memX"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 2
suid 48,0
)
)
uid 10727,0
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*330 (LeafLogPort
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m 4
decl (Decl
n "cntIncrY"
t "std_ulogic"
o 24
suid 49,0
)
)
uid 10729,0
)
*331 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addrY"
t "unsigned"
b "(patternAddressBitNb-1 DOWNTO 0)"
o 22
suid 50,0
)
)
uid 10731,0
)
*332 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memWrY"
t "std_ulogic"
o 30
suid 51,0
)
)
uid 10733,0
)
*333 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memEnY"
t "std_ulogic"
o 28
suid 52,0
)
)
uid 10735,0
)
*334 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "memY"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 3
suid 53,0
)
)
uid 10737,0
)
*335 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 1
suid 54,0
)
)
uid 10739,0
)
*336 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "interpolateLin"
t "std_ulogic"
o 6
suid 70,0
)
)
uid 10771,0
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*337 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 25
suid 74,0
)
)
uid 16726,0
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*338 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "addr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 20
suid 75,0
)
)
uid 16728,0
)
*339 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(signalBitNb-1 DOWNTO 0)"
o 38
suid 77,0
)
)
uid 17172,0
)
*340 (LeafLogPort
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m 4
decl (Decl
n "write"
t "std_ulogic"
o 37
suid 78,0
)
)
uid 17556,0
)
*341 (LeafLogPort
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decl (Decl
n "hClk"
t "std_ulogic"
o 8
suid 79,0
)
)
uid 19623,0
)
*342 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 9
suid 80,0
)
)
uid 19625,0
)
*343 (LeafLogPort
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decl (Decl
n "hAddr"
t "unsigned"
b "(ahbAddressBitNb-1 downto 0)"
o 10
suid 81,0
)
)
uid 19627,0
)
*344 (LeafLogPort
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decl (Decl
n "hReset_n"
t "std_ulogic"
o 11
suid 82,0
)
)
uid 19629,0
)
*345 (LeafLogPort
port (LogicalPort
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 12
suid 83,0
)
)
uid 19631,0
)
*346 (LeafLogPort
port (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 downto 0)"
o 13
suid 84,0
)
)
uid 19633,0
)
*347 (LeafLogPort
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decl (Decl
n "hWrite"
t "std_ulogic"
o 14
suid 85,0
)
)
uid 19635,0
)
*348 (LeafLogPort
port (LogicalPort
decl (Decl
n "hSel"
t "std_ulogic"
o 15
suid 86,0
)
)
uid 19637,0
)
*349 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_ulogic"
o 16
suid 87,0
)
)
uid 19639,0
)
*350 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_ulogic"
o 17
suid 88,0
)
)
uid 19641,0
)
*351 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "run_int"
t "std_ulogic"
o 39
suid 90,0
)
)
uid 20565,0
)
*352 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "interpolateLin_int"
t "std_ulogic"
o 40
suid 92,0
)
)
uid 20567,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 10787,0
optionalChildren [
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sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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emptyMRCItem *354 (MRCItem
litem &300
pos 40
dimension 20
)
uid 10789,0
optionalChildren [
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litem &301
pos 0
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uid 10790,0
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*357 (MRCItem
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*359 (MRCItem
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*360 (MRCItem
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*362 (MRCItem
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*363 (MRCItem
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*364 (MRCItem
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*365 (MRCItem
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*367 (MRCItem
litem &322
pos 25
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*368 (MRCItem
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*369 (MRCItem
litem &324
pos 5
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uid 10716,0
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*370 (MRCItem
litem &325
pos 26
dimension 20
uid 10720,0
)
*371 (MRCItem
litem &326
pos 27
dimension 20
uid 10722,0
)
*372 (MRCItem
litem &327
pos 28
dimension 20
uid 10724,0
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*373 (MRCItem
litem &328
pos 29
dimension 20
uid 10726,0
)
*374 (MRCItem
litem &329
pos 6
dimension 20
uid 10728,0
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*375 (MRCItem
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pos 30
dimension 20
uid 10730,0
)
*376 (MRCItem
litem &331
pos 31
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uid 10732,0
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*377 (MRCItem
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pos 32
dimension 20
uid 10734,0
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*378 (MRCItem
litem &333
pos 33
dimension 20
uid 10736,0
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*379 (MRCItem
litem &334
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dimension 20
uid 10738,0
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*380 (MRCItem
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uid 10740,0
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*381 (MRCItem
litem &336
pos 8
dimension 20
uid 10772,0
)
*382 (MRCItem
litem &337
pos 34
dimension 20
uid 16727,0
)
*383 (MRCItem
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pos 35
dimension 20
uid 16729,0
)
*384 (MRCItem
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pos 36
dimension 20
uid 17173,0
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*385 (MRCItem
litem &340
pos 37
dimension 20
uid 17557,0
)
*386 (MRCItem
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pos 1
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uid 19622,0
)
*387 (MRCItem
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pos 2
dimension 20
uid 19624,0
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*388 (MRCItem
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pos 0
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uid 19626,0
)
*389 (MRCItem
litem &344
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dimension 20
uid 19628,0
)
*390 (MRCItem
litem &345
pos 11
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uid 19630,0
)
*391 (MRCItem
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*392 (MRCItem
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pos 13
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uid 19634,0
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uid 19636,0
)
*394 (MRCItem
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pos 15
dimension 20
uid 19638,0
)
*395 (MRCItem
litem &350
pos 16
dimension 20
uid 19640,0
)
*396 (MRCItem
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pos 38
dimension 20
uid 20566,0
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*397 (MRCItem
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pos 39
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uid 20568,0
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]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 10793,0
optionalChildren [
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pos 0
dimension 20
uid 10794,0
)
*399 (MRCItem
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pos 1
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)
*400 (MRCItem
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pos 2
dimension 100
uid 10796,0
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*401 (MRCItem
litem &308
pos 3
dimension 50
uid 10797,0
)
*402 (MRCItem
litem &309
pos 4
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uid 10798,0
)
*403 (MRCItem
litem &310
pos 5
dimension 100
uid 10799,0
)
*404 (MRCItem
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pos 6
dimension 50
uid 10800,0
)
*405 (MRCItem
litem &312
pos 7
dimension 80
uid 10801,0
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]
)
fixedCol 4
fixedRow 2
name "Ports"
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vaOverrides [
]
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uid 10773,0
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genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *406 (LEmptyRow
)
uid 10803,0
optionalChildren [
*407 (RefLabelRowHdr
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*408 (TitleRowHdr
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*409 (FilterRowHdr
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*410 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*411 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*412 (GroupColHdr
tm "GroupColHdrMgr"
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*413 (NameColHdr
tm "GenericNameColHdrMgr"
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*414 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*415 (InitColHdr
tm "GenericValueColHdrMgr"
)
*416 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*417 (EolColHdr
tm "GenericEolColHdrMgr"
)
*418 (LogGeneric
generic (GiElement
name "testOutBitNb"
type "positive"
value "16"
)
uid 12900,0
)
*419 (LogGeneric
generic (GiElement
name "updatePeriodBitNb"
type "positive"
value "16"
)
uid 15331,0
)
*420 (LogGeneric
generic (GiElement
name "signalBitNb"
type "positive"
value "16"
)
uid 16243,0
)
*421 (LogGeneric
generic (GiElement
name "patternAddressBitNb"
type "positive"
value "8"
)
uid 17007,0
)
]
)
pdm (PhysicalDM
uid 10815,0
optionalChildren [
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sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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uid 10817,0
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propVa (MVa
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fixedCol 3
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uid 10802,0
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