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value "U:\\SEm_curves\\Synthesis" ) (vvPair variable "mm" value "03" ) (vvPair variable "module_name" value "blockRAM" ) (vvPair variable "month" value "Mar" ) (vvPair variable "month_long" value "March" ) (vvPair variable "p" value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/block@r@a@m/symbol.sb" ) (vvPair variable "p_logical" value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/blockRAM/symbol.sb" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "systemOnChip" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_ADMS" value "" ) (vvPair variable "task_AsmPath" value "$HEI_LIBS_DIR/NanoBlaze/hdl" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$ISE_WORK_DIR" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME/modeltech/bin" ) (vvPair variable "task_NC" value "" ) (vvPair variable "task_PrecisionRTLPath" value "" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "sb" ) (vvPair variable "this_file" value "symbol" ) (vvPair variable "this_file_logical" value "symbol" ) (vvPair variable "time" value "14:40:20" ) (vvPair variable "unit" value "blockRAM" ) (vvPair variable "user" value "francois" ) (vvPair variable "version" value "2018.1 (Build 12)" ) (vvPair variable "view" value "symbol" ) (vvPair variable "year" value "2019" ) (vvPair variable "yy" value "19" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 51,0 optionalChildren [ *71 (SymbolBody uid 8,0 optionalChildren [ *72 (CptPort uid 83,0 ps "OnEdgeStrategy" shape (Triangle uid 88,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "37250,12625,38000,13375" ) tg (CPTG uid 85,0 ps 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