DocumentHdrVersion "1.1" Header (DocumentHdr version 2 dialect 11 dmPackageRefs [ (DmPackageRef library "ieee" unitName "std_logic_1164" ) (DmPackageRef library "ieee" unitName "numeric_std" itemName "ALL" ) ] instances [ (Instance name "I_DUT" duLibraryName "PipelinedOperators" duName "pipelineCounter" elements [ (GiElement name "bitNb" type "positive" value "counterBitNb" ) (GiElement name "stageNb" type "positive" value "pipelineStageNb" ) ] mwi 0 uid 2719,0 ) (Instance name "I_tester" duLibraryName "PipelinedOperators_test" duName "PipelineCounter_tester" elements [ (GiElement name "counterBitNb" type "integer" value "counterBitNb" ) (GiElement name "clockFrequency" type "real" value "clockFrequency" ) ] mwi 0 uid 2970,0 ) ] libraryRefs [ "ieee" ] ) version "32.1" appVersion "2019.2 (Build 5)" noEmbeddedEditors 1 model (BlockDiag VExpander (VariableExpander vvMap [ (vvPair variable " " value " " ) (vvPair variable "HDLDir" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hdl" ) (vvPair variable "HDSDir" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds" ) (vvPair variable "SideDataDesignDir" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb\\struct.bd.info" ) (vvPair variable "SideDataUserDir" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb\\struct.bd.user" ) (vvPair variable "SourceDir" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds" ) (vvPair variable "appl" value "HDL Designer" ) (vvPair variable "arch_name" value "struct" ) (vvPair variable "asm_file" value "beamer.asm" ) (vvPair variable "concat_file" value "concatenated" ) (vvPair variable "config" value "%(unit)_%(view)_config" ) (vvPair variable "d" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb" ) (vvPair variable "d_logical" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tb" ) (vvPair variable "date" value "28.04.2023" ) (vvPair variable "day" value "ven." ) (vvPair variable "day_long" value "vendredi" ) (vvPair variable "dd" value "28" ) (vvPair variable "designName" value "$DESIGN_NAME" ) (vvPair variable "entity_name" value "pipelineCounter_tb" ) (vvPair variable "ext" value "" ) (vvPair variable "f" value "struct.bd" ) (vvPair variable "f_logical" value "struct.bd" ) (vvPair variable "f_noext" value "struct" ) (vvPair variable "graphical_source_author" value "axel.amand" ) (vvPair variable "graphical_source_date" value "28.04.2023" ) (vvPair variable "graphical_source_group" value "UNKNOWN" ) (vvPair variable "graphical_source_host" value "WE7860" ) (vvPair variable "graphical_source_time" value "15:21:02" ) (vvPair variable "group" value "UNKNOWN" ) (vvPair variable "host" value "WE7860" ) (vvPair variable "language" value "VHDL" ) (vvPair variable "library" value "PipelinedOperators_test" ) (vvPair variable "library_downstream_ModelSim" value "D:\\Users\\ELN_labs\\VHDL_comp" ) (vvPair variable "library_downstream_ModelSimCompiler" value "$SCRATCH_DIR/PipelinedOperators_test" ) (vvPair variable "mm" value "04" ) (vvPair variable "module_name" value "pipelineCounter_tb" ) (vvPair variable "month" value "avr." ) (vvPair variable "month_long" value "avril" ) (vvPair variable "p" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipeline@counter_tb\\struct.bd" ) (vvPair variable "p_logical" value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\PipelinedOperators_test\\hds\\pipelineCounter_tb\\struct.bd" ) (vvPair variable "package_name" value "" ) (vvPair variable "project_name" value "hds" ) (vvPair variable "series" value "HDL Designer Series" ) (vvPair variable "task_ADMS" value "" ) (vvPair variable "task_AsmPath" value "$HEI_LIBS_DIR/NanoBlaze/hdl" ) (vvPair variable "task_DesignCompilerPath" value "" ) (vvPair variable "task_HDSPath" value "$HDS_HOME" ) (vvPair variable "task_ISEBinPath" value "$ISE_HOME" ) (vvPair variable "task_ISEPath" value "$ISE_WORK_DIR" ) (vvPair variable "task_LeonardoPath" value "" ) (vvPair variable "task_ModelSimPath" value "$MODELSIM_HOME/modeltech/bin" ) (vvPair variable "task_NC" value "" ) (vvPair variable "task_PrecisionRTLPath" value "" ) (vvPair variable "task_QuestaSimPath" value "" ) (vvPair variable "task_VCSPath" value "" ) (vvPair variable "this_ext" value "bd" ) (vvPair variable "this_file" value "struct" ) (vvPair variable "this_file_logical" value "struct" ) (vvPair variable "time" value "15:21:02" ) (vvPair variable "unit" value "pipelineCounter_tb" ) (vvPair variable "user" value "axel.amand" ) (vvPair variable "version" value "2019.2 (Build 5)" ) (vvPair variable "view" value "struct" ) (vvPair variable "year" value "2023" ) (vvPair variable "yy" value "23" ) ] ) LanguageMgr "Vhdl2008LangMgr" uid 153,0 optionalChildren [ *1 (Grouping uid 110,0 optionalChildren [ *2 (CommentText uid 112,0 shape (Rectangle uid 113,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "36000,48000,53000,49000" ) oxt "18000,70000,35000,71000" text (MLText uid 114,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "36200,48500,36200,48500" st " by %user on %dd %month %year " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 ) *3 (CommentText uid 115,0 shape (Rectangle uid 116,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,44000,57000,45000" ) oxt "35000,66000,39000,67000" text (MLText uid 117,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "53200,44500,53200,44500" st " Project: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 ) *4 (CommentText uid 118,0 shape (Rectangle uid 119,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "36000,46000,53000,47000" ) oxt "18000,68000,35000,69000" text (MLText uid 120,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "36200,46500,36200,46500" st " " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 ) *5 (CommentText uid 121,0 shape (Rectangle uid 122,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,46000,36000,47000" ) oxt "14000,68000,18000,69000" text (MLText uid 123,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "32200,46500,32200,46500" st " Title: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 ) *6 (CommentText uid 124,0 shape (Rectangle uid 125,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "53000,45000,73000,49000" ) oxt "35000,67000,55000,71000" text (MLText uid 126,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "53200,45200,67300,46400" st " " tm "CommentText" wrapOption 3 visibleHeight 4000 visibleWidth 20000 ) ignorePrefs 1 ) *7 (CommentText uid 127,0 shape (Rectangle uid 128,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "57000,44000,73000,45000" ) oxt "39000,66000,55000,67000" text (MLText uid 129,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "57200,44500,57200,44500" st " " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 16000 ) position 1 ignorePrefs 1 ) *8 (CommentText uid 130,0 shape (Rectangle uid 131,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,44000,53000,46000" ) oxt "14000,66000,35000,68000" text (MLText uid 132,0 va (VaSet fg "32768,0,0" ) xt "37350,44400,47650,45600" st " " ju 0 tm "CommentText" wrapOption 3 visibleHeight 2000 visibleWidth 21000 ) position 1 ignorePrefs 1 ) *9 (CommentText uid 133,0 shape (Rectangle uid 134,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,47000,36000,48000" ) oxt "14000,69000,18000,70000" text (MLText uid 135,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "32200,47500,32200,47500" st " Path: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 ) *10 (CommentText uid 136,0 shape (Rectangle uid 137,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "32000,48000,36000,49000" ) oxt "14000,70000,18000,71000" text (MLText uid 138,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "32200,48500,32200,48500" st " Edited: " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 4000 ) position 1 ignorePrefs 1 ) *11 (CommentText uid 139,0 shape (Rectangle uid 140,0 sl 0 va (VaSet vasetType 1 fg "65280,65280,46080" ) xt "36000,47000,53000,48000" ) oxt "18000,69000,35000,70000" text (MLText uid 141,0 va (VaSet fg "0,0,32768" bg "0,0,32768" ) xt "36200,47500,36200,47500" st " %library/%unit/%view " tm "CommentText" wrapOption 3 visibleHeight 1000 visibleWidth 17000 ) position 1 ignorePrefs 1 ) ] shape (GroupingShape uid 111,0 va (VaSet vasetType 1 fg "65535,65535,65535" lineStyle 2 lineWidth 2 ) xt "32000,44000,73000,49000" ) oxt "14000,66000,55000,71000" ) *12 (Net uid 2648,0 decl (Decl n "reset" t "std_ulogic" o 3 suid 25,0 ) declText (MLText uid 2649,0 va (VaSet font "Verdana,8,0" ) xt "2000,15200,14600,16200" st "SIGNAL reset : std_ulogic" ) ) *13 (Net uid 2656,0 decl (Decl n "clock" t "std_ulogic" o 1 suid 26,0 ) declText (MLText uid 2657,0 va (VaSet font "Verdana,8,0" ) xt "2000,13200,14600,14200" st "SIGNAL clock : std_ulogic" ) ) *14 (SaComponent uid 2719,0 optionalChildren [ *15 (CptPort uid 2707,0 ps "OnEdgeStrategy" shape (Triangle uid 2708,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "46000,17625,46750,18375" ) tg (CPTG uid 2709,0 ps "CptPortTextPlaceStrategy" stg "RightVerticalLayoutStrategy" f (Text uid 2710,0 va (VaSet ) xt "41000,17550,45000,18450" st "countOut" ju 2 blo "45000,18250" ) ) thePort (LogicalPort m 1 decl (Decl n "countOut" t "unsigned" b "(bitNb-1 downto 0)" o 1 suid 1,0 ) ) ) *16 (CptPort uid 2711,0 ps "OnEdgeStrategy" shape (Triangle uid 2712,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "29250,17625,30000,18375" ) tg (CPTG uid 2713,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 2714,0 va (VaSet ) xt "31000,17400,33500,18300" st "clock" blo "31000,18100" ) ) thePort (LogicalPort decl (Decl n "clock" t "std_ulogic" o 2 suid 2,0 ) ) ) *17 (CptPort uid 2715,0 ps "OnEdgeStrategy" shape (Triangle uid 2716,0 ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "29250,19625,30000,20375" ) tg (CPTG uid 2717,0 ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text uid 2718,0 va (VaSet ) xt "31000,19550,33500,20450" st "reset" blo "31000,20250" ) ) thePort (LogicalPort decl (Decl n "reset" t "std_ulogic" o 3 suid 3,0 ) ) ) ] shape (Rectangle uid 2720,0 va (VaSet vasetType 1 fg "0,65535,0" bg "0,65535,0" lineColor "0,32896,0" lineWidth 2 ) xt "30000,14000,46000,22000" ) oxt "32000,15000,48000,23000" ttg (MlTextGroup uid 2721,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *18 (Text uid 2722,0 va (VaSet font "Verdana,9,1" ) xt "30600,22800,40100,23700" st "PipelinedOperators" blo "30600,23500" tm "BdLibraryNameMgr" ) *19 (Text uid 2723,0 va (VaSet font "Verdana,9,1" ) xt "30600,23700,38600,24600" st "pipelineCounter" blo "30600,24400" tm "CptNameMgr" ) *20 (Text uid 2724,0 va (VaSet font "Verdana,9,1" ) xt "30600,24600,33100,25500" st "I_DUT" blo "30600,25300" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation uid 2725,0 ps "EdgeToEdgeStrategy" matrix (Matrix uid 2726,0 text (MLText uid 2727,0 va (VaSet font "Verdana,8,0" ) xt "30000,25400,49400,27400" st "bitNb = counterBitNb ( positive ) stageNb = pipelineStageNb ( positive ) " ) header "" ) elements [ (GiElement name "bitNb" type "positive" value "counterBitNb" ) (GiElement name "stageNb" type "positive" value "pipelineStageNb" ) ] ) ordering 1 connectByName 1 portVis (PortSigDisplay sTC 0 ) archFileType "UNKNOWN" ) *21 (Net uid 2728,0 decl (Decl n "countOut" t "unsigned" b "(counterBitNb-1 downto 0)" o 2 suid 28,0 ) declText (MLText uid 2729,0 va (VaSet font "Verdana,8,0" ) xt "2000,14200,26300,15200" st "SIGNAL countOut : unsigned(counterBitNb-1 downto 0)" ) ) *22 (Blk uid 2970,0 shape (Rectangle uid 2971,0 va (VaSet vasetType 1 fg "40000,56832,65535" ) xt "17000,30000,60000,37000" ) oxt "0,0,8000,10000" ttg (MlTextGroup uid 2972,0 ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *23 (Text uid 2973,0 va (VaSet ) xt "17800,37200,32200,38400" st "PipelinedOperators_test" blo "17800,38200" tm "BdLibraryNameMgr" ) *24 (Text uid 2974,0 va (VaSet ) xt "17800,38400,31500,39600" st "PipelineCounter_tester" blo "17800,39400" tm "BlkNameMgr" ) *25 (Text uid 2975,0 va (VaSet ) xt "17800,39600,22600,40800" st "I_tester" blo "17800,40600" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation uid 2976,0 ps "EdgeToEdgeStrategy" matrix (Matrix uid 2977,0 text (MLText uid 2978,0 va (VaSet isHidden 1 ) xt "17800,43200,43700,45600" st "counterBitNb = counterBitNb ( integer ) clockFrequency = clockFrequency ( real ) " ) header "" ) elements [ (GiElement name "counterBitNb" type "integer" value "counterBitNb" ) (GiElement name "clockFrequency" type "real" value "clockFrequency" ) ] ) ) *26 (Wire uid 2650,0 shape (OrthoPolyLine uid 2651,0 va (VaSet vasetType 3 ) xt "28000,20000,29250,30000" pts [ "29250,20000" "28000,20000" "28000,30000" ] ) start &17 end &22 sat 32 eat 2 stc 0 st 0 sf 1 si 0 tg (WTG uid 2654,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 2655,0 va (VaSet font "Verdana,12,0" ) xt "24250,18700,27750,20000" st "reset" blo "24250,19700" tm "WireNameMgr" ) ) on &12 ) *27 (Wire uid 2658,0 shape (OrthoPolyLine uid 2659,0 va (VaSet vasetType 3 ) xt "26000,18000,29250,30000" pts [ "29250,18000" "26000,18000" "26000,30000" ] ) start &16 end &22 sat 32 eat 2 stc 0 st 0 sf 1 si 0 tg (WTG uid 2662,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 2663,0 va (VaSet font "Verdana,12,0" ) xt "24250,16700,27750,18000" st "clock" blo "24250,17700" tm "WireNameMgr" ) ) on &13 ) *28 (Wire uid 2730,0 shape (OrthoPolyLine uid 2731,0 va (VaSet vasetType 3 lineWidth 2 ) xt "46750,18000,50000,30000" pts [ "46750,18000" "50000,18000" "50000,30000" ] ) start &15 end &22 sat 32 eat 1 sty 1 stc 0 st 0 sf 1 si 0 tg (WTG uid 2734,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text uid 2735,0 va (VaSet font "Verdana,12,0" ) xt "48750,16700,54350,18000" st "countOut" blo "48750,17700" tm "WireNameMgr" ) ) on &21 ) ] bg "65535,65535,65535" grid (Grid origin "0,0" isVisible 0 isActive 1 xSpacing 1000 xySpacing 1000 xShown 1 yShown 1 color "26368,26368,26368" ) packageList *29 (PackageList uid 142,0 stg "VerticalLayoutStrategy" textVec [ *30 (Text uid 143,0 va (VaSet font "Verdana,8,1" ) xt "0,0,6500,900" st "Package List" blo "0,700" ) *31 (MLText uid 144,0 va (VaSet ) xt "0,1000,17500,4600" st "LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.ALL;" tm "PackageList" ) ] ) compDirBlock (MlTextGroup uid 145,0 stg "VerticalLayoutStrategy" textVec [ *32 (Text uid 146,0 va (VaSet isHidden 1 font "Verdana,8,1" ) xt "20000,0,30000,900" st "Compiler Directives" blo "20000,700" ) *33 (Text uid 147,0 va (VaSet isHidden 1 font "Verdana,8,1" ) xt "20000,1000,31500,1900" st "Pre-module directives:" blo "20000,1700" ) *34 (MLText uid 148,0 va (VaSet isHidden 1 ) xt "20000,2000,32100,4400" st "`resetall `timescale 1ns/10ps" tm "BdCompilerDirectivesTextMgr" ) *35 (Text uid 149,0 va (VaSet isHidden 1 font "Verdana,8,1" ) xt "20000,4000,32000,4900" st "Post-module directives:" blo "20000,4700" ) *36 (MLText uid 150,0 va (VaSet isHidden 1 ) xt "20000,0,20000,0" tm "BdCompilerDirectivesTextMgr" ) *37 (Text uid 151,0 va (VaSet isHidden 1 font "Verdana,8,1" ) xt "20000,5000,31500,5900" st "End-module directives:" blo "20000,5700" ) *38 (MLText uid 152,0 va (VaSet isHidden 1 ) xt "20000,6000,20000,6000" tm "BdCompilerDirectivesTextMgr" ) ] associable 1 ) windowSize "-8,-8,1928,1048" viewArea "-1064,-1064,93622,50381" cachedDiagramExtent "0,0,73000,49000" pageSetupInfo (PageSetupInfo ptrCmd "\\\\ipp://ipp.hevs.ch\\PREA309_HPLJP3005DN,winspool," fileName "\\\\EIV\\a309_hplj4050.electro.eiv" toPrinter 1 xMargin 48 yMargin 48 paperWidth 761 paperHeight 1077 unixPaperWidth 595 unixPaperHeight 842 windowsPaperWidth 761 windowsPaperHeight 1077 paperType "A4" unixPaperName "A4 (210mm x 297mm)" windowsPaperName "A4" windowsPaperType 9 exportedDirectories [ "$HDS_PROJECT_DIR/HTMLExport" ] boundaryWidth 0 ) hasePageBreakOrigin 1 pageBreakOrigin "0,0" lastUid 3007,0 defaultCommentText (CommentText shape (Rectangle layer 0 va (VaSet vasetType 1 fg "65535,65535,65535" lineStyle 2 ) xt "0,0,15000,5000" ) text (MLText va (VaSet fg "65535,0,0" ) xt "200,200,3200,1400" st " Text " tm "CommentText" wrapOption 3 visibleHeight 4600 visibleWidth 14600 ) ) defaultRequirementText (RequirementText shape (ZoomableIcon layer 0 va (VaSet vasetType 1 fg "59904,39936,65280" lineColor "0,0,32768" ) xt "0,0,1500,1750" iconName "reqTracerRequirement.bmp" iconMaskName "reqTracerRequirement.msk" ) autoResize 1 text (MLText va (VaSet fg "0,0,32768" font "Verdana,8,0" ) xt "450,2150,1450,3150" st " Text " tm "RequirementText" wrapOption 3 visibleHeight 1350 visibleWidth 1100 ) ) defaultPanel (Panel shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "32768,0,0" lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (Text va (VaSet font "Verdana,10,1" ) xt "1000,1000,4400,2200" st "Panel0" blo "1000,2000" tm "PanelText" ) ) ) defaultBlk (Blk shape (Rectangle va (VaSet vasetType 1 fg "40000,56832,65535" ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *39 (Text va (VaSet ) xt "1700,3200,6300,4400" st "" blo "1700,4200" tm "BdLibraryNameMgr" ) *40 (Text va (VaSet ) xt "1700,4400,5800,5600" st "" blo "1700,5400" tm "BlkNameMgr" ) *41 (Text va (VaSet ) xt "1700,5600,2900,6800" st "I0" blo "1700,6600" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 ) xt "1700,13200,1700,13200" ) header "" ) elements [ ] ) ) defaultMWComponent (MWC shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *42 (Text va (VaSet ) xt "1000,3500,3300,4500" st "Library" blo "1000,4300" ) *43 (Text va (VaSet ) xt "1000,4500,7000,5500" st "MWComponent" blo "1000,5300" ) *44 (Text va (VaSet ) xt "1000,5500,1600,6500" st "I0" blo "1000,6300" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 ) xt "-6000,1500,-6000,1500" ) header "" ) elements [ ] ) prms (Property pclass "params" pname "params" ptn "String" ) visOptions (mwParamsVisibilityOptions ) ) defaultSaComponent (SaComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *45 (Text va (VaSet ) xt "1250,3500,3550,4500" st "Library" blo "1250,4300" tm "BdLibraryNameMgr" ) *46 (Text va (VaSet ) xt "1250,4500,6750,5500" st "SaComponent" blo "1250,5300" tm "CptNameMgr" ) *47 (Text va (VaSet ) xt "1250,5500,1850,6500" st "I0" blo "1250,6300" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 ) xt "-5750,1500,-5750,1500" ) header "" ) elements [ ] ) archFileType "UNKNOWN" ) defaultVhdlComponent (VhdlComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *48 (Text va (VaSet ) xt "950,3500,3250,4500" st "Library" blo "950,4300" ) *49 (Text va (VaSet ) xt "950,4500,7050,5500" st "VhdlComponent" blo "950,5300" ) *50 (Text va (VaSet ) xt "950,5500,1550,6500" st "I0" blo "950,6300" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 ) xt "-6050,1500,-6050,1500" ) header "" ) elements [ ] ) entityPath "" archName "" archPath "" ) defaultVerilogComponent (VerilogComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" ) xt "-50,0,8050,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *51 (Text va (VaSet ) xt "450,3500,2750,4500" st "Library" blo "450,4300" ) *52 (Text va (VaSet ) xt "450,4500,7550,5500" st "VerilogComponent" blo "450,5300" ) *53 (Text va (VaSet ) xt "450,5500,1050,6500" st "I0" blo "450,6300" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 ) xt "-6550,1500,-6550,1500" ) header "" ) elements [ ] ) entityPath "" ) defaultHdlText (HdlText shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,32768" ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *54 (Text va (VaSet ) xt "3400,4000,4600,5000" st "eb1" blo "3400,4800" tm "HdlTextNameMgr" ) *55 (Text va (VaSet ) xt "3400,5000,3800,6000" st "1" blo "3400,5800" tm "HdlTextNumberMgr" ) ] ) ) defaultEmbeddedText (EmbeddedText commentText (CommentText ps "CenterOffsetStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" lineStyle 2 ) xt "0,0,18000,5000" ) text (MLText va (VaSet ) xt "200,200,3200,1400" st " Text " tm "HdlTextMgr" wrapOption 3 visibleHeight 4600 visibleWidth 17600 ) ) ) defaultGlobalConnector (GlobalConnector shape (Circle va (VaSet vasetType 1 fg "65535,65535,0" ) xt "-1000,-1000,1000,1000" radius 1000 ) name (Text va (VaSet ) xt "-300,-500,300,500" st "G" blo "-300,300" ) ) defaultRipper (Ripper ps "OnConnectorStrategy" shape (Line2D pts [ "0,0" "1000,1000" ] va (VaSet vasetType 1 ) xt "0,0,1000,1000" ) ) defaultBdJunction (BdJunction ps "OnConnectorStrategy" shape (Circle va (VaSet vasetType 1 ) xt "-400,-400,400,400" radius 400 ) ) defaultPortIoIn (PortIoIn shape (CompositeShape va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon sl 0 ro 270 xt "-2000,-375,-500,375" ) (Line sl 0 ro 270 xt "-500,0,0,0" pts [ "-500,0" "0,0" ] ) ] ) tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet isHidden 1 font "Verdana,12,0" ) xt "-1375,-1000,-1375,-1000" ju 2 blo "-1375,-1000" tm "WireNameMgr" ) ) ) defaultPortIoOut (PortIoOut shape (CompositeShape va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Pentagon sl 0 ro 270 xt "500,-375,2000,375" ) (Line sl 0 ro 270 xt "0,0,500,0" pts [ "0,0" "500,0" ] ) ] ) tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet isHidden 1 font "Verdana,12,0" ) xt "625,-1000,625,-1000" blo "625,-1000" tm "WireNameMgr" ) ) ) defaultPortIoInOut (PortIoInOut shape (CompositeShape va (VaSet vasetType 1 fg "0,0,32768" ) optionalChildren [ (Hexagon sl 0 xt "500,-375,2000,375" ) (Line sl 0 xt "0,0,500,0" pts [ "0,0" "500,0" ] ) ] ) tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet isHidden 1 font "Verdana,12,0" ) xt "0,-375,0,-375" blo "0,-375" tm "WireNameMgr" ) ) ) defaultPortIoBuffer (PortIoBuffer shape (CompositeShape va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "0,0,32768" ) optionalChildren [ (Hexagon sl 0 xt "500,-375,2000,375" ) (Line sl 0 xt "0,0,500,0" pts [ "0,0" "500,0" ] ) ] ) tg (WTG ps "PortIoTextPlaceStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet isHidden 1 font "Verdana,12,0" ) xt "0,-375,0,-375" blo "0,-375" tm "WireNameMgr" ) ) ) defaultSignal (Wire shape (OrthoPolyLine va (VaSet vasetType 3 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 stc 0 st 0 sf 1 si 0 tg (WTG ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet font "Verdana,12,0" ) xt "0,0,2600,1400" st "sig0" blo "0,1200" tm "WireNameMgr" ) ) ) defaultBus (Wire shape (OrthoPolyLine va (VaSet vasetType 3 lineWidth 2 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 sty 1 stc 0 st 0 sf 1 si 0 tg (WTG ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet font "Verdana,12,0" ) xt "0,0,3900,1400" st "dbus0" blo "0,1200" tm "WireNameMgr" ) ) ) defaultBundle (Bundle shape (OrthoPolyLine va (VaSet vasetType 3 lineStyle 3 lineWidth 1 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 textGroup (BiTextGroup ps "ConnStartEndStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet ) xt "0,0,2600,1000" st "bundle0" blo "0,800" tm "BundleNameMgr" ) second (MLText va (VaSet ) xt "0,1000,1500,2200" st "()" tm "BundleContentsMgr" ) ) bundleNet &0 ) defaultPortMapFrame (PortMapFrame ps "PortMapFrameStrategy" shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "0,0,50000" lineWidth 2 ) xt "0,0,10000,12000" ) portMapText (BiTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" first (MLText va (VaSet ) xt "0,0,5000,1200" st "Auto list" ) second (MLText va (VaSet ) xt "0,1000,9600,2200" st "User defined list" tm "PortMapTextMgr" ) ) ) defaultGenFrame (Frame shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "28160,28160,28160" lineStyle 2 lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (MLText va (VaSet ) xt "0,-1100,18500,100" st "g0: FOR i IN 0 TO n GENERATE" tm "FrameTitleTextMgr" ) ) seqNum (FrameSequenceNumber ps "TopLeftStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "50,50,1050,1450" ) num (Text va (VaSet ) xt "350,250,750,1250" st "1" blo "350,1050" tm "FrameSeqNumMgr" ) ) decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *56 (Text va (VaSet font "Verdana,8,1" ) xt "14100,20000,22000,21000" st "Frame Declarations" blo "14100,20800" ) *57 (MLText va (VaSet ) xt "14100,21000,14100,21000" tm "BdFrameDeclTextMgr" ) ] ) ) defaultBlockFrame (Frame shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "28160,28160,28160" lineStyle 1 lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (MLText va (VaSet ) xt "0,-1100,11000,100" st "b0: BLOCK (guard)" tm "FrameTitleTextMgr" ) ) seqNum (FrameSequenceNumber ps "TopLeftStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "50,50,1050,1450" ) num (Text va (VaSet ) xt "350,250,750,1250" st "1" blo "350,1050" tm "FrameSeqNumMgr" ) ) decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *58 (Text va (VaSet font "Verdana,8,1" ) xt "14100,20000,22000,21000" st "Frame Declarations" blo "14100,20800" ) *59 (MLText va (VaSet ) xt "14100,21000,14100,21000" tm "BdFrameDeclTextMgr" ) ] ) style 3 ) defaultSaCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,1400,1750" st "Port" blo "0,1550" ) ) thePort (LogicalPort decl (Decl n "Port" t "" o 0 ) ) ) defaultSaCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,1400,1750" st "Port" blo "0,1550" ) ) thePort (LogicalPort m 3 decl (Decl n "Port" t "" o 0 ) ) ) defaultDeclText (MLText va (VaSet font "Verdana,8,0" ) ) archDeclarativeBlock (BdArchDeclBlock uid 1,0 stg "BdArchDeclBlockLS" declLabel (Text uid 2,0 va (VaSet font "Verdana,8,1" ) xt "0,5600,6500,6500" st "Declarations" blo "0,6300" ) portLabel (Text uid 3,0 va (VaSet font "Verdana,8,1" ) xt "0,6500,3000,7400" st "Ports:" blo "0,7200" ) preUserLabel (Text uid 4,0 va (VaSet font "Verdana,8,1" ) xt "0,7400,4500,8300" st "Pre User:" blo "0,8100" ) preUserText (MLText uid 5,0 va (VaSet font "Verdana,8,0" ) xt "2000,8300,22100,12300" st "constant counterBitNb: positive := 20; constant pipelineStageNb: positive := 5; constant clockFrequency : real := 60.0E6; --constant clockFrequency : real := 66.0E6;" tm "BdDeclarativeTextMgr" ) diagSignalLabel (Text uid 6,0 va (VaSet font "Verdana,8,1" ) xt "0,12300,8500,13200" st "Diagram Signals:" blo "0,13000" ) postUserLabel (Text uid 7,0 va (VaSet isHidden 1 font "Verdana,8,1" ) xt "0,5600,5500,6500" st "Post User:" blo "0,6300" ) postUserText (MLText uid 8,0 va (VaSet isHidden 1 font "Verdana,8,0" ) xt "0,5600,0,5600" tm "BdDeclarativeTextMgr" ) ) commonDM (CommonDM ldm (LogicalDM suid 28,0 usingSuid 1 emptyRow *60 (LEmptyRow ) uid 1321,0 optionalChildren [ *61 (RefLabelRowHdr ) *62 (TitleRowHdr ) *63 (FilterRowHdr ) *64 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *65 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *66 (GroupColHdr tm "GroupColHdrMgr" ) *67 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) *68 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) *69 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) *70 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) *71 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) *72 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) *73 (LeafLogPort port (LogicalPort m 4 decl (Decl n "reset" t "std_ulogic" o 3 suid 25,0 ) ) uid 2672,0 ) *74 (LeafLogPort port (LogicalPort m 4 decl (Decl n "clock" t "std_ulogic" o 1 suid 26,0 ) ) uid 2674,0 ) *75 (LeafLogPort port (LogicalPort m 4 decl (Decl n "countOut" t "unsigned" b "(counterBitNb-1 downto 0)" o 2 suid 28,0 ) ) uid 2736,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 1334,0 optionalChildren [ *76 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *77 (MRCItem litem &60 pos 3 dimension 20 ) uid 1336,0 optionalChildren [ *78 (MRCItem litem &61 pos 0 dimension 20 uid 1337,0 ) *79 (MRCItem litem &62 pos 1 dimension 23 uid 1338,0 ) *80 (MRCItem litem &63 pos 2 hidden 1 dimension 20 uid 1339,0 ) *81 (MRCItem litem &73 pos 0 dimension 20 uid 2673,0 ) *82 (MRCItem litem &74 pos 1 dimension 20 uid 2675,0 ) *83 (MRCItem litem &75 pos 2 dimension 20 uid 2737,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 1340,0 optionalChildren [ *84 (MRCItem litem &64 pos 0 dimension 20 uid 1341,0 ) *85 (MRCItem litem &66 pos 1 dimension 50 uid 1342,0 ) *86 (MRCItem litem &67 pos 2 dimension 100 uid 1343,0 ) *87 (MRCItem litem &68 pos 3 dimension 50 uid 1344,0 ) *88 (MRCItem litem &69 pos 4 dimension 100 uid 1345,0 ) *89 (MRCItem litem &70 pos 5 dimension 100 uid 1346,0 ) *90 (MRCItem litem &71 pos 6 dimension 50 uid 1347,0 ) *91 (MRCItem litem &72 pos 7 dimension 80 uid 1348,0 ) ] ) fixedCol 4 fixedRow 2 name "Ports" uid 1335,0 vaOverrides [ ] ) ] ) uid 1320,0 ) genericsCommonDM (CommonDM ldm (LogicalDM emptyRow *92 (LEmptyRow ) uid 1350,0 optionalChildren [ *93 (RefLabelRowHdr ) *94 (TitleRowHdr ) *95 (FilterRowHdr ) *96 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *97 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *98 (GroupColHdr tm "GroupColHdrMgr" ) *99 (NameColHdr tm "GenericNameColHdrMgr" ) *100 (TypeColHdr tm "GenericTypeColHdrMgr" ) *101 (InitColHdr tm "GenericValueColHdrMgr" ) *102 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) *103 (EolColHdr tm "GenericEolColHdrMgr" ) ] ) pdm (PhysicalDM uid 1362,0 optionalChildren [ *104 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *105 (MRCItem litem &92 pos 0 dimension 20 ) uid 1364,0 optionalChildren [ *106 (MRCItem litem &93 pos 0 dimension 20 uid 1365,0 ) *107 (MRCItem litem &94 pos 1 dimension 23 uid 1366,0 ) *108 (MRCItem litem &95 pos 2 hidden 1 dimension 20 uid 1367,0 ) ] ) sheetCol (SheetCol propVa (MVa cellColor "0,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" textAngle 90 ) uid 1368,0 optionalChildren [ *109 (MRCItem litem &96 pos 0 dimension 20 uid 1369,0 ) *110 (MRCItem litem &98 pos 1 dimension 50 uid 1370,0 ) *111 (MRCItem litem &99 pos 2 dimension 100 uid 1371,0 ) *112 (MRCItem litem &100 pos 3 dimension 100 uid 1372,0 ) *113 (MRCItem litem &101 pos 4 dimension 50 uid 1373,0 ) *114 (MRCItem litem &102 pos 5 dimension 50 uid 1374,0 ) *115 (MRCItem litem &103 pos 6 dimension 80 uid 1375,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 1363,0 vaOverrides [ ] ) ] ) uid 1349,0 type 1 ) activeModelName "BlockDiag" )