ARCHITECTURE studentVersion OF sineTable IS

  signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
  signal phaseTableAddress2 : unsigned(tableAddressBitNb-1 downto 0);
  signal quarterSine : signed(sine'range);

BEGIN

  phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);

  sequenceTable: process(phaseTableAddress)
  begin
    if phase(phase'high-1) = '1' then
      phaseTableAddress2 <= 8 - phaseTableAddress;
    else
      phaseTableAddress2 <= phaseTableAddress;
    end if;
  end process sequenceTable;

  quarterTable: process(phaseTableAddress2)
  begin
    case to_integer(phaseTableAddress2) is
      when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
      when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
      when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
      when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length);
      when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length);
      when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length);
      when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length);
      when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
      when others => quarterSine <= (others => '-');
    end case;
    if phaseTableAddress2 = 0 then
      if phase(phase'high-1) = '1' then
        quarterSine <= to_signed(16#7FFF#, quarterSine'length);
      end if;
    end if;
  end process quarterTable;

  invert: process(quarterSine, phase(phase'high))
  begin
    if phase(phase'high) = '1' then
      sine <= NOT quarterSine;
    else
      sine <= quarterSine;
    end if;
  end process invert;

END ARCHITECTURE studentVersion;