2195 lines
26 KiB
Plaintext
2195 lines
26 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "27.1"
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appVersion "2019.2 (Build 5)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 14,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 144,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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|
*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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|
*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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|
*14 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "adrSrc"
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t "std_uLogic"
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o 10
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suid 1,0
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)
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)
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uid 116,0
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)
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*15 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "ALUOp"
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t "std_ulogic_vector"
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b "(1 DOWNTO 0)"
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o 5
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suid 2,0
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)
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)
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uid 118,0
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)
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*16 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "ALUSrcA"
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t "std_ulogic_vector"
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b "(1 DOWNTO 0)"
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o 6
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suid 3,0
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)
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)
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uid 120,0
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)
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*17 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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|
n "ALUSrcB"
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t "std_ulogic_vector"
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b "(1 DOWNTO 0)"
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o 7
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suid 4,0
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)
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)
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uid 122,0
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)
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*18 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
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n "branch"
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t "std_uLogic"
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o 11
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suid 5,0
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)
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)
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|
uid 124,0
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)
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*19 (LogPort
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port (LogicalPort
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|
lang 11
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|
decl (Decl
|
|
n "clk"
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|
t "std_ulogic"
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o 1
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suid 6,0
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)
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)
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uid 126,0
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)
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*20 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "IRWrite"
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t "std_ulogic"
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o 8
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suid 7,0
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)
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)
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uid 128,0
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)
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*21 (LogPort
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port (LogicalPort
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lang 11
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m 1
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decl (Decl
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n "memWrite"
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t "std_ulogic"
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o 12
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suid 8,0
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)
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)
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uid 130,0
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)
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*22 (LogPort
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port (LogicalPort
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lang 11
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decl (Decl
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n "op"
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t "std_ulogic_vector"
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b "(6 DOWNTO 0)"
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o 3
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suid 9,0
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)
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)
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uid 132,0
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)
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*23 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
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n "PCupdate"
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t "std_uLogic"
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o 9
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suid 10,0
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)
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)
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uid 134,0
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)
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*24 (LogPort
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port (LogicalPort
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|
lang 11
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m 1
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|
decl (Decl
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|
n "regwrite"
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|
t "std_ulogic"
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|
o 13
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suid 11,0
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)
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)
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uid 136,0
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)
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|
*25 (LogPort
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port (LogicalPort
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|
lang 11
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|
m 1
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|
decl (Decl
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|
n "resultSrc"
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|
t "std_ulogic_vector"
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b "(1 DOWNTO 0)"
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o 14
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suid 12,0
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)
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)
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uid 138,0
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)
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*26 (LogPort
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port (LogicalPort
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|
lang 11
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|
decl (Decl
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|
n "rst"
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|
t "std_ulogic"
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|
o 4
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suid 13,0
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)
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)
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uid 140,0
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)
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*27 (LogPort
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port (LogicalPort
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|
lang 11
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decl (Decl
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|
n "en"
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|
t "std_ulogic"
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o 2
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suid 14,0
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)
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)
|
|
uid 337,0
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|
)
|
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]
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)
|
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pdm (PhysicalDM
|
|
displayShortBounds 1
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|
editShortBounds 1
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|
uid 157,0
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|
optionalChildren [
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*28 (Sheet
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|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
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fontColor "0,0,0"
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|
font "Tahoma,10,0"
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)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
|
|
emptyMRCItem *29 (MRCItem
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|
litem &1
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|
pos 14
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|
dimension 20
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)
|
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uid 159,0
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|
optionalChildren [
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|
*30 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 160,0
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)
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*31 (MRCItem
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litem &3
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pos 1
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dimension 23
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|
uid 161,0
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)
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*32 (MRCItem
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litem &4
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pos 2
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hidden 1
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dimension 20
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uid 162,0
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)
|
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*33 (MRCItem
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litem &14
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pos 8
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dimension 20
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uid 117,0
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)
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*34 (MRCItem
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litem &15
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pos 3
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dimension 20
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uid 119,0
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)
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*35 (MRCItem
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litem &16
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pos 4
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dimension 20
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uid 121,0
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)
|
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*36 (MRCItem
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litem &17
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pos 5
|
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dimension 20
|
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uid 123,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &18
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pos 9
|
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dimension 20
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uid 125,0
|
|
)
|
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*38 (MRCItem
|
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litem &19
|
|
pos 0
|
|
dimension 20
|
|
uid 127,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 20
|
|
uid 129,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &21
|
|
pos 10
|
|
dimension 20
|
|
uid 131,0
|
|
)
|
|
*41 (MRCItem
|
|
litem &22
|
|
pos 1
|
|
dimension 20
|
|
uid 133,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &23
|
|
pos 7
|
|
dimension 20
|
|
uid 135,0
|
|
)
|
|
*43 (MRCItem
|
|
litem &24
|
|
pos 11
|
|
dimension 20
|
|
uid 137,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &25
|
|
pos 12
|
|
dimension 20
|
|
uid 139,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &26
|
|
pos 2
|
|
dimension 20
|
|
uid 141,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &27
|
|
pos 13
|
|
dimension 20
|
|
uid 338,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 163,0
|
|
optionalChildren [
|
|
*47 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 164,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 165,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 166,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 167,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 168,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 169,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 170,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 171,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 158,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 143,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *55 (LEmptyRow
|
|
)
|
|
uid 173,0
|
|
optionalChildren [
|
|
*56 (RefLabelRowHdr
|
|
)
|
|
*57 (TitleRowHdr
|
|
)
|
|
*58 (FilterRowHdr
|
|
)
|
|
*59 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*60 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*61 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*62 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*63 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*64 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*65 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*66 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 185,0
|
|
optionalChildren [
|
|
*67 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *68 (MRCItem
|
|
litem &55
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 187,0
|
|
optionalChildren [
|
|
*69 (MRCItem
|
|
litem &56
|
|
pos 0
|
|
dimension 20
|
|
uid 188,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &57
|
|
pos 1
|
|
dimension 23
|
|
uid 189,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &58
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 190,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 191,0
|
|
optionalChildren [
|
|
*72 (MRCItem
|
|
litem &59
|
|
pos 0
|
|
dimension 20
|
|
uid 192,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &61
|
|
pos 1
|
|
dimension 50
|
|
uid 193,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &62
|
|
pos 2
|
|
dimension 100
|
|
uid 194,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &63
|
|
pos 3
|
|
dimension 100
|
|
uid 195,0
|
|
)
|
|
*76 (MRCItem
|
|
litem &64
|
|
pos 4
|
|
dimension 50
|
|
uid 196,0
|
|
)
|
|
*77 (MRCItem
|
|
litem &65
|
|
pos 5
|
|
dimension 50
|
|
uid 197,0
|
|
)
|
|
*78 (MRCItem
|
|
litem &66
|
|
pos 6
|
|
dimension 80
|
|
uid 198,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 186,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 172,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\mainFSM"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "18.10.2022"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "mar."
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "mardi"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "18"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "mainFSM"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "18.10.2022"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE2332101"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "09:29:07"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE2332101"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "HEIRV32"
|
|
)
|
|
(vvPair
|
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variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "10"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "mainFSM"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "oct."
|
|
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|
|
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|
|
variable "month_long"
|
|
value "octobre"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\main@f@s@m\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\Users\\axel.amand\\Desktop\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\hds\\mainFSM\\symbol.sb"
|
|
)
|
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(vvPair
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variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
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|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
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|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "09:29:07"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "mainFSM"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2022"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "22"
|
|
)
|
|
]
|
|
)
|
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LanguageMgr "Vhdl2008LangMgr"
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