2067 lines
26 KiB
Plaintext
2067 lines
26 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 2019,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 201,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "outX"
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t "std_ulogic"
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o 1
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suid 3,0
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)
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)
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uid 203,0
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)
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*3 (LogPort
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port (LogicalPort
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decl (Decl
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n "selSinCos"
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t "std_ulogic"
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o 6
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suid 13,0
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)
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)
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uid 204,0
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)
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*4 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 3
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suid 1,0
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)
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)
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uid 206,0
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)
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*5 (LogPort
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port (LogicalPort
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decl (Decl
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n "run"
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t "std_ulogic"
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o 2
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suid 2,0
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)
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)
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uid 209,0
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)
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*6 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "outY"
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t "std_ulogic"
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o 5
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suid 5,0
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)
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)
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uid 210,0
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)
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*7 (LogPort
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port (LogicalPort
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 4
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suid 4,0
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)
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)
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uid 211,0
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)
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*8 (RefLabelRowHdr
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)
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*9 (TitleRowHdr
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)
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*10 (FilterRowHdr
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)
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|
*11 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*12 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*13 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*14 (NameColHdr
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tm "NameColHdrMgr"
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)
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*15 (ModeColHdr
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|
tm "ModeColHdrMgr"
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)
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*16 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*17 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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|
*18 (InitColHdr
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tm "InitColHdrMgr"
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)
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*19 (EolColHdr
|
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tm "EolColHdrMgr"
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)
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|
*20 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "interpolateLin"
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t "std_ulogic"
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o 7
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suid 2014,0
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)
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)
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uid 539,0
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)
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*21 (LogPort
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port (LogicalPort
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|
decl (Decl
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n "updatePeriod"
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t "unsigned"
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b "(updatePeriodBitNb-1 DOWNTO 0)"
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o 8
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suid 2015,0
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)
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)
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uid 541,0
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)
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*22 (LogPort
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port (LogicalPort
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decl (Decl
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n "memX"
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t "std_ulogic_vector"
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b "(signalBitNb-1 DOWNTO 0)"
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o 9
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suid 2016,0
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)
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)
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uid 543,0
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)
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*23 (LogPort
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port (LogicalPort
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decl (Decl
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n "memY"
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t "std_ulogic_vector"
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b "(signalBitNb-1 DOWNTO 0)"
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o 10
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suid 2018,0
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)
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)
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uid 653,0
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)
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*24 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "newPolynom"
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t "std_ulogic"
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o 11
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suid 2019,0
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)
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)
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uid 725,0
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)
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]
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)
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pdm (PhysicalDM
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displayShortBounds 1
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editShortBounds 1
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uid 215,0
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optionalChildren [
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*25 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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|
cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
|
|
groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *26 (MRCItem
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litem &1
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pos 11
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dimension 20
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)
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uid 132,0
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optionalChildren [
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*27 (MRCItem
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litem &8
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pos 0
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dimension 20
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uid 135,0
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)
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*28 (MRCItem
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litem &9
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pos 1
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dimension 23
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uid 137,0
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)
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*29 (MRCItem
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litem &10
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pos 2
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hidden 1
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dimension 20
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uid 139,0
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)
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*30 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 159,0
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)
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*31 (MRCItem
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litem &3
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pos 5
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dimension 20
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uid 160,0
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)
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*32 (MRCItem
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litem &4
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pos 2
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dimension 20
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uid 162,0
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)
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*33 (MRCItem
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litem &5
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pos 1
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dimension 20
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uid 165,0
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)
|
|
*34 (MRCItem
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|
litem &6
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pos 4
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dimension 20
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uid 166,0
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)
|
|
*35 (MRCItem
|
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litem &7
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pos 3
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dimension 20
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uid 167,0
|
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)
|
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*36 (MRCItem
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litem &20
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pos 6
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dimension 20
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uid 540,0
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)
|
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*37 (MRCItem
|
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litem &21
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pos 7
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dimension 20
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uid 542,0
|
|
)
|
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*38 (MRCItem
|
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litem &22
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pos 8
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dimension 20
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uid 544,0
|
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)
|
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*39 (MRCItem
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litem &23
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pos 9
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dimension 20
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uid 654,0
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)
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*40 (MRCItem
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litem &24
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pos 10
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dimension 20
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uid 724,0
|
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)
|
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]
|
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)
|
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sheetCol (SheetCol
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|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
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font "courier,10,0"
|
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textAngle 90
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)
|
|
uid 133,0
|
|
optionalChildren [
|
|
*41 (MRCItem
|
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litem &11
|
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pos 0
|
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dimension 20
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uid 141,0
|
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)
|
|
*42 (MRCItem
|
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litem &13
|
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pos 1
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dimension 50
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uid 145,0
|
|
)
|
|
*43 (MRCItem
|
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litem &14
|
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pos 2
|
|
dimension 100
|
|
uid 147,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &15
|
|
pos 3
|
|
dimension 50
|
|
uid 149,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &16
|
|
pos 4
|
|
dimension 100
|
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uid 151,0
|
|
)
|
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*46 (MRCItem
|
|
litem &17
|
|
pos 5
|
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dimension 100
|
|
uid 153,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &18
|
|
pos 6
|
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dimension 50
|
|
uid 155,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &19
|
|
pos 7
|
|
dimension 80
|
|
uid 157,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 131,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 200,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *49 (LEmptyRow
|
|
)
|
|
uid 217,0
|
|
optionalChildren [
|
|
*50 (RefLabelRowHdr
|
|
)
|
|
*51 (TitleRowHdr
|
|
)
|
|
*52 (FilterRowHdr
|
|
)
|
|
*53 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*54 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*55 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*56 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*57 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*58 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*59 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*60 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*61 (LogGeneric
|
|
generic (GiElement
|
|
name "updatePeriodBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 197,0
|
|
)
|
|
*62 (LogGeneric
|
|
generic (GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 593,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 218,0
|
|
optionalChildren [
|
|
*63 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *64 (MRCItem
|
|
litem &49
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 172,0
|
|
optionalChildren [
|
|
*65 (MRCItem
|
|
litem &50
|
|
pos 0
|
|
dimension 20
|
|
uid 175,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &51
|
|
pos 1
|
|
dimension 23
|
|
uid 177,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &52
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 179,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &61
|
|
pos 0
|
|
dimension 20
|
|
uid 199,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &62
|
|
pos 1
|
|
dimension 20
|
|
uid 594,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 173,0
|
|
optionalChildren [
|
|
*70 (MRCItem
|
|
litem &53
|
|
pos 0
|
|
dimension 20
|
|
uid 181,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &55
|
|
pos 1
|
|
dimension 50
|
|
uid 185,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &56
|
|
pos 2
|
|
dimension 100
|
|
uid 187,0
|
|
)
|
|
*73 (MRCItem
|
|
litem &57
|
|
pos 3
|
|
dimension 100
|
|
uid 189,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &58
|
|
pos 4
|
|
dimension 50
|
|
uid 191,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &59
|
|
pos 5
|
|
dimension 50
|
|
uid 193,0
|
|
)
|
|
*76 (MRCItem
|
|
litem &60
|
|
pos 6
|
|
dimension 80
|
|
uid 195,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 171,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 216,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/beamer@periph@operator/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/beamer@periph@operator/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/beamer@periph@operator"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/beamerPeriphOperator"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "13"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "beamerPeriphOperator"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:40:21"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "03"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "beamerPeriphOperator"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Mar"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "March"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/beamer@periph@operator/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/beamerPeriphOperator/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "systemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:40:21"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "beamerPeriphOperator"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
|
|
optionalChildren [
|
|
*77 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*78 (CptPort
|
|
uid 52,0
|
|
ps "OnEdgeStrategy"
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|
shape (Triangle
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|
va (VaSet
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|
vasetType 1
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|
fg "0,65535,0"
|
|
)
|
|
xt "41250,26625,42000,27375"
|
|
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|
tg (CPTG
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|
uid 54,0
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ps "CptPortTextPlaceStrategy"
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font "courier,9,0"
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xt "43000,26400,45500,27300"
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st "clock"
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blo "43000,27100"
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tm "CptPortNameMgr"
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dt (MLText
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)
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st "clock : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
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|
suid 1,0
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)
|
|
)
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)
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*79 (CptPort
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uid 57,0
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ps "OnEdgeStrategy"
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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xt "41250,12625,42000,13375"
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tg (CPTG
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|
uid 59,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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blo "43000,13100"
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tm "CptPortNameMgr"
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)
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thePort (LogicalPort
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decl (Decl
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n "run"
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t "std_ulogic"
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)
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)
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*80 (CptPort
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uid 67,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 68,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 69,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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va (VaSet
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font "courier,9,0"
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blo "57001,13100"
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tm "CptPortNameMgr"
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dt (MLText
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uid 71,0
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va (VaSet
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font "courier,8,0"
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)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "outX"
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t "std_ulogic"
|
|
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|
|
suid 3,0
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)
|
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)
|
|
)
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*81 (CptPort
|
|
uid 76,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 77,0
|
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ro 90
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va (VaSet
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tg (CPTG
|
|
uid 78,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 79,0
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va (VaSet
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font "courier,9,0"
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xt "43000,28400,45500,29300"
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st "reset"
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blo "43000,29100"
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tm "CptPortNameMgr"
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)
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dt (MLText
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uid 80,0
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va (VaSet
|
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font "courier,8,0"
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)
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xt "2000,10300,21000,11200"
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st "reset : IN std_ulogic ;"
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)
|
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thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
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|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
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*82 (CptPort
|
|
uid 82,0
|
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ps "OnEdgeStrategy"
|
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shape (Triangle
|
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uid 83,0
|
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ro 90
|
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va (VaSet
|
|
vasetType 1
|
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fg "0,65535,0"
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tg (CPTG
|
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uid 84,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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uid 85,0
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va (VaSet
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font "courier,9,0"
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blo "57001,15100"
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tm "CptPortNameMgr"
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va (VaSet
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)
|
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thePort (LogicalPort
|
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m 1
|
|
decl (Decl
|
|
n "outY"
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t "std_ulogic"
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suid 5,0
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*83 (CptPort
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uid 125,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 130,0
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va (VaSet
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vasetType 1
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tg (CPTG
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uid 127,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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uid 128,0
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va (VaSet
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font "courier,9,0"
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)
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st "selSinCos"
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blo "57001,19100"
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tm "CptPortNameMgr"
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uid 129,0
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va (VaSet
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font "courier,8,0"
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st "selSinCos : IN std_ulogic ;"
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|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
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|
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|
|
suid 13,0
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)
|
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)
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)
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*84 (CptPort
|
|
uid 524,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
|
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uid 525,0
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ro 90
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va (VaSet
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vasetType 1
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tg (CPTG
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uid 526,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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uid 527,0
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va (VaSet
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st "interpolateLin"
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blo "43000,15100"
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 528,0
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va (VaSet
|
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font "courier,8,0"
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)
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xt "2000,13000,21000,13900"
|
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st "interpolateLin : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "interpolateLin"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 2014,0
|
|
)
|
|
)
|
|
)
|
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*85 (CptPort
|
|
uid 529,0
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ps "OnEdgeStrategy"
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shape (Triangle
|
|
uid 530,0
|
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ro 90
|
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va (VaSet
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vasetType 1
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)
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)
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tg (CPTG
|
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uid 531,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 532,0
|
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va (VaSet
|
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font "courier,9,0"
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)
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xt "43000,16400,49500,17300"
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st "updatePeriod"
|
|
blo "43000,17100"
|
|
tm "CptPortNameMgr"
|
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)
|
|
)
|
|
dt (MLText
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uid 533,0
|
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va (VaSet
|
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font "courier,8,0"
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)
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xt "2000,13900,35000,14800"
|
|
st "updatePeriod : IN unsigned (updatePeriodBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "updatePeriod"
|
|
t "unsigned"
|
|
b "(updatePeriodBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 2015,0
|
|
)
|
|
)
|
|
)
|
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*86 (CptPort
|
|
uid 534,0
|
|
ps "OnEdgeStrategy"
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shape (Triangle
|
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uid 535,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "41250,20625,42000,21375"
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|
)
|
|
tg (CPTG
|
|
uid 536,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
|
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f (Text
|
|
uid 537,0
|
|
va (VaSet
|
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font "courier,9,0"
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)
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xt "43000,20400,45000,21300"
|
|
st "memX"
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|
blo "43000,21100"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 538,0
|
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va (VaSet
|
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font "courier,8,0"
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|
|
st "memX : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "memX"
|
|
t "std_ulogic_vector"
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|
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|
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)
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|
*87 (CptPort
|
|
uid 648,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 649,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "41250,22625,42000,23375"
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|
)
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|
tg (CPTG
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|
uid 650,0
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|
ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
|
|
uid 651,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "43000,22400,45000,23300"
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|
st "memY"
|
|
blo "43000,23100"
|
|
tm "CptPortNameMgr"
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|
)
|
|
)
|
|
dt (MLText
|
|
uid 652,0
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va (VaSet
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font "courier,8,0"
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xt "2000,15700,36500,16600"
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|
st "memY : IN std_ulogic_vector (signalBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "memY"
|
|
t "std_ulogic_vector"
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|
b "(signalBitNb-1 DOWNTO 0)"
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o 10
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|
|
)
|
|
xt "0,12000,0,12000"
|
|
)
|
|
header "Generic Declarations"
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portInstanceVisAsIs 1
|
|
portInstanceVis (PortSigDisplay
|
|
)
|
|
)
|
|
defaultCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "0,750,1500,1650"
|
|
st "In0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "In0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
bg "0,0,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "0,750,3500,1650"
|
|
st "Buffer0"
|
|
blo "0,1450"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Buffer0"
|
|
t "std_logic_vector"
|
|
b "(15 DOWNTO 0)"
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
DeclarativeBlock *106 (SymDeclBlock
|
|
uid 1,0
|
|
stg "SymDeclLayoutStrategy"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,5800,6500,6700"
|
|
st "Declarations"
|
|
blo "0,6500"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,6700,3000,7600"
|
|
st "Ports:"
|
|
blo "0,7400"
|
|
)
|
|
externalLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,17500,2500,18400"
|
|
st "User:"
|
|
blo "0,18200"
|
|
)
|
|
internalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "courier,8,1"
|
|
)
|
|
xt "0,5800,7500,6700"
|
|
st "Internal User:"
|
|
blo "0,6500"
|
|
)
|
|
externalText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,18400,2000,18400"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
internalText (MLText
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "courier,8,0"
|
|
)
|
|
xt "0,5800,0,5800"
|
|
tm "SyDeclarativeTextMgr"
|
|
)
|
|
)
|
|
lastUid 776,0
|
|
okToSyncOnLoad 1
|
|
OkToSyncGenericsOnLoad 1
|
|
activeModelName "Symbol"
|
|
)
|