1710 lines
22 KiB
Plaintext
1710 lines
22 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 2006,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 225,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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decl (Decl
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n "updateMem"
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t "std_ulogic"
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o 4
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suid 4,0
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)
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)
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uid 226,0
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)
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*3 (LogPort
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port (LogicalPort
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decl (Decl
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n "patternSize"
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t "unsigned"
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b "(addressBitNb-1 DOWNTO 0)"
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o 6
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suid 6,0
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)
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)
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uid 227,0
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)
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*4 (LogPort
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port (LogicalPort
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 3
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suid 3,0
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)
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)
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uid 228,0
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)
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*5 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "addr"
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t "unsigned"
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b "(addressBitNb-1 DOWNTO 0)"
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o 5
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suid 5,0
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)
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)
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uid 229,0
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)
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*6 (LogPort
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port (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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o 2
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suid 2,0
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)
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)
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uid 230,0
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)
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*7 (LogPort
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port (LogicalPort
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decl (Decl
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n "en"
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t "std_ulogic"
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o 1
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suid 1,0
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)
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)
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uid 231,0
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)
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*8 (RefLabelRowHdr
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)
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*9 (TitleRowHdr
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)
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*10 (FilterRowHdr
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)
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|
*11 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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|
*12 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*13 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*14 (NameColHdr
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tm "NameColHdrMgr"
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)
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*15 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*16 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*17 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*18 (InitColHdr
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tm "InitColHdrMgr"
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)
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|
*19 (EolColHdr
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tm "EolColHdrMgr"
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)
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]
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)
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pdm (PhysicalDM
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|
uid 232,0
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optionalChildren [
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*20 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *21 (MRCItem
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litem &1
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pos 6
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dimension 20
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)
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uid 163,0
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optionalChildren [
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*22 (MRCItem
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litem &8
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pos 0
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dimension 20
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uid 166,0
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)
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*23 (MRCItem
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litem &9
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pos 1
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dimension 23
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uid 168,0
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)
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*24 (MRCItem
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litem &10
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pos 2
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hidden 1
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dimension 20
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uid 170,0
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)
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*25 (MRCItem
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litem &2
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pos 3
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dimension 20
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uid 189,0
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)
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*26 (MRCItem
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litem &3
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pos 5
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dimension 20
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uid 190,0
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)
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*27 (MRCItem
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litem &4
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pos 2
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dimension 20
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uid 191,0
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)
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*28 (MRCItem
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litem &5
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pos 4
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dimension 20
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uid 192,0
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)
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*29 (MRCItem
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litem &6
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pos 1
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dimension 20
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uid 193,0
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)
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*30 (MRCItem
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litem &7
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pos 0
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dimension 20
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uid 194,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
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uid 164,0
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optionalChildren [
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*31 (MRCItem
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litem &11
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pos 0
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dimension 20
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uid 172,0
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)
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*32 (MRCItem
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litem &13
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pos 1
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dimension 50
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uid 176,0
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)
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*33 (MRCItem
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litem &14
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pos 2
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dimension 100
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uid 178,0
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)
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*34 (MRCItem
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litem &15
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pos 3
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dimension 50
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uid 180,0
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)
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*35 (MRCItem
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litem &16
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pos 4
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dimension 100
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uid 182,0
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)
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*36 (MRCItem
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litem &17
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pos 5
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dimension 100
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uid 184,0
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)
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*37 (MRCItem
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litem &18
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pos 6
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dimension 50
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|
uid 186,0
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)
|
|
*38 (MRCItem
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|
litem &19
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pos 7
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dimension 80
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|
uid 188,0
|
|
)
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]
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)
|
|
fixedCol 4
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fixedRow 2
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name "Ports"
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uid 162,0
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|
vaOverrides [
|
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]
|
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)
|
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]
|
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)
|
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uid 224,0
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|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *39 (LEmptyRow
|
|
)
|
|
uid 234,0
|
|
optionalChildren [
|
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*40 (RefLabelRowHdr
|
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)
|
|
*41 (TitleRowHdr
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)
|
|
*42 (FilterRowHdr
|
|
)
|
|
*43 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*44 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*45 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*46 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*47 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*48 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*49 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*50 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*51 (LogGeneric
|
|
generic (GiElement
|
|
name "addressBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 220,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 235,0
|
|
optionalChildren [
|
|
*52 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *53 (MRCItem
|
|
litem &39
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 196,0
|
|
optionalChildren [
|
|
*54 (MRCItem
|
|
litem &40
|
|
pos 0
|
|
dimension 20
|
|
uid 199,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &41
|
|
pos 1
|
|
dimension 23
|
|
uid 201,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &42
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 203,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &51
|
|
pos 0
|
|
dimension 20
|
|
uid 222,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 197,0
|
|
optionalChildren [
|
|
*58 (MRCItem
|
|
litem &43
|
|
pos 0
|
|
dimension 20
|
|
uid 205,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &45
|
|
pos 1
|
|
dimension 50
|
|
uid 209,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &46
|
|
pos 2
|
|
dimension 100
|
|
uid 211,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &47
|
|
pos 3
|
|
dimension 100
|
|
uid 213,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &48
|
|
pos 4
|
|
dimension 50
|
|
uid 215,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &49
|
|
pos 5
|
|
dimension 50
|
|
uid 217,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &50
|
|
pos 6
|
|
dimension 80
|
|
uid 219,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 195,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 233,0
|
|
type 1
|
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)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
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|
value " "
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|
)
|
|
(vvPair
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|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/block@r@a@m@address@counter/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/block@r@a@m@address@counter/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds"
|
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)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/block@r@a@m@address@counter"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/blockRAMAddressCounter"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "13"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "blockRAMAddressCounter"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:40:20"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SystemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "03"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "blockRAMAddressCounter"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Mar"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "March"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/block@r@a@m@address@counter/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip/hds/blockRAMAddressCounter/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "systemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:40:20"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "blockRAMAddressCounter"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
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uid 51,0
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optionalChildren [
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xt "37250,20625,38000,21375"
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tg (CPTG
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font "courier,9,0"
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blo "39000,21100"
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tm "CptPortNameMgr"
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dt (MLText
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st "en : IN std_ulogic ;"
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thePort (LogicalPort
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decl (Decl
|
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n "en"
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xt "37250,24625,38000,25375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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st "clock"
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blo "39000,25100"
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tm "CptPortNameMgr"
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dt (MLText
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st "clock : IN std_ulogic ;"
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thePort (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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)
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tg (CPTG
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uid 132,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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font "courier,9,0"
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st "reset"
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blo "39000,27100"
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tm "CptPortNameMgr"
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)
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dt (MLText
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uid 134,0
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va (VaSet
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font "courier,8,0"
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)
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xt "2000,12600,19500,13500"
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st "reset : IN std_ulogic ;"
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)
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thePort (LogicalPort
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|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
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|
o 3
|
|
suid 3,0
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)
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)
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*69 (CptPort
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uid 135,0
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shape (Triangle
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va (VaSet
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vasetType 1
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xt "37250,18625,38000,19375"
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tg (CPTG
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uid 137,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "courier,9,0"
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)
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|
st "updateMem"
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|
blo "39000,19100"
|
|
tm "CptPortNameMgr"
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)
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)
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dt (MLText
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uid 139,0
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va (VaSet
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font "courier,8,0"
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)
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st "updateMem : IN std_ulogic ;"
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)
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thePort (LogicalPort
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decl (Decl
|
|
n "updateMem"
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t "std_ulogic"
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|
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|
suid 4,0
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|
)
|
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)
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uid 140,0
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shape (Triangle
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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tg (CPTG
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va (VaSet
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font "courier,9,0"
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)
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st "addr"
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ju 2
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|
blo "53000,17100"
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tm "CptPortNameMgr"
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dt (MLText
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uid 144,0
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va (VaSet
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font "courier,8,0"
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)
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st "addr : OUT unsigned (addressBitNb-1 DOWNTO 0) ;"
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)
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thePort (LogicalPort
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|
m 1
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|
decl (Decl
|
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n "addr"
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|
t "unsigned"
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b "(addressBitNb-1 DOWNTO 0)"
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|
o 5
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suid 5,0
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*71 (CptPort
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uid 155,0
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shape (Triangle
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uid 161,0
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ro 90
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va (VaSet
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vasetType 1
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)
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tg (CPTG
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uid 157,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 158,0
|
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va (VaSet
|
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font "courier,9,0"
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)
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st "patternSize"
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|
blo "39000,17100"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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font "courier,8,0"
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st "patternSize : IN unsigned (addressBitNb-1 DOWNTO 0)"
|
|
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thePort (LogicalPort
|
|
decl (Decl
|
|
n "patternSize"
|
|
t "unsigned"
|
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b "(addressBitNb-1 DOWNTO 0)"
|
|
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shape (Rectangle
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uid 81,0
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va (VaSet
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vasetType 1
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lineWidth 2
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biTextGroup (BiTextGroup
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uid 10,0
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second (Text
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va (VaSet
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uid 13,0
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ps "CenterOffsetStrategy"
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text (MLText
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|
|
|
addressBitNb positive 8 "
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header "Generic Declarations"
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|
showHdrWhenContentsEmpty 1
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elements [
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(GiElement
|
|
name "addressBitNb"
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|
type "positive"
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|
value "8"
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)
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portInstanceVisAsIs 1
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portInstanceVis (PortSigDisplay
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sTC 0
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portVis (PortSigDisplay
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sTC 0
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sF 0
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tm "CommentText"
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