4970 lines
58 KiB
Plaintext
4970 lines
58 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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instances [
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(Instance
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name "U_1"
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duLibraryName "gates"
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duName "and2"
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elements [
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(GiElement
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name "delay"
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type "time"
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value "0 ps"
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)
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]
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mwi 0
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uid 645,0
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)
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(Instance
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name "U_0"
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duLibraryName "gates"
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duName "or2"
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elements [
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(GiElement
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name "delay"
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type "time"
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value "0 ps"
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)
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]
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mwi 0
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uid 667,0
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)
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(Instance
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name "U_mainDecoder"
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duLibraryName "HEIRV32_SC"
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duName "mainDecoder"
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elements [
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(GiElement
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name "g_tDec"
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type "time"
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value "g_tDec"
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)
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]
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mwi 0
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uid 1321,0
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)
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(Instance
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name "U_aluDecoder"
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duLibraryName "HEIRV32"
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duName "aluDecoder"
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elements [
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|
(GiElement
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name "g_tDec"
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type "time"
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value "g_tDec"
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)
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]
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mwi 0
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uid 1351,0
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\master@version.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\master@version.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds"
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)
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|
(vvPair
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|
variable "appl"
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value "HDL Designer"
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|
)
|
|
(vvPair
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|
variable "arch_name"
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value "masterVersion"
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|
)
|
|
(vvPair
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|
variable "concat_file"
|
|
value "concatenated"
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|
)
|
|
(vvPair
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|
variable "config"
|
|
value "%(unit)_%(view)_config"
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|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit"
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)
|
|
(vvPair
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|
variable "d_logical"
|
|
value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit"
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)
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|
(vvPair
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|
variable "date"
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|
value "04.11.2022"
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|
)
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|
(vvPair
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|
variable "day"
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|
value "ven."
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|
)
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|
(vvPair
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|
variable "day_long"
|
|
value "vendredi"
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|
)
|
|
(vvPair
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|
variable "dd"
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value "04"
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)
|
|
(vvPair
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variable "entity_name"
|
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value "controlUnit"
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)
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|
(vvPair
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|
variable "ext"
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value "<TBD>"
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)
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(vvPair
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|
variable "f"
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value "master@version.bd"
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)
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(vvPair
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variable "f_logical"
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value "masterVersion.bd"
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)
|
|
(vvPair
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|
variable "f_noext"
|
|
value "master@version"
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)
|
|
(vvPair
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variable "graphical_source_author"
|
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value "axel.amand"
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)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
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value "04.11.2022"
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)
|
|
(vvPair
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|
variable "graphical_source_group"
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value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE7860"
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)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "11:25:12"
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)
|
|
(vvPair
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|
variable "group"
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value "UNKNOWN"
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)
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(vvPair
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|
variable "host"
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value "WE7860"
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)
|
|
(vvPair
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variable "language"
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value "VHDL"
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)
|
|
(vvPair
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variable "library"
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value "HEIRV32_SC"
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)
|
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(vvPair
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|
variable "library_downstream_Concatenation"
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value "$HDS_PROJECT_DIR/../Board/concat"
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)
|
|
(vvPair
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|
variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/CAr/RiscV/HEIRV32/SingleCycle/work"
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)
|
|
(vvPair
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|
variable "mm"
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value "11"
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)
|
|
(vvPair
|
|
variable "module_name"
|
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value "controlUnit"
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)
|
|
(vvPair
|
|
variable "month"
|
|
value "nov."
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|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "novembre"
|
|
)
|
|
(vvPair
|
|
variable "p"
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value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\control@unit\\master@version.bd"
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)
|
|
(vvPair
|
|
variable "p_logical"
|
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value "C:\\dev\\car-labs\\hdl\\Prefs\\..\\RiscV\\HEIRV32\\SingleCycle\\hds\\controlUnit\\masterVersion.bd"
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)
|
|
(vvPair
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|
variable "package_name"
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|
value "<Undefined Variable>"
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|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "master@version"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "masterVersion"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "11:25:12"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "controlUnit"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "masterVersion"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2022"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "22"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
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uid 276,0
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optionalChildren [
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shape (CompositeShape
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fg "0,0,32768"
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stc 0
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sf 1
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tg (WTG
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uid 27,0
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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va (VaSet
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lang 11
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uid 105,0
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lang 11
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decl (Decl
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t "std_ulogic_vector"
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b "(1 DOWNTO 0)"
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declText (MLText
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shape (CompositeShape
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tg (WTG
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tm "WireNameMgr"
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lang 11
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ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
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uid 1296,0
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va (VaSet
|
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font "Verdana,12,0"
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)
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xt "23900,32300,29000,33700"
|
|
st "branch"
|
|
ju 2
|
|
blo "29000,33500"
|
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)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
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decl (Decl
|
|
n "branch"
|
|
t "std_uLogic"
|
|
o 13
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*56 (CptPort
|
|
uid 1297,0
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ps "OnEdgeStrategy"
|
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shape (Triangle
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uid 1298,0
|
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ro 90
|
|
va (VaSet
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vasetType 1
|
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fg "0,65535,0"
|
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)
|
|
xt "30000,43625,30750,44375"
|
|
)
|
|
tg (CPTG
|
|
uid 1299,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1300,0
|
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va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "23800,43300,29000,44700"
|
|
st "immSrc"
|
|
ju 2
|
|
blo "29000,44500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
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lang 11
|
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m 1
|
|
decl (Decl
|
|
n "immSrc"
|
|
t "std_ulogic_vector"
|
|
b "(1 DOWNTO 0)"
|
|
o 8
|
|
suid 4,0
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)
|
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)
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)
|
|
*57 (CptPort
|
|
uid 1301,0
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ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 1302,0
|
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ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "30000,34625,30750,35375"
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)
|
|
tg (CPTG
|
|
uid 1303,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
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f (Text
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|
uid 1304,0
|
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va (VaSet
|
|
font "Verdana,12,0"
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|
)
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xt "25100,34300,29000,35700"
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|
st "jump"
|
|
ju 2
|
|
blo "29000,35500"
|
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)
|
|
)
|
|
thePort (LogicalPort
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m 1
|
|
decl (Decl
|
|
n "jump"
|
|
t "std_uLogic"
|
|
o 14
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*58 (CptPort
|
|
uid 1305,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1306,0
|
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ro 90
|
|
va (VaSet
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|
vasetType 1
|
|
fg "0,65535,0"
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)
|
|
xt "30000,39625,30750,40375"
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)
|
|
tg (CPTG
|
|
uid 1307,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
|
|
uid 1308,0
|
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va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "21800,39300,29000,40700"
|
|
st "memWrite"
|
|
ju 2
|
|
blo "29000,40500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "memWrite"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*59 (CptPort
|
|
uid 1309,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
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|
uid 1310,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "14250,35625,15000,36375"
|
|
)
|
|
tg (CPTG
|
|
uid 1311,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
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f (Text
|
|
uid 1312,0
|
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va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "16000,35300,18400,36700"
|
|
st "op"
|
|
blo "16000,36500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "op"
|
|
t "std_ulogic_vector"
|
|
b "(6 DOWNTO 0)"
|
|
o 3
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
*60 (CptPort
|
|
uid 1313,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1314,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "30000,45625,30750,46375"
|
|
)
|
|
tg (CPTG
|
|
uid 1315,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1316,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "22900,45300,29000,46700"
|
|
st "regwrite"
|
|
ju 2
|
|
blo "29000,46500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "regwrite"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
*61 (CptPort
|
|
uid 1317,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1318,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "30000,37625,30750,38375"
|
|
)
|
|
tg (CPTG
|
|
uid 1319,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1320,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "22700,37300,29000,38700"
|
|
st "resultSrc"
|
|
ju 2
|
|
blo "29000,38500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "resultSrc"
|
|
t "std_ulogic_vector"
|
|
b "(1 DOWNTO 0)"
|
|
o 11
|
|
suid 9,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1322,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
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|
lineWidth 2
|
|
)
|
|
xt "15000,31000,30000,50000"
|
|
)
|
|
oxt "15000,6000,30000,25000"
|
|
ttg (MlTextGroup
|
|
uid 1323,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*62 (Text
|
|
uid 1324,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "28700,50300,36100,51500"
|
|
st "HEIRV32_SC"
|
|
blo "28700,51300"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*63 (Text
|
|
uid 1325,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "28700,51500,36300,52700"
|
|
st "mainDecoder"
|
|
blo "28700,52500"
|
|
tm "CptNameMgr"
|
|
)
|
|
*64 (Text
|
|
uid 1326,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "28700,52700,37600,53900"
|
|
st "U_mainDecoder"
|
|
blo "28700,53700"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1327,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1328,0
|
|
text (MLText
|
|
uid 1329,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "29000,55200,45000,56000"
|
|
st "g_tDec = g_tDec ( time ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "g_tDec"
|
|
type "time"
|
|
value "g_tDec"
|
|
)
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
uid 1330,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "15250,48250,16750,49750"
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|
iconName "VhdlFileViewIcon.png"
|
|
iconMaskName "VhdlFileViewIcon.msk"
|
|
ftype 10
|
|
)
|
|
viewiconposition 0
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*65 (SaComponent
|
|
uid 1351,0
|
|
optionalChildren [
|
|
*66 (CptPort
|
|
uid 1331,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1332,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "30000,60625,30750,61375"
|
|
)
|
|
tg (CPTG
|
|
uid 1333,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1334,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "20400,60300,29000,61700"
|
|
st "ALUControl"
|
|
ju 2
|
|
blo "29000,61500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "ALUControl"
|
|
t "std_ulogic_vector"
|
|
b "(2 DOWNTO 0)"
|
|
o 7
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*67 (CptPort
|
|
uid 1335,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1336,0
|
|
ro 180
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "20625,55250,21375,56000"
|
|
)
|
|
tg (CPTG
|
|
uid 1337,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1338,0
|
|
ro 270
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "20300,57000,21700,62000"
|
|
st "ALUOp"
|
|
ju 2
|
|
blo "21500,57000"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "ALUOp"
|
|
t "std_ulogic_vector"
|
|
b "(1 DOWNTO 0)"
|
|
o 20
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*68 (CptPort
|
|
uid 1339,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1340,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "13250,59625,14000,60375"
|
|
)
|
|
tg (CPTG
|
|
uid 1341,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1342,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "15000,59300,19700,60700"
|
|
st "funct3"
|
|
blo "15000,60500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "funct3"
|
|
t "std_ulogic_vector"
|
|
b "(2 DOWNTO 0)"
|
|
o 2
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*69 (CptPort
|
|
uid 1343,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1344,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "13250,61625,14000,62375"
|
|
)
|
|
tg (CPTG
|
|
uid 1345,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1346,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "15000,61300,19700,62700"
|
|
st "funct7"
|
|
blo "15000,62500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "funct7"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*70 (CptPort
|
|
uid 1347,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1348,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "13250,57625,14000,58375"
|
|
)
|
|
tg (CPTG
|
|
uid 1349,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1350,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "15000,57300,17400,58700"
|
|
st "op"
|
|
blo "15000,58500"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "op"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1352,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "14000,56000,30000,65000"
|
|
)
|
|
oxt "20000,12000,36000,21000"
|
|
ttg (MlTextGroup
|
|
uid 1353,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*71 (Text
|
|
uid 1354,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "30650,62800,35650,64000"
|
|
st "HEIRV32"
|
|
blo "30650,63800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*72 (Text
|
|
uid 1355,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "30650,64000,37350,65200"
|
|
st "aluDecoder"
|
|
blo "30650,65000"
|
|
tm "CptNameMgr"
|
|
)
|
|
*73 (Text
|
|
uid 1356,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "30650,65200,38650,66400"
|
|
st "U_aluDecoder"
|
|
blo "30650,66200"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1357,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1358,0
|
|
text (MLText
|
|
uid 1359,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "31000,66200,47000,67000"
|
|
st "g_tDec = g_tDec ( time ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "g_tDec"
|
|
type "time"
|
|
value "g_tDec"
|
|
)
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
uid 1360,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "14250,63250,15750,64750"
|
|
iconName "VhdlFileViewIcon.png"
|
|
iconMaskName "VhdlFileViewIcon.msk"
|
|
ftype 10
|
|
)
|
|
viewiconposition 0
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*74 (Wire
|
|
uid 29,0
|
|
shape (OrthoPolyLine
|
|
uid 30,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "30750,42000,40000,42000"
|
|
pts [
|
|
"40000,42000"
|
|
"30750,42000"
|
|
]
|
|
)
|
|
start &1
|
|
end &54
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 33,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 34,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "39000,40800,43600,42000"
|
|
st "ALUSrc"
|
|
blo "39000,41800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &2
|
|
)
|
|
*75 (Wire
|
|
uid 99,0
|
|
shape (OrthoPolyLine
|
|
uid 100,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "30750,44000,40000,44000"
|
|
pts [
|
|
"40000,44000"
|
|
"30750,44000"
|
|
]
|
|
)
|
|
start &3
|
|
end &56
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 103,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 104,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "39000,42800,47800,44000"
|
|
st "immSrc : (1:0)"
|
|
blo "39000,43800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &4
|
|
)
|
|
*76 (Wire
|
|
uid 113,0
|
|
shape (OrthoPolyLine
|
|
uid 114,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "30750,40000,40000,40000"
|
|
pts [
|
|
"40000,40000"
|
|
"30750,40000"
|
|
]
|
|
)
|
|
start &5
|
|
end &58
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 117,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 118,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "39000,38800,44700,40000"
|
|
st "memWrite"
|
|
blo "39000,39800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &6
|
|
)
|
|
*77 (Wire
|
|
uid 141,0
|
|
shape (OrthoPolyLine
|
|
uid 142,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "52000,31000,56000,31000"
|
|
pts [
|
|
"56000,31000"
|
|
"52000,31000"
|
|
]
|
|
)
|
|
start &7
|
|
end &39
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 145,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 146,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "55000,29800,58900,31000"
|
|
st "PCSrc"
|
|
blo "55000,30800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &8
|
|
)
|
|
*78 (Wire
|
|
uid 155,0
|
|
shape (OrthoPolyLine
|
|
uid 156,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "30750,46000,40000,46000"
|
|
pts [
|
|
"40000,46000"
|
|
"30750,46000"
|
|
]
|
|
)
|
|
start &9
|
|
end &60
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 159,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 160,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "39000,44800,43700,46000"
|
|
st "regwrite"
|
|
blo "39000,45800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &10
|
|
)
|
|
*79 (Wire
|
|
uid 169,0
|
|
shape (OrthoPolyLine
|
|
uid 170,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "30750,38000,40000,38000"
|
|
pts [
|
|
"40000,38000"
|
|
"30750,38000"
|
|
]
|
|
)
|
|
start &11
|
|
end &61
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 173,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 174,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "39000,36800,48600,38000"
|
|
st "resultSrc : (1:0)"
|
|
blo "39000,37800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &12
|
|
)
|
|
*80 (Wire
|
|
uid 698,0
|
|
optionalChildren [
|
|
*81 (Ripper
|
|
uid 702,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"8000,36000"
|
|
"7000,37000"
|
|
]
|
|
uid 703,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "7000,36000,8000,37000"
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 699,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "6000,36000,14250,36000"
|
|
pts [
|
|
"6000,36000"
|
|
"14250,36000"
|
|
]
|
|
)
|
|
start &24
|
|
end &59
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 700,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 701,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "7000,34800,13200,36000"
|
|
st "op : (6:0)"
|
|
blo "7000,35800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &47
|
|
)
|
|
*82 (Wire
|
|
uid 704,0
|
|
shape (OrthoPolyLine
|
|
uid 705,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "7000,37000,13250,58000"
|
|
pts [
|
|
"7000,37000"
|
|
"7000,58000"
|
|
"13250,58000"
|
|
]
|
|
)
|
|
start &81
|
|
end &70
|
|
sat 32
|
|
eat 32
|
|
sl "(5)"
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 706,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 707,0
|
|
va (VaSet
|
|
)
|
|
xt "9000,56800,12400,58000"
|
|
st "op(5)"
|
|
blo "9000,57800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &47
|
|
)
|
|
*83 (Wire
|
|
uid 732,0
|
|
shape (OrthoPolyLine
|
|
uid 733,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "12000,62000,13250,62000"
|
|
pts [
|
|
"12000,62000"
|
|
"13250,62000"
|
|
]
|
|
)
|
|
start &26
|
|
end &69
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 734,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 735,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "12000,60800,15900,62000"
|
|
st "funct7"
|
|
blo "12000,61800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &49
|
|
)
|
|
*84 (Wire
|
|
uid 740,0
|
|
shape (OrthoPolyLine
|
|
uid 741,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "12000,60000,13250,60000"
|
|
pts [
|
|
"12000,60000"
|
|
"13250,60000"
|
|
]
|
|
)
|
|
start &25
|
|
end &68
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 742,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 743,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "7000,58800,15200,60000"
|
|
st "funct3 : (2:0)"
|
|
blo "7000,59800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &48
|
|
)
|
|
*85 (Wire
|
|
uid 748,0
|
|
shape (OrthoPolyLine
|
|
uid 749,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "42950,29000,45335,29000"
|
|
pts [
|
|
"42950,29000"
|
|
"45335,29000"
|
|
]
|
|
)
|
|
start &32
|
|
end &37
|
|
sat 32
|
|
eat 32
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 750,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 751,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "42950,27800,53150,29000"
|
|
st "out1 : std_uLogic"
|
|
blo "42950,28800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &44
|
|
)
|
|
*86 (Wire
|
|
uid 752,0
|
|
shape (OrthoPolyLine
|
|
uid 753,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "6000,27000,36000,27000"
|
|
pts [
|
|
"6000,27000"
|
|
"36000,27000"
|
|
]
|
|
)
|
|
start &27
|
|
end &30
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 754,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 755,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "8000,25800,10800,27000"
|
|
st "zero"
|
|
blo "8000,26800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &46
|
|
)
|
|
*87 (Wire
|
|
uid 764,0
|
|
shape (OrthoPolyLine
|
|
uid 765,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "30750,61000,33000,61000"
|
|
pts [
|
|
"33000,61000"
|
|
"30750,61000"
|
|
]
|
|
)
|
|
start &28
|
|
end &66
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 766,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 767,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "31000,59800,41900,61000"
|
|
st "ALUControl : (2:0)"
|
|
blo "31000,60800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &50
|
|
)
|
|
*88 (Wire
|
|
uid 782,0
|
|
shape (OrthoPolyLine
|
|
uid 783,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "30750,33000,45334,35000"
|
|
pts [
|
|
"45334,33000"
|
|
"33000,33000"
|
|
"33000,35000"
|
|
"30750,35000"
|
|
]
|
|
)
|
|
start &38
|
|
end &57
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 784,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 785,0
|
|
va (VaSet
|
|
)
|
|
xt "42000,31800,45100,33000"
|
|
st "jump"
|
|
blo "42000,32800"
|
|
tm "WireNameMgr"
|
|
)
|
|
s (Text
|
|
uid 786,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "42000,33000,42000,33000"
|
|
blo "42000,33000"
|
|
tm "SignalTypeMgr"
|
|
)
|
|
)
|
|
on &51
|
|
)
|
|
*89 (Wire
|
|
uid 787,0
|
|
shape (OrthoPolyLine
|
|
uid 788,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "30750,31000,36000,33000"
|
|
pts [
|
|
"36000,31000"
|
|
"32000,31000"
|
|
"32000,33000"
|
|
"30750,33000"
|
|
]
|
|
)
|
|
start &31
|
|
end &55
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 789,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 790,0
|
|
va (VaSet
|
|
)
|
|
xt "32000,29800,36100,31000"
|
|
st "branch"
|
|
blo "32000,30800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &43
|
|
)
|
|
*90 (Wire
|
|
uid 791,0
|
|
shape (OrthoPolyLine
|
|
uid 792,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "21000,50750,21000,55250"
|
|
pts [
|
|
"21000,50750"
|
|
"21000,55250"
|
|
]
|
|
)
|
|
start &53
|
|
end &67
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 793,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 794,0
|
|
va (VaSet
|
|
)
|
|
xt "22000,52800,26400,54000"
|
|
st "ALUOp"
|
|
blo "22000,53800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &45
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *91 (PackageList
|
|
uid 265,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*92 (Text
|
|
uid 266,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,0,7600,1200"
|
|
st "Package List"
|
|
blo "0,1000"
|
|
)
|
|
*93 (MLText
|
|
uid 267,0
|
|
va (VaSet
|
|
)
|
|
xt "0,1200,17500,7200"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
LIBRARY gates;
|
|
USE gates.gates.all;"
|
|
tm "PackageList"
|
|
)
|
|
]
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pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2900,1200"
|
|
st "sig0"
|
|
blo "0,1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,3800,1200"
|
|
st "dbus0"
|
|
blo "0,1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineColor "32768,0,0"
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,4700,1200"
|
|
st "bundle0"
|
|
blo "0,1000"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1200,1500,2400"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1300,18500,-100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1850,1650"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "250,250,1650,1450"
|
|
st "1"
|
|
blo "250,1250"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*118 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11200,20000,22000,21200"
|
|
st "Frame Declarations"
|
|
blo "11200,21000"
|
|
)
|
|
*119 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11200,21200,11200,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1300,11000,-100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1850,1650"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "250,250,1650,1450"
|
|
st "1"
|
|
blo "250,1250"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*120 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11200,20000,22000,21200"
|
|
st "Frame Declarations"
|
|
blo "11200,21000"
|
|
)
|
|
*121 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11200,21200,11200,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "20000,0,27400,1200"
|
|
st "Declarations"
|
|
blo "20000,1000"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "20000,1200,23700,2400"
|
|
st "Ports:"
|
|
blo "20000,2200"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "20000,0,25200,1200"
|
|
st "Pre User:"
|
|
blo "20000,1000"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "20000,11200,29500,12400"
|
|
st "Diagram Signals:"
|
|
blo "20000,12200"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "20000,0,26400,1200"
|
|
st "Post User:"
|
|
blo "20000,1000"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 44,0
|
|
usingSuid 1
|
|
emptyRow *122 (LEmptyRow
|
|
)
|
|
uid 278,0
|
|
optionalChildren [
|
|
*123 (RefLabelRowHdr
|
|
)
|
|
*124 (TitleRowHdr
|
|
)
|
|
*125 (FilterRowHdr
|
|
)
|
|
*126 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*127 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*128 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*129 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*130 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*131 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*132 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*133 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*134 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*135 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "ALUSrc"
|
|
t "std_uLogic"
|
|
o 6
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 217,0
|
|
)
|
|
*136 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "PCSrc"
|
|
t "std_uLogic"
|
|
o 7
|
|
suid 10,0
|
|
)
|
|
)
|
|
uid 219,0
|
|
)
|
|
*137 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "immSrc"
|
|
t "std_ulogic_vector"
|
|
b "(1 DOWNTO 0)"
|
|
o 8
|
|
suid 7,0
|
|
)
|
|
)
|
|
uid 221,0
|
|
)
|
|
*138 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "memWrite"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 8,0
|
|
)
|
|
)
|
|
uid 223,0
|
|
)
|
|
*139 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "regwrite"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 225,0
|
|
)
|
|
*140 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "resultSrc"
|
|
t "std_ulogic_vector"
|
|
b "(1 downto 0)"
|
|
o 11
|
|
suid 12,0
|
|
)
|
|
)
|
|
uid 227,0
|
|
)
|
|
*141 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "branch"
|
|
t "std_uLogic"
|
|
o 13
|
|
suid 31,0
|
|
)
|
|
)
|
|
uid 861,0
|
|
)
|
|
*142 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "out1"
|
|
t "std_uLogic"
|
|
o 15
|
|
suid 34,0
|
|
)
|
|
)
|
|
uid 863,0
|
|
)
|
|
*143 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 4
|
|
decl (Decl
|
|
n "ALUOp"
|
|
t "std_ulogic_vector"
|
|
b "(1 DOWNTO 0)"
|
|
o 12
|
|
suid 35,0
|
|
)
|
|
)
|
|
uid 865,0
|
|
)
|
|
*144 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "zero"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 36,0
|
|
)
|
|
)
|
|
uid 867,0
|
|
)
|
|
*145 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "op"
|
|
t "std_ulogic_vector"
|
|
b "(6 DOWNTO 0)"
|
|
o 3
|
|
suid 37,0
|
|
)
|
|
)
|
|
uid 869,0
|
|
)
|
|
*146 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "funct3"
|
|
t "std_ulogic_vector"
|
|
b "(2 DOWNTO 0)"
|
|
o 1
|
|
suid 41,0
|
|
)
|
|
)
|
|
uid 877,0
|
|
)
|
|
*147 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "funct7"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 42,0
|
|
)
|
|
)
|
|
uid 879,0
|
|
)
|
|
*148 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "ALUControl"
|
|
t "std_ulogic_vector"
|
|
b "(2 DOWNTO 0)"
|
|
o 5
|
|
suid 43,0
|
|
)
|
|
)
|
|
uid 881,0
|
|
)
|
|
*149 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "jump"
|
|
t "std_uLogic"
|
|
o 14
|
|
suid 44,0
|
|
)
|
|
)
|
|
uid 895,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 291,0
|
|
optionalChildren [
|
|
*150 (Sheet
|
|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *151 (MRCItem
|
|
litem &122
|
|
pos 15
|
|
dimension 20
|
|
)
|
|
uid 293,0
|
|
optionalChildren [
|
|
*152 (MRCItem
|
|
litem &123
|
|
pos 0
|
|
dimension 20
|
|
uid 294,0
|
|
)
|
|
*153 (MRCItem
|
|
litem &124
|
|
pos 1
|
|
dimension 23
|
|
uid 295,0
|
|
)
|
|
*154 (MRCItem
|
|
litem &125
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 296,0
|
|
)
|
|
*155 (MRCItem
|
|
litem &135
|
|
pos 0
|
|
dimension 20
|
|
uid 218,0
|
|
)
|
|
*156 (MRCItem
|
|
litem &136
|
|
pos 1
|
|
dimension 20
|
|
uid 220,0
|
|
)
|
|
*157 (MRCItem
|
|
litem &137
|
|
pos 2
|
|
dimension 20
|
|
uid 222,0
|
|
)
|
|
*158 (MRCItem
|
|
litem &138
|
|
pos 3
|
|
dimension 20
|
|
uid 224,0
|
|
)
|
|
*159 (MRCItem
|
|
litem &139
|
|
pos 4
|
|
dimension 20
|
|
uid 226,0
|
|
)
|
|
*160 (MRCItem
|
|
litem &140
|
|
pos 5
|
|
dimension 20
|
|
uid 228,0
|
|
)
|
|
*161 (MRCItem
|
|
litem &141
|
|
pos 11
|
|
dimension 20
|
|
uid 862,0
|
|
)
|
|
*162 (MRCItem
|
|
litem &142
|
|
pos 12
|
|
dimension 20
|
|
uid 864,0
|
|
)
|
|
*163 (MRCItem
|
|
litem &143
|
|
pos 13
|
|
dimension 20
|
|
uid 866,0
|
|
)
|
|
*164 (MRCItem
|
|
litem &144
|
|
pos 6
|
|
dimension 20
|
|
uid 868,0
|
|
)
|
|
*165 (MRCItem
|
|
litem &145
|
|
pos 7
|
|
dimension 20
|
|
uid 870,0
|
|
)
|
|
*166 (MRCItem
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|
litem &146
|
|
pos 8
|
|
dimension 20
|
|
uid 878,0
|
|
)
|
|
*167 (MRCItem
|
|
litem &147
|
|
pos 9
|
|
dimension 20
|
|
uid 880,0
|
|
)
|
|
*168 (MRCItem
|
|
litem &148
|
|
pos 10
|
|
dimension 20
|
|
uid 882,0
|
|
)
|
|
*169 (MRCItem
|
|
litem &149
|
|
pos 14
|
|
dimension 20
|
|
uid 896,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
textAngle 90
|
|
)
|
|
uid 297,0
|
|
optionalChildren [
|
|
*170 (MRCItem
|
|
litem &126
|
|
pos 0
|
|
dimension 20
|
|
uid 298,0
|
|
)
|
|
*171 (MRCItem
|
|
litem &128
|
|
pos 1
|
|
dimension 50
|
|
uid 299,0
|
|
)
|
|
*172 (MRCItem
|
|
litem &129
|
|
pos 2
|
|
dimension 100
|
|
uid 300,0
|
|
)
|
|
*173 (MRCItem
|
|
litem &130
|
|
pos 3
|
|
dimension 50
|
|
uid 301,0
|
|
)
|
|
*174 (MRCItem
|
|
litem &131
|
|
pos 4
|
|
dimension 100
|
|
uid 302,0
|
|
)
|
|
*175 (MRCItem
|
|
litem &132
|
|
pos 5
|
|
dimension 100
|
|
uid 303,0
|
|
)
|
|
*176 (MRCItem
|
|
litem &133
|
|
pos 6
|
|
dimension 50
|
|
uid 304,0
|
|
)
|
|
*177 (MRCItem
|
|
litem &134
|
|
pos 7
|
|
dimension 80
|
|
uid 305,0
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|
)
|
|
]
|
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)
|
|
fixedCol 4
|
|
fixedRow 2
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|
name "Ports"
|
|
uid 292,0
|
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vaOverrides [
|
|
]
|
|
)
|
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]
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)
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|
uid 277,0
|
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)
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|
genericsCommonDM (CommonDM
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|
ldm (LogicalDM
|
|
emptyRow *178 (LEmptyRow
|
|
)
|
|
uid 307,0
|
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optionalChildren [
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|
*179 (RefLabelRowHdr
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|
)
|
|
*180 (TitleRowHdr
|
|
)
|
|
*181 (FilterRowHdr
|
|
)
|
|
*182 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*183 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*184 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*185 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*186 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*187 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*188 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*189 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*190 (LogGeneric
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|
generic (GiElement
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|
name "g_tDec"
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|
type "time"
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|
value "25 ps"
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)
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uid 1261,0
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)
|
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]
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)
|
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pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
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|
uid 319,0
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optionalChildren [
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|
*191 (Sheet
|
|
sheetRow (SheetRow
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|
headerVa (MVa
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|
cellColor "49152,49152,49152"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
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|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
)
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|
emptyMRCItem *192 (MRCItem
|
|
litem &178
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 321,0
|
|
optionalChildren [
|
|
*193 (MRCItem
|
|
litem &179
|
|
pos 0
|
|
dimension 20
|
|
uid 322,0
|
|
)
|
|
*194 (MRCItem
|
|
litem &180
|
|
pos 1
|
|
dimension 23
|
|
uid 323,0
|
|
)
|
|
*195 (MRCItem
|
|
litem &181
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 324,0
|
|
)
|
|
*196 (MRCItem
|
|
litem &190
|
|
pos 0
|
|
dimension 20
|
|
uid 1260,0
|
|
)
|
|
]
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|
)
|
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sheetCol (SheetCol
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propVa (MVa
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|
cellColor "0,49152,49152"
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fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
textAngle 90
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)
|
|
uid 325,0
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|
optionalChildren [
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|
*197 (MRCItem
|
|
litem &182
|
|
pos 0
|
|
dimension 20
|
|
uid 326,0
|
|
)
|
|
*198 (MRCItem
|
|
litem &184
|
|
pos 1
|
|
dimension 50
|
|
uid 327,0
|
|
)
|
|
*199 (MRCItem
|
|
litem &185
|
|
pos 2
|
|
dimension 100
|
|
uid 328,0
|
|
)
|
|
*200 (MRCItem
|
|
litem &186
|
|
pos 3
|
|
dimension 100
|
|
uid 329,0
|
|
)
|
|
*201 (MRCItem
|
|
litem &187
|
|
pos 4
|
|
dimension 50
|
|
uid 330,0
|
|
)
|
|
*202 (MRCItem
|
|
litem &188
|
|
pos 5
|
|
dimension 50
|
|
uid 331,0
|
|
)
|
|
*203 (MRCItem
|
|
litem &189
|
|
pos 6
|
|
dimension 80
|
|
uid 332,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 320,0
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|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
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|
uid 306,0
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|
type 1
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)
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|
activeModelName "BlockDiag"
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)
|