58 lines
2.0 KiB
VHDL
58 lines
2.0 KiB
VHDL
ARCHITECTURE masterVersion OF sineTable IS
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signal changeSign : std_uLogic;
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signal flipPhase : std_uLogic;
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signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0);
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signal phaseTableAddress2 : unsigned(phaseTableAddress1'range);
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signal quarterSine : signed(sine'range);
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signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine
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begin
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changeSign <= phase(phase'high);
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flipPhase <= phase(phase'high-1);
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phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
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checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1)
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begin
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if (flipPhase xor shiftPhase) = '0' then
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phaseTableAddress2 <= phaseTableAddress1;
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else
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phaseTableAddress2 <= 0 - phaseTableAddress1;
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end if;
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end process checkPhase;
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quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase)
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begin
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case to_integer(phaseTableAddress2) is
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when 0 => if (flipPhase xor shiftPhase) = '0' then
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quarterSine <= to_signed(16#0000#, quarterSine'length);
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else
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quarterSine <= to_signed(16#7FFF#, quarterSine'length);
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end if;
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when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
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when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
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when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length);
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when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length);
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when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length);
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when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length);
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when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
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when others => quarterSine <= (others => '-');
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end case;
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end process quarterTable;
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checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine)
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begin
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if (changeSign xor (flipPhase and shiftPhase)) = '0' then
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sine <= quarterSine;
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else
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sine <= 0 - quarterSine;
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end if;
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end process checkSign;
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END ARCHITECTURE masterVersion;
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