127 lines
3.4 KiB
Plaintext
127 lines
3.4 KiB
Plaintext
--
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-- VHDL Architecture Lissajous.lissajousGenerator.struct
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:47:09 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY DigitalToAnalogConverter;
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LIBRARY SplineInterpolator;
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ARCHITECTURE struct OF lissajousGenerator IS
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-- Architecture declarations
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-- Internal signal declarations
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SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
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SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
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-- Component Declarations
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COMPONENT DAC
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GENERIC (
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signalBitNb : positive := 16
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);
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PORT (
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serialOut : OUT std_ulogic ;
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parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
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clock : IN std_ulogic ;
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reset : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT sineGen
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GENERIC (
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signalBitNb : positive := 16;
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phaseBitNb : positive := 10
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);
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PORT (
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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step : IN unsigned (phaseBitNb-1 DOWNTO 0);
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sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
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sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
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square : OUT unsigned (signalBitNb-1 DOWNTO 0);
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triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
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FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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triggerOut <= squareY(squareY'high);
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-- HDL Embedded Text Block 2 eb2
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stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length);
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-- HDL Embedded Text Block 3 eb3
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stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length);
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-- Instance port mappings.
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I_dacX : DAC
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GENERIC MAP (
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signalBitNb => signalBitNb
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)
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PORT MAP (
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serialOut => xOut,
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parallelIn => sineX,
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clock => clock,
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reset => reset
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);
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I_dacY : DAC
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GENERIC MAP (
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signalBitNb => signalBitNb
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)
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PORT MAP (
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serialOut => yOut,
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parallelIn => sineY,
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clock => clock,
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reset => reset
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);
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I_sinX : sineGen
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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step => stepXUnsigned,
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sawtooth => OPEN,
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sine => sineX,
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square => OPEN,
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triangle => OPEN
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);
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I_sinY : sineGen
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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step => stepYUnsigned,
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sawtooth => OPEN,
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sine => sineY,
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square => squareY,
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triangle => OPEN
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);
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END struct;
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