39 lines
983 B
VHDL
39 lines
983 B
VHDL
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
|
|
|
|
subtype st is signed(coeffBitNb-1+oversamplingBitNb+8 DOWNTO 0);
|
|
signal x: st;
|
|
signal u: st;
|
|
signal v: st;
|
|
signal w: st;
|
|
|
|
BEGIN
|
|
|
|
process(clock, reset) begin
|
|
if reset = '1' then
|
|
x <= (others => '0');
|
|
u <= (others => '0');
|
|
v <= (others => '0');
|
|
w <= (others => '0');
|
|
elsif rising_edge(clock) then
|
|
|
|
if restartPolynom = '1' then
|
|
|
|
x <= resize(d, st'high+1) sla (oversamplingBitNb * 3 + 1);
|
|
u <= resize(a, st'high+1) + (resize(b, st'high+1) sla oversamplingBitNb) + (resize(c, st'high+1) sla (oversamplingBitNb*2));
|
|
v <= resize(6*a, v'length) + (resize(b, st'high+1) sla (oversamplingBitNb + 1));
|
|
w <= resize(6*a, w'length);
|
|
|
|
else
|
|
|
|
x <= x + u;
|
|
u <= u + v;
|
|
v <= v + w;
|
|
|
|
end if;
|
|
|
|
end if;
|
|
end process;
|
|
|
|
sampleOut <= resize(x sra (oversamplingBitNb * 3 + 1),signalBitNb);
|
|
END ARCHITECTURE studentVersion;
|