85 lines
2.1 KiB
VHDL
85 lines
2.1 KiB
VHDL
-- ------------------------------------------------------------------------------
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-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch)
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-- ------------------------------------------------------------------------------
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-- FIFO bridge with bus width adaptation
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-- A register that connects two FIFOs.
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-- Many IP blocks nowadays have FIFO or FIFO-like interfaces and often they
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-- have to be connected. This block can the be used for this task.
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--
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-- Created on 2012
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--
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-- Author: Oliver A. Gubler (oliver.gubler@hevs.ch)
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--
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-- 2016-04-01: fix bug in FWFT read when full
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-- 2016-03-22: +add FirstWordFallThrough (FWFT) generic
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-- 2012: +intital release
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-- ------------------------------------------------------------------------------
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--
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ARCHITECTURE RTL OF fifoBridgeRxToTx IS
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signal read1: std_ulogic;
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signal read2: std_ulogic;
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signal read: std_ulogic;
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signal storedData: std_ulogic_vector(data1'range);
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signal write: std_ulogic;
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BEGIN
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readControl: process(reset, clock)
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begin
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if reset = '1' then
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read1 <= '0';
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read2 <= '0';
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elsif rising_edge(clock) then
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if (empty1 = '0') and (full2 = '0') then
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read1 <= '1';
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else
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read1 <= '0';
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end if;
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read2 <= read1;
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end if;
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end process readControl;
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read <= not empty1 and not full2 when firstWordFallThrough
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else not empty1 and read1;
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rd1 <= read;
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readData: process(reset, clock)
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begin
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if reset = '1' then
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storedData <= (others => '0');
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elsif rising_edge(clock) then
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if firstWordFallThrough then
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storedData <= data1;
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else
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if read = '1' then
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storedData <= data1;
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end if;
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end if;
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end if;
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end process readData;
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data2 <= storedData;
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writeControl: process(reset, clock)
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begin
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if reset = '1' then
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write <= '0';
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elsif rising_edge(clock) then
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if firstWordFallThrough then
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write <= not empty1 and not full2;
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else
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if read = '1' then
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write <= '1';
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else
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write <= '0';
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end if;
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end if;
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end if;
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end process writeControl;
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wr2 <= write;
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end RTL;
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