4419 lines
52 KiB
Plaintext
4419 lines
52 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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instances [
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(Instance
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name "I_inv1"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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mwi 0
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(Instance
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name "I_dff"
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duLibraryName "Board"
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duName "DFF"
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elements [
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mwi 0
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)
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(Instance
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name "I_inv2"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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]
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mwi 0
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uid 176,0
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)
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(Instance
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name "I_cnt"
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duLibraryName "PipelinedOperators"
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duName "pipelineCounter"
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elements [
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(GiElement
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name "bitNb"
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type "positive"
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value "counterBitNb"
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name "stageNb"
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type "positive"
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value "pipelineStageNb"
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mwi 0
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(Instance
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duLibraryName "Lattice"
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duName "pll"
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elements [
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mwi 0
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uid 323,0
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embeddedInstances [
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(EmbeddedInstance
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name "eb5"
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number "5"
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)
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(EmbeddedInstance
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name "eb6"
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number "6"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds"
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipeline@counter_ebs3\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipeline@counter_ebs3\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds"
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(vvPair
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variable "appl"
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value "HDL Designer"
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variable "arch_name"
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value "struct"
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variable "concat_file"
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value "concatenated"
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variable "config"
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value "%(unit)_%(view)_config"
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(vvPair
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variable "d_logical"
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(vvPair
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variable "date"
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value "08.05.2023"
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(vvPair
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variable "day"
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value "lun."
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)
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(vvPair
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variable "day_long"
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value "lundi"
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)
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(vvPair
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variable "dd"
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value "08"
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(vvPair
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variable "entity_name"
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value "pipelineCounter_ebs3"
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(vvPair
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variable "ext"
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value "<TBD>"
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(vvPair
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variable "f"
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value "struct.bd"
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)
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(vvPair
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variable "f_logical"
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value "struct.bd"
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(vvPair
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variable "f_noext"
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value "struct"
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(vvPair
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variable "graphical_source_author"
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value "axel.amand"
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(vvPair
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variable "graphical_source_date"
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value "08.05.2023"
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(vvPair
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variable "graphical_source_group"
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value "UNKNOWN"
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(vvPair
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variable "graphical_source_host"
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value "WE7860"
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(vvPair
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variable "graphical_source_time"
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value "11:16:01"
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(vvPair
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variable "group"
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value "UNKNOWN"
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)
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(vvPair
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variable "host"
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value "WE7860"
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)
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(vvPair
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variable "language"
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value "VHDL"
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)
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(vvPair
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variable "library"
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value "Board"
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)
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(vvPair
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variable "library_downstream_Concatenation"
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value "$HDS_PROJECT_DIR/../Board/concat"
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)
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(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/Board"
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)
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(vvPair
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variable "mm"
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value "05"
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(vvPair
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variable "module_name"
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value "pipelineCounter_ebs3"
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(vvPair
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variable "month"
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value "mai"
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(vvPair
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variable "month_long"
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value "mai"
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(vvPair
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variable "p"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipeline@counter_ebs3\\struct.bd"
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)
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(vvPair
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variable "p_logical"
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value "C:\\dev\\sem-labs\\10-PipelinedOperators\\Prefs\\..\\Board\\hds\\pipelineCounter_ebs3\\struct.bd"
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)
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(vvPair
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variable "package_name"
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value "<Undefined Variable>"
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(vvPair
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variable "project_name"
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value "hds"
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(vvPair
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variable "series"
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value "HDL Designer Series"
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(vvPair
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variable "this_ext"
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value "bd"
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(vvPair
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variable "this_file"
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value "struct"
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(vvPair
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variable "this_file_logical"
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value "struct"
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(vvPair
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variable "time"
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value "11:16:01"
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(vvPair
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variable "unit"
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value "pipelineCounter_ebs3"
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(vvPair
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variable "user"
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value "axel.amand"
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(vvPair
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variable "version"
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value "2019.2 (Build 5)"
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(vvPair
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variable "view"
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value "struct"
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(vvPair
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variable "year"
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value "2023"
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(vvPair
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variable "yy"
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value "23"
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tg (WTG
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tm "WireNameMgr"
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tg (WTG
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stg "STSignalDisplayStrategy"
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commentText (CommentText
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shape (Rectangle
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tm "HdlTextMgr"
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stg "VerticalLayoutStrategy"
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va (VaSet
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tm "HdlTextNameMgr"
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va (VaSet
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st "5"
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blo "35400,30000"
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tm "HdlTextNumberMgr"
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uid 130,0
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va (VaSet
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ro 90
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va (VaSet
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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isHidden 1
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font "Verdana,12,0"
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)
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st "in1"
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va (VaSet
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font "Verdana,12,0"
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blo "37000,34900"
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thePort (LogicalPort
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n "in1"
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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va (VaSet
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st "out1"
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font "Verdana,12,0"
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decl (Decl
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n "out1"
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ro 90
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va (VaSet
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oxt "23000,4000,28000,10000"
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ttg (MlTextGroup
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uid 132,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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uid 133,0
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va (VaSet
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)
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st "Board"
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blo "38460,37700"
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tm "BdLibraryNameMgr"
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)
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uid 134,0
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va (VaSet
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st "inverterIn"
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blo "38460,38700"
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tm "CptNameMgr"
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)
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uid 135,0
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va (VaSet
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)
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st "I_inv1"
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blo "38460,39700"
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tm "InstanceNameMgr"
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ga (GenericAssociation
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uid 136,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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text (MLText
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uid 138,0
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va (VaSet
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)
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xt "37000,37400,37000,37400"
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)
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header ""
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)
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elements [
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portVis (PortSigDisplay
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sN 0
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sTC 0
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uid 150,0
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uid 159,0
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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st "D"
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blo "49000,26500"
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thePort (LogicalPort
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decl (Decl
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n "D"
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t "std_uLogic"
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o 3
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*27 (CptPort
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uid 163,0
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optionalChildren [
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pts [
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uid 167,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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ro 90
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va (VaSet
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isHidden 1
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fg "0,65535,0"
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)
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tg (CPTG
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uid 165,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 166,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "49000,29400,52200,30800"
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st "CLK"
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blo "49000,30600"
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "CLK"
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t "std_uLogic"
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o 1
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)
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)
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)
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uid 168,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 169,0
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va (VaSet
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vasetType 1
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isHidden 1
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fg "0,65535,0"
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tg (CPTG
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uid 170,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 171,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "50000,30600,53200,32000"
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st "CLR"
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blo "50000,31800"
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "CLR"
|
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t "std_uLogic"
|
|
o 2
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)
|
|
)
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|
)
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*30 (CptPort
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uid 172,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 173,0
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ro 90
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va (VaSet
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vasetType 1
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isHidden 1
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fg "0,65535,0"
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)
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xt "54000,25625,54750,26375"
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)
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tg (CPTG
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uid 174,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 175,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "51200,25300,53000,26700"
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st "Q"
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|
ju 2
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blo "53000,26500"
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)
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thePort (LogicalPort
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|
m 1
|
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decl (Decl
|
|
n "Q"
|
|
t "std_uLogic"
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|
o 4
|
|
)
|
|
)
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)
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]
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shape (Rectangle
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uid 151,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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)
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xt "48000,24000,54000,32000"
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)
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showPorts 0
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oxt "0,0,8000,10000"
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ttg (MlTextGroup
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uid 152,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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uid 153,0
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va (VaSet
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)
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xt "52600,31700,56200,32900"
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st "Board"
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blo "52600,32700"
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tm "BdLibraryNameMgr"
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)
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uid 154,0
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va (VaSet
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xt "52600,32700,55300,33900"
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st "DFF"
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blo "52600,33700"
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tm "CptNameMgr"
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)
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uid 155,0
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va (VaSet
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)
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xt "52600,33700,55600,34900"
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st "I_dff"
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|
blo "52600,34700"
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tm "InstanceNameMgr"
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)
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)
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ga (GenericAssociation
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|
uid 156,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 157,0
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text (MLText
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uid 158,0
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va (VaSet
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)
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|
xt "25000,21000,25000,21000"
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|
)
|
|
header ""
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|
)
|
|
elements [
|
|
]
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)
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|
portVis (PortSigDisplay
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|
sTC 0
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sT 1
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)
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archFileType "UNKNOWN"
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*34 (SaComponent
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uid 176,0
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optionalChildren [
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*35 (CptPort
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uid 185,0
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optionalChildren [
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*36 (Circle
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uid 190,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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lineColor "0,32896,0"
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|
lineWidth 2
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)
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xt "58092,25546,59000,26454"
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radius 454
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)
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|
]
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 186,0
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|
ro 90
|
|
va (VaSet
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vasetType 1
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|
isHidden 1
|
|
fg "0,65535,0"
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|
)
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|
xt "57342,25625,58092,26375"
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)
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tg (CPTG
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|
uid 187,0
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ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
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f (Text
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uid 188,0
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va (VaSet
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isHidden 1
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font "Verdana,12,0"
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)
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xt "59000,25500,61700,26900"
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|
st "in1"
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|
blo "59000,26700"
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uid 189,0
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va (VaSet
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isHidden 1
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font "Verdana,12,0"
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)
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xt "59000,26900,59000,26900"
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|
blo "59000,26900"
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|
)
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|
)
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thePort (LogicalPort
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|
decl (Decl
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|
n "in1"
|
|
t "std_uLogic"
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|
o 1
|
|
)
|
|
)
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)
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*37 (CptPort
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uid 191,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 192,0
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ro 90
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|
va (VaSet
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vasetType 1
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isHidden 1
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fg "0,65535,0"
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)
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xt "64000,25625,64750,26375"
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tg (CPTG
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uid 193,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 194,0
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va (VaSet
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isHidden 1
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font "Verdana,12,0"
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)
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xt "60050,25500,63750,26900"
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st "out1"
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ju 2
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blo "63750,26700"
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ju 2
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blo "63750,26900"
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thePort (LogicalPort
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n "out1"
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oxt "23000,4000,28000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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textVec [
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va (VaSet
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blo "60460,29700"
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tm "BdLibraryNameMgr"
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uid 180,0
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st "inverterIn"
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blo "60460,30700"
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tm "CptNameMgr"
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)
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uid 181,0
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va (VaSet
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)
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xt "60460,30700,64460,31900"
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st "I_inv2"
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blo "60460,31700"
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tm "InstanceNameMgr"
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)
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)
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ga (GenericAssociation
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uid 182,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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sTC 0
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va (VaSet
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vasetType 1
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tg (CPTG
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stg "RightVerticalLayoutStrategy"
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ju 2
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blo "86000,22550"
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thePort (LogicalPort
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m 1
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decl (Decl
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n "countOut"
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t "unsigned"
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b "(bitNb-1 downto 0)"
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)
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ro 90
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va (VaSet
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vasetType 1
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tg (CPTG
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stg "VerticalLayoutStrategy"
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va (VaSet
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st "clock"
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blo "72000,22400"
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)
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)
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thePort (LogicalPort
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decl (Decl
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t "std_ulogic"
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uid 213,0
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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vasetType 1
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)
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tg (CPTG
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uid 215,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 216,0
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va (VaSet
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)
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xt "72000,23550,75300,24750"
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st "reset"
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blo "72000,24550"
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 3
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)
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)
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]
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va (VaSet
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vasetType 1
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lineColor "0,32896,0"
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)
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xt "71000,18000,87000,26000"
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)
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|
oxt "32000,15000,48000,23000"
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ttg (MlTextGroup
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uid 198,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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uid 199,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "71600,25800,82400,27000"
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st "PipelinedOperators"
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blo "71600,26800"
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tm "BdLibraryNameMgr"
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)
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|
*46 (Text
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uid 200,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "71600,26700,80600,27900"
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st "pipelineCounter"
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|
blo "71600,27700"
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tm "CptNameMgr"
|
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)
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|
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uid 201,0
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va (VaSet
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|
font "Verdana,9,1"
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)
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xt "71600,27600,74900,28800"
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st "I_cnt"
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|
blo "71600,28600"
|
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tm "InstanceNameMgr"
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|
)
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]
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)
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|
ga (GenericAssociation
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|
uid 202,0
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ps "EdgeToEdgeStrategy"
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|
matrix (Matrix
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uid 203,0
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text (MLText
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uid 204,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "71000,29400,90400,31400"
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st "bitNb = counterBitNb ( positive )
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|
stageNb = pipelineStageNb ( positive ) "
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)
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header ""
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)
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elements [
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(GiElement
|
|
name "bitNb"
|
|
type "positive"
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|
value "counterBitNb"
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|
)
|
|
(GiElement
|
|
name "stageNb"
|
|
type "positive"
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|
value "pipelineStageNb"
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|
)
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]
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)
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|
ordering 1
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connectByName 1
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portVis (PortSigDisplay
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sTC 0
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)
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|
archFileType "UNKNOWN"
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)
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shape (CompositeShape
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uid 218,0
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va (VaSet
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vasetType 1
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fg "0,0,32768"
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)
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optionalChildren [
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(Pentagon
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uid 219,0
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sl 0
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ro 270
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xt "95500,21625,97000,22375"
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(Line
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uid 220,0
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sl 0
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ro 270
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xt "95000,22000,95500,22000"
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pts [
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|
"95000,22000"
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"95500,22000"
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]
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)
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]
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)
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tg (WTG
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uid 221,0
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ps "PortIoTextPlaceStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 222,0
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va (VaSet
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isHidden 1
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font "Verdana,12,0"
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)
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xt "98000,21300,124300,22700"
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st "countOut : (counterBitNb-1 downto 0)"
|
|
blo "98000,22500"
|
|
tm "WireNameMgr"
|
|
)
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|
)
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)
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|
*49 (Net
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uid 259,0
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decl (Decl
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n "reset_n"
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|
t "std_ulogic"
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|
o 1
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|
suid 1,0
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)
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declText (MLText
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uid 260,0
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va (VaSet
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)
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xt "2000,11600,15600,12800"
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st "reset_n : std_ulogic
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"
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)
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)
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*50 (Net
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uid 261,0
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decl (Decl
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n "resetSynch"
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|
|
suid 2,0
|
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)
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declText (MLText
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uid 262,0
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va (VaSet
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)
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st "SIGNAL resetSynch : std_ulogic
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"
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)
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)
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|
*51 (Net
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uid 263,0
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decl (Decl
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n "clock"
|
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t "std_ulogic"
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suid 3,0
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)
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declText (MLText
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|
uid 264,0
|
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va (VaSet
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)
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xt "2000,10400,15100,11600"
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|
st "clock : std_ulogic
|
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"
|
|
)
|
|
)
|
|
*52 (Net
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uid 265,0
|
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decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
declText (MLText
|
|
uid 266,0
|
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va (VaSet
|
|
)
|
|
xt "2000,20000,19500,21200"
|
|
st "SIGNAL reset : std_ulogic
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|
"
|
|
)
|
|
)
|
|
*53 (Net
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uid 269,0
|
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decl (Decl
|
|
n "logic1"
|
|
t "std_uLogic"
|
|
o 6
|
|
suid 6,0
|
|
)
|
|
declText (MLText
|
|
uid 270,0
|
|
va (VaSet
|
|
)
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|
xt "2000,18800,20000,20000"
|
|
st "SIGNAL logic1 : std_uLogic
|
|
"
|
|
)
|
|
)
|
|
*54 (Net
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|
uid 271,0
|
|
decl (Decl
|
|
n "countOut"
|
|
t "unsigned"
|
|
b "(counterBitNb-1 downto 0)"
|
|
o 7
|
|
suid 7,0
|
|
)
|
|
declText (MLText
|
|
uid 272,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,12800,29600,14000"
|
|
st "countOut : unsigned(counterBitNb-1 downto 0)
|
|
"
|
|
)
|
|
)
|
|
*55 (SaComponent
|
|
uid 323,0
|
|
optionalChildren [
|
|
*56 (CptPort
|
|
uid 287,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 288,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "58000,18625,58750,19375"
|
|
)
|
|
tg (CPTG
|
|
uid 289,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 290,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "52700,18500,57000,19500"
|
|
st "clk10MHz"
|
|
ju 2
|
|
blo "57000,19300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk10MHz"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*57 (CptPort
|
|
uid 291,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 292,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "58000,17625,58750,18375"
|
|
)
|
|
tg (CPTG
|
|
uid 293,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 294,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "52700,17500,57000,18500"
|
|
st "clk50MHz"
|
|
ju 2
|
|
blo "57000,18300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk50MHz"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*58 (CptPort
|
|
uid 295,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 296,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "58000,14625,58750,15375"
|
|
)
|
|
tg (CPTG
|
|
uid 297,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 298,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "52700,14500,57000,15500"
|
|
st "clk60MHz"
|
|
ju 2
|
|
blo "57000,15300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk60MHz"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*59 (CptPort
|
|
uid 299,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 300,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "58000,16625,58750,17375"
|
|
)
|
|
tg (CPTG
|
|
uid 301,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 302,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "52700,16500,57000,17500"
|
|
st "clk75MHz"
|
|
ju 2
|
|
blo "57000,17300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk75MHz"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*60 (CptPort
|
|
uid 303,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 304,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,18625,46000,19375"
|
|
)
|
|
tg (CPTG
|
|
uid 305,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 306,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "47000,18500,50200,19500"
|
|
st "en10M"
|
|
blo "47000,19300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en10M"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*61 (CptPort
|
|
uid 307,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 308,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,17625,46000,18375"
|
|
)
|
|
tg (CPTG
|
|
uid 309,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 310,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "47000,17500,50200,18500"
|
|
st "en50M"
|
|
blo "47000,18300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en50M"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
*62 (CptPort
|
|
uid 311,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 312,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,16625,46000,17375"
|
|
)
|
|
tg (CPTG
|
|
uid 313,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 314,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "47000,16500,50200,17500"
|
|
st "en75M"
|
|
blo "47000,17300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en75M"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
*63 (CptPort
|
|
uid 315,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 316,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "58000,20625,58750,21375"
|
|
)
|
|
tg (CPTG
|
|
uid 317,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 318,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "52800,20500,57000,21500"
|
|
st "pllLocked"
|
|
ju 2
|
|
blo "57000,21300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "pllLocked"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 9,0
|
|
)
|
|
)
|
|
)
|
|
*64 (CptPort
|
|
uid 319,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 320,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "45250,14625,46000,15375"
|
|
)
|
|
tg (CPTG
|
|
uid 321,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 322,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "47000,14500,51600,15500"
|
|
st "clkIn100M"
|
|
blo "47000,15300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "clkIn100M"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 10,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 324,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "46000,14000,58000,22000"
|
|
)
|
|
oxt "20000,20000,32000,28000"
|
|
ttg (MlTextGroup
|
|
uid 325,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*65 (Text
|
|
uid 326,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "54400,11000,58100,12000"
|
|
st "Lattice"
|
|
blo "54400,11800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*66 (Text
|
|
uid 327,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "54400,12000,56200,13000"
|
|
st "pll"
|
|
blo "54400,12800"
|
|
tm "CptNameMgr"
|
|
)
|
|
*67 (Text
|
|
uid 328,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "54400,13000,57200,14000"
|
|
st "I_pll"
|
|
blo "54400,13800"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 329,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 330,0
|
|
text (MLText
|
|
uid 331,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "22000,-55200,22000,-55200"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
uid 332,0
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "46250,20250,47750,21750"
|
|
iconName "VhdlFileViewIcon.png"
|
|
iconMaskName "VhdlFileViewIcon.msk"
|
|
ftype 10
|
|
)
|
|
ordering 1
|
|
viewiconposition 0
|
|
portVis (PortSigDisplay
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*68 (Net
|
|
uid 339,0
|
|
lang 11
|
|
decl (Decl
|
|
n "clk_sys"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 9,0
|
|
)
|
|
declText (MLText
|
|
uid 340,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,17200,19500,18000"
|
|
st "SIGNAL clk_sys : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*69 (HdlText
|
|
uid 341,0
|
|
optionalChildren [
|
|
*70 (EmbeddedText
|
|
uid 346,0
|
|
commentText (CommentText
|
|
uid 347,0
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
uid 348,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "33000,17000,39000,19000"
|
|
)
|
|
oxt "0,0,18000,5000"
|
|
text (MLText
|
|
uid 349,0
|
|
va (VaSet
|
|
)
|
|
xt "33200,17200,38700,18400"
|
|
st "
|
|
logic0 <= '0';
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 2000
|
|
visibleWidth 6000
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 342,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "32000,16000,40000,20000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 343,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*71 (Text
|
|
uid 344,0
|
|
va (VaSet
|
|
)
|
|
xt "32400,20000,35000,21200"
|
|
st "eb6"
|
|
blo "32400,21000"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*72 (Text
|
|
uid 345,0
|
|
va (VaSet
|
|
)
|
|
xt "32400,21000,33800,22200"
|
|
st "6"
|
|
blo "32400,22000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*73 (Net
|
|
uid 370,0
|
|
lang 11
|
|
decl (Decl
|
|
n "logic0"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 11,0
|
|
)
|
|
declText (MLText
|
|
uid 371,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,18000,19500,18800"
|
|
st "SIGNAL logic0 : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*74 (Net
|
|
uid 376,0
|
|
decl (Decl
|
|
n "resetSynch_n"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 12,0
|
|
)
|
|
declText (MLText
|
|
uid 377,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,22400,19500,23200"
|
|
st "SIGNAL resetSynch_n : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*75 (Wire
|
|
uid 223,0
|
|
shape (OrthoPolyLine
|
|
uid 224,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "43000,26000,48000,26000"
|
|
pts [
|
|
"48000,26000"
|
|
"43000,26000"
|
|
]
|
|
)
|
|
start &26
|
|
end &14
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 227,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 228,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "44000,24600,48400,26000"
|
|
st "logic1"
|
|
blo "44000,25800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &53
|
|
)
|
|
*76 (Wire
|
|
uid 229,0
|
|
shape (OrthoPolyLine
|
|
uid 230,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "46000,30000,48000,30000"
|
|
pts [
|
|
"46000,30000"
|
|
"48000,30000"
|
|
]
|
|
)
|
|
end &27
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 233,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 234,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "44000,28600,47800,30000"
|
|
st "clock"
|
|
blo "44000,29800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &51
|
|
)
|
|
*77 (Wire
|
|
uid 235,0
|
|
shape (OrthoPolyLine
|
|
uid 236,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "54000,26000,58092,26000"
|
|
pts [
|
|
"54000,26000"
|
|
"58092,26000"
|
|
]
|
|
)
|
|
start &30
|
|
end &35
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 237,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 238,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "53000,24600,63200,26000"
|
|
st "resetSynch_n"
|
|
blo "53000,25800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &74
|
|
)
|
|
*78 (Wire
|
|
uid 239,0
|
|
shape (OrthoPolyLine
|
|
uid 240,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "87750,22000,95000,22000"
|
|
pts [
|
|
"87750,22000"
|
|
"95000,22000"
|
|
]
|
|
)
|
|
start &42
|
|
end &48
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 241,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 242,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "90000,20700,96600,22100"
|
|
st "countOut"
|
|
blo "90000,21900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &54
|
|
)
|
|
*79 (Wire
|
|
uid 243,0
|
|
shape (OrthoPolyLine
|
|
uid 244,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "31000,34000,36092,34000"
|
|
pts [
|
|
"31000,34000"
|
|
"36092,34000"
|
|
]
|
|
)
|
|
start &12
|
|
end &19
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 245,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 246,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "30000,32600,35700,34000"
|
|
st "reset_n"
|
|
blo "30000,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &49
|
|
)
|
|
*80 (Wire
|
|
uid 247,0
|
|
shape (OrthoPolyLine
|
|
uid 248,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "30000,15000,45250,15000"
|
|
pts [
|
|
"30000,15000"
|
|
"45250,15000"
|
|
]
|
|
)
|
|
start &13
|
|
end &64
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 249,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 250,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "30000,13600,33800,15000"
|
|
st "clock"
|
|
blo "30000,14800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &51
|
|
)
|
|
*81 (Wire
|
|
uid 251,0
|
|
shape (OrthoPolyLine
|
|
uid 252,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "64000,24000,70250,26000"
|
|
pts [
|
|
"64000,26000"
|
|
"67000,26000"
|
|
"67000,24000"
|
|
"70250,24000"
|
|
]
|
|
)
|
|
start &37
|
|
end &44
|
|
ss 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 253,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 254,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "64000,22600,72600,24000"
|
|
st "resetSynch"
|
|
blo "64000,23800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &50
|
|
)
|
|
*82 (Wire
|
|
uid 255,0
|
|
shape (OrthoPolyLine
|
|
uid 256,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "42000,32000,51000,34000"
|
|
pts [
|
|
"42000,34000"
|
|
"51000,34000"
|
|
"51000,32000"
|
|
]
|
|
)
|
|
start &21
|
|
end &29
|
|
ss 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 257,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 258,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43000,32600,47100,34000"
|
|
st "reset"
|
|
blo "43000,33800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &52
|
|
)
|
|
*83 (Wire
|
|
uid 335,0
|
|
shape (OrthoPolyLine
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end &87
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sat 32
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ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "-7500,1200,-7500,1200"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
portVis (PortSigDisplay
|
|
)
|
|
entityPath ""
|
|
archName ""
|
|
archPath ""
|
|
)
|
|
defaultVerilogComponent (VerilogComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "-1650,0,9650,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*111 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "-1150,3200,2950,4400"
|
|
st "Library"
|
|
blo "-1150,4200"
|
|
)
|
|
*112 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "-1150,4400,9150,5600"
|
|
st "VerilogComponent"
|
|
blo "-1150,5400"
|
|
)
|
|
*113 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "-1150,5600,1350,6800"
|
|
st "U_0"
|
|
blo "-1150,6600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "-8150,1200,-8150,1200"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,37120"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*114 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "2800,3800,5200,5000"
|
|
st "eb1"
|
|
blo "2800,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*115 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "2800,5000,4000,6200"
|
|
st "1"
|
|
blo "2800,6000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "0,0,1500,1500"
|
|
iconName "UnknownFile.png"
|
|
iconMaskName "UnknownFile.msk"
|
|
)
|
|
viewiconposition 0
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "-650,-600,650,600"
|
|
st "G"
|
|
blo "-650,400"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2900,1200"
|
|
st "sig0"
|
|
blo "0,1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,3800,1200"
|
|
st "dbus0"
|
|
blo "0,1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineColor "32768,0,0"
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,4700,1200"
|
|
st "bundle0"
|
|
blo "0,1000"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1200,1500,2400"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1300,18500,-100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1850,1650"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "250,250,1650,1450"
|
|
st "1"
|
|
blo "250,1250"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*116 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11200,20000,22000,21200"
|
|
st "Frame Declarations"
|
|
blo "11200,21000"
|
|
)
|
|
*117 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11200,21200,11200,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1300,11000,-100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1850,1650"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "250,250,1650,1450"
|
|
st "1"
|
|
blo "250,1250"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*118 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11200,20000,22000,21200"
|
|
st "Frame Declarations"
|
|
blo "11200,21000"
|
|
)
|
|
*119 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11200,21200,11200,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,8000,7400,9200"
|
|
st "Declarations"
|
|
blo "0,9000"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,9200,3700,10400"
|
|
st "Ports:"
|
|
blo "0,10200"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,14000,5200,15200"
|
|
st "Pre User:"
|
|
blo "0,15000"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,15200,24000,16000"
|
|
st "constant pipelineStageNb: positive := 5;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,16000,9500,17200"
|
|
st "Diagram Signals:"
|
|
blo "0,17000"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,8000,6400,9200"
|
|
st "Post User:"
|
|
blo "0,9000"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,8000,0,8000"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 12,0
|
|
usingSuid 1
|
|
emptyRow *120 (LEmptyRow
|
|
)
|
|
uid 54,0
|
|
optionalChildren [
|
|
*121 (RefLabelRowHdr
|
|
)
|
|
*122 (TitleRowHdr
|
|
)
|
|
*123 (FilterRowHdr
|
|
)
|
|
*124 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*125 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*126 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*127 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*128 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*129 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*130 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*131 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*132 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*133 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset_n"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 273,0
|
|
)
|
|
*134 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSynch"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 275,0
|
|
)
|
|
*135 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 277,0
|
|
)
|
|
*136 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
uid 279,0
|
|
)
|
|
*137 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "logic1"
|
|
t "std_uLogic"
|
|
o 6
|
|
suid 6,0
|
|
)
|
|
)
|
|
uid 283,0
|
|
)
|
|
*138 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "countOut"
|
|
t "unsigned"
|
|
b "(counterBitNb-1 downto 0)"
|
|
o 7
|
|
suid 7,0
|
|
)
|
|
)
|
|
uid 285,0
|
|
)
|
|
*139 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 4
|
|
decl (Decl
|
|
n "clk_sys"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 9,0
|
|
)
|
|
)
|
|
uid 372,0
|
|
)
|
|
*140 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 4
|
|
decl (Decl
|
|
n "logic0"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 374,0
|
|
)
|
|
*141 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSynch_n"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 12,0
|
|
)
|
|
)
|
|
uid 378,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 67,0
|
|
optionalChildren [
|
|
*142 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *143 (MRCItem
|
|
litem &120
|
|
pos 9
|
|
dimension 20
|
|
)
|
|
uid 69,0
|
|
optionalChildren [
|
|
*144 (MRCItem
|
|
litem &121
|
|
pos 0
|
|
dimension 20
|
|
uid 70,0
|
|
)
|
|
*145 (MRCItem
|
|
litem &122
|
|
pos 1
|
|
dimension 23
|
|
uid 71,0
|
|
)
|
|
*146 (MRCItem
|
|
litem &123
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 72,0
|
|
)
|
|
*147 (MRCItem
|
|
litem &133
|
|
pos 0
|
|
dimension 20
|
|
uid 274,0
|
|
)
|
|
*148 (MRCItem
|
|
litem &134
|
|
pos 1
|
|
dimension 20
|
|
uid 276,0
|
|
)
|
|
*149 (MRCItem
|
|
litem &135
|
|
pos 2
|
|
dimension 20
|
|
uid 278,0
|
|
)
|
|
*150 (MRCItem
|
|
litem &136
|
|
pos 3
|
|
dimension 20
|
|
uid 280,0
|
|
)
|
|
*151 (MRCItem
|
|
litem &137
|
|
pos 4
|
|
dimension 20
|
|
uid 284,0
|
|
)
|
|
*152 (MRCItem
|
|
litem &138
|
|
pos 5
|
|
dimension 20
|
|
uid 286,0
|
|
)
|
|
*153 (MRCItem
|
|
litem &139
|
|
pos 6
|
|
dimension 20
|
|
uid 373,0
|
|
)
|
|
*154 (MRCItem
|
|
litem &140
|
|
pos 7
|
|
dimension 20
|
|
uid 375,0
|
|
)
|
|
*155 (MRCItem
|
|
litem &141
|
|
pos 8
|
|
dimension 20
|
|
uid 379,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
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|
font "Tahoma,10,0"
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|
textAngle 90
|
|
)
|
|
uid 73,0
|
|
optionalChildren [
|
|
*156 (MRCItem
|
|
litem &124
|
|
pos 0
|
|
dimension 20
|
|
uid 74,0
|
|
)
|
|
*157 (MRCItem
|
|
litem &126
|
|
pos 1
|
|
dimension 50
|
|
uid 75,0
|
|
)
|
|
*158 (MRCItem
|
|
litem &127
|
|
pos 2
|
|
dimension 100
|
|
uid 76,0
|
|
)
|
|
*159 (MRCItem
|
|
litem &128
|
|
pos 3
|
|
dimension 50
|
|
uid 77,0
|
|
)
|
|
*160 (MRCItem
|
|
litem &129
|
|
pos 4
|
|
dimension 100
|
|
uid 78,0
|
|
)
|
|
*161 (MRCItem
|
|
litem &130
|
|
pos 5
|
|
dimension 100
|
|
uid 79,0
|
|
)
|
|
*162 (MRCItem
|
|
litem &131
|
|
pos 6
|
|
dimension 50
|
|
uid 80,0
|
|
)
|
|
*163 (MRCItem
|
|
litem &132
|
|
pos 7
|
|
dimension 80
|
|
uid 81,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 68,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 53,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *164 (LEmptyRow
|
|
)
|
|
uid 83,0
|
|
optionalChildren [
|
|
*165 (RefLabelRowHdr
|
|
)
|
|
*166 (TitleRowHdr
|
|
)
|
|
*167 (FilterRowHdr
|
|
)
|
|
*168 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*169 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*170 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*171 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*172 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*173 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*174 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*175 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*176 (LogGeneric
|
|
generic (GiElement
|
|
name "counterBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 469,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 95,0
|
|
optionalChildren [
|
|
*177 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *178 (MRCItem
|
|
litem &164
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 97,0
|
|
optionalChildren [
|
|
*179 (MRCItem
|
|
litem &165
|
|
pos 0
|
|
dimension 20
|
|
uid 98,0
|
|
)
|
|
*180 (MRCItem
|
|
litem &166
|
|
pos 1
|
|
dimension 23
|
|
uid 99,0
|
|
)
|
|
*181 (MRCItem
|
|
litem &167
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 100,0
|
|
)
|
|
*182 (MRCItem
|
|
litem &176
|
|
pos 0
|
|
dimension 20
|
|
uid 470,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 101,0
|
|
optionalChildren [
|
|
*183 (MRCItem
|
|
litem &168
|
|
pos 0
|
|
dimension 20
|
|
uid 102,0
|
|
)
|
|
*184 (MRCItem
|
|
litem &170
|
|
pos 1
|
|
dimension 50
|
|
uid 103,0
|
|
)
|
|
*185 (MRCItem
|
|
litem &171
|
|
pos 2
|
|
dimension 100
|
|
uid 104,0
|
|
)
|
|
*186 (MRCItem
|
|
litem &172
|
|
pos 3
|
|
dimension 100
|
|
uid 105,0
|
|
)
|
|
*187 (MRCItem
|
|
litem &173
|
|
pos 4
|
|
dimension 50
|
|
uid 106,0
|
|
)
|
|
*188 (MRCItem
|
|
litem &174
|
|
pos 5
|
|
dimension 50
|
|
uid 107,0
|
|
)
|
|
*189 (MRCItem
|
|
litem &175
|
|
pos 6
|
|
dimension 80
|
|
uid 108,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 96,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 82,0
|
|
type 1
|
|
)
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|
activeModelName "BlockDiag"
|
|
)
|