49 lines
1.7 KiB
VHDL
49 lines
1.7 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program IS distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License along with
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-- this program. If not, see <http://www.gnu.org/licenses/>
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--------------------------------------------------------------------------------
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-- EdgeDetector
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-- Detect rising and falling edges of a signal.
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--
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--------------------------------------------------------------------------------
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-- History:
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-- v0.1 : guo 2014-04-02 -- Initial version
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-- v1.0 : cof 2019-10-02 -- Updated symbol
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--------------------------------------------------------------------------------
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ARCHITECTURE RTL OF edgeDetector IS
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SIGNAL pulse_delayed : std_ulogic;
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SIGNAL rising_detected_s : std_ulogic;
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SIGNAL falling_detected_s : std_ulogic;
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BEGIN
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-- delay pulse
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reg : PROCESS (reset, clock)
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BEGIN
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IF reset = '1' THEN
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pulse_delayed <= '0';
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ELSIF rising_edge(clock) THEN
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pulse_delayed <= pulse;
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END IF;
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END PROCESS reg ;
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-- edge detection
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rising <= '1' when (pulse = '1') and (pulse_delayed = '0')
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else '0';
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falling <= '1' when (pulse = '0') and (pulse_delayed = '1')
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else '0';
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END ARCHITECTURE RTL;
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