1586 lines
40 KiB
VHDL
1586 lines
40 KiB
VHDL
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 17:45:49 01.05.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lissajousGenerator_circuit_EBS3 IS
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PORT(
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clock : IN std_ulogic;
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reset_N : IN std_ulogic;
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triggerOut : OUT std_ulogic;
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xOut : OUT std_ulogic;
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yOut : OUT std_ulogic
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);
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-- Declarations
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END lissajousGenerator_circuit_EBS3 ;
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-- VHDL Entity Board.DFF.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:07:05 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY DFF IS
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PORT(
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CLK : IN std_uLogic;
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CLR : IN std_uLogic;
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D : IN std_uLogic;
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Q : OUT std_uLogic
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);
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-- Declarations
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END DFF ;
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ARCHITECTURE sim OF DFF IS
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BEGIN
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process(clk, clr)
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begin
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if clr = '1' then
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q <= '0';
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elsif rising_edge(clk) then
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q <= d;
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end if;
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end process;
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END ARCHITECTURE sim;
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-- VHDL Entity Board.inverterIn.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:07:14 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY inverterIn IS
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PORT(
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in1 : IN std_uLogic;
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out1 : OUT std_uLogic
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);
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-- Declarations
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END inverterIn ;
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ARCHITECTURE sim OF inverterIn IS
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BEGIN
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out1 <= NOT in1;
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END ARCHITECTURE sim;
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-- VHDL Entity Lissajous.lissajousGenerator.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:07:53 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lissajousGenerator IS
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GENERIC(
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signalBitNb : positive := 16;
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phaseBitNb : positive := 16;
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stepX : positive := 1;
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stepY : positive := 1
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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triggerOut : OUT std_ulogic;
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xOut : OUT std_ulogic;
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yOut : OUT std_ulogic
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);
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-- Declarations
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END lissajousGenerator ;
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-- VHDL Entity DigitalToAnalogConverter.DAC.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:06:08 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY DAC IS
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GENERIC(
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signalBitNb : positive := 16
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);
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PORT(
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serialOut : OUT std_ulogic;
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parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
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clock : IN std_ulogic;
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reset : IN std_ulogic
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);
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-- Declarations
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END DAC ;
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ARCHITECTURE masterVersion OF DAC IS
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signal parallelIn1: unsigned(parallelIn'range);
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signal integrator: unsigned(parallelIn'high+1 downto 0);
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signal quantized: std_ulogic;
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BEGIN
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-- parallelIn1 <= parallelIn;
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parallelIn1 <= parallelIn/2 + 2**(parallelIn'length-2);
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integrate: process(reset, clock)
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begin
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if reset = '1' then
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integrator <= (others => '0');
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elsif rising_edge(clock) then
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if quantized = '0' then
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integrator <= integrator + parallelIn1;
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else
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integrator <= integrator + parallelIn1 - 2**parallelIn'length;
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end if;
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end if;
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end process integrate;
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quantized <= integrator(integrator'high);
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serialOut <= quantized;
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END ARCHITECTURE masterVersion;
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-- VHDL Entity SplineInterpolator.sineGen.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:40 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY sineGen IS
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GENERIC(
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signalBitNb : positive := 16;
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phaseBitNb : positive := 10
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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step : IN unsigned (phaseBitNb-1 DOWNTO 0);
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sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
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sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
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square : OUT unsigned (signalBitNb-1 DOWNTO 0);
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triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END sineGen ;
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-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:20 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorCoefficients IS
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GENERIC(
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bitNb : positive := 16;
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coeffBitNb : positive := 16
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);
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PORT(
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sample1 : IN signed (bitNb-1 DOWNTO 0);
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sample2 : IN signed (bitNb-1 DOWNTO 0);
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sample3 : IN signed (bitNb-1 DOWNTO 0);
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sample4 : IN signed (bitNb-1 DOWNTO 0);
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a : OUT signed (coeffBitNb-1 DOWNTO 0);
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b : OUT signed (coeffBitNb-1 DOWNTO 0);
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c : OUT signed (coeffBitNb-1 DOWNTO 0);
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d : OUT signed (coeffBitNb-1 DOWNTO 0);
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interpolateLinear : IN std_ulogic
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);
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-- Declarations
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END interpolatorCoefficients ;
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ARCHITECTURE masterVersion OF interpolatorCoefficients IS
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BEGIN
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calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4)
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begin
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if interpolateLinear = '1' then
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a <= (others => '0');
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b <= (others => '0');
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c <= resize(2*sample3, c'length)
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- resize(2*sample2, c'length);
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d <= resize( sample2, d'length);
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else
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a <= resize( sample4, a'length)
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- resize(3*sample3, a'length)
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+ resize(3*sample2, a'length)
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- resize( sample1, a'length);
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b <= resize(2*sample1, b'length)
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- resize(5*sample2, b'length)
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+ resize(4*sample3, b'length)
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- resize( sample4, b'length);
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c <= resize( sample3, c'length)
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- resize( sample1, c'length);
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d <= resize( sample2, d'length);
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end if;
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end process calcCoeffs;
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END ARCHITECTURE masterVersion;
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-- VHDL Entity WaveformGenerator.sawtoothGen.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 08:02:49 03/11/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY sawtoothGen IS
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GENERIC(
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bitNb : positive := 16
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);
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PORT(
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sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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step : IN unsigned (bitNb-1 DOWNTO 0);
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en : IN std_ulogic
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);
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-- Declarations
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END sawtoothGen ;
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ARCHITECTURE masterVersion OF sawtoothGen IS
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signal counter: unsigned(sawtooth'range);
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begin
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count: process(reset, clock)
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begin
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if reset = '1' then
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counter <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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counter <= counter + step;
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end if;
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end if;
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end process count;
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sawtooth <= counter;
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END ARCHITECTURE masterVersion;
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-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:24 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorShiftRegister IS
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GENERIC(
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signalBitNb : positive := 16
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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shiftSamples : IN std_ulogic;
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sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
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sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END interpolatorShiftRegister ;
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ARCHITECTURE masterVersion OF interpolatorShiftRegister IS
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-- signal sample4_int: signed(sampleIn'range);
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-- signal sample3_int: signed(sampleIn'range);
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-- signal sample2_int: signed(sampleIn'range);
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-- signal sample1_int: signed(sampleIn'range);
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type samplesArray is array(3 downto 0) of signed(sampleIn'range);
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signal samples: samplesArray;
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begin
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shiftThem: process(reset, clock)
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begin
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if reset = '1' then
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samples <= (others=>(others=>'0'));
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-- sample1_int <= (others => '0');
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-- sample2_int <= (others => '0');
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-- sample3_int <= (others => '0');
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-- sample4_int <= (others => '0');
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elsif rising_edge(clock) then
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if shiftSamples = '1' then
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-- sample1_int <= sample2_int;
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-- sample2_int <= sample3_int;
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-- sample3_int <= sample4_int;
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-- sample4_int <= sampleIn;
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samples(0) <= samples(1);
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samples(1) <= samples(2);
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samples(2) <= samples(3);
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samples(3) <= sampleIn;
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end if;
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end if;
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end process shiftThem;
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sample4 <= samples(3);
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sample3 <= samples(2);
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sample2 <= samples(1);
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sample1 <= samples(0);
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END ARCHITECTURE masterVersion;
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-- VHDL Entity SplineInterpolator.sineTable.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:46 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY sineTable IS
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GENERIC(
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inputBitNb : positive := 16;
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outputBitNb : positive := 16;
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tableAddressBitNb : positive := 3
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);
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PORT(
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sine : OUT signed (outputBitNb-1 DOWNTO 0);
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phase : IN unsigned (inputBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END sineTable ;
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ARCHITECTURE masterVersion OF sineTable IS
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signal changeSign : std_uLogic;
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signal flipPhase : std_uLogic;
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signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0);
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signal phaseTableAddress2 : unsigned(phaseTableAddress1'range);
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signal quarterSine : signed(sine'range);
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signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine
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begin
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changeSign <= phase(phase'high);
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flipPhase <= phase(phase'high-1);
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phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
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checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1)
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begin
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if (flipPhase xor shiftPhase) = '0' then
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phaseTableAddress2 <= phaseTableAddress1;
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else
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phaseTableAddress2 <= 0 - phaseTableAddress1;
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end if;
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end process checkPhase;
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quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase)
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begin
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case to_integer(phaseTableAddress2) is
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when 0 => if (flipPhase xor shiftPhase) = '0' then
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quarterSine <= to_signed(16#0000#, quarterSine'length);
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else
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quarterSine <= to_signed(16#7FFF#, quarterSine'length);
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end if;
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when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
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when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
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when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length);
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when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length);
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when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length);
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when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length);
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when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
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when others => quarterSine <= (others => '-');
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end case;
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end process quarterTable;
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checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine)
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begin
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if (changeSign xor (flipPhase and shiftPhase)) = '0' then
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sine <= quarterSine;
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else
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sine <= 0 - quarterSine;
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end if;
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end process checkSign;
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END ARCHITECTURE masterVersion;
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-- VHDL Entity SplineInterpolator.resizer.symbol
|
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--
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-- Created:
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-- by - francois.francois (Aphelia)
|
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-- at - 13:00:36 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
|
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
|
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ENTITY resizer IS
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GENERIC(
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inputBitNb : positive := 16;
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outputBitNb : positive := 16
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);
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PORT(
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resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
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resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END resizer ;
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ARCHITECTURE masterVersion OF resizer IS
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|
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BEGIN
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outGtIn: if resizeOut'length > resizeIn'length generate
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begin
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resizeOut <= shift_left(
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resize(
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resizeIn,
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resizeOut'length
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),
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resizeOut'length-resizeIn'length
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);
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end generate outGtIn;
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outEqIn: if resizeOut'length = resizeIn'length generate
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begin
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resizeOut <= resizeIn;
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end generate outEqIn;
|
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|
|
outLtIn: if resizeOut'length < resizeIn'length generate
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|
begin
|
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resizeOut <= resize(
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shift_right(
|
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resizeIn,
|
|
resizeIn'length-resizeOut'length
|
|
),
|
|
resizeOut'length
|
|
);
|
|
end generate outLtIn;
|
|
|
|
END ARCHITECTURE masterVersion;
|
|
|
|
|
|
|
|
|
|
|
|
-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol
|
|
--
|
|
-- Created:
|
|
-- by - francois.francois (Aphelia)
|
|
-- at - 13:00:14 02/19/19
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
ENTITY interpolatorCalculatePolynom IS
|
|
GENERIC(
|
|
signalBitNb : positive := 16;
|
|
coeffBitNb : positive := 16;
|
|
oversamplingBitNb : positive := 8
|
|
);
|
|
PORT(
|
|
clock : IN std_ulogic;
|
|
reset : IN std_ulogic;
|
|
restartPolynom : IN std_ulogic;
|
|
d : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
|
|
c : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
b : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
a : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
en : IN std_ulogic
|
|
);
|
|
|
|
-- Declarations
|
|
|
|
END interpolatorCalculatePolynom ;
|
|
|
|
|
|
|
|
|
|
|
|
ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS
|
|
|
|
constant additionalBitNb: positive := 1;
|
|
constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1
|
|
+ additionalBitNb;
|
|
signal x: signed(internalsBitNb-1 downto 0);
|
|
signal u: signed(internalsBitNb-1 downto 0);
|
|
signal v: signed(internalsBitNb-1 downto 0);
|
|
signal w: signed(internalsBitNb-1 downto 0);
|
|
|
|
BEGIN
|
|
|
|
iterativePolynom: process(reset, clock)
|
|
begin
|
|
if reset = '1' then
|
|
x <= (others => '0');
|
|
u <= (others => '0');
|
|
v <= (others => '0');
|
|
w <= (others => '0');
|
|
sampleOut <= (others => '0');
|
|
elsif rising_edge(clock) then
|
|
if en = '1' then
|
|
if restartPolynom = '1' then
|
|
x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb);
|
|
u <= resize(a, u'length)
|
|
+ shift_left(resize(b, u'length), oversamplingBitNb)
|
|
+ shift_left(resize(c, u'length), 2*oversamplingBitNb);
|
|
v <= resize(6*a, v'length)
|
|
+ shift_left(resize(2*b, v'length), oversamplingBitNb);
|
|
w <= resize(6*a, w'length);
|
|
sampleOut <= resize(d, sampleOut'length);
|
|
else
|
|
x <= x + u;
|
|
u <= u + v;
|
|
v <= v + w;
|
|
sampleOut <= resize(
|
|
shift_right(x, 3*oversamplingBitNb+1), sampleOut'length
|
|
);
|
|
-- limit overflow
|
|
if x(x'high downto x'high-additionalBitNb) = "01" then
|
|
sampleOut <= not shift_left(
|
|
resize("10", sampleOut'length), sampleOut'length-2
|
|
);
|
|
end if;
|
|
-- limit underflow
|
|
if x(x'high downto x'high-additionalBitNb) = "10" then
|
|
sampleOut <= shift_left(
|
|
resize("10", sampleOut'length), sampleOut'length-2
|
|
);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process iterativePolynom;
|
|
|
|
END ARCHITECTURE masterVersion;
|
|
|
|
|
|
|
|
|
|
-- VHDL Entity WaveformGenerator.sawtoothToSquare.symbol
|
|
--
|
|
-- Created:
|
|
-- by - francois.francois (Aphelia)
|
|
-- at - 08:02:49 03/11/19
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
ENTITY sawtoothToSquare IS
|
|
GENERIC(
|
|
bitNb : positive := 16
|
|
);
|
|
PORT(
|
|
square : OUT unsigned (bitNb-1 DOWNTO 0);
|
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
|
);
|
|
|
|
-- Declarations
|
|
|
|
END sawtoothToSquare ;
|
|
|
|
|
|
|
|
|
|
|
|
ARCHITECTURE masterVersion OF sawtoothToSquare IS
|
|
BEGIN
|
|
|
|
square <= (others => sawtooth(sawtooth'high));
|
|
|
|
END ARCHITECTURE masterVersion;
|
|
|
|
|
|
|
|
|
|
-- VHDL Entity WaveformGenerator.sawtoothToTriangle.symbol
|
|
--
|
|
-- Created:
|
|
-- by - francois.francois (Aphelia)
|
|
-- at - 08:02:49 03/11/19
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
ENTITY sawtoothToTriangle IS
|
|
GENERIC(
|
|
bitNb : positive := 16
|
|
);
|
|
PORT(
|
|
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
|
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
|
);
|
|
|
|
-- Declarations
|
|
|
|
END sawtoothToTriangle ;
|
|
|
|
|
|
|
|
|
|
|
|
ARCHITECTURE masterVersion OF sawtoothToTriangle IS
|
|
|
|
signal MSB: std_uLogic;
|
|
signal triangleInt: unsigned(triangle'range);
|
|
|
|
begin
|
|
|
|
MSB <= sawtooth(sawtooth'high);
|
|
|
|
foldDown: process(MSB, sawtooth)
|
|
begin
|
|
if MSB = '0' then
|
|
triangleInt <= sawtooth;
|
|
else
|
|
triangleInt <= not sawtooth;
|
|
end if;
|
|
end process foldDown;
|
|
|
|
triangle <= triangleInt(triangleInt'high-1 downto 0) & '0';
|
|
|
|
END ARCHITECTURE masterVersion;
|
|
|
|
|
|
|
|
|
|
-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol
|
|
--
|
|
-- Created:
|
|
-- by - francois.francois (Aphelia)
|
|
-- at - 13:00:28 02/19/19
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
ENTITY interpolatorTrigger IS
|
|
GENERIC(
|
|
counterBitNb : positive := 4
|
|
);
|
|
PORT(
|
|
triggerOut : OUT std_ulogic;
|
|
clock : IN std_ulogic;
|
|
reset : IN std_ulogic;
|
|
en : IN std_ulogic
|
|
);
|
|
|
|
-- Declarations
|
|
|
|
END interpolatorTrigger ;
|
|
|
|
|
|
|
|
|
|
|
|
ARCHITECTURE masterVersion OF interpolatorTrigger IS
|
|
|
|
signal triggerCounter: unsigned(counterBitNb-1 downto 0);
|
|
|
|
BEGIN
|
|
|
|
count: process(reset, clock)
|
|
begin
|
|
if reset = '1' then
|
|
triggerCounter <= (others => '0');
|
|
elsif rising_edge(clock) then
|
|
if en = '1' then
|
|
triggerCounter <= triggerCounter + 1;
|
|
end if;
|
|
end if;
|
|
end process count;
|
|
|
|
trig: process(triggerCounter, en)
|
|
begin
|
|
if triggerCounter = 0 then
|
|
triggerOut <= en;
|
|
else
|
|
triggerOut <= '0';
|
|
end if;
|
|
end process trig;
|
|
|
|
END ARCHITECTURE masterVersion;
|
|
|
|
|
|
|
|
|
|
-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol
|
|
--
|
|
-- Created:
|
|
-- by - francois.francois (Aphelia)
|
|
-- at - 13:00:32 02/19/19
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
ENTITY offsetToUnsigned IS
|
|
GENERIC(
|
|
bitNb : positive := 16
|
|
);
|
|
PORT(
|
|
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
|
signedIn : IN signed (bitNb-1 DOWNTO 0)
|
|
);
|
|
|
|
-- Declarations
|
|
|
|
END offsetToUnsigned ;
|
|
|
|
|
|
|
|
|
|
|
|
ARCHITECTURE masterVersion OF offsetToUnsigned IS
|
|
|
|
BEGIN
|
|
|
|
unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0));
|
|
|
|
END ARCHITECTURE masterVersion;
|
|
|
|
|
|
|
|
|
|
--
|
|
-- VHDL Architecture SplineInterpolator.sineGen.struct
|
|
--
|
|
-- Created:
|
|
-- by - axel.amand.UNKNOWN (WE7860)
|
|
-- at - 14:42:04 28.04.2023
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
LIBRARY SplineInterpolator;
|
|
LIBRARY WaveformGenerator;
|
|
|
|
ARCHITECTURE struct OF sineGen IS
|
|
|
|
-- Architecture declarations
|
|
constant tableAddressBitNb : positive := 3;
|
|
constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
|
|
constant coeffBitNb : positive := signalBitNb+4;
|
|
|
|
-- Internal signal declarations
|
|
SIGNAL a : signed(coeffBitNb-1 DOWNTO 0);
|
|
SIGNAL b : signed(coeffBitNb-1 DOWNTO 0);
|
|
SIGNAL c : signed(coeffBitNb-1 DOWNTO 0);
|
|
SIGNAL d : signed(coeffBitNb-1 DOWNTO 0);
|
|
SIGNAL logic0 : std_ulogic;
|
|
SIGNAL logic1 : std_ulogic;
|
|
SIGNAL newPolynom : std_ulogic;
|
|
SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0);
|
|
SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0);
|
|
|
|
-- Implicit buffer signal declarations
|
|
SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0);
|
|
|
|
|
|
-- Component Declarations
|
|
COMPONENT interpolatorCalculatePolynom
|
|
GENERIC (
|
|
signalBitNb : positive := 16;
|
|
coeffBitNb : positive := 16;
|
|
oversamplingBitNb : positive := 8
|
|
);
|
|
PORT (
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic ;
|
|
restartPolynom : IN std_ulogic ;
|
|
d : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
|
|
c : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
b : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
a : IN signed (coeffBitNb-1 DOWNTO 0);
|
|
en : IN std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT interpolatorCoefficients
|
|
GENERIC (
|
|
bitNb : positive := 16;
|
|
coeffBitNb : positive := 16
|
|
);
|
|
PORT (
|
|
sample1 : IN signed (bitNb-1 DOWNTO 0);
|
|
sample2 : IN signed (bitNb-1 DOWNTO 0);
|
|
sample3 : IN signed (bitNb-1 DOWNTO 0);
|
|
sample4 : IN signed (bitNb-1 DOWNTO 0);
|
|
a : OUT signed (coeffBitNb-1 DOWNTO 0);
|
|
b : OUT signed (coeffBitNb-1 DOWNTO 0);
|
|
c : OUT signed (coeffBitNb-1 DOWNTO 0);
|
|
d : OUT signed (coeffBitNb-1 DOWNTO 0);
|
|
interpolateLinear : IN std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT interpolatorShiftRegister
|
|
GENERIC (
|
|
signalBitNb : positive := 16
|
|
);
|
|
PORT (
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic ;
|
|
shiftSamples : IN std_ulogic ;
|
|
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
|
|
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
|
|
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
|
|
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
|
|
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT interpolatorTrigger
|
|
GENERIC (
|
|
counterBitNb : positive := 4
|
|
);
|
|
PORT (
|
|
triggerOut : OUT std_ulogic ;
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic ;
|
|
en : IN std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT offsetToUnsigned
|
|
GENERIC (
|
|
bitNb : positive := 16
|
|
);
|
|
PORT (
|
|
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
|
signedIn : IN signed (bitNb-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT resizer
|
|
GENERIC (
|
|
inputBitNb : positive := 16;
|
|
outputBitNb : positive := 16
|
|
);
|
|
PORT (
|
|
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
|
|
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT sineTable
|
|
GENERIC (
|
|
inputBitNb : positive := 16;
|
|
outputBitNb : positive := 16;
|
|
tableAddressBitNb : positive := 3
|
|
);
|
|
PORT (
|
|
sine : OUT signed (outputBitNb-1 DOWNTO 0);
|
|
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT sawtoothGen
|
|
GENERIC (
|
|
bitNb : positive := 16
|
|
);
|
|
PORT (
|
|
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic ;
|
|
step : IN unsigned (bitNb-1 DOWNTO 0);
|
|
en : IN std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT sawtoothToSquare
|
|
GENERIC (
|
|
bitNb : positive := 16
|
|
);
|
|
PORT (
|
|
square : OUT unsigned (bitNb-1 DOWNTO 0);
|
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT sawtoothToTriangle
|
|
GENERIC (
|
|
bitNb : positive := 16
|
|
);
|
|
PORT (
|
|
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
|
|
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
|
|
-- Optional embedded configurations
|
|
-- pragma synthesis_off
|
|
FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom;
|
|
FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients;
|
|
FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister;
|
|
FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger;
|
|
FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned;
|
|
FOR ALL : resizer USE ENTITY SplineInterpolator.resizer;
|
|
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
|
|
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
|
|
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
|
|
FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable;
|
|
-- pragma synthesis_on
|
|
|
|
|
|
BEGIN
|
|
-- Architecture concurrent statements
|
|
-- HDL Embedded Text Block 2 eb2
|
|
logic1 <= '1';
|
|
|
|
-- HDL Embedded Text Block 3 eb3
|
|
logic0 <= '0';
|
|
|
|
|
|
-- Instance port mappings.
|
|
I_spline : interpolatorCalculatePolynom
|
|
GENERIC MAP (
|
|
signalBitNb => signalBitNb,
|
|
coeffBitNb => coeffBitNb,
|
|
oversamplingBitNb => sampleCountBitNb
|
|
)
|
|
PORT MAP (
|
|
clock => clock,
|
|
reset => reset,
|
|
restartPolynom => newPolynom,
|
|
d => d,
|
|
sampleOut => sineSigned,
|
|
c => c,
|
|
b => b,
|
|
a => a,
|
|
en => logic1
|
|
);
|
|
I_coeffs : interpolatorCoefficients
|
|
GENERIC MAP (
|
|
bitNb => signalBitNb,
|
|
coeffBitNb => coeffBitNb
|
|
)
|
|
PORT MAP (
|
|
sample1 => sample1,
|
|
sample2 => sample2,
|
|
sample3 => sample3,
|
|
sample4 => sample4,
|
|
a => a,
|
|
b => b,
|
|
c => c,
|
|
d => d,
|
|
interpolateLinear => logic0
|
|
);
|
|
I_shReg : interpolatorShiftRegister
|
|
GENERIC MAP (
|
|
signalBitNb => signalBitNb
|
|
)
|
|
PORT MAP (
|
|
clock => clock,
|
|
reset => reset,
|
|
shiftSamples => newPolynom,
|
|
sampleIn => sineSamples,
|
|
sample1 => sample1,
|
|
sample2 => sample2,
|
|
sample3 => sample3,
|
|
sample4 => sample4
|
|
);
|
|
I_trig : interpolatorTrigger
|
|
GENERIC MAP (
|
|
counterBitNb => sampleCountBitNb
|
|
)
|
|
PORT MAP (
|
|
triggerOut => newPolynom,
|
|
clock => clock,
|
|
reset => reset,
|
|
en => logic1
|
|
);
|
|
I_unsigned : offsetToUnsigned
|
|
GENERIC MAP (
|
|
bitNb => signalBitNb
|
|
)
|
|
PORT MAP (
|
|
unsignedOut => sine,
|
|
signedIn => sineSigned
|
|
);
|
|
I_size : resizer
|
|
GENERIC MAP (
|
|
inputBitNb => phaseBitNb,
|
|
outputBitNb => signalBitNb
|
|
)
|
|
PORT MAP (
|
|
resizeOut => sawtooth_internal,
|
|
resizeIn => phase
|
|
);
|
|
I_sin : sineTable
|
|
GENERIC MAP (
|
|
inputBitNb => phaseBitNb,
|
|
outputBitNb => signalBitNb,
|
|
tableAddressBitNb => tableAddressBitNb
|
|
)
|
|
PORT MAP (
|
|
sine => sineSamples,
|
|
phase => phase
|
|
);
|
|
I_saw : sawtoothGen
|
|
GENERIC MAP (
|
|
bitNb => phaseBitNb
|
|
)
|
|
PORT MAP (
|
|
sawtooth => phase,
|
|
clock => clock,
|
|
reset => reset,
|
|
step => step,
|
|
en => logic1
|
|
);
|
|
I_square : sawtoothToSquare
|
|
GENERIC MAP (
|
|
bitNb => signalBitNb
|
|
)
|
|
PORT MAP (
|
|
square => square,
|
|
sawtooth => sawtooth_internal
|
|
);
|
|
I_tri : sawtoothToTriangle
|
|
GENERIC MAP (
|
|
bitNb => signalBitNb
|
|
)
|
|
PORT MAP (
|
|
triangle => triangle,
|
|
sawtooth => sawtooth_internal
|
|
);
|
|
|
|
-- Implicit buffered output assignments
|
|
sawtooth <= sawtooth_internal;
|
|
|
|
END struct;
|
|
|
|
|
|
|
|
|
|
--
|
|
-- VHDL Architecture Lissajous.lissajousGenerator.struct
|
|
--
|
|
-- Created:
|
|
-- by - axel.amand.UNKNOWN (WE7860)
|
|
-- at - 14:47:09 28.04.2023
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
LIBRARY DigitalToAnalogConverter;
|
|
LIBRARY SplineInterpolator;
|
|
|
|
ARCHITECTURE struct OF lissajousGenerator IS
|
|
|
|
-- Architecture declarations
|
|
|
|
-- Internal signal declarations
|
|
SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0);
|
|
SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
|
SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
|
|
|
|
|
-- Component Declarations
|
|
COMPONENT DAC
|
|
GENERIC (
|
|
signalBitNb : positive := 16
|
|
);
|
|
PORT (
|
|
serialOut : OUT std_ulogic ;
|
|
parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT sineGen
|
|
GENERIC (
|
|
signalBitNb : positive := 16;
|
|
phaseBitNb : positive := 10
|
|
);
|
|
PORT (
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic ;
|
|
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
|
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
|
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
|
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
|
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
|
);
|
|
END COMPONENT;
|
|
|
|
-- Optional embedded configurations
|
|
-- pragma synthesis_off
|
|
FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
|
|
FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
|
|
-- pragma synthesis_on
|
|
|
|
|
|
BEGIN
|
|
-- Architecture concurrent statements
|
|
-- HDL Embedded Text Block 1 eb1
|
|
triggerOut <= squareY(squareY'high);
|
|
|
|
-- HDL Embedded Text Block 2 eb2
|
|
stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length);
|
|
|
|
-- HDL Embedded Text Block 3 eb3
|
|
stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length);
|
|
|
|
|
|
-- Instance port mappings.
|
|
I_dacX : DAC
|
|
GENERIC MAP (
|
|
signalBitNb => signalBitNb
|
|
)
|
|
PORT MAP (
|
|
serialOut => xOut,
|
|
parallelIn => sineX,
|
|
clock => clock,
|
|
reset => reset
|
|
);
|
|
I_dacY : DAC
|
|
GENERIC MAP (
|
|
signalBitNb => signalBitNb
|
|
)
|
|
PORT MAP (
|
|
serialOut => yOut,
|
|
parallelIn => sineY,
|
|
clock => clock,
|
|
reset => reset
|
|
);
|
|
I_sinX : sineGen
|
|
GENERIC MAP (
|
|
signalBitNb => signalBitNb,
|
|
phaseBitNb => phaseBitNb
|
|
)
|
|
PORT MAP (
|
|
clock => clock,
|
|
reset => reset,
|
|
step => stepXUnsigned,
|
|
sawtooth => OPEN,
|
|
sine => sineX,
|
|
square => OPEN,
|
|
triangle => OPEN
|
|
);
|
|
I_sinY : sineGen
|
|
GENERIC MAP (
|
|
signalBitNb => signalBitNb,
|
|
phaseBitNb => phaseBitNb
|
|
)
|
|
PORT MAP (
|
|
clock => clock,
|
|
reset => reset,
|
|
step => stepYUnsigned,
|
|
sawtooth => OPEN,
|
|
sine => sineY,
|
|
square => squareY,
|
|
triangle => OPEN
|
|
);
|
|
|
|
END struct;
|
|
|
|
|
|
|
|
|
|
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
|
|
-- Module Version: 5.7
|
|
--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
|
|
|
|
-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
|
|
|
|
library IEEE;
|
|
use IEEE.std_logic_1164.all;
|
|
library ECP5U;
|
|
use ECP5U.components.all;
|
|
|
|
ENTITY pll IS
|
|
PORT(
|
|
clkIn100M : IN std_ulogic;
|
|
en75M : IN std_ulogic;
|
|
en50M : IN std_ulogic;
|
|
en10M : IN std_ulogic;
|
|
clk60MHz : OUT std_ulogic;
|
|
clk75MHz : OUT std_ulogic;
|
|
clk50MHz : OUT std_ulogic;
|
|
clk10MHz : OUT std_ulogic;
|
|
pllLocked : OUT std_ulogic
|
|
);
|
|
|
|
-- Declarations
|
|
|
|
END pll ;
|
|
|
|
architecture rtl of pll is
|
|
|
|
-- internal signal declarations
|
|
signal REFCLK: std_logic;
|
|
signal CLKOS3_t: std_logic;
|
|
signal CLKOS2_t: std_logic;
|
|
signal CLKOS_t: std_logic;
|
|
signal CLKOP_t: std_logic;
|
|
signal scuba_vhi: std_logic;
|
|
signal scuba_vlo: std_logic;
|
|
|
|
attribute FREQUENCY_PIN_CLKOS3 : string;
|
|
attribute FREQUENCY_PIN_CLKOS2 : string;
|
|
attribute FREQUENCY_PIN_CLKOS : string;
|
|
attribute FREQUENCY_PIN_CLKOP : string;
|
|
attribute FREQUENCY_PIN_CLKI : string;
|
|
attribute ICP_CURRENT : string;
|
|
attribute LPF_RESISTOR : string;
|
|
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
|
|
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
|
|
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
|
|
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
|
|
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
|
|
attribute ICP_CURRENT of PLLInst_0 : label is "5";
|
|
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
|
|
attribute syn_keep : boolean;
|
|
attribute NGD_DRC_MASK : integer;
|
|
attribute NGD_DRC_MASK of rtl : architecture is 1;
|
|
|
|
begin
|
|
-- component instantiation statements
|
|
scuba_vhi_inst: VHI
|
|
port map (Z=>scuba_vhi);
|
|
|
|
scuba_vlo_inst: VLO
|
|
port map (Z=>scuba_vlo);
|
|
|
|
PLLInst_0: EHXPLLL
|
|
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
|
|
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
|
|
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
|
|
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
|
|
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
|
|
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
|
|
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
|
|
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
|
|
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
|
|
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
|
|
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
|
|
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
|
|
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
|
|
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
|
|
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
|
|
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
|
|
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
|
|
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
|
|
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
|
|
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
|
|
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
|
|
|
|
clk10MHz <= CLKOS3_t;
|
|
clk50MHz <= CLKOS2_t;
|
|
clk75MHz <= CLKOS_t;
|
|
clk60MHz <= CLKOP_t;
|
|
end rtl;
|
|
|
|
|
|
|
|
|
|
--
|
|
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
|
|
--
|
|
-- Created:
|
|
-- by - axel.amand.UNKNOWN (WE7860)
|
|
-- at - 17:45:49 01.05.2023
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.all;
|
|
|
|
LIBRARY Board;
|
|
LIBRARY Lattice;
|
|
LIBRARY Lissajous;
|
|
|
|
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
|
|
|
|
-- Architecture declarations
|
|
constant signalBitNb: positive := 16;
|
|
constant phaseBitNb: positive := 17;
|
|
constant stepX: positive := 3;
|
|
constant stepY: positive := 4;
|
|
|
|
-- Internal signal declarations
|
|
SIGNAL clkSys : std_ulogic;
|
|
SIGNAL logic0 : std_ulogic;
|
|
SIGNAL logic1 : std_uLogic;
|
|
SIGNAL reset : std_ulogic;
|
|
SIGNAL resetSynch : std_ulogic;
|
|
SIGNAL resetSynch_N : std_ulogic;
|
|
|
|
|
|
-- Component Declarations
|
|
COMPONENT DFF
|
|
PORT (
|
|
CLK : IN std_uLogic ;
|
|
CLR : IN std_uLogic ;
|
|
D : IN std_uLogic ;
|
|
Q : OUT std_uLogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT inverterIn
|
|
PORT (
|
|
in1 : IN std_uLogic ;
|
|
out1 : OUT std_uLogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT pll
|
|
PORT (
|
|
clkIn100M : IN std_ulogic ;
|
|
en75M : IN std_ulogic ;
|
|
en50M : IN std_ulogic ;
|
|
en10M : IN std_ulogic ;
|
|
clk60MHz : OUT std_ulogic ;
|
|
clk75MHz : OUT std_ulogic ;
|
|
clk50MHz : OUT std_ulogic ;
|
|
clk10MHz : OUT std_ulogic ;
|
|
pllLocked : OUT std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
COMPONENT lissajousGenerator
|
|
GENERIC (
|
|
signalBitNb : positive := 16;
|
|
phaseBitNb : positive := 16;
|
|
stepX : positive := 1;
|
|
stepY : positive := 1
|
|
);
|
|
PORT (
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic ;
|
|
triggerOut : OUT std_ulogic ;
|
|
xOut : OUT std_ulogic ;
|
|
yOut : OUT std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
|
|
-- Optional embedded configurations
|
|
-- pragma synthesis_off
|
|
FOR ALL : DFF USE ENTITY Board.DFF;
|
|
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
|
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
|
|
FOR ALL : pll USE ENTITY Lattice.pll;
|
|
-- pragma synthesis_on
|
|
|
|
|
|
BEGIN
|
|
-- Architecture concurrent statements
|
|
-- HDL Embedded Text Block 5 eb5
|
|
logic1 <= '1';
|
|
|
|
-- HDL Embedded Text Block 6 eb6
|
|
logic0 <= '0';
|
|
|
|
|
|
-- Instance port mappings.
|
|
I_dff : DFF
|
|
PORT MAP (
|
|
CLK => clock,
|
|
CLR => reset,
|
|
D => logic1,
|
|
Q => resetSynch_N
|
|
);
|
|
I_inv1 : inverterIn
|
|
PORT MAP (
|
|
in1 => reset_N,
|
|
out1 => reset
|
|
);
|
|
I_inv2 : inverterIn
|
|
PORT MAP (
|
|
in1 => resetSynch_N,
|
|
out1 => resetSynch
|
|
);
|
|
U_pll : pll
|
|
PORT MAP (
|
|
clkIn100M => clock,
|
|
en75M => logic0,
|
|
en50M => logic0,
|
|
en10M => logic0,
|
|
clk60MHz => clkSys,
|
|
clk75MHz => OPEN,
|
|
clk50MHz => OPEN,
|
|
clk10MHz => OPEN,
|
|
pllLocked => OPEN
|
|
);
|
|
I_main : lissajousGenerator
|
|
GENERIC MAP (
|
|
signalBitNb => signalBitNb,
|
|
phaseBitNb => phaseBitNb,
|
|
stepX => stepX,
|
|
stepY => stepY
|
|
)
|
|
PORT MAP (
|
|
clock => clkSys,
|
|
reset => resetSynch,
|
|
triggerOut => triggerOut,
|
|
xOut => xOut,
|
|
yOut => yOut
|
|
);
|
|
|
|
END masterVersion;
|
|
|
|
|
|
|
|
|