17 lines
427 B
VHDL
17 lines
427 B
VHDL
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ARCHITECTURE rtl OF mux4To1ULogVec IS
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BEGIN
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muxSelect: process(sel, in1, in2, in3, in4)
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begin
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case to_integer(unsigned(sel)) is
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when 0 => out1 <= in1 after g_tMux;
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when 1 => out1 <= in2 after g_tMux;
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when 2 => out1 <= in3 after g_tMux;
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when 3 => out1 <= in4 after g_tMux;
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when others => out1 <= (others => 'X') after g_tMux;
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end case;
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end process muxSelect;
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END ARCHITECTURE rtl;
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