3942 lines
48 KiB
Plaintext
3942 lines
48 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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itemName "ALL"
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)
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]
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instances [
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(Instance
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name "I_tester"
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duLibraryName "Lissajous_test"
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duName "lissajousGenerator_tester"
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elements [
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(GiElement
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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(GiElement
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name "clockFrequency"
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value "clockFrequency"
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mwi 0
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uid 421,0
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)
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(Instance
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name "I_DUT"
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duLibraryName "Lissajous"
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duName "lissajousGenerator"
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elements [
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(GiElement
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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)
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(GiElement
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name "phaseBitNb"
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type "positive"
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value "phaseBitNb"
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)
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(GiElement
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name "stepX"
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value "stepX"
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(GiElement
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name "stepY"
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value "stepY"
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mwi 0
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uid 1594,0
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(Instance
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name "I_filtX"
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duLibraryName "WaveformGenerator"
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duName "lowpass"
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elements [
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(GiElement
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name "signalBitNb"
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embeddedInstances [
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name "eb1"
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number "1"
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]
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libraryRefs [
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"ieee"
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
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value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds"
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)
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(vvPair
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variable "appl"
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value "HDL Designer"
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)
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(vvPair
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variable "arch_name"
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value "struct"
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(vvPair
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variable "asm_file"
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value "beamer.asm"
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(vvPair
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variable "concat_file"
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value "concatenated"
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(vvPair
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variable "config"
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value "%(unit)_%(view)_config"
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(vvPair
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variable "d"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test"
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)
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(vvPair
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variable "d_logical"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_test"
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)
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(vvPair
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variable "date"
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value "28.04.2023"
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(vvPair
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variable "day"
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value "ven."
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)
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(vvPair
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variable "day_long"
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value "vendredi"
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)
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(vvPair
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variable "dd"
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value "28"
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)
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(vvPair
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variable "designName"
|
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value "$DESIGN_NAME"
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)
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(vvPair
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variable "entity_name"
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value "lissajousGenerator_test"
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)
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(vvPair
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variable "ext"
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value "<TBD>"
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)
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(vvPair
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variable "f"
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value "struct.bd"
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)
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(vvPair
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variable "f_logical"
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value "struct.bd"
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)
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(vvPair
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variable "f_noext"
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value "struct"
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)
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(vvPair
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variable "graphical_source_author"
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value "axel.amand"
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)
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(vvPair
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variable "graphical_source_date"
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value "28.04.2023"
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)
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(vvPair
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variable "graphical_source_group"
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value "UNKNOWN"
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)
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(vvPair
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variable "graphical_source_host"
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value "WE7860"
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)
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(vvPair
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variable "graphical_source_time"
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value "14:48:46"
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)
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(vvPair
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variable "group"
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value "UNKNOWN"
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)
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(vvPair
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|
variable "host"
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value "WE7860"
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)
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(vvPair
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variable "language"
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value "VHDL"
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)
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(vvPair
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variable "library"
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value "Lissajous_test"
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)
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(vvPair
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variable "library_downstream_Concatenation"
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value "$HDS_PROJECT_DIR/../Lissajous_test/concat"
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)
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(vvPair
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variable "library_downstream_ModelSim"
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value "D:\\Users\\ELN_labs\\VHDL_comp"
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)
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(vvPair
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variable "library_downstream_ModelSimCompiler"
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value "$SCRATCH_DIR/Lissajous_test"
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)
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(vvPair
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variable "mm"
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|
value "04"
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)
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|
(vvPair
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variable "module_name"
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|
value "lissajousGenerator_test"
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)
|
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(vvPair
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|
variable "month"
|
|
value "avr."
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)
|
|
(vvPair
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|
variable "month_long"
|
|
value "avril"
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)
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|
(vvPair
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|
variable "p"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajous@generator_test\\struct.bd"
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)
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(vvPair
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variable "p_logical"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Lissajous_test\\hds\\lissajousGenerator_test\\struct.bd"
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)
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(vvPair
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variable "package_name"
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value "<Undefined Variable>"
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)
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(vvPair
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variable "project_name"
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value "hds"
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)
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(vvPair
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variable "series"
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value "HDL Designer Series"
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)
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(vvPair
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variable "task_ADMS"
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value "<TBD>"
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)
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(vvPair
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variable "task_AsmPath"
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value "$HEI_LIBS_DIR/NanoBlaze/hdl"
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)
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(vvPair
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variable "task_DesignCompilerPath"
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value "<TBD>"
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)
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(vvPair
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variable "task_HDSPath"
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value "$HDS_HOME"
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)
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(vvPair
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variable "task_ISEBinPath"
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value "$ISE_HOME"
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)
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(vvPair
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variable "task_ISEPath"
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value "$ISE_WORK_DIR"
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(vvPair
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variable "task_LeonardoPath"
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value "<TBD>"
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(vvPair
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variable "task_ModelSimPath"
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value "$MODELSIM_HOME/modeltech/bin"
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(vvPair
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variable "task_NC"
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value "<TBD>"
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(vvPair
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variable "task_PrecisionRTLPath"
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value "<TBD>"
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(vvPair
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variable "task_QuestaSimPath"
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value "<TBD>"
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(vvPair
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variable "task_VCSPath"
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value "<TBD>"
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(vvPair
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variable "this_ext"
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value "bd"
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variable "this_file"
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value "struct"
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(vvPair
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variable "this_file_logical"
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value "struct"
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(vvPair
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variable "time"
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value "14:48:46"
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variable "unit"
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value "lissajousGenerator_test"
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variable "user"
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value "axel.amand"
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variable "version"
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value "2019.2 (Build 5)"
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variable "view"
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value "struct"
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text (MLText
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)
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st "
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tm "CommentText"
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text (MLText
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bg "0,0,32768"
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)
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st "
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tm "CommentText"
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ignorePrefs 1
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oxt "14000,66000,55000,71000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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blo "11700,61200"
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tm "BdLibraryNameMgr"
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uid 425,0
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va (VaSet
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blo "11700,62400"
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tm "BlkNameMgr"
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va (VaSet
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tm "InstanceNameMgr"
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
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text (MLText
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uid 429,0
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va (VaSet
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(GiElement
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declText (MLText
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uid 1555,0
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va (VaSet
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uid 1562,0
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declText (MLText
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va (VaSet
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font "Verdana,8,0"
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uid 1594,0
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optionalChildren [
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uid 1574,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1575,0
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ro 90
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va (VaSet
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vasetType 1
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)
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tg (CPTG
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uid 1576,0
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stg "VerticalLayoutStrategy"
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uid 1577,0
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va (VaSet
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)
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st "clock"
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blo "24000,40400"
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "clock"
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t "std_ulogic"
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suid 1,0
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)
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)
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)
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*20 (CptPort
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uid 1578,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1579,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
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uid 1580,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 1581,0
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va (VaSet
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)
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st "triggerOut"
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ju 2
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blo "38000,40400"
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)
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)
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thePort (LogicalPort
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m 1
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decl (Decl
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n "triggerOut"
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t "std_ulogic"
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suid 3,0
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)
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)
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)
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*21 (CptPort
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uid 1582,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1583,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
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uid 1584,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 1585,0
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va (VaSet
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)
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st "xOut"
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ju 2
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blo "38000,38400"
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)
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)
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thePort (LogicalPort
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m 1
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decl (Decl
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n "xOut"
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t "std_ulogic"
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o 4
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suid 4,0
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)
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)
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)
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*22 (CptPort
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uid 1586,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1587,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "39000,35625,39750,36375"
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)
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tg (CPTG
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uid 1588,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 1589,0
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va (VaSet
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)
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xt "34800,35400,38000,36600"
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st "yOut"
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ju 2
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|
blo "38000,36400"
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)
|
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)
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thePort (LogicalPort
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m 1
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decl (Decl
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n "yOut"
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t "std_ulogic"
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|
o 5
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suid 5,0
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)
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)
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)
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*23 (CptPort
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uid 1590,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 1591,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "22250,41625,23000,42375"
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)
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tg (CPTG
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uid 1592,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 1593,0
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va (VaSet
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)
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st "reset"
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blo "24000,42500"
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "reset"
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t "std_ulogic"
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o 2
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suid 2006,0
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)
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)
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shape (Rectangle
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uid 1595,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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bg "0,65535,0"
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)
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)
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ttg (MlTextGroup
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uid 1596,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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uid 1597,0
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va (VaSet
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)
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st "Lissajous"
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tm "BdLibraryNameMgr"
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)
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uid 1598,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "23600,44700,34100,45900"
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st "lissajousGenerator"
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blo "23600,45700"
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tm "CptNameMgr"
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)
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uid 1599,0
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va (VaSet
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font "Verdana,9,1"
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)
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xt "23600,45600,27300,46800"
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st "I_DUT"
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blo "23600,46600"
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tm "InstanceNameMgr"
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)
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ga (GenericAssociation
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uid 1600,0
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ps "EdgeToEdgeStrategy"
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matrix (Matrix
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uid 1601,0
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text (MLText
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uid 1602,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "23000,47600,42200,51600"
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st "signalBitNb = signalBitNb ( positive )
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phaseBitNb = phaseBitNb ( positive )
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)
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header ""
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)
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elements [
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value "signalBitNb"
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(GiElement
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name "phaseBitNb"
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type "positive"
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(GiElement
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)
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(GiElement
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name "stepY"
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type "positive"
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value "stepY"
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)
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]
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)
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connectByName 1
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portVis (PortSigDisplay
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|
sTC 0
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)
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archFileType "UNKNOWN"
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)
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uid 1603,0
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optionalChildren [
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*28 (EmbeddedText
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uid 1608,0
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commentText (CommentText
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uid 1609,0
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ps "CenterOffsetStrategy"
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shape (Rectangle
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uid 1610,0
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va (VaSet
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vasetType 1
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fg "65535,65535,65535"
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lineStyle 2
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)
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xt "43000,3000,59000,7000"
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)
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oxt "0,0,18000,5000"
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text (MLText
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uid 1611,0
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va (VaSet
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)
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xt "43200,3200,57300,6800"
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st "
|
|
xParallel <= (others => xSerial);
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yParallel <= (others => ySerial);
|
|
|
|
"
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|
tm "HdlTextMgr"
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|
wrapOption 3
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visibleHeight 4000
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|
visibleWidth 16000
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)
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)
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)
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shape (Rectangle
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uid 1604,0
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va (VaSet
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vasetType 1
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fg "65535,65535,32768"
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)
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)
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|
oxt "0,0,8000,10000"
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ttg (MlTextGroup
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uid 1605,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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uid 1606,0
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va (VaSet
|
|
)
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|
xt "43400,8000,46000,9200"
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|
st "eb1"
|
|
blo "43400,9000"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*30 (Text
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uid 1607,0
|
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va (VaSet
|
|
)
|
|
xt "43400,9000,44800,10200"
|
|
st "1"
|
|
blo "43400,10000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
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]
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)
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*31 (SaComponent
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|
uid 1612,0
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optionalChildren [
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*32 (CptPort
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uid 1621,0
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ps "OnEdgeStrategy"
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|
shape (Triangle
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uid 1622,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62250,39625,63000,40375"
|
|
)
|
|
tg (CPTG
|
|
uid 1623,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1624,0
|
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va (VaSet
|
|
)
|
|
xt "64000,39400,67400,40600"
|
|
st "clock"
|
|
blo "64000,40400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
)
|
|
)
|
|
)
|
|
*33 (CptPort
|
|
uid 1625,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
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uid 1626,0
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|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "79000,35625,79750,36375"
|
|
)
|
|
tg (CPTG
|
|
uid 1627,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1628,0
|
|
va (VaSet
|
|
)
|
|
xt "70700,35400,78000,36600"
|
|
st "lowpassOut"
|
|
ju 2
|
|
blo "78000,36400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "lowpassOut"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
)
|
|
)
|
|
)
|
|
*34 (CptPort
|
|
uid 1629,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1630,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62250,41625,63000,42375"
|
|
)
|
|
tg (CPTG
|
|
uid 1631,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1632,0
|
|
va (VaSet
|
|
)
|
|
xt "64000,41400,67300,42600"
|
|
st "reset"
|
|
blo "64000,42400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
)
|
|
)
|
|
)
|
|
*35 (CptPort
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|
uid 1633,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1634,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62250,35625,63000,36375"
|
|
)
|
|
tg (CPTG
|
|
uid 1635,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1636,0
|
|
va (VaSet
|
|
)
|
|
xt "64000,35400,69800,36600"
|
|
st "lowpassIn"
|
|
blo "64000,36400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "lowpassIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1613,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "63000,32000,79000,44000"
|
|
)
|
|
oxt "32000,10000,48000,22000"
|
|
ttg (MlTextGroup
|
|
uid 1614,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*36 (Text
|
|
uid 1615,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "63600,43800,75100,45000"
|
|
st "WaveformGenerator"
|
|
blo "63600,44800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*37 (Text
|
|
uid 1616,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "63600,44700,68200,45900"
|
|
st "lowpass"
|
|
blo "63600,45700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*38 (Text
|
|
uid 1617,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "63600,45600,67600,46800"
|
|
st "I_filtX"
|
|
blo "63600,46600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1618,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1619,0
|
|
text (MLText
|
|
uid 1620,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "63000,47600,83800,49600"
|
|
st "signalBitNb = signalBitNb ( positive )
|
|
shiftBitNb = lowpassShiftBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
(GiElement
|
|
name "shiftBitNb"
|
|
type "positive"
|
|
value "lowpassShiftBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*39 (Net
|
|
uid 1683,0
|
|
decl (Decl
|
|
n "ySerial"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 15,0
|
|
)
|
|
declText (MLText
|
|
uid 1684,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,24400,15300,25400"
|
|
st "SIGNAL ySerial : std_ulogic"
|
|
)
|
|
)
|
|
*40 (Net
|
|
uid 1693,0
|
|
decl (Decl
|
|
n "xSerial"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 17,0
|
|
)
|
|
declText (MLText
|
|
uid 1694,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,21400,15300,22400"
|
|
st "SIGNAL xSerial : std_ulogic"
|
|
)
|
|
)
|
|
*41 (Net
|
|
uid 1695,0
|
|
decl (Decl
|
|
n "xLowapss"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 18,0
|
|
)
|
|
declText (MLText
|
|
uid 1696,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,19400,27200,20400"
|
|
st "SIGNAL xLowapss : unsigned(signalBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*42 (Net
|
|
uid 1697,0
|
|
decl (Decl
|
|
n "xParallel"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 19,0
|
|
)
|
|
declText (MLText
|
|
uid 1698,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,20400,26400,21400"
|
|
st "SIGNAL xParallel : unsigned(signalBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*43 (SaComponent
|
|
uid 1699,0
|
|
optionalChildren [
|
|
*44 (CptPort
|
|
uid 1708,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1709,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62250,19625,63000,20375"
|
|
)
|
|
tg (CPTG
|
|
uid 1710,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1711,0
|
|
va (VaSet
|
|
)
|
|
xt "64000,19400,67400,20600"
|
|
st "clock"
|
|
blo "64000,20400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
)
|
|
)
|
|
)
|
|
*45 (CptPort
|
|
uid 1712,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1713,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "79000,15625,79750,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 1714,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1715,0
|
|
va (VaSet
|
|
)
|
|
xt "70700,15400,78000,16600"
|
|
st "lowpassOut"
|
|
ju 2
|
|
blo "78000,16400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "lowpassOut"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 1
|
|
)
|
|
)
|
|
)
|
|
*46 (CptPort
|
|
uid 1716,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1717,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62250,21625,63000,22375"
|
|
)
|
|
tg (CPTG
|
|
uid 1718,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1719,0
|
|
va (VaSet
|
|
)
|
|
xt "64000,21400,67300,22600"
|
|
st "reset"
|
|
blo "64000,22400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
)
|
|
)
|
|
)
|
|
*47 (CptPort
|
|
uid 1720,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 1721,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "62250,15625,63000,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 1722,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 1723,0
|
|
va (VaSet
|
|
)
|
|
xt "64000,15400,69800,16600"
|
|
st "lowpassIn"
|
|
blo "64000,16400"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "lowpassIn"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 1700,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "63000,12000,79000,24000"
|
|
)
|
|
oxt "32000,10000,48000,22000"
|
|
ttg (MlTextGroup
|
|
uid 1701,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*48 (Text
|
|
uid 1702,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "63600,23800,75100,25000"
|
|
st "WaveformGenerator"
|
|
blo "63600,24800"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*49 (Text
|
|
uid 1703,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "63600,24700,68200,25900"
|
|
st "lowpass"
|
|
blo "63600,25700"
|
|
tm "CptNameMgr"
|
|
)
|
|
*50 (Text
|
|
uid 1704,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "63600,25600,67500,26800"
|
|
st "I_filty"
|
|
blo "63600,26600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
uid 1705,0
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
uid 1706,0
|
|
text (MLText
|
|
uid 1707,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "63000,27600,83800,29600"
|
|
st "signalBitNb = signalBitNb ( positive )
|
|
shiftBitNb = lowpassShiftBitNb ( positive ) "
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "signalBitNb"
|
|
)
|
|
(GiElement
|
|
name "shiftBitNb"
|
|
type "positive"
|
|
value "lowpassShiftBitNb"
|
|
)
|
|
]
|
|
)
|
|
ordering 1
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
*51 (Net
|
|
uid 1744,0
|
|
decl (Decl
|
|
n "yLowpass"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 21,0
|
|
)
|
|
declText (MLText
|
|
uid 1745,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,22400,27200,23400"
|
|
st "SIGNAL yLowpass : unsigned(signalBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*52 (Net
|
|
uid 1762,0
|
|
decl (Decl
|
|
n "yParallel"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 23,0
|
|
)
|
|
declText (MLText
|
|
uid 1763,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,23400,26400,24400"
|
|
st "SIGNAL yParallel : unsigned(signalBitNb-1 DOWNTO 0)"
|
|
)
|
|
)
|
|
*53 (Net
|
|
uid 1827,0
|
|
decl (Decl
|
|
n "triggerOut"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 24,0
|
|
)
|
|
declText (MLText
|
|
uid 1828,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,18400,15700,19400"
|
|
st "SIGNAL triggerOut : std_ulogic"
|
|
)
|
|
)
|
|
*54 (Wire
|
|
uid 1556,0
|
|
shape (OrthoPolyLine
|
|
uid 1557,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "21000,42000,22250,52000"
|
|
pts [
|
|
"22250,42000"
|
|
"21000,42000"
|
|
"21000,52000"
|
|
]
|
|
)
|
|
start &23
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1560,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1561,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "17250,40700,21350,42100"
|
|
st "reset"
|
|
blo "17250,41900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*55 (Wire
|
|
uid 1564,0
|
|
shape (OrthoPolyLine
|
|
uid 1565,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "19000,40000,22250,52000"
|
|
pts [
|
|
"22250,40000"
|
|
"19000,40000"
|
|
"19000,52000"
|
|
]
|
|
)
|
|
start &19
|
|
end &12
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1568,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1569,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "17250,38700,21050,40100"
|
|
st "clock"
|
|
blo "17250,39900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*56 (Wire
|
|
uid 1637,0
|
|
optionalChildren [
|
|
*57 (BdJunction
|
|
uid 1645,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
uid 1646,0
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "46600,35600,47400,36400"
|
|
radius 400
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 1638,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "39750,36000,47000,52000"
|
|
pts [
|
|
"39750,36000"
|
|
"47000,36000"
|
|
"47000,52000"
|
|
]
|
|
)
|
|
start &22
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1643,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1644,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "41000,34600,46000,36000"
|
|
st "ySerial"
|
|
blo "41000,35800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &39
|
|
)
|
|
*58 (Wire
|
|
uid 1647,0
|
|
shape (OrthoPolyLine
|
|
uid 1648,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "47000,8000,47000,36000"
|
|
pts [
|
|
"47000,36000"
|
|
"47000,8000"
|
|
]
|
|
)
|
|
start &57
|
|
end &27
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1651,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1652,0
|
|
ro 270
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "45600,31500,47000,36500"
|
|
st "ySerial"
|
|
blo "46800,36500"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &39
|
|
)
|
|
*59 (Wire
|
|
uid 1653,0
|
|
shape (OrthoPolyLine
|
|
uid 1654,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "59000,42000,62250,42000"
|
|
pts [
|
|
"59000,42000"
|
|
"62250,42000"
|
|
]
|
|
)
|
|
end &34
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1657,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1658,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "59000,40600,63100,42000"
|
|
st "reset"
|
|
blo "59000,41800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*60 (Wire
|
|
uid 1659,0
|
|
shape (OrthoPolyLine
|
|
uid 1660,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "59000,40000,62250,40000"
|
|
pts [
|
|
"59000,40000"
|
|
"62250,40000"
|
|
]
|
|
)
|
|
end &32
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1663,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1664,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "59000,38600,62800,40000"
|
|
st "clock"
|
|
blo "59000,39800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*61 (Wire
|
|
uid 1665,0
|
|
shape (OrthoPolyLine
|
|
uid 1666,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "79750,36000,83000,52000"
|
|
pts [
|
|
"79750,36000"
|
|
"83000,36000"
|
|
"83000,52000"
|
|
]
|
|
)
|
|
start &33
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1669,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1670,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "81750,34600,88850,36000"
|
|
st "xLowapss"
|
|
blo "81750,35800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &41
|
|
)
|
|
*62 (Wire
|
|
uid 1671,0
|
|
shape (OrthoPolyLine
|
|
uid 1672,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "55000,8000,62250,36000"
|
|
pts [
|
|
"62250,36000"
|
|
"55000,36000"
|
|
"55000,8000"
|
|
]
|
|
)
|
|
start &35
|
|
end &27
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1675,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1676,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "56000,34600,62100,36000"
|
|
st "xParallel"
|
|
blo "56000,35800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &42
|
|
)
|
|
*63 (Wire
|
|
uid 1687,0
|
|
optionalChildren [
|
|
*64 (BdJunction
|
|
uid 1752,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
uid 1753,0
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "44600,37600,45400,38400"
|
|
radius 400
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 1688,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "39750,38000,45000,52000"
|
|
pts [
|
|
"39750,38000"
|
|
"45000,38000"
|
|
"45000,52000"
|
|
]
|
|
)
|
|
start &21
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1691,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1692,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "41000,36700,46000,38100"
|
|
st "xSerial"
|
|
blo "41000,37900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &40
|
|
)
|
|
*65 (Wire
|
|
uid 1724,0
|
|
shape (OrthoPolyLine
|
|
uid 1725,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "59000,20000,62250,20000"
|
|
pts [
|
|
"59000,20000"
|
|
"62250,20000"
|
|
]
|
|
)
|
|
end &44
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1728,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1729,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "59000,18600,62800,20000"
|
|
st "clock"
|
|
blo "59000,19800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &17
|
|
)
|
|
*66 (Wire
|
|
uid 1730,0
|
|
shape (OrthoPolyLine
|
|
uid 1731,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "59000,22000,62250,22000"
|
|
pts [
|
|
"59000,22000"
|
|
"62250,22000"
|
|
]
|
|
)
|
|
end &46
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1734,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1735,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "59000,20600,63100,22000"
|
|
st "reset"
|
|
blo "59000,21800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &16
|
|
)
|
|
*67 (Wire
|
|
uid 1738,0
|
|
shape (OrthoPolyLine
|
|
uid 1739,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "79750,16000,85000,52000"
|
|
pts [
|
|
"79750,16000"
|
|
"85000,16000"
|
|
"85000,52000"
|
|
]
|
|
)
|
|
start &45
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1742,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1743,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "81750,14700,88850,16100"
|
|
st "yLowpass"
|
|
blo "81750,15900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &51
|
|
)
|
|
*68 (Wire
|
|
uid 1746,0
|
|
shape (OrthoPolyLine
|
|
uid 1747,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "45000,8000,45000,38000"
|
|
pts [
|
|
"45000,38000"
|
|
"45000,8000"
|
|
]
|
|
)
|
|
start &64
|
|
end &27
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1750,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1751,0
|
|
ro 270
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "43700,9900,45100,14900"
|
|
st "xSerial"
|
|
blo "44900,14900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &40
|
|
)
|
|
*69 (Wire
|
|
uid 1756,0
|
|
shape (OrthoPolyLine
|
|
uid 1757,0
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
xt "57000,8000,62250,16000"
|
|
pts [
|
|
"62250,16000"
|
|
"57000,16000"
|
|
"57000,8000"
|
|
]
|
|
)
|
|
start &47
|
|
end &27
|
|
sat 32
|
|
eat 2
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1760,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1761,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "55250,14700,61350,16100"
|
|
st "yParallel"
|
|
blo "55250,15900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &52
|
|
)
|
|
*70 (Wire
|
|
uid 1829,0
|
|
shape (OrthoPolyLine
|
|
uid 1830,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "39750,40000,43000,52000"
|
|
pts [
|
|
"39750,40000"
|
|
"43000,40000"
|
|
"43000,52000"
|
|
]
|
|
)
|
|
start &20
|
|
end &12
|
|
sat 32
|
|
eat 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 1833,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 1834,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "41000,38700,49100,40100"
|
|
st "triggerOut"
|
|
blo "41000,39900"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &53
|
|
)
|
|
]
|
|
bg "65535,65535,65535"
|
|
grid (Grid
|
|
origin "0,0"
|
|
isVisible 0
|
|
isActive 1
|
|
xSpacing 1000
|
|
xySpacing 1000
|
|
xShown 1
|
|
yShown 1
|
|
color "26368,26368,26368"
|
|
)
|
|
packageList *71 (PackageList
|
|
uid 142,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*72 (Text
|
|
uid 143,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,0,6900,1000"
|
|
st "Package List"
|
|
blo "0,800"
|
|
)
|
|
*73 (MLText
|
|
uid 144,0
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,17500,4600"
|
|
st "LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.ALL;"
|
|
tm "PackageList"
|
|
)
|
|
]
|
|
)
|
|
compDirBlock (MlTextGroup
|
|
uid 145,0
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*74 (Text
|
|
uid 146,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,0,30200,1000"
|
|
st "Compiler Directives"
|
|
blo "20000,800"
|
|
)
|
|
*75 (Text
|
|
uid 147,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,1000,32200,2000"
|
|
st "Pre-module directives:"
|
|
blo "20000,1800"
|
|
)
|
|
*76 (MLText
|
|
uid 148,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,2000,32100,4400"
|
|
st "`resetall
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|
`timescale 1ns/10ps"
|
|
tm "BdCompilerDirectivesTextMgr"
|
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)
|
|
*77 (Text
|
|
uid 149,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,4000,32800,5000"
|
|
st "Post-module directives:"
|
|
blo "20000,4800"
|
|
)
|
|
*78 (MLText
|
|
uid 150,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,0,20000,0"
|
|
tm "BdCompilerDirectivesTextMgr"
|
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)
|
|
*79 (Text
|
|
uid 151,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "20000,5000,32400,6000"
|
|
st "End-module directives:"
|
|
blo "20000,5800"
|
|
)
|
|
*80 (MLText
|
|
uid 152,0
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "20000,6000,20000,6000"
|
|
tm "BdCompilerDirectivesTextMgr"
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)
|
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]
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)
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pageSetupInfo (PageSetupInfo
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ptrCmd "Generic PostScript Printer,winspool,"
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fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
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unixPaperWidth 595
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windowsPaperWidth 1077
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unixPaperName "A4 (210mm x 297mm)"
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windowsPaperName "A4"
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exportedDirectories [
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]
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)
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defaultCommentText (CommentText
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layer 0
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va (VaSet
|
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vasetType 1
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fg "65535,65535,65535"
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lineStyle 2
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)
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|
xt "0,0,15000,5000"
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)
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|
text (MLText
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va (VaSet
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fg "65535,0,0"
|
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)
|
|
xt "200,200,3200,1400"
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st "
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|
Text
|
|
"
|
|
tm "CommentText"
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|
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|
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)
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)
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defaultRequirementText (RequirementText
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va (VaSet
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fg "59904,39936,65280"
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lineColor "0,0,32768"
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)
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xt "0,0,1500,1750"
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text (MLText
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va (VaSet
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xt "450,2150,1450,3150"
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st "
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Text
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tm "RequirementText"
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)
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va (VaSet
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lineColor "32768,0,0"
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (Text
|
|
va (VaSet
|
|
font "Verdana,10,1"
|
|
)
|
|
xt "1000,1000,4400,2200"
|
|
st "Panel0"
|
|
blo "1000,2000"
|
|
tm "PanelText"
|
|
)
|
|
)
|
|
)
|
|
defaultBlk (Blk
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "40000,56832,65535"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*81 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,3200,6300,4400"
|
|
st "<library>"
|
|
blo "1700,4200"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*82 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,4400,5800,5600"
|
|
st "<block>"
|
|
blo "1700,5400"
|
|
tm "BlkNameMgr"
|
|
)
|
|
*83 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1700,5600,2900,6800"
|
|
st "I0"
|
|
blo "1700,6600"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "1700,13200,1700,13200"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
)
|
|
defaultMWComponent (MWC
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*84 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,3500,3300,4500"
|
|
st "Library"
|
|
blo "1000,4300"
|
|
)
|
|
*85 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,4500,7000,5500"
|
|
st "MWComponent"
|
|
blo "1000,5300"
|
|
)
|
|
*86 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1000,5500,1600,6500"
|
|
st "I0"
|
|
blo "1000,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6000,1500,-6000,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
prms (Property
|
|
pclass "params"
|
|
pname "params"
|
|
ptn "String"
|
|
)
|
|
visOptions (mwParamsVisibilityOptions
|
|
)
|
|
)
|
|
defaultSaComponent (SaComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*87 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,3500,3550,4500"
|
|
st "Library"
|
|
blo "1250,4300"
|
|
tm "BdLibraryNameMgr"
|
|
)
|
|
*88 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,4500,6750,5500"
|
|
st "SaComponent"
|
|
blo "1250,5300"
|
|
tm "CptNameMgr"
|
|
)
|
|
*89 (Text
|
|
va (VaSet
|
|
)
|
|
xt "1250,5500,1850,6500"
|
|
st "I0"
|
|
blo "1250,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-5750,1500,-5750,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
archFileType "UNKNOWN"
|
|
)
|
|
defaultVhdlComponent (VhdlComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*90 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,3500,3250,4500"
|
|
st "Library"
|
|
blo "950,4300"
|
|
)
|
|
*91 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,4500,7050,5500"
|
|
st "VhdlComponent"
|
|
blo "950,5300"
|
|
)
|
|
*92 (Text
|
|
va (VaSet
|
|
)
|
|
xt "950,5500,1550,6500"
|
|
st "I0"
|
|
blo "950,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6050,1500,-6050,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
archName ""
|
|
archPath ""
|
|
)
|
|
defaultVerilogComponent (VerilogComponent
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "-50,0,8050,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*93 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,3500,2750,4500"
|
|
st "Library"
|
|
blo "450,4300"
|
|
)
|
|
*94 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,4500,7550,5500"
|
|
st "VerilogComponent"
|
|
blo "450,5300"
|
|
)
|
|
*95 (Text
|
|
va (VaSet
|
|
)
|
|
xt "450,5500,1050,6500"
|
|
st "I0"
|
|
blo "450,6300"
|
|
tm "InstanceNameMgr"
|
|
)
|
|
]
|
|
)
|
|
ga (GenericAssociation
|
|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
isHidden 1
|
|
)
|
|
xt "-6550,1500,-6550,1500"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*96 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,4000,4600,5000"
|
|
st "eb1"
|
|
blo "3400,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*97 (Text
|
|
va (VaSet
|
|
)
|
|
xt "3400,5000,3800,6000"
|
|
st "1"
|
|
blo "3400,5800"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
)
|
|
xt "-300,-500,300,500"
|
|
st "G"
|
|
blo "-300,300"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,2600,1400"
|
|
st "sig0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "0,0,3900,1400"
|
|
st "dbus0"
|
|
blo "0,1200"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineStyle 3
|
|
lineWidth 1
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2600,1000"
|
|
st "bundle0"
|
|
blo "0,800"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,1500,2200"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,50000"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,0,5000,1200"
|
|
st "Auto list"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1000,9600,2200"
|
|
st "User defined list"
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,18500,100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*98 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*99 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "28160,28160,28160"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1100,11000,100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1050,1450"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "350,250,750,1250"
|
|
st "1"
|
|
blo "350,1050"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*100 (Text
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "14100,20000,22000,21000"
|
|
st "Frame Declarations"
|
|
blo "14100,20800"
|
|
)
|
|
*101 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "14100,21000,14100,21000"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,1400,1750"
|
|
st "Port"
|
|
blo "0,1550"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5400,7000,6400"
|
|
st "Declarations"
|
|
blo "0,6200"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,6400,3400,7400"
|
|
st "Ports:"
|
|
blo "0,7200"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,7400,4800,8400"
|
|
st "Pre User:"
|
|
blo "0,8200"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "2000,8400,21800,15400"
|
|
st "constant signalBitNb: positive := 16;
|
|
constant phaseBitNb: positive := 17;
|
|
constant stepX: positive := 2;
|
|
constant stepY: positive := 3;
|
|
constant lowpassShiftBitNb: positive := 8;
|
|
constant clockFrequency: real := 60.0E6;
|
|
--constant clockFrequency: real := 66.0E6;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,15400,9000,16400"
|
|
st "Diagram Signals:"
|
|
blo "0,16200"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,1"
|
|
)
|
|
xt "0,5400,6000,6400"
|
|
st "Post User:"
|
|
blo "0,6200"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "0,5400,0,5400"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 24,0
|
|
usingSuid 1
|
|
emptyRow *102 (LEmptyRow
|
|
)
|
|
uid 727,0
|
|
optionalChildren [
|
|
*103 (RefLabelRowHdr
|
|
)
|
|
*104 (TitleRowHdr
|
|
)
|
|
*105 (FilterRowHdr
|
|
)
|
|
*106 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*107 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*108 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*109 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*110 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*111 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*112 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*113 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*114 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*115 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 10,0
|
|
)
|
|
)
|
|
uid 1570,0
|
|
)
|
|
*116 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 1572,0
|
|
)
|
|
*117 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "ySerial"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 15,0
|
|
)
|
|
)
|
|
uid 1764,0
|
|
)
|
|
*118 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "xSerial"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 17,0
|
|
)
|
|
)
|
|
uid 1766,0
|
|
)
|
|
*119 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "xLowapss"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 18,0
|
|
)
|
|
)
|
|
uid 1768,0
|
|
)
|
|
*120 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "xParallel"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 5
|
|
suid 19,0
|
|
)
|
|
)
|
|
uid 1770,0
|
|
)
|
|
*121 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "yLowpass"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 7
|
|
suid 21,0
|
|
)
|
|
)
|
|
uid 1772,0
|
|
)
|
|
*122 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "yParallel"
|
|
t "unsigned"
|
|
b "(signalBitNb-1 DOWNTO 0)"
|
|
o 8
|
|
suid 23,0
|
|
)
|
|
)
|
|
uid 1774,0
|
|
)
|
|
*123 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "triggerOut"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 24,0
|
|
)
|
|
)
|
|
uid 1835,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 740,0
|
|
optionalChildren [
|
|
*124 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *125 (MRCItem
|
|
litem &102
|
|
pos 9
|
|
dimension 20
|
|
)
|
|
uid 742,0
|
|
optionalChildren [
|
|
*126 (MRCItem
|
|
litem &103
|
|
pos 0
|
|
dimension 20
|
|
uid 743,0
|
|
)
|
|
*127 (MRCItem
|
|
litem &104
|
|
pos 1
|
|
dimension 23
|
|
uid 744,0
|
|
)
|
|
*128 (MRCItem
|
|
litem &105
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 745,0
|
|
)
|
|
*129 (MRCItem
|
|
litem &115
|
|
pos 0
|
|
dimension 20
|
|
uid 1571,0
|
|
)
|
|
*130 (MRCItem
|
|
litem &116
|
|
pos 1
|
|
dimension 20
|
|
uid 1573,0
|
|
)
|
|
*131 (MRCItem
|
|
litem &117
|
|
pos 2
|
|
dimension 20
|
|
uid 1765,0
|
|
)
|
|
*132 (MRCItem
|
|
litem &118
|
|
pos 3
|
|
dimension 20
|
|
uid 1767,0
|
|
)
|
|
*133 (MRCItem
|
|
litem &119
|
|
pos 4
|
|
dimension 20
|
|
uid 1769,0
|
|
)
|
|
*134 (MRCItem
|
|
litem &120
|
|
pos 5
|
|
dimension 20
|
|
uid 1771,0
|
|
)
|
|
*135 (MRCItem
|
|
litem &121
|
|
pos 6
|
|
dimension 20
|
|
uid 1773,0
|
|
)
|
|
*136 (MRCItem
|
|
litem &122
|
|
pos 7
|
|
dimension 20
|
|
uid 1775,0
|
|
)
|
|
*137 (MRCItem
|
|
litem &123
|
|
pos 8
|
|
dimension 20
|
|
uid 1836,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 746,0
|
|
optionalChildren [
|
|
*138 (MRCItem
|
|
litem &106
|
|
pos 0
|
|
dimension 20
|
|
uid 747,0
|
|
)
|
|
*139 (MRCItem
|
|
litem &108
|
|
pos 1
|
|
dimension 50
|
|
uid 748,0
|
|
)
|
|
*140 (MRCItem
|
|
litem &109
|
|
pos 2
|
|
dimension 100
|
|
uid 749,0
|
|
)
|
|
*141 (MRCItem
|
|
litem &110
|
|
pos 3
|
|
dimension 50
|
|
uid 750,0
|
|
)
|
|
*142 (MRCItem
|
|
litem &111
|
|
pos 4
|
|
dimension 100
|
|
uid 751,0
|
|
)
|
|
*143 (MRCItem
|
|
litem &112
|
|
pos 5
|
|
dimension 100
|
|
uid 752,0
|
|
)
|
|
*144 (MRCItem
|
|
litem &113
|
|
pos 6
|
|
dimension 50
|
|
uid 753,0
|
|
)
|
|
*145 (MRCItem
|
|
litem &114
|
|
pos 7
|
|
dimension 80
|
|
uid 754,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 741,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 726,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *146 (LEmptyRow
|
|
)
|
|
uid 756,0
|
|
optionalChildren [
|
|
*147 (RefLabelRowHdr
|
|
)
|
|
*148 (TitleRowHdr
|
|
)
|
|
*149 (FilterRowHdr
|
|
)
|
|
*150 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*151 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*152 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*153 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*154 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*155 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*156 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*157 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 768,0
|
|
optionalChildren [
|
|
*158 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *159 (MRCItem
|
|
litem &146
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 770,0
|
|
optionalChildren [
|
|
*160 (MRCItem
|
|
litem &147
|
|
pos 0
|
|
dimension 20
|
|
uid 771,0
|
|
)
|
|
*161 (MRCItem
|
|
litem &148
|
|
pos 1
|
|
dimension 23
|
|
uid 772,0
|
|
)
|
|
*162 (MRCItem
|
|
litem &149
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 773,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 774,0
|
|
optionalChildren [
|
|
*163 (MRCItem
|
|
litem &150
|
|
pos 0
|
|
dimension 20
|
|
uid 775,0
|
|
)
|
|
*164 (MRCItem
|
|
litem &152
|
|
pos 1
|
|
dimension 50
|
|
uid 776,0
|
|
)
|
|
*165 (MRCItem
|
|
litem &153
|
|
pos 2
|
|
dimension 100
|
|
uid 777,0
|
|
)
|
|
*166 (MRCItem
|
|
litem &154
|
|
pos 3
|
|
dimension 100
|
|
uid 778,0
|
|
)
|
|
*167 (MRCItem
|
|
litem &155
|
|
pos 4
|
|
dimension 50
|
|
uid 779,0
|
|
)
|
|
*168 (MRCItem
|
|
litem &156
|
|
pos 5
|
|
dimension 50
|
|
uid 780,0
|
|
)
|
|
*169 (MRCItem
|
|
litem &157
|
|
pos 6
|
|
dimension 80
|
|
uid 781,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 769,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 755,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|