1093 lines
14 KiB
Plaintext
1093 lines
14 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2002,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 97,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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decl (Decl
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n "in1"
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t "std_uLogic"
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o 1
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suid 1,0
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)
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)
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uid 98,0
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)
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*3 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "out1"
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t "std_uLogic"
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o 2
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suid 2,0
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)
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)
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uid 99,0
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)
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*4 (RefLabelRowHdr
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)
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*5 (TitleRowHdr
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)
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*6 (FilterRowHdr
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)
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*7 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*8 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*9 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*10 (NameColHdr
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tm "NameColHdrMgr"
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)
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*11 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*12 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*13 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*14 (InitColHdr
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tm "InitColHdrMgr"
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)
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*15 (EolColHdr
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tm "EolColHdrMgr"
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)
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]
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)
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pdm (PhysicalDM
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uid 100,0
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optionalChildren [
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*16 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
|
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
|
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groupVa (MVa
|
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *17 (MRCItem
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litem &1
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pos 3
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dimension 20
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)
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uid 43,0
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optionalChildren [
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*18 (MRCItem
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litem &4
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pos 0
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dimension 20
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uid 46,0
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)
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*19 (MRCItem
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litem &5
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pos 1
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dimension 23
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uid 48,0
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)
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*20 (MRCItem
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litem &6
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pos 2
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hidden 1
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dimension 20
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uid 50,0
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)
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*21 (MRCItem
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litem &2
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pos 0
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dimension 20
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uid 69,0
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)
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*22 (MRCItem
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litem &3
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pos 1
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dimension 20
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uid 70,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
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uid 44,0
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optionalChildren [
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*23 (MRCItem
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litem &7
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pos 0
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dimension 20
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uid 52,0
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)
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*24 (MRCItem
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litem &9
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pos 1
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dimension 50
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uid 56,0
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)
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*25 (MRCItem
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litem &10
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pos 2
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dimension 100
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uid 58,0
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)
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*26 (MRCItem
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litem &11
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pos 3
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dimension 50
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uid 60,0
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)
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*27 (MRCItem
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litem &12
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pos 4
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dimension 100
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uid 62,0
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)
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*28 (MRCItem
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litem &13
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pos 5
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dimension 100
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uid 64,0
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)
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*29 (MRCItem
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litem &14
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pos 6
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dimension 50
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uid 66,0
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)
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*30 (MRCItem
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litem &15
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pos 7
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dimension 80
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uid 68,0
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)
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]
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)
|
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 42,0
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vaOverrides [
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]
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)
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]
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)
|
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uid 96,0
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)
|
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genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *31 (LEmptyRow
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)
|
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uid 102,0
|
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optionalChildren [
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*32 (RefLabelRowHdr
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)
|
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*33 (TitleRowHdr
|
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)
|
|
*34 (FilterRowHdr
|
|
)
|
|
*35 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*36 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*37 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*38 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
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)
|
|
*39 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
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)
|
|
*40 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
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)
|
|
*41 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
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)
|
|
*42 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 103,0
|
|
optionalChildren [
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*43 (Sheet
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sheetRow (SheetRow
|
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headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *44 (MRCItem
|
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litem &31
|
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pos 3
|
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dimension 20
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)
|
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uid 72,0
|
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optionalChildren [
|
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*45 (MRCItem
|
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litem &32
|
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pos 0
|
|
dimension 20
|
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uid 75,0
|
|
)
|
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*46 (MRCItem
|
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litem &33
|
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pos 1
|
|
dimension 23
|
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uid 77,0
|
|
)
|
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*47 (MRCItem
|
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litem &34
|
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pos 2
|
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hidden 1
|
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dimension 20
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uid 79,0
|
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)
|
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]
|
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)
|
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sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
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)
|
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uid 73,0
|
|
optionalChildren [
|
|
*48 (MRCItem
|
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litem &35
|
|
pos 0
|
|
dimension 20
|
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uid 81,0
|
|
)
|
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*49 (MRCItem
|
|
litem &37
|
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pos 1
|
|
dimension 50
|
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uid 85,0
|
|
)
|
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*50 (MRCItem
|
|
litem &38
|
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pos 2
|
|
dimension 100
|
|
uid 87,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &39
|
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pos 3
|
|
dimension 100
|
|
uid 89,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &40
|
|
pos 4
|
|
dimension 50
|
|
uid 91,0
|
|
)
|
|
*53 (MRCItem
|
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litem &41
|
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pos 5
|
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dimension 50
|
|
uid 93,0
|
|
)
|
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*54 (MRCItem
|
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litem &42
|
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pos 6
|
|
dimension 80
|
|
uid 95,0
|
|
)
|
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]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 71,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 101,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds/inverter/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds/inverter/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds/inverter"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds/inverter"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Tue"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Tuesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "19"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "inverter"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:07:09"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Board"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "$HDS_PROJECT_DIR/../Board/concat"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Board"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "02"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "inverter"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Feb"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "February"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds/inverter/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Prefs/../Board/hds/inverter/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "lissajous"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:07:09"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "inverter"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 29,0
|
|
optionalChildren [
|
|
*55 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*56 (CptPort
|
|
uid 16,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 17,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "22250,6625,23000,7375"
|
|
)
|
|
tg (CPTG
|
|
uid 38,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 19,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "courier,12,0"
|
|
)
|
|
xt "23000,6500,25700,7900"
|
|
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