345 lines
12 KiB
VHDL
345 lines
12 KiB
VHDL
ARCHITECTURE studentVersion OF charToMorseController IS
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signal isA, isB, isC, isD, isE, isF, isG, isH,
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isI, isJ, isK, isL, isM, isN, isO, isP,
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isQ, isR, isS, isT, isU, isV, isW, isX,
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isY, isZ,
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is0, is1, is2, is3, is4, is5, is6, is7,
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is8, is9 : std_ulogic;
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type T_MORSE is (SHORT, LONG, SPACE, END_WORD);
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--type registers_type is array (1 to 5) of T_MORSE;
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signal register1: T_MORSE;
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signal register2: T_MORSE;
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signal register3: T_MORSE;
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signal register4: T_MORSE;
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signal register5: T_MORSE;
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TYPE GENERAL_STATE_TYPE IS (
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waitForChar,
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storeChar,
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sendRegisters,
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sended
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);
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signal general_current_state, general_next_state : GENERAL_STATE_TYPE;
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TYPE SENDING_STATE_TYPE IS (
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waiting,
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sendR1,
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waitR1,
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sendR2,
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waitR2,
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sendR3,
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waitR3,
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sendR4,
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waitR4,
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sendR5,
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waitEndWord
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);
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signal sending_current_state, sending_next_state : SENDING_STATE_TYPE;
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BEGIN
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------------------------------------------------------------------------------
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-- conditions for morse units
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isA <= '1' when std_match(unsigned(char), "1-0" & x"1") else '0'; -- 1-0 0001
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isB <= '1' when std_match(unsigned(char), "1-0" & x"2") else '0'; -- 1-0 0010
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isC <= '1' when std_match(unsigned(char), "1-0" & x"3") else '0'; -- 1-0 0011
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isD <= '1' when std_match(unsigned(char), "1-0" & x"4") else '0'; -- 1-0 0100
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isE <= '1' when std_match(unsigned(char), "1-0" & x"5") else '0'; -- 1-0 0101
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isF <= '1' when std_match(unsigned(char), "1-0" & x"6") else '0'; -- 1-0 0110
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isG <= '1' when std_match(unsigned(char), "1-0" & x"7") else '0'; -- 1-0 0111
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isH <= '1' when std_match(unsigned(char), "1-0" & x"8") else '0'; -- 1-0 1000
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isI <= '1' when std_match(unsigned(char), "1-0" & x"9") else '0'; -- 1-0 1001
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isJ <= '1' when std_match(unsigned(char), "1-0" & x"A") else '0'; -- 1-0 1010
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isK <= '1' when std_match(unsigned(char), "1-0" & x"B") else '0'; -- 1-0 1011
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isL <= '1' when std_match(unsigned(char), "1-0" & x"C") else '0'; -- 1-0 1100
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isM <= '1' when std_match(unsigned(char), "1-0" & x"D") else '0'; -- 1-0 1101
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isN <= '1' when std_match(unsigned(char), "1-0" & x"E") else '0'; -- 1-0 1110
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isO <= '1' when std_match(unsigned(char), "1-0" & x"F") else '0'; -- 1-0 1111
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isP <= '1' when std_match(unsigned(char), "1-1" & x"0") else '0'; -- 1-1 0000
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isQ <= '1' when std_match(unsigned(char), "1-1" & x"1") else '0'; -- 1-1 0001
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isR <= '1' when std_match(unsigned(char), "1-1" & x"2") else '0'; -- 1-1 0010
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isS <= '1' when std_match(unsigned(char), "1-1" & x"3") else '0'; -- 1-1 0011
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isT <= '1' when std_match(unsigned(char), "1-1" & x"4") else '0'; -- 1-1 0100
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isU <= '1' when std_match(unsigned(char), "1-1" & x"5") else '0'; -- 1-1 0101
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isV <= '1' when std_match(unsigned(char), "1-1" & x"6") else '0'; -- 1-1 0110
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isW <= '1' when std_match(unsigned(char), "1-1" & x"7") else '0'; -- 1-1 0111
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isX <= '1' when std_match(unsigned(char), "1-1" & x"8") else '0'; -- 1-1 1000
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isY <= '1' when std_match(unsigned(char), "1-1" & x"9") else '0'; -- 1-1 1001
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isZ <= '1' when std_match(unsigned(char), "1-1" & x"A") else '0'; -- 1-1 1010
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is0 <= '1' when std_match(unsigned(char), "011" & x"0") else '0'; -- 011 0000
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is1 <= '1' when std_match(unsigned(char), "011" & x"1") else '0'; -- 011 0001
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is2 <= '1' when std_match(unsigned(char), "011" & x"2") else '0'; -- 011 0010
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is3 <= '1' when std_match(unsigned(char), "011" & x"3") else '0'; -- 011 0011
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is4 <= '1' when std_match(unsigned(char), "011" & x"4") else '0'; -- 011 0100
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is5 <= '1' when std_match(unsigned(char), "011" & x"5") else '0'; -- 011 0101
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is6 <= '1' when std_match(unsigned(char), "011" & x"6") else '0'; -- 011 0110
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is7 <= '1' when std_match(unsigned(char), "011" & x"7") else '0'; -- 011 0111
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is8 <= '1' when std_match(unsigned(char), "011" & x"8") else '0'; -- 011 1000
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is9 <= '1' when std_match(unsigned(char), "011" & x"9") else '0'; -- 011 1001
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process(reset, clock) begin
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if reset = '1' then
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general_current_state <= waitForChar;
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sending_current_state <= waiting;
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elsif rising_edge(clock) then
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general_current_state <= general_next_state;
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sending_current_state <= sending_next_state;
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end if;
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end process;
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process(general_current_state) begin
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case general_current_state is
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when waitForChar =>
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register1 <= END_WORD;
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register2 <= END_WORD;
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register3 <= END_WORD;
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register4 <= END_WORD;
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register5 <= END_WORD;
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if charNotReady = '0' then
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general_next_state <= storeChar;
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else
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general_next_state <= waitForChar;
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end if;
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when storeChar =>
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if isA then
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register1 <= SHORT;
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register2 <= LONG;
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general_next_state <= sendRegisters;
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elsif isB then
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register1 <= LONG;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isC then
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register1 <= LONG;
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register2 <= SHORT;
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register3 <= LONG;
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register4 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isD then
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register1 <= LONG;
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register2 <= SHORT;
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register3 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isE then
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register1 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isF then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= LONG;
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register4 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isG then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isH then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isI then
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register1 <= SHORT;
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register2 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isJ then
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register1 <= SHORT;
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register2 <= LONG;
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register3 <= LONG;
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register4 <= LONG;
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general_next_state <= sendRegisters;
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elsif isK then
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register1 <= LONG;
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register2 <= SHORT;
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register3 <= LONG;
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general_next_state <= sendRegisters;
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elsif isL then
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register1 <= SHORT;
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register2 <= LONG;
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register3 <= SHORT;
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register4 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isM then
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register1 <= LONG;
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register2 <= LONG;
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general_next_state <= sendRegisters;
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elsif isN then
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register1 <= LONG;
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register2 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isO then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= LONG;
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general_next_state <= sendRegisters;
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elsif isP then
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register1 <= SHORT;
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register2 <= LONG;
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register3 <= LONG;
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register4 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isQ then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= SHORT;
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register4 <= LONG;
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general_next_state <= sendRegisters;
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elsif isR then
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register1 <= SHORT;
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register2 <= LONG;
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register3 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isS then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= SHORT;
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general_next_state <= sendRegisters;
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elsif isT then
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register1 <= LONG;
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general_next_state <= sendRegisters;
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elsif isU then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= LONG;
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general_next_state <= sendRegisters;
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elsif isV then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= LONG;
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general_next_state <= sendRegisters;
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elsif isW then
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register1 <= SHORT;
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register2 <= LONG;
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register3 <= LONG;
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general_next_state <= sendRegisters;
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elsif isX then
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register1 <= LONG;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= LONG;
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general_next_state <= sendRegisters;
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elsif isY then
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register1 <= LONG;
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register2 <= SHORT;
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register3 <= LONG;
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register4 <= LONG;
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general_next_state <= sendRegisters;
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elsif isZ then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= SHORT;
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register4 <= SHORT;
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general_next_state <= sendRegisters;
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elsif is0 then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= LONG;
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register4 <= LONG;
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register5 <= LONG;
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general_next_state <= sendRegisters;
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elsif is1 then
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register1 <= SHORT;
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register2 <= LONG;
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register3 <= LONG;
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register4 <= LONG;
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register5 <= LONG;
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general_next_state <= sendRegisters;
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elsif is2 then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= LONG;
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register4 <= LONG;
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register5 <= LONG;
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general_next_state <= sendRegisters;
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elsif is3 then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= LONG;
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register5 <= LONG;
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general_next_state <= sendRegisters;
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elsif is4 then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= SHORT;
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register5 <= LONG;
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general_next_state <= sendRegisters;
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elsif is5 then
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register1 <= SHORT;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= SHORT;
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register5 <= SHORT;
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general_next_state <= sendRegisters;
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elsif is6 then
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register1 <= LONG;
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register2 <= SHORT;
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register3 <= SHORT;
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register4 <= SHORT;
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register5 <= SHORT;
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general_next_state <= sendRegisters;
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elsif is7 then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= SHORT;
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register4 <= SHORT;
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register5 <= SHORT;
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general_next_state <= sendRegisters;
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elsif is8 then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= LONG;
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register4 <= SHORT;
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register5 <= SHORT;
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general_next_state <= sendRegisters;
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elsif is9 then
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register1 <= LONG;
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register2 <= LONG;
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register3 <= LONG;
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register4 <= LONG;
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register5 <= SHORT;
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general_next_state <= sendRegisters;
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else
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register1 <= END_WORD;
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register2 <= END_WORD;
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register3 <= END_WORD;
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register4 <= END_WORD;
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register5 <= END_WORD;
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general_next_state <= storeChar;
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end if;
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when sendRegisters =>
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sending_next_state <= sendR1;
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when sended =>
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register1 <= END_WORD;
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register2 <= END_WORD;
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register3 <= END_WORD;
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register4 <= END_WORD;
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register5 <= END_WORD;
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WHEN OTHERS =>
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general_next_state <= waitForChar;
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end case;
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end process;
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process(sending_current_state) begin
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end process;
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morseOut <= '0';
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startCounter <= '0';
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unitNb <= (others => '-');
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END ARCHITECTURE studentVersion;
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