1810 lines
23 KiB
Plaintext
1810 lines
23 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 2008,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 198,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "triangle"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 7
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suid 5,0
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)
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)
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uid 200,0
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)
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*3 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "square"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 6
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suid 6,0
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)
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)
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uid 201,0
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)
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*4 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "sawtooth"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 4
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suid 3,0
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)
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)
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uid 202,0
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)
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*5 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "sine"
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t "unsigned"
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b "(signalBitNb-1 DOWNTO 0)"
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o 5
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suid 4,0
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)
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)
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uid 203,0
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)
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*6 (LogPort
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port (LogicalPort
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decl (Decl
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|
n "reset"
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t "std_ulogic"
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o 2
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suid 2,0
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)
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)
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uid 204,0
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)
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*7 (LogPort
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port (LogicalPort
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decl (Decl
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|
n "clock"
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t "std_ulogic"
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o 1
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suid 1,0
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)
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)
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uid 205,0
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)
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*8 (LogPort
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port (LogicalPort
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decl (Decl
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|
n "step"
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|
t "unsigned"
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|
b "(phaseBitNb-1 DOWNTO 0)"
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o 3
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suid 8,0
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)
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)
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uid 206,0
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)
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*9 (RefLabelRowHdr
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)
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*10 (TitleRowHdr
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)
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|
*11 (FilterRowHdr
|
|
)
|
|
*12 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*13 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
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)
|
|
*14 (GroupColHdr
|
|
tm "GroupColHdrMgr"
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|
)
|
|
*15 (NameColHdr
|
|
tm "NameColHdrMgr"
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|
)
|
|
*16 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*17 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*18 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
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)
|
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*19 (InitColHdr
|
|
tm "InitColHdrMgr"
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)
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*20 (EolColHdr
|
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tm "EolColHdrMgr"
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)
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]
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)
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pdm (PhysicalDM
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|
displayShortBounds 1
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editShortBounds 1
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uid 207,0
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optionalChildren [
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*21 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "courier,10,0"
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)
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emptyMRCItem *22 (MRCItem
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litem &1
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pos 8
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dimension 20
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)
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uid 134,0
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optionalChildren [
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*23 (MRCItem
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litem &9
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pos 0
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dimension 20
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uid 137,0
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)
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*24 (MRCItem
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litem &10
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pos 1
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dimension 23
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uid 139,0
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)
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*25 (MRCItem
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litem &11
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pos 2
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hidden 1
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dimension 20
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uid 141,0
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)
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*26 (MRCItem
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litem &2
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pos 3
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dimension 20
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uid 161,0
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)
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*27 (MRCItem
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litem &3
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pos 4
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dimension 20
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uid 162,0
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)
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*28 (MRCItem
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litem &4
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pos 2
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dimension 20
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uid 163,0
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)
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*29 (MRCItem
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litem &5
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pos 5
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dimension 20
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uid 164,0
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)
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*30 (MRCItem
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litem &6
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pos 1
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dimension 20
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uid 165,0
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)
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*31 (MRCItem
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litem &7
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pos 0
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dimension 20
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uid 166,0
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)
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*32 (MRCItem
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litem &8
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pos 6
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dimension 20
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uid 167,0
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)
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]
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)
|
|
sheetCol (SheetCol
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|
propVa (MVa
|
|
cellColor "0,49152,49152"
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|
fontColor "0,0,0"
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font "courier,10,0"
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textAngle 90
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)
|
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uid 135,0
|
|
optionalChildren [
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|
*33 (MRCItem
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litem &12
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pos 0
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dimension 20
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uid 143,0
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)
|
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*34 (MRCItem
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litem &14
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pos 1
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dimension 50
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uid 147,0
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)
|
|
*35 (MRCItem
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litem &15
|
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pos 2
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dimension 100
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|
uid 149,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &16
|
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pos 3
|
|
dimension 50
|
|
uid 151,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &17
|
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pos 4
|
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dimension 100
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|
uid 153,0
|
|
)
|
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*38 (MRCItem
|
|
litem &18
|
|
pos 5
|
|
dimension 100
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|
uid 155,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &19
|
|
pos 6
|
|
dimension 50
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|
uid 157,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &20
|
|
pos 7
|
|
dimension 80
|
|
uid 159,0
|
|
)
|
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]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
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|
name "Ports"
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|
uid 133,0
|
|
vaOverrides [
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|
]
|
|
)
|
|
]
|
|
)
|
|
uid 197,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *41 (LEmptyRow
|
|
)
|
|
uid 209,0
|
|
optionalChildren [
|
|
*42 (RefLabelRowHdr
|
|
)
|
|
*43 (TitleRowHdr
|
|
)
|
|
*44 (FilterRowHdr
|
|
)
|
|
*45 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*46 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*47 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*48 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*49 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*50 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*51 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*52 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*53 (LogGeneric
|
|
generic (GiElement
|
|
name "signalBitNb"
|
|
type "positive"
|
|
value "16"
|
|
)
|
|
uid 193,0
|
|
)
|
|
*54 (LogGeneric
|
|
generic (GiElement
|
|
name "phaseBitNb"
|
|
type "positive"
|
|
value "10"
|
|
)
|
|
uid 194,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 210,0
|
|
optionalChildren [
|
|
*55 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *56 (MRCItem
|
|
litem &41
|
|
pos 2
|
|
dimension 20
|
|
)
|
|
uid 169,0
|
|
optionalChildren [
|
|
*57 (MRCItem
|
|
litem &42
|
|
pos 0
|
|
dimension 20
|
|
uid 172,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &43
|
|
pos 1
|
|
dimension 23
|
|
uid 174,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &44
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 176,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &53
|
|
pos 0
|
|
dimension 20
|
|
uid 195,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &54
|
|
pos 1
|
|
dimension 20
|
|
uid 196,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 170,0
|
|
optionalChildren [
|
|
*62 (MRCItem
|
|
litem &45
|
|
pos 0
|
|
dimension 20
|
|
uid 178,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &47
|
|
pos 1
|
|
dimension 50
|
|
uid 182,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &48
|
|
pos 2
|
|
dimension 100
|
|
uid 184,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &49
|
|
pos 3
|
|
dimension 100
|
|
uid 186,0
|
|
)
|
|
*66 (MRCItem
|
|
litem &50
|
|
pos 4
|
|
dimension 50
|
|
uid 188,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &51
|
|
pos 5
|
|
dimension 50
|
|
uid 190,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &52
|
|
pos 6
|
|
dimension 80
|
|
uid 192,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 168,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 208,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sineGen"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Tue"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Tuesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "19"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "sineGen"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "02/19/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:00:40"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SplineInterpolator"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SplineInterpolator"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "U:\\SEm_curves\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "02"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "sineGen"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Feb"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "February"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sine@gen/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SplineInterpolator/Prefs/../SplineInterpolator/hds/sineGen/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "splineInterpolator"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:00:40"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "sineGen"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
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LanguageMgr "Vhdl2008LangMgr"
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uid 51,0
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decl (Decl
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uid 118,0
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