28 lines
1.1 KiB
VHDL
28 lines
1.1 KiB
VHDL
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ARCHITECTURE rtl OF aluDecoder IS
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signal lsig_rTypeSub : std_ulogic;
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BEGIN
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lsig_rTypeSub <= funct7 and op; -- true for R-type substract
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decode : process(op, funct3, funct7, ALUOp, lsig_rTypeSub)
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begin
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case ALUOp is
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when "00" => ALUControl <= "000" after g_tDec; -- addition
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when "01" => ALUControl <= "001" after g_tDec; -- substraction
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when others =>
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case funct3 is -- R-type or I-type
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when "000" =>
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if lsig_rTypeSub = '1' then
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ALUControl <= "001" after g_tDec; -- sub
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else
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ALUControl <= "000" after g_tDec; -- add, addi
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end if;
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when "010" => ALUControl <= "101" after g_tDec; -- slt, slti
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when "110" => ALUControl <= "011" after g_tDec; -- or, ori
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when "111" => ALUControl <= "010" after g_tDec; -- and, andi
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when others => ALUControl <= "---" after g_tDec; -- unknown
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end case;
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end case;
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end process decode;
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END ARCHITECTURE rtl;
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