SEm-Labos/Libs/RiscV/NEORV32/setups/README.md

Exemplary FPGA Board Setups

• Setups using Commercial Toolchains
• Setups using Open-Source Toolchains
• Adding Your Project Setup
• Setup-Specific NEORV32 Software Framework Modification

This folder provides exemplary NEORV32 SoC setups and projects for different FPGA platforms/boards. You can directly use one of the provided setups or use them as starting point to build your own setup. Project maintainers may make pull requests against this repository to add or link their setups.

Setups using Commercial Toolchains

Setup	Toolchain	Board 📚	FPGA	Author(s)
📁 de0-nano-test-setup	Intel Quartus Prime	Terasic DE0-Nano	Intel Cyclone IV EP4CE22F17C6N	stnolting
📁 de0-nano-test-setup-qsys	Intel Quartus Prime	Terasic DE0-Nano	Intel Cyclone IV EP4CE22F17C6N	torerams
📁 de0-nano-test-setup-avalonmm	Intel Quartus Prime	Terasic DE0-Nano	Intel Cyclone IV EP4CE22F17C6N	torerams
📁 terasic-cyclone-V-gx-starter-kit-test-setup	Intel Quartus Prime	Terasic Cyclone-V GX Starter Kit	Intel Cyclone V 5CGXFC5C6F27C7N	zs6mue
📁 UPduino_v3	Lattice Radiant	tinyVision.ai Inc. UPduino v3.0	Lattice iCE40 UltraPlus iCE40UP5K-SG48I	stnolting
📁 arty-a7-35-test-setup	Xilinx Vivado	Digilent Arty A7-35	Xilinx Artix-7 XC7A35TICSG324-1L	stnolting
📁 nexys-a7-test-setup	Xilinx Vivado	Digilent Nexys A7	Xilinx Artix-7 XC7A50TCSG324-1	AWenzel83
📁 nexys-a7-test-setup	Xilinx Vivado	Digilent Nexys 4 DDR	Xilinx Artix-7 XC7A100TCSG324-1	AWenzel83
🌍 custom CRC32 processor module for the nexys-a7 boards (tutorial)	Xilinx Vivado	Digilent Nexys A7	Xilinx Artix-7 XC7A50TCSG324-1	motius (ikstvn, turbinenreiter)
🌍 neorv32-examples	Intel Quartus Prime	Different Terasic boards	Different Intel FPGAs	emb4fun

Setups using Open-Source Toolchains

Setup	Toolchain	Board 📚	FPGA	Author(s)
📁 UPduino v3	GHDL, Yosys, nextPNR	UPduino v3.0	Lattice iCE40 UltraPlus iCE40UP5K-SG48I	tmeissner
📁 FOMU	GHDL, Yosys, nextPNR	FOMU	Lattice iCE40 UltraPlus iCE40UP5K-SG48I	umarcor
📁 iCESugar	GHDL, Yosys, nextPNR	iCESugar	Lattice iCE40 UltraPlus iCE40UP5K-SG48I	umarcor
📁 AlhambraII	GHDL, Yosys, nextPNR	AlhambraII	Lattice iCE40HX4K	zipotron
📁 Orange Crab	GHDL, Yosys, nextPNR	Orange Crab	Lattice ECP5-25F	umarcor, jeremyherbert
📁 ULX3S	GHDL, Yosys, nextPNR	ULX3S	Lattice ECP5 LFE5U-85F-6BG381C	zipotron
🌍 ULX3S-SDRAM	GHDL, Yosys, nextPNR	ULX3S	Lattice ECP5 LFE5U-85F-6BG381C	zipotron

ℹ️ All setups using open-source toolchains are located in the osflow folder. See the README there for more information how to run a specific setup / configuration.

Adding Your Project Setup

Please respect the following guidelines if you'd like to add (or link) your setup to the list.

• check out the project's code of conduct
• add a link if the board you are using provides online documentation (and/or can be purchased somewhere)
• use the 📁 emoji (:file_folder:) if the setup is located in this folder; use the 🌍 emoji (:earth_africa:) if it is a link to your local project
• please add a README to give some brief information about the setup and a .gitignore to keep things clean; take a look at UPduino_v3 to get some ideas what a project setup might look like

Setup-Specific NEORV32 Software Framework Modification

In order to use the features provided by the setups, minor optional changes can be made to the default NEORV32 setup.

• To change the default data memory size take a look at the 📚 User Guide section General Software Framework Setup
• To modify the SPI flash base address for storing/booting software application see 📚 User Guide section Customizing the Internal Bootloader