153 lines
4.4 KiB
Plaintext
153 lines
4.4 KiB
Plaintext
--
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-- VHDL Architecture Lissajous_test.lissajousGenerator_test.struct
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:48:46 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.ALL;
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LIBRARY Lissajous;
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LIBRARY Lissajous_test;
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LIBRARY WaveformGenerator;
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ARCHITECTURE struct OF lissajousGenerator_test IS
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-- Architecture declarations
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constant signalBitNb: positive := 16;
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constant phaseBitNb: positive := 17;
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constant stepX: positive := 2;
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constant stepY: positive := 3;
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constant lowpassShiftBitNb: positive := 8;
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constant clockFrequency: real := 60.0E6;
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--constant clockFrequency: real := 66.0E6;
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-- Internal signal declarations
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SIGNAL clock : std_ulogic;
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SIGNAL reset : std_ulogic;
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SIGNAL triggerOut : std_ulogic;
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SIGNAL xLowapss : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL xParallel : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL xSerial : std_ulogic;
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SIGNAL yLowpass : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL yParallel : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL ySerial : std_ulogic;
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-- Component Declarations
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COMPONENT lissajousGenerator
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GENERIC (
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signalBitNb : positive := 16;
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phaseBitNb : positive := 16;
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stepX : positive := 1;
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stepY : positive := 1
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);
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PORT (
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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triggerOut : OUT std_ulogic ;
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xOut : OUT std_ulogic ;
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yOut : OUT std_ulogic
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);
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END COMPONENT;
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COMPONENT lissajousGenerator_tester
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GENERIC (
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signalBitNb : positive := 16;
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clockFrequency : real := 60.0E6
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);
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PORT (
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triggerOut : IN std_ulogic ;
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xLowapss : IN unsigned (signalBitNb-1 DOWNTO 0);
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xSerial : IN std_ulogic ;
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yLowpass : IN unsigned (signalBitNb-1 DOWNTO 0);
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ySerial : IN std_ulogic ;
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clock : OUT std_ulogic ;
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reset : OUT std_ulogic
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);
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END COMPONENT;
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COMPONENT lowpass
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GENERIC (
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signalBitNb : positive := 16;
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shiftBitNb : positive := 12
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);
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PORT (
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lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
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FOR ALL : lissajousGenerator_tester USE ENTITY Lissajous_test.lissajousGenerator_tester;
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FOR ALL : lowpass USE ENTITY WaveformGenerator.lowpass;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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xParallel <= (others => xSerial);
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yParallel <= (others => ySerial);
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-- Instance port mappings.
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I_DUT : lissajousGenerator
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb,
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stepX => stepX,
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stepY => stepY
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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triggerOut => triggerOut,
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xOut => xSerial,
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yOut => ySerial
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);
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I_tester : lissajousGenerator_tester
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GENERIC MAP (
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signalBitNb => signalBitNb,
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clockFrequency => clockFrequency
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)
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PORT MAP (
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triggerOut => triggerOut,
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xLowapss => xLowapss,
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xSerial => xSerial,
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yLowpass => yLowpass,
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ySerial => ySerial,
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clock => clock,
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reset => reset
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);
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I_filtX : lowpass
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GENERIC MAP (
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signalBitNb => signalBitNb,
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shiftBitNb => lowpassShiftBitNb
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)
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PORT MAP (
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lowpassOut => xLowapss,
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clock => clock,
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reset => reset,
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lowpassIn => xParallel
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);
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I_filty : lowpass
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GENERIC MAP (
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signalBitNb => signalBitNb,
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shiftBitNb => lowpassShiftBitNb
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)
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PORT MAP (
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lowpassOut => yLowpass,
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clock => clock,
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reset => reset,
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lowpassIn => yParallel
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);
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END struct;
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