4393 lines
51 KiB
Plaintext
4393 lines
51 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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instances [
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(Instance
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name "U_pll"
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duLibraryName "Lattice"
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duName "pll"
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elements [
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]
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mwi 0
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uid 168,0
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)
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(Instance
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name "I_inv1"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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]
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mwi 0
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uid 199,0
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)
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(Instance
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name "I_dff"
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duLibraryName "Board"
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duName "DFF"
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elements [
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]
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mwi 0
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uid 219,0
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)
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(Instance
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name "I_inv2"
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duLibraryName "Board"
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duName "inverterIn"
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elements [
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]
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mwi 0
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uid 245,0
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)
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(Instance
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name "I_main"
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duLibraryName "Lissajous"
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duName "lissajousGenerator"
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elements [
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(GiElement
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name "signalBitNb"
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type "positive"
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value "signalBitNb"
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)
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(GiElement
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name "phaseBitNb"
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type "positive"
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value "phaseBitNb"
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)
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(GiElement
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name "stepX"
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type "positive"
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value "stepX"
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)
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(GiElement
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|
name "stepY"
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type "positive"
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value "stepY"
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)
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]
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mwi 0
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uid 265,0
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)
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]
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embeddedInstances [
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|
(EmbeddedInstance
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name "eb5"
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number "5"
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)
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(EmbeddedInstance
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name "eb6"
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number "6"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
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model (BlockDiag
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VExpander (VariableExpander
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vvMap [
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3\\master@version.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3\\master@version.bd.user"
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)
|
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(vvPair
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|
variable "SourceDir"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds"
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)
|
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(vvPair
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|
variable "appl"
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value "HDL Designer"
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)
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|
(vvPair
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|
variable "arch_name"
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value "masterVersion"
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)
|
|
(vvPair
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|
variable "concat_file"
|
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value "concatenated"
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)
|
|
(vvPair
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variable "config"
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value "%(unit)_%(view)_config"
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)
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(vvPair
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variable "d"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3"
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)
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(vvPair
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variable "d_logical"
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajousGenerator_circuit_EBS3"
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)
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(vvPair
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variable "date"
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value "01.05.2023"
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)
|
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(vvPair
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variable "day"
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value "lun."
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)
|
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(vvPair
|
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variable "day_long"
|
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value "lundi"
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)
|
|
(vvPair
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variable "dd"
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value "01"
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)
|
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(vvPair
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variable "entity_name"
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value "lissajousGenerator_circuit_EBS3"
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)
|
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(vvPair
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variable "ext"
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value "<TBD>"
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)
|
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(vvPair
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variable "f"
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value "master@version.bd"
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)
|
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(vvPair
|
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variable "f_logical"
|
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value "masterVersion.bd"
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)
|
|
(vvPair
|
|
variable "f_noext"
|
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value "master@version"
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)
|
|
(vvPair
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variable "graphical_source_author"
|
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value "axel.amand"
|
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)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "01.05.2023"
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)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
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value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
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value "WE7860"
|
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)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
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value "17:45:49"
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)
|
|
(vvPair
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|
variable "group"
|
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value "UNKNOWN"
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)
|
|
(vvPair
|
|
variable "host"
|
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value "WE7860"
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)
|
|
(vvPair
|
|
variable "language"
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value "VHDL"
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)
|
|
(vvPair
|
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variable "library"
|
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value "Board"
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)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
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value "$HDS_PROJECT_DIR/../Board/concat"
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)
|
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(vvPair
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variable "library_downstream_ModelSimCompiler"
|
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value "$SCRATCH_DIR/Board"
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)
|
|
(vvPair
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variable "mm"
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value "05"
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)
|
|
(vvPair
|
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variable "module_name"
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value "lissajousGenerator_circuit_EBS3"
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)
|
|
(vvPair
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variable "month"
|
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value "mai"
|
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)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "mai"
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)
|
|
(vvPair
|
|
variable "p"
|
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value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3\\master@version.bd"
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|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajousGenerator_circuit_EBS3\\masterVersion.bd"
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|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
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value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "bd"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "master@version"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "masterVersion"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "17:45:49"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "lissajousGenerator_circuit_EBS3"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "axel.amand"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2019.2 (Build 5)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "masterVersion"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2023"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "23"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 52,0
|
|
optionalChildren [
|
|
*1 (SaComponent
|
|
uid 168,0
|
|
optionalChildren [
|
|
*2 (CptPort
|
|
uid 132,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 133,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "51000,6625,51750,7375"
|
|
)
|
|
tg (CPTG
|
|
uid 134,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 135,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "45700,6500,50000,7500"
|
|
st "clk10MHz"
|
|
ju 2
|
|
blo "50000,7300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk10MHz"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*3 (CptPort
|
|
uid 136,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 137,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "51000,5625,51750,6375"
|
|
)
|
|
tg (CPTG
|
|
uid 138,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 139,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "45700,5500,50000,6500"
|
|
st "clk50MHz"
|
|
ju 2
|
|
blo "50000,6300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk50MHz"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*4 (CptPort
|
|
uid 140,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 141,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "51000,2625,51750,3375"
|
|
)
|
|
tg (CPTG
|
|
uid 142,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 143,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "45700,2500,50000,3500"
|
|
st "clk60MHz"
|
|
ju 2
|
|
blo "50000,3300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk60MHz"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*5 (CptPort
|
|
uid 144,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 145,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "51000,4625,51750,5375"
|
|
)
|
|
tg (CPTG
|
|
uid 146,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 147,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "45700,4500,50000,5500"
|
|
st "clk75MHz"
|
|
ju 2
|
|
blo "50000,5300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "clk75MHz"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*6 (CptPort
|
|
uid 148,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 149,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,6625,39000,7375"
|
|
)
|
|
tg (CPTG
|
|
uid 150,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 151,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "40000,6500,43200,7500"
|
|
st "en10M"
|
|
blo "40000,7300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en10M"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*7 (CptPort
|
|
uid 152,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 153,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,5625,39000,6375"
|
|
)
|
|
tg (CPTG
|
|
uid 154,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 155,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "40000,5500,43200,6500"
|
|
st "en50M"
|
|
blo "40000,6300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en50M"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
*8 (CptPort
|
|
uid 156,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 157,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,4625,39000,5375"
|
|
)
|
|
tg (CPTG
|
|
uid 158,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 159,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "40000,4500,43200,5500"
|
|
st "en75M"
|
|
blo "40000,5300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "en75M"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
*9 (CptPort
|
|
uid 160,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 161,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "51000,8625,51750,9375"
|
|
)
|
|
tg (CPTG
|
|
uid 162,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 163,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "45800,8500,50000,9500"
|
|
st "pllLocked"
|
|
ju 2
|
|
blo "50000,9300"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 1
|
|
decl (Decl
|
|
n "pllLocked"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 9,0
|
|
)
|
|
)
|
|
)
|
|
*10 (CptPort
|
|
uid 164,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 165,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "38250,2625,39000,3375"
|
|
)
|
|
tg (CPTG
|
|
uid 166,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 167,0
|
|
va (VaSet
|
|
font "Verdana,8,0"
|
|
)
|
|
xt "40000,2500,44600,3500"
|
|
st "clkIn100M"
|
|
blo "40000,3300"
|
|
)
|
|
)
|
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tm "CptNameMgr"
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tm "InstanceNameMgr"
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va (VaSet
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blo "23000,3500"
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commentText (CommentText
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va (VaSet
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va (VaSet
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st "
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tm "HdlTextMgr"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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st "eb5"
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blo "31400,17000"
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tm "HdlTextNameMgr"
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)
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va (VaSet
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st "5"
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blo "31400,18000"
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tm "HdlTextNumberMgr"
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)
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uid 199,0
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optionalChildren [
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uid 208,0
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uid 213,0
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va (VaSet
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)
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 210,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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uid 212,0
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va (VaSet
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blo "33000,22900"
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thePort (LogicalPort
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n "in1"
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t "std_uLogic"
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)
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)
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)
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uid 214,0
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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vasetType 1
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isHidden 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
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uid 216,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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st "out1"
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blo "37750,22700"
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decl (Decl
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n "out1"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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st "Board"
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blo "34460,25700"
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tm "BdLibraryNameMgr"
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va (VaSet
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tm "CptNameMgr"
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va (VaSet
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st "I_inv1"
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tm "InstanceNameMgr"
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ga (GenericAssociation
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text (MLText
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va (VaSet
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header ""
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)
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elements [
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]
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portVis (PortSigDisplay
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sTC 0
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shape (Triangle
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ro 90
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va (VaSet
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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st "D"
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blo "45000,14500"
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)
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thePort (LogicalPort
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decl (Decl
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n "D"
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t "std_uLogic"
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)
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)
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)
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*29 (CptPort
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uid 232,0
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optionalChildren [
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ro 90
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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va (VaSet
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font "Verdana,12,0"
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)
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st "CLK"
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blo "45000,18600"
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)
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)
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thePort (LogicalPort
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decl (Decl
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n "CLK"
|
|
t "std_uLogic"
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|
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)
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)
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)
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uid 237,0
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ps "OnEdgeStrategy"
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shape (Triangle
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va (VaSet
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vasetType 1
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isHidden 1
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fg "0,65535,0"
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)
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tg (CPTG
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uid 239,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,12,0"
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)
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|
st "CLR"
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|
blo "46000,19800"
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)
|
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)
|
|
thePort (LogicalPort
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decl (Decl
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|
n "CLR"
|
|
t "std_uLogic"
|
|
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|
|
)
|
|
)
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|
*32 (CptPort
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uid 241,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 242,0
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ro 90
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va (VaSet
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vasetType 1
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isHidden 1
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fg "0,65535,0"
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)
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xt "50000,13625,50750,14375"
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)
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tg (CPTG
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uid 243,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 244,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "47200,13300,49000,14700"
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st "Q"
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|
ju 2
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|
blo "49000,14500"
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)
|
|
thePort (LogicalPort
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|
m 1
|
|
decl (Decl
|
|
n "Q"
|
|
t "std_uLogic"
|
|
o 4
|
|
)
|
|
)
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)
|
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]
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shape (Rectangle
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|
uid 220,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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|
lineColor "0,32896,0"
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|
lineWidth 2
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)
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|
xt "44000,12000,50000,20000"
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)
|
|
showPorts 0
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|
oxt "0,0,8000,10000"
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ttg (MlTextGroup
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uid 221,0
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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textVec [
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uid 222,0
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va (VaSet
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xt "48600,19700,52200,20900"
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st "Board"
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blo "48600,20700"
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tm "BdLibraryNameMgr"
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*34 (Text
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uid 223,0
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va (VaSet
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xt "48600,20700,51300,21900"
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st "DFF"
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blo "48600,21700"
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tm "CptNameMgr"
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*35 (Text
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uid 224,0
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va (VaSet
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xt "48600,21700,51600,22900"
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st "I_dff"
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blo "48600,22700"
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tm "InstanceNameMgr"
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)
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ga (GenericAssociation
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uid 225,0
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ro 90
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va (VaSet
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tg (CPTG
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tg (WTG
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declText (MLText
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uid 357,0
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va (VaSet
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declText (MLText
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uid 359,0
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va (VaSet
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declText (MLText
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|
|
"
|
|
)
|
|
)
|
|
*58 (Net
|
|
uid 364,0
|
|
decl (Decl
|
|
n "reset_N"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
declText (MLText
|
|
uid 365,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,10200,15800,11400"
|
|
st "reset_N : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*59 (Net
|
|
uid 366,0
|
|
decl (Decl
|
|
n "xOut"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 6,0
|
|
)
|
|
declText (MLText
|
|
uid 367,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,12600,15200,13800"
|
|
st "xOut : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*60 (Net
|
|
uid 368,0
|
|
decl (Decl
|
|
n "resetSynch"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 7,0
|
|
)
|
|
declText (MLText
|
|
uid 369,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,24600,21100,25800"
|
|
st "SIGNAL resetSynch : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*61 (Net
|
|
uid 370,0
|
|
decl (Decl
|
|
n "logic1"
|
|
t "std_uLogic"
|
|
o 8
|
|
suid 8,0
|
|
)
|
|
declText (MLText
|
|
uid 371,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,22200,20000,23400"
|
|
st "SIGNAL logic1 : std_uLogic
|
|
"
|
|
)
|
|
)
|
|
*62 (Net
|
|
uid 372,0
|
|
decl (Decl
|
|
n "yOut"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 9,0
|
|
)
|
|
declText (MLText
|
|
uid 373,0
|
|
va (VaSet
|
|
)
|
|
xt "2000,13800,15200,15000"
|
|
st "yOut : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*63 (Net
|
|
uid 380,0
|
|
lang 11
|
|
decl (Decl
|
|
n "clkSys"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 11,0
|
|
)
|
|
declText (MLText
|
|
uid 381,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,20600,19500,21400"
|
|
st "SIGNAL clkSys : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*64 (HdlText
|
|
uid 382,0
|
|
optionalChildren [
|
|
*65 (EmbeddedText
|
|
uid 387,0
|
|
commentText (CommentText
|
|
uid 388,0
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
uid 389,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineStyle 2
|
|
)
|
|
xt "22000,5000,31000,7000"
|
|
)
|
|
oxt "0,0,18000,5000"
|
|
text (MLText
|
|
uid 390,0
|
|
va (VaSet
|
|
)
|
|
xt "22200,5200,30400,6400"
|
|
st "
|
|
logic0 <= '0';
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 2000
|
|
visibleWidth 9000
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 383,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,32768"
|
|
)
|
|
xt "22000,4000,32000,8000"
|
|
)
|
|
oxt "0,0,8000,10000"
|
|
ttg (MlTextGroup
|
|
uid 384,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*66 (Text
|
|
uid 385,0
|
|
va (VaSet
|
|
)
|
|
xt "24400,8000,27000,9200"
|
|
st "eb6"
|
|
blo "24400,9000"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*67 (Text
|
|
uid 386,0
|
|
va (VaSet
|
|
)
|
|
xt "24400,9000,25800,10200"
|
|
st "6"
|
|
blo "24400,10000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
*68 (Net
|
|
uid 411,0
|
|
lang 11
|
|
decl (Decl
|
|
n "logic0"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 13,0
|
|
)
|
|
declText (MLText
|
|
uid 412,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,21400,19500,22200"
|
|
st "SIGNAL logic0 : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*69 (Net
|
|
uid 464,0
|
|
decl (Decl
|
|
n "resetSynch_N"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 14,0
|
|
)
|
|
declText (MLText
|
|
uid 465,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,25800,19500,26600"
|
|
st "SIGNAL resetSynch_N : std_ulogic
|
|
"
|
|
)
|
|
)
|
|
*70 (Wire
|
|
uid 312,0
|
|
shape (OrthoPolyLine
|
|
uid 313,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "26000,3000,38250,3000"
|
|
pts [
|
|
"26000,3000"
|
|
"38250,3000"
|
|
]
|
|
)
|
|
start &14
|
|
end &10
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 314,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 315,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "26000,1600,29800,3000"
|
|
st "clock"
|
|
blo "26000,2800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &55
|
|
)
|
|
*71 (Wire
|
|
uid 316,0
|
|
shape (OrthoPolyLine
|
|
uid 317,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "83750,6000,91000,6000"
|
|
pts [
|
|
"91000,6000"
|
|
"83750,6000"
|
|
]
|
|
)
|
|
start &54
|
|
end &47
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 318,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 319,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "86000,4600,89800,6000"
|
|
st "yOut"
|
|
blo "86000,5800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &62
|
|
)
|
|
*72 (Wire
|
|
uid 320,0
|
|
shape (OrthoPolyLine
|
|
uid 321,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "38000,20000,47000,22000"
|
|
pts [
|
|
"38000,22000"
|
|
"47000,22000"
|
|
"47000,20000"
|
|
]
|
|
)
|
|
start &23
|
|
end &31
|
|
ss 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 322,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 323,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "39000,20600,43100,22000"
|
|
st "reset"
|
|
blo "39000,21800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &57
|
|
)
|
|
*73 (Wire
|
|
uid 324,0
|
|
shape (OrthoPolyLine
|
|
uid 325,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "83750,10000,91000,10000"
|
|
pts [
|
|
"91000,10000"
|
|
"83750,10000"
|
|
]
|
|
)
|
|
start &52
|
|
end &45
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 326,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 327,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "86000,8600,94100,10000"
|
|
st "triggerOut"
|
|
blo "86000,9800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &56
|
|
)
|
|
*74 (Wire
|
|
uid 328,0
|
|
shape (OrthoPolyLine
|
|
uid 329,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "42000,18000,44000,18000"
|
|
pts [
|
|
"42000,18000"
|
|
"44000,18000"
|
|
]
|
|
)
|
|
end &29
|
|
sat 16
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 332,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 333,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "40000,16600,43800,18000"
|
|
st "clock"
|
|
blo "40000,17800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &55
|
|
)
|
|
*75 (Wire
|
|
uid 334,0
|
|
shape (OrthoPolyLine
|
|
uid 335,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "50000,14000,54092,14000"
|
|
pts [
|
|
"50000,14000"
|
|
"54092,14000"
|
|
]
|
|
)
|
|
start &32
|
|
end &37
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 336,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 337,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "49000,12600,59300,14000"
|
|
st "resetSynch_N"
|
|
blo "49000,13800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &69
|
|
)
|
|
*76 (Wire
|
|
uid 338,0
|
|
shape (OrthoPolyLine
|
|
uid 339,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "39000,14000,44000,14000"
|
|
pts [
|
|
"44000,14000"
|
|
"39000,14000"
|
|
]
|
|
)
|
|
start &28
|
|
end &16
|
|
sat 32
|
|
eat 2
|
|
stc 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 342,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 343,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "40000,12600,44400,14000"
|
|
st "logic1"
|
|
blo "40000,13800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &61
|
|
)
|
|
*77 (Wire
|
|
uid 344,0
|
|
shape (OrthoPolyLine
|
|
uid 345,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "83750,8000,91000,8000"
|
|
pts [
|
|
"91000,8000"
|
|
"83750,8000"
|
|
]
|
|
)
|
|
start &53
|
|
end &46
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 346,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 347,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "86000,6600,89800,8000"
|
|
st "xOut"
|
|
blo "86000,7800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &59
|
|
)
|
|
*78 (Wire
|
|
uid 348,0
|
|
shape (OrthoPolyLine
|
|
uid 349,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "27000,22000,32092,22000"
|
|
pts [
|
|
"27000,22000"
|
|
"32092,22000"
|
|
]
|
|
)
|
|
start &15
|
|
end &21
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 350,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 351,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "26000,20600,31800,22000"
|
|
st "reset_N"
|
|
blo "26000,21800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &58
|
|
)
|
|
*79 (Wire
|
|
uid 352,0
|
|
shape (OrthoPolyLine
|
|
uid 353,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "60000,12000,66250,14000"
|
|
pts [
|
|
"60000,14000"
|
|
"63000,14000"
|
|
"63000,12000"
|
|
"66250,12000"
|
|
]
|
|
)
|
|
start &39
|
|
end &48
|
|
ss 0
|
|
sat 32
|
|
eat 32
|
|
stc 0
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 354,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 355,0
|
|
va (VaSet
|
|
font "Verdana,12,0"
|
|
)
|
|
xt "60000,10600,68600,12000"
|
|
st "resetSynch"
|
|
blo "60000,11800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &60
|
|
)
|
|
*80 (Wire
|
|
uid 376,0
|
|
shape (OrthoPolyLine
|
|
uid 377,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "51750,3000,66250,10000"
|
|
pts [
|
|
"51750,3000"
|
|
"63000,3000"
|
|
"63000,10000"
|
|
"66250,10000"
|
|
]
|
|
)
|
|
start &4
|
|
end &44
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
uid 378,0
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
uid 379,0
|
|
va (VaSet
|
|
)
|
|
xt "53750,1800,57850,3000"
|
|
st "clkSys"
|
|
blo "53750,2800"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
on &63
|
|
)
|
|
*81 (Wire
|
|
uid 393,0
|
|
optionalChildren [
|
|
*82 (BdJunction
|
|
uid 403,0
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
uid 404,0
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "33600,4600,34400,5400"
|
|
radius 400
|
|
)
|
|
)
|
|
]
|
|
shape (OrthoPolyLine
|
|
uid 394,0
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
xt "32000,5000,38250,5000"
|
|
pts [
|
|
"32000,5000"
|
|
"38250,5000"
|
|
]
|
|
)
|
|
start &64
|
|
end &8
|
|
sat 2
|
|
eat 32
|
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sf 1
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si 0
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tg (WTG
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uid 397,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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blo "35000,4800"
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tm "WireNameMgr"
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)
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)
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on &68
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)
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*83 (Wire
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uid 399,0
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*84 (BdJunction
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uid 409,0
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ps "OnConnectorStrategy"
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va (VaSet
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)
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start &6
|
|
end &82
|
|
sat 32
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eat 32
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st 0
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sf 1
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si 0
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tg (WTG
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uid 401,0
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stg "STSignalDisplayStrategy"
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blo "32250,6800"
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tm "WireNameMgr"
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)
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)
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on &68
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va (VaSet
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start &7
|
|
end &84
|
|
sat 32
|
|
eat 32
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|
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st 0
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sf 1
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si 0
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tg (WTG
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uid 407,0
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ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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blo "32250,5800"
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tm "WireNameMgr"
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on &68
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|
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blo "0,1000"
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uid 43,0
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tm "PackageList"
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compDirBlock (MlTextGroup
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uid 44,0
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stg "VerticalLayoutStrategy"
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uid 45,0
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font "Verdana,9,1"
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)
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uid 46,0
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font "Verdana,9,1"
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uid 47,0
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tm "BdCompilerDirectivesTextMgr"
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font "Verdana,9,1"
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uid 49,0
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tm "BdCompilerDirectivesTextMgr"
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uid 50,0
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font "Verdana,9,1"
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uid 51,0
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tm "BdCompilerDirectivesTextMgr"
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windowsPaperName "A4 (210 x 297 mm)"
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windowsPaperType 9
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exportedDirectories [
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tm "CommentText"
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st "
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tm "RequirementText"
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ps "TopLeftStrategy"
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text (Text
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tm "PanelText"
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va (VaSet
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|
ps "EdgeToEdgeStrategy"
|
|
matrix (Matrix
|
|
text (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "-8150,1200,-8150,1200"
|
|
)
|
|
header ""
|
|
)
|
|
elements [
|
|
]
|
|
)
|
|
entityPath ""
|
|
)
|
|
defaultHdlText (HdlText
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,37120"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,8000,10000"
|
|
)
|
|
ttg (MlTextGroup
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*111 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "2800,3800,5200,5000"
|
|
st "eb1"
|
|
blo "2800,4800"
|
|
tm "HdlTextNameMgr"
|
|
)
|
|
*112 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "2800,5000,4000,6200"
|
|
st "1"
|
|
blo "2800,6000"
|
|
tm "HdlTextNumberMgr"
|
|
)
|
|
]
|
|
)
|
|
viewicon (ZoomableIcon
|
|
sl 0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "49152,49152,49152"
|
|
)
|
|
xt "0,0,1500,1500"
|
|
iconName "UnknownFile.png"
|
|
iconMaskName "UnknownFile.msk"
|
|
)
|
|
viewiconposition 0
|
|
)
|
|
defaultEmbeddedText (EmbeddedText
|
|
commentText (CommentText
|
|
ps "CenterOffsetStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,18000,5000"
|
|
)
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "200,200,3200,1400"
|
|
st "
|
|
Text
|
|
"
|
|
tm "HdlTextMgr"
|
|
wrapOption 3
|
|
visibleHeight 4600
|
|
visibleWidth 17600
|
|
)
|
|
)
|
|
)
|
|
defaultGlobalConnector (GlobalConnector
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,0"
|
|
)
|
|
xt "-1000,-1000,1000,1000"
|
|
radius 1000
|
|
)
|
|
name (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "-650,-600,650,600"
|
|
st "G"
|
|
blo "-650,400"
|
|
)
|
|
)
|
|
defaultRipper (Ripper
|
|
ps "OnConnectorStrategy"
|
|
shape (Line2D
|
|
pts [
|
|
"0,0"
|
|
"1000,1000"
|
|
]
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "0,0,1000,1000"
|
|
)
|
|
)
|
|
defaultBdJunction (BdJunction
|
|
ps "OnConnectorStrategy"
|
|
shape (Circle
|
|
va (VaSet
|
|
vasetType 1
|
|
)
|
|
xt "-400,-400,400,400"
|
|
radius 400
|
|
)
|
|
)
|
|
defaultPortIoIn (PortIoIn
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "-2000,-375,-500,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "-500,0,0,0"
|
|
pts [
|
|
"-500,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "-1375,-1000,-1375,-1000"
|
|
ju 2
|
|
blo "-1375,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoOut (PortIoOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Pentagon
|
|
sl 0
|
|
ro 270
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
ro 270
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "625,-1000,625,-1000"
|
|
blo "625,-1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoInOut (PortIoInOut
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultPortIoBuffer (PortIoBuffer
|
|
shape (CompositeShape
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
)
|
|
optionalChildren [
|
|
(Hexagon
|
|
sl 0
|
|
xt "500,-375,2000,375"
|
|
)
|
|
(Line
|
|
sl 0
|
|
xt "0,0,500,0"
|
|
pts [
|
|
"0,0"
|
|
"500,0"
|
|
]
|
|
)
|
|
]
|
|
)
|
|
stc 0
|
|
sf 1
|
|
tg (WTG
|
|
ps "PortIoTextPlaceStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,-375,0,-375"
|
|
blo "0,-375"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultSignal (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,2900,1200"
|
|
st "sig0"
|
|
blo "0,1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBus (Wire
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
sty 1
|
|
st 0
|
|
sf 1
|
|
si 0
|
|
tg (WTG
|
|
ps "ConnStartEndStrategy"
|
|
stg "STSignalDisplayStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,3800,1200"
|
|
st "dbus0"
|
|
blo "0,1000"
|
|
tm "WireNameMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultBundle (Bundle
|
|
shape (OrthoPolyLine
|
|
va (VaSet
|
|
vasetType 3
|
|
lineColor "32768,0,0"
|
|
lineWidth 2
|
|
)
|
|
pts [
|
|
"0,0"
|
|
"0,0"
|
|
]
|
|
)
|
|
ss 0
|
|
es 0
|
|
sat 32
|
|
eat 32
|
|
textGroup (BiTextGroup
|
|
ps "ConnStartEndStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,0,4700,1200"
|
|
st "bundle0"
|
|
blo "0,1000"
|
|
tm "BundleNameMgr"
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,1200,1500,2400"
|
|
st "()"
|
|
tm "BundleContentsMgr"
|
|
)
|
|
)
|
|
bundleNet &0
|
|
)
|
|
defaultPortMapFrame (PortMapFrame
|
|
ps "PortMapFrameStrategy"
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "0,0,32768"
|
|
lineWidth 2
|
|
)
|
|
xt "0,0,10000,12000"
|
|
)
|
|
portMapText (BiTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (MLText
|
|
va (VaSet
|
|
)
|
|
)
|
|
second (MLText
|
|
va (VaSet
|
|
)
|
|
tm "PortMapTextMgr"
|
|
)
|
|
)
|
|
)
|
|
defaultGenFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 2
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1300,18500,-100"
|
|
st "g0: FOR i IN 0 TO n GENERATE"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1850,1650"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "250,250,1650,1450"
|
|
st "1"
|
|
blo "250,1250"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*113 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11200,20000,22000,21200"
|
|
st "Frame Declarations"
|
|
blo "11200,21000"
|
|
)
|
|
*114 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11200,21200,11200,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
)
|
|
defaultBlockFrame (Frame
|
|
shape (RectFrame
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
lineColor "26368,26368,26368"
|
|
lineStyle 1
|
|
lineWidth 3
|
|
)
|
|
xt "0,0,20000,20000"
|
|
)
|
|
title (TextAssociate
|
|
ps "TopLeftStrategy"
|
|
text (MLText
|
|
va (VaSet
|
|
)
|
|
xt "0,-1300,11000,-100"
|
|
st "b0: BLOCK (guard)"
|
|
tm "FrameTitleTextMgr"
|
|
)
|
|
)
|
|
seqNum (FrameSequenceNumber
|
|
ps "TopLeftStrategy"
|
|
shape (Rectangle
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "50,50,1850,1650"
|
|
)
|
|
num (Text
|
|
va (VaSet
|
|
)
|
|
xt "250,250,1650,1450"
|
|
st "1"
|
|
blo "250,1250"
|
|
tm "FrameSeqNumMgr"
|
|
)
|
|
)
|
|
decls (MlTextGroup
|
|
ps "BottomRightOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
textVec [
|
|
*115 (Text
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "11200,20000,22000,21200"
|
|
st "Frame Declarations"
|
|
blo "11200,21000"
|
|
)
|
|
*116 (MLText
|
|
va (VaSet
|
|
)
|
|
xt "11200,21200,11200,21200"
|
|
tm "BdFrameDeclTextMgr"
|
|
)
|
|
]
|
|
)
|
|
style 3
|
|
)
|
|
defaultSaCptPort (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultSaCptPortBuffer (CptPort
|
|
ps "OnEdgeStrategy"
|
|
shape (Diamond
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "65535,65535,65535"
|
|
)
|
|
xt "0,0,750,750"
|
|
)
|
|
tg (CPTG
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
va (VaSet
|
|
)
|
|
xt "0,750,2800,1950"
|
|
st "Port"
|
|
blo "0,1750"
|
|
)
|
|
)
|
|
thePort (LogicalPort
|
|
lang 11
|
|
m 3
|
|
decl (Decl
|
|
n "Port"
|
|
t ""
|
|
o 0
|
|
)
|
|
)
|
|
)
|
|
defaultDeclText (MLText
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
)
|
|
archDeclarativeBlock (BdArchDeclBlock
|
|
uid 1,0
|
|
stg "BdArchDeclBlockLS"
|
|
declLabel (Text
|
|
uid 2,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,6600,7400,7800"
|
|
st "Declarations"
|
|
blo "0,7600"
|
|
)
|
|
portLabel (Text
|
|
uid 3,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,7800,3700,9000"
|
|
st "Ports:"
|
|
blo "0,8800"
|
|
)
|
|
preUserLabel (Text
|
|
uid 4,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,15000,5200,16200"
|
|
st "Pre User:"
|
|
blo "0,16000"
|
|
)
|
|
preUserText (MLText
|
|
uid 5,0
|
|
va (VaSet
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "2000,16200,22000,19400"
|
|
st "constant signalBitNb: positive := 16;
|
|
constant phaseBitNb: positive := 17;
|
|
constant stepX: positive := 3;
|
|
constant stepY: positive := 4;"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
diagSignalLabel (Text
|
|
uid 6,0
|
|
va (VaSet
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,19400,9500,20600"
|
|
st "Diagram Signals:"
|
|
blo "0,20400"
|
|
)
|
|
postUserLabel (Text
|
|
uid 7,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Verdana,9,1"
|
|
)
|
|
xt "0,6600,6400,7800"
|
|
st "Post User:"
|
|
blo "0,7600"
|
|
)
|
|
postUserText (MLText
|
|
uid 8,0
|
|
va (VaSet
|
|
isHidden 1
|
|
font "Courier New,8,0"
|
|
)
|
|
xt "0,6600,0,6600"
|
|
tm "BdDeclarativeTextMgr"
|
|
)
|
|
)
|
|
commonDM (CommonDM
|
|
ldm (LogicalDM
|
|
suid 14,0
|
|
usingSuid 1
|
|
emptyRow *117 (LEmptyRow
|
|
)
|
|
uid 54,0
|
|
optionalChildren [
|
|
*118 (RefLabelRowHdr
|
|
)
|
|
*119 (TitleRowHdr
|
|
)
|
|
*120 (FilterRowHdr
|
|
)
|
|
*121 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*122 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*123 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*124 (NameColHdr
|
|
tm "BlockDiagramNameColHdrMgr"
|
|
)
|
|
*125 (ModeColHdr
|
|
tm "BlockDiagramModeColHdrMgr"
|
|
)
|
|
*126 (TypeColHdr
|
|
tm "BlockDiagramTypeColHdrMgr"
|
|
)
|
|
*127 (BoundsColHdr
|
|
tm "BlockDiagramBoundsColHdrMgr"
|
|
)
|
|
*128 (InitColHdr
|
|
tm "BlockDiagramInitColHdrMgr"
|
|
)
|
|
*129 (EolColHdr
|
|
tm "BlockDiagramEolColHdrMgr"
|
|
)
|
|
*130 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 413,0
|
|
)
|
|
*131 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "triggerOut"
|
|
t "std_ulogic"
|
|
o 2
|
|
suid 2,0
|
|
)
|
|
)
|
|
uid 415,0
|
|
)
|
|
*132 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 417,0
|
|
)
|
|
*133 (LeafLogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "reset_N"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
uid 421,0
|
|
)
|
|
*134 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "xOut"
|
|
t "std_ulogic"
|
|
o 6
|
|
suid 6,0
|
|
)
|
|
)
|
|
uid 423,0
|
|
)
|
|
*135 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSynch"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 7,0
|
|
)
|
|
)
|
|
uid 425,0
|
|
)
|
|
*136 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "logic1"
|
|
t "std_uLogic"
|
|
o 8
|
|
suid 8,0
|
|
)
|
|
)
|
|
uid 427,0
|
|
)
|
|
*137 (LeafLogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "yOut"
|
|
t "std_ulogic"
|
|
o 9
|
|
suid 9,0
|
|
)
|
|
)
|
|
uid 429,0
|
|
)
|
|
*138 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 4
|
|
decl (Decl
|
|
n "clkSys"
|
|
t "std_ulogic"
|
|
o 10
|
|
suid 11,0
|
|
)
|
|
)
|
|
uid 431,0
|
|
)
|
|
*139 (LeafLogPort
|
|
port (LogicalPort
|
|
lang 11
|
|
m 4
|
|
decl (Decl
|
|
n "logic0"
|
|
t "std_ulogic"
|
|
o 11
|
|
suid 13,0
|
|
)
|
|
)
|
|
uid 433,0
|
|
)
|
|
*140 (LeafLogPort
|
|
port (LogicalPort
|
|
m 4
|
|
decl (Decl
|
|
n "resetSynch_N"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 14,0
|
|
)
|
|
)
|
|
uid 466,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 67,0
|
|
optionalChildren [
|
|
*141 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *142 (MRCItem
|
|
litem &117
|
|
pos 11
|
|
dimension 20
|
|
)
|
|
uid 69,0
|
|
optionalChildren [
|
|
*143 (MRCItem
|
|
litem &118
|
|
pos 0
|
|
dimension 20
|
|
uid 70,0
|
|
)
|
|
*144 (MRCItem
|
|
litem &119
|
|
pos 1
|
|
dimension 23
|
|
uid 71,0
|
|
)
|
|
*145 (MRCItem
|
|
litem &120
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 72,0
|
|
)
|
|
*146 (MRCItem
|
|
litem &130
|
|
pos 0
|
|
dimension 20
|
|
uid 414,0
|
|
)
|
|
*147 (MRCItem
|
|
litem &131
|
|
pos 1
|
|
dimension 20
|
|
uid 416,0
|
|
)
|
|
*148 (MRCItem
|
|
litem &132
|
|
pos 2
|
|
dimension 20
|
|
uid 418,0
|
|
)
|
|
*149 (MRCItem
|
|
litem &133
|
|
pos 3
|
|
dimension 20
|
|
uid 422,0
|
|
)
|
|
*150 (MRCItem
|
|
litem &134
|
|
pos 4
|
|
dimension 20
|
|
uid 424,0
|
|
)
|
|
*151 (MRCItem
|
|
litem &135
|
|
pos 5
|
|
dimension 20
|
|
uid 426,0
|
|
)
|
|
*152 (MRCItem
|
|
litem &136
|
|
pos 6
|
|
dimension 20
|
|
uid 428,0
|
|
)
|
|
*153 (MRCItem
|
|
litem &137
|
|
pos 7
|
|
dimension 20
|
|
uid 430,0
|
|
)
|
|
*154 (MRCItem
|
|
litem &138
|
|
pos 8
|
|
dimension 20
|
|
uid 432,0
|
|
)
|
|
*155 (MRCItem
|
|
litem &139
|
|
pos 9
|
|
dimension 20
|
|
uid 434,0
|
|
)
|
|
*156 (MRCItem
|
|
litem &140
|
|
pos 10
|
|
dimension 20
|
|
uid 467,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 73,0
|
|
optionalChildren [
|
|
*157 (MRCItem
|
|
litem &121
|
|
pos 0
|
|
dimension 20
|
|
uid 74,0
|
|
)
|
|
*158 (MRCItem
|
|
litem &123
|
|
pos 1
|
|
dimension 50
|
|
uid 75,0
|
|
)
|
|
*159 (MRCItem
|
|
litem &124
|
|
pos 2
|
|
dimension 100
|
|
uid 76,0
|
|
)
|
|
*160 (MRCItem
|
|
litem &125
|
|
pos 3
|
|
dimension 50
|
|
uid 77,0
|
|
)
|
|
*161 (MRCItem
|
|
litem &126
|
|
pos 4
|
|
dimension 100
|
|
uid 78,0
|
|
)
|
|
*162 (MRCItem
|
|
litem &127
|
|
pos 5
|
|
dimension 100
|
|
uid 79,0
|
|
)
|
|
*163 (MRCItem
|
|
litem &128
|
|
pos 6
|
|
dimension 50
|
|
uid 80,0
|
|
)
|
|
*164 (MRCItem
|
|
litem &129
|
|
pos 7
|
|
dimension 80
|
|
uid 81,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 68,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 53,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *165 (LEmptyRow
|
|
)
|
|
uid 83,0
|
|
optionalChildren [
|
|
*166 (RefLabelRowHdr
|
|
)
|
|
*167 (TitleRowHdr
|
|
)
|
|
*168 (FilterRowHdr
|
|
)
|
|
*169 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*170 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*171 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*172 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*173 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*174 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*175 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*176 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 95,0
|
|
optionalChildren [
|
|
*177 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *178 (MRCItem
|
|
litem &165
|
|
pos 0
|
|
dimension 20
|
|
)
|
|
uid 97,0
|
|
optionalChildren [
|
|
*179 (MRCItem
|
|
litem &166
|
|
pos 0
|
|
dimension 20
|
|
uid 98,0
|
|
)
|
|
*180 (MRCItem
|
|
litem &167
|
|
pos 1
|
|
dimension 23
|
|
uid 99,0
|
|
)
|
|
*181 (MRCItem
|
|
litem &168
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 100,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 101,0
|
|
optionalChildren [
|
|
*182 (MRCItem
|
|
litem &169
|
|
pos 0
|
|
dimension 20
|
|
uid 102,0
|
|
)
|
|
*183 (MRCItem
|
|
litem &171
|
|
pos 1
|
|
dimension 50
|
|
uid 103,0
|
|
)
|
|
*184 (MRCItem
|
|
litem &172
|
|
pos 2
|
|
dimension 100
|
|
uid 104,0
|
|
)
|
|
*185 (MRCItem
|
|
litem &173
|
|
pos 3
|
|
dimension 100
|
|
uid 105,0
|
|
)
|
|
*186 (MRCItem
|
|
litem &174
|
|
pos 4
|
|
dimension 50
|
|
uid 106,0
|
|
)
|
|
*187 (MRCItem
|
|
litem &175
|
|
pos 5
|
|
dimension 50
|
|
uid 107,0
|
|
)
|
|
*188 (MRCItem
|
|
litem &176
|
|
pos 6
|
|
dimension 80
|
|
uid 108,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 96,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 82,0
|
|
type 1
|
|
)
|
|
activeModelName "BlockDiag"
|
|
)
|