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SEm-Labos/zz-solutions/04-Lissajous/Board/hds/lissajous@generator_circuit_@e@b@s3/master@version.bd
2024-03-15 15:03:34 +01:00

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51 KiB
Plaintext

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
]
instances [
(Instance
name "U_pll"
duLibraryName "Lattice"
duName "pll"
elements [
]
mwi 0
uid 168,0
)
(Instance
name "I_inv1"
duLibraryName "Board"
duName "inverterIn"
elements [
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mwi 0
uid 199,0
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(Instance
name "I_dff"
duLibraryName "Board"
duName "DFF"
elements [
]
mwi 0
uid 219,0
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(Instance
name "I_inv2"
duLibraryName "Board"
duName "inverterIn"
elements [
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mwi 0
uid 245,0
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(Instance
name "I_main"
duLibraryName "Lissajous"
duName "lissajousGenerator"
elements [
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name "signalBitNb"
type "positive"
value "signalBitNb"
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(GiElement
name "phaseBitNb"
type "positive"
value "phaseBitNb"
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(GiElement
name "stepX"
type "positive"
value "stepX"
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mwi 0
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embeddedInstances [
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name "eb5"
number "5"
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name "eb6"
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libraryRefs [
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version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
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vvMap [
(vvPair
variable "HDLDir"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3\\master@version.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3\\master@version.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "masterVersion"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3"
)
(vvPair
variable "d_logical"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajousGenerator_circuit_EBS3"
)
(vvPair
variable "date"
value "01.05.2023"
)
(vvPair
variable "day"
value "lun."
)
(vvPair
variable "day_long"
value "lundi"
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(vvPair
variable "dd"
value "01"
)
(vvPair
variable "entity_name"
value "lissajousGenerator_circuit_EBS3"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "master@version.bd"
)
(vvPair
variable "f_logical"
value "masterVersion.bd"
)
(vvPair
variable "f_noext"
value "master@version"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
)
(vvPair
variable "graphical_source_date"
value "01.05.2023"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
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(vvPair
variable "graphical_source_host"
value "WE7860"
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(vvPair
variable "graphical_source_time"
value "17:45:49"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Board"
)
(vvPair
variable "library_downstream_Concatenation"
value "$HDS_PROJECT_DIR/../Board/concat"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Board"
)
(vvPair
variable "mm"
value "05"
)
(vvPair
variable "module_name"
value "lissajousGenerator_circuit_EBS3"
)
(vvPair
variable "month"
value "mai"
)
(vvPair
variable "month_long"
value "mai"
)
(vvPair
variable "p"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajous@generator_circuit_@e@b@s3\\master@version.bd"
)
(vvPair
variable "p_logical"
value "C:\\dev\\sem-labs\\04-Lissajous\\Prefs\\..\\Board\\hds\\lissajousGenerator_circuit_EBS3\\masterVersion.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "master@version"
)
(vvPair
variable "this_file_logical"
value "masterVersion"
)
(vvPair
variable "time"
value "17:45:49"
)
(vvPair
variable "unit"
value "lissajousGenerator_circuit_EBS3"
)
(vvPair
variable "user"
value "axel.amand"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "masterVersion"
)
(vvPair
variable "year"
value "2023"
)
(vvPair
variable "yy"
value "23"
)
]
)
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*32 (CptPort
uid 241,0
ps "OnEdgeStrategy"
shape (Triangle
uid 242,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "50000,13625,50750,14375"
)
tg (CPTG
uid 243,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 244,0
va (VaSet
font "Verdana,12,0"
)
xt "47200,13300,49000,14700"
st "Q"
ju 2
blo "49000,14500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 220,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "44000,12000,50000,20000"
)
showPorts 0
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 221,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*33 (Text
uid 222,0
va (VaSet
)
xt "48600,19700,52200,20900"
st "Board"
blo "48600,20700"
tm "BdLibraryNameMgr"
)
*34 (Text
uid 223,0
va (VaSet
)
xt "48600,20700,51300,21900"
st "DFF"
blo "48600,21700"
tm "CptNameMgr"
)
*35 (Text
uid 224,0
va (VaSet
)
xt "48600,21700,51600,22900"
st "I_dff"
blo "48600,22700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 225,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 226,0
text (MLText
uid 227,0
va (VaSet
)
xt "21000,9000,21000,9000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*36 (SaComponent
uid 245,0
optionalChildren [
*37 (CptPort
uid 254,0
optionalChildren [
*38 (Circle
uid 259,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "54092,13546,55000,14454"
radius 454
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 255,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "53342,13625,54092,14375"
)
tg (CPTG
uid 256,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 257,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "55000,13500,57700,14900"
st "in1"
blo "55000,14700"
)
s (Text
uid 258,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "55000,14900,55000,14900"
blo "55000,14900"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*39 (CptPort
uid 260,0
ps "OnEdgeStrategy"
shape (Triangle
uid 261,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "60000,13625,60750,14375"
)
tg (CPTG
uid 262,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 263,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "56050,13500,59750,14900"
st "out1"
ju 2
blo "59750,14700"
)
s (Text
uid 264,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "59750,14900,59750,14900"
ju 2
blo "59750,14900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 246,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "55000,11000,60000,17000"
)
showPorts 0
oxt "23000,4000,28000,10000"
ttg (MlTextGroup
uid 247,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*40 (Text
uid 248,0
va (VaSet
)
xt "56460,16700,60060,17900"
st "Board"
blo "56460,17700"
tm "BdLibraryNameMgr"
)
*41 (Text
uid 249,0
va (VaSet
)
xt "56460,17700,62860,18900"
st "inverterIn"
blo "56460,18700"
tm "CptNameMgr"
)
*42 (Text
uid 250,0
va (VaSet
)
xt "56460,18700,60460,19900"
st "I_inv2"
blo "56460,19700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 251,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 252,0
text (MLText
uid 253,0
va (VaSet
)
xt "55000,17400,55000,17400"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*43 (SaComponent
uid 265,0
optionalChildren [
*44 (CptPort
uid 274,0
ps "OnEdgeStrategy"
shape (Triangle
uid 275,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66250,9625,67000,10375"
)
tg (CPTG
uid 276,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 277,0
va (VaSet
)
xt "68000,9400,71400,10600"
st "clock"
blo "68000,10400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
)
)
)
*45 (CptPort
uid 278,0
ps "OnEdgeStrategy"
shape (Triangle
uid 279,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "83000,9625,83750,10375"
)
tg (CPTG
uid 280,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 281,0
va (VaSet
)
xt "75400,9400,82000,10600"
st "triggerOut"
ju 2
blo "82000,10400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "triggerOut"
t "std_ulogic"
o 3
)
)
)
*46 (CptPort
uid 282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "83000,7625,83750,8375"
)
tg (CPTG
uid 284,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 285,0
va (VaSet
)
xt "78800,7400,82000,8600"
st "xOut"
ju 2
blo "82000,8400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "xOut"
t "std_ulogic"
o 4
)
)
)
*47 (CptPort
uid 286,0
ps "OnEdgeStrategy"
shape (Triangle
uid 287,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "83000,5625,83750,6375"
)
tg (CPTG
uid 288,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 289,0
va (VaSet
)
xt "78800,5400,82000,6600"
st "yOut"
ju 2
blo "82000,6400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "yOut"
t "std_ulogic"
o 5
)
)
)
*48 (CptPort
uid 290,0
ps "OnEdgeStrategy"
shape (Triangle
uid 291,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "66250,11625,67000,12375"
)
tg (CPTG
uid 292,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 293,0
va (VaSet
)
xt "68000,11500,71300,12700"
st "reset"
blo "68000,12500"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 2
)
)
)
]
shape (Rectangle
uid 266,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "67000,2000,83000,14000"
)
oxt "32000,10000,48000,22000"
ttg (MlTextGroup
uid 267,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*49 (Text
uid 268,0
va (VaSet
font "Verdana,9,1"
)
xt "67600,13800,72800,15000"
st "Lissajous"
blo "67600,14800"
tm "BdLibraryNameMgr"
)
*50 (Text
uid 269,0
va (VaSet
font "Verdana,9,1"
)
xt "67600,14700,78100,15900"
st "lissajousGenerator"
blo "67600,15700"
tm "CptNameMgr"
)
*51 (Text
uid 270,0
va (VaSet
font "Verdana,9,1"
)
xt "67600,15600,71700,16800"
st "I_main"
blo "67600,16600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 271,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 272,0
text (MLText
uid 273,0
va (VaSet
)
xt "67000,17600,90500,22400"
st "signalBitNb = signalBitNb ( positive )
phaseBitNb = phaseBitNb ( positive )
stepX = stepX ( positive )
stepY = stepY ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "phaseBitNb"
type "positive"
value "phaseBitNb"
)
(GiElement
name "stepX"
type "positive"
value "stepX"
)
(GiElement
name "stepY"
type "positive"
value "stepY"
)
]
)
connectByName 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*52 (PortIoOut
uid 294,0
shape (CompositeShape
uid 295,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 296,0
sl 0
ro 270
xt "91500,9625,93000,10375"
)
(Line
uid 297,0
sl 0
ro 270
xt "91000,10000,91500,10000"
pts [
"91000,10000"
"91500,10000"
]
)
]
)
tg (WTG
uid 298,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 299,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "94000,9300,102100,10700"
st "triggerOut"
blo "94000,10500"
tm "WireNameMgr"
)
)
)
*53 (PortIoOut
uid 300,0
shape (CompositeShape
uid 301,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 302,0
sl 0
ro 270
xt "91500,7625,93000,8375"
)
(Line
uid 303,0
sl 0
ro 270
xt "91000,8000,91500,8000"
pts [
"91000,8000"
"91500,8000"
]
)
]
)
tg (WTG
uid 304,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 305,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "94000,7300,97800,8700"
st "xOut"
blo "94000,8500"
tm "WireNameMgr"
)
)
)
*54 (PortIoOut
uid 306,0
shape (CompositeShape
uid 307,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 308,0
sl 0
ro 270
xt "91500,5625,93000,6375"
)
(Line
uid 309,0
sl 0
ro 270
xt "91000,6000,91500,6000"
pts [
"91000,6000"
"91500,6000"
]
)
]
)
tg (WTG
uid 310,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 311,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "94000,5300,97800,6700"
st "yOut"
blo "94000,6500"
tm "WireNameMgr"
)
)
)
*55 (Net
uid 356,0
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
declText (MLText
uid 357,0
va (VaSet
)
xt "2000,9000,15100,10200"
st "clock : std_ulogic
"
)
)
*56 (Net
uid 358,0
decl (Decl
n "triggerOut"
t "std_ulogic"
o 2
suid 2,0
)
declText (MLText
uid 359,0
va (VaSet
)
xt "2000,11400,16100,12600"
st "triggerOut : std_ulogic
"
)
)
*57 (Net
uid 360,0
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
declText (MLText
uid 361,0
va (VaSet
)
xt "2000,23400,19500,24600"
st "SIGNAL reset : std_ulogic
"
)
)
*58 (Net
uid 364,0
decl (Decl
n "reset_N"
t "std_ulogic"
o 5
suid 5,0
)
declText (MLText
uid 365,0
va (VaSet
)
xt "2000,10200,15800,11400"
st "reset_N : std_ulogic
"
)
)
*59 (Net
uid 366,0
decl (Decl
n "xOut"
t "std_ulogic"
o 6
suid 6,0
)
declText (MLText
uid 367,0
va (VaSet
)
xt "2000,12600,15200,13800"
st "xOut : std_ulogic
"
)
)
*60 (Net
uid 368,0
decl (Decl
n "resetSynch"
t "std_ulogic"
o 7
suid 7,0
)
declText (MLText
uid 369,0
va (VaSet
)
xt "2000,24600,21100,25800"
st "SIGNAL resetSynch : std_ulogic
"
)
)
*61 (Net
uid 370,0
decl (Decl
n "logic1"
t "std_uLogic"
o 8
suid 8,0
)
declText (MLText
uid 371,0
va (VaSet
)
xt "2000,22200,20000,23400"
st "SIGNAL logic1 : std_uLogic
"
)
)
*62 (Net
uid 372,0
decl (Decl
n "yOut"
t "std_ulogic"
o 9
suid 9,0
)
declText (MLText
uid 373,0
va (VaSet
)
xt "2000,13800,15200,15000"
st "yOut : std_ulogic
"
)
)
*63 (Net
uid 380,0
lang 11
decl (Decl
n "clkSys"
t "std_ulogic"
o 10
suid 11,0
)
declText (MLText
uid 381,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,20600,19500,21400"
st "SIGNAL clkSys : std_ulogic
"
)
)
*64 (HdlText
uid 382,0
optionalChildren [
*65 (EmbeddedText
uid 387,0
commentText (CommentText
uid 388,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 389,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "22000,5000,31000,7000"
)
oxt "0,0,18000,5000"
text (MLText
uid 390,0
va (VaSet
)
xt "22200,5200,30400,6400"
st "
logic0 <= '0';
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 9000
)
)
)
]
shape (Rectangle
uid 383,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "22000,4000,32000,8000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 384,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*66 (Text
uid 385,0
va (VaSet
)
xt "24400,8000,27000,9200"
st "eb6"
blo "24400,9000"
tm "HdlTextNameMgr"
)
*67 (Text
uid 386,0
va (VaSet
)
xt "24400,9000,25800,10200"
st "6"
blo "24400,10000"
tm "HdlTextNumberMgr"
)
]
)
)
*68 (Net
uid 411,0
lang 11
decl (Decl
n "logic0"
t "std_ulogic"
o 11
suid 13,0
)
declText (MLText
uid 412,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,21400,19500,22200"
st "SIGNAL logic0 : std_ulogic
"
)
)
*69 (Net
uid 464,0
decl (Decl
n "resetSynch_N"
t "std_ulogic"
o 4
suid 14,0
)
declText (MLText
uid 465,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,25800,19500,26600"
st "SIGNAL resetSynch_N : std_ulogic
"
)
)
*70 (Wire
uid 312,0
shape (OrthoPolyLine
uid 313,0
va (VaSet
vasetType 3
)
xt "26000,3000,38250,3000"
pts [
"26000,3000"
"38250,3000"
]
)
start &14
end &10
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 314,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 315,0
va (VaSet
font "Verdana,12,0"
)
xt "26000,1600,29800,3000"
st "clock"
blo "26000,2800"
tm "WireNameMgr"
)
)
on &55
)
*71 (Wire
uid 316,0
shape (OrthoPolyLine
uid 317,0
va (VaSet
vasetType 3
)
xt "83750,6000,91000,6000"
pts [
"91000,6000"
"83750,6000"
]
)
start &54
end &47
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 318,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 319,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,4600,89800,6000"
st "yOut"
blo "86000,5800"
tm "WireNameMgr"
)
)
on &62
)
*72 (Wire
uid 320,0
shape (OrthoPolyLine
uid 321,0
va (VaSet
vasetType 3
)
xt "38000,20000,47000,22000"
pts [
"38000,22000"
"47000,22000"
"47000,20000"
]
)
start &23
end &31
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 322,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 323,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,20600,43100,22000"
st "reset"
blo "39000,21800"
tm "WireNameMgr"
)
)
on &57
)
*73 (Wire
uid 324,0
shape (OrthoPolyLine
uid 325,0
va (VaSet
vasetType 3
)
xt "83750,10000,91000,10000"
pts [
"91000,10000"
"83750,10000"
]
)
start &52
end &45
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 326,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 327,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,8600,94100,10000"
st "triggerOut"
blo "86000,9800"
tm "WireNameMgr"
)
)
on &56
)
*74 (Wire
uid 328,0
shape (OrthoPolyLine
uid 329,0
va (VaSet
vasetType 3
)
xt "42000,18000,44000,18000"
pts [
"42000,18000"
"44000,18000"
]
)
end &29
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 332,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 333,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,16600,43800,18000"
st "clock"
blo "40000,17800"
tm "WireNameMgr"
)
)
on &55
)
*75 (Wire
uid 334,0
shape (OrthoPolyLine
uid 335,0
va (VaSet
vasetType 3
)
xt "50000,14000,54092,14000"
pts [
"50000,14000"
"54092,14000"
]
)
start &32
end &37
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 337,0
va (VaSet
font "Verdana,12,0"
)
xt "49000,12600,59300,14000"
st "resetSynch_N"
blo "49000,13800"
tm "WireNameMgr"
)
)
on &69
)
*76 (Wire
uid 338,0
shape (OrthoPolyLine
uid 339,0
va (VaSet
vasetType 3
)
xt "39000,14000,44000,14000"
pts [
"44000,14000"
"39000,14000"
]
)
start &28
end &16
sat 32
eat 2
stc 0
sf 1
si 0
tg (WTG
uid 342,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 343,0
va (VaSet
font "Verdana,12,0"
)
xt "40000,12600,44400,14000"
st "logic1"
blo "40000,13800"
tm "WireNameMgr"
)
)
on &61
)
*77 (Wire
uid 344,0
shape (OrthoPolyLine
uid 345,0
va (VaSet
vasetType 3
)
xt "83750,8000,91000,8000"
pts [
"91000,8000"
"83750,8000"
]
)
start &53
end &46
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 346,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 347,0
va (VaSet
font "Verdana,12,0"
)
xt "86000,6600,89800,8000"
st "xOut"
blo "86000,7800"
tm "WireNameMgr"
)
)
on &59
)
*78 (Wire
uid 348,0
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sat 32
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st 0
sf 1
si 0
tg (WTG
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stg "STSignalDisplayStrategy"
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va (VaSet
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blo "26000,21800"
tm "WireNameMgr"
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)
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uid 352,0
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xt "60000,12000,66250,14000"
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end &48
ss 0
sat 32
eat 32
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st 0
sf 1
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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st "resetSynch"
blo "60000,11800"
tm "WireNameMgr"
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uid 376,0
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va (VaSet
vasetType 3
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start &4
end &44
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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tm "WireNameMgr"
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ps "OnConnectorStrategy"
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start &64
end &8
sat 2
eat 32
st 0
sf 1
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 398,0
va (VaSet
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blo "35000,4800"
tm "WireNameMgr"
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on &68
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uid 399,0
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uid 409,0
ps "OnConnectorStrategy"
shape (Circle
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va (VaSet
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)
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xt "34000,5000,38250,7000"
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start &6
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sat 32
eat 32
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st 0
sf 1
si 0
tg (WTG
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stg "STSignalDisplayStrategy"
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va (VaSet
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on &68
)
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xt "34000,6000,38250,6000"
pts [
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start &7
end &84
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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tm "WireNameMgr"
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)
on &68
)
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Text
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tm "CommentText"
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)
)
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Text
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tm "RequirementText"
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shape (RectFrame
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blo "1000,2000"
tm "PanelText"
)
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xt "0,0,8000,10000"
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va (VaSet
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tm "BdLibraryNameMgr"
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blo "1300,5400"
tm "BlkNameMgr"
)
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xt "1300,5600,3800,6800"
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blo "1300,6600"
tm "InstanceNameMgr"
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xt "1300,13200,1300,13200"
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header ""
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elements [
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xt "0,0,1500,1500"
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ttg (MlTextGroup
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xt "-350,3200,3750,4400"
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va (VaSet
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blo "-350,5400"
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va (VaSet
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xt "-350,5600,2150,6800"
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tm "InstanceNameMgr"
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xt "-7350,1200,-7350,1200"
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header ""
)
elements [
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)
prms (Property
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pname "params"
ptn "String"
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visOptions (mwParamsVisibilityOptions
)
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ttg (MlTextGroup
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tm "CptNameMgr"
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tm "InstanceNameMgr"
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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xt "-7000,1200,-7000,1200"
)
header ""
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viewicon (ZoomableIcon
sl 0
va (VaSet
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xt "0,0,1500,1500"
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iconMaskName "UnknownFile.msk"
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viewiconposition 0
portVis (PortSigDisplay
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xt "-1000,0,9000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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blo "-500,5400"
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va (VaSet
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xt "-500,5600,2000,6800"
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tm "InstanceNameMgr"
)
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)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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xt "-7500,1200,-7500,1200"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
)
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archName ""
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)
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va (VaSet
vasetType 1
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lineColor "0,32896,0"
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xt "-1650,0,9650,10000"
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ttg (MlTextGroup
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blo "-1150,4200"
)
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va (VaSet
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blo "-1150,5400"
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va (VaSet
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xt "-1150,5600,1350,6800"
st "U_0"
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tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
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xt "-8150,1200,-8150,1200"
)
header ""
)
elements [
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)
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defaultHdlText (HdlText
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va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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)
xt "2800,3800,5200,5000"
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tm "HdlTextNameMgr"
)
*112 (Text
va (VaSet
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)
xt "2800,5000,4000,6200"
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blo "2800,6000"
tm "HdlTextNumberMgr"
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]
)
viewicon (ZoomableIcon
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va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "0,0,1500,1500"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
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va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
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xt "0,0,18000,5000"
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text (MLText
va (VaSet
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xt "200,200,3200,1400"
st "
Text
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tm "HdlTextMgr"
wrapOption 3
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)
)
)
defaultGlobalConnector (GlobalConnector
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vasetType 1
fg "65535,65535,0"
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xt "-1000,-1000,1000,1000"
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)
name (Text
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st "G"
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ps "OnConnectorStrategy"
shape (Line2D
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]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
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vasetType 1
)
xt "-400,-400,400,400"
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)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
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fg "0,0,32768"
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ro 270
xt "-2000,-375,-500,375"
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tg (WTG
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ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
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)
defaultPortIoOut (PortIoOut
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va (VaSet
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fg "0,0,32768"
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sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
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ro 270
xt "0,0,500,0"
pts [
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)
stc 0
sf 1
tg (WTG
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va (VaSet
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xt "625,-1000,625,-1000"
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tm "WireNameMgr"
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)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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sl 0
xt "500,-375,2000,375"
)
(Line
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xt "0,0,500,0"
pts [
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]
)
stc 0
sf 1
tg (WTG
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stg "STSignalDisplayStrategy"
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xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
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)
defaultPortIoBuffer (PortIoBuffer
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va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
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xt "500,-375,2000,375"
)
(Line
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tg (WTG
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stg "STSignalDisplayStrategy"
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tm "WireNameMgr"
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shape (OrthoPolyLine
va (VaSet
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ss 0
es 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
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stg "STSignalDisplayStrategy"
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blo "0,1000"
tm "WireNameMgr"
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)
)
defaultBus (Wire
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va (VaSet
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sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
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stg "STSignalDisplayStrategy"
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ss 0
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sat 32
eat 32
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blo "0,1000"
tm "BundleNameMgr"
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tm "BundleContentsMgr"
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portMapText (BiTextGroup
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va (VaSet
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second (MLText
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tm "PortMapTextMgr"
)
)
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)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1300,11000,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1850,1650"
)
num (Text
va (VaSet
)
xt "250,250,1650,1450"
st "1"
blo "250,1250"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Verdana,9,1"
)
xt "11200,20000,22000,21200"
st "Frame Declarations"
blo "11200,21000"
)
*116 (MLText
va (VaSet
)
xt "11200,21200,11200,21200"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
lang 11
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
font "Courier New,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,9,1"
)
xt "0,6600,7400,7800"
st "Declarations"
blo "0,7600"
)
portLabel (Text
uid 3,0
va (VaSet
font "Verdana,9,1"
)
xt "0,7800,3700,9000"
st "Ports:"
blo "0,8800"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,9,1"
)
xt "0,15000,5200,16200"
st "Pre User:"
blo "0,16000"
)
preUserText (MLText
uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16200,22000,19400"
st "constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 17;
constant stepX: positive := 3;
constant stepY: positive := 4;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Verdana,9,1"
)
xt "0,19400,9500,20600"
st "Diagram Signals:"
blo "0,20400"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,9,1"
)
xt "0,6600,6400,7800"
st "Post User:"
blo "0,7600"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "0,6600,0,6600"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 14,0
usingSuid 1
emptyRow *117 (LEmptyRow
)
uid 54,0
optionalChildren [
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)
*119 (TitleRowHdr
)
*120 (FilterRowHdr
)
*121 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*122 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*123 (GroupColHdr
tm "GroupColHdrMgr"
)
*124 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*125 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*126 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*127 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*128 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*129 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*130 (LeafLogPort
port (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 1,0
)
)
uid 413,0
)
*131 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "triggerOut"
t "std_ulogic"
o 2
suid 2,0
)
)
uid 415,0
)
*132 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 3,0
)
)
uid 417,0
)
*133 (LeafLogPort
port (LogicalPort
decl (Decl
n "reset_N"
t "std_ulogic"
o 5
suid 5,0
)
)
uid 421,0
)
*134 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "xOut"
t "std_ulogic"
o 6
suid 6,0
)
)
uid 423,0
)
*135 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "resetSynch"
t "std_ulogic"
o 7
suid 7,0
)
)
uid 425,0
)
*136 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "logic1"
t "std_uLogic"
o 8
suid 8,0
)
)
uid 427,0
)
*137 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "yOut"
t "std_ulogic"
o 9
suid 9,0
)
)
uid 429,0
)
*138 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "clkSys"
t "std_ulogic"
o 10
suid 11,0
)
)
uid 431,0
)
*139 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "logic0"
t "std_ulogic"
o 11
suid 13,0
)
)
uid 433,0
)
*140 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "resetSynch_N"
t "std_ulogic"
o 4
suid 14,0
)
)
uid 466,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*141 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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emptyMRCItem *142 (MRCItem
litem &117
pos 11
dimension 20
)
uid 69,0
optionalChildren [
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uid 70,0
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dimension 23
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litem &120
pos 2
hidden 1
dimension 20
uid 72,0
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litem &130
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dimension 20
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dimension 20
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litem &132
pos 2
dimension 20
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litem &133
pos 3
dimension 20
uid 422,0
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litem &134
pos 4
dimension 20
uid 424,0
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litem &135
pos 5
dimension 20
uid 426,0
)
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litem &136
pos 6
dimension 20
uid 428,0
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litem &137
pos 7
dimension 20
uid 430,0
)
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litem &138
pos 8
dimension 20
uid 432,0
)
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litem &139
pos 9
dimension 20
uid 434,0
)
*156 (MRCItem
litem &140
pos 10
dimension 20
uid 467,0
)
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sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
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textAngle 90
)
uid 73,0
optionalChildren [
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litem &121
pos 0
dimension 20
uid 74,0
)
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litem &123
pos 1
dimension 50
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)
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litem &124
pos 2
dimension 100
uid 76,0
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pos 4
dimension 100
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litem &127
pos 5
dimension 100
uid 79,0
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litem &128
pos 6
dimension 50
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)
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litem &129
pos 7
dimension 80
uid 81,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 68,0
vaOverrides [
]
)
]
)
uid 53,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *165 (LEmptyRow
)
uid 83,0
optionalChildren [
*166 (RefLabelRowHdr
)
*167 (TitleRowHdr
)
*168 (FilterRowHdr
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*169 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*170 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*171 (GroupColHdr
tm "GroupColHdrMgr"
)
*172 (NameColHdr
tm "GenericNameColHdrMgr"
)
*173 (TypeColHdr
tm "GenericTypeColHdrMgr"
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*174 (InitColHdr
tm "GenericValueColHdrMgr"
)
*175 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*176 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 95,0
optionalChildren [
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sheetRow (SheetRow
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cellColor "49152,49152,49152"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *178 (MRCItem
litem &165
pos 0
dimension 20
)
uid 97,0
optionalChildren [
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litem &166
pos 0
dimension 20
uid 98,0
)
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litem &167
pos 1
dimension 23
uid 99,0
)
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litem &168
pos 2
hidden 1
dimension 20
uid 100,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
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uid 101,0
optionalChildren [
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litem &169
pos 0
dimension 20
uid 102,0
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litem &171
pos 1
dimension 50
uid 103,0
)
*184 (MRCItem
litem &172
pos 2
dimension 100
uid 104,0
)
*185 (MRCItem
litem &173
pos 3
dimension 100
uid 105,0
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litem &174
pos 4
dimension 50
uid 106,0
)
*187 (MRCItem
litem &175
pos 5
dimension 50
uid 107,0
)
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litem &176
pos 6
dimension 80
uid 108,0
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]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 96,0
vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)