22 lines
368 B
VHDL
22 lines
368 B
VHDL
ARCHITECTURE studentVersion OF sawtoothGen IS
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signal counter : unsigned(bitNb-1 downto 0);
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BEGIN
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count: process(clock)
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begin
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if reset = '1' then
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counter <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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counter <= counter + step;
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end if;
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end if;
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end process count;
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sawtooth <= counter;
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END ARCHITECTURE studentVersion;
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