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SEm-Labos/06-07-08-09-SystemOnChip/SystemOnChip_test/hds/ahb@beamer_tb/struct.bd
github-classroom[bot] d212040c30
Initial commit
2024-02-23 13:01:05 +00:00

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DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
(DmPackageRef
library "AhbLite"
unitName "ahbLite"
)
]
instances [
(Instance
name "I_tester"
duLibraryName "SystemOnChip_test"
duName "ahbBeamer_tester"
elements [
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "clockFrequency"
type "real"
value "clockFrequency"
)
]
mwi 0
uid 12657,0
)
(Instance
name "I_filt"
duLibraryName "WaveformGenerator"
duName "lowpass"
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "shiftBitNb"
type "positive"
value "lowpassShiftBitNb"
)
]
mwi 0
uid 13849,0
)
(Instance
name "I_DUT"
duLibraryName "SystemOnChip"
duName "ahbBeamer"
elements [
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "testOutBitNb"
type "positive"
value "testOutBitNb"
)
]
mwi 0
uid 14527,0
)
]
embeddedInstances [
(EmbeddedInstance
name "eb2"
number "2"
)
]
libraryRefs [
"ieee"
"AhbLite"
]
)
version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "asm_file"
value "beamer.asm"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb"
)
(vvPair
variable "d_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahbBeamer_tb"
)
(vvPair
variable "date"
value "28.04.2023"
)
(vvPair
variable "day"
value "ven."
)
(vvPair
variable "day_long"
value "vendredi"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "designName"
value "$DESIGN_NAME"
)
(vvPair
variable "entity_name"
value "ahbBeamer_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "axel.amand"
)
(vvPair
variable "graphical_source_date"
value "28.04.2023"
)
(vvPair
variable "graphical_source_group"
value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE7860"
)
(vvPair
variable "graphical_source_time"
value "15:04:15"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE7860"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "SystemOnChip_test"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/SystemOnChip_test"
)
(vvPair
variable "mm"
value "04"
)
(vvPair
variable "module_name"
value "ahbBeamer_tb"
)
(vvPair
variable "month"
value "avr."
)
(vvPair
variable "month_long"
value "avril"
)
(vvPair
variable "p"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahb@beamer_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\SystemOnChip_test\\hds\\ahbBeamer_tb\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_ADMS"
value "<TBD>"
)
(vvPair
variable "task_AsmPath"
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "$ISE_HOME"
)
(vvPair
variable "task_ISEPath"
value "$ISE_WORK_DIR"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME/modeltech/bin"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "15:04:15"
)
(vvPair
variable "unit"
value "ahbBeamer_tb"
)
(vvPair
variable "user"
value "axel.amand"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2023"
)
(vvPair
variable "yy"
value "23"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 198,0
optionalChildren [
*1 (Grouping
uid 1487,0
optionalChildren [
*2 (CommentText
uid 1489,0
shape (Rectangle
uid 1490,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "119000,85000,138000,87000"
)
oxt "45000,22000,64000,24000"
text (MLText
uid 1491,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "119200,85400,134600,86600"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 18600
)
position 1
ignorePrefs 1
)
*3 (CommentText
uid 1492,0
shape (Rectangle
uid 1493,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "87000,85000,113000,87000"
)
oxt "13000,22000,39000,24000"
text (MLText
uid 1494,0
va (VaSet
fg "32768,0,0"
font "Verdana,12,1"
)
xt "93150,85300,106850,86700"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 25600
)
position 1
ignorePrefs 1
)
*4 (CommentText
uid 1495,0
shape (Rectangle
uid 1496,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "92000,91000,113000,93000"
)
oxt "18000,28000,39000,30000"
text (MLText
uid 1497,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "92200,91400,110000,92600"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*5 (CommentText
uid 1498,0
shape (Rectangle
uid 1499,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "113000,85000,119000,87000"
)
oxt "39000,22000,45000,24000"
text (MLText
uid 1500,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "113200,85400,117900,86600"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 5600
)
position 1
ignorePrefs 1
)
*6 (CommentText
uid 1501,0
shape (Rectangle
uid 1502,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "92000,87000,113000,89000"
)
oxt "18000,24000,39000,26000"
text (MLText
uid 1503,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "92200,87400,107400,88600"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*7 (CommentText
uid 1504,0
shape (Rectangle
uid 1505,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "87000,87000,92000,89000"
)
oxt "13000,24000,18000,26000"
text (MLText
uid 1506,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "87200,87400,90600,88600"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 1507,0
shape (Rectangle
uid 1508,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "87000,89000,92000,91000"
)
oxt "13000,26000,18000,28000"
text (MLText
uid 1509,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "87200,89400,90600,90600"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 1510,0
shape (Rectangle
uid 1511,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "113000,87000,138000,93000"
)
oxt "39000,24000,64000,30000"
text (MLText
uid 1512,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "113200,87200,127300,88400"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 5600
visibleWidth 24600
)
ignorePrefs 1
)
*10 (CommentText
uid 1513,0
shape (Rectangle
uid 1514,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "92000,89000,113000,91000"
)
oxt "18000,26000,39000,28000"
text (MLText
uid 1515,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "92200,89400,112500,90600"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*11 (CommentText
uid 1516,0
shape (Rectangle
uid 1517,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "87000,91000,92000,93000"
)
oxt "13000,28000,18000,30000"
text (MLText
uid 1518,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "87200,91400,91500,92600"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 1488,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 1
)
xt "87000,85000,138000,93000"
)
oxt "13000,22000,64000,30000"
)
*12 (Net
uid 12555,0
decl (Decl
n "hReset_n"
t "std_uLogic"
o 6
suid 108,0
)
declText (MLText
uid 12556,0
va (VaSet
isHidden 1
)
xt "0,0,18700,1200"
st "SIGNAL hReset_n : std_uLogic"
)
)
*13 (Net
uid 12563,0
decl (Decl
n "hClk"
t "std_uLogic"
o 3
suid 109,0
)
declText (MLText
uid 12564,0
va (VaSet
isHidden 1
)
xt "0,0,17500,1200"
st "SIGNAL hClk : std_uLogic"
)
)
*14 (Net
uid 12571,0
decl (Decl
n "hResp"
t "std_uLogic"
o 7
suid 110,0
)
declText (MLText
uid 12572,0
va (VaSet
isHidden 1
)
xt "0,0,18000,1200"
st "SIGNAL hResp : std_uLogic"
)
)
*15 (Net
uid 12579,0
decl (Decl
n "hReady"
t "std_uLogic"
o 5
suid 111,0
)
declText (MLText
uid 12580,0
va (VaSet
isHidden 1
)
xt "0,0,18300,1200"
st "SIGNAL hReady : std_uLogic"
)
)
*16 (Net
uid 12587,0
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 4
suid 112,0
)
declText (MLText
uid 12588,0
va (VaSet
isHidden 1
)
xt "0,0,37800,1200"
st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*17 (Net
uid 12595,0
decl (Decl
n "hSel"
t "std_uLogic"
o 8
suid 113,0
)
declText (MLText
uid 12596,0
va (VaSet
isHidden 1
)
xt "0,0,17400,1200"
st "SIGNAL hSel : std_uLogic"
)
)
*18 (Net
uid 12603,0
decl (Decl
n "hWrite"
t "std_uLogic"
o 11
suid 114,0
)
declText (MLText
uid 12604,0
va (VaSet
isHidden 1
)
xt "0,0,17800,1200"
st "SIGNAL hWrite : std_uLogic"
)
)
*19 (Net
uid 12611,0
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 9
suid 115,0
)
declText (MLText
uid 12612,0
va (VaSet
isHidden 1
)
xt "0,0,38100,1200"
st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)"
)
)
*20 (Net
uid 12619,0
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 10
suid 116,0
)
declText (MLText
uid 12620,0
va (VaSet
isHidden 1
)
xt "0,0,38000,1200"
st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
)
)
*21 (Net
uid 12627,0
decl (Decl
n "hAddr"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 2
suid 117,0
)
declText (MLText
uid 12628,0
va (VaSet
isHidden 1
)
xt "0,0,35300,1200"
st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )"
)
)
*22 (Blk
uid 12657,0
shape (Rectangle
uid 12658,0
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "39000,69000,129000,77000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 12659,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*23 (Text
uid 12660,0
va (VaSet
font "Verdana,12,0"
)
xt "39400,76900,53500,78300"
st "SystemOnChip_test"
blo "39400,78100"
tm "BdLibraryNameMgr"
)
*24 (Text
uid 12661,0
va (VaSet
font "Verdana,12,0"
)
xt "39400,78300,52800,79700"
st "ahbBeamer_tester"
blo "39400,79500"
tm "BlkNameMgr"
)
*25 (Text
uid 12662,0
va (VaSet
font "Verdana,12,0"
)
xt "39400,79700,45300,81100"
st "I_tester"
blo "39400,80900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 12663,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 12664,0
text (MLText
uid 12665,0
va (VaSet
font "Verdana,8,0"
)
xt "39400,82300,65200,85300"
st "patternAddressBitNb = patternAddressBitNb ( positive )
signalBitNb = signalBitNb ( positive )
clockFrequency = clockFrequency ( real ) "
)
header ""
)
elements [
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "clockFrequency"
type "real"
value "clockFrequency"
)
]
)
viewicon (ZoomableIcon
uid 12742,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "39250,75250,40750,76750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
)
*26 (Net
uid 13629,0
decl (Decl
n "selSinCos"
t "std_ulogic"
o 17
suid 120,0
)
declText (MLText
uid 13630,0
va (VaSet
isHidden 1
)
xt "0,0,18500,1200"
st "SIGNAL selSinCos : std_ulogic"
)
)
*27 (Net
uid 13637,0
decl (Decl
n "outY"
t "std_ulogic"
o 15
suid 121,0
)
declText (MLText
uid 13638,0
va (VaSet
isHidden 1
)
xt "0,0,17200,1200"
st "SIGNAL outY : std_ulogic"
)
)
*28 (Net
uid 13645,0
decl (Decl
n "outX"
t "std_ulogic"
o 14
suid 122,0
)
declText (MLText
uid 13646,0
va (VaSet
isHidden 1
)
xt "0,0,17200,1200"
st "SIGNAL outX : std_ulogic"
)
)
*29 (HdlText
uid 13840,0
optionalChildren [
*30 (EmbeddedText
uid 13845,0
commentText (CommentText
uid 13846,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 13847,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "85000,28000,101000,30000"
)
oxt "0,0,18000,5000"
text (MLText
uid 13848,0
va (VaSet
)
xt "85200,28200,100700,29400"
st "
lowpassInY <= (others => outY);
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 13841,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "85000,27000,101000,31000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 13842,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*31 (Text
uid 13843,0
va (VaSet
)
xt "85400,31000,88000,32200"
st "eb2"
blo "85400,32000"
tm "HdlTextNameMgr"
)
*32 (Text
uid 13844,0
va (VaSet
)
xt "85400,32000,86800,33200"
st "2"
blo "85400,33000"
tm "HdlTextNumberMgr"
)
]
)
)
*33 (SaComponent
uid 13849,0
optionalChildren [
*34 (CptPort
uid 13858,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13859,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "100250,44625,101000,45375"
)
tg (CPTG
uid 13860,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13861,0
va (VaSet
)
xt "102000,44400,105400,45600"
st "clock"
blo "102000,45400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
)
)
)
*35 (CptPort
uid 13862,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13863,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "117000,40625,117750,41375"
)
tg (CPTG
uid 13864,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 13865,0
va (VaSet
)
xt "108700,40400,116000,41600"
st "lowpassOut"
ju 2
blo "116000,41400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "lowpassOut"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 1
)
)
)
*36 (CptPort
uid 13866,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13867,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "100250,46625,101000,47375"
)
tg (CPTG
uid 13868,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13869,0
va (VaSet
)
xt "102000,46400,105300,47600"
st "reset"
blo "102000,47400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
)
)
)
*37 (CptPort
uid 13870,0
ps "OnEdgeStrategy"
shape (Triangle
uid 13871,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "100250,40625,101000,41375"
)
tg (CPTG
uid 13872,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 13873,0
va (VaSet
)
xt "102000,40400,107800,41600"
st "lowpassIn"
blo "102000,41400"
)
)
thePort (LogicalPort
decl (Decl
n "lowpassIn"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 4
)
)
)
]
shape (Rectangle
uid 13850,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "101000,37000,117000,49000"
)
oxt "32000,10000,48000,22000"
ttg (MlTextGroup
uid 13851,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*38 (Text
uid 13852,0
va (VaSet
font "Verdana,9,1"
)
xt "101600,48800,113100,50000"
st "WaveformGenerator"
blo "101600,49800"
tm "BdLibraryNameMgr"
)
*39 (Text
uid 13853,0
va (VaSet
font "Verdana,9,1"
)
xt "101600,50000,106200,51200"
st "lowpass"
blo "101600,51000"
tm "CptNameMgr"
)
*40 (Text
uid 13854,0
va (VaSet
font "Verdana,9,1"
)
xt "101600,51200,104900,52400"
st "I_filt"
blo "101600,52200"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 13855,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 13856,0
text (MLText
uid 13857,0
va (VaSet
font "Verdana,8,0"
)
xt "101000,52600,121800,54600"
st "signalBitNb = signalBitNb ( positive )
shiftBitNb = lowpassShiftBitNb ( positive ) "
)
header ""
)
elements [
(GiElement
name "signalBitNb"
type "positive"
value "signalBitNb"
)
(GiElement
name "shiftBitNb"
type "positive"
value "lowpassShiftBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*41 (Net
uid 13892,0
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 123,0
)
declText (MLText
uid 13893,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "2000,11400,15500,12400"
st "SIGNAL clock : std_ulogic"
)
)
*42 (Net
uid 13896,0
decl (Decl
n "reset"
t "std_ulogic"
o 16
suid 125,0
)
declText (MLText
uid 13897,0
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "2000,14600,15500,15600"
st "SIGNAL reset : std_ulogic"
)
)
*43 (Net
uid 13922,0
decl (Decl
n "lowpassInY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 12
suid 127,0
)
declText (MLText
uid 13923,0
va (VaSet
isHidden 1
)
xt "0,0,33000,1200"
st "SIGNAL lowpassInY : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*44 (Net
uid 13924,0
decl (Decl
n "lowpassOutY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 13
suid 128,0
)
declText (MLText
uid 13925,0
va (VaSet
isHidden 1
)
xt "0,0,33500,1200"
st "SIGNAL lowpassOutY : unsigned(signalBitNb-1 DOWNTO 0)"
)
)
*45 (SaComponent
uid 14527,0
optionalChildren [
*46 (CptPort
uid 14471,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14472,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,56625,69000,57375"
)
tg (CPTG
uid 14473,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14474,0
va (VaSet
)
xt "70000,56400,73000,57600"
st "hClk"
blo "70000,57400"
)
)
thePort (LogicalPort
decl (Decl
n "hClk"
t "std_ulogic"
o 13
suid 1,0
)
)
)
*47 (CptPort
uid 14475,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14476,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,38625,69000,39375"
)
tg (CPTG
uid 14477,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14478,0
va (VaSet
)
xt "70000,38400,73700,39600"
st "hAddr"
blo "70000,39400"
)
)
thePort (LogicalPort
decl (Decl
n "hAddr"
t "unsigned"
b "(ahbAddressBitNb-1 downto 0)"
o 2
suid 2,0
)
)
)
*48 (CptPort
uid 14479,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14480,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "85000,38625,85750,39375"
)
tg (CPTG
uid 14481,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14482,0
va (VaSet
)
xt "81001,38400,84001,39600"
st "outX"
ju 2
blo "84001,39400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outX"
t "std_ulogic"
o 1
suid 3,0
)
)
)
*49 (CptPort
uid 14483,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14484,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,58625,69000,59375"
)
tg (CPTG
uid 14485,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14486,0
va (VaSet
)
xt "70000,58400,75400,59600"
st "hReset_n"
blo "70000,59400"
)
)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_ulogic"
o 14
suid 4,0
)
)
)
*50 (CptPort
uid 14487,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14488,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "85000,40625,85750,41375"
)
tg (CPTG
uid 14489,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14490,0
va (VaSet
)
xt "81001,40400,84001,41600"
st "outY"
ju 2
blo "84001,41400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outY"
t "std_ulogic"
o 3
suid 5,0
)
)
)
*51 (CptPort
uid 14491,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14492,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,40625,69000,41375"
)
tg (CPTG
uid 14493,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14494,0
va (VaSet
)
xt "70000,40400,74600,41600"
st "hWData"
blo "70000,41400"
)
)
thePort (LogicalPort
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 4
suid 11,0
)
)
)
*52 (CptPort
uid 14495,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14496,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "85000,44625,85750,45375"
)
tg (CPTG
uid 14497,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14498,0
va (VaSet
)
xt "78201,44400,84001,45600"
st "selSinCos"
ju 2
blo "84001,45400"
)
)
thePort (LogicalPort
decl (Decl
n "selSinCos"
t "std_ulogic"
o 5
suid 13,0
)
)
)
*53 (CptPort
uid 14499,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14500,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "85000,56625,85750,57375"
)
tg (CPTG
uid 14501,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 14502,0
va (VaSet
)
xt "79400,56400,84000,57600"
st "testOut"
ju 2
blo "84000,57400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 6
suid 2014,0
)
)
)
*54 (CptPort
uid 14503,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14504,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,48625,69000,49375"
)
tg (CPTG
uid 14505,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14506,0
va (VaSet
)
xt "70000,48400,74400,49600"
st "hRData"
blo "70000,49400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 downto 0)"
o 7
suid 2015,0
)
)
)
*55 (CptPort
uid 14507,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14508,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,42625,69000,43375"
)
tg (CPTG
uid 14509,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14510,0
va (VaSet
)
xt "70000,42400,74200,43600"
st "hTrans"
blo "70000,43400"
)
)
thePort (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 downto 0)"
o 8
suid 2016,0
)
)
)
*56 (CptPort
uid 14511,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14512,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,44625,69000,45375"
)
tg (CPTG
uid 14513,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14514,0
va (VaSet
)
xt "70000,44400,73900,45600"
st "hWrite"
blo "70000,45400"
)
)
thePort (LogicalPort
decl (Decl
n "hWrite"
t "std_ulogic"
o 9
suid 2017,0
)
)
)
*57 (CptPort
uid 14515,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14516,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,46625,69000,47375"
)
tg (CPTG
uid 14517,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14518,0
va (VaSet
)
xt "70000,46400,72900,47600"
st "hSel"
blo "70000,47400"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_ulogic"
o 10
suid 2018,0
)
)
)
*58 (CptPort
uid 14519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14520,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,50625,69000,51375"
)
tg (CPTG
uid 14521,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14522,0
va (VaSet
)
xt "70000,50400,74400,51600"
st "hReady"
blo "70000,51400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hReady"
t "std_ulogic"
o 11
suid 2019,0
)
)
)
*59 (CptPort
uid 14523,0
ps "OnEdgeStrategy"
shape (Triangle
uid 14524,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "68250,52625,69000,53375"
)
tg (CPTG
uid 14525,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 14526,0
va (VaSet
)
xt "70000,52400,73800,53600"
st "hResp"
blo "70000,53400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "hResp"
t "std_ulogic"
o 12
suid 2020,0
)
)
)
]
shape (Rectangle
uid 14528,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "69000,35000,85000,61000"
)
oxt "43000,6000,59000,32000"
ttg (MlTextGroup
uid 14529,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*60 (Text
uid 14530,0
va (VaSet
font "Verdana,9,1"
)
xt "69600,60800,78000,62000"
st "SystemOnChip"
blo "69600,61800"
tm "BdLibraryNameMgr"
)
*61 (Text
uid 14531,0
va (VaSet
font "Verdana,9,1"
)
xt "69600,61700,75800,62900"
st "ahbBeamer"
blo "69600,62700"
tm "CptNameMgr"
)
*62 (Text
uid 14532,0
va (VaSet
font "Verdana,9,1"
)
xt "69600,62600,73300,63800"
st "I_DUT"
blo "69600,63600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 14533,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 14534,0
text (MLText
uid 14535,0
va (VaSet
font "Verdana,8,0"
)
xt "69000,64600,94800,66600"
st "patternAddressBitNb = patternAddressBitNb ( positive )
testOutBitNb = testOutBitNb ( positive ) "
)
header ""
)
elements [
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
(GiElement
name "testOutBitNb"
type "positive"
value "testOutBitNb"
)
]
)
viewicon (ZoomableIcon
uid 14536,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "69250,59250,70750,60750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*63 (Wire
uid 12557,0
shape (OrthoPolyLine
uid 12558,0
va (VaSet
vasetType 3
)
xt "67000,59000,68250,69000"
pts [
"68250,59000"
"67000,59000"
"67000,69000"
]
)
start &49
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12561,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12562,0
va (VaSet
font "Verdana,12,0"
)
xt "60250,57600,67050,59000"
st "hReset_n"
blo "60250,58800"
tm "WireNameMgr"
)
)
on &12
)
*64 (Wire
uid 12565,0
shape (OrthoPolyLine
uid 12566,0
va (VaSet
vasetType 3
)
xt "65000,57000,68250,69000"
pts [
"68250,57000"
"65000,57000"
"65000,69000"
]
)
start &46
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12569,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12570,0
va (VaSet
font "Verdana,12,0"
)
xt "63250,55600,66750,57000"
st "hClk"
blo "63250,56800"
tm "WireNameMgr"
)
)
on &13
)
*65 (Wire
uid 12573,0
shape (OrthoPolyLine
uid 12574,0
va (VaSet
vasetType 3
)
xt "61000,53000,68250,69000"
pts [
"68250,53000"
"61000,53000"
"61000,69000"
]
)
start &59
end &22
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12577,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12578,0
va (VaSet
font "Verdana,12,0"
)
xt "62250,51600,66950,53000"
st "hResp"
blo "62250,52800"
tm "WireNameMgr"
)
)
on &14
)
*66 (Wire
uid 12581,0
shape (OrthoPolyLine
uid 12582,0
va (VaSet
vasetType 3
)
xt "59000,51000,68250,69000"
pts [
"68250,51000"
"59000,51000"
"59000,69000"
]
)
start &58
end &22
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12585,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12586,0
va (VaSet
font "Verdana,12,0"
)
xt "61250,49600,66750,51000"
st "hReady"
blo "61250,50800"
tm "WireNameMgr"
)
)
on &15
)
*67 (Wire
uid 12589,0
shape (OrthoPolyLine
uid 12590,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "57000,49000,68250,69000"
pts [
"68250,49000"
"57000,49000"
"57000,69000"
]
)
start &54
end &22
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12593,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12594,0
va (VaSet
font "Verdana,12,0"
)
xt "62250,47600,67650,49000"
st "hRData"
blo "62250,48800"
tm "WireNameMgr"
)
)
on &16
)
*68 (Wire
uid 12597,0
shape (OrthoPolyLine
uid 12598,0
va (VaSet
vasetType 3
)
xt "55000,47000,68250,69000"
pts [
"68250,47000"
"55000,47000"
"55000,69000"
]
)
start &57
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12601,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12602,0
va (VaSet
font "Verdana,12,0"
)
xt "63250,45600,66750,47000"
st "hSel"
blo "63250,46800"
tm "WireNameMgr"
)
)
on &17
)
*69 (Wire
uid 12605,0
shape (OrthoPolyLine
uid 12606,0
va (VaSet
vasetType 3
)
xt "53000,45000,68250,69000"
pts [
"68250,45000"
"53000,45000"
"53000,69000"
]
)
start &56
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12609,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12610,0
va (VaSet
font "Verdana,12,0"
)
xt "62250,43600,67250,45000"
st "hWrite"
blo "62250,44800"
tm "WireNameMgr"
)
)
on &18
)
*70 (Wire
uid 12613,0
shape (OrthoPolyLine
uid 12614,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "51000,43000,68250,69000"
pts [
"68250,43000"
"51000,43000"
"51000,69000"
]
)
start &55
end &22
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12617,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12618,0
va (VaSet
font "Verdana,12,0"
)
xt "62250,41600,67350,43000"
st "hTrans"
blo "62250,42800"
tm "WireNameMgr"
)
)
on &19
)
*71 (Wire
uid 12621,0
shape (OrthoPolyLine
uid 12622,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "49000,41000,68250,69000"
pts [
"68250,41000"
"49000,41000"
"49000,69000"
]
)
start &51
end &22
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12625,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12626,0
va (VaSet
font "Verdana,12,0"
)
xt "61250,39600,67150,41000"
st "hWData"
blo "61250,40800"
tm "WireNameMgr"
)
)
on &20
)
*72 (Wire
uid 12629,0
shape (OrthoPolyLine
uid 12630,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "47000,39000,68250,69000"
pts [
"68250,39000"
"47000,39000"
"47000,69000"
]
)
start &47
end &22
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 12633,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 12634,0
va (VaSet
font "Verdana,12,0"
)
xt "62250,37600,66750,39000"
st "hAddr"
blo "62250,38800"
tm "WireNameMgr"
)
)
on &21
)
*73 (Wire
uid 13631,0
shape (OrthoPolyLine
uid 13632,0
va (VaSet
vasetType 3
)
xt "85750,45000,89000,69000"
pts [
"85750,45000"
"89000,45000"
"89000,69000"
]
)
start &52
end &22
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13635,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13636,0
va (VaSet
font "Verdana,12,0"
)
xt "87750,43600,94650,45000"
st "selSinCos"
blo "87750,44800"
tm "WireNameMgr"
)
)
on &26
)
*74 (Wire
uid 13639,0
optionalChildren [
*75 (BdJunction
uid 13904,0
ps "OnConnectorStrategy"
shape (Circle
uid 13905,0
va (VaSet
vasetType 1
)
xt "92600,40600,93400,41400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 13640,0
va (VaSet
vasetType 3
)
xt "85750,41000,93000,69000"
pts [
"85750,41000"
"93000,41000"
"93000,69000"
]
)
start &50
end &22
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13643,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13644,0
va (VaSet
font "Verdana,12,0"
)
xt "87750,39600,91350,41000"
st "outY"
blo "87750,40800"
tm "WireNameMgr"
)
)
on &27
)
*76 (Wire
uid 13647,0
shape (OrthoPolyLine
uid 13648,0
va (VaSet
vasetType 3
)
xt "85750,39000,95000,69000"
pts [
"85750,39000"
"95000,39000"
"95000,69000"
]
)
start &48
end &22
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13651,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13652,0
va (VaSet
font "Verdana,12,0"
)
xt "87750,37600,91450,39000"
st "outX"
blo "87750,38800"
tm "WireNameMgr"
)
)
on &28
)
*77 (Wire
uid 13874,0
shape (OrthoPolyLine
uid 13875,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "97000,31000,100250,41000"
pts [
"100250,41000"
"97000,41000"
"97000,31000"
]
)
start &37
end &29
sat 32
eat 2
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13878,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13879,0
va (VaSet
font "Verdana,12,0"
)
xt "94000,39600,102800,41000"
st "lowpassInY"
blo "94000,40800"
tm "WireNameMgr"
)
)
on &43
)
*78 (Wire
uid 13880,0
shape (OrthoPolyLine
uid 13881,0
va (VaSet
vasetType 3
)
xt "97000,45000,100250,69000"
pts [
"97000,69000"
"97000,45000"
"100250,45000"
]
)
start &22
end &34
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13884,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13885,0
va (VaSet
font "Verdana,12,0"
)
xt "97000,43600,100800,45000"
st "clock"
blo "97000,44800"
tm "WireNameMgr"
)
)
on &41
)
*79 (Wire
uid 13886,0
shape (OrthoPolyLine
uid 13887,0
va (VaSet
vasetType 3
)
xt "99000,47000,100250,69000"
pts [
"99000,69000"
"99000,47000"
"100250,47000"
]
)
start &22
end &36
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13890,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13891,0
va (VaSet
font "Verdana,12,0"
)
xt "97000,45600,101100,47000"
st "reset"
blo "97000,46800"
tm "WireNameMgr"
)
)
on &42
)
*80 (Wire
uid 13898,0
shape (OrthoPolyLine
uid 13899,0
va (VaSet
vasetType 3
)
xt "93000,31000,93000,41000"
pts [
"93000,41000"
"93000,31000"
]
)
start &75
end &29
sat 32
eat 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13902,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13903,0
va (VaSet
font "Verdana,12,0"
)
xt "89000,31600,92600,33000"
st "outY"
blo "89000,32800"
tm "WireNameMgr"
)
)
on &27
)
*81 (Wire
uid 13908,0
shape (OrthoPolyLine
uid 13909,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "117750,41000,121000,69000"
pts [
"117750,41000"
"121000,41000"
"121000,69000"
]
)
start &35
end &22
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 13912,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 13913,0
va (VaSet
font "Verdana,12,0"
)
xt "119750,39600,129550,41000"
st "lowpassOutY"
blo "119750,40800"
tm "WireNameMgr"
)
)
on &44
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "32768,32768,32768"
)
packageList *82 (PackageList
uid 187,0
stg "VerticalLayoutStrategy"
textVec [
*83 (Text
uid 1297,0
va (VaSet
font "Verdana,8,1"
)
xt "29000,19000,35900,20000"
st "Package List"
blo "29000,19800"
)
*84 (MLText
uid 1298,0
va (VaSet
)
xt "29000,20000,46500,26000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 190,0
stg "VerticalLayoutStrategy"
textVec [
*85 (Text
uid 191,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,0,32500,1200"
st "Compiler Directives"
blo "20000,1000"
)
*86 (Text
uid 192,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,1400,35100,2600"
st "Pre-module directives:"
blo "20000,2400"
)
*87 (MLText
uid 193,0
va (VaSet
isHidden 1
)
xt "20000,2800,32100,5200"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*88 (Text
uid 194,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,5600,35700,6800"
st "Post-module directives:"
blo "20000,6600"
)
*89 (MLText
uid 195,0
va (VaSet
isHidden 1
)
xt "20000,7000,20000,7000"
tm "BdCompilerDirectivesTextMgr"
)
*90 (Text
uid 196,0
va (VaSet
isHidden 1
font "Verdana,10,1"
)
xt "20000,7200,35200,8400"
st "End-module directives:"
blo "20000,8200"
)
*91 (MLText
uid 197,0
va (VaSet
isHidden 1
)
xt "20000,1200,20000,1200"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "-8,-8,1928,1048"
viewArea "27404,17388,169965,94845"
cachedDiagramExtent "0,0,138000,93000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
xMargin 48
yMargin 48
paperWidth 761
paperHeight 1077
unixPaperWidth 595
unixPaperHeight 842
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "A4"
unixPaperName "A4 (210mm x 297mm)"
windowsPaperName "A4"
windowsPaperType 9
scale 67
titlesVisible 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "29000,19000"
lastUid 14713,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,3200,1400"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "Verdana,8,0"
)
xt "450,2150,1450,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Verdana,8,1"
)
xt "300,1000,4000,2000"
st "Panel0"
blo "300,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*92 (Text
va (VaSet
font "Verdana,12,0"
)
xt "1500,2550,8000,3950"
st "<library>"
blo "1500,3750"
tm "BdLibraryNameMgr"
)
*93 (Text
va (VaSet
font "Verdana,12,0"
)
xt "1500,3950,7300,5350"
st "<block>"
blo "1500,5150"
tm "BlkNameMgr"
)
*94 (Text
va (VaSet
font "Verdana,12,0"
)
xt "1500,5350,4800,6750"
st "U_0"
blo "1500,6550"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "1500,12550,1500,12550"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "250,8250,1750,9750"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-600,0,8600,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*95 (Text
va (VaSet
)
xt "-100,3000,4300,4200"
st "Library"
blo "-100,4000"
)
*96 (Text
va (VaSet
)
xt "-100,4200,9800,5400"
st "MWComponent"
blo "-100,5200"
)
*97 (Text
va (VaSet
)
xt "-100,5400,2700,6600"
st "U_0"
blo "-100,6400"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-7100,1000,-7100,1000"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-850,0,8850,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*98 (Text
va (VaSet
)
xt "-350,2550,4050,3750"
st "Library"
blo "-350,3550"
tm "BdLibraryNameMgr"
)
*99 (Text
va (VaSet
)
xt "-350,3750,8950,4950"
st "SaComponent"
blo "-350,4750"
tm "CptNameMgr"
)
*100 (Text
va (VaSet
)
xt "-350,4950,2450,6150"
st "U_0"
blo "-350,5950"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-7350,550,-7350,550"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-600,8250,900,9750"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-1350,0,9350,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*101 (Text
va (VaSet
)
xt "-850,2550,3550,3750"
st "Library"
blo "-850,3550"
)
*102 (Text
va (VaSet
)
xt "-850,3750,9450,4950"
st "VhdlComponent"
blo "-850,4750"
)
*103 (Text
va (VaSet
)
xt "-850,4950,1950,6150"
st "U_0"
blo "-850,5950"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-7850,550,-7850,550"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-2100,0,10100,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*104 (Text
va (VaSet
)
xt "-1600,2550,2800,3750"
st "Library"
blo "-1600,3550"
)
*105 (Text
va (VaSet
)
xt "-1600,3750,10100,4950"
st "VerilogComponent"
blo "-1600,4750"
)
*106 (Text
va (VaSet
)
xt "-1600,4950,1200,6150"
st "U_0"
blo "-1600,5950"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "Verdana,8,0"
)
xt "-8600,550,-8600,550"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*107 (Text
va (VaSet
font "Verdana,8,1"
)
xt "2950,3400,5250,4400"
st "eb1"
blo "2950,4200"
tm "HdlTextNameMgr"
)
*108 (Text
va (VaSet
font "Verdana,8,1"
)
xt "2950,4400,4150,5400"
st "1"
blo "2950,5200"
tm "HdlTextNumberMgr"
)
]
)
viewicon (ZoomableIcon
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "250,8250,1750,9750"
iconName "UnknownFile.png"
iconMaskName "UnknownFile.msk"
)
viewiconposition 0
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,3200,1400"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-750,-600,750,600"
st "G"
blo "-750,400"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
stc 0
sf 1
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,3400,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Verdana,12,0"
)
xt "0,0,4700,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,400,3700,1400"
st "bundle0"
blo "0,1200"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1400,1500,2600"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,5000,1200"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1200,9600,2400"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,18500,-200"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "150,400,950,1400"
st "1"
blo "150,1200"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*109 (Text
va (VaSet
font "Verdana,8,1"
)
xt "11800,20000,21800,21000"
st "Frame Declarations"
blo "11800,20800"
)
*110 (MLText
va (VaSet
)
xt "11800,21000,11800,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,11000,-200"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "150,400,950,1400"
st "1"
blo "150,1200"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*111 (Text
va (VaSet
font "Verdana,8,1"
)
xt "11800,20000,21800,21000"
st "Frame Declarations"
blo "11800,20800"
)
*112 (MLText
va (VaSet
)
xt "11800,21000,11800,21000"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,2800,1950"
st "Port"
blo "0,1750"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
isHidden 1
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Verdana,8,1"
)
xt "29000,26800,36000,27800"
st "Declarations"
blo "29000,27600"
)
portLabel (Text
uid 3,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "29000,28000,32400,29000"
st "Ports:"
blo "29000,28800"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Verdana,8,1"
)
xt "29000,27800,33800,28800"
st "Pre User:"
blo "29000,28600"
)
preUserText (MLText
uid 5,0
va (VaSet
)
xt "31000,28800,56600,37200"
st "constant patternAddressBitNb: positive := 9;
constant testOutBitNb: positive := 16;
constant signalBitNb: positive := 16;
constant lowpassShiftBitNb: positive := 8;
constant clockFrequency : real := 60.0E6;
--constant clockFrequency : real := 66.0E6;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "29000,28000,38000,29000"
st "Diagram Signals:"
blo "29000,28800"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Verdana,8,1"
)
xt "29000,28000,35000,29000"
st "Post User:"
blo "29000,28800"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
)
xt "31000,42400,31000,42400"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 129,0
usingSuid 1
emptyRow *113 (LEmptyRow
)
uid 3310,0
optionalChildren [
*114 (RefLabelRowHdr
)
*115 (TitleRowHdr
)
*116 (FilterRowHdr
)
*117 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*118 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*119 (GroupColHdr
tm "GroupColHdrMgr"
)
*120 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*121 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*122 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*123 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*124 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*125 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*126 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hReset_n"
t "std_uLogic"
o 6
suid 108,0
)
)
uid 12637,0
)
*127 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hClk"
t "std_uLogic"
o 3
suid 109,0
)
)
uid 12639,0
)
*128 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hResp"
t "std_uLogic"
o 7
suid 110,0
)
)
uid 12641,0
)
*129 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hReady"
t "std_uLogic"
o 5
suid 111,0
)
)
uid 12643,0
)
*130 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 4
suid 112,0
)
)
uid 12645,0
)
*131 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hSel"
t "std_uLogic"
o 8
suid 113,0
)
)
uid 12647,0
)
*132 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hWrite"
t "std_uLogic"
o 11
suid 114,0
)
)
uid 12649,0
)
*133 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 9
suid 115,0
)
)
uid 12651,0
)
*134 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 10
suid 116,0
)
)
uid 12653,0
)
*135 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "hAddr"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 2
suid 117,0
)
)
uid 12655,0
)
*136 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "selSinCos"
t "std_ulogic"
o 17
suid 120,0
)
)
uid 13653,0
)
*137 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "outY"
t "std_ulogic"
o 15
suid 121,0
)
)
uid 13655,0
)
*138 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "outX"
t "std_ulogic"
o 14
suid 122,0
)
)
uid 13657,0
)
*139 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 123,0
)
)
uid 13914,0
)
*140 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 16
suid 125,0
)
)
uid 13918,0
)
*141 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "lowpassInY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 12
suid 127,0
)
)
uid 13926,0
)
*142 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "lowpassOutY"
t "unsigned"
b "(signalBitNb-1 DOWNTO 0)"
o 13
suid 128,0
)
)
uid 13928,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 3323,0
optionalChildren [
*143 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *144 (MRCItem
litem &113
pos 17
dimension 20
)
uid 3325,0
optionalChildren [
*145 (MRCItem
litem &114
pos 0
dimension 20
uid 3326,0
)
*146 (MRCItem
litem &115
pos 1
dimension 23
uid 3327,0
)
*147 (MRCItem
litem &116
pos 2
hidden 1
dimension 20
uid 3328,0
)
*148 (MRCItem
litem &126
pos 0
dimension 20
uid 12638,0
)
*149 (MRCItem
litem &127
pos 1
dimension 20
uid 12640,0
)
*150 (MRCItem
litem &128
pos 2
dimension 20
uid 12642,0
)
*151 (MRCItem
litem &129
pos 3
dimension 20
uid 12644,0
)
*152 (MRCItem
litem &130
pos 4
dimension 20
uid 12646,0
)
*153 (MRCItem
litem &131
pos 5
dimension 20
uid 12648,0
)
*154 (MRCItem
litem &132
pos 6
dimension 20
uid 12650,0
)
*155 (MRCItem
litem &133
pos 7
dimension 20
uid 12652,0
)
*156 (MRCItem
litem &134
pos 8
dimension 20
uid 12654,0
)
*157 (MRCItem
litem &135
pos 9
dimension 20
uid 12656,0
)
*158 (MRCItem
litem &136
pos 10
dimension 20
uid 13654,0
)
*159 (MRCItem
litem &137
pos 11
dimension 20
uid 13656,0
)
*160 (MRCItem
litem &138
pos 12
dimension 20
uid 13658,0
)
*161 (MRCItem
litem &139
pos 13
dimension 20
uid 13915,0
)
*162 (MRCItem
litem &140
pos 14
dimension 20
uid 13919,0
)
*163 (MRCItem
litem &141
pos 15
dimension 20
uid 13927,0
)
*164 (MRCItem
litem &142
pos 16
dimension 20
uid 13929,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 3329,0
optionalChildren [
*165 (MRCItem
litem &117
pos 0
dimension 20
uid 3330,0
)
*166 (MRCItem
litem &119
pos 1
dimension 50
uid 3331,0
)
*167 (MRCItem
litem &120
pos 2
dimension 100
uid 3332,0
)
*168 (MRCItem
litem &121
pos 3
dimension 50
uid 3333,0
)
*169 (MRCItem
litem &122
pos 4
dimension 100
uid 3334,0
)
*170 (MRCItem
litem &123
pos 5
dimension 100
uid 3335,0
)
*171 (MRCItem
litem &124
pos 6
dimension 50
uid 3336,0
)
*172 (MRCItem
litem &125
pos 7
dimension 80
uid 3337,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 3324,0
vaOverrides [
]
)
]
)
uid 3309,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *173 (LEmptyRow
)
uid 3339,0
optionalChildren [
*174 (RefLabelRowHdr
)
*175 (TitleRowHdr
)
*176 (FilterRowHdr
)
*177 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*178 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*179 (GroupColHdr
tm "GroupColHdrMgr"
)
*180 (NameColHdr
tm "GenericNameColHdrMgr"
)
*181 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*182 (InitColHdr
tm "GenericValueColHdrMgr"
)
*183 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*184 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 3351,0
optionalChildren [
*185 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *186 (MRCItem
litem &173
pos 0
dimension 20
)
uid 3353,0
optionalChildren [
*187 (MRCItem
litem &174
pos 0
dimension 20
uid 3354,0
)
*188 (MRCItem
litem &175
pos 1
dimension 23
uid 3355,0
)
*189 (MRCItem
litem &176
pos 2
hidden 1
dimension 20
uid 3356,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 3357,0
optionalChildren [
*190 (MRCItem
litem &177
pos 0
dimension 20
uid 3358,0
)
*191 (MRCItem
litem &179
pos 1
dimension 50
uid 3359,0
)
*192 (MRCItem
litem &180
pos 2
dimension 100
uid 3360,0
)
*193 (MRCItem
litem &181
pos 3
dimension 100
uid 3361,0
)
*194 (MRCItem
litem &182
pos 4
dimension 50
uid 3362,0
)
*195 (MRCItem
litem &183
pos 5
dimension 50
uid 3363,0
)
*196 (MRCItem
litem &184
pos 6
dimension 80
uid 3364,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 3352,0
vaOverrides [
]
)
]
)
uid 3338,0
type 1
)
activeModelName "BlockDiag"
)